kernel update to 3.18.123 4.9.129c4.14.72

2018-09-26 23:12:39 +08:00 · 2018-09-26 23:12:39 +08:00 · 30412d10ae
commit 30412d10ae
parent d94396a4ea
51 changed files with 25813 additions and 13478 deletions
--- a/include/kernel-version.mk
+++ b/include/kernel-version.mk
@ -2,13 +2,13 @@

 LINUX_RELEASE?=1

-LINUX_VERSION-3.18 = .122
-LINUX_VERSION-4.9 = .128
-LINUX_VERSION-4.14 = .71
+LINUX_VERSION-3.18 = .123
+LINUX_VERSION-4.9 = .129
+LINUX_VERSION-4.14 = .72

-LINUX_KERNEL_HASH-3.18.122 = 675b1ce36af23caa500cb1d4f0ec2976791fb0a97ebb6486a5e2ebcb5527ade5
-LINUX_KERNEL_HASH-4.9.128 = bdb76f48491a6aadc89c0f0f7fdc240d77cee54da5aac59da0b5d98e226b6f12
-LINUX_KERNEL_HASH-4.14.71 = 76a4473dbcbd922c23a16130414829a36eb7e2f4e5859bd1b742fffdff907489
+LINUX_KERNEL_HASH-3.18.123 = c10de32c9b31fb619b016a00d77afc394db5a4542e258e927f06a5ead86f8c64
+LINUX_KERNEL_HASH-4.9.129 = 6f5510d3fcfec1bf1e2d9c8e2fdcd7628c1886c6bdb29092adc5ccdf75e39318
+LINUX_KERNEL_HASH-4.14.72 = df925906250bbc40fcf0137d7ad0fb8edc528d926832634f1233b7540564557f

 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
 sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))
--- a/target/linux/adm5120/patches-3.18/100-rootfs_split.patch
+++ b/target/linux/adm5120/patches-3.18/100-rootfs_split.patch
@ -246,7 +246,7 @@
 
 --- a/drivers/mtd/mtdchar.c
 +++ b/drivers/mtd/mtdchar.c
-@@ -1008,6 +1008,12 @@ static int mtdchar_ioctl(struct file *fi
+@@ -1012,6 +1012,12 @@ static int mtdchar_ioctl(struct file *fi
 		break;
 	}
 
--- a/target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch
+++ b/target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch
@ -24,7 +24,7 @@ produce a noisy warning.
 
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
-@@ -357,10 +357,14 @@ static int xhci_try_enable_msi(struct us
+@@ -372,10 +372,14 @@ static int xhci_try_enable_msi(struct us
 		free_irq(hcd->irq, hcd);
 	hcd->irq = 0;
 
--- a/target/linux/ar71xx/patches-4.14/203-MIPS-ath79-fix-restart.patch
+++ b/target/linux/ar71xx/patches-4.14/203-MIPS-ath79-fix-restart.patch
@ -1,20 +0,0 @@
--- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
- 
- static void ath79_restart(char *command)
- {
-+	local_irq_disable();
- 	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
- 	for (;;)
- 		if (cpu_wait)
--- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -135,6 +135,7 @@ static inline u32 ath79_pll_rr(unsigned
- static inline void ath79_reset_wr(unsigned reg, u32 val)
- {
- 	__raw_writel(val, ath79_reset_base + reg);
-+	(void) __raw_readl(ath79_reset_base + reg); /* flush */
- }
- 
- static inline u32 ath79_reset_rr(unsigned reg)
--- a/target/linux/ar71xx/patches-4.9/203-MIPS-ath79-fix-restart.patch
+++ b/target/linux/ar71xx/patches-4.9/203-MIPS-ath79-fix-restart.patch
@ -1,20 +0,0 @@
--- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
- 
- static void ath79_restart(char *command)
- {
-+	local_irq_disable();
- 	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
- 	for (;;)
- 		if (cpu_wait)
--- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -135,6 +135,7 @@ static inline u32 ath79_pll_rr(unsigned
- static inline void ath79_reset_wr(unsigned reg, u32 val)
- {
- 	__raw_writel(val, ath79_reset_base + reg);
-+	(void) __raw_readl(ath79_reset_base + reg); /* flush */
- }
- 
- static inline u32 ath79_reset_rr(unsigned reg)
--- a/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch
+++ b/target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch
@ -280,7 +280,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
-@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
+@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
 	u32 major;
 	u32 minor;
 	u32 rev = 0;
@ -288,7 +288,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
 	major = id & REV_ID_MAJOR_MASK;
-@@ -151,6 +152,17 @@ static void __init ath79_detect_sys_type
+@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
 		rev = id & AR934X_REV_ID_REVISION_MASK;
 		break;
 
@ -306,7 +306,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
 	case REV_ID_MAJOR_QCA9556:
 		ath79_soc = ATH79_SOC_QCA9556;
 		chip = "9556";
-@@ -163,14 +175,30 @@ static void __init ath79_detect_sys_type
+@@ -164,14 +176,30 @@ static void __init ath79_detect_sys_type
 		rev = id & QCA955X_REV_ID_REVISION_MASK;
 		break;
 
--- a/target/linux/ath79/patches-4.14/0013-MIPS-ath79-fix-system-restart.patch
+++ b/target/linux/ath79/patches-4.14/0013-MIPS-ath79-fix-system-restart.patch
@ -1,35 +0,0 @@
-From 59c7470bc5c4b29ed77d46fc4982f1d85b5cbec1 Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <nbd@nbd.name>
-Date: Mon, 5 Mar 2018 11:33:54 +0100
-Subject: [PATCH 13/33] MIPS: ath79: fix system restart
-
-This patch disables irq on reboot to fix hang issues that were observed
-due to pending interrupts.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
-Signed-off-by: John Crispin <john@phrozen.org>
---
- arch/mips/ath79/setup.c                  | 1 +
- arch/mips/include/asm/mach-ath79/ath79.h | 1 +
- 2 files changed, 2 insertions(+)
-
--- a/arch/mips/ath79/setup.c
-+++ b/arch/mips/ath79/setup.c
-@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP
- 
- static void ath79_restart(char *command)
- {
-+	local_irq_disable();
- 	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
- 	for (;;)
- 		if (cpu_wait)
--- a/arch/mips/include/asm/mach-ath79/ath79.h
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -167,6 +167,7 @@ static inline u32 ath79_pll_rr(unsigned
- static inline void ath79_reset_wr(unsigned reg, u32 val)
- {
- 	__raw_writel(val, ath79_reset_base + reg);
-+	(void) __raw_readl(ath79_reset_base + reg); /* flush */
- }
- 
- static inline u32 ath79_reset_rr(unsigned reg)
--- a/target/linux/bcm53xx/patches-4.14/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
+++ b/target/linux/bcm53xx/patches-4.14/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
@ -40,7 +40,7 @@ it on BCM4708 family.
 /* called during probe() after chip reset completes */
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
-@@ -153,6 +153,49 @@ int xhci_start(struct xhci_hcd *xhci)
+@@ -168,6 +168,49 @@ int xhci_start(struct xhci_hcd *xhci)
 	return ret;
 }
 
@ -90,7 +90,7 @@ it on BCM4708 family.
 /*
  * Reset a halted HC.
  *
-@@ -536,10 +579,20 @@ static int xhci_init(struct usb_hcd *hcd
+@@ -551,10 +594,20 @@ static int xhci_init(struct usb_hcd *hcd
 
 static int xhci_run_finished(struct xhci_hcd *xhci)
 {
@ -114,7 +114,7 @@ it on BCM4708 family.
 	xhci->shared_hcd->state = HC_STATE_RUNNING;
 	xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 
-@@ -549,6 +602,10 @@ static int xhci_run_finished(struct xhci
+@@ -564,6 +617,10 @@ static int xhci_run_finished(struct xhci
 	xhci_dbg_trace(xhci, trace_xhci_dbg_init,
 			"Finished xhci_run for USB3 roothub");
 	return 0;
--- a/target/linux/brcm2708/patches-4.9/950-0031-Add-dwc_otg-driver.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0031-Add-dwc_otg-driver.patch
@ -707,7 +707,7 @@ Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 		msleep(100);	/* Cool down */
 --- a/drivers/usb/core/message.c
 +++ b/drivers/usb/core/message.c
-@@ -1912,6 +1912,85 @@ free_interfaces:
+@@ -1923,6 +1923,85 @@ free_interfaces:
 	if (cp->string == NULL &&
 			!(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
 		cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
--- a/target/linux/generic/backport-4.14/700-1-6-e1000e-Remove-Other-from-EIAC.diff
+++ b/target/linux/generic/backport-4.14/700-1-6-e1000e-Remove-Other-from-EIAC.diff
@ -1,66 +0,0 @@
-From patchwork Mon Mar  5 21:40:25 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [net,v2,1/6] e1000e: Remove Other from EIAC
-X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
-X-Patchwork-Id: 881773
-X-Patchwork-Delegate: davem@davemloft.net
-Message-Id: <20180305214030.25141-2-jeffrey.t.kirsher@intel.com>
-To: davem@davemloft.net
-Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
- nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
- Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-Date: Mon,  5 Mar 2018 13:40:25 -0800
-From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-List-Id: <netdev.vger.kernel.org>
-
-From: Benjamin Poirier <bpoirier@suse.com>
-
-It was reported that emulated e1000e devices in vmware esxi 6.5 Build
-7526125 do not link up after commit 4aea7a5c5e94 ("e1000e: Avoid receiver
-overrun interrupt bursts", v4.15-rc1). Some tracing shows that after
-e1000e_trigger_lsc() is called, ICR reads out as 0x0 in e1000_msix_other()
-on emulated e1000e devices. In comparison, on real e1000e 82574 hardware,
-icr=0x80000004 (_INT_ASSERTED | _LSC) in the same situation.
-
-Some experimentation showed that this flaw in vmware e1000e emulation can
-be worked around by not setting Other in EIAC. This is how it was before
-16ecba59bc33 ("e1000e: Do not read ICR in Other interrupt", v4.5-rc1).
-
-Fixes: 4aea7a5c5e94 ("e1000e: Avoid receiver overrun interrupt bursts")
-Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
-Tested-by: Aaron Brown <aaron.f.brown@intel.com>
-Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
- drivers/net/ethernet/intel/e1000e/netdev.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
-+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
-@@ -1914,6 +1914,8 @@ static irqreturn_t e1000_msix_other(int
- 	bool enable = true;
- 
- 	icr = er32(ICR);
-+	ew32(ICR, E1000_ICR_OTHER);
-+
- 	if (icr & E1000_ICR_RXO) {
- 		ew32(ICR, E1000_ICR_RXO);
- 		enable = false;
-@@ -2036,7 +2038,6 @@ static void e1000_configure_msix(struct
- 		       hw->hw_addr + E1000_EITR_82574(vector));
- 	else
- 		writel(1, hw->hw_addr + E1000_EITR_82574(vector));
-	adapter->eiac_mask |= E1000_IMS_OTHER;
- 
- 	/* Cause Tx interrupts on every write back */
- 	ivar |= BIT(31);
-@@ -2261,7 +2262,7 @@ static void e1000_irq_enable(struct e100
- 
- 	if (adapter->msix_entries) {
- 		ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
-		ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC);
-+		ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
- 	} else if (hw->mac.type >= e1000_pch_lpt) {
- 		ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
- 	} else {
--- a/target/linux/generic/backport-4.14/700-2-6-Partial-revert-e1000e-Avoid-receiver-overrun-interrupt-bursts.diff
+++ b/target/linux/generic/backport-4.14/700-2-6-Partial-revert-e1000e-Avoid-receiver-overrun-interrupt-bursts.diff
@ -1,84 +0,0 @@
-From patchwork Mon Mar  5 21:40:26 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [net, v2,
- 2/6] Partial revert "e1000e: Avoid receiver overrun interrupt bursts"
-X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
-X-Patchwork-Id: 881769
-X-Patchwork-Delegate: davem@davemloft.net
-Message-Id: <20180305214030.25141-3-jeffrey.t.kirsher@intel.com>
-To: davem@davemloft.net
-Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
- nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
- Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-Date: Mon,  5 Mar 2018 13:40:26 -0800
-From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-List-Id: <netdev.vger.kernel.org>
-
-From: Benjamin Poirier <bpoirier@suse.com>
-
-This partially reverts commit 4aea7a5c5e940c1723add439f4088844cd26196d.
-
-We keep the fix for the first part of the problem (1) described in the log
-of that commit, that is to read ICR in the other interrupt handler. We
-remove the fix for the second part of the problem (2), Other interrupt
-throttling.
-
-Bursts of "Other" interrupts may once again occur during rxo (receive
-overflow) traffic conditions. This is deemed acceptable in the interest of
-avoiding unforeseen fallout from changes that are not strictly necessary.
-As discussed, the e1000e driver should be in "maintenance mode".
-
-Link: https://www.spinics.net/lists/netdev/msg480675.html
-Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
-Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
-Tested-by: Aaron Brown <aaron.f.brown@intel.com>
-Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
- drivers/net/ethernet/intel/e1000e/netdev.c | 16 ++--------------
- 1 file changed, 2 insertions(+), 14 deletions(-)
-
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
-+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
-@@ -1911,21 +1911,10 @@ static irqreturn_t e1000_msix_other(int
- 	struct e1000_adapter *adapter = netdev_priv(netdev);
- 	struct e1000_hw *hw = &adapter->hw;
- 	u32 icr;
-	bool enable = true;
- 
- 	icr = er32(ICR);
- 	ew32(ICR, E1000_ICR_OTHER);
- 
-	if (icr & E1000_ICR_RXO) {
-		ew32(ICR, E1000_ICR_RXO);
-		enable = false;
-		/* napi poll will re-enable Other, make sure it runs */
-		if (napi_schedule_prep(&adapter->napi)) {
-			adapter->total_rx_bytes = 0;
-			adapter->total_rx_packets = 0;
-			__napi_schedule(&adapter->napi);
-		}
-	}
- 	if (icr & E1000_ICR_LSC) {
- 		ew32(ICR, E1000_ICR_LSC);
- 		hw->mac.get_link_status = true;
-@@ -1934,7 +1923,7 @@ static irqreturn_t e1000_msix_other(int
- 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
- 	}
- 
-	if (enable && !test_bit(__E1000_DOWN, &adapter->state))
-+	if (!test_bit(__E1000_DOWN, &adapter->state))
- 		ew32(IMS, E1000_IMS_OTHER);
- 
- 	return IRQ_HANDLED;
-@@ -2704,8 +2693,7 @@ static int e1000e_poll(struct napi_struc
- 		napi_complete_done(napi, work_done);
- 		if (!test_bit(__E1000_DOWN, &adapter->state)) {
- 			if (adapter->msix_entries)
-				ew32(IMS, adapter->rx_ring->ims_val |
-				     E1000_IMS_OTHER);
-+				ew32(IMS, adapter->rx_ring->ims_val);
- 			else
- 				e1000_irq_enable(adapter);
- 		}
--- a/target/linux/generic/backport-4.14/700-3-6-e1000e-Fix-queue-interrupt-re-raising-in-Other-interrupt.diff
+++ b/target/linux/generic/backport-4.14/700-3-6-e1000e-Fix-queue-interrupt-re-raising-in-Other-interrupt.diff
@ -1,50 +0,0 @@
-From patchwork Mon Mar  5 21:40:27 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [net, v2,
- 3/6] e1000e: Fix queue interrupt re-raising in Other interrupt
-X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
-X-Patchwork-Id: 881775
-X-Patchwork-Delegate: davem@davemloft.net
-Message-Id: <20180305214030.25141-4-jeffrey.t.kirsher@intel.com>
-To: davem@davemloft.net
-Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
- nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
- Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-Date: Mon,  5 Mar 2018 13:40:27 -0800
-From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-List-Id: <netdev.vger.kernel.org>
-
-From: Benjamin Poirier <bpoirier@suse.com>
-
-Restores the ICS write for Rx/Tx queue interrupts which was present before
-commit 16ecba59bc33 ("e1000e: Do not read ICR in Other interrupt", v4.5-rc1)
-but was not restored in commit 4aea7a5c5e94
-("e1000e: Avoid receiver overrun interrupt bursts", v4.15-rc1).
-
-This re-raises the queue interrupts in case the txq or rxq bits were set in
-ICR and the Other interrupt handler read and cleared ICR before the queue
-interrupt was raised.
-
-Fixes: 4aea7a5c5e94 ("e1000e: Avoid receiver overrun interrupt bursts")
-Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
-Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
-Tested-by: Aaron Brown <aaron.f.brown@intel.com>
-Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
- drivers/net/ethernet/intel/e1000e/netdev.c | 3 +++
- 1 file changed, 3 insertions(+)
-
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
-+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
-@@ -1915,6 +1915,9 @@ static irqreturn_t e1000_msix_other(int
- 	icr = er32(ICR);
- 	ew32(ICR, E1000_ICR_OTHER);
- 
-+	if (icr & adapter->eiac_mask)
-+		ew32(ICS, (icr & adapter->eiac_mask));
-+
- 	if (icr & E1000_ICR_LSC) {
- 		ew32(ICR, E1000_ICR_LSC);
- 		hw->mac.get_link_status = true;
--- a/target/linux/generic/backport-4.14/700-4-6-e1000e-Avoid-missed-interrupts-following-ICR-read.diff
+++ b/target/linux/generic/backport-4.14/700-4-6-e1000e-Avoid-missed-interrupts-following-ICR-read.diff
@ -1,131 +0,0 @@
-From patchwork Mon Mar  5 21:40:28 2018
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [net,v2,4/6] e1000e: Avoid missed interrupts following ICR read
-X-Patchwork-Submitter: "Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>
-X-Patchwork-Id: 881771
-X-Patchwork-Delegate: davem@davemloft.net
-Message-Id: <20180305214030.25141-5-jeffrey.t.kirsher@intel.com>
-To: davem@davemloft.net
-Cc: Benjamin Poirier <bpoirier@suse.com>, netdev@vger.kernel.org,
- nhorman@redhat.com, sassmann@redhat.com, jogreene@redhat.com,
- Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-Date: Mon,  5 Mar 2018 13:40:28 -0800
-From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-List-Id: <netdev.vger.kernel.org>
-
-From: Benjamin Poirier <bpoirier@suse.com>
-
-The 82574 specification update errata 12 states that interrupts may be
-missed if ICR is read while INT_ASSERTED is not set. Avoid that problem by
-setting all bits related to events that can trigger the Other interrupt in
-IMS.
-
-The Other interrupt is raised for such events regardless of whether or not
-they are set in IMS. However, only when they are set is the INT_ASSERTED
-bit also set in ICR.
-
-By doing this, we ensure that INT_ASSERTED is always set when we read ICR
-in e1000_msix_other() and steer clear of the errata. This also ensures that
-ICR will automatically be cleared on read, therefore we no longer need to
-clear bits explicitly.
-
-Signed-off-by: Benjamin Poirier <bpoirier@suse.com>
-Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
-Tested-by: Aaron Brown <aaron.f.brown@intel.com>
-Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
- drivers/net/ethernet/intel/e1000e/defines.h | 21 ++++++++++++++++++++-
- drivers/net/ethernet/intel/e1000e/netdev.c  | 11 ++++-------
- 2 files changed, 24 insertions(+), 8 deletions(-)
-
--- a/drivers/net/ethernet/intel/e1000e/defines.h
-+++ b/drivers/net/ethernet/intel/e1000e/defines.h
-@@ -400,6 +400,10 @@
- #define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
- #define E1000_ICR_RXO           0x00000040 /* Receiver Overrun */
- #define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
-+#define E1000_ICR_MDAC          0x00000200 /* MDIO Access Complete */
-+#define E1000_ICR_SRPD          0x00010000 /* Small Receive Packet Detected */
-+#define E1000_ICR_ACK           0x00020000 /* Receive ACK Frame Detected */
-+#define E1000_ICR_MNG           0x00040000 /* Manageability Event Detected */
- #define E1000_ICR_ECCER         0x00400000 /* Uncorrectable ECC Error */
- /* If this bit asserted, the driver should claim the interrupt */
- #define E1000_ICR_INT_ASSERTED	0x80000000
-@@ -407,7 +411,7 @@
- #define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
- #define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
- #define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
-#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
-+#define E1000_ICR_OTHER         0x01000000 /* Other Interrupt */
- 
- /* PBA ECC Register */
- #define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
-@@ -431,12 +435,27 @@
- 	E1000_IMS_RXSEQ  |    \
- 	E1000_IMS_LSC)
- 
-+/* These are all of the events related to the OTHER interrupt.
-+ */
-+#define IMS_OTHER_MASK ( \
-+	E1000_IMS_LSC  | \
-+	E1000_IMS_RXO  | \
-+	E1000_IMS_MDAC | \
-+	E1000_IMS_SRPD | \
-+	E1000_IMS_ACK  | \
-+	E1000_IMS_MNG)
-+
- /* Interrupt Mask Set */
- #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
- #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
- #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
- #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
-+#define E1000_IMS_RXO       E1000_ICR_RXO       /* Receiver Overrun */
- #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
-+#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO Access Complete */
-+#define E1000_IMS_SRPD      E1000_ICR_SRPD      /* Small Receive Packet */
-+#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive ACK Frame Detected */
-+#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability Event */
- #define E1000_IMS_ECCER     E1000_ICR_ECCER     /* Uncorrectable ECC Error */
- #define E1000_IMS_RXQ0      E1000_ICR_RXQ0      /* Rx Queue 0 Interrupt */
- #define E1000_IMS_RXQ1      E1000_ICR_RXQ1      /* Rx Queue 1 Interrupt */
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
-+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
-@@ -1910,16 +1910,12 @@ static irqreturn_t e1000_msix_other(int
- 	struct net_device *netdev = data;
- 	struct e1000_adapter *adapter = netdev_priv(netdev);
- 	struct e1000_hw *hw = &adapter->hw;
-	u32 icr;
-
-	icr = er32(ICR);
-	ew32(ICR, E1000_ICR_OTHER);
-+	u32 icr = er32(ICR);
- 
- 	if (icr & adapter->eiac_mask)
- 		ew32(ICS, (icr & adapter->eiac_mask));
- 
- 	if (icr & E1000_ICR_LSC) {
-		ew32(ICR, E1000_ICR_LSC);
- 		hw->mac.get_link_status = true;
- 		/* guard against interrupt when we're going down */
- 		if (!test_bit(__E1000_DOWN, &adapter->state))
-@@ -1927,7 +1923,7 @@ static irqreturn_t e1000_msix_other(int
- 	}
- 
- 	if (!test_bit(__E1000_DOWN, &adapter->state))
-		ew32(IMS, E1000_IMS_OTHER);
-+		ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
- 
- 	return IRQ_HANDLED;
- }
-@@ -2254,7 +2250,8 @@ static void e1000_irq_enable(struct e100
- 
- 	if (adapter->msix_entries) {
- 		ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
-		ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
-+		ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
-+		     IMS_OTHER_MASK);
- 	} else if (hw->mac.type >= e1000_pch_lpt) {
- 		ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
- 	} else {
--- a/target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch
+++ b/target/linux/generic/backport-4.9/090-net-generalize-napi_complete_done.patch
@ -1379,7 +1379,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 		 */
 --- a/drivers/net/xen-netfront.c
 +++ b/drivers/net/xen-netfront.c
-@@ -1065,7 +1065,7 @@ err:
+@@ -1064,7 +1064,7 @@ err:
 	if (work_done < budget) {
 		int more_to_do = 0;
 
--- a/target/linux/generic/pending-4.14/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-4.14/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@ -181,7 +181,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 		cfg->fc_flags |= RTF_REJECT;
 
 	if (rtm->rtm_type == RTN_LOCAL)
-@@ -3494,6 +3528,9 @@ static int rt6_fill_node(struct net *net
+@@ -3499,6 +3533,9 @@ static int rt6_fill_node(struct net *net
 		case -EACCES:
 			rtm->rtm_type = RTN_PROHIBIT;
 			break;
@ -191,7 +191,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 		case -EAGAIN:
 			rtm->rtm_type = RTN_THROW;
 			break;
-@@ -3812,6 +3849,8 @@ static int ip6_route_dev_notify(struct n
+@@ -3817,6 +3854,8 @@ static int ip6_route_dev_notify(struct n
 #ifdef CONFIG_IPV6_MULTIPLE_TABLES
 		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
 		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@ -200,7 +200,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
 		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
 #endif
-@@ -3823,6 +3862,7 @@ static int ip6_route_dev_notify(struct n
+@@ -3828,6 +3867,7 @@ static int ip6_route_dev_notify(struct n
 		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
 #ifdef CONFIG_IPV6_MULTIPLE_TABLES
 		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@ -208,7 +208,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
 #endif
 	}
-@@ -4039,6 +4079,17 @@ static int __net_init ip6_route_net_init
+@@ -4044,6 +4084,17 @@ static int __net_init ip6_route_net_init
 	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
 	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
 			 ip6_template_metrics, true);
@ -226,7 +226,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 #endif
 
 	net->ipv6.sysctl.flush_delay = 0;
-@@ -4057,6 +4108,8 @@ out:
+@@ -4062,6 +4113,8 @@ out:
 	return ret;
 
 #ifdef CONFIG_IPV6_MULTIPLE_TABLES
@ -235,7 +235,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 out_ip6_prohibit_entry:
 	kfree(net->ipv6.ip6_prohibit_entry);
 out_ip6_null_entry:
-@@ -4074,6 +4127,7 @@ static void __net_exit ip6_route_net_exi
+@@ -4079,6 +4132,7 @@ static void __net_exit ip6_route_net_exi
 #ifdef CONFIG_IPV6_MULTIPLE_TABLES
 	kfree(net->ipv6.ip6_prohibit_entry);
 	kfree(net->ipv6.ip6_blk_hole_entry);
@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 #endif
 	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
 }
-@@ -4147,6 +4201,9 @@ void __init ip6_route_init_special_entri
+@@ -4152,6 +4206,9 @@ void __init ip6_route_init_special_entri
 	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
 	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
 	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
--- a/target/linux/generic/pending-4.9/190-2-5-e1000e-Fix-wrong-comment-related-to-link-detection.patch
+++ b/target/linux/generic/pending-4.9/190-2-5-e1000e-Fix-wrong-comment-related-to-link-detection.patch
@ -23,7 +23,7 @@ Tested-by: Aaron Brown <aaron.f.brown@intel.com>

 --- a/drivers/net/ethernet/intel/e1000e/netdev.c
 +++ b/drivers/net/ethernet/intel/e1000e/netdev.c
-@@ -5078,7 +5078,7 @@ static bool e1000e_has_link(struct e1000
+@@ -5067,7 +5067,7 @@ static bool e1000e_has_link(struct e1000
 
 	/* get_link_status is set on LSC (link status) interrupt or
 	 * Rx sequence error interrupt.  get_link_status will stay
@ -32,7 +32,7 @@ Tested-by: Aaron Brown <aaron.f.brown@intel.com>
 	 * for copper adapters ONLY
 	 */
 	switch (hw->phy.media_type) {
-@@ -5096,7 +5096,7 @@ static bool e1000e_has_link(struct e1000
+@@ -5085,7 +5085,7 @@ static bool e1000e_has_link(struct e1000
 		break;
 	case e1000_media_type_internal_serdes:
 		ret_val = hw->mac.ops.check_for_link(hw);
--- a/target/linux/ipq40xx/patches-4.14/080-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch
+++ b/target/linux/ipq40xx/patches-4.14/080-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch
@ -71,7 +71,7 @@ Origin: other, https://patchwork.kernel.org/patch/10339127/
 			#interrupt-cells = <2>;
 --- a/drivers/pinctrl/qcom/pinctrl-msm.c
 +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
-@@ -831,11 +831,24 @@ static int msm_gpio_init(struct msm_pinc
+@@ -839,11 +839,24 @@ static int msm_gpio_init(struct msm_pinc
 		return ret;
 	}
 
--- a/target/linux/ipq806x/patches-4.14/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
+++ b/target/linux/ipq806x/patches-4.14/0073-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
@ -112,7 +112,7 @@ Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
 #include "../core.h"
 #include "../pinconf.h"
 #include "pinctrl-msm.h"
-@@ -638,6 +639,9 @@ static void msm_gpio_irq_ack(struct irq_
+@@ -646,6 +647,9 @@ static void msm_gpio_irq_ack(struct irq_
 	const struct msm_pingroup *g;
 	unsigned long flags;
 	u32 val;
@ -122,7 +122,7 @@ Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
 
 	g = &pctrl->soc->groups[d->hwirq];
 
-@@ -676,11 +680,30 @@ static int msm_gpio_irq_set_type(struct
+@@ -684,11 +688,30 @@ static int msm_gpio_irq_set_type(struct
 	else
 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 
@ -157,7 +157,7 @@ Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
 
 	/* Update configuration for gpio.
 	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
-@@ -954,4 +977,3 @@ int msm_pinctrl_remove(struct platform_d
+@@ -962,4 +985,3 @@ int msm_pinctrl_remove(struct platform_d
 	return 0;
 }
 EXPORT_SYMBOL(msm_pinctrl_remove);
--- a/target/linux/layerscape/Makefile
+++ b/target/linux/layerscape/Makefile
@ -9,8 +9,8 @@ include $(TOPDIR)/rules.mk
 BOARD:=layerscape
 BOARDNAME:=NXP Layerscape
 KERNEL_PATCHVER:=4.9
-FEATURES:=squashfs nand usb pcie gpio fpu ubifs
-SUBTARGETS:=armv8_64b armv8_32b
+FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4
+SUBTARGETS:=armv8_64b armv8_32b armv7
 MAINTAINER:=Yangbo Lu <yangbo.lu@nxp.com>

 define Target/Description
--- a/target/linux/layerscape/README
+++ b/target/linux/layerscape/README
@ -4,10 +4,15 @@ Layerscape Quick Start
 1. Layerscape target support
 ----------------------------
 * ARMv8 64-bit
-  LS1012ARDB LS1012AFRDM LS1043ARDB LS1046ARDB LS1088ARDB LS2088ARDB
+  LS1012ARDB LS1012AFRWY LS1043ARDB LS1046ARDB LS1088ARDB LS2088ARDB
+  (SD card boot support on LS1043ARDB/LS1046ARDB/LS1088ARDB)

 * ARMv8 32-bit
-  LS1012ARDB LS1012AFRDM LS1043ARDB LS1046ARDB
+  LS1012ARDB LS1012AFRWY LS1043ARDB LS1046ARDB
+
+* ARMv7
+  LS1021ATWR
+  (SD card boot support on LS1021ATWR)


 2. Build
@ -17,129 +22,94 @@ Before configuration and build, update and install package feeds.
 $ ./scripts/feeds update -a
 $ ./scripts/feeds install -a

-2.1 make menuconfig
-------------------
-* For single device
+* make menuconfig
+  Target System:   "NXP Layerscape"
+  Subtarget:       (Select subtarget)
+  Target Profile:  (Select device, or "Multiple devices")
+  Target Devices:  (Select devices. Available when Target Profile is "Multiple devices")
+  Target Images:   (Disable "GZip images" if don't want to unzip manually to use the images.)

-  Target System:   "NXP Layerscape".
-  Subtarget:       "ARMv8 64-bit based boards" or "ARMv8 32-bit based boards"
-  Target Profile:  (select device you want to build)
+  Note: The first time make menuconfig would create a .config file which
+  would include all dependencies for selected target. After that, make
+  menuconfig still could be used to modify packages. If want to change
+  other target, please remove .config and make menuconfig to select again.
+  Otherwise the packages selected in .config would be a mess.

-  For example, build firmware for 64-bit ls1043ardb.
-  +---------------------------------------------+
-  | Target System (NXP Layerscape)  --->        |
-  |---------------------------------------------|
-  | Subtarget (ARMv8 64-bit based boards)  ---> |
-  |---------------------------------------------|
-  | Target Profile (ls1043ardb-armv8_64b)  ---> |
-  +---------------------------------------------+
+* make download (or make download -j<n>)

-* For multiple devices
+* make (or make -j<n>)

-  Target System:   "NXP Layerscape".
-  Subtarget:       "ARMv8 64-bit based boards" or "ARMv8 32-bit based boards"
-  Target Profile:  "Multiple devices"
-  Target Devices:  (select devices you want to build)
-
-  For example, build firmware for all 64-bit devices.
-  Target Devices  --->
-  +-----------------------------------------------------------------+
-  | [*] Enable all profiles by default                              |
-  |-----------------------------------------------------------------|
-  | [*] Use a per-device root filesystem that adds profile packages |
-  |-----------------------------------------------------------------|
-  | [*] ls1012afrdm-armv8_64b  --->                                 |
-  |-----------------------------------------------------------------|
-  | [*] ls1012ardb-armv8_64b  --->                                  |
-  |-----------------------------------------------------------------|
-  | [*] ls1043ardb-armv8_64b  --->                                  |
-  |-----------------------------------------------------------------|
-  | [*] ls1046ardb-armv8_64b  --->                                  |
-  |-----------------------------------------------------------------|
-  | [*] ls1088ardb-armv8_64b  --->                                  |
-  |-----------------------------------------------------------------|
-  | [*] ls2088ardb-armv8_64b  --->                                  |
-  +-----------------------------------------------------------------+
-
-Note: The first time make menuconfig would create a .config file which
-would include all dependencies for selected target. After that, make
-menuconfig still could be used to modify packages. If want to change
-other target, please remove .config and make menuconfig to select again.
-Otherwise the packages selected in .config would be a mess.
-
-2.2 make (or make -j<n>)
------------------------
-
-2.3 Final firmware
------------------
-Final firmware would be in bin/targets/layerscape/<subtarget>/, and
-named as openwrt-layerscape-<subtarget>-<device>-<rootfs>-firmware.bin.
+* Final firmware/image
+  Path: bin/targets/layerscape/<subtarget>/
+  Firmware for flash: openwrt-layerscape-<subtarget>-<device>-<rootfs>-firmware.bin
+  Image for SD card: openwrt-layerscape-<subtarget>-<device>-<rootfs>-sdcard.img


-3. Program firmware to NOR/QSPI flash
-------------------------------------
-* LS1043ARDB (NOR flash)
+3. Program NOR/QSPI flash or SD card
+------------------------------------
+The firmware.bin or sdcard.img is an all-in-one image including all things for
+OpenWrt staring up. (except LS1012AFRWY. Refer to 3.3.)
+If you want to install all things into flash, please use firmware.bin.
+If you want to install all things into SD card, please use sdcard.img.

-  Start up from bank0, and program firmware to bank4 with below commands.
-  Switch to bank4 to start up OpenWrt.
+3.1 Program sdcard.img to SD card
+---------------------------------
+sdcard.img could be programmed to SD card in either u-boot environment
+or linux environment. After programming, configure the board to boot
+from SD card.

-  => tftp a0000000 <firmware_name>.bin
-  => protect off all
-  => erase 64000000 +$filesize
-  => cp.b a0000000 64000000 $filesize
-  => cpld reset altbank
+* u-boot environment

-* LS2088ARDB (NOR flash)
+  => tftp a0000000 <image_name>-sdcard.img
+  => mmc write a0000000 0 a0000

-  Start up from bank0, and program firmware to bank4 with below commands.
-  Switch to bank4 to start up OpenWrt.
+  Note: The default sdcard.img size is 320MB. a0000 is the block number for 320MB.
+  blk_num = filesize / 512.

-  => tftp a0000000 <firmware_name>.bin
-  => protect off all
-  => erase 584000000 +$filesize
-  => cp.b a0000000 584000000 $filesize
-  => qix altbank
+* linux environment

+  $ dd if=./<image_name>-sdcard.img of=/dev/mmcblkx
+
+  Note: Need to check the SD card device name to replace "mmcblkx".
+
+3.2 Program firmware.bin to flash
+---------------------------------
 * LS1012ARDB (QSPI flash)
-
  Start up from bank1, and program firmware to bank2 with below commands.
  Switch to bank2 to start up OpenWrt.

-  => tftp a0000000 <firmware_name>.bin
+  => tftp a0000000 <firmware_name>-firmware.bin
  => i2c mw 0x24 0x7 0xfc;i2c mw 0x24 0x3 0xf5
  => sf probe 0:0
  => sf erase 0 +$filesize
  => sf write a0000000 0 $filesize
  => reset

-* LS1012AFRDM (QSPI flash)
+* LS1043ARDB (NOR flash)
+  Start up from bank0, and program firmware to bank4 with below commands.
+  Switch to bank4 to start up OpenWrt.

-  LS1012AFRDM board only has one bank. Start up board, and program firmware
-  with below commands. Reset to start up OpenWrt.
-
-  => tftp 96000000 <firmware_name>.bin
-  => sf probe 0:0
-  => sf erase 0 +$filesize
-  => sf write 96000000 0 $filesize
-  => reset
+  => tftp a0000000 <firmware_name>-firmware.bin
+  => protect off all
+  => erase 64000000 +$filesize
+  => cp.b a0000000 64000000 $filesize
+  => cpld reset altbank

 * LS1046ARDB (QSPI flash)
-
  Start up from bank1, and program firmware to bank2 with below commands.
  Switch to bank2 to start up OpenWrt.

-  => tftp a0000000 <firmware_name>.bin
+  => tftp a0000000 <firmware_name>-firmware.bin
  => sf probe 0:1
  => sf erase 0 +$filesize
  => sf write a0000000 0 $filesize
  => cpld reset altbank

 * LS1088ARDB (QSPI flash)
-
  Start up from bank0, and program firmware to bank1 with below commands.
  Switch to bank1 to start up OpenWrt.

-  => tftp a0000000 <firmware_name>.bin
+  => tftp a0000000 <firmware_name>-firmware.bin
  => sf probe 0:1
  => sf erase 0 +$filesize
  => sf write a0000000 0 $filesize
@ -149,6 +119,35 @@ named as openwrt-layerscape-<subtarget>-<device>-<rootfs>-firmware.bin.
  bank1 instead of 'qix altbank'.
  => i2c mw 66 50 20;i2c mw 66 10 20;i2c mw 66 10 21

+* LS2088ARDB (NOR flash)
+  Start up from bank0, and program firmware to bank4 with below commands.
+  Switch to bank4 to start up OpenWrt.
+
+  => tftp a0000000 <firmware_name>-firmware.bin
+  => protect off all
+  => erase 584000000 +$filesize
+  => cp.b a0000000 584000000 $filesize
+  => qix altbank
+
+3.3 Program LS1012AFRWY
+-----------------------
+* LS1012AFRWY (QSPI flash + SD card)
+  LS1012AFRWY only supports 2MB QSPI flash. We have to put u-boot, and
+  some firmwares on QSPI flash, and kernel/dtb/rootfs on SD card.
+  So both firmware.bin and sdcard.img are needed for OpenWrt starting up.
+
+  To program sdcard.img, please use linux command described in 3.1 on a
+  linux machine.
+  To program firmware.bin, start up board from QSPI flash, and program
+  firmware with below commands. Reset to start up OpenWrt. (LS1012AFRWY
+  supports only one bank.)
+
+  => tftp 96000000 <firmware_name>-firmware.bin
+  => sf probe 0:0
+  => sf erase 0 +$filesize
+  => sf write 96000000 0 $filesize
+  => reset
+

 4. Known issues and limitation
 ------------------------------
@ -161,10 +160,7 @@ named as openwrt-layerscape-<subtarget>-<device>-<rootfs>-firmware.bin.
  => setenv eth1addr 00:04:9F:04:65:4c


-5. Other references and sources
-------------------------------
+5. Other references
+-------------------
 - NXP LSDK site: https://lsdk.github.io/
-
- NXP LSDK github: https://github.com/qoriq-open-source
-
- LEDE documentation: https://lede-project.org/docs/start
+- OpenWrt documentation: https://openwrt.org/docs/start
--- a/target/linux/layerscape/armv7/config-4.9
+++ b/target/linux/layerscape/armv7/config-4.9
@ -0,0 +1,951 @@
+CONFIG_ABX500_CORE=y
+CONFIG_AD525X_DPOT=y
+CONFIG_AD525X_DPOT_I2C=y
+# CONFIG_AD525X_DPOT_SPI is not set
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AK8975=y
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_APDS9802ALS=y
+CONFIG_AQUANTIA_PHY=y
+# CONFIG_ARCH_AXXIA is not set
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_AT803X_PHY=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXP20X_POWER is not set
+CONFIG_BATTERY_ACT8945A=y
+CONFIG_BATTERY_SBS=y
+CONFIG_BCM_NET_PHYLIB=y
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_BLK_MQ_PCI=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_BOUNCE=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_BUILD_BIN2C=y
+CONFIG_CACHE_L2X0=y
+# CONFIG_CACHE_L2X0_PMU is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+# CONFIG_CHARGER_MAX14577 is not set
+CONFIG_CHARGER_TPS65090=y
+# CONFIG_CHARGER_TPS65217 is not set
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=64
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MAX77686=y
+# CONFIG_COMMON_CLK_PALMAS is not set
+# CONFIG_COMMON_CLK_RK808 is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+CONFIG_COMPACTION=y
+CONFIG_COMPAT_BRK=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CORTINA_PHY is not set
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_AES_ARM_CE is not set
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_GHASH_ARM_CE is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SHA1_ARM_CE is not set
+# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
+# CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
+# CONFIG_CRYPTO_SHA512_ARM is not set
+# CONFIG_CRYPTO_TLS is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_IMX_UART_PORT=1
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_RODATA=y
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVKMEM=y
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DW_DMAC=y
+CONFIG_DW_DMAC_CORE=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_MM_EDAC is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EFI=y
+# CONFIG_EFIVAR_FS is not set
+CONFIG_EFI_ARMSTUB=y
+# CONFIG_EFI_CAPSULE_LOADER is not set
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_EXPORTFS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+# CONFIG_EXTCON_MAX14577 is not set
+# CONFIG_EXTCON_MAX8997 is not set
+# CONFIG_EXTCON_PALMAS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAT_FS=y
+# CONFIG_FEC is not set
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FREEZER=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+# CONFIG_FSL_PPFE is not set
+CONFIG_FSL_PQ_MDIO=y
+# CONFIG_FSL_QDMA is not set
+# CONFIG_FSL_SDK_DPA is not set
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTM_ALARM=y
+CONFIG_FTRACE=y
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GIANFAR=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_AXP209 is not set
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_EM=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=y
+# CONFIG_GPIO_STMPE is not set
+CONFIG_GPIO_SYSCON=y
+# CONFIG_GPIO_TPS65218 is not set
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=y
+CONFIG_GPIO_XILINX=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SMCCC=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IMX_SRC=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DEMUX_PINCTRL=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+CONFIG_I2C_XILINX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_ICS932S401=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+CONFIG_IIO_HRTIMER_TRIGGER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IMX2_WDT=y
+CONFIG_IMX_DMA=y
+CONFIG_IMX_SDMA=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_ISL29003=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYS=y
+CONFIG_KVM=y
+CONFIG_KVM_ARM_HOST=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_MAX8997 is not set
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LS_SOC_DRIVERS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MCPM=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BOARDINFO=y
+# CONFIG_MDIO_FSL_BACKPLANE is not set
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMCG=y
+# CONFIG_MEMCG_SWAP is not set
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_ACT8945A=y
+CONFIG_MFD_AS3711=y
+CONFIG_MFD_AS3722=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_BCM590XX=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MAX14577=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX8907=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65218=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+# CONFIG_MFD_TWL4030_AUDIO is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSDOS_FS=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_DENALI=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MX3_IPU=y
+CONFIG_MX3_IPU_IRQS=4
+CONFIG_NAMESPACES=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_NS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=y
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_BUS_ADDR_T_64BIT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_PALMAS=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AS3722=y
+CONFIG_POWER_RESET_BRCMKONA=y
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PROBE_EVENTS is not set
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_CONSOLE=y
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PSTORE_ZLIB_COMPRESS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_GIANFAR=y
+CONFIG_PWM=y
+# CONFIG_PWM_IMX is not set
+# CONFIG_PWM_STMPE is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_TWL is not set
+# CONFIG_PWM_TWL_LED is not set
+CONFIG_QORIQ_CPUFREQ=y
+# CONFIG_QUICC_ENGINE is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_AS3711=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BCM590XX=y
+CONFIG_REGULATOR_DA9210=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_LP872X=y
+# CONFIG_REGULATOR_MAX14577 is not set
+CONFIG_REGULATOR_MAX77686=y
+# CONFIG_REGULATOR_MAX77802 is not set
+CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_MAX8973=y
+# CONFIG_REGULATOR_MAX8997 is not set
+# CONFIG_REGULATOR_MAX8998 is not set
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PWM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_REGULATOR_TPS51632=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65218=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_VEXPRESS=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
+CONFIG_RTC_DRV_DS3232=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_EM3027=y
+# CONFIG_RTC_DRV_IMXDI is not set
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_MAX8907=y
+# CONFIG_RTC_DRV_MAX8997 is not set
+# CONFIG_RTC_DRV_MAX8998 is not set
+# CONFIG_RTC_DRV_MXC is not set
+CONFIG_RTC_DRV_PALMAS=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_DRV_PCF85263=y
+# CONFIG_RTC_DRV_RK808 is not set
+# CONFIG_RTC_DRV_S5M is not set
+CONFIG_RTC_DRV_TPS6586X=y
+CONFIG_RTC_DRV_TPS65910=y
+CONFIG_RTC_DRV_TWL4030=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIL24=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_SENSORS_ISL29028=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_LM95245=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EM=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
+CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_ST_ASC=y
+CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SMSC_PHY=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+CONFIG_SOC_LS1021A=y
+# CONFIG_SOC_VF610 is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_IMX is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPMI=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STAGING_BOARD=y
+CONFIG_STMPE_I2C=y
+# CONFIG_STMPE_SPI is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_SW_SYNC is not set
+CONFIG_SYNC_FILE=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TRACING_EVENTS_GPIO=y
+CONFIG_TREE_RCU=y
+CONFIG_TUN=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_TWL4030_WATCHDOG is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNIX_DIAG=y
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VDSO=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VETH=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VEXPRESS_SYSCFG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VHOST=y
+CONFIG_VHOST_NET=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
--- a/target/linux/layerscape/armv7/target.mk
+++ b/target/linux/layerscape/armv7/target.mk
@ -0,0 +1,16 @@
+#
+# Copyright 2018 NXP
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+ARCH:=arm
+BOARDNAME:=ARMv7 based boards
+CPU_TYPE:=cortex-a7
+CPU_SUBTYPE:=neon-vfpv4
+KERNELNAME:=zImage dtbs
+
+define Target/Description
+	Build firmware images for NXP Layerscape ARMv7 based boards.
+endef
--- a/target/linux/layerscape/armv8_32b/config-4.9
+++ b/target/linux/layerscape/armv8_32b/config-4.9
@ -145,6 +145,8 @@ CONFIG_CAN_RAW=y
 # CONFIG_CAN_SJA1000 is not set
 # CONFIG_CAN_SOFTING is not set
 # CONFIG_CAN_TI_HECC is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_CFS_BANDWIDTH is not set
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_CPUACCT=y
@ -464,6 +466,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_CHIP=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 CONFIG_GENERIC_MSI_IRQ=y
--- a/target/linux/layerscape/armv8_64b/config-4.9
+++ b/target/linux/layerscape/armv8_64b/config-4.9
@ -98,6 +98,7 @@ CONFIG_ARM_GIC=y
 CONFIG_ARM_GIC_V2M=y
 CONFIG_ARM_GIC_V3=y
 CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
 # CONFIG_ARM_PL172_MPMC is not set
 CONFIG_ARM_PMU=y
 CONFIG_ARM_PSCI_FW=y
@ -157,6 +158,8 @@ CONFIG_CAVIUM_ERRATUM_22375=y
 CONFIG_CAVIUM_ERRATUM_23144=y
 CONFIG_CAVIUM_ERRATUM_23154=y
 CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_CEPH_LIB=y
 # CONFIG_CEPH_LIB_PRETTYDEBUG is not set
 # CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
@ -165,7 +168,7 @@ CONFIG_CFQ_GROUP_IOSCHED=y
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_CGROUP_DEVICE=y
-# CONFIG_CGROUP_FREEZER is not set
+CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_HUGETLB=y
 CONFIG_CGROUP_PERF=y
 CONFIG_CGROUP_PIDS=y
@ -417,6 +420,8 @@ CONFIG_FSL_BMAN_DEBUGFS=y
 CONFIG_FSL_DPAA2=y
 CONFIG_FSL_DPAA2_ETH=y
 CONFIG_FSL_DPAA2_ETHSW=y
+# CONFIG_FSL_DPAA2_ETH_CEETM is not set
+# CONFIG_FSL_DPAA2_ETH_DEBUGFS is not set
 # CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE is not set
 CONFIG_FSL_DPAA2_EVB=y
 CONFIG_FSL_DPAA2_MAC=y
@ -499,6 +504,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_CHIP=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
 CONFIG_GENERIC_IRQ_MIGRATION=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
@ -845,6 +851,7 @@ CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_IP_TUNNEL=y
 CONFIG_NET_NS=y
 CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
 CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
@ -957,6 +964,7 @@ CONFIG_QCOM_QDF2400_ERRATUM_0065=y
 # CONFIG_QFMT_V2 is not set
 CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
 CONFIG_QORIQ_CPUFREQ=y
+CONFIG_QORIQ_THERMAL=y
 # CONFIG_QUICC_ENGINE is not set
 CONFIG_QUOTA=y
 CONFIG_QUOTACTL=y
@ -1233,4 +1241,3 @@ CONFIG_XZ_DEC_SPARC=y
 CONFIG_XZ_DEC_X86=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_ZLIB_INFLATE=y
-CONFIG_QORIQ_THERMAL=y
--- a/target/linux/layerscape/image/Makefile
+++ b/target/linux/layerscape/image/Makefile
@ -9,214 +9,52 @@ include $(INCLUDE_DIR)/image.mk

 ITB_BOARDS = traverse-five64

-define Build/append-ls-rcw
+LS_SD_ROOTFSPART_OFFSET = 64
+LS_SD_IMAGE_SIZE = $(shell echo $$((($(LS_SD_ROOTFSPART_OFFSET) + \
+	$(CONFIG_TARGET_ROOTFS_PARTSIZE)) * 1024 * 1024)))
+
+define Build/ls-clean
 	rm -f $@
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-rcw.bin >> $@
 endef

-define Build/append-ls-uboot
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-$(SUBTARGET)-uboot.bin >> $@
+define Build/ls-append
+	dd if=$(STAGING_DIR_IMAGE)/$(1) >> $@
 endef

-define Build/append-ls-ppa
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-ppa.itb >> $@
-endef
-
-define Build/append-ls-fman
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-fman.bin >> $@
-endef
-
-define Build/append-ls-mc
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-mc.itb >> $@
-endef
-
-define Build/append-ls-ppfe
-	dd if=$(STAGING_DIR_IMAGE)/pfe.itb >> $@
-endef
-
-define Build/append-ls-dpl
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-dpl.dtb >> $@
-endef
-
-define Build/append-ls-dpc
-	dd if=$(STAGING_DIR_IMAGE)/$(1)-dpc.dtb >> $@
-endef
-
-define Build/append-ls-dtb
+define Build/ls-append-dtb
 	$(call Image/BuildDTB,$(DTS_DIR)/$(1).dts,$(DTS_DIR)/$(1).dtb)
 	dd if=$(DTS_DIR)/$(1).dtb >> $@
 endef

+define Build/ls-append-sdhead
+	./gen_sdcard_head_img.sh $(STAGING_DIR_IMAGE)/$(1)-sdcard-head.img \
+		$(LS_SD_ROOTFSPART_OFFSET) $(CONFIG_TARGET_ROOTFS_PARTSIZE)
+	dd if=$(STAGING_DIR_IMAGE)/$(1)-sdcard-head.img >> $@
+endef
+
 define Build/traverse-fit
-	./mkits-multiple-config.sh -o $@.its -A $(LINUX_KARCH) -v $(LINUX_VERSION) \
-		-k $@ -a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
+	./mkits-multiple-config.sh -o $@.its -A $(LINUX_KARCH) \
+		-v $(LINUX_VERSION) -k $@ -a $(KERNEL_LOADADDR) \
+		-e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \
 		-C gzip -c 1 -c 2 \
-		-d $(DEVICE_DTS_DIR)/freescale/traverse-ls1043s.dtb -D "Traverse_LS1043S" -n "ls1043s" -a $(FDT_LOADADDR) -c 1 \
-		-d $(DEVICE_DTS_DIR)/freescale/traverse-ls1043v.dtb -D "Traverse_LS1043V" -n "ls1043v" -a $(FDT_LOADADDR) -c 2
+		-d $(DEVICE_DTS_DIR)/freescale/traverse-ls1043s.dtb \
+		-D "Traverse_LS1043S" -n "ls1043s" -a $(FDT_LOADADDR) -c 1 \
+		-d $(DEVICE_DTS_DIR)/freescale/traverse-ls1043v.dtb \
+		-D "Traverse_LS1043V" -n "ls1043v" -a $(FDT_LOADADDR) -c 2
 	PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
 	@mv -f $@.new $@
 endef

-define Device/Default
-  PROFILES = Default
-  FILESYSTEMS := squashfs
-  DEVICE_DTS :=
-  IMAGES = firmware.bin
-
 ifeq ($(SUBTARGET),armv8_64b)
-  KERNEL := kernel-bin | gzip | uImage gzip
-  KERNEL_LOADADDR = 0x80080000
-  KERNEL_ENTRY_POINT = 0x80080000
+include armv8_64b.mk
 endif
+
 ifeq ($(SUBTARGET),armv8_32b)
-  KERNEL := kernel-bin | uImage none
-  KERNEL_NAME := zImage
-  KERNEL_LOADADDR = 0x80008000
-  KERNEL_ENTRY_POINT = 0x80008000
-endif
-  FDT_LOADADDR = 0x90000000
-endef
-
-define Device/ls1043ardb
-  DEVICE_TITLE := ls1043ardb-$(SUBTARGET)
-  DEVICE_PACKAGES +=	rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb \
-			fman-layerscape-ls1043ardb layerscape-ppa-ls1043ardb
-  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk
-  IMAGE/firmware.bin =	append-ls-rcw $(1) | pad-to 1M | \
-			append-ls-uboot $(1) | pad-to 4M | \
-			append-ls-ppa $(1) | pad-to 9M | \
-			append-ls-fman $(1) | pad-to 15M | \
-			append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
-			append-kernel | pad-to 32M | \
-			append-rootfs | pad-rootfs | check-size 67108865
-endef
-TARGET_DEVICES += ls1043ardb
-
-define Device/ls1046ardb
-  DEVICE_TITLE := ls1046ardb-$(SUBTARGET)
-  DEVICE_PACKAGES +=	rcw-layerscape-ls1046ardb uboot-layerscape-$(SUBTARGET)-ls1046ardb \
-			fman-layerscape-ls1046ardb layerscape-ppa-ls1046ardb
-  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk
-  FILESYSTEMS := ubifs
-  UBIFS_OPTS := -m 1 -e 262016 -c 128
-  UBINIZE_OPTS := -E 5
-  BLOCKSIZE := 256KiB
-  PAGESIZE := 1
-  IMAGE/firmware.bin =	append-ls-rcw $(1) | pad-to 1M | \
-			append-ls-uboot $(1) | pad-to 4M | \
-			append-ls-ppa $(1) | pad-to 9M | \
-			append-ls-fman $(1) | pad-to 15M | \
-			append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
-			append-kernel | pad-to 32M | \
-			append-ubi | check-size 67108865
-endef
-TARGET_DEVICES += ls1046ardb
-
-define Device/ls1012ardb
-  DEVICE_TITLE := ls1012ardb-$(SUBTARGET)
-  DEVICE_PACKAGES +=	rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb \
-			kmod-ppfe layerscape-ppfe layerscape-ppa-ls1012ardb
-  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1012a-rdb
-  FILESYSTEMS := ubifs
-  UBIFS_OPTS := -m 1 -e 262016 -c 128
-  UBINIZE_OPTS := -E 5
-  BLOCKSIZE := 256KiB
-  PAGESIZE := 1
-  IMAGE/firmware.bin =	append-ls-rcw $(1) | pad-to 1M | \
-			append-ls-uboot $(1) | pad-to 4M | \
-			append-ls-ppa $(1) | pad-to 10M | \
-			append-ls-ppfe | pad-to 15M | \
-			append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
-			append-kernel | pad-to 32M | \
-			append-ubi | check-size 67108865
-endef
-TARGET_DEVICES += ls1012ardb
-
-define Device/ls1012afrdm
-  DEVICE_TITLE := ls1012afrdm-$(SUBTARGET)
-  DEVICE_PACKAGES +=	rcw-layerscape-ls1012afrdm uboot-layerscape-$(SUBTARGET)-ls1012afrdm \
-			kmod-ppfe layerscape-ppfe layerscape-ppa-ls1012afrdm
-  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1012a-frdm
-  FILESYSTEMS := ubifs
-  UBIFS_OPTS := -m 1 -e 262016 -c 128
-  UBINIZE_OPTS := -E 5
-  BLOCKSIZE := 256KiB
-  PAGESIZE := 1
-  IMAGE/firmware.bin =	append-ls-rcw $(1) | pad-to 1M | \
-			append-ls-uboot $(1) | pad-to 4M | \
-			append-ls-ppa $(1) | pad-to 10M | \
-			append-ls-ppfe | pad-to 15M | \
-			append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
-			append-kernel | pad-to 32M | \
-			append-ubi | check-size 67108865
-endef
-TARGET_DEVICES += ls1012afrdm
-
-ifeq ($(SUBTARGET),armv8_64b)
-define Device/ls1088ardb
-  DEVICE_TITLE := ls1088ardb-$(SUBTARGET)
-  DEVICE_PACKAGES +=	rcw-layerscape-ls1088ardb uboot-layerscape-$(SUBTARGET)-ls1088ardb \
-			layerscape-mc-ls1088ardb layerscape-dpl-ls1088ardb restool \
-			layerscape-ppa-ls1088ardb
-  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1088a-rdb
-  FILESYSTEMS := ubifs
-  UBIFS_OPTS := -m 1 -e 262016 -c 128
-  UBINIZE_OPTS := -E 5
-  BLOCKSIZE := 256KiB
-  PAGESIZE := 1
-  IMAGE/firmware.bin =	append-ls-rcw $(1) | pad-to 1M | \
-			append-ls-uboot $(1) | pad-to 4M | \
-			append-ls-ppa $(1) | pad-to 10M | \
-			append-ls-mc $(1) | pad-to 13M | \
-			append-ls-dpl $(1) | pad-to 14M | \
-			append-ls-dpc $(1) | pad-to 15M | \
-			append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
-			append-kernel | pad-to 32M | \
-			append-ubi | check-size 67108865
-endef
-TARGET_DEVICES += ls1088ardb
-
-define Device/ls2088ardb
-  DEVICE_TITLE := ls2088ardb-$(SUBTARGET)
-  DEVICE_PACKAGES +=	rcw-layerscape-ls2088ardb uboot-layerscape-$(SUBTARGET)-ls2088ardb \
-			layerscape-mc-ls2088ardb layerscape-dpl-ls2088ardb restool \
-			layerscape-ppa-ls2088ardb
-  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls2088a-rdb
-  IMAGE/firmware.bin =	append-ls-rcw $(1) | pad-to 1M | \
-			append-ls-uboot $(1) | pad-to 4M | \
-			append-ls-ppa $(1) | pad-to 10M | \
-			append-ls-mc $(1) | pad-to 13M | \
-			append-ls-dpl $(1) | pad-to 14M | \
-			append-ls-dpc $(1) | pad-to 15M | \
-			append-ls-dtb $$(DEVICE_DTS) | pad-to 16M | \
-			append-kernel | pad-to 32M | \
-			append-rootfs | pad-rootfs | check-size 67108865
-endef
-TARGET_DEVICES += ls2088ardb
+include armv8_32b.mk
 endif

-define Device/traverse-five64
-  KERNEL_NAME := Image
-  KERNEL_SUFFIX := -kernel.itb
-  KERNEL_INSTALL := 1
-  FILESYSTEMS := ubifs
-  DEVICE_TITLE := Traverse LS1043 Boards (Five64, LS1043S)
-  DEVICE_PACKAGES += fman-layerscape-ls1043ardb kmod-i2c-core kmod-rtc-isl1208 uboot-envtools \
-	uboot-traverse-ls1043v uboot-traverse-ls1043v-sdcard \
-	kmod-hwmon-core kmod-hwmon-ltc2990 kmod-gpio-pca953x kmod-input-gpio-keys-polled \
-	kmod-i2c-mux-pca954x kmod-hwmon-pac1934 kmod-hwmon-emc17xx
-  DEVICE_DESCRIPTION = Build images for Traverse LS1043 boards. This generates a single image \
-  	capable of booting on any of the boards in this family.
-  DEVICE_DTS = freescale/traverse-ls1043s
-  DEVICE_DTS_DIR = $(LINUX_DIR)/arch/arm64/boot/dts
-  DEVICE_DTS_CONFIG = ls1043s
-  KERNEL := kernel-bin | gzip | traverse-fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR)
-  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR)
-  IMAGES = root sysupgrade.tar
-  IMAGE/root = append-rootfs
-  IMAGE/sysupgrade.tar = sysupgrade-tar
-  UBIFS_OPTS := -m 2048 -e 124KiB -c 4096
-endef
-TARGET_DEVICES += traverse-five64
+ifeq ($(SUBTARGET),armv7)
+include armv7.mk
+endif

 $(eval $(call BuildImage))
--- a/target/linux/layerscape/image/armv7.mk
+++ b/target/linux/layerscape/image/armv7.mk
@ -0,0 +1,47 @@
+#
+# Copyright 2018 NXP
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Device/Default
+  PROFILES := Default
+  FILESYSTEMS := squashfs
+  IMAGES := firmware.bin
+  KERNEL := kernel-bin | uImage none
+  KERNEL_NAME := zImage
+  KERNEL_LOADADDR := 0x80008000
+  KERNEL_ENTRY_POINT := 0x80008000
+endef
+
+define Device/ls1021atwr
+  DEVICE_TITLE := LS1021ATWR
+  DEVICE_PACKAGES += layerscape-rcw-ls1021atwr
+  DEVICE_DTS := ls1021a-twr
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-rootfs | pad-rootfs | check-size 67108865
+endef
+TARGET_DEVICES += ls1021atwr
+
+define Device/ls1021atwr-sdboot
+  DEVICE_TITLE := LS1021ATWR (SD Card Boot)
+  DEVICE_DTS := ls1021a-twr
+  FILESYSTEMS := ext4
+  IMAGES := sdcard.img
+  IMAGE/sdcard.img := \
+    ls-clean | \
+    ls-append-sdhead $(1) | pad-to 4K | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
+    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
+endef
+TARGET_DEVICES += ls1021atwr-sdboot
--- a/target/linux/layerscape/image/armv8_32b.mk
+++ b/target/linux/layerscape/image/armv8_32b.mk
@ -0,0 +1,117 @@
+#
+# Copyright 2018 NXP
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Device/Default
+  PROFILES := Default
+  IMAGES := firmware.bin
+  FILESYSTEMS := ubifs
+  KERNEL := kernel-bin | uImage none
+  KERNEL_NAME := zImage
+  KERNEL_LOADADDR := 0x80008000
+  KERNEL_ENTRY_POINT := 0x80008000
+endef
+
+define Device/ls1012ardb
+  DEVICE_TITLE := LS1012ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1012ardb \
+    layerscape-ppfe \
+    layerscape-ppa-ls1012ardb \
+    u-boot-ls1012ardb-image \
+    kmod-ppfe
+  DEVICE_DTS := ../../../arm64/boot/dts/freescale/fsl-ls1012a-rdb
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 256KiB
+  PAGESIZE := 1
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 10M | \
+    ls-append pfe.itb | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-ubi | check-size 67108865
+endef
+TARGET_DEVICES += ls1012ardb
+
+define Device/ls1012afrwy
+  DEVICE_TITLE := LS1012AFRWY
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1012afrwy \
+    layerscape-ppfe \
+    layerscape-ppa-ls1012afrwy \
+    u-boot-ls1012afrwy-image \
+    kmod-ppfe
+  DEVICE_DTS := ../../../arm64/boot/dts/freescale/fsl-ls1012a-frwy
+  FILESYSTEMS := ext4
+  IMAGES := firmware.bin sdcard.img
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 128K | \
+    ls-append pfe.itb | pad-to 384K | \
+    ls-append $(1)-ppa.itb | pad-to 1024K | \
+    ls-append $(1)-uboot.bin | pad-to 1856K | \
+    ls-append $(1)-uboot-env.bin | pad-to 2048K | \
+    check-size 2097153
+  IMAGE/sdcard.img := \
+    ls-clean | \
+    ls-append-sdhead $(1) | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
+    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
+endef
+TARGET_DEVICES += ls1012afrwy
+
+define Device/ls1043ardb
+  DEVICE_TITLE := LS1043ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1043ardb \
+    layerscape-fman-ls1043ardb \
+    layerscape-ppa-ls1043ardb \
+    u-boot-ls1043ardb-image
+  DEVICE_DTS := ../../../arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk
+  FILESYSTEMS := squashfs
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 9M | \
+    ls-append $(1)-fman.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-rootfs | pad-rootfs | check-size 67108865
+endef
+TARGET_DEVICES += ls1043ardb
+
+define Device/ls1046ardb
+  DEVICE_TITLE := LS1046ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1046ardb \
+    layerscape-fman-ls1046ardb \
+    layerscape-ppa-ls1046ardb \
+    u-boot-ls1046ardb-image
+  DEVICE_DTS := ../../../arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 256KiB
+  PAGESIZE := 1
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 9M | \
+    ls-append $(1)-fman.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-ubi | check-size 67108865
+endef
+TARGET_DEVICES += ls1046ardb
--- a/target/linux/layerscape/image/armv8_64b.mk
+++ b/target/linux/layerscape/image/armv8_64b.mk
@ -0,0 +1,263 @@
+#
+# Copyright 2018 NXP
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Device/Default
+  PROFILES := Default
+  IMAGES := firmware.bin
+  FILESYSTEMS := ubifs
+  KERNEL := kernel-bin | gzip | uImage gzip
+  KERNEL_LOADADDR := 0x80080000
+  KERNEL_ENTRY_POINT := 0x80080000
+endef
+
+define Device/ls1012ardb
+  DEVICE_TITLE := LS1012ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1012ardb \
+    layerscape-ppfe \
+    layerscape-ppa-ls1012ardb \
+    kmod-ppfe
+  DEVICE_DTS := freescale/fsl-ls1012a-rdb
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 256KiB
+  PAGESIZE := 1
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 10M | \
+    ls-append pfe.itb | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-ubi | check-size 67108865
+endef
+TARGET_DEVICES += ls1012ardb
+
+define Device/ls1012afrwy
+  DEVICE_TITLE := LS1012AFRWY
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1012afrwy \
+    layerscape-ppfe \
+    layerscape-ppa-ls1012afrwy \
+    kmod-ppfe
+  DEVICE_DTS := freescale/fsl-ls1012a-frwy
+  FILESYSTEMS := ext4
+  IMAGES := firmware.bin sdcard.img
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 128K | \
+    ls-append pfe.itb | pad-to 384K | \
+    ls-append $(1)-ppa.itb | pad-to 1024K | \
+    ls-append $(1)-uboot.bin | pad-to 1856K | \
+    ls-append $(1)-uboot-env.bin | pad-to 2048K | \
+    check-size 2097153
+  IMAGE/sdcard.img := \
+    ls-clean | \
+    ls-append-sdhead $(1) | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
+    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
+endef
+TARGET_DEVICES += ls1012afrwy
+
+define Device/ls1043ardb
+  DEVICE_TITLE := LS1043ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1043ardb \
+    layerscape-fman-ls1043ardb \
+    layerscape-ppa-ls1043ardb
+  DEVICE_DTS := freescale/fsl-ls1043a-rdb-sdk
+  FILESYSTEMS := squashfs
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 9M | \
+    ls-append $(1)-fman.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-rootfs | pad-rootfs | check-size 67108865
+endef
+TARGET_DEVICES += ls1043ardb
+
+define Device/ls1043ardb-sdboot
+  DEVICE_TITLE := LS1043ARDB (SD Card Boot)
+  DEVICE_PACKAGES += \
+    layerscape-fman-ls1043ardb \
+    layerscape-ppa-ls1043ardb
+  DEVICE_DTS := freescale/fsl-ls1043a-rdb-sdk
+  FILESYSTEMS := ext4
+  IMAGES := sdcard.img
+  IMAGE/sdcard.img := \
+    ls-clean | \
+    ls-append-sdhead $(1) | pad-to 4K | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append ls1043ardb-ppa.itb | pad-to 9M | \
+    ls-append ls1043ardb-fman.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
+    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
+endef
+TARGET_DEVICES += ls1043ardb-sdboot
+
+define Device/ls1046ardb
+  DEVICE_TITLE := LS1046ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1046ardb \
+    layerscape-fman-ls1046ardb \
+    layerscape-ppa-ls1046ardb
+  DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 256KiB
+  PAGESIZE := 1
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 9M | \
+    ls-append $(1)-fman.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-ubi | check-size 67108865
+endef
+TARGET_DEVICES += ls1046ardb
+
+define Device/ls1046ardb-sdboot
+  DEVICE_TITLE := LS1046ARDB (SD Card Boot)
+  DEVICE_PACKAGES += \
+    layerscape-fman-ls1046ardb \
+    layerscape-ppa-ls1046ardb
+  DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk
+  FILESYSTEMS := ext4
+  IMAGES := sdcard.img
+  IMAGE/sdcard.img := \
+    ls-clean | \
+    ls-append-sdhead $(1) | pad-to 4K | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append ls1046ardb-ppa.itb | pad-to 9M | \
+    ls-append ls1046ardb-fman.bin | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
+    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
+endef
+TARGET_DEVICES += ls1046ardb-sdboot
+
+define Device/ls1088ardb
+  DEVICE_TITLE := LS1088ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1088ardb \
+    layerscape-mc-ls1088ardb \
+    layerscape-dpl-ls1088ardb \
+    layerscape-ppa-ls1088ardb \
+    restool
+  DEVICE_DTS := freescale/fsl-ls1088a-rdb
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 256KiB
+  PAGESIZE := 1
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 10M | \
+    ls-append $(1)-mc.itb | pad-to 13M | \
+    ls-append $(1)-dpl.dtb | pad-to 14M | \
+    ls-append $(1)-dpc.dtb | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-ubi | check-size 67108865
+endef
+TARGET_DEVICES += ls1088ardb
+
+define Device/ls1088ardb-sdboot
+  DEVICE_TITLE := LS1088ARDB (SD Card Boot)
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls1088ardb-sdboot \
+    layerscape-mc-ls1088ardb \
+    layerscape-dpl-ls1088ardb \
+    layerscape-ppa-ls1088ardb \
+    restool
+  DEVICE_DTS := freescale/fsl-ls1088a-rdb
+  FILESYSTEMS := ext4
+  IMAGES := sdcard.img
+  IMAGE/sdcard.img := \
+    ls-clean | \
+    ls-append-sdhead $(1) | pad-to 4K | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append ls1088ardb-ppa.itb | pad-to 10M | \
+    ls-append ls1088ardb-mc.itb | pad-to 13M | \
+    ls-append ls1088ardb-dpl.dtb | pad-to 14M | \
+    ls-append ls1088ardb-dpc.dtb | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
+    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
+endef
+TARGET_DEVICES += ls1088ardb-sdboot
+
+define Device/ls2088ardb
+  DEVICE_TITLE := LS2088ARDB
+  DEVICE_PACKAGES += \
+    layerscape-rcw-ls2088ardb \
+    layerscape-mc-ls2088ardb \
+    layerscape-dpl-ls2088ardb \
+    layerscape-ppa-ls2088ardb \
+    restool
+  DEVICE_DTS := freescale/fsl-ls2088a-rdb
+  FILESYSTEMS := squashfs
+  IMAGE/firmware.bin := \
+    ls-clean | \
+    ls-append $(1)-rcw.bin | pad-to 1M | \
+    ls-append $(1)-uboot.bin | pad-to 3M | \
+    ls-append $(1)-uboot-env.bin | pad-to 4M | \
+    ls-append $(1)-ppa.itb | pad-to 10M | \
+    ls-append $(1)-mc.itb | pad-to 13M | \
+    ls-append $(1)-dpl.dtb | pad-to 14M | \
+    ls-append $(1)-dpc.dtb | pad-to 15M | \
+    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
+    append-kernel | pad-to 32M | \
+    append-rootfs | pad-rootfs | check-size 67108865
+endef
+TARGET_DEVICES += ls2088ardb
+
+define Device/traverse-five64
+  KERNEL_NAME := Image
+  KERNEL_SUFFIX := -kernel.itb
+  KERNEL_INSTALL := 1
+  FDT_LOADADDR = 0x90000000
+  FILESYSTEMS := ubifs
+  DEVICE_TITLE := Traverse LS1043 Boards (Five64, LS1043S)
+  DEVICE_PACKAGES += \
+    layerscape-fman-ls1043ardb \
+    uboot-envtools uboot-traverse-ls1043v uboot-traverse-ls1043v-sdcard \
+    kmod-i2c-core kmod-i2c-mux-pca954x \
+    kmod-hwmon-core kmod-hwmon-ltc2990 kmod-hwmon-pac1934 kmod-hwmon-emc17xx\
+    kmod-gpio-pca953x kmod-input-gpio-keys-polled \
+    kmod-rtc-isl1208
+  DEVICE_DESCRIPTION = \
+    Build images for Traverse LS1043 boards. This generates a single image \
+    capable of booting on any of the boards in this family.
+  DEVICE_DTS = freescale/traverse-ls1043s
+  DEVICE_DTS_DIR = $(LINUX_DIR)/arch/arm64/boot/dts
+  DEVICE_DTS_CONFIG = ls1043s
+  KERNEL := kernel-bin | gzip | traverse-fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR)
+  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR)
+  IMAGES = root sysupgrade.tar
+  IMAGE/root = append-rootfs
+  IMAGE/sysupgrade.tar = sysupgrade-tar
+  UBIFS_OPTS := -m 2048 -e 124KiB -c 4096
+endef
+TARGET_DEVICES += traverse-five64
--- a/target/linux/layerscape/image/gen_sdcard_head_img.sh
+++ b/target/linux/layerscape/image/gen_sdcard_head_img.sh
@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+#
+# Copyright 2018 NXP
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+set -x
+[ $# -eq 3 ] || {
+    echo "SYNTAX: $0 <file> <rootfs part offset> <rootfs size>"
+    exit 1
+}
+
+OUTPUT="$1"
+ROOTFSOFFSET="$(($2 * 1024))"
+ROOTFSSIZE="$3"
+
+head=4
+sect=16
+
+set `ptgen -o $OUTPUT -h $head -s $sect -l $ROOTFSOFFSET -t 83 -p ${ROOTFSSIZE}M`
--- a/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch
@ -1,7 +1,7 @@
-From e43dec70614b55ba1ce24dfcdf8f51e36d800af2 Mon Sep 17 00:00:00 2001
+From 0774b97305507af18f8c43efb69aa00e6c57ae90 Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:26:46 +0800
-Subject: [PATCH 01/30] config: support layerscape
+Date: Fri, 6 Jul 2018 15:31:14 +0800
+Subject: [PATCH] config: support layerscape
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@ -19,22 +19,22 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 arch/arm/mach-imx/Kconfig               |  1 +
 drivers/base/Kconfig                    |  1 +
 drivers/crypto/Makefile                 |  2 +-
- drivers/net/ethernet/freescale/Kconfig  |  4 ++-
- drivers/net/ethernet/freescale/Makefile |  2 ++
- drivers/ptp/Kconfig                     | 29 +++++++++++++++++++
- drivers/rtc/Kconfig                     |  8 ++++++
+ drivers/net/ethernet/freescale/Kconfig  |  4 +-
+ drivers/net/ethernet/freescale/Makefile |  2 +
+ drivers/ptp/Kconfig                     | 29 +++++++++++
+ drivers/rtc/Kconfig                     |  8 +++
 drivers/rtc/Makefile                    |  1 +
 drivers/soc/Kconfig                     |  3 +-
- drivers/soc/fsl/Kconfig                 | 22 ++++++++++++++
- drivers/soc/fsl/Kconfig.arm             | 16 +++++++++++
- drivers/soc/fsl/Makefile                |  4 +++
- drivers/soc/fsl/layerscape/Kconfig      | 10 +++++++
+ drivers/soc/fsl/Kconfig                 | 30 ++++++++++++
+ drivers/soc/fsl/Kconfig.arm             | 16 ++++++
+ drivers/soc/fsl/Makefile                |  5 ++
+ drivers/soc/fsl/layerscape/Kconfig      | 10 ++++
 drivers/soc/fsl/layerscape/Makefile     |  1 +
- drivers/staging/Kconfig                 |  6 ++++
+ drivers/staging/Kconfig                 |  6 +++
 drivers/staging/Makefile                |  3 ++
- drivers/staging/fsl-dpaa2/Kconfig       | 51 +++++++++++++++++++++++++++++++++
- drivers/staging/fsl-dpaa2/Makefile      |  9 ++++++
- 18 files changed, 169 insertions(+), 4 deletions(-)
+ drivers/staging/fsl-dpaa2/Kconfig       | 65 +++++++++++++++++++++++++
+ drivers/staging/fsl-dpaa2/Makefile      |  9 ++++
+ 18 files changed, 192 insertions(+), 4 deletions(-)
 create mode 100644 drivers/soc/fsl/Kconfig
 create mode 100644 drivers/soc/fsl/Kconfig.arm
 create mode 100644 drivers/soc/fsl/layerscape/Kconfig
@ -179,7 +179,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 source "drivers/soc/rockchip/Kconfig"
 --- /dev/null
 +++ b/drivers/soc/fsl/Kconfig
-@@ -0,0 +1,22 @@
+@@ -0,0 +1,30 @@
 +#
 +# Freescale SOC drivers
 +#
@ -199,6 +199,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	  Initially only reading SVR and registering soc device are supported.
 +	  Other guts accesses, such as reading RCW, should eventually be moved
 +	  into this driver as well.
+
+config FSL_SLEEP_FSM
+	bool
+	help
+	  This driver configures a hardware FSM (Finite State Machine) for deep sleep.
+	  The FSM is used to finish clean-ups at the last stage of system entering deep
+	  sleep, and also wakes up system when a wake up event happens.
+
 +if ARM || ARM64
 +source "drivers/soc/fsl/Kconfig.arm"
 +endif
@ -223,7 +231,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +endif
 --- a/drivers/soc/fsl/Makefile
 +++ b/drivers/soc/fsl/Makefile
-@@ -5,3 +5,7 @@
+@@ -5,3 +5,8 @@
 obj-$(CONFIG_FSL_DPAA)                 += qbman/
 obj-$(CONFIG_QUICC_ENGINE)		+= qe/
 obj-$(CONFIG_CPM)			+= qe/
@ -231,6 +239,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +obj-$(CONFIG_FSL_LS2_CONSOLE)		+= ls2-console/
 +obj-$(CONFIG_SUSPEND)			+= rcpm.o
 +obj-$(CONFIG_LS_SOC_DRIVERS)		+= layerscape/
+obj-$(CONFIG_FSL_SLEEP_FSM)	+= sleep_fsm.o
 --- /dev/null
 +++ b/drivers/soc/fsl/layerscape/Kconfig
@@ -0,0 +1,10 @@
@ -285,7 +294,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +obj-$(CONFIG_FSL_PPFE)		+= fsl_ppfe/
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/Kconfig
-@@ -0,0 +1,51 @@
+@@ -0,0 +1,65 @@
 +#
 +# Freescale DataPath Acceleration Architecture Gen2 (DPAA2) drivers
 +#
@ -317,7 +326,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +# QBMAN_DEBUG requires some additional DPIO APIs
 +config FSL_DPAA2_ETH_DEBUGFS
-+	depends on DEBUG_FS && FSL_QBMAN_DEBUG
+	depends on DEBUG_FS
 +	bool "Enable debugfs support"
 +	default n
 +	---help---
@ -332,11 +341,25 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +          (PFC) in the driver.
 +
 +          If unsure, say N.
+
+config FSL_DPAA2_ETH_CEETM
+	depends on NET_SCHED
+	bool "DPAA2 Ethernet CEETM QoS"
+	default n
+	---help---
+	  Enable QoS offloading support through the CEETM hardware block.
 +endif
 +
 +source "drivers/staging/fsl-dpaa2/mac/Kconfig"
 +source "drivers/staging/fsl-dpaa2/evb/Kconfig"
-+source "drivers/staging/fsl-dpaa2/ethsw/Kconfig"
+
+config FSL_DPAA2_ETHSW
+	tristate "Freescale DPAA2 Ethernet Switch"
+	depends on FSL_DPAA2
+	depends on NET_SWITCHDEV
+	---help---
+	Driver for Freescale DPAA2 Ethernet Switch. Select
+	BRIDGE to have support for bridge tools.
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/Makefile
@@ -0,0 +1,9 @@
@ -347,5 +370,5 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +obj-$(CONFIG_FSL_DPAA2_ETH)	+= ethernet/
 +obj-$(CONFIG_FSL_DPAA2_MAC)	+= mac/
 +obj-$(CONFIG_FSL_DPAA2_EVB)	+= evb/
-+obj-$(CONFIG_FSL_DPAA2_ETHSW)	+= ethsw/
 +obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
+obj-$(CONFIG_FSL_DPAA2_ETHSW)	+= ethsw/
--- a/target/linux/layerscape/patches-4.9/202-core-linux-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/202-core-linux-support-layerscape.patch
--- a/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
@ -1,7 +1,7 @@
-From 45e934873f9147f692dddbb61abc088f4c8059d7 Mon Sep 17 00:00:00 2001
+From 2f2a0ab9e4b3186be981f7151a4f4f794d4b6caa Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 14:51:29 +0800
-Subject: [PATCH 03/30] arch: support layerscape
+Date: Thu, 5 Jul 2018 16:18:37 +0800
+Subject: [PATCH 03/32] arch: support layerscape
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
@ -20,22 +20,25 @@ Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- arch/arm/include/asm/delay.h          | 16 +++++++++
- arch/arm/include/asm/io.h             | 31 ++++++++++++++++++
- arch/arm/include/asm/mach/map.h       |  4 +--
- arch/arm/include/asm/pgtable.h        |  7 ++++
- arch/arm/kernel/bios32.c              | 43 ++++++++++++++++++++++++
- arch/arm/mm/dma-mapping.c             |  1 +
- arch/arm/mm/ioremap.c                 |  7 ++++
- arch/arm/mm/mmu.c                     |  9 +++++
- arch/arm64/include/asm/cache.h        |  2 +-
- arch/arm64/include/asm/io.h           | 30 +++++++++++++++++
- arch/arm64/include/asm/pci.h          |  4 +++
- arch/arm64/include/asm/pgtable-prot.h |  1 +
- arch/arm64/include/asm/pgtable.h      |  5 +++
- arch/arm64/kernel/pci.c               | 62 +++++++++++++++++++++++++++++++++++
- arch/arm64/mm/dma-mapping.c           |  6 ++++
- 15 files changed, 225 insertions(+), 3 deletions(-)
+ arch/arm/include/asm/delay.h           | 16 +++++++
+ arch/arm/include/asm/dma-mapping.h     |  6 ---
+ arch/arm/include/asm/io.h              | 31 +++++++++++++
+ arch/arm/include/asm/mach/map.h        |  4 +-
+ arch/arm/include/asm/pgtable.h         |  7 +++
+ arch/arm/kernel/bios32.c               | 43 ++++++++++++++++++
+ arch/arm/mm/dma-mapping.c              |  1 +
+ arch/arm/mm/ioremap.c                  |  7 +++
+ arch/arm/mm/mmu.c                      |  9 ++++
+ arch/arm64/include/asm/cache.h         |  2 +-
+ arch/arm64/include/asm/io.h            | 30 +++++++++++++
+ arch/arm64/include/asm/pci.h           |  4 ++
+ arch/arm64/include/asm/pgtable-prot.h  |  2 +
+ arch/arm64/include/asm/pgtable.h       |  5 +++
+ arch/arm64/kernel/pci.c                | 62 ++++++++++++++++++++++++++
+ arch/arm64/mm/dma-mapping.c            |  6 +++
+ arch/powerpc/include/asm/dma-mapping.h |  5 ---
+ arch/tile/include/asm/dma-mapping.h    |  5 ---
+ 18 files changed, 226 insertions(+), 19 deletions(-)

 --- a/arch/arm/include/asm/delay.h
 +++ b/arch/arm/include/asm/delay.h
@ -62,6 +65,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 /* Loop-based definitions for assembly code. */
 extern void __loop_delay(unsigned long loops);
 extern void __loop_udelay(unsigned long usecs);
+--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
+@@ -31,12 +31,6 @@ static inline struct dma_map_ops *get_dm
+ 		return __generic_dma_ops(dev);
+ }
+ 
+-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+-{
+-	BUG_ON(!dev);
+-	dev->archdata.dma_ops = ops;
+-}
+-
+ #define HAVE_ARCH_DMA_SUPPORTED 1
+ extern int dma_supported(struct device *dev, u64 mask);
+ 
 --- a/arch/arm/include/asm/io.h
 +++ b/arch/arm/include/asm/io.h
@@ -129,6 +129,7 @@ static inline u32 __raw_readl(const vola
@ -343,6 +361,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+@@ -68,6 +69,7 @@
+ #define PAGE_HYP_DEVICE		__pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
+ 
+ #define PAGE_S2			__pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
+#define PAGE_S2_NS		__pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
+ #define PAGE_S2_DEVICE		__pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
+ 
+ #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_NG | PTE_PXN | PTE_UXN)
 --- a/arch/arm64/include/asm/pgtable.h
 +++ b/arch/arm64/include/asm/pgtable.h
@@ -370,6 +370,11 @@ static inline int pmd_protnone(pmd_t pmd
@ -441,7 +467,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #include <linux/swiotlb.h>
 
 #include <asm/cacheflush.h>
-+#include <../../../drivers/staging/fsl-mc/include/mc-bus.h>
+#include <linux/fsl/mc.h>
 
 static int swiotlb __ro_after_init;
 
@ -461,3 +487,31 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	__iommu_setup_dma_ops(dev, dma_base, size, iommu);
 }
 +EXPORT_SYMBOL(arch_setup_dma_ops);
+--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
+@@ -91,11 +91,6 @@ static inline struct dma_map_ops *get_dm
+ 	return dev->archdata.dma_ops;
+ }
+ 
+-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+-{
+-	dev->archdata.dma_ops = ops;
+-}
+-
+ /*
+  * get_dma_offset()
+  *
+--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
+@@ -59,11 +59,6 @@ static inline phys_addr_t dma_to_phys(st
+ 
+ static inline void dma_mark_clean(void *addr, size_t size) {}
+ 
+-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+-{
+-	dev->archdata.dma_ops = ops;
+-}
+-
+ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+ {
+ 	if (!dev->dma_mask)
--- a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
+++ b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
--- a/target/linux/layerscape/patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch
+++ b/target/linux/layerscape/patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch
@ -11,7 +11,7 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>

 --- a/arch/arm64/boot/dts/freescale/Makefile
 +++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -20,7 +20,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
+@@ -21,7 +21,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
--- a/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
@ -1,7 +1,7 @@
-From 825d57369b196b64387348922b47adc5b651622c Mon Sep 17 00:00:00 2001
+From c03c545e064a81515fe109ddcc4ecb3895528e58 Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 14:55:47 +0800
-Subject: [PATCH 05/30] mtd: spi-nor: support layerscape
+Date: Fri, 6 Jul 2018 15:32:05 +0800
+Subject: [PATCH] mtd: spi-nor: support layerscape

 This is an integrated patch for layerscape qspi support.

@ -17,15 +17,16 @@ Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
 Signed-off-by: Ash Benz <ash.benz@bk.ru>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
+ drivers/mtd/devices/m25p80.c      |   3 +-
 drivers/mtd/mtdchar.c             |   2 +-
- drivers/mtd/spi-nor/fsl-quadspi.c | 327 +++++++++++++++++++++++++++++++-------
- drivers/mtd/spi-nor/spi-nor.c     | 136 ++++++++++++++--
+ drivers/mtd/spi-nor/fsl-quadspi.c | 327 ++++++++++++++++++++++++------
+ drivers/mtd/spi-nor/spi-nor.c     | 141 ++++++++++++-
 include/linux/mtd/spi-nor.h       |  14 +-
- 4 files changed, 409 insertions(+), 70 deletions(-)
+ 5 files changed, 416 insertions(+), 71 deletions(-)

 --- a/drivers/mtd/mtdchar.c
 +++ b/drivers/mtd/mtdchar.c
-@@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *
+@@ -455,7 +455,7 @@ static int mtdchar_readoob(struct file *
 	 * data. For our userspace tools it is important to dump areas
 	 * with ECC errors!
 	 * For kernel internal usage it also might return -EUCLEAN
@ -758,9 +759,15 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
 	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
-@@ -1131,6 +1152,9 @@ static const struct flash_info spi_nor_i
+@@ -1130,7 +1151,15 @@ static const struct flash_info spi_nor_i
+ 	{ "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
 	{ "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
+	{
+		"w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
 	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
 +	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
 +	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
@ -768,7 +775,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	{ "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
 	{
 		"w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
-@@ -1197,6 +1221,53 @@ static const struct flash_info *spi_nor_
+@@ -1197,6 +1226,53 @@ static const struct flash_info *spi_nor_
 		id[0], id[1], id[2]);
 	return ERR_PTR(-ENODEV);
 }
@ -822,7 +829,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
 			size_t *retlen, u_char *buf)
-@@ -1416,7 +1487,7 @@ static int macronix_quad_enable(struct s
+@@ -1416,7 +1492,7 @@ static int macronix_quad_enable(struct s
  * Write status Register and configuration register with 2 bytes
  * The first byte will be written to the status register, while the
  * second byte will be written to the configuration register.
@ -831,7 +838,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  */
 static int write_sr_cr(struct spi_nor *nor, u16 val)
 {
-@@ -1464,6 +1535,24 @@ static int spansion_quad_enable(struct s
+@@ -1464,6 +1540,24 @@ static int spansion_quad_enable(struct s
 	return 0;
 }
 
@ -856,7 +863,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
 {
 	int status;
-@@ -1610,9 +1699,25 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1610,9 +1704,25 @@ int spi_nor_scan(struct spi_nor *nor, co
 		write_sr(nor, 0);
 		spi_nor_wait_till_ready(nor);
 	}
@ -882,7 +889,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	mtd->priv = nor;
 	mtd->type = MTD_NORFLASH;
 	mtd->writesize = 1;
-@@ -1646,6 +1751,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1646,6 +1756,8 @@ int spi_nor_scan(struct spi_nor *nor, co
 		nor->flags |= SNOR_F_USE_FSR;
 	if (info->flags & SPI_NOR_HAS_TB)
 		nor->flags |= SNOR_F_HAS_SR_TB;
@ -891,7 +898,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
 	/* prefer "small sector" erase if possible */
-@@ -1685,9 +1792,15 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1685,9 +1797,15 @@ int spi_nor_scan(struct spi_nor *nor, co
 	/* Some devices cannot do fast-read, no matter what DT tells us */
 	if (info->flags & SPI_NOR_NO_FR)
 		nor->flash_read = SPI_NOR_NORMAL;
@ -910,7 +917,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 		ret = set_quad_mode(nor, info);
 		if (ret) {
 			dev_err(dev, "quad mode not supported\n");
-@@ -1700,6 +1813,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1700,6 +1818,9 @@ int spi_nor_scan(struct spi_nor *nor, co
 
 	/* Default commands */
 	switch (nor->flash_read) {
--- a/target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch
--- a/target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch
@ -1,7 +1,7 @@
-From 5fcb42fbd224e1103bacbae4785745842cfd6304 Mon Sep 17 00:00:00 2001
+From b2ee6e29bad31facbbf5ac1ce98235ac163d9fa9 Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:00:43 +0800
-Subject: [PATCH 08/30] pci: support layerscape
+Date: Thu, 5 Jul 2018 16:26:47 +0800
+Subject: [PATCH 08/32] pci: support layerscape

 This is an integrated patch for layerscape pcie support.

@ -15,19 +15,19 @@ Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
 Signed-off-by: Christoph Hellwig <hch@lst.de>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/irqchip/irq-ls-scfg-msi.c            | 257 +++++++--
+ drivers/irqchip/irq-ls-scfg-msi.c            | 257 ++++++-
 drivers/pci/host/Makefile                    |   2 +-
- drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++++++++++
- drivers/pci/host/pci-layerscape-ep.c         | 309 +++++++++++
- drivers/pci/host/pci-layerscape-ep.h         | 115 ++++
+ drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++
+ drivers/pci/host/pci-layerscape-ep.c         | 309 ++++++++
+ drivers/pci/host/pci-layerscape-ep.h         | 115 +++
 drivers/pci/host/pci-layerscape.c            |  48 +-
 drivers/pci/host/pcie-designware.c           |   6 +
 drivers/pci/host/pcie-designware.h           |   1 +
 drivers/pci/pci.c                            |   2 +-
- drivers/pci/pcie/portdrv_core.c              | 181 +++----
- drivers/pci/quirks.c                         |   8 +
+ drivers/pci/pcie/portdrv_core.c              | 181 ++---
+ drivers/pci/quirks.c                         |  15 +
 include/linux/pci.h                          |   1 +
- 12 files changed, 1539 insertions(+), 149 deletions(-)
+ 12 files changed, 1546 insertions(+), 149 deletions(-)
 create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
 create mode 100644 drivers/pci/host/pci-layerscape-ep.c
 create mode 100644 drivers/pci/host/pci-layerscape-ep.h
@ -2060,7 +2060,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	}
 --- a/drivers/pci/quirks.c
 +++ b/drivers/pci/quirks.c
-@@ -4679,3 +4679,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
+@@ -3329,6 +3329,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
+ 
+/*
+ * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
+ * bus reset. Link state of device does not comes UP and so config space
+ * never accessible again.
+ */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
+
+ static void quirk_no_pm_reset(struct pci_dev *dev)
+ {
+ 	/*
+@@ -4679,3 +4686,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
--- a/target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch
+++ b/target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch
--- a/target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch
--- a/target/linux/layerscape/patches-4.9/706-fsl_ppfe-support-layercape.patch
+++ b/target/linux/layerscape/patches-4.9/706-fsl_ppfe-support-layercape.patch
@ -1,48 +1,48 @@
-From 79fb41b6040d00d3bdfca9eb70a7848441eb7447 Mon Sep 17 00:00:00 2001
+From 50fb2f2e93aeae0baed156eb4794a2f358376b77 Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:14:12 +0800
-Subject: [PATCH] fsl_ppfe: support layercape
+Date: Thu, 5 Jul 2018 17:19:20 +0800
+Subject: [PATCH 12/32] fsl_ppfe: support layercape

 This is an integrated patch for layerscape pfe support.

 Calvin Johnson <calvin.johnson@nxp.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/staging/fsl_ppfe/Kconfig                   |   20 +
- drivers/staging/fsl_ppfe/Makefile                  |   19 +
- drivers/staging/fsl_ppfe/TODO                      |    2 +
- drivers/staging/fsl_ppfe/include/pfe/cbus.h        |   78 +
- drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h    |   55 +
- .../staging/fsl_ppfe/include/pfe/cbus/class_csr.h  |  289 +++
- .../staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h  |  242 ++
- drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h    |   86 +
- drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h    |  100 +
- .../staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h  |   50 +
- .../staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h    |  168 ++
- .../staging/fsl_ppfe/include/pfe/cbus/util_csr.h   |   61 +
- drivers/staging/fsl_ppfe/include/pfe/pfe.h         |  372 +++
- drivers/staging/fsl_ppfe/pfe_ctrl.c                |  238 ++
- drivers/staging/fsl_ppfe/pfe_ctrl.h                |  112 +
- drivers/staging/fsl_ppfe/pfe_debugfs.c             |  111 +
- drivers/staging/fsl_ppfe/pfe_debugfs.h             |   25 +
- drivers/staging/fsl_ppfe/pfe_eth.c                 | 2474 ++++++++++++++++++++
- drivers/staging/fsl_ppfe/pfe_eth.h                 |  184 ++
- drivers/staging/fsl_ppfe/pfe_firmware.c            |  314 +++
- drivers/staging/fsl_ppfe/pfe_firmware.h            |   32 +
- drivers/staging/fsl_ppfe/pfe_hal.c                 | 1516 ++++++++++++
- drivers/staging/fsl_ppfe/pfe_hif.c                 | 1072 +++++++++
- drivers/staging/fsl_ppfe/pfe_hif.h                 |  211 ++
- drivers/staging/fsl_ppfe/pfe_hif_lib.c             |  637 +++++
- drivers/staging/fsl_ppfe/pfe_hif_lib.h             |  240 ++
- drivers/staging/fsl_ppfe/pfe_hw.c                  |  176 ++
- drivers/staging/fsl_ppfe/pfe_hw.h                  |   27 +
- drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c    |  385 +++
- drivers/staging/fsl_ppfe/pfe_mod.c                 |  141 ++
- drivers/staging/fsl_ppfe/pfe_mod.h                 |  112 +
- drivers/staging/fsl_ppfe/pfe_perfmon.h             |   38 +
- drivers/staging/fsl_ppfe/pfe_sysfs.c               |  818 +++++++
- drivers/staging/fsl_ppfe/pfe_sysfs.h               |   29 +
- 34 files changed, 10434 insertions(+)
+ drivers/staging/fsl_ppfe/Kconfig              |   20 +
+ drivers/staging/fsl_ppfe/Makefile             |   19 +
+ drivers/staging/fsl_ppfe/TODO                 |    2 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus.h   |   78 +
+ .../staging/fsl_ppfe/include/pfe/cbus/bmu.h   |   55 +
+ .../fsl_ppfe/include/pfe/cbus/class_csr.h     |  289 ++
+ .../fsl_ppfe/include/pfe/cbus/emac_mtip.h     |  242 ++
+ .../staging/fsl_ppfe/include/pfe/cbus/gpi.h   |   86 +
+ .../staging/fsl_ppfe/include/pfe/cbus/hif.h   |  100 +
+ .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h     |   50 +
+ .../fsl_ppfe/include/pfe/cbus/tmu_csr.h       |  168 ++
+ .../fsl_ppfe/include/pfe/cbus/util_csr.h      |   61 +
+ drivers/staging/fsl_ppfe/include/pfe/pfe.h    |  372 +++
+ drivers/staging/fsl_ppfe/pfe_ctrl.c           |  238 ++
+ drivers/staging/fsl_ppfe/pfe_ctrl.h           |  112 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.c        |  111 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.h        |   25 +
+ drivers/staging/fsl_ppfe/pfe_eth.c            | 2491 +++++++++++++++++
+ drivers/staging/fsl_ppfe/pfe_eth.h            |  184 ++
+ drivers/staging/fsl_ppfe/pfe_firmware.c       |  314 +++
+ drivers/staging/fsl_ppfe/pfe_firmware.h       |   32 +
+ drivers/staging/fsl_ppfe/pfe_hal.c            | 1516 ++++++++++
+ drivers/staging/fsl_ppfe/pfe_hif.c            | 1072 +++++++
+ drivers/staging/fsl_ppfe/pfe_hif.h            |  211 ++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.c        |  640 +++++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.h        |  241 ++
+ drivers/staging/fsl_ppfe/pfe_hw.c             |  176 ++
+ drivers/staging/fsl_ppfe/pfe_hw.h             |   27 +
+ .../staging/fsl_ppfe/pfe_ls1012a_platform.c   |  385 +++
+ drivers/staging/fsl_ppfe/pfe_mod.c            |  156 ++
+ drivers/staging/fsl_ppfe/pfe_mod.h            |  114 +
+ drivers/staging/fsl_ppfe/pfe_perfmon.h        |   38 +
+ drivers/staging/fsl_ppfe/pfe_sysfs.c          |  818 ++++++
+ drivers/staging/fsl_ppfe/pfe_sysfs.h          |   29 +
+ 34 files changed, 10472 insertions(+)
 create mode 100644 drivers/staging/fsl_ppfe/Kconfig
 create mode 100644 drivers/staging/fsl_ppfe/Makefile
 create mode 100644 drivers/staging/fsl_ppfe/TODO
@ -2159,7 +2159,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#endif /* _PFE_DEBUGFS_H_ */
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_eth.c
-@@ -0,0 +1,2474 @@
+@@ -0,0 +1,2491 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@ -4457,6 +4457,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		goto err0;
 +	}
 +
+	if (us)
+		emac_txq_cnt = EMAC_TXQ_CNT;
 +	/* Create an ethernet device instance */
 +	ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt);
 +
@ -4503,6 +4505,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		}
 +	}
 +
+	if (us)
+		goto phy_init;
+
 +	ndev->mtu = 1500;
 +
 +	/* Set MTU limits */
@ -4542,6 +4547,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		netdev_err(ndev, "register_netdev() failed\n");
 +		goto err3;
 +	}
+
+phy_init:
 +	device_init_wakeup(&ndev->dev, WAKE_MAGIC);
 +
 +	if (!(priv->einfo->phy_flags & GEMAC_NO_PHY)) {
@ -4553,6 +4560,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		}
 +	}
 +
+	if (us) {
+		if (priv->phydev)
+			phy_start(priv->phydev);
+		return 0;
+	}
+
 +	netif_carrier_on(ndev);
 +
 +	/* Create all the sysfs files */
@ -4564,6 +4577,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +	return 0;
 +err4:
+	if (us)
+		goto err3;
 +	unregister_netdev(ndev);
 +err3:
 +	pfe_eth_mdio_exit(priv->mii_bus);
@ -4610,13 +4625,15 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +{
 +	netif_info(priv, probe, priv->ndev, "%s\n", __func__);
 +
-+	pfe_eth_sysfs_exit(priv->ndev);
-+
-+	unregister_netdev(priv->ndev);
+	if (!us)
+		pfe_eth_sysfs_exit(priv->ndev);
 +
 +	if (!(priv->einfo->phy_flags & GEMAC_NO_PHY))
 +		pfe_phy_exit(priv->ndev);
 +
+	if (!us)
+		unregister_netdev(priv->ndev);
+
 +	if (priv->mii_bus)
 +		pfe_eth_mdio_exit(priv->mii_bus);
 +
@ -7983,7 +8000,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#endif /* _PFE_HIF_H_ */
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c
-@@ -0,0 +1,637 @@
+@@ -0,0 +1,640 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@ -8421,6 +8438,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;
 +
 +			if (size) {
+				size += PFE_PARSE_INFO_SIZE;
 +				*len = CL_DESC_BUF_LEN(desc->ctrl) -
 +						PFE_PKT_HEADER_SZ - size;
 +				*ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ
@ -8428,8 +8446,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +				*priv_data = desc->data + PFE_PKT_HEADER_SZ;
 +			} else {
 +				*len = CL_DESC_BUF_LEN(desc->ctrl) -
-+						PFE_PKT_HEADER_SZ;
-+				*ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ;
+				       PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE;
+				*ofst = pfe_pkt_headroom
+					+ PFE_PKT_HEADER_SZ
+					+ PFE_PARSE_INFO_SIZE;
 +				*priv_data = NULL;
 +			}
 +
@ -8623,7 +8643,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
-@@ -0,0 +1,240 @@
+@@ -0,0 +1,241 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@ -8649,6 +8669,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +#define HIF_CL_REQ_TIMEOUT	10
 +#define GFP_DMA_PFE 0
+#define PFE_PARSE_INFO_SIZE	16
 +
 +enum {
 +	REQUEST_CL_REGISTER = 0,
@ -8772,7 +8793,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#define PFE_BUF_SIZE		2048
 +#define PFE_PKT_HEADROOM	128
 +
-+#define SKB_SHARED_INFO_SIZE   (sizeof(struct skb_shared_info))
+#define SKB_SHARED_INFO_SIZE   SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
 +#define PFE_PKT_SIZE		(PFE_BUF_SIZE - PFE_PKT_HEADROOM \
 +				 - SKB_SHARED_INFO_SIZE)
 +#define MAX_L2_HDR_SIZE		14	/* Not correct for VLAN/PPPoE */
@ -9463,7 +9484,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +MODULE_AUTHOR("NXP DNCPE");
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_mod.c
-@@ -0,0 +1,141 @@
+@@ -0,0 +1,156 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@ -9485,6 +9506,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#include <linux/dma-mapping.h>
 +#include "pfe_mod.h"
 +
+unsigned int us;
+module_param(us, uint, 0444);
+MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n"
+			"1: module enabled for userspace networking\n");
 +struct pfe *pfe;
 +
 +/*
@ -9522,6 +9547,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	if (rc < 0)
 +		goto err_hw;
 +
+	if (us)
+		goto firmware_init;
+
 +	rc = pfe_hif_lib_init(pfe);
 +	if (rc < 0)
 +		goto err_hif_lib;
@ -9530,6 +9558,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	if (rc < 0)
 +		goto err_hif;
 +
+firmware_init:
 +	rc = pfe_firmware_init(pfe);
 +	if (rc < 0)
 +		goto err_firmware;
@ -9565,6 +9594,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	pfe_firmware_exit(pfe);
 +
 +err_firmware:
+	if (us)
+		goto err_hif_lib;
+
 +	pfe_hif_exit(pfe);
 +
 +err_hif:
@ -9597,17 +9629,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#endif
 +	pfe_firmware_exit(pfe);
 +
+	if (us)
+		goto hw_exit;
+
 +	pfe_hif_exit(pfe);
 +
 +	pfe_hif_lib_exit(pfe);
 +
+hw_exit:
 +	pfe_hw_exit(pfe);
 +
 +	return 0;
 +}
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_mod.h
-@@ -0,0 +1,112 @@
+@@ -0,0 +1,114 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@ -9632,6 +9668,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#include <linux/device.h>
 +#include <linux/elf.h>
 +
+extern unsigned int us;
+
 +struct pfe;
 +
 +#include "pfe_hw.h"
--- a/target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch
@ -1,20 +1,111 @@
-From b018e44a68dc2f4df819ae194e39e07313841dad Mon Sep 17 00:00:00 2001
+From d78d78ccbaded757e8bea0d13c4120518bdd4660 Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:27:58 +0800
-Subject: [PATCH 15/30] cpufreq: support layerscape
+Date: Thu, 5 Jul 2018 17:21:38 +0800
+Subject: [PATCH 15/32] cpufreq: support layerscape

 This is an integrated patch for layerscape pm support.

 Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/cpufreq/Kconfig         |   2 +-
- drivers/cpufreq/qoriq-cpufreq.c | 176 +++++++++++++++-------------------------
- drivers/firmware/psci.c         |  12 ++-
- drivers/soc/fsl/rcpm.c          | 158 ++++++++++++++++++++++++++++++++++++
- 4 files changed, 235 insertions(+), 113 deletions(-)
+ .../devicetree/bindings/powerpc/fsl/pmc.txt   |  59 ++--
+ drivers/cpufreq/Kconfig                       |   2 +-
+ drivers/cpufreq/qoriq-cpufreq.c               | 176 +++++------
+ drivers/firmware/psci.c                       |  12 +-
+ drivers/soc/fsl/rcpm.c                        | 158 ++++++++++
+ drivers/soc/fsl/sleep_fsm.c                   | 279 ++++++++++++++++++
+ drivers/soc/fsl/sleep_fsm.h                   | 130 ++++++++
+ 7 files changed, 678 insertions(+), 138 deletions(-)
 create mode 100644 drivers/soc/fsl/rcpm.c
+ create mode 100644 drivers/soc/fsl/sleep_fsm.c
+ create mode 100644 drivers/soc/fsl/sleep_fsm.h

+--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
+@@ -9,15 +9,20 @@ Properties:
+ 
+   "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
+   compatible.  "fsl,mpc8536-pmc" should also be listed for any chip
+-  whose PMC is compatible, and implies deep-sleep capability.
+  whose PMC is compatible, and implies deep-sleep capability and
+  wake on user defined packet(wakeup on ARP).
+
+  "fsl,p1022-pmc" should be listed for any chip whose PMC is
+  compatible, and implies lossless Ethernet capability during sleep.
+ 
+   "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
+   compatible; all statements below that apply to "fsl,mpc8548-pmc" also
+   apply to "fsl,mpc8641d-pmc".
+ 
+   Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
+-  bit assignments are indicated via the sleep specifier in each device's
+-  sleep property.
+  bit assignments are indicated via the clock nodes.  Device which has a
+  controllable clock source should have a "fsl,pmc-handle" property pointing
+  to the clock node.
+ 
+ - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
+   is the PMC block, and the second resource is the Clock Configuration
+@@ -33,31 +38,35 @@ Properties:
+   this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
+   a wakeup source from deep sleep.
+ 
+-Sleep specifiers:
+-
+-  fsl,mpc8349-pmc: Sleep specifiers consist of one cell.  For each bit
+-  that is set in the cell, the corresponding bit in SCCR will be saved
+-  and cleared on suspend, and restored on resume.  This sleep controller
+-  supports disabling and resuming devices at any time.
+-
+-  fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
+-  which will be ORed into PMCDR upon suspend, and cleared from PMCDR
+-  upon resume.  The first two cells are as described for fsl,mpc8578-pmc.
+-  This sleep controller only supports disabling devices during system
+-  sleep, or permanently.
+-
+-  fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
+-  first of which will be ORed into DEVDISR (and the second into
+-  DEVDISR2, if present -- this cell should be zero or absent if the
+-  hardware does not have DEVDISR2) upon a request for permanent device
+-  disabling.  This sleep controller does not support configuring devices
+-  to disable during system sleep (unless supported by another compatible
+-  match), or dynamically.
+Clock nodes:
+The clock nodes are to describe the masks in PM controller registers for each
+soc clock.
+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
+  ORed into PMCDR before suspend if the device using this clock is the wake-up
+  source and need to be running during low power mode; clear the mask if
+  otherwise.
+
+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
+  bit specified by the mask in SCCR will be saved and cleared on suspend, and
+  restored on resume.
+
+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
+  DEVDISR2 register.  For compatible devices, the mask will be ORed into DEVDISR
+  or DEVDISR2 when the clock should be permenently disabled.
+ 
+ Example:
+ 
+-	power@b00 {
+-		compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
+-		reg = <0xb00 0x100 0xa00 0x100>;
+-		interrupts = <80 8>;
+	power@e0070 {
+		compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
+		reg = <0xe0070 0x20>;
+
+		etsec1_clk: soc-clk@24 {
+			fsl,pmcdr-mask = <0x00000080>;
+		};
+		etsec2_clk: soc-clk@25 {
+			fsl,pmcdr-mask = <0x00000040>;
+		};
+		etsec3_clk: soc-clk@26 {
+			fsl,pmcdr-mask = <0x00000020>;
+		};
+ 	};
 --- a/drivers/cpufreq/Kconfig
 +++ b/drivers/cpufreq/Kconfig
@@ -334,7 +334,7 @@ endif
@ -522,3 +613,418 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +}
 +
 +subsys_initcall(layerscape_rcpm_init);
+--- /dev/null
+++ b/drivers/soc/fsl/sleep_fsm.c
+@@ -0,0 +1,279 @@
+/*
+ * deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2018 NXP
+ *
+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
+ *         Chenhui Zhao <chenhui.zhao@freescale.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *	 notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the above-listed copyright holders nor the
+ *	 names of any contributors may be used to endorse or promote products
+ *	 derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+	/* EPGCR (Event Processor Global Control Register) */
+	{EPGCR, 0},
+	/* EPECR (Event Processor Event Control Registers) */
+	{EPECR0 + EPECR_STRIDE * 0, 0},
+	{EPECR0 + EPECR_STRIDE * 1, 0},
+	{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+	{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+	{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+	{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+	{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+	{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+	{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+	{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+	{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+	{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
+	/*
+	 * EPEVTCR (Event Processor EVT Pin Control Registers)
+	 * SCU8 triger EVT2, and SCU11 triger EVT9
+	 */
+	{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+	/* EPCMPR (Event Processor Counter Compare Registers) */
+	{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+	{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+	/* EPCCR (Event Processor Counter Control Registers) */
+	{EPCCR0 + EPCCR_STRIDE * 0, 0},
+	{EPCCR0 + EPCCR_STRIDE * 1, 0},
+	{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 3, 0},
+	{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 6, 0},
+	{EPCCR0 + EPCCR_STRIDE * 7, 0},
+	{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 13, 0},
+	{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+	/* EPSMCR (Event Processor SCU Mux Control Registers) */
+	{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+	{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+	{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+	{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+	{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+	{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+	{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+	{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+	{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+	{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+	{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+	{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+	/* EPACR (Event Processor Action Control Registers) */
+	{EPACR0 + EPACR_STRIDE * 0, 0},
+	{EPACR0 + EPACR_STRIDE * 1, 0},
+	{EPACR0 + EPACR_STRIDE * 2, 0},
+	{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+	{EPACR0 + EPACR_STRIDE * 4, 0},
+	{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+	{EPACR0 + EPACR_STRIDE * 6, 0},
+	{EPACR0 + EPACR_STRIDE * 7, 0},
+	{EPACR0 + EPACR_STRIDE * 8, 0},
+	{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+	{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+	{EPACR0 + EPACR_STRIDE * 11, 0},
+	{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+	{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+	{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+	{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+	/* EPIMCR (Event Processor Input Mux Control Registers) */
+	{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+	/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+	{EPXTRIGCR, 0x0000FFDF},
+	/* end */
+	{FSM_END_FLAG, 0},
+};
+
+struct fsm_reg_vals npc_default_val[] = {
+	/* NPC triggered Memory-Mapped Access Registers */
+	{NCR, 0x80000000},
+	{MCCR1, 0},
+	{MCSR1, 0},
+	{MMAR1LO, 0},
+	{MMAR1HI, 0},
+	{MMDR1, 0},
+	{MCSR2, 0},
+	{MMAR2LO, 0},
+	{MMAR2HI, 0},
+	{MMDR2, 0},
+	{MCSR3, 0x80000000},
+	{MMAR3LO, 0x000E2130},
+	{MMAR3HI, 0x00030000},
+	{MMDR3, 0x00020000},
+	/* end */
+	{FSM_END_FLAG, 0},
+};
+
+/**
+ * fsl_fsm_setup - Configure EPU's FSM registers
+ * @base: the base address of registers
+ * @val: Pointer to address-value pairs for FSM registers
+ */
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+	struct fsm_reg_vals *data = val;
+
+	WARN_ON(!base || !data);
+	while (data->offset != FSM_END_FLAG) {
+		iowrite32be(data->value, base + data->offset);
+		data++;
+	}
+}
+
+void fsl_epu_setup_default(void __iomem *epu_base)
+{
+	fsl_fsm_setup(epu_base, epu_default_val);
+}
+
+void fsl_npc_setup_default(void __iomem *npc_base)
+{
+	fsl_fsm_setup(npc_base, npc_default_val);
+}
+
+void fsl_epu_clean_default(void __iomem *epu_base)
+{
+	u32 offset;
+
+	/* follow the exact sequence to clear the registers */
+	/* Clear EPACRn */
+	for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPEVTCRn */
+	for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPGCR */
+	iowrite32be(0, epu_base + EPGCR);
+
+	/* Clear EPSMCRn */
+	for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPCCRn */
+	for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPCMPRn */
+	for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPCTRn */
+	for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPIMCRn */
+	for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+
+	/* Clear EPXTRIGCRn */
+	iowrite32be(0, epu_base + EPXTRIGCR);
+
+	/* Clear EPECRn */
+	for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+		iowrite32be(0, epu_base + offset);
+}
+--- /dev/null
+++ b/drivers/soc/fsl/sleep_fsm.h
+@@ -0,0 +1,130 @@
+/*
+ * deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *	 notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the above-listed copyright holders nor the
+ *	 names of any contributors may be used to endorse or promote products
+ *	 derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B	4
+#define FSL_STRIDE_8B	8
+
+/* End flag */
+#define FSM_END_FLAG		0xFFFFFFFFUL
+
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET	0x00022000
+#define EPU_BLOCK_OFFSET	0x00000000
+#define NPC_BLOCK_OFFSET	0x00001000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR		0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0	0x050
+#define EPEVTCR9	0x074
+#define EPEVTCR_STRIDE	FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR	0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0		0x100
+#define EPIMCR31	0x17C
+#define EPIMCR_STRIDE	FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0		0x200
+#define EPSMCR15	0x278
+#define EPSMCR_STRIDE	FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0		0x300
+#define EPECR15		0x33C
+#define EPECR_STRIDE	FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0		0x400
+#define EPACR15		0x43C
+#define EPACR_STRIDE	FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0		0x800
+#define EPCCR15		0x83C
+#define EPCCR31		0x87C
+#define EPCCR_STRIDE	FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0		0x900
+#define EPCMPR15	0x93C
+#define EPCMPR31	0x97C
+#define EPCMPR_STRIDE	FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0		0xA00
+#define EPCTR31		0xA7C
+#define EPCTR_STRIDE	FSL_STRIDE_4B
+
+/* NPC triggered Memory-Mapped Access Registers */
+#define NCR		0x000
+#define MCCR1		0x0CC
+#define MCSR1		0x0D0
+#define MMAR1LO		0x0D4
+#define MMAR1HI		0x0D8
+#define MMDR1		0x0DC
+#define MCSR2		0x0E0
+#define MMAR2LO		0x0E4
+#define MMAR2HI		0x0E8
+#define MMDR2		0x0EC
+#define MCSR3		0x0F0
+#define MMAR3LO		0x0F4
+#define MMAR3HI		0x0F8
+#define MMDR3		0x0FC
+
+/* RCPM Core State Action Control Register 0 */
+#define CSTTACR0	0xB00
+
+/* RCPM Core Group 1 Configuration Register 0 */
+#define CG1CR0		0x31C
+
+struct fsm_reg_vals {
+	u32 offset;
+	u32 value;
+};
+
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
+void fsl_epu_setup_default(void __iomem *epu_base);
+void fsl_npc_setup_default(void __iomem *npc_base);
+void fsl_epu_clean_default(void __iomem *epu_base);
+
+#endif /* _FSL_SLEEP_FSM_H */
--- a/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch
--- a/target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch
@ -1,7 +1,7 @@
-From 515d590e3d5313110faa4f2c86f7784d9b070fa9 Mon Sep 17 00:00:00 2001
+From d3d537ebe9884e7d945ab74bb02312d0c2c9b08d Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:30:59 +0800
-Subject: [PATCH 17/30] dma: support layerscape
+Date: Thu, 5 Jul 2018 17:32:53 +0800
+Subject: [PATCH 17/32] dma: support layerscape

 This is an integrated patch for layerscape dma support.

@ -10,16 +10,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
 drivers/dma/Kconfig                     |   31 +
 drivers/dma/Makefile                    |    3 +
- drivers/dma/caam_dma.c                  |  563 ++++++++++++++
+ drivers/dma/caam_dma.c                  |  563 ++++++++++
 drivers/dma/dpaa2-qdma/Kconfig          |    8 +
 drivers/dma/dpaa2-qdma/Makefile         |    8 +
- drivers/dma/dpaa2-qdma/dpaa2-qdma.c     |  986 ++++++++++++++++++++++++
- drivers/dma/dpaa2-qdma/dpaa2-qdma.h     |  262 +++++++
- drivers/dma/dpaa2-qdma/dpdmai.c         |  454 +++++++++++
- drivers/dma/dpaa2-qdma/fsl_dpdmai.h     |  521 +++++++++++++
- drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h |  222 ++++++
- drivers/dma/fsl-qdma.c                  | 1243 +++++++++++++++++++++++++++++++
- 11 files changed, 4301 insertions(+)
+ drivers/dma/dpaa2-qdma/dpaa2-qdma.c     |  940 +++++++++++++++++
+ drivers/dma/dpaa2-qdma/dpaa2-qdma.h     |  227 +++++
+ drivers/dma/dpaa2-qdma/dpdmai.c         |  515 ++++++++++
+ drivers/dma/dpaa2-qdma/fsl_dpdmai.h     |  521 ++++++++++
+ drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h |  222 ++++
+ drivers/dma/fsl-qdma.c                  | 1243 +++++++++++++++++++++++
+ 11 files changed, 4281 insertions(+)
 create mode 100644 drivers/dma/caam_dma.c
 create mode 100644 drivers/dma/dpaa2-qdma/Kconfig
 create mode 100644 drivers/dma/dpaa2-qdma/Makefile
@ -686,7 +686,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +fsl-dpaa2-qdma-objs    := dpaa2-qdma.o dpdmai.o
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/dpaa2-qdma.c
-@@ -0,0 +1,986 @@
+@@ -0,0 +1,940 @@
 +/*
 + * drivers/dma/dpaa2-qdma/dpaa2-qdma.c
 + *
@ -723,7 +723,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +#include "../virt-dma.h"
 +
-+#include "../../../drivers/staging/fsl-mc/include/mc.h"
+#include <linux/fsl/mc.h>
 +#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h"
 +#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
 +#include "fsl_dpdmai_cmd.h"
@ -786,10 +786,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		comp_temp->fl_bus_addr = comp_temp->fd_bus_addr +
 +					sizeof(struct dpaa2_fd);
 +		comp_temp->desc_virt_addr =
-+			(void *)((struct dpaa2_frame_list *)
+			(void *)((struct dpaa2_fl_entry *)
 +				comp_temp->fl_virt_addr + 3);
 +		comp_temp->desc_bus_addr = comp_temp->fl_bus_addr +
-+				sizeof(struct dpaa2_frame_list) * 3;
+				sizeof(struct dpaa2_fl_entry) * 3;
 +
 +		comp_temp->qchan = dpaa2_chan;
 +		comp_temp->sg_blk_num = 0;
@ -816,19 +816,19 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	memset(fd, 0, sizeof(struct dpaa2_fd));
 +
 +	/* fd populated */
-+	fd->simple.addr = dpaa2_comp->fl_bus_addr;
+	dpaa2_fd_set_addr(fd, dpaa2_comp->fl_bus_addr);
 +	/* Bypass memory translation, Frame list format, short length disable */
 +	/* we need to disable BMT if fsl-mc use iova addr */
 +	if (smmu_disable)
-+		fd->simple.bpid = QMAN_FD_BMT_ENABLE;
-+	fd->simple.format_offset = QMAN_FD_FMT_ENABLE | QMAN_FD_SL_DISABLE;
+		dpaa2_fd_set_bpid(fd, QMAN_FD_BMT_ENABLE);
+	dpaa2_fd_set_format(fd, QMAN_FD_FMT_ENABLE | QMAN_FD_SL_DISABLE);
 +
-+	fd->simple.frc = format | QDMA_SER_CTX;
+	dpaa2_fd_set_frc(fd, format | QDMA_SER_CTX);
 +}
 +
 +/* first frame list for descriptor buffer */
 +static void dpaa2_qdma_populate_first_framel(
-+		struct dpaa2_frame_list *f_list,
+		struct dpaa2_fl_entry *f_list,
 +		struct dpaa2_qdma_comp *dpaa2_comp)
 +{
 +	struct dpaa2_qdma_sd_d *sdd;
@ -836,48 +836,45 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	sdd = (struct dpaa2_qdma_sd_d *)dpaa2_comp->desc_virt_addr;
 +	memset(sdd, 0, 2 * (sizeof(*sdd)));
 +	/* source and destination descriptor */
-+	sdd->cmd = QDMA_SD_CMD_RDTTYPE_COHERENT; /* source descriptor CMD */
+	sdd->cmd = cpu_to_le32(QDMA_SD_CMD_RDTTYPE_COHERENT); /* source descriptor CMD */
 +	sdd++;
-+	sdd->cmd = QDMA_DD_CMD_WRTTYPE_COHERENT; /* dest descriptor CMD */
+	sdd->cmd = cpu_to_le32(QDMA_DD_CMD_WRTTYPE_COHERENT); /* dest descriptor CMD */
 +
-+	memset(f_list, 0, sizeof(struct dpaa2_frame_list));
+	memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
 +	/* first frame list to source descriptor */
-+	f_list->addr_lo = dpaa2_comp->desc_bus_addr;
-+	f_list->addr_hi = (dpaa2_comp->desc_bus_addr >> 32);
-+	f_list->data_len.data_len_sl0 = 0x20; /* source/destination desc len */
-+	f_list->fmt = QDMA_FL_FMT_SBF; /* single buffer frame */
+
+	dpaa2_fl_set_addr(f_list, dpaa2_comp->desc_bus_addr);
+	dpaa2_fl_set_len(f_list, 0x20);
+	dpaa2_fl_set_format(f_list, QDMA_FL_FMT_SBF | QDMA_FL_SL_LONG);
+
 +	if (smmu_disable)
-+		f_list->bmt = QDMA_FL_BMT_ENABLE; /* bypass memory translation */
-+	f_list->sl = QDMA_FL_SL_LONG; /* long length */
-+	f_list->f = 0; /* not the last frame list */
+		f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); /* bypass memory translation */
 +}
 +
 +/* source and destination frame list */
-+static void dpaa2_qdma_populate_frames(struct dpaa2_frame_list *f_list,
+static void dpaa2_qdma_populate_frames(struct dpaa2_fl_entry *f_list,
 +		dma_addr_t dst, dma_addr_t src, size_t len, uint8_t fmt)
 +{
 +	/* source frame list to source buffer */
-+	memset(f_list, 0, sizeof(struct dpaa2_frame_list));
-+	f_list->addr_lo = src;
-+	f_list->addr_hi = (src >> 32);
-+	f_list->data_len.data_len_sl0 = len;
-+	f_list->fmt = fmt; /* single buffer frame or scatter gather frame */
+	memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
+
+
+	dpaa2_fl_set_addr(f_list, src);
+	dpaa2_fl_set_len(f_list, len);
+	dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG)); /* single buffer frame or scatter gather frame */
 +	if (smmu_disable)
-+		f_list->bmt = QDMA_FL_BMT_ENABLE; /* bypass memory translation */
-+	f_list->sl = QDMA_FL_SL_LONG; /* long length */
-+	f_list->f = 0; /* not the last frame list */
+		f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); /* bypass memory translation */
 +
 +	f_list++;
 +	/* destination frame list to destination buffer */
-+	memset(f_list, 0, sizeof(struct dpaa2_frame_list));
-+	f_list->addr_lo = dst;
-+	f_list->addr_hi = (dst >> 32);
-+	f_list->data_len.data_len_sl0 = len;
-+	f_list->fmt = fmt; /* single buffer frame or scatter gather frame */
+	memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
+
+	dpaa2_fl_set_addr(f_list, dst);
+	dpaa2_fl_set_len(f_list, len);
+	dpaa2_fl_set_format(f_list, (fmt | QDMA_FL_SL_LONG));
+	dpaa2_fl_set_final(f_list, QDMA_FL_F); /* single buffer frame or scatter gather frame */
 +	if (smmu_disable)
-+		f_list->bmt = QDMA_FL_BMT_ENABLE; /* bypass memory translation */
-+	f_list->sl = QDMA_FL_SL_LONG; /* long length */
-+	f_list->f = QDMA_FL_F; /* Final bit: 1, for last frame list */
+		f_list->bpid = cpu_to_le16(QDMA_FL_BMT_ENABLE); /* bypass memory translation */
 +}
 +
 +static struct dma_async_tx_descriptor *dpaa2_qdma_prep_memcpy(
@ -886,7 +883,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +{
 +	struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
 +	struct dpaa2_qdma_comp *dpaa2_comp;
-+	struct dpaa2_frame_list *f_list;
+	struct dpaa2_fl_entry *f_list;
 +	uint32_t format;
 +
 +	dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan);
@ -899,7 +896,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	/* populate Frame descriptor */
 +	dpaa2_qdma_populate_fd(format, dpaa2_comp);
 +
-+	f_list = (struct dpaa2_frame_list *)dpaa2_comp->fl_virt_addr;
+	f_list = (struct dpaa2_fl_entry *)dpaa2_comp->fl_virt_addr;
 +
 +#ifdef LONG_FORMAT
 +	/* first frame list for descriptor buffer (logn format) */
@ -1062,48 +1059,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	return total_len;
 +}
 +
-+static struct dma_async_tx_descriptor *dpaa2_qdma_prep_sg(
-+		struct dma_chan *chan,
-+		struct scatterlist *dst_sg, u32 dst_nents,
-+		struct scatterlist *src_sg, u32 src_nents,
-+		unsigned long flags)
-+{
-+	struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
-+	struct dpaa2_qdma_comp *dpaa2_comp;
-+	struct dpaa2_frame_list *f_list;
-+	struct device *dev = dpaa2_chan->qdma->priv->dev;
-+	uint32_t total_len = 0;
-+
-+	/* basic sanity checks */
-+	if (dst_nents == 0 || src_nents == 0)
-+		return NULL;
-+
-+	if (dst_sg == NULL || src_sg == NULL)
-+		return NULL;
-+
-+	/* get the descriptors required */
-+	dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan);
-+
-+	/* populate Frame descriptor */
-+	dpaa2_qdma_populate_fd(QDMA_FD_LONG_FORMAT, dpaa2_comp);
-+
-+	/* prepare Scatter gather entry for source and destination */
-+	total_len = dpaa2_qdma_populate_sg(dev, dpaa2_chan,
-+			dpaa2_comp, dst_sg, dst_nents, src_sg, src_nents);
-+
-+	f_list = (struct dpaa2_frame_list *)dpaa2_comp->fl_virt_addr;
-+	/* first frame list for descriptor buffer */
-+	dpaa2_qdma_populate_first_framel(f_list, dpaa2_comp);
-+	f_list++;
-+	/* prepare Scatter gather entry for source and destination */
-+	/* populate source and destination frame list table */
-+	dpaa2_qdma_populate_frames(f_list, dpaa2_comp->sge_dst_bus_addr,
-+			dpaa2_comp->sge_src_bus_addr,
-+			total_len, QDMA_FL_FMT_SGE);
-+
-+	return vchan_tx_prep(&dpaa2_chan->vchan, &dpaa2_comp->vdesc, flags);
-+}
-+
 +static enum dma_status dpaa2_qdma_tx_status(struct dma_chan *chan,
 +		dma_cookie_t cookie, struct dma_tx_state *txstate)
 +{
@ -1263,7 +1218,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +		/* obtain FD and process the error */
 +		fd = dpaa2_dq_fd(dq);
-+		status = fd->simple.ctrl & 0xff;
+
+		status = dpaa2_fd_get_ctrl(fd) & 0xff;
 +		if (status)
 +			dev_err(priv->dev, "FD error occurred\n");
 +		found = 0;
@ -1279,8 +1235,8 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +				fd_eq = (struct dpaa2_fd *)
 +					dpaa2_comp->fd_virt_addr;
 +
-+				if (fd_eq->simple.addr ==
-+					fd->simple.addr) {
+				if (le64_to_cpu(fd_eq->simple.addr) ==
+						le64_to_cpu(fd->simple.addr)) {
 +
 +					list_del(&dpaa2_comp->list);
 +					list_add_tail(&dpaa2_comp->list,
@ -1574,7 +1530,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	dma_cap_set(DMA_PRIVATE, dpaa2_qdma->dma_dev.cap_mask);
 +	dma_cap_set(DMA_SLAVE, dpaa2_qdma->dma_dev.cap_mask);
 +	dma_cap_set(DMA_MEMCPY, dpaa2_qdma->dma_dev.cap_mask);
-+	dma_cap_set(DMA_SG, dpaa2_qdma->dma_dev.cap_mask);
 +
 +	dpaa2_qdma->dma_dev.dev = dev;
 +	dpaa2_qdma->dma_dev.device_alloc_chan_resources
@ -1583,7 +1538,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		= dpaa2_qdma_free_chan_resources;
 +	dpaa2_qdma->dma_dev.device_tx_status = dpaa2_qdma_tx_status;
 +	dpaa2_qdma->dma_dev.device_prep_dma_memcpy = dpaa2_qdma_prep_memcpy;
-+	dpaa2_qdma->dma_dev.device_prep_dma_sg = dpaa2_qdma_prep_sg;
 +	dpaa2_qdma->dma_dev.device_issue_pending = dpaa2_qdma_issue_pending;
 +
 +	err = dma_async_device_register(&dpaa2_qdma->dma_dev);
@ -1675,7 +1629,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +MODULE_LICENSE("Dual BSD/GPL");
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/dpaa2-qdma.h
-@@ -0,0 +1,262 @@
+@@ -0,0 +1,227 @@
 +/* Copyright 2015 NXP Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@ -1777,7 +1731,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	} ctrl;
 +} __attribute__((__packed__));
 +
-+#define QMAN_FD_FMT_ENABLE (1 << 12) /* frame list table enable */
+#define QMAN_FD_FMT_ENABLE (1) /* frame list table enable */
 +#define QMAN_FD_BMT_ENABLE (1 << 15) /* bypass memory translation */
 +#define QMAN_FD_BMT_DISABLE (0 << 15) /* bypass memory translation */
 +#define QMAN_FD_SL_DISABLE (0 << 14) /* short lengthe disabled */
@ -1802,49 +1756,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#define QMAN_FD_CBMT_DISABLE (0 << 15) /* Flow Context: 64bit virtual address */
 +#define QMAN_FD_SC_DISABLE (0 << 27) /* stashing control */
 +
-+#define QDMA_FL_FMT_SBF 0x0	/* Single buffer frame */
+#define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */
 +#define QDMA_FL_FMT_SGE 0x2 /* Scatter gather frame */
-+#define QDMA_FL_BMT_ENABLE 0x1 /* enable bypass memory translation */
+#define QDMA_FL_BMT_ENABLE (0x1 << 15)/* enable bypass memory translation */
 +#define QDMA_FL_BMT_DISABLE 0x0 /* enable bypass memory translation */
-+#define QDMA_FL_SL_LONG 0x0 /* long length */
+#define QDMA_FL_SL_LONG (0x0 << 2)/* long length */
 +#define QDMA_FL_SL_SHORT 0x1 /* short length */
-+#define QDMA_FL_F 0x1 /* last frame list bit */
+#define QDMA_FL_F (0x1)/* last frame list bit */
 +/*Description of Frame list table structure*/
-+struct dpaa2_frame_list  {
-+	uint32_t addr_lo;	/* lower 32 bits of address */
-+	uint32_t addr_hi:17; /* upper 17 bits of address */
-+	uint32_t resrvd:15;
-+	union {
-+		uint32_t data_len_sl0; /* If SL=0, then data length is 32 */
-+		struct {
-+			uint32_t data_len:18; /* IF SL=1; length is 18bit */
-+			uint32_t resrvd:2;
-+			uint32_t mem:12; /* Valid only when SL=1 */
-+		} data_len_sl1;
-+	} data_len;
-+	/* word 4 */
-+	uint32_t bpid:14; /* Frame buffer pool ID */
-+	uint32_t ivp:1; /* Invalid Pool ID. */
-+	uint32_t bmt:1; /* Bypass Memory Translation */
-+	uint32_t offset:12; /* Frame offset */
-+	uint32_t fmt:2; /* Frame Format */
-+	uint32_t sl:1; /* Short Length */
-+	uint32_t f:1; /* Final bit */
-+
-+	uint32_t frc; /* Frame Context */
-+	/* word 6 */
-+	uint32_t err:8; /* Frame errors */
-+	uint32_t resrvd0:8;
-+	uint32_t asal:4; /* accelerator-specific annotation length */
-+	uint32_t resrvd1:1;
-+	uint32_t ptv2:1;
-+	uint32_t ptv1:1;
-+	uint32_t pta:1; /* pass-through annotation */
-+	uint32_t resrvd2:8;
-+
-+	uint32_t flc_lo; /* lower 32 bits fo flow context */
-+	uint32_t flc_hi; /* higher 32 bits fo flow context */
-+} __attribute__((__packed__));
 +
 +struct dpaa2_qdma_chan {
 +	struct virt_dma_chan		vchan;
@ -1931,7 +1850,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
 +#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
-+		sizeof(struct dpaa2_frame_list) * 3 + \
+		sizeof(struct dpaa2_fl_entry) * 3 + \
 +		sizeof(struct dpaa2_qdma_sd_d) * 2)
 +
 +/* qdma_sg_blk + 16 SGs */
@ -1940,7 +1859,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#endif /* __DPAA2_QDMA_H */
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/dpdmai.c
-@@ -0,0 +1,454 @@
+@@ -0,0 +1,515 @@
 +/* Copyright 2013-2015 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@ -1976,22 +1895,56 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#include <linux/io.h>
 +#include "fsl_dpdmai.h"
 +#include "fsl_dpdmai_cmd.h"
-+#include "../../../drivers/staging/fsl-mc/include/mc-sys.h"
-+#include "../../../drivers/staging/fsl-mc/include/mc-cmd.h"
+#include <linux/fsl/mc.h>
+
+struct dpdmai_cmd_open {
+	__le32 dpdmai_id;
+};
+
+struct dpdmai_rsp_get_attributes {
+	__le32 id;
+	u8 num_of_priorities;
+	u8 pad0[3];
+	__le16 major;
+	__le16 minor;
+};
+
+
+struct dpdmai_cmd_queue {
+	__le32 dest_id;
+	u8 priority;
+	u8 queue;
+	u8 dest_type;
+	u8 pad;
+	__le64 user_ctx;
+	union {
+		__le32 options;
+		__le32 fqid;
+	};
+};
+
+struct dpdmai_rsp_get_tx_queue {
+	__le64 pad;
+	__le32 fqid;
+};
+
 +
 +int dpdmai_open(struct fsl_mc_io *mc_io,
 +		uint32_t cmd_flags,
 +		int dpdmai_id,
 +		uint16_t *token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
+	struct dpdmai_cmd_open *cmd_params;
 +	int err;
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_OPEN,
 +					  cmd_flags,
 +					  0);
-+	DPDMAI_CMD_OPEN(cmd, dpdmai_id);
+
+	cmd_params = (struct dpdmai_cmd_open *)cmd.params;
+	cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id);
 +
 +	/* send command to mc*/
 +	err = mc_send_command(mc_io, &cmd);
@ -1999,8 +1952,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		return err;
 +
 +	/* retrieve response parameters */
-+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
-+
+	*token = mc_cmd_hdr_read_token(&cmd);
 +	return 0;
 +}
 +
@ -2008,7 +1960,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		 uint32_t cmd_flags,
 +		 uint16_t token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLOSE,
@ -2023,7 +1975,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		  const struct dpdmai_cfg *cfg,
 +		  uint16_t *token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
 +
 +	/* prepare command */
@ -2047,7 +1999,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		   uint32_t cmd_flags,
 +		   uint16_t token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DESTROY,
@ -2062,7 +2014,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		  uint32_t cmd_flags,
 +		  uint16_t token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_ENABLE,
@ -2077,7 +2029,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		   uint32_t cmd_flags,
 +		   uint16_t token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_DISABLE,
@ -2093,7 +2045,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		      uint16_t token,
 +		      int *en)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_IS_ENABLED,
@ -2115,7 +2067,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		 uint32_t cmd_flags,
 +		 uint16_t token)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_RESET,
@ -2133,7 +2085,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		   int *type,
 +		   struct dpdmai_irq_cfg	*irq_cfg)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
 +
 +	/* prepare command */
@ -2159,7 +2111,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		   uint8_t irq_index,
 +		   struct dpdmai_irq_cfg *irq_cfg)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ,
@ -2177,7 +2129,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			  uint8_t irq_index,
 +			  uint8_t *en)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
 +
 +	/* prepare command */
@ -2203,7 +2155,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			  uint8_t irq_index,
 +			  uint8_t en)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ_ENABLE,
@ -2221,7 +2173,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			uint8_t irq_index,
 +			uint32_t *mask)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
 +
 +	/* prepare command */
@ -2247,7 +2199,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			uint8_t irq_index,
 +			uint32_t mask)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_IRQ_MASK,
@ -2265,7 +2217,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			  uint8_t irq_index,
 +			  uint32_t *status)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
 +
 +	/* prepare command */
@ -2291,7 +2243,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			    uint8_t irq_index,
 +			    uint32_t status)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_CLEAR_IRQ_STATUS,
@ -2308,8 +2260,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			  uint16_t token,
 +			  struct dpdmai_attr *attr)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
 +	int err;
+	struct dpdmai_rsp_get_attributes *rsp_params;
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_ATTR,
@ -2322,7 +2275,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		return err;
 +
 +	/* retrieve response parameters */
-+	DPDMAI_RSP_GET_ATTR(cmd, attr);
+	rsp_params = (struct dpdmai_rsp_get_attributes *)cmd.params;
+	attr->id = le32_to_cpu(rsp_params->id);
+	attr->version.major = le16_to_cpu(rsp_params->major);
+	attr->version.minor = le16_to_cpu(rsp_params->minor);
+	attr->num_of_priorities = rsp_params->num_of_priorities;
+
 +
 +	return 0;
 +}
@ -2333,13 +2291,22 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			uint8_t priority,
 +			const struct dpdmai_rx_queue_cfg *cfg)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
+	struct dpdmai_cmd_queue *cmd_params;
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_SET_RX_QUEUE,
 +					  cmd_flags,
 +					  token);
-+	DPDMAI_CMD_SET_RX_QUEUE(cmd, priority, cfg);
+
+	cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
+	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
+	cmd_params->priority = cfg->dest_cfg.priority;
+	cmd_params->queue = priority;
+	cmd_params->dest_type = cfg->dest_cfg.dest_type;
+	cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx);
+	cmd_params->options = cpu_to_le32(cfg->options);
+
 +
 +	/* send command to mc*/
 +	return mc_send_command(mc_io, &cmd);
@ -2350,14 +2317,17 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			uint16_t token,
 +			uint8_t priority, struct dpdmai_rx_queue_attr *attr)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
+	struct dpdmai_cmd_queue *cmd_params;
 +	int err;
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_RX_QUEUE,
 +					  cmd_flags,
 +					  token);
-+	DPDMAI_CMD_GET_RX_QUEUE(cmd, priority);
+
+	cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
+	cmd_params->queue = priority;
 +
 +	/* send command to mc*/
 +	err = mc_send_command(mc_io, &cmd);
@ -2365,7 +2335,11 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		return err;
 +
 +	/* retrieve response parameters */
-+	DPDMAI_RSP_GET_RX_QUEUE(cmd, attr);
+	attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id);
+	attr->dest_cfg.priority = cmd_params->priority;
+	attr->dest_cfg.dest_type = cmd_params->dest_type;
+	attr->user_ctx = le64_to_cpu(cmd_params->user_ctx);
+	attr->fqid = le32_to_cpu(cmd_params->fqid);
 +
 +	return 0;
 +}
@ -2376,14 +2350,18 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			uint8_t priority,
 +			struct dpdmai_tx_queue_attr *attr)
 +{
-+	struct mc_command cmd = { 0 };
+	struct fsl_mc_command cmd = { 0 };
+	struct dpdmai_cmd_queue *cmd_params;
+	struct dpdmai_rsp_get_tx_queue *rsp_params;
 +	int err;
 +
 +	/* prepare command */
 +	cmd.header = mc_encode_cmd_header(DPDMAI_CMDID_GET_TX_QUEUE,
 +					  cmd_flags,
 +					  token);
-+	DPDMAI_CMD_GET_TX_QUEUE(cmd, priority);
+
+	cmd_params = (struct dpdmai_cmd_queue *)cmd.params;
+	cmd_params->queue = priority;
 +
 +	/* send command to mc*/
 +	err = mc_send_command(mc_io, &cmd);
@ -2391,7 +2369,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		return err;
 +
 +	/* retrieve response parameters */
-+	DPDMAI_RSP_GET_TX_QUEUE(cmd, attr);
+
+	rsp_params = (struct dpdmai_rsp_get_tx_queue *)cmd.params;
+	attr->fqid = le32_to_cpu(rsp_params->fqid);
 +
 +	return 0;
 +}
--- a/target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch
@ -1,7 +1,7 @@
-From 0a6c701f92e1aa368c44632fa0985e92703354ed Mon Sep 17 00:00:00 2001
+From 89a1f0d7826df69d8e02268b97bc3da02e07203f Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:35:48 +0800
-Subject: [PATCH 22/30] iommu: support layerscape
+Date: Thu, 5 Jul 2018 17:35:15 +0800
+Subject: [PATCH 22/32] iommu: support layerscape

 This is an integrated patch for layerscape smmu support.

@ -11,17 +11,17 @@ Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
 Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/iommu/amd_iommu.c    |  56 ++++++----
- drivers/iommu/arm-smmu-v3.c  | 111 ++++++++++++++------
- drivers/iommu/arm-smmu.c     | 100 +++++++++++++++---
- drivers/iommu/dma-iommu.c    | 242 ++++++++++++++++++++++++++++++++++++-------
- drivers/iommu/intel-iommu.c  |  92 ++++++++++++----
- drivers/iommu/iommu.c        | 219 ++++++++++++++++++++++++++++++++++++---
+ drivers/iommu/amd_iommu.c    |  56 +++++---
+ drivers/iommu/arm-smmu-v3.c  | 111 +++++++++++-----
+ drivers/iommu/arm-smmu.c     | 100 ++++++++++++---
+ drivers/iommu/dma-iommu.c    | 242 +++++++++++++++++++++++++++++------
+ drivers/iommu/intel-iommu.c  |  92 ++++++++++---
+ drivers/iommu/iommu.c        | 240 ++++++++++++++++++++++++++++++++--
 drivers/iommu/mtk_iommu.c    |   2 +
 drivers/iommu/mtk_iommu_v1.c |   2 +
 include/linux/dma-iommu.h    |  11 ++
- include/linux/iommu.h        |  55 +++++++---
- 10 files changed, 739 insertions(+), 151 deletions(-)
+ include/linux/iommu.h        |  57 +++++++--
+ 10 files changed, 762 insertions(+), 151 deletions(-)

 --- a/drivers/iommu/amd_iommu.c
 +++ b/drivers/iommu/amd_iommu.c
@ -214,7 +214,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 	for (i = 0; i < nent; ++i) {
 		arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste);
-@@ -1364,8 +1374,6 @@ static bool arm_smmu_capable(enum iommu_
+@@ -1365,8 +1375,6 @@ static bool arm_smmu_capable(enum iommu_
 	switch (cap) {
 	case IOMMU_CAP_CACHE_COHERENCY:
 		return true;
@ -223,7 +223,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	case IOMMU_CAP_NOEXEC:
 		return true;
 	default:
-@@ -1377,7 +1385,9 @@ static struct iommu_domain *arm_smmu_dom
+@@ -1378,7 +1386,9 @@ static struct iommu_domain *arm_smmu_dom
 {
 	struct arm_smmu_domain *smmu_domain;
 
@ -234,7 +234,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 		return NULL;
 
 	/*
-@@ -1508,6 +1518,11 @@ static int arm_smmu_domain_finalise(stru
+@@ -1509,6 +1519,11 @@ static int arm_smmu_domain_finalise(stru
 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 	struct arm_smmu_device *smmu = smmu_domain->smmu;
 
@ -246,7 +246,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	/* Restrict the stage to what we can actually support */
 	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
 		smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
-@@ -1580,7 +1595,7 @@ static __le64 *arm_smmu_get_step_for_sid
+@@ -1581,7 +1596,7 @@ static __le64 *arm_smmu_get_step_for_sid
 	return step;
 }
 
@ -255,7 +255,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 {
 	int i, j;
 	struct arm_smmu_master_data *master = fwspec->iommu_priv;
-@@ -1599,17 +1614,14 @@ static int arm_smmu_install_ste_for_dev(
+@@ -1600,17 +1615,14 @@ static int arm_smmu_install_ste_for_dev(
 
 		arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
 	}
@ -275,7 +275,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 }
 
 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
-@@ -1628,7 +1640,7 @@ static int arm_smmu_attach_dev(struct io
+@@ -1629,7 +1641,7 @@ static int arm_smmu_attach_dev(struct io
 	ste = &master->ste;
 
 	/* Already attached to a different domain? */
@ -284,7 +284,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 		arm_smmu_detach_dev(dev);
 
 	mutex_lock(&smmu_domain->init_mutex);
-@@ -1649,10 +1661,12 @@ static int arm_smmu_attach_dev(struct io
+@@ -1650,10 +1662,12 @@ static int arm_smmu_attach_dev(struct io
 		goto out_unlock;
 	}
 
@ -300,7 +300,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 		ste->s1_cfg = &smmu_domain->s1_cfg;
 		ste->s2_cfg = NULL;
 		arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
-@@ -1661,10 +1675,7 @@ static int arm_smmu_attach_dev(struct io
+@@ -1662,10 +1676,7 @@ static int arm_smmu_attach_dev(struct io
 		ste->s2_cfg = &smmu_domain->s2_cfg;
 	}
 
@ -312,7 +312,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 out_unlock:
 	mutex_unlock(&smmu_domain->init_mutex);
 	return ret;
-@@ -1712,6 +1723,9 @@ arm_smmu_iova_to_phys(struct iommu_domai
+@@ -1696,6 +1707,9 @@ arm_smmu_unmap(struct iommu_domain *doma
 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 	struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
 
@ -322,7 +322,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	if (!ops)
 		return 0;
 
-@@ -1810,7 +1824,7 @@ static void arm_smmu_remove_device(struc
+@@ -1811,7 +1825,7 @@ static void arm_smmu_remove_device(struc
 		return;
 
 	master = fwspec->iommu_priv;
@ -331,7 +331,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 		arm_smmu_detach_dev(dev);
 	iommu_group_remove_device(dev);
 	kfree(master);
-@@ -1839,6 +1853,9 @@ static int arm_smmu_domain_get_attr(stru
+@@ -1840,6 +1854,9 @@ static int arm_smmu_domain_get_attr(stru
 {
 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 
@ -341,7 +341,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	switch (attr) {
 	case DOMAIN_ATTR_NESTING:
 		*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
-@@ -1854,6 +1871,9 @@ static int arm_smmu_domain_set_attr(stru
+@@ -1855,6 +1872,9 @@ static int arm_smmu_domain_set_attr(stru
 	int ret = 0;
 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
 
@ -351,7 +351,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	mutex_lock(&smmu_domain->init_mutex);
 
 	switch (attr) {
-@@ -1883,6 +1903,31 @@ static int arm_smmu_of_xlate(struct devi
+@@ -1884,6 +1904,31 @@ static int arm_smmu_of_xlate(struct devi
 	return iommu_fwspec_add_ids(dev, args->args, 1);
 }
 
@ -383,7 +383,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 static struct iommu_ops arm_smmu_ops = {
 	.capable		= arm_smmu_capable,
 	.domain_alloc		= arm_smmu_domain_alloc,
-@@ -1898,6 +1943,8 @@ static struct iommu_ops arm_smmu_ops = {
+@@ -1899,6 +1944,8 @@ static struct iommu_ops arm_smmu_ops = {
 	.domain_get_attr	= arm_smmu_domain_get_attr,
 	.domain_set_attr	= arm_smmu_domain_set_attr,
 	.of_xlate		= arm_smmu_of_xlate,
@ -398,7 +398,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #include <linux/spinlock.h>
 
 #include <linux/amba/bus.h>
-+#include "../staging/fsl-mc/include/mc-bus.h"
+#include <linux/fsl/mc.h>
 
 #include "io-pgtable.h"
 
@ -1132,7 +1132,11 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
 --- a/drivers/iommu/iommu.c
 +++ b/drivers/iommu/iommu.c
-@@ -36,6 +36,7 @@
+@@ -33,9 +33,11 @@
+ #include <linux/bitops.h>
+ #include <linux/property.h>
+ #include <trace/events/iommu.h>
+#include <linux/fsl/mc.h>
 
 static struct kset *iommu_group_kset;
 static DEFINE_IDA(iommu_group_ida);
@ -1140,7 +1144,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 struct iommu_callback_data {
 	const struct iommu_ops *ops;
-@@ -68,6 +69,13 @@ struct iommu_group_attribute {
+@@ -68,6 +70,13 @@ struct iommu_group_attribute {
 			 const char *buf, size_t count);
 };
 
@ -1154,7 +1158,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #define IOMMU_GROUP_ATTR(_name, _mode, _show, _store)		\
 struct iommu_group_attribute iommu_group_attr_##_name =		\
 	__ATTR(_name, _mode, _show, _store)
-@@ -86,6 +94,18 @@ static int __iommu_attach_group(struct i
+@@ -86,6 +95,18 @@ static int __iommu_attach_group(struct i
 static void __iommu_detach_group(struct iommu_domain *domain,
 				 struct iommu_group *group);
 
@ -1173,7 +1177,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 static ssize_t iommu_group_attr_show(struct kobject *kobj,
 				     struct attribute *__attr, char *buf)
 {
-@@ -133,8 +153,131 @@ static ssize_t iommu_group_show_name(str
+@@ -133,8 +154,131 @@ static ssize_t iommu_group_show_name(str
 	return sprintf(buf, "%s\n", group->name);
 }
 
@ -1305,7 +1309,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 static void iommu_group_release(struct kobject *kobj)
 {
 	struct iommu_group *group = to_iommu_group(kobj);
-@@ -212,6 +355,11 @@ struct iommu_group *iommu_group_alloc(vo
+@@ -212,6 +356,11 @@ struct iommu_group *iommu_group_alloc(vo
 	 */
 	kobject_put(&group->kobj);
 
@ -1317,7 +1321,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	pr_debug("Allocated group %d\n", group->id);
 
 	return group;
-@@ -318,7 +466,7 @@ static int iommu_group_create_direct_map
+@@ -318,7 +467,7 @@ static int iommu_group_create_direct_map
 					      struct device *dev)
 {
 	struct iommu_domain *domain = group->default_domain;
@ -1326,7 +1330,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	struct list_head mappings;
 	unsigned long pg_size;
 	int ret = 0;
-@@ -331,18 +479,21 @@ static int iommu_group_create_direct_map
+@@ -331,18 +480,21 @@ static int iommu_group_create_direct_map
 	pg_size = 1UL << __ffs(domain->pgsize_bitmap);
 	INIT_LIST_HEAD(&mappings);
 
@ -1351,7 +1355,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 		for (addr = start; addr < end; addr += pg_size) {
 			phys_addr_t phys_addr;
 
-@@ -358,7 +509,7 @@ static int iommu_group_create_direct_map
+@@ -358,7 +510,7 @@ static int iommu_group_create_direct_map
 	}
 
 out:
@ -1360,7 +1364,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 	return ret;
 }
-@@ -563,6 +714,19 @@ struct iommu_group *iommu_group_get(stru
+@@ -563,6 +715,19 @@ struct iommu_group *iommu_group_get(stru
 EXPORT_SYMBOL_GPL(iommu_group_get);
 
 /**
@ -1380,7 +1384,34 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  * iommu_group_put - Decrement group reference
  * @group: the group to use
  *
-@@ -845,10 +1009,19 @@ struct iommu_group *iommu_group_get_for_
+@@ -812,6 +977,26 @@ struct iommu_group *pci_device_group(str
+ 	return group;
+ }
+ 
+/* Get the IOMMU group for device on fsl-mc bus */
+struct iommu_group *fsl_mc_device_group(struct device *dev)
+{
+	struct device *cont_dev = fsl_mc_cont_dev(dev);
+	struct iommu_group *group;
+
+	/* Container device is responsible for creating the iommu group */
+	if (fsl_mc_is_cont_dev(dev)) {
+		group = iommu_group_alloc();
+		if (IS_ERR(group))
+			return NULL;
+	} else {
+		get_device(cont_dev);
+		group = iommu_group_get(cont_dev);
+		put_device(cont_dev);
+	}
+
+	return group;
+}
+
+ /**
+  * iommu_group_get_for_dev - Find or create the IOMMU group for a device
+  * @dev: target device
+@@ -845,10 +1030,19 @@ struct iommu_group *iommu_group_get_for_
 	 * IOMMU driver.
 	 */
 	if (!group->default_domain) {
@ -1403,7 +1434,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	}
 
 	ret = iommu_group_add_device(group, dev);
-@@ -1557,20 +1730,38 @@ int iommu_domain_set_attr(struct iommu_d
+@@ -1557,20 +1751,38 @@ int iommu_domain_set_attr(struct iommu_d
 }
 EXPORT_SYMBOL_GPL(iommu_domain_set_attr);
 
@ -1604,7 +1635,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 extern void iommu_group_put(struct iommu_group *group);
 extern int iommu_group_register_notifier(struct iommu_group *group,
 					 struct notifier_block *nb);
-@@ -439,16 +460,22 @@ static inline void iommu_set_fault_handl
+@@ -330,6 +351,8 @@ static inline size_t iommu_map_sg(struct
+ extern struct iommu_group *pci_device_group(struct device *dev);
+ /* Generic device grouping function */
+ extern struct iommu_group *generic_device_group(struct device *dev);
+/* FSL-MC device grouping function */
+struct iommu_group *fsl_mc_device_group(struct device *dev);
+ 
+ /**
+  * struct iommu_fwspec - per-device IOMMU instance data
+@@ -439,16 +462,22 @@ static inline void iommu_set_fault_handl
 {
 }
 
--- a/target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch
@ -1,7 +1,7 @@
-From 5a5ff01c790d49c0f6fd247f68f2fd9a2128ea91 Mon Sep 17 00:00:00 2001
+From dab02a7cc54494740e849cd51b554d100eb5541d Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:36:28 +0800
-Subject: [PATCH 23/30] irqchip: support layerscape
+Date: Thu, 5 Jul 2018 17:36:09 +0800
+Subject: [PATCH 23/32] irqchip: support layerscape

 This is an integrated patch for layerscape gic support.

@ -9,16 +9,17 @@ Signed-off-by: Eric Auger <eric.auger@redhat.com>
 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/irqchip/Makefile         |  1 +
- drivers/irqchip/irq-gic-v3-its.c |  1 +
- include/linux/irqdomain.h        | 36 ++++++++++++++++++++++++++++++++++++
- kernel/irq/irqdomain.c           | 39 +++++++++++++++++++++++++++++++++++++++
- kernel/irq/msi.c                 |  4 ++--
- 5 files changed, 79 insertions(+), 2 deletions(-)
+ drivers/irqchip/Makefile           |  1 +
+ drivers/irqchip/irq-gic-v3-its.c   |  1 +
+ include/linux/irqchip/arm-gic-v3.h |  3 +++
+ include/linux/irqdomain.h          | 36 +++++++++++++++++++++++++++
+ kernel/irq/irqdomain.c             | 39 ++++++++++++++++++++++++++++++
+ kernel/irq/msi.c                   |  4 +--
+ 6 files changed, 82 insertions(+), 2 deletions(-)

 --- a/drivers/irqchip/Makefile
 +++ b/drivers/irqchip/Makefile
-@@ -74,3 +74,4 @@ obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scf
+@@ -75,3 +75,4 @@ obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scf
 obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o
 obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
@ -33,9 +34,21 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	info->ops = &its_msi_domain_ops;
 	info->data = its;
 	inner_domain->host_data = info;
+--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
+@@ -133,6 +133,9 @@
+ #define GIC_BASER_SHAREABILITY(reg, type)				\
+ 	(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+ 
+/* encode a size field of width @w containing @n - 1 units */
+#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
+
+ #define GICR_PROPBASER_SHAREABILITY_SHIFT		(10)
+ #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT		(7)
+ #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT		(56)
 --- a/include/linux/irqdomain.h
 +++ b/include/linux/irqdomain.h
-@@ -183,6 +183,12 @@ enum {
+@@ -187,6 +187,12 @@ enum {
 	/* Irq domain is an IPI domain with single virq */
 	IRQ_DOMAIN_FLAG_IPI_SINGLE	= (1 << 3),
 
@ -48,7 +61,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 	/*
 	 * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved
 	 * for implementation specific purposes and ignored by the
-@@ -216,6 +222,7 @@ struct irq_domain *irq_domain_add_legacy
+@@ -220,6 +226,7 @@ struct irq_domain *irq_domain_add_legacy
 					 void *host_data);
 extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
 						   enum irq_domain_bus_token bus_token);
@ -56,7 +69,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 extern void irq_set_default_host(struct irq_domain *host);
 extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs,
 				  irq_hw_number_t hwirq, int node,
-@@ -446,6 +453,19 @@ static inline bool irq_domain_is_ipi_sin
+@@ -453,6 +460,19 @@ static inline bool irq_domain_is_ipi_sin
 {
 	return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE;
 }
@ -76,7 +89,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #else	/* CONFIG_IRQ_DOMAIN_HIERARCHY */
 static inline void irq_domain_activate_irq(struct irq_data *data) { }
 static inline void irq_domain_deactivate_irq(struct irq_data *data) { }
-@@ -477,6 +497,22 @@ static inline bool irq_domain_is_ipi_sin
+@@ -484,6 +504,22 @@ static inline bool irq_domain_is_ipi_sin
 {
 	return false;
 }
@ -101,7 +114,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #else /* CONFIG_IRQ_DOMAIN */
 --- a/kernel/irq/irqdomain.c
 +++ b/kernel/irq/irqdomain.c
-@@ -278,6 +278,31 @@ struct irq_domain *irq_find_matching_fws
+@@ -319,6 +319,31 @@ struct irq_domain *irq_find_matching_fws
 EXPORT_SYMBOL_GPL(irq_find_matching_fwspec);
 
 /**
@ -133,7 +146,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  * irq_set_default_host() - Set a "default" irq domain
  * @domain: default domain pointer
  *
-@@ -1408,6 +1433,20 @@ static void irq_domain_check_hierarchy(s
+@@ -1420,6 +1445,20 @@ static void irq_domain_check_hierarchy(s
 	if (domain->ops->alloc)
 		domain->flags |= IRQ_DOMAIN_FLAG_HIERARCHY;
 }
--- a/target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch
@ -1,7 +1,7 @@
-From a2a97f0d2c07a772899ca09967547bea6c9124c5 Mon Sep 17 00:00:00 2001
+From 1d35e363dd6e8bb1733bca0dfc186e3f70e692fe Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:46:03 +0800
-Subject: [PATCH 29/30] usb: support layerscape
+Date: Thu, 5 Jul 2018 17:38:52 +0800
+Subject: [PATCH 29/32] usb: support layerscape

 This is an integrated patch for layerscape usb support.

@ -17,30 +17,31 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
 drivers/net/usb/cdc_ether.c           |   8 +
 drivers/net/usb/r8152.c               |   6 +
- drivers/usb/common/common.c           |  50 ++++++
+ drivers/usb/common/common.c           |  50 +++++
 drivers/usb/core/hub.c                |   8 +
- drivers/usb/dwc3/core.c               | 243 ++++++++++++++++++++++++++++-
- drivers/usb/dwc3/core.h               |  51 ++++++-
+ drivers/usb/dwc3/core.c               | 243 +++++++++++++++++++++-
+ drivers/usb/dwc3/core.h               |  51 ++++-
 drivers/usb/dwc3/ep0.c                |   4 +-
 drivers/usb/dwc3/gadget.c             |   7 +
 drivers/usb/dwc3/host.c               |  24 ++-
- drivers/usb/gadget/udc/fsl_udc_core.c |  46 +++---
+ drivers/usb/gadget/udc/fsl_udc_core.c |  46 +++--
 drivers/usb/gadget/udc/fsl_usb2_udc.h |  16 +-
- drivers/usb/host/Kconfig              |   2 +-
- drivers/usb/host/ehci-fsl.c           | 279 +++++++++++++++++++++++++++++++---
+ drivers/usb/host/Kconfig              |   4 +-
+ drivers/usb/host/ehci-fsl.c           | 279 ++++++++++++++++++++++++--
 drivers/usb/host/ehci-fsl.h           |   3 +
 drivers/usb/host/ehci-hub.c           |   4 +
- drivers/usb/host/ehci.h               |   9 ++
- drivers/usb/host/fsl-mph-dr-of.c      |  12 ++
- drivers/usb/host/xhci-plat.c          |  10 ++
- drivers/usb/host/xhci-ring.c          |  29 +++-
- drivers/usb/host/xhci.c               |  38 ++++-
- drivers/usb/host/xhci.h               |   5 +-
- drivers/usb/phy/phy-fsl-usb.c         |  59 +++++--
+ drivers/usb/host/ehci.h               |   9 +
+ drivers/usb/host/fsl-mph-dr-of.c      |  16 +-
+ drivers/usb/host/xhci-hub.c           |  22 ++
+ drivers/usb/host/xhci-plat.c          |  16 +-
+ drivers/usb/host/xhci-ring.c          |  29 ++-
+ drivers/usb/host/xhci.c               |  38 +++-
+ drivers/usb/host/xhci.h               |   6 +-
+ drivers/usb/phy/phy-fsl-usb.c         |  59 ++++--
 drivers/usb/phy/phy-fsl-usb.h         |   8 +
 include/linux/usb.h                   |   1 +
 include/linux/usb/of.h                |   2 +
- 25 files changed, 836 insertions(+), 88 deletions(-)
+ 26 files changed, 867 insertions(+), 92 deletions(-)

 --- a/drivers/net/usb/cdc_ether.c
 +++ b/drivers/net/usb/cdc_ether.c
@ -924,11 +925,13 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #endif
 --- a/drivers/usb/host/Kconfig
 +++ b/drivers/usb/host/Kconfig
-@@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
+@@ -164,8 +164,8 @@ config XPS_USB_HCD_XILINX
+ 		devices only.
 
 config USB_EHCI_FSL
- 	tristate "Support for Freescale PPC on-chip EHCI USB controller"
+-	tristate "Support for Freescale PPC on-chip EHCI USB controller"
 -	depends on FSL_SOC
+	tristate "Support for Freescale QorIQ(ARM/PPC) on-chip EHCI USB controller"
 +	depends on USB_EHCI_HCD
 	select USB_EHCI_ROOT_HUB_TT
 	---help---
@ -1399,6 +1402,17 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 /*
 --- a/drivers/usb/host/fsl-mph-dr-of.c
 +++ b/drivers/usb/host/fsl-mph-dr-of.c
+@@ -98,8 +98,8 @@ static struct platform_device *fsl_usb2_
+ 
+ 	pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask;
+ 
+-	if (!pdev->dev.dma_mask)
+-		pdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
+	if (!pdev->dev.dma_mask && ofdev->dev.of_node)
+		of_dma_configure(&pdev->dev, ofdev->dev.of_node);
+ 	else
+ 		dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+ 
@@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
 		of_property_read_bool(np, "fsl,usb-erratum-a007792");
 	pdata->has_fsl_erratum_a005275 =
@ -1418,12 +1432,57 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 
 	/*
 	 * Determine whether phy_clk_valid needs to be checked
+--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
+@@ -562,12 +562,34 @@ void xhci_set_link_state(struct xhci_hcd
+ 				int port_id, u32 link_state)
+ {
+ 	u32 temp;
+	u32 portpmsc_u2_backup = 0;
+
+	/* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
+	if (xhci->shared_hcd->speed >= HCD_USB3 &&
+			link_state == USB_SS_PORT_LS_U3 &&
+			(xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
+		portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
+		portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
+		temp = readl(port_array[port_id] + PORTPMSC);
+		temp |= PORT_U2_TIMEOUT_MASK;
+		writel(temp, port_array[port_id] + PORTPMSC);
+	}
+ 
+ 	temp = readl(port_array[port_id]);
+ 	temp = xhci_port_state_to_neutral(temp);
+ 	temp &= ~PORT_PLS_MASK;
+ 	temp |= PORT_LINK_STROBE | link_state;
+ 	writel(temp, port_array[port_id]);
+
+	/* Restore U2 timeout info after U3 entry complete */
+	if (xhci->shared_hcd->speed >= HCD_USB3 &&
+			link_state == USB_SS_PORT_LS_U3 &&
+			(xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
+		temp = readl(port_array[port_id] + PORTPMSC);
+		temp &= ~PORT_U2_TIMEOUT_MASK;
+		temp |= portpmsc_u2_backup;
+		writel(temp, port_array[port_id] + PORTPMSC);
+	}
+ }
+ 
+ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 --- a/drivers/usb/host/xhci-plat.c
 +++ b/drivers/usb/host/xhci-plat.c
-@@ -223,6 +223,16 @@ static int xhci_plat_probe(struct platfo
- 	if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
- 		xhci->quirks |= XHCI_LPM_SUPPORT;
+@@ -220,8 +220,22 @@ static int xhci_plat_probe(struct platfo
+ 		goto disable_clk;
+ 	}
 
+-	if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
+	if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable")) {
+ 		xhci->quirks |= XHCI_LPM_SUPPORT;
+		if (device_property_read_bool(&pdev->dev,
+					"snps,dis-u1u2-when-u3-quirk"))
+			xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
+	}
+
 +	if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
 +		xhci->quirks |= XHCI_REVERSE_IN_OUT;
 +
@ -1433,10 +1492,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
 +	if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
 +		xhci->quirks |= XHCI_STOP_EP_IN_U1;
-+
+ 
 	if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
 		xhci->quirks |= XHCI_BROKEN_PORT_PED;
- 
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
@@ -1852,14 +1852,17 @@ static int finish_td(struct xhci_hcd *xh
@ -1551,13 +1609,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 #define	XHCI_LINK_TRB_QUIRK	(1 << 0)
 #define XHCI_RESET_EP_QUIRK	(1 << 1)
 #define XHCI_NEC_HOST		(1 << 2)
-@@ -1661,6 +1661,9 @@ struct xhci_hcd {
+@@ -1661,6 +1661,10 @@ struct xhci_hcd {
 #define XHCI_SSIC_PORT_UNUSED	(1 << 22)
 #define XHCI_NO_64BIT_SUPPORT	(1 << 23)
 #define XHCI_MISSING_CAS	(1 << 24)
 +#define XHCI_REVERSE_IN_OUT    (1 << 29)
 +#define XHCI_STOP_TRANSFER_IN_BLOCK    (1 << 30)
 +#define XHCI_STOP_EP_IN_U1    (1 << 31)
+#define XHCI_DIS_U1U2_WHEN_U3 (1 << 32)
 /* For controller with a broken Port Disable implementation */
 #define XHCI_BROKEN_PORT_PED	(1 << 25)
 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7	(1 << 26)
--- a/target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch
@ -1,7 +1,7 @@
-From 954edeee88305fecefe3f681e67a298f06e27974 Mon Sep 17 00:00:00 2001
+From e6af99cc1d56322fc960d072af1a7e0e9285b90c Mon Sep 17 00:00:00 2001
 From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Wed, 17 Jan 2018 15:48:47 +0800
-Subject: [PATCH 30/30] vfio: support layerscape
+Date: Thu, 5 Jul 2018 17:39:43 +0800
+Subject: [PATCH 30/32] vfio: support layerscape

 This is an integrated patch for layerscape vfio support.

@ -15,12 +15,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 drivers/vfio/Makefile                     |   1 +
 drivers/vfio/fsl-mc/Kconfig               |   9 +
 drivers/vfio/fsl-mc/Makefile              |   2 +
- drivers/vfio/fsl-mc/vfio_fsl_mc.c         | 753 ++++++++++++++++++++++++++++++
- drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c    | 199 ++++++++
- drivers/vfio/fsl-mc/vfio_fsl_mc_private.h |  55 +++
+ drivers/vfio/fsl-mc/vfio_fsl_mc.c         | 752 ++++++++++++++++++++++
+ drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c    | 199 ++++++
+ drivers/vfio/fsl-mc/vfio_fsl_mc_private.h |  55 ++
 drivers/vfio/vfio_iommu_type1.c           |  39 +-
 include/uapi/linux/vfio.h                 |   1 +
- 9 files changed, 1058 insertions(+), 2 deletions(-)
+ 9 files changed, 1057 insertions(+), 2 deletions(-)
 create mode 100644 drivers/vfio/fsl-mc/Kconfig
 create mode 100644 drivers/vfio/fsl-mc/Makefile
 create mode 100644 drivers/vfio/fsl-mc/vfio_fsl_mc.c
@ -61,7 +61,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +obj-$(CONFIG_VFIO_FSL_MC) += vfio_fsl_mc.o vfio_fsl_mc_intr.o
 --- /dev/null
 +++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
-@@ -0,0 +1,753 @@
+@@ -0,0 +1,752 @@
 +/*
 + * Freescale Management Complex (MC) device passthrough using VFIO
 + *
@ -83,10 +83,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#include <linux/vfio.h>
 +#include <linux/delay.h>
 +
-+#include "../../staging/fsl-mc/include/mc.h"
-+#include "../../staging/fsl-mc/include/mc-bus.h"
-+#include "../../staging/fsl-mc/include/mc-sys.h"
-+#include "../../staging/fsl-mc/bus/dprc-cmd.h"
+#include <linux/fsl/mc.h>
 +
 +#include "vfio_fsl_mc_private.h"
 +
@ -353,8 +350,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	uint64_t data[8];
 +	int i;
 +
-+	/* Read ioctl supported only for DPRC device */
-+	if (strcmp(vdev->mc_dev->obj_desc.type, "dprc"))
+	/* Read ioctl supported only for DPRC and DPMCP device */
+	if (strcmp(vdev->mc_dev->obj_desc.type, "dprc") &&
+	    strcmp(vdev->mc_dev->obj_desc.type, "dpmcp"))
 +		return -EINVAL;
 +
 +	if (index >= vdev->num_regions)
@ -455,8 +453,9 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	uint64_t data[8];
 +	int ret;
 +
-+	/* Write ioctl supported only for DPRC device */
-+	if (strcmp(vdev->mc_dev->obj_desc.type, "dprc"))
+	/* Write ioctl supported only for DPRC and DPMCP device */
+	if (strcmp(vdev->mc_dev->obj_desc.type, "dprc") &&
+	    strcmp(vdev->mc_dev->obj_desc.type, "dpmcp"))
 +		return -EINVAL;
 +
 +	if (index >= vdev->num_regions)
@ -835,7 +834,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#include <linux/eventfd.h>
 +#include <linux/msi.h>
 +
-+#include "../../staging/fsl-mc/include/mc.h"
+#include "linux/fsl/mc.h"
 +#include "vfio_fsl_mc_private.h"
 +
 +static irqreturn_t vfio_fsl_mc_irq_handler(int irq_num, void *arg)
--- a/target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch
@ -0,0 +1,542 @@
+From 2887442bd13bc8be687afc7172cb01c2b7f0dd3b Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:41:14 +0800
+Subject: [PATCH 31/32] flexcan: support layerscape
+
+This is an integrated patch for layerscape flexcan support.
+
+Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
+Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
+Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/net/can/flexcan.c | 212 ++++++++++++++++++++++----------------
+ 1 file changed, 123 insertions(+), 89 deletions(-)
+
+--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
+@@ -184,6 +184,7 @@
+  *   MX53  FlexCAN2  03.00.00.00    yes        no         no        no
+  *   MX6s  FlexCAN3  10.00.12.00    yes       yes         no       yes
+  *   VF610 FlexCAN3  ?               no       yes        yes       yes?
+ * LS1021A FlexCAN2  03.00.04.00     no       yes         no       yes
+  *
+  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
+  */
+@@ -260,6 +261,10 @@ struct flexcan_priv {
+ 	struct flexcan_platform_data *pdata;
+ 	const struct flexcan_devtype_data *devtype_data;
+ 	struct regulator *reg_xceiver;
+
+	/* Read and Write APIs */
+	u32 (*read)(void __iomem *addr);
+	void (*write)(u32 val, void __iomem *addr);
+ };
+ 
+ static struct flexcan_devtype_data fsl_p1010_devtype_data = {
+@@ -276,6 +281,10 @@ static struct flexcan_devtype_data fsl_v
+ 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
+ };
+ 
+static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
+	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
+};
+
+ static const struct can_bittiming_const flexcan_bittiming_const = {
+ 	.name = DRV_NAME,
+ 	.tseg1_min = 4,
+@@ -288,32 +297,38 @@ static const struct can_bittiming_const
+ 	.brp_inc = 1,
+ };
+ 
+-/* Abstract off the read/write for arm versus ppc. This
+- * assumes that PPC uses big-endian registers and everything
+- * else uses little-endian registers, independent of CPU
+- * endianness.
+/* FlexCAN module is essentially modelled as a little-endian IP in most
+ * SoCs, i.e the registers as well as the message buffer areas are
+ * implemented in a little-endian fashion.
+ *
+ * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
+ * module in a big-endian fashion (i.e the registers as well as the
+ * message buffer areas are implemented in a big-endian way).
+ *
+ * In addition, the FlexCAN module can be found on SoCs having ARM or
+ * PPC cores. So, we need to abstract off the register read/write
+ * functions, ensuring that these cater to all the combinations of module
+ * endianness and underlying CPU endianness.
+  */
+-#if defined(CONFIG_PPC)
+-static inline u32 flexcan_read(void __iomem *addr)
+static inline u32 flexcan_read_be(void __iomem *addr)
+ {
+-	return in_be32(addr);
+	return ioread32be(addr);
+ }
+ 
+-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_be(u32 val, void __iomem *addr)
+ {
+-	out_be32(addr, val);
+	iowrite32be(val, addr);
+ }
+-#else
+-static inline u32 flexcan_read(void __iomem *addr)
+
+static inline u32 flexcan_read_le(void __iomem *addr)
+ {
+-	return readl(addr);
+	return ioread32(addr);
+ }
+ 
+-static inline void flexcan_write(u32 val, void __iomem *addr)
+static inline void flexcan_write_le(u32 val, void __iomem *addr)
+ {
+-	writel(val, addr);
+	iowrite32(val, addr);
+ }
+-#endif
+ 
+ static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
+ {
+@@ -344,14 +359,14 @@ static int flexcan_chip_enable(struct fl
+ 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
+ 	u32 reg;
+ 
+-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
+ 	reg &= ~FLEXCAN_MCR_MDIS;
+-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
+ 
+-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+ 		udelay(10);
+ 
+-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
+ 		return -ETIMEDOUT;
+ 
+ 	return 0;
+@@ -363,14 +378,14 @@ static int flexcan_chip_disable(struct f
+ 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
+ 	u32 reg;
+ 
+-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
+ 	reg |= FLEXCAN_MCR_MDIS;
+-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
+ 
+-	while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+ 		udelay(10);
+ 
+-	if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
+ 		return -ETIMEDOUT;
+ 
+ 	return 0;
+@@ -382,14 +397,14 @@ static int flexcan_chip_freeze(struct fl
+ 	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
+ 	u32 reg;
+ 
+-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
+ 	reg |= FLEXCAN_MCR_HALT;
+-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
+ 
+-	while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+ 		udelay(100);
+ 
+-	if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+ 		return -ETIMEDOUT;
+ 
+ 	return 0;
+@@ -401,14 +416,14 @@ static int flexcan_chip_unfreeze(struct
+ 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
+ 	u32 reg;
+ 
+-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
+ 	reg &= ~FLEXCAN_MCR_HALT;
+-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
+ 
+-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
+ 		udelay(10);
+ 
+-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
+ 		return -ETIMEDOUT;
+ 
+ 	return 0;
+@@ -419,11 +434,11 @@ static int flexcan_chip_softreset(struct
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+ 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
+ 
+-	flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+-	while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
+	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
+	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
+ 		udelay(10);
+ 
+-	if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
+ 		return -ETIMEDOUT;
+ 
+ 	return 0;
+@@ -434,7 +449,7 @@ static int __flexcan_get_berr_counter(co
+ {
+ 	const struct flexcan_priv *priv = netdev_priv(dev);
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+-	u32 reg = flexcan_read(&regs->ecr);
+	u32 reg = priv->read(&regs->ecr);
+ 
+ 	bec->txerr = (reg >> 0) & 0xff;
+ 	bec->rxerr = (reg >> 8) & 0xff;
+@@ -491,24 +506,24 @@ static int flexcan_start_xmit(struct sk_
+ 
+ 	if (cf->can_dlc > 0) {
+ 		data = be32_to_cpup((__be32 *)&cf->data[0]);
+-		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
+		priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
+ 	}
+ 	if (cf->can_dlc > 4) {
+ 		data = be32_to_cpup((__be32 *)&cf->data[4]);
+-		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
+		priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
+ 	}
+ 
+ 	can_put_echo_skb(skb, dev, 0);
+ 
+-	flexcan_write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
+-	flexcan_write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
+	priv->write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
+	priv->write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
+ 
+ 	/* Errata ERR005829 step8:
+ 	 * Write twice INACTIVE(0x8) code to first MB.
+ 	 */
+-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ 		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
+-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ 		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
+ 
+ 	return NETDEV_TX_OK;
+@@ -632,8 +647,8 @@ static void flexcan_read_fifo(const stru
+ 	struct flexcan_mb __iomem *mb = &regs->mb[0];
+ 	u32 reg_ctrl, reg_id;
+ 
+-	reg_ctrl = flexcan_read(&mb->can_ctrl);
+-	reg_id = flexcan_read(&mb->can_id);
+	reg_ctrl = priv->read(&mb->can_ctrl);
+	reg_id = priv->read(&mb->can_id);
+ 	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
+ 		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ 	else
+@@ -643,12 +658,12 @@ static void flexcan_read_fifo(const stru
+ 		cf->can_id |= CAN_RTR_FLAG;
+ 	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
+ 
+-	*(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
+-	*(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
+	*(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
+	*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
+ 
+ 	/* mark as read */
+-	flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+-	flexcan_read(&regs->timer);
+	priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+	priv->read(&regs->timer);
+ }
+ 
+ static int flexcan_read_frame(struct net_device *dev)
+@@ -685,17 +700,17 @@ static int flexcan_poll(struct napi_stru
+ 	/* The error bits are cleared on read,
+ 	 * use saved value from irq handler.
+ 	 */
+-	reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
+	reg_esr = priv->read(&regs->esr) | priv->reg_esr;
+ 
+ 	/* handle state changes */
+ 	work_done += flexcan_poll_state(dev, reg_esr);
+ 
+ 	/* handle RX-FIFO */
+-	reg_iflag1 = flexcan_read(&regs->iflag1);
+	reg_iflag1 = priv->read(&regs->iflag1);
+ 	while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
+ 	       work_done < quota) {
+ 		work_done += flexcan_read_frame(dev);
+-		reg_iflag1 = flexcan_read(&regs->iflag1);
+		reg_iflag1 = priv->read(&regs->iflag1);
+ 	}
+ 
+ 	/* report bus errors */
+@@ -705,8 +720,8 @@ static int flexcan_poll(struct napi_stru
+ 	if (work_done < quota) {
+ 		napi_complete_done(napi, work_done);
+ 		/* enable IRQs */
+-		flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+-		flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
+		priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+		priv->write(priv->reg_ctrl_default, &regs->ctrl);
+ 	}
+ 
+ 	return work_done;
+@@ -720,12 +735,12 @@ static irqreturn_t flexcan_irq(int irq,
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+ 	u32 reg_iflag1, reg_esr;
+ 
+-	reg_iflag1 = flexcan_read(&regs->iflag1);
+-	reg_esr = flexcan_read(&regs->esr);
+	reg_iflag1 = priv->read(&regs->iflag1);
+	reg_esr = priv->read(&regs->esr);
+ 
+ 	/* ACK all bus error and state change IRQ sources */
+ 	if (reg_esr & FLEXCAN_ESR_ALL_INT)
+-		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+ 
+ 	/* schedule NAPI in case of:
+ 	 * - rx IRQ
+@@ -739,16 +754,16 @@ static irqreturn_t flexcan_irq(int irq,
+ 		 * save them for later use.
+ 		 */
+ 		priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
+-		flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+		priv->write(FLEXCAN_IFLAG_DEFAULT &
+ 			      ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
+-		flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+		priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+ 			      &regs->ctrl);
+ 		napi_schedule(&priv->napi);
+ 	}
+ 
+ 	/* FIFO overflow */
+ 	if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
+-		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+		priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+ 		dev->stats.rx_over_errors++;
+ 		dev->stats.rx_errors++;
+ 	}
+@@ -760,9 +775,9 @@ static irqreturn_t flexcan_irq(int irq,
+ 		can_led_event(dev, CAN_LED_EVENT_TX);
+ 
+ 		/* after sending a RTR frame MB is in RX mode */
+-		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ 			      &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
+-		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
+		priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
+ 		netif_wake_queue(dev);
+ 	}
+ 
+@@ -776,7 +791,7 @@ static void flexcan_set_bittiming(struct
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+ 	u32 reg;
+ 
+-	reg = flexcan_read(&regs->ctrl);
+	reg = priv->read(&regs->ctrl);
+ 	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
+ 		 FLEXCAN_CTRL_RJW(0x3) |
+ 		 FLEXCAN_CTRL_PSEG1(0x7) |
+@@ -800,11 +815,11 @@ static void flexcan_set_bittiming(struct
+ 		reg |= FLEXCAN_CTRL_SMP;
+ 
+ 	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
+-	flexcan_write(reg, &regs->ctrl);
+	priv->write(reg, &regs->ctrl);
+ 
+ 	/* print chip status */
+ 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
+-		   flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
+ }
+ 
+ /* flexcan_chip_start
+@@ -842,13 +857,13 @@ static int flexcan_chip_start(struct net
+ 	 * choose format C
+ 	 * set max mailbox number
+ 	 */
+-	reg_mcr = flexcan_read(&regs->mcr);
+	reg_mcr = priv->read(&regs->mcr);
+ 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
+ 	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
+ 		FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
+ 		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+ 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
+-	flexcan_write(reg_mcr, &regs->mcr);
+	priv->write(reg_mcr, &regs->mcr);
+ 
+ 	/* CTRL
+ 	 *
+@@ -861,7 +876,7 @@ static int flexcan_chip_start(struct net
+ 	 * enable bus off interrupt
+ 	 * (== FLEXCAN_CTRL_ERR_STATE)
+ 	 */
+-	reg_ctrl = flexcan_read(&regs->ctrl);
+	reg_ctrl = priv->read(&regs->ctrl);
+ 	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
+ 	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
+ 		FLEXCAN_CTRL_ERR_STATE;
+@@ -881,29 +896,29 @@ static int flexcan_chip_start(struct net
+ 	/* leave interrupts disabled for now */
+ 	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
+ 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
+-	flexcan_write(reg_ctrl, &regs->ctrl);
+	priv->write(reg_ctrl, &regs->ctrl);
+ 
+ 	/* clear and invalidate all mailboxes first */
+ 	for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
+-		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
+		priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
+ 			      &regs->mb[i].can_ctrl);
+ 	}
+ 
+ 	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
+-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ 		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
+ 
+ 	/* mark TX mailbox as INACTIVE */
+-	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
+	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ 		      &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
+ 
+ 	/* acceptance mask/acceptance code (accept everything) */
+-	flexcan_write(0x0, &regs->rxgmask);
+-	flexcan_write(0x0, &regs->rx14mask);
+-	flexcan_write(0x0, &regs->rx15mask);
+	priv->write(0x0, &regs->rxgmask);
+	priv->write(0x0, &regs->rx14mask);
+	priv->write(0x0, &regs->rx15mask);
+ 
+ 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
+-		flexcan_write(0x0, &regs->rxfgmask);
+		priv->write(0x0, &regs->rxfgmask);
+ 
+ 	/* On Vybrid, disable memory error detection interrupts
+ 	 * and freeze mode.
+@@ -916,16 +931,16 @@ static int flexcan_chip_start(struct net
+ 		 * and Correction of Memory Errors" to write to
+ 		 * MECR register
+ 		 */
+-		reg_ctrl2 = flexcan_read(&regs->ctrl2);
+		reg_ctrl2 = priv->read(&regs->ctrl2);
+ 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
+-		flexcan_write(reg_ctrl2, &regs->ctrl2);
+		priv->write(reg_ctrl2, &regs->ctrl2);
+ 
+-		reg_mecr = flexcan_read(&regs->mecr);
+		reg_mecr = priv->read(&regs->mecr);
+ 		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
+-		flexcan_write(reg_mecr, &regs->mecr);
+		priv->write(reg_mecr, &regs->mecr);
+ 		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
+ 			      FLEXCAN_MECR_FANCEI_MSK);
+-		flexcan_write(reg_mecr, &regs->mecr);
+		priv->write(reg_mecr, &regs->mecr);
+ 	}
+ 
+ 	err = flexcan_transceiver_enable(priv);
+@@ -941,13 +956,13 @@ static int flexcan_chip_start(struct net
+ 
+ 	/* enable interrupts atomically */
+ 	disable_irq(dev->irq);
+-	flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
+-	flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+	priv->write(priv->reg_ctrl_default, &regs->ctrl);
+	priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+ 	enable_irq(dev->irq);
+ 
+ 	/* print chip status */
+ 	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
+-		   flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
+		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
+ 
+ 	return 0;
+ 
+@@ -972,8 +987,8 @@ static void flexcan_chip_stop(struct net
+ 	flexcan_chip_disable(priv);
+ 
+ 	/* Disable all interrupts */
+-	flexcan_write(0, &regs->imask1);
+-	flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+	priv->write(0, &regs->imask1);
+	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+ 		      &regs->ctrl);
+ 
+ 	flexcan_transceiver_disable(priv);
+@@ -1089,25 +1104,25 @@ static int register_flexcandev(struct ne
+ 	err = flexcan_chip_disable(priv);
+ 	if (err)
+ 		goto out_disable_per;
+-	reg = flexcan_read(&regs->ctrl);
+	reg = priv->read(&regs->ctrl);
+ 	reg |= FLEXCAN_CTRL_CLK_SRC;
+-	flexcan_write(reg, &regs->ctrl);
+	priv->write(reg, &regs->ctrl);
+ 
+ 	err = flexcan_chip_enable(priv);
+ 	if (err)
+ 		goto out_chip_disable;
+ 
+ 	/* set freeze, halt and activate FIFO, restrict register access */
+-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
+ 	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
+ 		FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
+-	flexcan_write(reg, &regs->mcr);
+	priv->write(reg, &regs->mcr);
+ 
+ 	/* Currently we only support newer versions of this core
+ 	 * featuring a RX FIFO. Older cores found on some Coldfire
+ 	 * derivates are not yet supported.
+ 	 */
+-	reg = flexcan_read(&regs->mcr);
+	reg = priv->read(&regs->mcr);
+ 	if (!(reg & FLEXCAN_MCR_FEN)) {
+ 		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
+ 		err = -ENODEV;
+@@ -1135,8 +1150,12 @@ static void unregister_flexcandev(struct
+ static const struct of_device_id flexcan_of_match[] = {
+ 	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
+ 	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
+	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
+	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
+	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
+ 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
+ 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
+	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
+ 	{ /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, flexcan_of_match);
+@@ -1213,6 +1232,21 @@ static int flexcan_probe(struct platform
+ 	dev->flags |= IFF_ECHO;
+ 
+ 	priv = netdev_priv(dev);
+
+	if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
+		priv->read = flexcan_read_be;
+		priv->write = flexcan_write_be;
+	} else {
+		if (of_device_is_compatible(pdev->dev.of_node,
+					    "fsl,p1010-flexcan")) {
+			priv->read = flexcan_read_be;
+			priv->write = flexcan_write_be;
+		} else {
+			priv->read = flexcan_read_le;
+			priv->write = flexcan_write_le;
+		}
+	}
+
+ 	priv->can.clock.freq = clock_freq;
+ 	priv->can.bittiming_const = &flexcan_bittiming_const;
+ 	priv->can.do_set_mode = flexcan_set_mode;
--- a/target/linux/layerscape/patches-4.9/820-kvm-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/820-kvm-support-layerscape.patch
@ -0,0 +1,239 @@
+From fe22151c95c02c6bb145ea6c3685941e8fb09d60 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:43:16 +0800
+Subject: [PATCH 32/32] kvm: support layerscape
+
+This is an integrated patch for layerscape kvm support.
+
+Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm/include/asm/kvm_mmu.h   |  3 +-
+ arch/arm/kvm/mmu.c               | 56 ++++++++++++++++++++++++++++++--
+ arch/arm64/include/asm/kvm_mmu.h | 14 ++++++--
+ virt/kvm/arm/vgic/vgic-its.c     | 24 +++++++++++---
+ virt/kvm/arm/vgic/vgic-v2.c      |  3 +-
+ 5 files changed, 88 insertions(+), 12 deletions(-)
+
+--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
+@@ -55,7 +55,8 @@ void stage2_unmap_vm(struct kvm *kvm);
+ int kvm_alloc_stage2_pgd(struct kvm *kvm);
+ void kvm_free_stage2_pgd(struct kvm *kvm);
+ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+-			  phys_addr_t pa, unsigned long size, bool writable);
+			  phys_addr_t pa, unsigned long size, bool writable,
+			  pgprot_t prot);
+ 
+ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+ 
+--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
+@@ -1020,9 +1020,11 @@ static int stage2_pmdp_test_and_clear_yo
+  * @guest_ipa:	The IPA at which to insert the mapping
+  * @pa:		The physical address of the device
+  * @size:	The size of the mapping
+ * @prot:	S2 page translation bits
+  */
+ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+-			  phys_addr_t pa, unsigned long size, bool writable)
+			  phys_addr_t pa, unsigned long size, bool writable,
+			  pgprot_t prot)
+ {
+ 	phys_addr_t addr, end;
+ 	int ret = 0;
+@@ -1033,7 +1035,7 @@ int kvm_phys_addr_ioremap(struct kvm *kv
+ 	pfn = __phys_to_pfn(pa);
+ 
+ 	for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
+-		pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
+		pte_t pte = pfn_pte(pfn, prot);
+ 
+ 		if (writable)
+ 			pte = kvm_s2pte_mkwrite(pte);
+@@ -1057,6 +1059,30 @@ out:
+ 	return ret;
+ }
+ 
+#ifdef CONFIG_ARM64
+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
+{
+	switch (pgprot_val(prot) & PTE_ATTRINDX_MASK) {
+		case PTE_ATTRINDX(MT_DEVICE_nGnRE):
+		case PTE_ATTRINDX(MT_DEVICE_nGnRnE):
+		case PTE_ATTRINDX(MT_DEVICE_GRE):
+			return PAGE_S2_DEVICE;
+		case PTE_ATTRINDX(MT_NORMAL_NC):
+		case PTE_ATTRINDX(MT_NORMAL):
+			return (pgprot_val(prot) & PTE_SHARED)
+				? PAGE_S2
+				: PAGE_S2_NS;
+	}
+
+	return PAGE_S2_DEVICE;
+}
+#else
+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
+{
+	return PAGE_S2_DEVICE;
+}
+#endif
+
+ static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
+ {
+ 	kvm_pfn_t pfn = *pfnp;
+@@ -1308,6 +1334,19 @@ static int user_mem_abort(struct kvm_vcp
+ 		hugetlb = true;
+ 		gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
+ 	} else {
+		if (!is_vm_hugetlb_page(vma)) {
+			pte_t *pte;
+			spinlock_t *ptl;
+			pgprot_t prot;
+
+			pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl);
+			prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
+			pte_unmap_unlock(pte, ptl);
+#ifdef CONFIG_ARM64
+			if (pgprot_val(prot) == pgprot_val(PAGE_S2_NS))
+				mem_type = PAGE_S2_NS;
+#endif
+		}
+ 		/*
+ 		 * Pages belonging to memslots that don't have the same
+ 		 * alignment for userspace and IPA cannot be mapped using
+@@ -1345,6 +1384,11 @@ static int user_mem_abort(struct kvm_vcp
+ 	if (is_error_noslot_pfn(pfn))
+ 		return -EFAULT;
+ 
+#ifdef CONFIG_ARM64
+	if (pgprot_val(mem_type) == pgprot_val(PAGE_S2_NS)) {
+		flags |= KVM_S2PTE_FLAG_IS_IOMAP;
+	} else
+#endif
+ 	if (kvm_is_device_pfn(pfn)) {
+ 		mem_type = PAGE_S2_DEVICE;
+ 		flags |= KVM_S2PTE_FLAG_IS_IOMAP;
+@@ -1882,6 +1926,9 @@ int kvm_arch_prepare_memory_region(struc
+ 			gpa_t gpa = mem->guest_phys_addr +
+ 				    (vm_start - mem->userspace_addr);
+ 			phys_addr_t pa;
+			pgprot_t prot;
+			pte_t *pte;
+			spinlock_t *ptl;
+ 
+ 			pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
+ 			pa += vm_start - vma->vm_start;
+@@ -1891,10 +1938,13 @@ int kvm_arch_prepare_memory_region(struc
+ 				ret = -EINVAL;
+ 				goto out;
+ 			}
+			pte = get_locked_pte(current->mm, mem->userspace_addr, &ptl);
+			prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
+			pte_unmap_unlock(pte, ptl);
+ 
+ 			ret = kvm_phys_addr_ioremap(kvm, gpa, pa,
+ 						    vm_end - vm_start,
+-						    writable);
+						    writable, prot);
+ 			if (ret)
+ 				break;
+ 		}
+--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
+@@ -167,7 +167,8 @@ void stage2_unmap_vm(struct kvm *kvm);
+ int kvm_alloc_stage2_pgd(struct kvm *kvm);
+ void kvm_free_stage2_pgd(struct kvm *kvm);
+ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+-			  phys_addr_t pa, unsigned long size, bool writable);
+			  phys_addr_t pa, unsigned long size, bool writable,
+			  pgprot_t prot);
+ 
+ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+ 
+@@ -274,8 +275,15 @@ static inline void __coherent_cache_gues
+ 
+ static inline void __kvm_flush_dcache_pte(pte_t pte)
+ {
+-	struct page *page = pte_page(pte);
+-	kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
+	if (pfn_valid(pte_pfn(pte))) {
+		struct page *page = pte_page(pte);
+		kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
+	} else {
+		void __iomem *va = ioremap_cache_ns(pte_pfn(pte) << PAGE_SHIFT, PAGE_SIZE);
+
+		kvm_flush_dcache_to_poc(va, PAGE_SIZE);
+		iounmap(va);
+	}
+ }
+ 
+ static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
+--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
+@@ -176,6 +176,8 @@ static struct its_itte *find_itte(struct
+ 
+ #define GIC_LPI_OFFSET 8192
+ 
+#define VITS_TYPER_DEVBITS 17
+
+ /*
+  * Finds and returns a collection in the ITS collection table.
+  * Must be called with the its_lock mutex held.
+@@ -375,7 +377,7 @@ static unsigned long vgic_mmio_read_its_
+ 	 * To avoid memory waste in the guest, we keep the number of IDBits and
+ 	 * DevBits low - as least for the time being.
+ 	 */
+-	reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
+	reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
+ 	reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
+ 
+ 	return extract_bytes(reg, addr & 7, len);
+@@ -601,16 +603,30 @@ static int vgic_its_cmd_handle_movi(stru
+  * Check whether an ID can be stored into the corresponding guest table.
+  * For a direct table this is pretty easy, but gets a bit nasty for
+  * indirect tables. We check whether the resulting guest physical address
+- * is actually valid (covered by a memslot and guest accessbible).
+ * is actually valid (covered by a memslot and guest accessible).
+  * For this we have to read the respective first level entry.
+  */
+-static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
+static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id)
+ {
+ 	int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
+	u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
+ 	int index;
+-	u64 indirect_ptr;
+ 	gfn_t gfn;
+ 
+	switch (type) {
+	case GITS_BASER_TYPE_DEVICE:
+		if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
+			return false;
+		break;
+	case GITS_BASER_TYPE_COLLECTION:
+		/* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
+		if (id >= BIT_ULL(16))
+			return false;
+		break;
+	default:
+		return false;
+	}
+
+ 	if (!(baser & GITS_BASER_INDIRECT)) {
+ 		phys_addr_t addr;
+ 
+--- a/virt/kvm/arm/vgic/vgic-v2.c
+++ b/virt/kvm/arm/vgic/vgic-v2.c
+@@ -290,7 +290,8 @@ int vgic_v2_map_resources(struct kvm *kv
+ 	if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
+ 		ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
+ 					    kvm_vgic_global_state.vcpu_base,
+-					    KVM_VGIC_V2_CPU_SIZE, true);
+					    KVM_VGIC_V2_CPU_SIZE, true,
+					    PAGE_S2_DEVICE);
+ 		if (ret) {
+ 			kvm_err("Unable to remap VGIC CPU to VCPU\n");
+ 			goto out;
--- a/target/linux/layerscape/patches-4.9/822-rgmii-fixed-link.patch
+++ b/target/linux/layerscape/patches-4.9/822-rgmii-fixed-link.patch
--- a/target/linux/mediatek/patches-4.14/0191-usb-xhci-allow-imod-interval-to-be-configurable.patch
+++ b/target/linux/mediatek/patches-4.14/0191-usb-xhci-allow-imod-interval-to-be-configurable.patch
@ -112,7 +112,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 		ret = PTR_ERR(hcd->usb_phy);
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
-@@ -597,11 +597,7 @@ int xhci_run(struct usb_hcd *hcd)
+@@ -612,11 +612,7 @@ int xhci_run(struct usb_hcd *hcd)
 			"// Set the interrupt modulation register");
 	temp = readl(&xhci->ir_set->irq_control);
 	temp &= ~ER_IRQ_INTERVAL_MASK;