From 5dacce1c4eea78ef10f2fee3b01e369626b1304a Mon Sep 17 00:00:00 2001 From: DHDAXCW Date: Mon, 24 Apr 2023 11:13:30 +0000 Subject: [PATCH] ??? --- .../boot/dts/rockchip/rk3568-hinlink-opc.dtsi | 21 ++++++----- .../boot/dts/rockchip/rk3568-opc-h68k.dts | 36 +++++++++---------- target/linux/rockchip/image/armv8.mk | 6 ++-- 3 files changed, 31 insertions(+), 32 deletions(-) diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi index b51efe99f..9a94c0775 100644 --- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi +++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi @@ -118,12 +118,13 @@ vin-supply = <&vcc5v0_usb>; }; - vcc3v3_pcie: vcc3v3-pcie { + vcc3v3_pcie: gpio-regulator { compatible = "regulator-fixed"; - enable-active-high; + regulator-name = "vcc3v3_pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; startup-delay-us = <5000>; vin-supply = <&vcc5v0_sys>; }; @@ -463,8 +464,12 @@ status = "okay"; }; +&pcie30phy { + status = "okay"; +}; + &pcie3x1 { - num-lanes = <1>; + rockchip,bifurcation; reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; @@ -474,15 +479,14 @@ #address-cells = <3>; #size-cells = <2>; - rtl8125_1: pcie-eth@10,0 { - compatible = "pci10ec,8125"; + rtl8125_1: pcie@10,0 { reg = <0x000000 0 0 0 0>; }; }; }; &pcie3x2 { - num-lanes = <1>; + rockchip,bifurcation; rockchip,init-delay-ms = <100>; reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; @@ -493,8 +497,7 @@ #address-cells = <3>; #size-cells = <2>; - rtl8125_2: pcie-eth@20,0 { - compatible = "pci10ec,8125"; + rtl8125_2: pcie@20,0 { reg = <0x000000 0 0 0 0>; }; }; diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts index 83a7d0a88..8a6045bc5 100644 --- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts +++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts @@ -16,20 +16,20 @@ }; &gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; + phy-mode = "rgmii"; clock_in_out = "output"; - phy-mode = "rgmii-id"; + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 20000 100000>; + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus>; - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x3c>; rx_delay = <0x2f>; phy-handle = <&rgmii_phy0>; @@ -37,20 +37,20 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; + phy-mode = "rgmii"; clock_in_out = "output"; - phy-mode = "rgmii-id"; + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 20000 100000>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; - snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x4f>; rx_delay = <0x26>; phy-handle = <&rgmii_phy1>; @@ -58,19 +58,15 @@ }; &mdio0 { - rgmii_phy0: ethernet-phy@0 { + rgmii_phy0: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; }; }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; }; -}; - -&vcc3v3_pcie { - gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; }; \ No newline at end of file diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 57a4a2668..fa10a8297 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -51,7 +51,7 @@ define Device/embedfire_lubancat2 SOC := rk3568 UBOOT_DEVICE_NAME := lubancat2-rk3568 IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core kmod-r8169 + DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core endef #TARGET_DEVICES += embedfire_lubancat2 @@ -71,9 +71,9 @@ define Device/hinlink_opc-h68k SOC := rk3568 UBOOT_DEVICE_NAME := opc-h68k-rk3568 IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata - DEVICE_PACKAGES := kmod-r8125 + DEVICE_PACKAGES := kmod-r8125 kmod-mt7921e kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core luci-app-usbmodem minicom fibocom-dial endef -#TARGET_DEVICES += hinlink_opc-h68k +# TARGET_DEVICES += hinlink_opc-h68k define Device/friendlyarm_nanopi-r2c DEVICE_VENDOR := FriendlyARM