Nanako/DHDAXCW-Rockchip-OpenWrt
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This commit is contained in:
DHDAXCW 2023-04-27 15:36:21 +00:00
parent c4d98eb916
commit 72817fc1ab
3 changed files with 34 additions and 26 deletions
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14
target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2n.dts
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@ -535,16 +535,13 @@
vpcie3v3-supply = <&vcc3v3_pcie>; vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay"; status = "okay";
pcie@10 { pcie@0,0 {
reg = <0x00100000 0 0 0 0>; reg = <0x00100000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
rtl8125_1: pcie-eth@10,0 { rtl8125_1: pcie@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>; reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
}; };
}; };
}; };
@ -555,16 +552,13 @@
vpcie3v3-supply = <&vcc3v3_pcie>; vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay"; status = "okay";
pcie@20 { pcie@0,0 {
reg = <0x00200000 0 0 0 0>; reg = <0x00200000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
rtl8125_2: pcie-eth@20,0 { rtl8125_2: pcie@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>; reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
}; };
}; };
}; };

34
target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
View File

@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h> #include <dt-bindings/leds/common.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h> #include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568-lubancat.dtsi" #include "rk3568-lubancat.dtsi"
@ -33,6 +34,19 @@
stdout-path = "serial2:1500000n8"; stdout-path = "serial2:1500000n8";
}; };
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&reset_button_pin>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <50>;
};
};
hdmi-con { hdmi-con {
compatible = "hdmi-connector"; compatible = "hdmi-connector";
type = "a"; type = "a";
@ -471,16 +485,13 @@
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
pcie@10 { pcie@0,0 {
reg = <0x00100000 0 0 0 0>; reg = <0x00100000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
rtl8125_1: pcie-eth@10,0 { rtl8125_1: pcie@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>; reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
}; };
}; };
}; };
@ -491,16 +502,13 @@
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
pcie@20 { pcie@0,0 {
reg = <0x00200000 0 0 0 0>; reg = <0x00200000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
rtl8125_2: pcie-eth@20,0 { rtl8125_2: pcie@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>; reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x4078>;
}; };
}; };
}; };
@ -551,6 +559,12 @@
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
}; };
}; };
gpio-key {
reset_button_pin: reset-button-pin {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
}; };
&pmu_io_domains { &pmu_io_domains {

12
target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
View File

@ -502,12 +502,12 @@
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
pcie@00 { pcie@0,0 {
reg = <0x00000000 0 0 0 0>; reg = <0x00100000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
r8125_1: pcie@01,0 { rtl8125_1: pcie@10,0 {
reg = <0x000000 0 0 0 0>; reg = <0x000000 0 0 0 0>;
}; };
}; };
@ -524,12 +524,12 @@
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
pcie@10 { pcie@0,0 {
reg = <0x00100000 0 0 0 0>; reg = <0x00200000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
r8125_2: pcie@10,0 { rtl8125_2: pcie@20,0 {
reg = <0x000000 0 0 0 0>; reg = <0x000000 0 0 0 0>;
}; };
}; };