Nanako/DHDAXCW-Rockchip-OpenWrt
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Update rk3568-lubancat2.dtsi

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骷髅头 2022-12-30 10:44:18 +08:00 committed by GitHub
parent d852f4f419
commit 8cfad22b98
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1 changed files with 4 additions and 4 deletions
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target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2.dtsi
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@ -115,7 +115,7 @@
compatible = "rockchip,rk3568-pcie"; compatible = "rockchip,rk3568-pcie";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
bus-range = <0x0 0xf>; bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>; <&cru CLK_PCIE30X2_AUX_NDFT>;
@ -138,7 +138,7 @@
num-ib-windows = <6>; num-ib-windows = <6>;
num-ob-windows = <2>; num-ob-windows = <2>;
max-link-speed = <3>; max-link-speed = <3>;
msi-map = <0x0 &gic 0x2000 0x1000>; msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>; num-lanes = <2>;
phys = <&pcie30phy>; phys = <&pcie30phy>;
phy-names = "pcie-phy"; phy-names = "pcie-phy";
@ -167,7 +167,7 @@
compatible = "rockchip,rk3568-pcie"; compatible = "rockchip,rk3568-pcie";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
bus-range = <0x0 0xf>; bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>; <&cru CLK_PCIE30X1_AUX_NDFT>;
@ -190,7 +190,7 @@
num-ib-windows = <6>; num-ib-windows = <6>;
num-ob-windows = <2>; num-ob-windows = <2>;
max-link-speed = <3>; max-link-speed = <3>;
msi-map = <0x0 &gic 0x1000 0x1000>; msi-map = <0x1000 &its 0x1000 0x1000>;
num-lanes = <1>; num-lanes = <1>;
phys = <&pcie30phy>; phys = <&pcie30phy>;
phy-names = "pcie-phy"; phy-names = "pcie-phy";