fix gmac0
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bd6ae62638
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8dc7a2a281
@ -23,3 +23,29 @@
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obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
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obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
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obj-$(CONFIG_LXT_PHY) += lxt.o
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obj-$(CONFIG_LXT_PHY) += lxt.o
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obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
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obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
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@@ -1730,7 +1730,7 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
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bsp_priv->ops->set_clock_selection(bsp_priv,
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bsp_priv->clock_input, true);
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- mdelay(5);
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+ usleep_range(100, 200);
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bsp_priv->clk_enabled = true;
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}
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} else {
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
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index 7c26394f6..3b9e4db37 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
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@@ -22,7 +22,7 @@ int dwmac4_dma_reset(void __iomem *ioaddr)
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return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
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!(value & DMA_BUS_MODE_SFT_RESET),
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- 10000, 1000000);
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+ 500, 1000000);
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}
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void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan)
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