diff --git a/README.md b/README.md
index cfa812893..f114ef85f 100644
--- a/README.md
+++ b/README.md
@@ -13,14 +13,13 @@ friendlyarm_nanopi-r4s
 friendlyarm_nanopi-r4se
 friendlyarm_nanopi-r5s
 friendlyarm_nanopi-r5c
-firefly_station-p2 停止支持，已移除
 hinlink_opc-h68k
+hinlink_opc-h69k
 ```
 
 ### Next plan to add equipment:
 ```
 hinlink_opc-h66k
-hinlink_opc-h69k
 ```
 How to compile the OpenWrt firmware you need
 -
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts
index b81063913..b18147f9e 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 // Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
 
@@ -73,4 +74,80 @@
 
 &vcc3v3_pcie {
 	gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
-};
\ No newline at end of file
+};
+=======
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
+
+/dts-v1/;
+
+#include "rk3568-hinlink-opc.dtsi"
+
+/ {
+	model = "HINLINK OPC-H68K Board";
+	compatible = "hinlink,opc-h68k", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &rtl8125_2;
+		ethernet3 = &rtl8125_1;
+	};
+};
+
+&gmac0 {
+        phy-mode = "rgmii";
+        clock_in_out = "output";
+        snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+        assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+        assigned-clock-rates = <0>, <125000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac0_miim
+                 &gmac0_tx_bus2
+                 &gmac0_rx_bus2
+                 &gmac0_rgmii_clk
+                 &gmac0_rgmii_bus>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
+};
+
+&gmac1 {
+        phy-mode = "rgmii";
+        clock_in_out = "output";
+        snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+        assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+        assigned-clock-rates = <0>, <125000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac1m1_miim
+                 &gmac1m1_tx_bus2
+                 &gmac1m1_rx_bus2
+                 &gmac1m1_rgmii_clk
+                 &gmac1m1_rgmii_bus>;
+	tx_delay = <0x4f>;
+	rx_delay = <0x26>;
+        phy-handle = <&rgmii_phy1>;
+        status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+>>>>>>> 271b198000bb77f61616b8185b83e6ac8ab186cb