From b62378dcb42f576539cb1da2b24b48eda9ac025a Mon Sep 17 00:00:00 2001 From: DHDAXCW Date: Fri, 19 Jul 2024 17:13:54 +0800 Subject: [PATCH] sync --- config/Config-kernel.in | 13 + doc/h68k.jpg | Bin 63089 -> 0 bytes doc/r1.jpg | Bin 51680 -> 0 bytes doc/star.png | Bin 167163 -> 0 bytes include/kernel-5.15 | 4 +- include/kernel-6.1 | 4 +- include/target.mk | 4 +- include/trusted-firmware-a.mk | 6 +- include/u-boot.mk | 35 +- package/base-files/files/bin/config_generate | 8 +- .../base-files/files/lib/upgrade/common.sh | 18 + package/base-files/files/lib/upgrade/stage2 | 3 +- package/firmware/ath11k-firmware/Makefile | 24 +- package/firmware/ath11k-wifi/Makefile | 94 - .../firmware/ath11k-wifi/board-2.bin.IPQ6018 | Bin 787208 -> 0 bytes .../board-edgecore-eap102.bin.IPQ8074 | Bin 131072 -> 0 bytes .../ath11k-wifi/board-gl-ax1800.bin.IPQ6018 | Bin 787208 -> 0 bytes .../ath11k-wifi/board-gl-axt1800.bin.IPQ6018 | Bin 787208 -> 0 bytes .../ath11k-wifi/qdss_trace_config.bin | 99 -- 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.../900-add-eth-ieee80211_bss_conf.patch | 55 + .../910-fix-build-for-kernel-5.10.patch | 20 - ...-channel-time-is-reset-by-ch_restore.patch | 58 - package/kernel/mac80211/realtek.mk | 172 +- package/kernel/mt76/Makefile | 28 +- .../patches-5.4/001-allow-vht-on-2g.patch | 59 + .../patches-5.4/002-fix-build-error.patch | 57 + .../mt76/patches-5.4/100-api_update.patch | 11 + ...ifi-mt76-ignore-key-disable-commands.patch | 301 ++++ .../patches-6.x/001-allow-vht-on-2g.patch | 59 + .../002-wifi-mt76-mt7915-fix-oops.patch | 100 ++ .../101-fixes-mt7925-build-error.patch | 23 + .../mt76/patches/001-allow-vht-on-2g.patch | 59 + .../mt76/patches/002-fix-page-pool.patch | 24 + package/kernel/rtw88-usb/Makefile | 105 ++ .../patches/001-fix-merge-error.patch | 96 + .../rtw88-usb/patches/101-wireless-6.1.patch | 432 +++++ .../rtw88-usb/patches/102-disable-pcie.patch | 69 + package/lean/autocore/files/x86/autocore | 2 - .../files/zzz-default-settings | 24 +- package/lean/r8101/Makefile | 39 + .../lean/r8101/patches/010-6.1-support.patch | 14 + package/utils/f2fs-tools/Makefile | 3 +- package/utils/lua/Makefile | 2 +- .../001-include-version-number.patch | 3 +- .../013-lnum-strtoul-parsing-fixes.patch | 11 +- .../lua/patches-host/100-no_readline.patch | 6 +- .../lua/patches-host/400-CVE-2014-5461.patch | 19 + .../patches/001-include-version-number.patch | 3 +- .../013-lnum-strtoul-parsing-fixes.patch | 11 +- .../utils/lua/patches/400-CVE-2014-5461.patch | 19 + package/wwan/luci-app-modem/Makefile | 1 - package/wwan/luci-app-sms-tool/LICENSE | 674 -------- package/wwan/luci-app-sms-tool/Makefile | 32 - .../luci-static/resources/icons/delsms.png | Bin 9221 -> 0 bytes .../luci-static/resources/icons/delsms2.png | Bin 1365 -> 0 bytes .../luasrc/controller/modem/sms.lua | 242 --- .../luasrc/model/cbi/modem/smsconfig.lua | 226 --- .../luasrc/view/modem/atcommands.htm | 136 -- .../luasrc/view/modem/readsms.htm | 285 --- .../luasrc/view/modem/sendsms.htm | 237 --- .../luasrc/view/modem/ussd.htm | 265 --- .../wwan/luci-app-sms-tool/po/pl/sms-tool.po | 288 --- .../luci-app-sms-tool/po/zh-cn/sms-tool.po | 246 --- .../root/etc/config/atcmds.user | 28 - .../root/etc/config/phonebook.user | 1 - .../root/etc/config/sms_tool | 14 - .../luci-app-sms-tool/root/etc/init.d/smsled | 26 - .../root/etc/uci-defaults/set_sms_ports.sh | 23 - .../root/etc/uci-defaults/start-smsled | 7 - .../luci-app-sms-tool/root/sbin/cronsync.sh | 21 - .../root/sbin/set_sms_ports.sh | 24 - .../root/sbin/smsled-init.sh | 21 - .../luci-app-sms-tool/root/sbin/smsled.sh | 39 - .../share/rpcd/acl.d/luci-app-sms-tool.json | 24 - target/linux/mediatek/Makefile | 4 +- .../lib/preinit/05_set_preinit_iface | 28 +- .../dts/mt7622-buffalo-wsr-2533dhp2.dts | 252 +-- .../dts/mt7622-buffalo-wsr-3200ax4s.dts | 175 ++ .../mediatek/dts/mt7622-buffalo-wsr.dtsi | 230 +++ .../mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi | 365 ++++ .../dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts | 63 + .../dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts | 78 + .../dts/mt7622-elecom-wrc-2533gent.dts | 2 +- .../dts/mt7622-elecom-wrc-x3200gst3.dts | 40 +- .../mediatek/dts/mt7622-linksys-e8450-ubi.dts | 88 +- .../mediatek/dts/mt7622-linksys-e8450.dts | 28 +- .../mediatek/dts/mt7622-linksys-e8450.dtsi | 17 +- .../mediatek/dts/mt7622-netgear-wax206.dts | 28 +- .../mediatek/dts/mt7622-reyee-ax3200-e5.dts | 96 + target/linux/mediatek/dts/mt7622-rfb1-ubi.dts | 4 +- .../mediatek/dts/mt7622-ruijie-rg-ew3200.dtsi | 240 +++ .../dts/mt7622-ruijie-rg-ew3200gx-pro.dts | 258 +-- .../mediatek/dts/mt7622-totolink-a8000ru.dts | 32 +- .../mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts | 35 +- .../dts/mt7622-ubnt-unifi-6-lr-v1.dts | 28 +- .../dts/mt7622-ubnt-unifi-6-lr-v1.dtsi | 25 + .../mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts | 35 +- .../dts/mt7622-ubnt-unifi-6-lr-v2.dts | 28 +- .../dts/mt7622-ubnt-unifi-6-lr-v2.dtsi | 26 + .../mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts | 89 + .../dts/mt7622-ubnt-unifi-6-lr-v3.dts | 100 ++ .../dts/mt7622-ubnt-unifi-6-lr-v3.dtsi | 50 + .../mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi | 25 - .../dts/mt7622-xiaomi-redmi-router-ax6s.dts | 52 +- .../mediatek/dts/mt7623a-unielec-u7623-02.dts | 22 + .../dts/mt7623a-unielec-u7623-02.dtsi | 6 +- .../mediatek/dts/mt7629-iptime-a6004mx.dts | 298 ++++ .../mediatek/dts/mt7629-netgear-ex6250-v2.dts | 242 +++ .../mediatek/dts/mt7629-tplink_eap225-v5.dts | 196 +++ ...3000.dts => mt7981a-comfast-cf-e393ax.dts} | 192 +- .../mediatek/dts/mt7981a-edgecore-eap111.dts | 201 +++ ...mt7981a-glinet-gl-x3000-xe3000-common.dtsi | 273 +++ .../mediatek/dts/mt7981a-glinet-gl-x3000.dts | 8 + .../mediatek/dts/mt7981a-glinet-gl-xe3000.dts | 23 + .../dts/mt7981a-ubnt-unifi-6-plus.dts | 170 ++ .../dts/mt7981b-cetron-ct3003-mod.dts | 23 - .../mediatek/dts/mt7981b-cetron-ct3003.dts | 29 +- .../dts/mt7981b-cmcc-rax3000m-emmc.dts | 42 - .../dts/mt7981b-cmcc-rax3000m-emmc.dtso | 43 + .../dts/mt7981b-cmcc-rax3000m-nand.dts | 92 - .../dts/mt7981b-cmcc-rax3000m-nand.dtso | 127 ++ .../mediatek/dts/mt7981b-cmcc-rax3000m.dts | 10 +- .../dts/mt7981b-confiabits-mt7981.dts | 296 ++++ .../mediatek/dts/mt7981b-cudy-m3000-v1.dts | 214 +++ .../mediatek/dts/mt7981b-cudy-re3000-v1.dts | 221 +++ .../mediatek/dts/mt7981b-cudy-tr3000-v1.dts | 232 +++ .../mediatek/dts/mt7981b-cudy-wr3000-v1.dts | 279 +++ .../mt7981b-dlink-aquila-pro-ai-m30-a1.dts | 310 ++++ .../mediatek/dts/mt7981b-fzs-5gcpe-p3.dts | 268 --- .../mediatek/dts/mt7981b-glinet-gl-mt2500.dts | 56 +- .../mediatek/dts/mt7981b-glinet-gl-mt3000.dts | 37 +- .../dts/mt7981b-h3c-magic-nx30-pro.dts | 15 +- .../mediatek/dts/mt7981b-jcg-q30-pro.dts | 42 +- .../mediatek/dts/mt7981b-nokia-ea0326gmp.dts | 189 +- .../dts/mt7981b-openembed-som7981.dts | 227 +++ .../mediatek/dts/mt7981b-openwrt-one.dts | 457 +++++ .../mediatek/dts/mt7981b-qihoo-360t7.dts | 15 +- .../mediatek/dts/mt7981b-routerich-ax3000.dts | 337 ++++ .../dts/mt7981b-unielec-u7981-01-emmc.dts | 99 ++ .../dts/mt7981b-unielec-u7981-01-nand.dts | 116 ++ .../dts/mt7981b-unielec-u7981-01.dtsi | 124 ++ .../dts/mt7981b-wavlink-wl-wn586x3.dts | 270 +++ .../mediatek/dts/mt7981b-xiaomi-ax3000t.dts | 49 - ...981b-xiaomi-mi-router-ax3000t-ubootmod.dts | 16 + .../dts/mt7981b-xiaomi-mi-router-ax3000t.dts | 34 + .../dts/mt7981b-xiaomi-mi-router-ax3000t.dtsi | 29 + ...i => mt7981b-xiaomi-mi-router-common.dtsi} | 228 +-- .../mt7981b-xiaomi-mi-router-wr30u-stock.dts | 34 + ...t7981b-xiaomi-mi-router-wr30u-ubootmod.dts | 16 + .../dts/mt7981b-xiaomi-mi-router-wr30u.dtsi | 23 + .../mediatek/dts/mt7981b-xiaomi-wr30u.dts | 35 - .../mediatek/dts/mt7981b-yuncore-ax835.dts | 257 +++ .../dts/mt7981b-zbtlink-zbt-z8102ax.dts | 326 ++++ ...01.dts => mt7981b-zbtlink-zbt-z8103ax.dts} | 148 +- .../dts/mt7981b-zyxel-nwa50ax-pro.dts | 229 +++ .../dts/mt7986a-acelink-ew-7886cax.dts | 238 +++ .../mediatek/dts/mt7986a-acer-predator-w6.dts | 507 ++++++ .../mediatek/dts/mt7986a-asus-rt-ax59u.dts | 309 ++++ .../mediatek/dts/mt7986a-asus-tuf-ax4200.dts | 75 +- .../mediatek/dts/mt7986a-asus-tuf-ax6000.dts | 435 +++++ .../dts/mt7986a-bananapi-bpi-r3-mini.dts | 715 ++++++++ .../mediatek/dts/mt7986a-glinet-gl-mt6000.dts | 60 +- .../mediatek/dts/mt7986a-hf-m7986r1-emmc.dts | 100 -- .../mediatek/dts/mt7986a-hf-m7986r1-nand.dts | 76 - .../mediatek/dts/mt7986a-hf-m7986r1.dtsi | 251 --- ...cs-05.dts => mt7986a-jdcloud-re-cp-03.dts} | 306 ++-- .../mediatek/dts/mt7986a-netcore-n60.dts | 36 +- .../dts/mt7986a-ruijie-rg-x60-pro.dts | 42 +- .../mediatek/dts/mt7986a-smartrg-SDG-8612.dts | 76 + .../mediatek/dts/mt7986a-smartrg-SDG-8614.dts | 124 ++ .../mediatek/dts/mt7986a-smartrg-SDG-8622.dts | 38 + .../mediatek/dts/mt7986a-smartrg-SDG-8632.dts | 38 + .../dts/mt7986a-smartrg-bonanza-peak.dtsi | 481 ++++++ .../dts/mt7986a-tplink-tl-xdr-common.dtsi | 56 +- .../dts/mt7986a-tplink-tl-xdr4288.dts | 9 +- .../dts/mt7986a-tplink-tl-xdr6086.dts | 1 - .../dts/mt7986a-tplink-tl-xdr6088.dts | 9 +- .../dts/mt7986a-tplink-tl-xtr8488.dts | 228 --- ...7986a-xiaomi-redmi-router-ax6000-stock.dts | 39 + ...6a-xiaomi-redmi-router-ax6000-ubootmod.dts | 28 + ...> mt7986a-xiaomi-redmi-router-ax6000.dtsi} | 70 +- .../dts/mt7986a-zyxel-ex5601-t0-common.dtsi | 435 +++++ .../dts/mt7986a-zyxel-ex5601-t0-stock.dts | 119 ++ .../dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts | 101 ++ .../dts/mt7986a-zyxel-ex5700-telenor.dts | 375 ++++ .../dts/mt7986b-mercusys-mr90x-v1.dts | 286 +++ .../mediatek/dts/mt7986b-netgear-wax220.dts | 293 ++++ .../mediatek/dts/mt7986b-tplink-re6000xd.dts | 298 ++++ .../mediatek/dts/mt7988a-smartrg-SDG-8733.dts | 17 + .../mediatek/dts/mt7988a-smartrg-SDG-8734.dts | 57 + .../dts/mt7988a-smartrg-mt-stuart.dtsi | 682 ++++++++ .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 801 --------- .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 - .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 - .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 63 - .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 501 ------ .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 52 - .../dts/mediatek/mt7986a-rfb-spim-nor.dts | 51 - .../arm64/boot/dts/mediatek/mt7986a-rfb.dtsi | 390 ----- .../arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 645 ------- .../arm64/boot/dts/mediatek/mt7986b-rfb.dts | 195 --- .../arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 15 - .../boot/dts/mediatek/mt7988a-rfb-emmc.dtso | 33 - .../dts/mediatek/mt7988a-rfb-eth1-aqr.dtso | 41 - .../mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso | 30 - .../dts/mediatek/mt7988a-rfb-eth1-mxl.dtso | 39 - .../dts/mediatek/mt7988a-rfb-eth1-sfp.dtso | 47 - .../dts/mediatek/mt7988a-rfb-eth2-aqr.dtso | 41 - .../dts/mediatek/mt7988a-rfb-eth2-mxl.dtso | 39 - .../dts/mediatek/mt7988a-rfb-eth2-sfp.dtso | 47 - .../boot/dts/mediatek/mt7988a-rfb-sd.dtso | 31 - .../dts/mediatek/mt7988a-rfb-snfi-nand.dtso | 69 - .../dts/mediatek/mt7988a-rfb-spim-nand.dtso | 64 - .../dts/mediatek/mt7988a-rfb-spim-nor.dtso | 59 - .../arm64/boot/dts/mediatek/mt7988a-rfb.dts | 200 --- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 1441 ---------------- .../drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 -- .../drivers/clk/mediatek/clk-mt7981-eth.c | 139 -- .../clk/mediatek/clk-mt7981-infracfg.c | 235 --- .../clk/mediatek/clk-mt7981-topckgen.c | 450 ----- .../drivers/clk/mediatek/clk-mt7986-apmixed.c | 100 -- .../drivers/clk/mediatek/clk-mt7986-eth.c | 132 -- .../clk/mediatek/clk-mt7986-infracfg.c | 224 --- .../clk/mediatek/clk-mt7986-topckgen.c | 342 ---- .../drivers/clk/mediatek/clk-mt7988-apmixed.c | 113 -- .../drivers/clk/mediatek/clk-mt7988-eth.c | 299 ---- .../clk/mediatek/clk-mt7988-infracfg.c | 406 ----- .../clk/mediatek/clk-mt7988-topckgen.c | 522 ------ .../drivers/net/phy/mediatek-2p5ge.c | 262 --- .../drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1041 ----------- .../drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1011 ----------- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1466 ---------------- .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 --- .../dt-bindings/clock/mediatek,mt7988-clk.h | 276 --- .../include/dt-bindings/clock/mt7986-clk.h | 169 -- .../include/dt-bindings/reset/mt7986-resets.h | 55 - .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 808 --------- .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 52 - .../dts/mediatek/mt7986a-rfb-spim-nor.dts | 51 - .../arm64/boot/dts/mediatek/mt7986a-rfb.dtsi | 389 ----- .../boot/dts/mediatek/mt7988a-rfb-emmc.dtso | 33 - .../dts/mediatek/mt7988a-rfb-eth1-aqr.dtso | 41 - .../mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso | 30 - .../dts/mediatek/mt7988a-rfb-eth1-mxl.dtso | 39 - .../dts/mediatek/mt7988a-rfb-eth1-sfp.dtso | 47 - .../dts/mediatek/mt7988a-rfb-eth2-aqr.dtso | 41 - .../dts/mediatek/mt7988a-rfb-eth2-mxl.dtso | 39 - .../dts/mediatek/mt7988a-rfb-eth2-sfp.dtso | 47 - .../boot/dts/mediatek/mt7988a-rfb-sd.dtso | 31 - .../dts/mediatek/mt7988a-rfb-snfi-nand.dtso | 69 - .../dts/mediatek/mt7988a-rfb-spim-nand.dtso | 64 - .../dts/mediatek/mt7988a-rfb-spim-nor.dtso | 59 - .../arm64/boot/dts/mediatek/mt7988a-rfb.dts | 200 --- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 1441 ---------------- .../drivers/clk/mediatek/clk-mt7988-apmixed.c | 113 -- .../drivers/clk/mediatek/clk-mt7988-eth.c | 141 -- .../clk/mediatek/clk-mt7988-infracfg.c | 376 ---- .../clk/mediatek/clk-mt7988-topckgen.c | 446 ----- .../drivers/net/phy/mediatek-2p5ge.c | 262 --- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1466 ---------------- .../dt-bindings/clock/mediatek,mt7988-clk.h | 276 --- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 14 +- .../mediatek/files/block/partitions/fit.c | 2 +- .../files/drivers/net/phy/mtk/mt753x/Kconfig | 3 - .../files/drivers/net/phy/mtk/mt753x/Makefile | 11 - .../files/drivers/net/phy/mtk/mt753x/mt7530.c | 631 ------- .../files/drivers/net/phy/mtk/mt753x/mt7530.h | 13 - .../files/drivers/net/phy/mtk/mt753x/mt7531.c | 918 ---------- .../files/drivers/net/phy/mtk/mt753x/mt7531.h | 13 - .../files/drivers/net/phy/mtk/mt753x/mt753x.h | 213 --- .../net/phy/mtk/mt753x/mt753x_common.c | 90 - .../drivers/net/phy/mtk/mt753x/mt753x_mdio.c | 597 ------- .../drivers/net/phy/mtk/mt753x/mt753x_nl.c | 382 ---- .../drivers/net/phy/mtk/mt753x/mt753x_nl.h | 43 - .../drivers/net/phy/mtk/mt753x/mt753x_regs.h | 294 ---- .../net/phy/mtk/mt753x/mt753x_swconfig.c | 510 ------ .../net/phy/mtk/mt753x/mt753x_swconfig.h | 29 - .../drivers/net/phy/mtk/mt753x/mt753x_vlan.c | 183 -- .../drivers/net/phy/mtk/mt753x/mt753x_vlan.h | 40 - .../files/drivers/net/phy/rtk/rtl8367c/acl.c | 30 +- .../files/drivers/net/phy/rtk/rtl8367c/cpu.c | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/igmp.c | 10 +- .../net/phy/rtk/rtl8367c/include/acl.h | 32 +- .../net/phy/rtk/rtl8367c/include/cpu.h | 6 +- .../net/phy/rtk/rtl8367c/include/dot1x.h | 2 +- .../net/phy/rtk/rtl8367c/include/eee.h | 2 +- .../net/phy/rtk/rtl8367c/include/i2c.h | 2 +- .../net/phy/rtk/rtl8367c/include/igmp.h | 12 +- .../net/phy/rtk/rtl8367c/include/interrupt.h | 2 +- .../drivers/net/phy/rtk/rtl8367c/include/l2.h | 50 +- .../net/phy/rtk/rtl8367c/include/leaky.h | 2 +- .../net/phy/rtk/rtl8367c/include/led.h | 20 +- .../net/phy/rtk/rtl8367c/include/mirror.h | 8 +- .../net/phy/rtk/rtl8367c/include/port.h | 34 +- .../net/phy/rtk/rtl8367c/include/ptp.h | 4 +- .../net/phy/rtk/rtl8367c/include/qos.h | 8 +- .../net/phy/rtk/rtl8367c/include/rate.h | 2 +- .../net/phy/rtk/rtl8367c/include/rtk_error.h | 8 +- .../net/phy/rtk/rtl8367c/include/rtk_switch.h | 8 +- .../net/phy/rtk/rtl8367c/include/rtk_types.h | 4 +- .../include/rtl8367c_asicdrv_cputag.h | 2 +- .../rtl8367c/include/rtl8367c_asicdrv_green.h | 2 +- .../rtl8367c/include/rtl8367c_asicdrv_qos.h | 2 +- .../rtl8367c_asicdrv_unknownMulticast.h | 2 +- .../phy/rtk/rtl8367c/include/rtl8367c_base.h | 2 +- .../phy/rtk/rtl8367c/include/rtl8367c_reg.h | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/l2.c | 48 +- .../files/drivers/net/phy/rtk/rtl8367c/led.c | 16 +- .../drivers/net/phy/rtk/rtl8367c/mirror.c | 4 +- .../files/drivers/net/phy/rtk/rtl8367c/port.c | 38 +- .../files/drivers/net/phy/rtk/rtl8367c/ptp.c | 2 +- .../files/drivers/net/phy/rtk/rtl8367c/qos.c | 8 +- .../files/drivers/net/phy/rtk/rtl8367c/rldp.c | 4 +- .../drivers/net/phy/rtk/rtl8367c/rtk_switch.c | 10 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c | 34 +- .../rtk/rtl8367c/rtl8367c_asicdrv_cputag.c | 26 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c | 18 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c | 4 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c | 16 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c | 2 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c | 20 +- .../rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c | 4 +- .../rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c | 4 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c | 2 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c | 60 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c | 18 +- .../phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c | 8 +- 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target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch delete mode 100644 target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch delete mode 100644 target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch delete mode 100644 target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch delete mode 100644 target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch delete mode 100644 target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch delete mode 100644 target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch delete mode 100644 target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch delete mode 100644 target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch diff --git a/config/Config-kernel.in b/config/Config-kernel.in index 2b904b57f..f7a8d5181 100644 --- a/config/Config-kernel.in +++ b/config/Config-kernel.in @@ -50,6 +50,11 @@ config KERNEL_ARM_PMU default n depends on (arm || aarch64) +config KERNEL_ARM_PMUV3 + bool + default y if TARGET_armsr_armv8 + depends on (arm_v7 || aarch64) && LINUX_6_6 + config KERNEL_RISCV_PMU bool select KERNEL_RISCV_PMU_SBI @@ -81,6 +86,7 @@ config KERNEL_PERF_EVENTS bool "Compile the kernel with performance events and counters" default n select KERNEL_ARM_PMU if (arm || aarch64) + select KERNEL_ARM_PMUV3 if (arm_v7 || aarch64) && LINUX_6_6 select KERNEL_RISCV_PMU if riscv64 config KERNEL_PROFILING @@ -1145,6 +1151,13 @@ config KERNEL_NET_L3_MASTER_DEV This module provides glue between core networking code and device drivers to support L3 master devices like VRF. +config KERNEL_XDP_SOCKETS + bool "XDP sockets support" + default y if KERNEL_DEBUG_INFO_BTF + help + XDP sockets allows a channel between XDP programs and + userspace applications. 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z?1HAut?l-a^#87jL$!iSvhYegz!`pZ0w~ySFjzIlT+l~*jg{}9pOx0|$E-p8{T3N^&VbBL=e?S7cMX`GUkBp`Pn!o%tE@E8 zA!scxe(-aR?+eZ_LKf4L@MPgtq41G8{^-C( z@3(QwfAUNha%#TM)e)s4{CfZ$d*t+0_8`FqlD4O4=BMUyeV5V0#`>`Or+opWpY=F( z>nnjhq)GmjcSi3Tf~1HIP8l3LEr?i_x3Q!YZW2W*?3jST`4^phy>9SozvrEevG?JS zaYY(L)uYe^H@0$Q%;c;gq6&5U8O=y`e%;Al1pvnKpE*eUcSlgqq`FXs@UIO#-9VeH zs{5apBw=c|!6Z>j3LGO5{{L`7|A+sF!TonSqs{-eGQeiT|6eWi|CbYNZUCGJ_|s+y VEvMMB7aH)RsjjP5rDF5$e*vdk(P01p diff --git a/include/kernel-5.15 b/include/kernel-5.15 index a03ed80f9..02ccce117 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .161 -LINUX_KERNEL_HASH-5.15.161 = d629f78680dc4b65e3d78b61406fb7757b960c83c206e63ad8c2606b3e3c474c +LINUX_VERSION-5.15 = .162 +LINUX_KERNEL_HASH-5.15.162 = 91bfc0ea152ce7b102a0b79d35a7c92843874ebf085c99d2ba8b4d85e62b1a7c diff --git a/include/kernel-6.1 b/include/kernel-6.1 index e8acd5ca1..1f97e8f30 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .96 -LINUX_KERNEL_HASH-6.1.96 = 3e77c9069de5e7ab02ff9c2dcfe77dab193613fc1de21071901b4153374862a9 +LINUX_VERSION-6.1 = .98 +LINUX_KERNEL_HASH-6.1.98 = 97cdc9127c7700556ea0891267a0c24cf372f4b81636fb8203a914f3a69f3406 diff --git a/include/target.mk b/include/target.mk index e5c064759..f59661f62 100644 --- a/include/target.mk +++ b/include/target.mk @@ -53,9 +53,9 @@ DEFAULT_PACKAGES.nas:=\ mdadm # For router targets DEFAULT_PACKAGES.router:=\ - dnsmasq-full firewall iptables ppp ppp-mod-pppoe \ + dnsmasq-full firewall iptables ppp ppp-mod-pppoe odhcp6c odhcpd-ipv6only \ block-mount coremark kmod-nf-nathelper kmod-nf-nathelper-extra kmod-ipt-raw kmod-tun \ - iptables-mod-tproxy iptables-mod-extra ipset ip-full default-settings luci \ + iptables-mod-tproxy iptables-mod-extra ipset ip-full default-settings luci luci-proto-ipv6 \ ddns-scripts_aliyun ddns-scripts_dnspod luci-app-ddns luci-app-upnp luci-app-autoreboot \ luci-app-arpbind luci-app-filetransfer luci-app-vsftpd luci-app-ssr-plus luci-app-vlmcsd \ luci-app-accesscontrol luci-app-nlbwmon luci-app-turboacc luci-app-wol curl ca-certificates diff --git a/include/trusted-firmware-a.mk b/include/trusted-firmware-a.mk index e469dae98..0c0118e09 100644 --- a/include/trusted-firmware-a.mk +++ b/include/trusted-firmware-a.mk @@ -63,11 +63,9 @@ define Build/Trusted-Firmware-A/Target URL:=https://www.trustedfirmware.org/projects/tf-a/ endef - ifndef Package/trusted-firmware-a-$(1)/install - define Package/trusted-firmware-a-$(1)/install + define Package/trusted-firmware-a-$(1)/install $$(Package/trusted-firmware-a/install) - endef - endif + endef endef define Build/Configure/Trusted-Firmware-A diff --git a/include/u-boot.mk b/include/u-boot.mk index 454880989..d824d97ff 100644 --- a/include/u-boot.mk +++ b/include/u-boot.mk @@ -1,5 +1,3 @@ -include $(INCLUDE_DIR)/prereq.mk - PKG_NAME ?= u-boot ifndef PKG_SOURCE_PROTO @@ -20,31 +18,6 @@ PKG_LICENSE_FILES:=Licenses/README PKG_BUILD_PARALLEL ?= 1 -ifdef UBOOT_USE_BINMAN - $(eval $(call TestHostCommand,python3-pyelftools, \ - Please install the Python3 elftools module, \ - $(STAGING_DIR_HOST)/bin/python3 -c 'import elftools')) -endif - -ifdef UBOOT_USE_INTREE_DTC - $(eval $(call TestHostCommand,python3-dev, \ - Please install the python3-dev package, \ - python3.11-config --includes 2>&1 | grep 'python3', \ - python3.10-config --includes 2>&1 | grep 'python3', \ - python3.9-config --includes 2>&1 | grep 'python3', \ - python3.8-config --includes 2>&1 | grep 'python3', \ - python3.7-config --includes 2>&1 | grep 'python3', \ - python3-config --includes 2>&1 | grep -E 'python3\.([7-9]|[0-9][0-9])\.?')) - - $(eval $(call TestHostCommand,python3-setuptools, \ - Please install the Python3 setuptools module, \ - $(STAGING_DIR_HOST)/bin/python3 -c 'import setuptools')) - - $(eval $(call TestHostCommand,swig, \ - Please install the swig package, \ - swig -version)) -endif - export GCC_HONOUR_COPTS=s define Package/u-boot/install/default @@ -69,7 +42,6 @@ endef TARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET)) UBOOT_MAKE_FLAGS = \ - PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \ HOSTCC="$(HOSTCC)" \ HOSTCFLAGS="$(HOST_CFLAGS) $(HOST_CPPFLAGS) -std=gnu11" \ HOSTLDFLAGS="$(HOST_LDFLAGS)" \ @@ -111,14 +83,9 @@ endef define Build/Configure/U-Boot +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) $(UBOOT_CONFIG)_config - $(if $(strip $(UBOOT_CUSTOMIZE_CONFIG)), - $(PKG_BUILD_DIR)/scripts/config --file $(PKG_BUILD_DIR)/.config $(UBOOT_CUSTOMIZE_CONFIG) - +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) oldconfig) endef -ifndef UBOOT_USE_INTREE_DTC - DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc) -endif +DTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc) define Build/Compile/U-Boot +$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \ diff --git a/package/base-files/files/bin/config_generate b/package/base-files/files/bin/config_generate index 4c83b49f7..a9ca4d5b2 100755 --- a/package/base-files/files/bin/config_generate +++ b/package/base-files/files/bin/config_generate @@ -305,10 +305,10 @@ generate_static_system() { set system.ntp='timeserver' set system.ntp.enabled='1' set system.ntp.enable_server='1' - add_list system.ntp.server='ntp.aliyun.com' - add_list system.ntp.server='time1.cloud.tencent.com' - add_list system.ntp.server='time.ustc.edu.cn' - add_list system.ntp.server='cn.pool.ntp.org' + add_list system.ntp.server='time.apple.com' + add_list system.ntp.server='time.google.com' + add_list system.ntp.server='time.windows.com' + add_list system.ntp.server='time.cloudflare.com' EOF if json_is_a system object; then diff --git a/package/base-files/files/lib/upgrade/common.sh b/package/base-files/files/lib/upgrade/common.sh index af1182cb1..ef8d01e16 100644 --- a/package/base-files/files/lib/upgrade/common.sh +++ b/package/base-files/files/lib/upgrade/common.sh @@ -165,6 +165,23 @@ part_magic_fat() { [ "$magic" = "FAT" ] || [ "$magic_fat32" = "FAT32" ] } +fitblk_get_bootdev() { + [ -e /sys/firmware/devicetree/base/chosen/rootdisk ] || return + + local rootdisk="$(cat /sys/firmware/devicetree/base/chosen/rootdisk)" + local handle bootdev + for handle in /sys/class/block/*/of_node/phandle /sys/class/block/*/device/of_node/phandle; do + [ ! -e "$handle" ] && continue + if [ "$rootdisk" = "$(cat $handle)" ]; then + bootdev="${handle%/of_node/phandle}" + bootdev="${bootdev%/device}" + bootdev="${bootdev#/sys/class/block/}" + echo "$bootdev" + break + fi + done +} + export_bootdevice() { local cmdline uuid blockdev uevent line class local MAJOR MINOR DEVNAME DEVTYPE @@ -196,6 +213,7 @@ export_bootdevice() { done ;; /dev/*) + [ "$rootpart" = "/dev/fit0" ] && rootpart="$(fitblk_get_bootdev)" uevent="/sys/class/block/${rootpart##*/}/../uevent" ;; 0x[a-f0-9][a-f0-9][a-f0-9] | 0x[a-f0-9][a-f0-9][a-f0-9][a-f0-9] | \ diff --git a/package/base-files/files/lib/upgrade/stage2 b/package/base-files/files/lib/upgrade/stage2 index da84698dd..c6bb150f5 100755 --- a/package/base-files/files/lib/upgrade/stage2 +++ b/package/base-files/files/lib/upgrade/stage2 @@ -45,7 +45,8 @@ switch_to_ramfs() { mtd partx losetup mkfs.ext4 nandwrite flash_erase \ ubiupdatevol ubiattach ubiblock ubiformat \ ubidetach ubirsvol ubirmvol ubimkvol \ - snapshot snapshot_tool date \ + snapshot snapshot_tool date logger \ + /usr/sbin/fw_printenv /usr/bin/fwtool \ $RAMFS_COPY_LOSETUP $RAMFS_COPY_LVM \ $RAMFS_COPY_BIN do diff --git a/package/firmware/ath11k-firmware/Makefile b/package/firmware/ath11k-firmware/Makefile index ea4977aa6..0e1c548e2 100644 --- a/package/firmware/ath11k-firmware/Makefile +++ b/package/firmware/ath11k-firmware/Makefile @@ -8,9 +8,9 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ath11k-firmware -PKG_SOURCE_DATE:=2023-08-22 -PKG_SOURCE_VERSION:=d8f82a98ff1aef330d65d8b5660b46d1a9809ee3 -PKG_MIRROR_HASH:=3dba19449758c3b17f117990d7ad4086554e012b579f1de16e9d9196a7fbaaa7 +PKG_SOURCE_DATE:=2023-03-31 +PKG_SOURCE_VERSION:=a039049a9349722fa5c74185452ab04644a0d351 +PKG_MIRROR_HASH:=ed401e3f6e91d70565b3396139193f7e815f410db93700697205ac8ed1b828c5 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git @@ -32,6 +32,11 @@ define Package/ath11k-firmware-default DEPENDS:= endef +define Package/ath11k-firmware-ipq6018 +$(Package/ath11k-firmware-default) + TITLE:=IPQ6018 ath11k firmware +endef + define Package/ath11k-firmware-ipq8074 $(Package/ath11k-firmware-default) TITLE:=IPQ8074 ath11k firmware @@ -57,21 +62,30 @@ define Download/qcn9074-board endef $(eval $(call Download,qcn9074-board)) +define Package/ath11k-firmware-ipq6018/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ6018 + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ6018/hw1.0 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ath11k-firmware/IPQ6018/hw1.0/2.5.0.1/WLAN.HK.2.5.0.1-01208-QCAHKSWPL_SILICONZ-1/* \ + $(1)/lib/firmware/IPQ6018/ +endef + define Package/ath11k-firmware-ipq8074/install $(INSTALL_DIR) $(1)/lib/firmware/IPQ8074 $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ath11k-firmware/IPQ8074/hw2.0/2.9.0.1/WLAN.HK.2.9.0.1-01890-QCAHKSWPL_SILICONZ-1/* \ + $(PKG_BUILD_DIR)/ath11k-firmware/IPQ8074/hw2.0/testing/2.9.0.1/WLAN.HK.2.9.0.1-01385-QCAHKSWPL_SILICONZ-1/* \ $(1)/lib/firmware/IPQ8074/ endef define Package/ath11k-firmware-qcn9074/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0 $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ath11k-firmware/QCN9074/hw1.0/2.9.0.1/WLAN.HK.2.9.0.1-01890-QCAHKSWPL_SILICONZ-1/* \ + $(PKG_BUILD_DIR)/ath11k-firmware/QCN9074/hw1.0/testing/2.9.0.1/WLAN.HK.2.9.0.1-01385-QCAHKSWPL_SILICONZ-1/* \ $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ $(INSTALL_BIN) \ $(DL_DIR)/$(QCN9074_BOARD_FILE) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board-2.bin endef +$(eval $(call BuildPackage,ath11k-firmware-ipq6018)) $(eval $(call BuildPackage,ath11k-firmware-ipq8074)) $(eval $(call BuildPackage,ath11k-firmware-qcn9074)) diff --git a/package/firmware/ath11k-wifi/Makefile b/package/firmware/ath11k-wifi/Makefile deleted file mode 100644 index 2c33df970..000000000 --- a/package/firmware/ath11k-wifi/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/version.mk - -PKG_NAME:=ath11k-wifi -PKG_RELEASE:=1 -PKG_FLAGS:=nonshared - -include $(INCLUDE_DIR)/package.mk - -define Build/Prepare - mkdir -p $(PKG_BUILD_DIR) -endef - -define Build/Compile -endef - -# Use ath10k-bdencoder from https://github.com/qca/qca-swiss-army-knife.git -# to generate the board-* files here. -# -# This is intended to be used on an interim basis until device-specific -# board data for new devices is available through the upstream compilation -# -# Please send a mail with your device-specific board files upstream. -# You can find instructions and examples on the linux-wireless wiki: -# - -ALLWIFIBOARDS:= \ - edgecore-eap102 \ - gl-ax1800 \ - gl-axt1800 \ - qihoo_v6 - -ALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ath11k-wifi-$(BOARD)) - -define Package/ath11k-wifi-default - SUBMENU:=ath11k Board-Specific Overrides - SECTION:=firmware - CATEGORY:=Firmware - DEPENDS:=@TARGET_ipq60xx - TITLE:=Custom Board -endef - -define ath11k-wifi-install-one-to - $(INSTALL_DIR) $(2)/lib/firmware/ath11k/$(3)/ - $(INSTALL_DATA) $(1) $(2)/lib/firmware/ath11k/$(3)/board-2.bin -endef - -define ath11k-wifi-install-one - $(if $(filter $(suffix $(1)),.IPQ6018 .ipq6018),\ - $(call ath11k-wifi-install-one-to,$(1),$(2),IPQ6018/hw1.0),\ - $(error Unrecognized board-file suffix '$(suffix $(1))' for '$(1)')\ - ) - -endef -# Blank line required at end of above define due to foreach context - -define generate-ath11k-wifi-package - define Package/ath11k-wifi-$(1) - $(call Package/ath11k-wifi-default) - TITLE:=board-2.bin Overrides for $(2) - CONFLICTS:=$(PREV_BOARD) - endef - - define Package/ath11k-wifi-$(1)/description -The $(2) requires board-specific, reference ("cal") data -that is not yet present in the upstream wireless firmware distribution. - -This package supplies board-2.bin file(s) that, in the interim, -overwrite those supplied by the ath10k-firmware-* packages. - -This is package is only necessary for the $(2). - -Do not install it for any other device! - endef - - define Package/ath11k-wifi-$(1)/install-overlay - $$$$(foreach IPQ_WIFI_BOARD_FILE,$$$$(wildcard board-$(1).*),\ - $$$$(call ath11k-wifi-install-one,$$$$(IPQ_WIFI_BOARD_FILE),$$(1))) - endef - - PREV_BOARD+=ath11k-wifi-$(1) -endef - -# Add board name to ALLWIFIBOARDS -# Place files in this directory as board-. -# Add $(eval $(call generate-ath11k-wifi-package,,)) - -$(eval $(call generate-ath11k-wifi-package,edgecore-eap102,Edgecore EAP102)) -$(eval $(call generate-ath11k-wifi-package,gl-ax1800,Gl.iNET AX1800)) -$(eval $(call generate-ath11k-wifi-package,gl-axt1800,Gl.iNET AXT1800)) -$(eval $(call generate-ath11k-wifi-package,qihoo_v6,QIHOO 360V6)) - - -$(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE)))) diff --git a/package/firmware/ath11k-wifi/board-2.bin.IPQ6018 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UMAC,MAC0,MAC1 -//seq_start; -//seq_type:mem_req; -//memory size always given in KB. beow example reserves 3 buffers segments of 16 KB. -//sink:etr_ddr,0x1,0x1000; -//seq_end; -//Below commands to enable Event traces on UMAC,MAC0,MAC1 -seq_start; -seq_type:mac_event_trace; -sink:etr_ddr; -subsys_cfg_start:mac0; -hwsch:0x1, 0x000FFFF1,0x1036052C,0x0,0x0; -rxdma:0x2, 0x3400,0x8000,0x0,0x0; -crypto:0x3, 0xF79B3770,0x0,0x0,0x0; -txpcu:0x4, 0xD687F4E7,0x20000092,0x0,0x0; -txole:0x5, 0x640F0622,0x2,0x0,0x0; -pdg:0x6, 0x3C800706,0x0,0x0,0x0; -subsys_cfg_end:mac0; -subsys_cfg_start:mac1; -hwsch:0x7, 0x000FFFF1,0x1036052C,0x0,0x0; -rxdma:0x8, 0x3400,0x8000,0x0,0x0; -crypto:0x9, 0xF79B3770,0x0,0x0,0x0; -txpcu:0xA, 0xD687F4E7,0x20000092,0x0,0x0; -txole:0xB, 0x640F0622,0x2,0x0,0x0; -pdg:0xC, 0x3C800706,0x0,0x0,0x0; -subsys_cfg_end:mac1; -swap:0xFFFFFFFF; -trigger_start:trc; -wfi:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -ts0:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -ts1:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -ts2:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -ts3:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -ts4:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -trigger_end:trc; -memw:0xFFFFFFFF,0xFFFFFFFF; -seq_end; -// Below commands to enable obo trace on the mac0 -//seq_start; -//seq_type:mac_obo_trace; -//sink:etb_wcss; -//subsys_cfg_start:mac0; -//hwsch:0x1,0xABCDABCD; -//subsys_cfg_end:mac0; -//swap:0xABCDABCD; -//trigger_start:trc; -//wfi:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -//ts0:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -//ts1:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -//ts2:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -//ts3:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -//ts4:0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF; -//trigger_end:trc; -//memw:0xFFFFFFFF,0xFFFFFFFF; -//seq_end; -// Below commands to enable TLV trace on the mac0 -//seq_start; -//seq_type:mac_tlv_trace; -//sink:etb_wcss; -//subsys_cfg_start:mac0; -//tlv_port:PDG_TXDMA_TLV; -//subsys_cfg_end:mac0; -//seq_end; -// Below commands to enable q6 etm -//seq_start; -//seq_type:q6_etm_trace; -//sink:etr_ddr; -//seq_end; -// Below commands to enable umac noc traces -//seq_start; -//seq_type:umac_noc_trace; -//sink:etb_wcss; -//ctrl:0x12; -//port_sel:0x4; -//lut:0xA; -//routeid_base:0x01000000; -//routeid_mask:0x01c00000; -//addr_lo:0x0; -//addr_hi:0x0; -//win_size:0x25; -//req_opcode:0x3; -//res_status:0x3; -//fltr_len:0xF; -//async_period:0xC; -//seq_end; -// Below commands to enable umac noc traces -//seq_start; -//seq_type:phy_tlv_trace; -//sink:etr_ddr; -//seq_end; -//seq_start; -//seq_type:phy_event_trace; -//sink:etr_ddr; -//phya:0x1,0x1; -//phyb:0x1,0x1; -//seq_end; diff --git a/package/firmware/b43legacy-firmware/Makefile b/package/firmware/b43legacy-firmware/Makefile deleted file mode 100755 index b7f325e13..000000000 --- a/package/firmware/b43legacy-firmware/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -# -# Copyright (C) 2016 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk - -PKG_NAME:=b43legacy-firmware -PKG_VERSION:=3.130.20.0 -PKG_RELEASE:=1 - -PKG_SOURCE:=wl_apsta-$(PKG_VERSION).o -PKG_SOURCE_URL:=@OPENWRT -PKG_HASH:=7dba610b1d96dd14e901bcbce14cd6ecd1b1ac6f5c0035b0d6b6dc46a7c3ef90 - -include $(INCLUDE_DIR)/package.mk - -define Package/b43legacy-firmware - SECTION:=firmware - CATEGORY:=Firmware - URL:=$(PKG_SOURCE_URL) - TITLE:=Broadcom bcm43xx b43legacy firmware -endef - -define Package/b43legacy-firmware/config - if PACKAGE_b43legacy-firmware - - config B43LEGACY_FW_SQUASH - bool "Remove unnecessary firmware files" - default y - help - This options allows you to remove unnecessary b43legacy firmware files - from the final rootfs image. This can reduce the rootfs size by - up to 50k. - - If unsure, say Y. - - config B43LEGACY_FW_SQUASH_COREREVS - string "Core revisions to include" - depends on B43LEGACY_FW_SQUASH - default "1,2,3,4" - help - This is a comma separated list of core revision numbers. - - Example (keep files for rev4 only): - 4 - - Example (keep files for rev2 and rev4): - 2,4 - - endif -endef - -define Build/Prepare - mkdir -p $(PKG_BUILD_DIR) -endef - -define Build/Compile - -endef - -define Package/b43legacy-firmware/install - $(INSTALL_DIR) $(1)/lib/firmware - b43-fwcutter --unsupported -w $(1)/lib/firmware/ $(DL_DIR)/$(PKG_SOURCE) - ifneq ($(CONFIG_B43LEGACY_FW_SQUASH),) - b43-fwsquash.py "G" "$(CONFIG_B43LEGACY_FW_SQUASH_COREREVS)" "$(1)/lib/firmware/b43legacy" - endif -endef - -$(eval $(call BuildPackage,b43legacy-firmware)) diff --git a/package/firmware/cypress-firmware/Makefile b/package/firmware/cypress-firmware/Makefile index c5f41e0cb..6a14ff993 100644 --- a/package/firmware/cypress-firmware/Makefile +++ b/package/firmware/cypress-firmware/Makefile @@ -1,19 +1,14 @@ -# -# Copyright (C) 2019-2020 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# +# SPDX-License-Identifier: GPL-2.0-or-later include $(TOPDIR)/rules.mk PKG_NAME:=cypress-firmware -PKG_VERSION:=5.4.18-2021_0812 +PKG_VERSION:=5.10.9-2022_0909 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/Infineon/ifx-linux-firmware/ -PKG_MIRROR_HASH:=ac882b482dd401b53cdecc6004cd2bd3d65e888c19206dcf10931a28033ada4d +PKG_MIRROR_HASH:=944faae3a80013f1a963b6692d7f50a38c97edcf91fd163de521df755e6922b5 PKG_SOURCE_VERSION:=release-v$(PKG_VERSION) PKG_MAINTAINER:=Álvaro Fernández Rojas @@ -38,12 +33,19 @@ define Package/cypress-firmware-43012-sdio endef define Package/cypress-firmware-43012-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43012-sdio.bin \ - $(1)/lib/firmware/brcm/brcmfmac43012-sdio.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43012-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43012-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43012-sdio.bin + $(LN) \ + ../cypress/cyfmac43012-sdio.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac43012-sdio.clm_blob endef @@ -56,9 +58,13 @@ define Package/cypress-firmware-43340-sdio endef define Package/cypress-firmware-43340-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43340-sdio.bin \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43340-sdio.bin \ $(1)/lib/firmware/brcm/brcmfmac43340-sdio.bin endef @@ -73,9 +79,13 @@ define Package/cypress-firmware-43362-sdio endef define Package/cypress-firmware-43362-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43362-sdio.bin \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43362-sdio.bin \ $(1)/lib/firmware/brcm/brcmfmac43362-sdio.bin endef @@ -85,12 +95,18 @@ $(eval $(call BuildPackage,cypress-firmware-43362-sdio)) define Package/cypress-firmware-4339-sdio $(Package/cypress-firmware-default) TITLE:=CYW4339 FullMac SDIO firmware + PROVIDES:=brcmfmac-firmware-4339-sdio + CONFLICTS:=brcmfmac-firmware-4339-sdio endef define Package/cypress-firmware-4339-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4339-sdio.bin \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4339-sdio.bin \ $(1)/lib/firmware/brcm/brcmfmac4339-sdio.bin endef @@ -105,17 +121,49 @@ define Package/cypress-firmware-43430-sdio endef define Package/cypress-firmware-43430-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43430-sdio.bin \ - $(1)/lib/firmware/brcm/brcmfmac43430-sdio.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43430-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43430-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43430-sdio.bin + $(LN) \ + ../cypress/cyfmac43430-sdio.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac43430-sdio.clm_blob endef $(eval $(call BuildPackage,cypress-firmware-43430-sdio)) +# Cypress 43439 SDIO Firmware +define Package/cypress-firmware-43439-sdio + $(Package/cypress-firmware-default) + TITLE:=CYW43439 FullMac SDIO firmware +endef + +define Package/cypress-firmware-43439-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/cypress + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac43439-sdio.bin \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac43439-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43439-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43439-sdio.bin + $(LN) \ + ../cypress/cyfmac43439-sdio.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac43439-sdio.clm_blob +endef + +$(eval $(call BuildPackage,cypress-firmware-43439-sdio)) + # Cypress 43455 SDIO Firmware define Package/cypress-firmware-43455-sdio $(Package/cypress-firmware-default) @@ -125,12 +173,19 @@ define Package/cypress-firmware-43455-sdio endef define Package/cypress-firmware-43455-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.bin \ - $(1)/lib/firmware/brcm/brcmfmac43455-sdio.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43455-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.bin + $(LN) \ + ../cypress/cyfmac43455-sdio.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac43455-sdio.clm_blob endef @@ -143,12 +198,19 @@ define Package/cypress-firmware-4354-sdio endef define Package/cypress-firmware-4354-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4354-sdio.bin \ - $(1)/lib/firmware/brcm/brcmfmac4354-sdio.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4354-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4354-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac4354-sdio.bin + $(LN) \ + ../cypress/cyfmac4354-sdio.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac4354-sdio.clm_blob endef @@ -161,12 +223,19 @@ define Package/cypress-firmware-4356-pcie endef define Package/cypress-firmware-4356-pcie/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4356-pcie.bin \ - $(1)/lib/firmware/brcm/brcmfmac4356-pcie.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4356-pcie.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4356-pcie.bin \ + $(1)/lib/firmware/brcm/brcmfmac4356-pcie.bin + $(LN) \ + ../cypress/cyfmac4356-pcie.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac4356-pcie.clm_blob endef @@ -179,12 +248,19 @@ define Package/cypress-firmware-4356-sdio endef define Package/cypress-firmware-4356-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4356-sdio.bin \ - $(1)/lib/firmware/brcm/brcmfmac4356-sdio.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4356-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4356-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac4356-sdio.bin + $(LN) \ + ../cypress/cyfmac4356-sdio.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac4356-sdio.clm_blob endef @@ -197,17 +273,49 @@ define Package/cypress-firmware-43570-pcie endef define Package/cypress-firmware-43570-pcie/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43570-pcie.bin \ - $(1)/lib/firmware/brcm/brcmfmac43570-pcie.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac43570-pcie.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac43570-pcie.bin \ + $(1)/lib/firmware/brcm/brcmfmac43570-pcie.bin + $(LN) \ + ../cypress/cyfmac43570-pcie.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac43570-pcie.clm_blob endef $(eval $(call BuildPackage,cypress-firmware-43570-pcie)) +# Cypress 4373 PCIe Firmware +define Package/cypress-firmware-4373-pcie + $(Package/cypress-firmware-default) + TITLE:=CYW4373 FullMac PCIe firmware +endef + +define Package/cypress-firmware-4373-pcie/install + $(INSTALL_DIR) $(1)/lib/firmware/cypress + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac4373-pcie.bin \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac4373-pcie.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4373-pcie.bin \ + $(1)/lib/firmware/brcm/brcmfmac4373-pcie.bin + $(LN) \ + ../cypress/cyfmac4373-pcie.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac4373-pcie.clm_blob +endef + +$(eval $(call BuildPackage,cypress-firmware-4373-pcie)) + # Cypress 4373 SDIO Firmware define Package/cypress-firmware-4373-sdio $(Package/cypress-firmware-default) @@ -215,12 +323,19 @@ define Package/cypress-firmware-4373-sdio endef define Package/cypress-firmware-4373-sdio/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4373-sdio.bin \ - $(1)/lib/firmware/brcm/brcmfmac4373-sdio.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4373-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4373-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac4373-sdio.bin + $(LN) \ + ../cypress/cyfmac4373-sdio.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac4373-sdio.clm_blob endef @@ -233,12 +348,19 @@ define Package/cypress-firmware-4373-usb endef define Package/cypress-firmware-4373-usb/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4373-usb.bin \ - $(1)/lib/firmware/brcm/brcmfmac4373-usb.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac4373.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac4373-usb.bin \ + $(1)/lib/firmware/brcm/brcmfmac4373-usb.bin + $(LN) \ + ../cypress/cyfmac4373.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac4373.clm_blob endef @@ -251,13 +373,114 @@ define Package/cypress-firmware-54591-pcie endef define Package/cypress-firmware-54591-pcie/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DIR) $(1)/lib/firmware/cypress $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac54591-pcie.bin \ - $(1)/lib/firmware/brcm/brcmfmac54591-pcie.bin + $(1)/lib/firmware/cypress/ $(INSTALL_DATA) \ $(PKG_BUILD_DIR)/firmware/cyfmac54591-pcie.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac54591-pcie.bin \ + $(1)/lib/firmware/brcm/brcmfmac54591-pcie.bin + $(LN) \ + ../cypress/cyfmac54591-pcie.clm_blob \ $(1)/lib/firmware/brcm/brcmfmac54591-pcie.clm_blob endef $(eval $(call BuildPackage,cypress-firmware-54591-pcie)) + +# Cypress 54591 SDIO Firmware +define Package/cypress-firmware-54591-sdio + $(Package/cypress-firmware-default) + TITLE:=CYW54591 FullMac SDIO firmware +endef + +define Package/cypress-firmware-54591-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/cypress + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac54591-sdio.bin \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac54591-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac54591-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac54591-sdio.bin + $(LN) \ + ../cypress/cyfmac54591-sdio.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac54591-sdio.clm_blob +endef + +$(eval $(call BuildPackage,cypress-firmware-54591-sdio)) + +# Cypress 55560 PCIe Firmware +define Package/cypress-firmware-55560-pcie + $(Package/cypress-firmware-default) + TITLE:=CYW55560 FullMac PCIe firmware +endef + +define Package/cypress-firmware-55560-pcie/install + $(INSTALL_DIR) $(1)/lib/firmware/cypress + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac55560-pcie.trxse \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac55560-pcie.trxse \ + $(1)/lib/firmware/brcm/brcmfmac55560-pcie.trxse +endef + +$(eval $(call BuildPackage,cypress-firmware-55560-pcie)) + +# Cypress 55572 PCIe Firmware +define Package/cypress-firmware-55572-pcie + $(Package/cypress-firmware-default) + TITLE:=CYW55572 FullMac PCIe firmware +endef + +define Package/cypress-firmware-55572-pcie/install + $(INSTALL_DIR) $(1)/lib/firmware/cypress + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac55572-pcie.trxse \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac55572-pcie.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac55572-pcie.trxse \ + $(1)/lib/firmware/brcm/brcmfmac55572-pcie.trxse + $(LN) \ + ../cypress/cyfmac55572-pcie.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac55572-pcie.clm_blob +endef + +$(eval $(call BuildPackage,cypress-firmware-55572-pcie)) + +# Cypress 55572 SDIO Firmware +define Package/cypress-firmware-55572-sdio + $(Package/cypress-firmware-default) + TITLE:=CYW55572 FullMac SDIO firmware +endef + +define Package/cypress-firmware-55572-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/cypress + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac55572-sdio.trxse \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac55572-sdio.clm_blob \ + $(1)/lib/firmware/cypress/ + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(LN) \ + ../cypress/cyfmac55572-sdio.trxse \ + $(1)/lib/firmware/brcm/brcmfmac55572-sdio.trxse + $(LN) \ + ../cypress/cyfmac55572-sdio.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac55572-sdio.clm_blob +endef + +$(eval $(call BuildPackage,cypress-firmware-55572-sdio)) diff --git a/package/firmware/cypress-nvram/Makefile b/package/firmware/cypress-nvram/Makefile index 806bfa2d9..dcf09d959 100644 --- a/package/firmware/cypress-nvram/Makefile +++ b/package/firmware/cypress-nvram/Makefile @@ -1,108 +1,38 @@ -# -# Copyright (C) 2019 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# +# SPDX-License-Identifier: GPL-2.0-or-later include $(TOPDIR)/rules.mk PKG_NAME:=cypress-nvram -PKG_SOURCE_DATE:=2019-09-03 -PKG_SOURCE_VERSION:=e7b78df22f2a0c5f56abb7b5880661611de35e5f -PKG_MIRROR_HASH:=1cb20a749696852be0a512d51961365dd9c031362af0af1a2b9f5a3fb894885f -PKG_RELEASE:=2 - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/openwrt/cypress-nvram.git +PKG_RELEASE:=7 PKG_MAINTAINER:=Álvaro Fernández Rojas -PKG_FLAGS:=nonshared - include $(INCLUDE_DIR)/package.mk define Package/cypress-nvram-default SECTION:=firmware CATEGORY:=Firmware - URL:=https://community.cypress.com/community/linux endef define Build/Compile true endef -# Cypress 43430 SDIO Raspberry Pi 3B NVRAM -define Package/cypress-nvram-43430-sdio-rpi-3b +# Cypress 4339 SDIO NVRAM +define Package/cypress-nvram-4339-sdio $(Package/cypress-nvram-default) - TITLE:=CYW43430 NVRAM for Raspberry Pi 3B - DEPENDS:=@TARGET_bcm27xx - PROVIDES:=brcmfmac-firmware-43430-sdio-rpi-3b - CONFLICTS:=brcmfmac-firmware-43430-sdio-rpi-3b + TITLE:=BCM4339 SDIO NVRAM + CONFLICTS:=brcmfmac-nvram-4339-sdio endef -define Package/cypress-nvram-43430-sdio-rpi-3b/install +define Package/cypress-nvram-4339-sdio/install $(INSTALL_DIR) $(1)/lib/firmware/brcm $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/brcmfmac43430-sdio.raspberrypi,3-model-b.txt \ - $(1)/lib/firmware/brcm/brcmfmac43430-sdio.raspberrypi,3-model-b.txt + ./files/brcmfmac4339-sdio.AP6335.txt \ + $(1)/lib/firmware/brcm/ + $(LN) \ + brcmfmac4339-sdio.AP6335.txt \ + $(1)/lib/firmware/brcm/brcmfmac4339-sdio.technexion,imx7d-pico-pi.txt endef -$(eval $(call BuildPackage,cypress-nvram-43430-sdio-rpi-3b)) - -# Cypress 43430 SDIO Raspberry Pi Zero W NVRAM -define Package/cypress-nvram-43430-sdio-rpi-zero-w - $(Package/cypress-nvram-default) - TITLE:=CYW43430 NVRAM for Raspberry Pi Zero W - DEPENDS:=@TARGET_bcm27xx - PROVIDES:=brcmfmac-firmware-43430-sdio-rpi-zero-w - CONFLICTS:=brcmfmac-firmware-43430-sdio-rpi-zero-w -endef - -define Package/cypress-nvram-43430-sdio-rpi-zero-w/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/brcmfmac43430-sdio.raspberrypi,model-zero-w.txt \ - $(1)/lib/firmware/brcm/brcmfmac43430-sdio.raspberrypi,model-zero-w.txt -endef - -$(eval $(call BuildPackage,cypress-nvram-43430-sdio-rpi-zero-w)) - -# Cypress 43455 SDIO Raspberry Pi 3B+ NVRAM -define Package/cypress-nvram-43455-sdio-rpi-3b-plus - $(Package/cypress-nvram-default) - TITLE:=CYW43455 NVRAM for Raspberry Pi 3B+ - DEPENDS:=@TARGET_bcm27xx - PROVIDES:=brcmfmac-firmware-43455-sdio-rpi-3b-plus - CONFLICTS:=brcmfmac-firmware-43455-sdio-rpi-3b-plus -endef - -define Package/cypress-nvram-43455-sdio-rpi-3b-plus/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt \ - $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt -endef - -$(eval $(call BuildPackage,cypress-nvram-43455-sdio-rpi-3b-plus)) - -# Cypress 43455 SDIO Raspberry Pi 4B NVRAM -define Package/cypress-nvram-43455-sdio-rpi-4b - $(Package/cypress-nvram-default) - TITLE:=CYW43455 NVRAM for Raspberry Pi 4B - DEPENDS:=@TARGET_bcm27xx - PROVIDES:=brcmfmac-firmware-43455-sdio-rpi-4b - CONFLICTS:=brcmfmac-firmware-43455-sdio-rpi-4b -endef - -define Package/cypress-nvram-43455-sdio-rpi-4b/install - $(INSTALL_DIR) $(1)/lib/firmware/brcm - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,4-model-b.txt \ - $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.txt - $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,4-model-b.txt \ - $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-compute-module.txt -endef - -$(eval $(call BuildPackage,cypress-nvram-43455-sdio-rpi-4b)) +$(eval $(call BuildPackage,cypress-nvram-4339-sdio)) diff --git a/package/firmware/cypress-nvram/files/brcmfmac4339-sdio.AP6335.txt b/package/firmware/cypress-nvram/files/brcmfmac4339-sdio.AP6335.txt new file mode 100644 index 000000000..1ddd92950 --- /dev/null +++ b/package/firmware/cypress-nvram/files/brcmfmac4339-sdio.AP6335.txt @@ -0,0 +1,99 @@ +#AP6335_NVRAM_V1.5_03112014 +NVRAMRev=$Rev: 410316 $ +sromrev=11 +boardrev=0x1203 +boardtype=0x06c5 +boardflags=0x00000c01 +boardflags2=0x00002000 +boardflags3=0x101188 +macaddr=00:90:4c:c5:12:38 +ccode=0 +regrev=0 +antswitch=0 +pdgain2g=7 +pdgain5g=7 +tworangetssi2g=0 +tworangetssi5g=0 +femctrl=7 +pcieingress_war=15 +vendid=0x14e4 +devid=0x43ae +manfid=0x2d0 +nocrc=1 +otpimagesize=502 +xtalfreq=37400 +extpagain2g=2 +pdetrange2g=2 +extpagain5g=2 +pdetrange5g=2 +rxgains2gelnagaina0=0 +rxgains2gtrisoa0=7 +rxgains2gtrelnabypa0=0 +rxgains5gelnagaina0=0 +rxgains5gtrisoa0=11 +rxgains5gtrelnabypa0=0 +rxchain=1 +txchain=1 +aa2g=1 +aa5g=1 +tssipos5g=0 +tssipos2g=0 +pa2ga0=-161,6269,-723 +pa2gccka0=-116,7568,-852 +pa5ga0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pa5gbw40a0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pa5gbw80a0=0xFF61,0x163C,0xFD55,0xFF5D,0x1671,0xFD4F,0xFF5F,0x16CA,0xFD45,0xFF60,0x1676,0xFD4D +pdoffset40ma0=0 +pdoffset80ma0=0 +pdoffsetcckma0=0 +maxp2ga0=75 +maxp5ga0=64,64,72,72 +cckbw202gpo=0x0000 +cckbw20ul2gpo=0x0 +mcsbw202gpo=0x99445533 +mcsbw402gpo=0x99775533 +dot11agofdmhrbw202gpo=0x2233 +ofdmlrbw202gpo=0x0000 +tssifloor2g=500 +mcsbw205glpo=0x66333330 +mcsbw405glpo=0x66665530 +mcsbw805glpo=0xAA555530 +mcsbw1605glpo=0x99555530 +mcsbw205gmpo=0x99BB5530 +mcsbw405gmpo=0x99BB5530 +mcsbw805gmpo=0xEE555530 +mcsbw1605gmpo=0x99555530 +mcsbw205ghpo=0x99995530 +mcsbw405ghpo=0x99BB5530 +mcsbw805ghpo=0xEE555530 +mcsbw1605ghpo=0x99555530 +mcslr5glpo=0x0000 +mcslr5gmpo=0x0000 +mcslr5ghpo=0x0000 +sb20in40hrrpo=0x0 +sb20in80and160hr5glpo=0x0 +sb40and80hr5glpo=0x0 +sb20in80and160hr5gmpo=0x0 +sb40and80hr5gmpo=0x0 +sb20in80and160hr5ghpo=0x0 +sb40and80hr5ghpo=0x0 +sb20in40lrpo=0x0 +sb20in80and160lr5glpo=0x0 +sb40and80lr5glpo=0x0 +sb20in80and160lr5gmpo=0x0 +sb40and80lr5gmpo=0x0 +sb20in80and160lr5ghpo=0x0 +sb40and80lr5ghpo=0x0 +dot11agduphrpo=0x0 +dot11agduplrpo=0x0 +phycal_tempdelta=25 +cckdigfilttype=2 +pacalidx2g=65 +dacrate2g=160 +swctrlmap_5g=0x00000008,0x00000010,0x00000008,0x000000,0x038 +swctrlmap_2g=0x00000001,0x00000002,0x00000001,0x040002,0x0ff +swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +rssicorrnorm_c0=3,3 +rssicorrnorm5g_c0=2,3,4,2,3,3,0,1,2,0,1,2 +muxenab=0x10 diff --git a/package/firmware/intel-microcode/Makefile b/package/firmware/intel-microcode/Makefile index 91a697c67..bdd8ae73d 100644 --- a/package/firmware/intel-microcode/Makefile +++ b/package/firmware/intel-microcode/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=intel-microcode -PKG_VERSION:=20240312 +PKG_VERSION:=20240531 PKG_RELEASE:=1 PKG_SOURCE:=intel-microcode_3.$(PKG_VERSION).1.tar.xz PKG_SOURCE_URL:=@DEBIAN/pool/non-free-firmware/i/intel-microcode/ -PKG_HASH:=25f53bab1bf0c84aba927a77a97a9f1147c94199fa95b5187d874f839f022808 +PKG_HASH:=808cbb57a790dab7060b59b31e70e54ac47d3798d75e9784ed57a65b9f951fc4 PKG_BUILD_DIR:=$(BUILD_DIR)/intel-microcode-3.$(PKG_VERSION).1 PKG_CPE_ID:=cpe:/a:intel:microcode diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 3729ee65f..b79ccf647 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -2,13 +2,13 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/version.mk PKG_NAME:=ipq-wifi -PKG_RELEASE:=2 +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware/qca-wireless.git -PKG_SOURCE_DATE:=2023-06-03 -PKG_SOURCE_VERSION:=cd9c30ca47b8e5388b770c523a7f6b8b969e2f92 -PKG_MIRROR_HASH:=45e623fcc512b514ade0f22e217275536aa8de4afba7dfdb11696482b8fa71a2 +PKG_SOURCE_DATE:=2024-04-16 +PKG_SOURCE_VERSION:=1d51799e6768a304da7840b8346e7487efd77f49 +PKG_MIRROR_HASH:=9cf0917532283c1a1708643022a5ed1ec4af6bb9ebaff57fc2f0f2c229f2469e PKG_FLAGS:=nonshared @@ -28,21 +28,38 @@ endef # ALLWIFIBOARDS:= \ + arcadyan_aw1000 \ buffalo_wxr-5950ax12 \ compex_wpq873 \ dynalink_dl-wrx36 \ edgecore_eap102 \ edimax_cax1800 \ + glinet_gl-ax1800 \ + glinet_gl-axt1800 \ + jdcloud_ax1800pro \ + jdcloud_ax6600 \ + linksys_mr7350 \ + linksys_mx4200 \ + linksys_mx5300 \ + netgear_lbr20 \ netgear_rax120v2 \ + netgear_wax214 \ netgear_wax218 \ - p2w_r619ac \ + netgear_wax620 \ + netgear_wax630 \ prpl_haze \ + qihoo_360v6 \ qnap_301w \ + redmi_ax5-jdcloud \ redmi_ax6 \ wallys_dr40x9 \ xiaomi_ax3600 \ xiaomi_ax9000 \ - zte_mf289f \ + xiaomi_rm1800 \ + yuncore_ax880 \ + yuncore_fap650 \ + zte_mf269 \ + zte_mf287 \ zte_mf287plus \ zyxel_nbg7815 @@ -52,7 +69,7 @@ define Package/ipq-wifi-default SUBMENU:=ath10k Board-Specific Overrides SECTION:=firmware CATEGORY:=Firmware - DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_ipq807x) + DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_qualcommax) TITLE:=Custom Board endef @@ -77,12 +94,14 @@ define ipq-wifi-install-one $(call ipq-wifi-install-one-to,$(1),$(2),QCA9984/hw1.0),\ $(if $(filter $(suffix $(1)),.QCA99X0 .qca99x0),\ $(call ipq-wifi-install-one-to,$(1),$(2),QCA99X0/hw2.0),\ + $(if $(filter $(suffix $(1)),.IPQ6018 .ipq6018),\ + $(call ipq-wifi-install-ath11-one-to,$(1),$(2),IPQ6018/hw1.0),\ $(if $(filter $(suffix $(1)),.IPQ8074 .ipq8074),\ $(call ipq-wifi-install-ath11-one-to,$(1),$(2),IPQ8074/hw2.0),\ $(if $(filter $(suffix $(1)),.QCN9074 .qcn9074),\ $(call ipq-wifi-install-ath11-one-to,$(1),$(2),QCN9074/hw1.0),\ $(error Unrecognized board-file suffix '$(suffix $(1))' for '$(1)')\ - ))))))) + )))))))) endef # Blank line required at end of above define due to foreach context @@ -118,21 +137,38 @@ endef # Place files in this directory as board-. # Add $(eval $(call generate-ipq-wifi-package,,)) +$(eval $(call generate-ipq-wifi-package,arcadyan_aw1000,Arcadyan AW1000)) $(eval $(call generate-ipq-wifi-package,buffalo_wxr-5950ax12,Buffalo WXR-5950AX12)) $(eval $(call generate-ipq-wifi-package,compex_wpq873,Compex WPQ-873)) $(eval $(call generate-ipq-wifi-package,dynalink_dl-wrx36,Dynalink DL-WRX36)) $(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102)) $(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800)) +$(eval $(call generate-ipq-wifi-package,glinet_gl-ax1800,GL.iNet GL-AX1800)) +$(eval $(call generate-ipq-wifi-package,glinet_gl-axt1800,GL.iNet GL-AXT1800)) +$(eval $(call generate-ipq-wifi-package,jdcloud_ax1800pro,JDCloud AX1800 Pro)) +$(eval $(call generate-ipq-wifi-package,jdcloud_ax6600,JDCloud AX6600)) +$(eval $(call generate-ipq-wifi-package,linksys_mr7350,Linksys MR7350)) +$(eval $(call generate-ipq-wifi-package,linksys_mx4200,Linksys MX4200)) +$(eval $(call generate-ipq-wifi-package,linksys_mx5300,Linksys MX5300)) +$(eval $(call generate-ipq-wifi-package,netgear_lbr20,Netgear LBR20)) $(eval $(call generate-ipq-wifi-package,netgear_rax120v2,Netgear RAX120v2)) +$(eval $(call generate-ipq-wifi-package,netgear_wax214,Netgear WAX214)) $(eval $(call generate-ipq-wifi-package,netgear_wax218,Netgear WAX218)) -$(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC)) +$(eval $(call generate-ipq-wifi-package,netgear_wax620,Netgear WAX620)) +$(eval $(call generate-ipq-wifi-package,netgear_wax630,Netgear WAX630)) +$(eval $(call generate-ipq-wifi-package,qihoo_360v6,Qihoo 360V6)) $(eval $(call generate-ipq-wifi-package,qnap_301w,QNAP 301w)) $(eval $(call generate-ipq-wifi-package,prpl_haze,prpl Haze)) +$(eval $(call generate-ipq-wifi-package,redmi_ax5-jdcloud,Redmi AX5 JDCloud)) $(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6)) $(eval $(call generate-ipq-wifi-package,wallys_dr40x9,Wallys DR40X9)) $(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600)) $(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000)) -$(eval $(call generate-ipq-wifi-package,zte_mf289f,ZTE MF289F)) +$(eval $(call generate-ipq-wifi-package,xiaomi_rm1800,Xiaomi RM1800)) +$(eval $(call generate-ipq-wifi-package,yuncore_ax880,Yuncore AX880)) +$(eval $(call generate-ipq-wifi-package,yuncore_fap650,Yuncore FAP650)) +$(eval $(call generate-ipq-wifi-package,zte_mf269,ZTE MF269)) +$(eval $(call generate-ipq-wifi-package,zte_mf287,ZTE MF287)) $(eval $(call generate-ipq-wifi-package,zte_mf287plus,ZTE MF287Plus)) $(eval $(call generate-ipq-wifi-package,zyxel_nbg7815,Zyxel NBG7815)) diff --git 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+PKG_HASH:=bf0f239dc0801e9d6bf5d5fb3e2f549575632cf4688f4348184199cb02c2bcd7 PKG_MAINTAINER:=Felix Fietkau diff --git a/package/firmware/linux-firmware/airoha.mk b/package/firmware/linux-firmware/airoha.mk new file mode 100644 index 000000000..627541ba9 --- /dev/null +++ b/package/firmware/linux-firmware/airoha.mk @@ -0,0 +1,8 @@ +Package/en8811h-firmware = $(call Package/firmware-default,Airoha EN8811H PHY firmware) +define Package/en8811h-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/airoha + $(CP) \ + $(PKG_BUILD_DIR)/airoha/*.bin \ + $(1)/lib/firmware/airoha +endef +$(eval $(call BuildPackage,en8811h-firmware)) diff --git a/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.bin b/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.bin old mode 100644 new mode 100755 diff --git a/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.txt b/package/firmware/linux-firmware/brcm_firmware/ap6236/brcmfmac43430-sdio.txt old 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HcmV?d00001 diff --git a/package/kernel/cryptodev-linux/Makefile b/package/kernel/cryptodev-linux/Makefile index 0b794a3cd..d04aaeace 100644 --- a/package/kernel/cryptodev-linux/Makefile +++ b/package/kernel/cryptodev-linux/Makefile @@ -11,7 +11,7 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=cryptodev-linux PKG_VERSION:=1.13 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_URL:=https://codeload.github.com/$(PKG_NAME)/$(PKG_NAME)/tar.gz/$(PKG_NAME)-$(PKG_VERSION)? PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz diff --git a/package/kernel/cryptodev-linux/patches/0005-fix-build-for-linux-5.10.220+.patch b/package/kernel/cryptodev-linux/patches/0005-fix-build-for-linux-5.10.220+.patch new file mode 100644 index 000000000..3d2565317 --- /dev/null +++ b/package/kernel/cryptodev-linux/patches/0005-fix-build-for-linux-5.10.220+.patch @@ -0,0 +1,11 @@ +--- a/ioctl.c ++++ b/ioctl.c +@@ -933,7 +933,7 @@ + if (unlikely(ret)) { + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)) + sys_close(fd); +-#elif (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) ++#elif (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 220)) + ksys_close(fd); + #else + close_fd(fd); diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index 7a808afee..e2d4aeff5 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2007-2015 OpenWrt.org +# Copyright (C) 2007-2023 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. @@ -10,16 +10,14 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=mac80211 -PKG_VERSION:=6.9.9 -PKG_RELEASE:=1 -PKG_LICENSE:=GPL-2.0-only -PKG_LICENSE_FILES:=COPYING - +PKG_VERSION:=6.1.24 +PKG_RELEASE:=3 +# PKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.58/ PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/ -PKG_HASH:=3417da091a57c7b1c145d44c1fae9f1e0bac6d0c8ad61b37e57b0a802eeb2837 +PKG_HASH:=5d39aca7e34c33cb9b3e366117b2e86841b7bdd37933679d6b1e61be6b150648 PKG_SOURCE:=backports-$(PKG_VERSION).tar.xz -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(if $(BUILD_VARIANT),$(PKG_NAME)-$(BUILD_VARIANT)/)backports-$(PKG_VERSION) +PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/backports-$(PKG_VERSION) PKG_BUILD_PARALLEL:=1 PKG_MAINTAINER:=Felix Fietkau @@ -50,13 +48,7 @@ define KernelPackage/mac80211/Default MAINTAINER:=Felix Fietkau endef -# config_pacakge: -# 1 = OpenWrt KernelPackage name -# 2 = Optional list of variants for which the module may be selected: -# If empty, the module is only selected with the first variant -# Use $(ALL_VARIANTS) to allow module selection in all variants -config_package=$(if $(and $(CONFIG_PACKAGE_kmod-$(1)),$(call mac80211_variant_check,$(2))),m) -mac80211_variant_check=$(if $(ALL_VARIANTS),$(filter $(BUILD_VARIANT),$(if $(1),$(1),$(firstword $(ALL_VARIANTS)))),y) +config_package=$(if $(CONFIG_PACKAGE_kmod-$(1)),m) config-y:= \ WLAN \ @@ -81,10 +73,10 @@ config-y:= \ WLAN_VENDOR_TI \ WLAN_VENDOR_ZYDAS \ -config-$(call config_package,cfg80211,$(ALL_VARIANTS)) += CFG80211 +config-$(call config_package,cfg80211) += CFG80211 config-$(CONFIG_PACKAGE_CFG80211_TESTMODE) += NL80211_TESTMODE -config-$(call config_package,mac80211,$(ALL_VARIANTS)) += MAC80211 +config-$(call config_package,mac80211) += MAC80211 config-$(CONFIG_PACKAGE_MAC80211_MESH) += MAC80211_MESH include ath.mk @@ -172,7 +164,7 @@ define KernelPackage/mac80211-hwsim $(call KernelPackage/mac80211/Default) TITLE:=mac80211 HW simulation device DEPENDS+= +kmod-mac80211 +@DRIVER_11AX_SUPPORT +@DRIVER_11AC_SUPPORT - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/virtual/mac80211_hwsim.ko + FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/mac80211_hwsim.ko AUTOLOAD:=$(call AutoProbe,mac80211_hwsim) endef @@ -188,7 +180,7 @@ endef define KernelPackage/rsi91x $(call KernelPackage/mac80211/Default) TITLE:=Redpine Signals Inc 91x WLAN driver support - DEPENDS+= +kmod-mac80211 +rs9113-firmware + DEPENDS+= +kmod-mac80211 +rs9113-firmware +@DRIVER_11N_SUPPORT FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rsi/rsi_91x.ko endef @@ -212,7 +204,7 @@ endef define KernelPackage/wlcore $(call KernelPackage/mac80211/Default) TITLE:=TI common driver part - DEPENDS+= +kmod-mmc +kmod-mac80211 + DEPENDS+= +kmod-mmc +kmod-mac80211 +@DRIVER_11N_SUPPORT FILES:= \ $(PKG_BUILD_DIR)/drivers/net/wireless/ti/wlcore/wlcore.ko \ $(PKG_BUILD_DIR)/drivers/net/wireless/ti/wlcore/wlcore_sdio.ko @@ -333,6 +325,7 @@ endif ifeq ($(strip $(CONFIG_EXTERNAL_KERNEL_TREE)),"") ifeq ($(strip $(CONFIG_KERNEL_GIT_CLONE_URI)),"") define Build/Configure + cmp $(PKG_BUILD_DIR)/include/linux/ath9k_platform.h $(LINUX_DIR)/include/linux/ath9k_platform.h cmp $(PKG_BUILD_DIR)/include/linux/ath5k_platform.h $(LINUX_DIR)/include/linux/ath5k_platform.h cmp $(PKG_BUILD_DIR)/include/linux/rt2x00_platform.h $(LINUX_DIR)/include/linux/rt2x00_platform.h endef @@ -391,6 +384,14 @@ define Build/InstallDev endef +define KernelPackage/cfg80211/install + $(INSTALL_DIR) $(1)/lib/wifi $(1)/lib/netifd/wireless + $(INSTALL_DATA) ./files/lib/wifi/mac80211.sh $(1)/lib/wifi + $(INSTALL_BIN) ./files/lib/netifd/wireless/mac80211.sh $(1)/lib/netifd/wireless + $(INSTALL_DIR) $(1)/etc/hotplug.d/ieee80211 + $(INSTALL_DATA) ./files/mac80211.hotplug $(1)/etc/hotplug.d/ieee80211/10-wifi-detect +endef + $(eval $(foreach drv,$(PKG_DRIVERS),$(call KernelPackage,$(drv)))) $(eval $(call KernelPackage,cfg80211)) $(eval $(call KernelPackage,mac80211)) diff --git a/package/kernel/mac80211/ath.mk b/package/kernel/mac80211/ath.mk index 1d4b37d25..6f5d17cef 100644 --- a/package/kernel/mac80211/ath.mk +++ b/package/kernel/mac80211/ath.mk @@ -1,6 +1,7 @@ PKG_DRIVERS += \ - ath ath5k ath6kl ath6kl-sdio ath6kl-usb ath9k ath9k-common ath9k-htc ath10k ath10k-smallbuffers \ - ath11k ath11k-ahb ath11k-pci carl9170 owl-loader ar5523 wil6210 + ath ath5k ath6kl ath6kl-sdio ath6kl-usb ath9k ath9k-common ath9k-htc \ + ath10k ath10k-pci ath10k-sdio ath10k-smallbuffers ath11k ath11k-ahb \ + ath11k-pci ar5523 carl9170 owl-loader wil6210 PKG_CONFIG_DEPENDS += \ CONFIG_PACKAGE_ATH_DEBUG \ @@ -37,7 +38,7 @@ ifdef CONFIG_PACKAGE_MAC80211_TRACING WIL6210_TRACING endif -config-$(call config_package,ath,regular smallbuffers) += ATH_CARDS ATH_COMMON +config-$(call config_package,ath) += ATH_CARDS ATH_COMMON config-$(CONFIG_PACKAGE_ATH_DEBUG) += ATH_DEBUG ATH10K_DEBUG ATH11K_DEBUG ATH9K_STATION_STATISTICS config-$(CONFIG_PACKAGE_ATH_DFS) += ATH9K_DFS_CERTIFIED ATH10K_DFS_CERTIFIED config-$(CONFIG_PACKAGE_ATH_SPECTRAL) += ATH9K_COMMON_SPECTRAL ATH10K_SPECTRAL ATH11K_SPECTRAL @@ -58,13 +59,21 @@ config-$(CONFIG_ATH10K_THERMAL) += ATH10K_THERMAL config-$(CONFIG_ATH11K_THERMAL) += ATH11K_THERMAL config-$(call config_package,ath9k-htc) += ATH9K_HTC -config-$(call config_package,ath10k,regular) += ATH10K ATH10K_PCI -config-$(call config_package,ath10k-smallbuffers,smallbuffers) += ATH10K ATH10K_PCI ATH10K_SMALLBUFFERS +config-$(call config_package,ath10k) += ATH10K +config-$(call config_package,ath10k-pci) += ATH10K_PCI +config-$(call config_package,ath10k-sdio) += ATH10K_SDIO +config-$(call config_package,ath10k-smallbuffers) += ATH10K ATH10K_PCI ATH10K_SMALLBUFFERS + config-$(call config_package,ath11k) += ATH11K config-$(call config_package,ath11k-ahb) += ATH11K_AHB config-$(call config_package,ath11k-pci) += ATH11K_PCI -config-$(call config_package,ath5k) += ATH5K ATH5K_PCI +config-$(call config_package,ath5k) += ATH5K +ifdef CONFIG_TARGET_ath25 + config-y += ATH5K_AHB +else + config-y += ATH5K_PCI +endif config-$(call config_package,ath6kl) += ATH6KL config-$(call config_package,ath6kl-sdio) += ATH6KL_SDIO @@ -128,7 +137,7 @@ endef define KernelPackage/ath $(call KernelPackage/mac80211/Default) TITLE:=Atheros common driver part - DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ath79 +kmod-mac80211 + DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ath79||TARGET_ath25 +kmod-mac80211 FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath.ko MENU:=1 endef @@ -141,7 +150,7 @@ define KernelPackage/ath5k $(call KernelPackage/mac80211/Default) TITLE:=Atheros 5xxx wireless cards support URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath5k - DEPENDS+= @PCI_SUPPORT +kmod-ath + DEPENDS+= @(PCI_SUPPORT||TARGET_ath25) +kmod-ath FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath5k/ath5k.ko AUTOLOAD:=$(call AutoProbe,ath5k) endef @@ -156,7 +165,7 @@ define KernelPackage/ath6kl TITLE:=Atheros FullMAC wireless devices (common code for ath6kl_sdio and ath6kl_usb) URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath6kl HIDDEN:=1 - DEPENDS+= +kmod-ath + DEPENDS+= +kmod-ath +@DRIVER_11N_SUPPORT FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath6kl/ath6kl_core.ko endef @@ -257,20 +266,17 @@ define KernelPackage/ath10k $(call KernelPackage/mac80211/Default) TITLE:=Atheros 802.11ac wireless cards support URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath10k - DEPENDS+= @PCI_SUPPORT +kmod-ath +@DRIVER_11AC_SUPPORT \ + DEPENDS+= +kmod-ath +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT \ +ATH10K_THERMAL:kmod-hwmon-core +ATH10K_THERMAL:kmod-thermal FILES:= \ - $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_core.ko \ - $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_pci.ko - AUTOLOAD:=$(call AutoProbe,ath10k_core ath10k_pci) + $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_core.ko + AUTOLOAD:=$(call AutoProbe,ath10k_core) MODPARAMS.ath10k_core:=frame_mode=2 - VARIANT:=regular endef define KernelPackage/ath10k/description This module adds support for wireless adapters based on -Atheros IEEE 802.11ac family of chipsets. For now only -PCI is supported. +Atheros IEEE 802.11ac family of chipsets. endef define KernelPackage/ath10k/config @@ -282,12 +288,42 @@ define KernelPackage/ath10k/config config ATH10K_THERMAL bool "Enable thermal sensors and throttling support" + default y depends on PACKAGE_kmod-ath10k || PACKAGE_kmod-ath10k-smallbuffers endef +define KernelPackage/ath10k-pci + $(call KernelPackage/mac80211/Default) + TITLE:=Atheros 802.11ac PCIE wireless cards support + URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath10k + DEPENDS+= @PCI_SUPPORT kmod-ath10k + FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_pci.ko + AUTOLOAD:=$(call AutoProbe,ath10k_pci) + VARIANT:=regular +endef + +define KernelPackage/ath10k-pci/description +This module adds support for wireless adapters based on +Atheros IEEE 802.11ac family of chipsets with PCIE bus. +endef + +define KernelPackage/ath10k-sdio + $(call KernelPackage/mac80211/Default) + TITLE:=Atheros 802.11ac SDIO wireless cards support + URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath10k + DEPENDS+= kmod-ath10k +kmod-mmc + FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_sdio.ko + AUTOLOAD:=$(call AutoProbe,ath10k_sdio) +endef + +define KernelPackage/ath10k-sdio/description +This module adds support for wireless adapters based on +Atheros IEEE 802.11ac family of chipsets with SDIO bus. +endef + define KernelPackage/ath10k-smallbuffers - $(call KernelPackage/ath10k) + $(call KernelPackage/ath10k-pci) TITLE+= (small buffers for low-RAM devices) VARIANT:=smallbuffers endef @@ -296,10 +332,11 @@ define KernelPackage/ath11k $(call KernelPackage/mac80211/Default) TITLE:=Qualcomm 802.11ax wireless chipset support (common code) URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath11k - DEPENDS+= +kmod-ath +@DRIVER_11AC_SUPPORT +@DRIVER_11AX_SUPPORT @!LINUX_5_15 \ + DEPENDS+= +kmod-ath +@DRIVER_11AC_SUPPORT +@DRIVER_11AX_SUPPORT \ +kmod-crypto-michael-mic +ATH11K_THERMAL:kmod-hwmon-core +ATH11K_THERMAL:kmod-thermal FILES:=$(PKG_BUILD_DIR)/drivers/soc/qcom/qmi_helpers.ko \ $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath11k/ath11k.ko + MODPARAMS.ath11k:=frame_mode=2 endef define KernelPackage/ath11k/description diff --git a/package/kernel/mac80211/broadcom.mk b/package/kernel/mac80211/broadcom.mk index a6f42cd19..a36f92477 100644 --- a/package/kernel/mac80211/broadcom.mk +++ b/package/kernel/mac80211/broadcom.mk @@ -245,11 +245,11 @@ config PACKAGE_B43_USE_BCMA This allows choosing buses that b43 should support. config PACKAGE_B43_BUSES_BCMA_AND_SSB - depends on !TARGET_bcm47xx_legacy && !TARGET_bcm47xx_mips74k && !TARGET_bcm53xx && !TARGET_bmips + depends on !TARGET_bcm47xx_legacy && !TARGET_bcm47xx_mips74k && !TARGET_bcm53xx bool "BCMA and SSB" config PACKAGE_B43_BUSES_BCMA - depends on !TARGET_bcm47xx_legacy && !TARGET_bmips_bcm6358 && !TARGET_bmips_bcm6368 + depends on !TARGET_bcm47xx_legacy bool "BCMA only" config PACKAGE_B43_BUSES_SSB @@ -416,10 +416,7 @@ define KernelPackage/brcmfmac DEPENDS+= @USB_SUPPORT +kmod-cfg80211 +@DRIVER_11AC_SUPPORT \ +kmod-brcmutil +BRCMFMAC_SDIO:kmod-mmc @!TARGET_uml \ +BRCMFMAC_USB:kmod-usb-core +BRCMFMAC_USB:brcmfmac-firmware-usb - FILES:= \ - $(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmfmac/brcmfmac.ko \ - $(foreach type,bca cyw wcc, \ - $(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmfmac/$(type)/brcmfmac-$(type).ko) + FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmfmac/brcmfmac.ko AUTOLOAD:=$(call AutoProbe,brcmfmac) endef @@ -433,10 +430,9 @@ define KernelPackage/brcmfmac/config config BRCMFMAC_SDIO bool "Enable SDIO bus interface support" default y if TARGET_bcm27xx - default y if TARGET_imx_cortexa7 - default y if TARGET_starfive - default y if TARGET_rockchip default y if TARGET_sunxi + default y if TARGET_rockchip + default y if TARGET_amlogic default n help Enable support for cards attached to an SDIO bus. diff --git a/package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh b/package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh new file mode 100644 index 000000000..469d4264a --- /dev/null +++ b/package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh @@ -0,0 +1,1244 @@ +#!/bin/sh +. /lib/netifd/netifd-wireless.sh +. /lib/netifd/hostapd.sh +. /lib/functions/system.sh + +init_wireless_driver "$@" + +MP_CONFIG_INT="mesh_retry_timeout mesh_confirm_timeout mesh_holding_timeout mesh_max_peer_links + mesh_max_retries mesh_ttl mesh_element_ttl mesh_hwmp_max_preq_retries + mesh_path_refresh_time mesh_min_discovery_timeout mesh_hwmp_active_path_timeout + mesh_hwmp_preq_min_interval mesh_hwmp_net_diameter_traversal_time mesh_hwmp_rootmode + mesh_hwmp_rann_interval mesh_gate_announcements mesh_sync_offset_max_neighor + mesh_rssi_threshold mesh_hwmp_active_path_to_root_timeout mesh_hwmp_root_interval + mesh_hwmp_confirmation_interval mesh_awake_window mesh_plink_timeout" +MP_CONFIG_BOOL="mesh_auto_open_plinks mesh_fwding" +MP_CONFIG_STRING="mesh_power_mode" + +NEWAPLIST= +OLDAPLIST= +NEWSPLIST= +OLDSPLIST= +NEWUMLIST= +OLDUMLIST= + +drv_mac80211_init_device_config() { + hostapd_common_add_device_config + + config_add_string path phy 'macaddr:macaddr' + config_add_string tx_burst + config_add_string distance + config_add_int beacon_int chanbw frag rts + config_add_int rxantenna txantenna antenna_gain txpower min_tx_power + config_add_boolean noscan ht_coex acs_exclude_dfs background_radar + config_add_array ht_capab + config_add_array channels + config_add_array scan_list + config_add_boolean \ + rxldpc \ + short_gi_80 \ + short_gi_160 \ + tx_stbc_2by1 \ + su_beamformer \ + su_beamformee \ + mu_beamformer \ + mu_beamformee \ + he_su_beamformer \ + he_su_beamformee \ + he_mu_beamformer \ + vht_txop_ps \ + htc_vht \ + rx_antenna_pattern \ + tx_antenna_pattern \ + he_spr_sr_control \ + he_spr_psr_enabled \ + he_bss_color_enabled \ + he_twt_required + config_add_int \ + beamformer_antennas \ + beamformee_antennas \ + vht_max_a_mpdu_len_exp \ + vht_max_mpdu \ + vht_link_adapt \ + vht160 \ + rx_stbc \ + tx_stbc \ + he_bss_color \ + he_spr_non_srg_obss_pd_max_offset + config_add_boolean \ + ldpc \ + greenfield \ + short_gi_20 \ + short_gi_40 \ + max_amsdu \ + dsss_cck_40 +} + +drv_mac80211_init_iface_config() { + hostapd_common_add_bss_config + + config_add_string 'macaddr:macaddr' ifname + + config_add_boolean wds powersave enable + config_add_string wds_bridge + config_add_int maxassoc + config_add_int max_listen_int + config_add_int dtim_period + config_add_int start_disabled + + # mesh + config_add_string mesh_id + config_add_int $MP_CONFIG_INT + config_add_boolean $MP_CONFIG_BOOL + config_add_string $MP_CONFIG_STRING +} + +mac80211_add_capabilities() { + local __var="$1"; shift + local __mask="$1"; shift + local __out= oifs + + oifs="$IFS" + IFS=: + for capab in "$@"; do + set -- $capab + + [ "$(($4))" -gt 0 ] || continue + [ "$(($__mask & $2))" -eq "$((${3:-$2}))" ] || continue + __out="$__out[$1]" + done + IFS="$oifs" + + export -n -- "$__var=$__out" +} + +mac80211_add_he_capabilities() { + local __out= oifs + + oifs="$IFS" + IFS=: + for capab in "$@"; do + set -- $capab + [ "$(($4))" -gt 0 ] || continue + [ "$(((0x$2) & $3))" -gt 0 ] || { + eval "$1=0" + continue + } + append base_cfg "$1=1" "$N" + done + IFS="$oifs" +} + +mac80211_hostapd_setup_base() { + local phy="$1" + + json_select config + + [ "$auto_channel" -gt 0 ] && channel=acs_survey + + [ "$auto_channel" -gt 0 ] && json_get_vars acs_exclude_dfs + [ -n "$acs_exclude_dfs" ] && [ "$acs_exclude_dfs" -gt 0 ] && + append base_cfg "acs_exclude_dfs=1" "$N" + + json_get_vars noscan ht_coex vendor_vht min_tx_power:0 + json_get_values ht_capab_list ht_capab tx_burst + json_get_values channel_list channels + + [ "$auto_channel" = 0 ] && [ -z "$channel_list" ] && \ + channel_list="$channel" + + [ "$min_tx_power" -gt 0 ] && append base_cfg "min_tx_power=$min_tx_power" + + set_default noscan 0 + + [ "$noscan" -gt 0 ] && hostapd_noscan=1 + [ "$tx_burst" = 0 ] && tx_burst= + + chan_ofs=0 + [ "$band" = "6g" ] && chan_ofs=1 + + ieee80211n=1 + ht_capab= + case "$htmode" in + VHT20|HT20|HE20) ;; + HT40*|VHT40|VHT80|VHT160|HE40|HE80|HE160) + case "$hwmode" in + a) + case "$(( (($channel / 4) + $chan_ofs) % 2 ))" in + 1) ht_capab="[HT40+]";; + 0) ht_capab="[HT40-]";; + esac + ;; + *) + case "$htmode" in + HT40+) ht_capab="[HT40+]";; + HT40-) ht_capab="[HT40-]";; + *) + if [ "$channel" -lt 7 ]; then + ht_capab="[HT40+]" + else + ht_capab="[HT40-]" + fi + ;; + esac + ;; + esac + [ "$auto_channel" -gt 0 ] && ht_capab="[HT40+]" + ;; + *) ieee80211n= ;; + esac + + [ -n "$ieee80211n" ] && { + append base_cfg "ieee80211n=1" "$N" + + set_default ht_coex 0 + append base_cfg "ht_coex=$ht_coex" "$N" + + json_get_vars \ + ldpc:1 \ + greenfield:0 \ + short_gi_20:1 \ + short_gi_40:1 \ + tx_stbc:1 \ + rx_stbc:3 \ + max_amsdu:1 \ + dsss_cck_40:1 + + ht_cap_mask=0 + for cap in $(iw phy "$phy" info | grep 'Capabilities:' | cut -d: -f2); do + ht_cap_mask="$(($ht_cap_mask | $cap))" + done + + cap_rx_stbc=$((($ht_cap_mask >> 8) & 3)) + [ "$rx_stbc" -lt "$cap_rx_stbc" ] && cap_rx_stbc="$rx_stbc" + ht_cap_mask="$(( ($ht_cap_mask & ~(0x300)) | ($cap_rx_stbc << 8) ))" + + mac80211_add_capabilities ht_capab_flags $ht_cap_mask \ + LDPC:0x1::$ldpc \ + GF:0x10::$greenfield \ + SHORT-GI-20:0x20::$short_gi_20 \ + SHORT-GI-40:0x40::$short_gi_40 \ + TX-STBC:0x80::$tx_stbc \ + RX-STBC1:0x300:0x100:1 \ + RX-STBC12:0x300:0x200:1 \ + RX-STBC123:0x300:0x300:1 \ + MAX-AMSDU-7935:0x800::$max_amsdu \ + DSSS_CCK-40:0x1000::$dsss_cck_40 + + ht_capab="$ht_capab$ht_capab_flags" + [ -n "$ht_capab" ] && append base_cfg "ht_capab=$ht_capab" "$N" + } + + # 802.11ac + enable_ac=0 + vht_oper_chwidth=0 + vht_center_seg0= + + idx="$channel" + case "$htmode" in + VHT20|HE20) enable_ac=1;; + VHT40|HE40) + case "$(( (($channel / 4) + $chan_ofs) % 2 ))" in + 1) idx=$(($channel + 2));; + 0) idx=$(($channel - 2));; + esac + enable_ac=1 + vht_center_seg0=$idx + ;; + VHT80|HE80) + case "$(( (($channel / 4) + $chan_ofs) % 4 ))" in + 1) idx=$(($channel + 6));; + 2) idx=$(($channel + 2));; + 3) idx=$(($channel - 2));; + 0) idx=$(($channel - 6));; + esac + enable_ac=1 + vht_oper_chwidth=1 + vht_center_seg0=$idx + ;; + VHT160|HE160) + if [ "$band" = "6g" ]; then + case "$channel" in + 1|5|9|13|17|21|25|29) idx=15;; + 33|37|41|45|49|53|57|61) idx=47;; + 65|69|73|77|81|85|89|93) idx=79;; + 97|101|105|109|113|117|121|125) idx=111;; + 129|133|137|141|145|149|153|157) idx=143;; + 161|165|169|173|177|181|185|189) idx=175;; + 193|197|201|205|209|213|217|221) idx=207;; + esac + else + case "$channel" in + 36|40|44|48|52|56|60|64) idx=50;; + 100|104|108|112|116|120|124|128) idx=114;; + esac + fi + enable_ac=1 + vht_oper_chwidth=2 + vht_center_seg0=$idx + ;; + esac + [ "$band" = "5g" ] && { + json_get_vars background_radar:0 + + [ "$background_radar" -eq 1 ] && append base_cfg "enable_background_radar=1" "$N" + } + [ "$band" = "6g" ] && { + op_class= + case "$htmode" in + HE20) op_class=131;; + HE*) op_class=$((132 + $vht_oper_chwidth)) + esac + [ -n "$op_class" ] && append base_cfg "op_class=$op_class" "$N" + } + [ "$hwmode" = "a" ] || enable_ac=0 + + if [ "$enable_ac" != "0" -o "$vendor_vht" = "1" ]; then + json_get_vars \ + rxldpc:1 \ + short_gi_80:1 \ + short_gi_160:1 \ + tx_stbc_2by1:1 \ + su_beamformer:1 \ + su_beamformee:1 \ + mu_beamformer:1 \ + mu_beamformee:1 \ + vht_txop_ps:1 \ + htc_vht:1 \ + beamformee_antennas:4 \ + beamformer_antennas:4 \ + rx_antenna_pattern:1 \ + tx_antenna_pattern:1 \ + vht_max_a_mpdu_len_exp:7 \ + vht_max_mpdu:11454 \ + rx_stbc:4 \ + vht_link_adapt:3 \ + vht160:2 + + set_default tx_burst 2.0 + append base_cfg "ieee80211ac=1" "$N" + vht_cap=0 + for cap in $(iw phy "$phy" info | awk -F "[()]" '/VHT Capabilities/ { print $2 }'); do + vht_cap="$(($vht_cap | $cap))" + done + + append base_cfg "vht_oper_chwidth=$vht_oper_chwidth" "$N" + append base_cfg "vht_oper_centr_freq_seg0_idx=$vht_center_seg0" "$N" + + cap_rx_stbc=$((($vht_cap >> 8) & 7)) + [ "$rx_stbc" -lt "$cap_rx_stbc" ] && cap_rx_stbc="$rx_stbc" + vht_cap="$(( ($vht_cap & ~(0x700)) | ($cap_rx_stbc << 8) ))" + + mac80211_add_capabilities vht_capab $vht_cap \ + RXLDPC:0x10::$rxldpc \ + SHORT-GI-80:0x20::$short_gi_80 \ + SHORT-GI-160:0x40::$short_gi_160 \ + TX-STBC-2BY1:0x80::$tx_stbc_2by1 \ + SU-BEAMFORMER:0x800::$su_beamformer \ + SU-BEAMFORMEE:0x1000::$su_beamformee \ + MU-BEAMFORMER:0x80000::$mu_beamformer \ + MU-BEAMFORMEE:0x100000::$mu_beamformee \ + VHT-TXOP-PS:0x200000::$vht_txop_ps \ + HTC-VHT:0x400000::$htc_vht \ + RX-ANTENNA-PATTERN:0x10000000::$rx_antenna_pattern \ + TX-ANTENNA-PATTERN:0x20000000::$tx_antenna_pattern \ + RX-STBC-1:0x700:0x100:1 \ + RX-STBC-12:0x700:0x200:1 \ + RX-STBC-123:0x700:0x300:1 \ + RX-STBC-1234:0x700:0x400:1 \ + + [ "$(($vht_cap & 0x800))" -gt 0 -a "$su_beamformer" -gt 0 ] && { + cap_ant="$(( ( ($vht_cap >> 16) & 3 ) + 1 ))" + [ "$cap_ant" -gt "$beamformer_antennas" ] && cap_ant="$beamformer_antennas" + [ "$cap_ant" -gt 1 ] && vht_capab="$vht_capab[SOUNDING-DIMENSION-$cap_ant]" + } + + [ "$(($vht_cap & 0x1000))" -gt 0 -a "$su_beamformee" -gt 0 ] && { + cap_ant="$(( ( ($vht_cap >> 13) & 3 ) + 1 ))" + [ "$cap_ant" -gt "$beamformee_antennas" ] && cap_ant="$beamformee_antennas" + [ "$cap_ant" -gt 1 ] && vht_capab="$vht_capab[BF-ANTENNA-$cap_ant]" + } + + # supported Channel widths + vht160_hw=0 + [ "$(($vht_cap & 12))" -eq 4 -a 1 -le "$vht160" ] && \ + vht160_hw=1 + [ "$(($vht_cap & 12))" -eq 8 -a 2 -le "$vht160" ] && \ + vht160_hw=2 + [ "$vht160_hw" = 1 ] && vht_capab="$vht_capab[VHT160]" + [ "$vht160_hw" = 2 ] && vht_capab="$vht_capab[VHT160-80PLUS80]" + + # maximum MPDU length + vht_max_mpdu_hw=3895 + [ "$(($vht_cap & 3))" -ge 1 -a 7991 -le "$vht_max_mpdu" ] && \ + vht_max_mpdu_hw=7991 + [ "$(($vht_cap & 3))" -ge 2 -a 11454 -le "$vht_max_mpdu" ] && \ + vht_max_mpdu_hw=11454 + [ "$vht_max_mpdu_hw" != 3895 ] && \ + vht_capab="$vht_capab[MAX-MPDU-$vht_max_mpdu_hw]" + + # maximum A-MPDU length exponent + vht_max_a_mpdu_len_exp_hw=0 + [ "$(($vht_cap & 58720256))" -ge 8388608 -a 1 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=1 + [ "$(($vht_cap & 58720256))" -ge 16777216 -a 2 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=2 + [ "$(($vht_cap & 58720256))" -ge 25165824 -a 3 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=3 + [ "$(($vht_cap & 58720256))" -ge 33554432 -a 4 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=4 + [ "$(($vht_cap & 58720256))" -ge 41943040 -a 5 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=5 + [ "$(($vht_cap & 58720256))" -ge 50331648 -a 6 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=6 + [ "$(($vht_cap & 58720256))" -ge 58720256 -a 7 -le "$vht_max_a_mpdu_len_exp" ] && \ + vht_max_a_mpdu_len_exp_hw=7 + vht_capab="$vht_capab[MAX-A-MPDU-LEN-EXP$vht_max_a_mpdu_len_exp_hw]" + + # whether or not the STA supports link adaptation using VHT variant + vht_link_adapt_hw=0 + [ "$(($vht_cap & 201326592))" -ge 134217728 -a 2 -le "$vht_link_adapt" ] && \ + vht_link_adapt_hw=2 + [ "$(($vht_cap & 201326592))" -ge 201326592 -a 3 -le "$vht_link_adapt" ] && \ + vht_link_adapt_hw=3 + [ "$vht_link_adapt_hw" != 0 ] && \ + vht_capab="$vht_capab[VHT-LINK-ADAPT-$vht_link_adapt_hw]" + + [ -n "$vht_capab" ] && append base_cfg "vht_capab=$vht_capab" "$N" + fi + + # 802.11ax + enable_ax=0 + case "$htmode" in + HE*) enable_ax=1 ;; + esac + + if [ "$enable_ax" != "0" ]; then + json_get_vars \ + he_su_beamformer:1 \ + he_su_beamformee:1 \ + he_mu_beamformer:1 \ + he_twt_required:0 \ + he_spr_sr_control:3 \ + he_spr_psr_enabled:0 \ + he_spr_non_srg_obss_pd_max_offset:0 \ + he_bss_color:128 \ + he_bss_color_enabled:1 + + he_phy_cap=$(iw phy "$phy" info | sed -n '/HE Iftypes: AP/,$p' | awk -F "[()]" '/HE PHY Capabilities/ { print $2 }' | head -1) + he_phy_cap=${he_phy_cap:2} + he_mac_cap=$(iw phy "$phy" info | sed -n '/HE Iftypes: AP/,$p' | awk -F "[()]" '/HE MAC Capabilities/ { print $2 }' | head -1) + he_mac_cap=${he_mac_cap:2} + + append base_cfg "ieee80211ax=1" "$N" + [ "$hwmode" = "a" ] && { + append base_cfg "he_oper_chwidth=$vht_oper_chwidth" "$N" + append base_cfg "he_oper_centr_freq_seg0_idx=$vht_center_seg0" "$N" + } + + mac80211_add_he_capabilities \ + he_su_beamformer:${he_phy_cap:6:2}:0x80:$he_su_beamformer \ + he_su_beamformee:${he_phy_cap:8:2}:0x1:$he_su_beamformee \ + he_mu_beamformer:${he_phy_cap:8:2}:0x2:$he_mu_beamformer \ + he_spr_psr_enabled:${he_phy_cap:14:2}:0x1:$he_spr_psr_enabled \ + he_twt_required:${he_mac_cap:0:2}:0x6:$he_twt_required + + if [ "$he_bss_color_enabled" -gt 0 ]; then + append base_cfg "he_bss_color=$he_bss_color" "$N" + [ "$he_spr_non_srg_obss_pd_max_offset" -gt 0 ] && { \ + append base_cfg "he_spr_non_srg_obss_pd_max_offset=$he_spr_non_srg_obss_pd_max_offset" "$N" + he_spr_sr_control=$((he_spr_sr_control | (1 << 2))) + } + [ "$he_spr_psr_enabled" -gt 0 ] || he_spr_sr_control=$((he_spr_sr_control | (1 << 0))) + append base_cfg "he_spr_sr_control=$he_spr_sr_control" "$N" + else + append base_cfg "he_bss_color_disabled=1" "$N" + fi + + + append base_cfg "he_default_pe_duration=4" "$N" + append base_cfg "he_rts_threshold=1023" "$N" + append base_cfg "he_mu_edca_qos_info_param_count=0" "$N" + append base_cfg "he_mu_edca_qos_info_q_ack=0" "$N" + append base_cfg "he_mu_edca_qos_info_queue_request=0" "$N" + append base_cfg "he_mu_edca_qos_info_txop_request=0" "$N" + append base_cfg "he_mu_edca_ac_be_aifsn=8" "$N" + append base_cfg "he_mu_edca_ac_be_aci=0" "$N" + append base_cfg "he_mu_edca_ac_be_ecwmin=9" "$N" + append base_cfg "he_mu_edca_ac_be_ecwmax=10" "$N" + append base_cfg "he_mu_edca_ac_be_timer=255" "$N" + append base_cfg "he_mu_edca_ac_bk_aifsn=15" "$N" + append base_cfg "he_mu_edca_ac_bk_aci=1" "$N" + append base_cfg "he_mu_edca_ac_bk_ecwmin=9" "$N" + append base_cfg "he_mu_edca_ac_bk_ecwmax=10" "$N" + append base_cfg "he_mu_edca_ac_bk_timer=255" "$N" + append base_cfg "he_mu_edca_ac_vi_ecwmin=5" "$N" + append base_cfg "he_mu_edca_ac_vi_ecwmax=7" "$N" + append base_cfg "he_mu_edca_ac_vi_aifsn=5" "$N" + append base_cfg "he_mu_edca_ac_vi_aci=2" "$N" + append base_cfg "he_mu_edca_ac_vi_timer=255" "$N" + append base_cfg "he_mu_edca_ac_vo_aifsn=5" "$N" + append base_cfg "he_mu_edca_ac_vo_aci=3" "$N" + append base_cfg "he_mu_edca_ac_vo_ecwmin=5" "$N" + append base_cfg "he_mu_edca_ac_vo_ecwmax=7" "$N" + append base_cfg "he_mu_edca_ac_vo_timer=255" "$N" + fi + + hostapd_prepare_device_config "$hostapd_conf_file" nl80211 + cat >> "$hostapd_conf_file" <> $hostapd_conf_file +} + +mac80211_hostapd_setup_bss() { + local phy="$1" + local ifname="$2" + local macaddr="$3" + local type="$4" + + hostapd_cfg= + append hostapd_cfg "$type=$ifname" "$N" + + hostapd_set_bss_options hostapd_cfg "$phy" "$vif" || return 1 + json_get_vars wds wds_bridge dtim_period max_listen_int start_disabled + + set_default wds 0 + set_default start_disabled 0 + + [ "$wds" -gt 0 ] && { + append hostapd_cfg "wds_sta=1" "$N" + [ -n "$wds_bridge" ] && append hostapd_cfg "wds_bridge=$wds_bridge" "$N" + } + [ "$staidx" -gt 0 -o "$start_disabled" -eq 1 ] && append hostapd_cfg "start_disabled=1" "$N" + + cat >> /var/run/hostapd-$phy.conf </dev/null); do + grep -i -q "$macaddr" "/sys/class/ieee80211/${phy}/macaddress" && return 0 + done + } + return 1 +} + +mac80211_check_ap() { + has_ap=1 +} + +mac80211_iw_interface_add() { + local phy="$1" + local ifname="$2" + local type="$3" + local wdsflag="$4" + local rc + local oldifname + + iw phy "$phy" interface add "$ifname" type "$type" $wdsflag >/dev/null 2>&1 + rc="$?" + + [ "$rc" = 233 ] && { + # Device might have just been deleted, give the kernel some time to finish cleaning it up + sleep 1 + + iw phy "$phy" interface add "$ifname" type "$type" $wdsflag >/dev/null 2>&1 + rc="$?" + } + + [ "$rc" = 233 ] && { + # Keep matching pre-existing interface + [ -d "/sys/class/ieee80211/${phy}/device/net/${ifname}" ] && \ + case "$(iw dev $ifname info | grep "^\ttype" | cut -d' ' -f2- 2>/dev/null)" in + "AP") + [ "$type" = "__ap" ] && rc=0 + ;; + "IBSS") + [ "$type" = "adhoc" ] && rc=0 + ;; + "managed") + [ "$type" = "managed" ] && rc=0 + ;; + "mesh point") + [ "$type" = "mp" ] && rc=0 + ;; + "monitor") + [ "$type" = "monitor" ] && rc=0 + ;; + esac + } + + [ "$rc" = 233 ] && { + iw dev "$ifname" del >/dev/null 2>&1 + [ "$?" = 0 ] && { + sleep 1 + + iw phy "$phy" interface add "$ifname" type "$type" $wdsflag >/dev/null 2>&1 + rc="$?" + } + } + + [ "$rc" != 0 ] && { + # Device might not support virtual interfaces, so the interface never got deleted in the first place. + # Check if the interface already exists, and avoid failing in this case. + [ -d "/sys/class/ieee80211/${phy}/device/net/${ifname}" ] && rc=0 + } + + [ "$rc" != 0 ] && { + # Device doesn't support virtual interfaces and may have existing interface other than ifname. + oldifname="$(basename "/sys/class/ieee80211/${phy}/device/net"/* 2>/dev/null)" + [ "$oldifname" ] && ip link set "$oldifname" name "$ifname" 1>/dev/null 2>&1 + rc="$?" + } + + [ "$rc" != 0 ] && echo "Failed to create interface $ifname" + return $rc +} + +mac80211_prepare_vif() { + json_select config + + json_get_vars ifname mode ssid wds powersave macaddr enable wpa_psk_file vlan_file + + [ -n "$ifname" ] || ifname="wlan${phy#phy}${if_idx:+-$if_idx}" + if_idx=$((${if_idx:-0} + 1)) + + set_default wds 0 + set_default powersave 0 + + json_select .. + + if [ -z "$macaddr" ]; then + macaddr="$(mac80211_generate_mac $phy)" + macidx="$(($macidx + 1))" + elif [ "$macaddr" = 'random' ]; then + macaddr="$(macaddr_random)" + fi + + json_add_object data + json_add_string ifname "$ifname" + json_close_object + + [ "$mode" == "ap" ] && { + [ -z "$wpa_psk_file" ] && hostapd_set_psk "$ifname" + [ -z "$vlan_file" ] && hostapd_set_vlan "$ifname" + } + + json_select config + + # It is far easier to delete and create the desired interface + case "$mode" in + adhoc) + mac80211_iw_interface_add "$phy" "$ifname" adhoc || return + ;; + ap) + # Hostapd will handle recreating the interface and + # subsequent virtual APs belonging to the same PHY + if [ -n "$hostapd_ctrl" ]; then + type=bss + else + type=interface + fi + + mac80211_hostapd_setup_bss "$phy" "$ifname" "$macaddr" "$type" || return + + NEWAPLIST="${NEWAPLIST}$ifname " + [ -n "$hostapd_ctrl" ] || { + ap_ifname="${ifname}" + hostapd_ctrl="${hostapd_ctrl:-/var/run/hostapd/$ifname}" + } + ;; + mesh) + mac80211_iw_interface_add "$phy" "$ifname" mp || return + ;; + monitor) + mac80211_iw_interface_add "$phy" "$ifname" monitor || return + ;; + sta) + local wdsflag= + [ "$enable" = 0 ] || staidx="$(($staidx + 1))" + [ "$wds" -gt 0 ] && wdsflag="4addr on" + mac80211_iw_interface_add "$phy" "$ifname" managed "$wdsflag" || return + if [ "$wds" -gt 0 ]; then + iw "$ifname" set 4addr on + else + iw "$ifname" set 4addr off + fi + [ "$powersave" -gt 0 ] && powersave="on" || powersave="off" + iw "$ifname" set power_save "$powersave" + ;; + esac + + case "$mode" in + monitor|mesh) + [ "$auto_channel" -gt 0 ] || iw dev "$ifname" set channel "$channel" $iw_htmode + ;; + esac + + if [ "$mode" != "ap" ]; then + # ALL ap functionality will be passed to hostapd + # All interfaces must have unique mac addresses + # which can either be explicitly set in the device + # section, or automatically generated + ip link set dev "$ifname" address "$macaddr" + fi + + json_select .. +} + +mac80211_setup_supplicant() { + local enable=$1 + local add_sp=0 + local spobj="$(ubus -S list | grep wpa_supplicant.${ifname})" + + [ "$enable" = 0 ] && { + ubus call wpa_supplicant.${phy} config_remove "{\"iface\":\"$ifname\"}" + ip link set dev "$ifname" down + iw dev "$ifname" del + return 0 + } + + wpa_supplicant_prepare_interface "$ifname" nl80211 || { + iw dev "$ifname" del + return 1 + } + if [ "$mode" = "sta" ]; then + wpa_supplicant_add_network "$ifname" + else + wpa_supplicant_add_network "$ifname" "$freq" "$htmode" "$noscan" + fi + + NEWSPLIST="${NEWSPLIST}$ifname " + + if [ "${NEWAPLIST%% *}" != "${OLDAPLIST%% *}" ]; then + [ "$spobj" ] && ubus call wpa_supplicant config_remove "{\"iface\":\"$ifname\"}" + add_sp=1 + fi + [ -z "$spobj" ] && add_sp=1 + + NEW_MD5_SP=$(test -e "${_config}" && md5sum ${_config}) + OLD_MD5_SP=$(uci -q -P /var/state get wireless._${phy}.md5_${ifname}) + if [ "$add_sp" = "1" ]; then + wpa_supplicant_run "$ifname" "$hostapd_ctrl" + else + [ "${NEW_MD5_SP}" == "${OLD_MD5_SP}" ] || ubus call $spobj reload + fi + uci -q -P /var/state set wireless._${phy}.md5_${ifname}="${NEW_MD5_SP}" + return 0 +} + +mac80211_setup_supplicant_noctl() { + local enable=$1 + local spobj="$(ubus -S list | grep wpa_supplicant.${ifname})" + wpa_supplicant_prepare_interface "$ifname" nl80211 || { + iw dev "$ifname" del + return 1 + } + + wpa_supplicant_add_network "$ifname" "$freq" "$htmode" "$noscan" + + NEWSPLIST="${NEWSPLIST}$ifname " + [ "$enable" = 0 ] && { + ubus call wpa_supplicant config_remove "{\"iface\":\"$ifname\"}" + ip link set dev "$ifname" down + return 0 + } + if [ -z "$spobj" ]; then + wpa_supplicant_run "$ifname" + else + ubus call $spobj reload + fi +} + +mac80211_prepare_iw_htmode() { + case "$htmode" in + VHT20|HT20|HE20) iw_htmode=HT20;; + HT40*|VHT40|VHT160|HE40) + case "$band" in + 2g) + case "$htmode" in + HT40+) iw_htmode="HT40+";; + HT40-) iw_htmode="HT40-";; + *) + if [ "$channel" -lt 7 ]; then + iw_htmode="HT40+" + else + iw_htmode="HT40-" + fi + ;; + esac + ;; + *) + case "$(( ($channel / 4) % 2 ))" in + 1) iw_htmode="HT40+" ;; + 0) iw_htmode="HT40-";; + esac + ;; + esac + [ "$auto_channel" -gt 0 ] && iw_htmode="HT40+" + ;; + VHT80|HE80) + iw_htmode="80MHZ" + ;; + NONE|NOHT) + iw_htmode="NOHT" + ;; + *) iw_htmode="" ;; + esac +} + +mac80211_setup_adhoc() { + local enable=$1 + json_get_vars bssid ssid key mcast_rate + + NEWUMLIST="${NEWUMLIST}$ifname " + + [ "$enable" = 0 ] && { + ip link set dev "$ifname" down + return 0 + } + + keyspec= + [ "$auth_type" = "wep" ] && { + set_default key 1 + case "$key" in + [1234]) + local idx + for idx in 1 2 3 4; do + json_get_var ikey "key$idx" + + [ -n "$ikey" ] && { + ikey="$(($idx - 1)):$(prepare_key_wep "$ikey")" + [ $idx -eq $key ] && ikey="d:$ikey" + append keyspec "$ikey" + } + done + ;; + *) + append keyspec "d:0:$(prepare_key_wep "$key")" + ;; + esac + } + + brstr= + for br in $basic_rate_list; do + wpa_supplicant_add_rate brstr "$br" + done + + mcval= + [ -n "$mcast_rate" ] && wpa_supplicant_add_rate mcval "$mcast_rate" + + iw dev "$ifname" set type ibss + iw dev "$ifname" ibss join "$ssid" $freq $iw_htmode fixed-freq $bssid \ + beacon-interval $beacon_int \ + ${brstr:+basic-rates $brstr} \ + ${mcval:+mcast-rate $mcval} \ + ${keyspec:+keys $keyspec} +} + +mac80211_setup_mesh() { + local enable=$1 + json_get_vars ssid mesh_id mcast_rate + + NEWUMLIST="${NEWUMLIST}$ifname " + + [ "$enable" = 0 ] && { + ip link set dev "$ifname" down + return 0 + } + + mcval= + [ -n "$mcast_rate" ] && wpa_supplicant_add_rate mcval "$mcast_rate" + [ -n "$mesh_id" ] && ssid="$mesh_id" + + iw dev "$ifname" mesh join "$ssid" freq $freq $iw_htmode \ + ${mcval:+mcast-rate $mcval} \ + beacon-interval $beacon_int +} + +mac80211_setup_vif() { + local name="$1" + local failed + local action=up + + json_select data + json_get_vars ifname + json_select .. + + json_select config + json_get_vars mode + json_get_var vif_txpower + json_get_var vif_enable enable 1 + + [ "$vif_enable" = 1 ] || action=down + if [ "$mode" != "ap" ] || [ "$ifname" = "$ap_ifname" ]; then + ip link set dev "$ifname" "$action" || { + wireless_setup_vif_failed IFUP_ERROR + json_select .. + return + } + [ -z "$vif_txpower" ] || iw dev "$ifname" set txpower fixed "${vif_txpower%%.*}00" + fi + + case "$mode" in + mesh) + wireless_vif_parse_encryption + [ -z "$htmode" ] && htmode="NOHT"; + if [ "$wpa" -gt 0 -o "$auto_channel" -gt 0 ] || chan_is_dfs "$phy" "$channel"; then + mac80211_setup_supplicant $vif_enable || failed=1 + else + mac80211_setup_mesh $vif_enable + fi + for var in $MP_CONFIG_INT $MP_CONFIG_BOOL $MP_CONFIG_STRING; do + json_get_var mp_val "$var" + [ -n "$mp_val" ] && iw dev "$ifname" set mesh_param "$var" "$mp_val" + done + ;; + adhoc) + wireless_vif_parse_encryption + if [ "$wpa" -gt 0 -o "$auto_channel" -gt 0 ]; then + mac80211_setup_supplicant_noctl $vif_enable || failed=1 + else + mac80211_setup_adhoc $vif_enable + fi + ;; + sta) + mac80211_setup_supplicant $vif_enable || failed=1 + ;; + esac + + json_select .. + [ -n "$failed" ] || wireless_add_vif "$name" "$ifname" +} + +get_freq() { + local phy="$1" + local channel="$2" + local band="$3" + + case "$band" in + 2g) band="1:";; + 5g) band="2:";; + 60g) band="3:";; + 6g) band="4:";; + esac + + iw "$phy" info | awk -v band="$band" -v channel="[$channel]" ' + +$1 ~ /Band/ { + band_match = band == $2 +} + +band_match && $3 == "MHz" && $4 == channel { + print $2 + exit +} +' +} + + +chan_is_dfs() { + local phy="$1" + local chan="$2" + iw "$phy" info | grep -E -m1 "(\* ${chan:-....} MHz${chan:+|\\[$chan\\]})" | grep -q "MHz.*radar detection" + return $! +} + +mac80211_vap_cleanup() { + local service="$1" + local vaps="$2" + + for wdev in $vaps; do + [ "$service" != "none" ] && ubus call ${service} config_remove "{\"iface\":\"$wdev\"}" + ip link set dev "$wdev" down 2>/dev/null + iw dev "$wdev" del + done +} + +mac80211_interface_cleanup() { + local phy="$1" + local primary_ap=$(uci -q -P /var/state get wireless._${phy}.aplist) + primary_ap=${primary_ap%% *} + + mac80211_vap_cleanup hostapd "${primary_ap}" + mac80211_vap_cleanup wpa_supplicant "$(uci -q -P /var/state get wireless._${phy}.splist)" + mac80211_vap_cleanup none "$(uci -q -P /var/state get wireless._${phy}.umlist)" +} + +mac80211_set_noscan() { + hostapd_noscan=1 +} + +drv_mac80211_cleanup() { + hostapd_common_cleanup +} + +drv_mac80211_setup() { + json_select config + json_get_vars \ + phy macaddr path \ + country chanbw distance \ + txpower antenna_gain \ + rxantenna txantenna \ + frag rts beacon_int:100 htmode + json_get_values basic_rate_list basic_rate + json_get_values scan_list scan_list + json_select .. + + find_phy || { + echo "Could not find PHY for device '$1'" + wireless_set_retry 0 + return 1 + } + + wireless_set_data phy="$phy" + [ -z "$(uci -q -P /var/state show wireless._${phy})" ] && uci -q -P /var/state set wireless._${phy}=phy + + OLDAPLIST=$(uci -q -P /var/state get wireless._${phy}.aplist) + OLDSPLIST=$(uci -q -P /var/state get wireless._${phy}.splist) + OLDUMLIST=$(uci -q -P /var/state get wireless._${phy}.umlist) + + local wdev + local cwdev + local found + + for wdev in $(list_phy_interfaces "$phy"); do + found=0 + for cwdev in $OLDAPLIST $OLDSPLIST $OLDUMLIST; do + if [ "$wdev" = "$cwdev" ]; then + found=1 + break + fi + done + if [ "$found" = "0" ]; then + ip link set dev "$wdev" down + iw dev "$wdev" del + fi + done + + # convert channel to frequency + [ "$auto_channel" -gt 0 ] || freq="$(get_freq "$phy" "$channel" "$band")" + + [ -n "$country" ] && { + iw reg get | grep -q "^country $country:" || { + iw reg set "$country" + sleep 1 + } + } + + hostapd_conf_file="/var/run/hostapd-$phy.conf" + + no_ap=1 + macidx=0 + staidx=0 + + [ -n "$chanbw" ] && { + for file in /sys/kernel/debug/ieee80211/$phy/ath9k*/chanbw /sys/kernel/debug/ieee80211/$phy/ath5k/bwmode; do + [ -f "$file" ] && echo "$chanbw" > "$file" + done + } + + set_default rxantenna 0xffffffff + set_default txantenna 0xffffffff + set_default distance 0 + set_default antenna_gain 0 + + [ "$txantenna" = "all" ] && txantenna=0xffffffff + [ "$rxantenna" = "all" ] && rxantenna=0xffffffff + + iw phy "$phy" set antenna $txantenna $rxantenna >/dev/null 2>&1 + iw phy "$phy" set antenna_gain $antenna_gain >/dev/null 2>&1 + iw phy "$phy" set distance "$distance" >/dev/null 2>&1 + + if [ -n "$txpower" ]; then + iw phy "$phy" set txpower fixed "${txpower%%.*}00" + else + iw phy "$phy" set txpower auto + fi + + [ -n "$frag" ] && iw phy "$phy" set frag "${frag%%.*}" + [ -n "$rts" ] && iw phy "$phy" set rts "${rts%%.*}" + + has_ap= + hostapd_ctrl= + ap_ifname= + hostapd_noscan= + for_each_interface "ap" mac80211_check_ap + + rm -f "$hostapd_conf_file" + + for_each_interface "sta adhoc mesh" mac80211_set_noscan + [ -n "$has_ap" ] && mac80211_hostapd_setup_base "$phy" + + mac80211_prepare_iw_htmode + for_each_interface "sta adhoc mesh monitor" mac80211_prepare_vif + NEWAPLIST= + for_each_interface "ap" mac80211_prepare_vif + NEW_MD5=$(test -e "${hostapd_conf_file}" && md5sum ${hostapd_conf_file}) + OLD_MD5=$(uci -q -P /var/state get wireless._${phy}.md5) + if [ "${NEWAPLIST}" != "${OLDAPLIST}" ]; then + mac80211_vap_cleanup hostapd "${OLDAPLIST}" + fi + [ -n "${NEWAPLIST}" ] && mac80211_iw_interface_add "$phy" "${NEWAPLIST%% *}" __ap + local add_ap=0 + local primary_ap=${NEWAPLIST%% *} + [ -n "$hostapd_ctrl" ] && { + local no_reload=1 + if [ -n "$(ubus list | grep hostapd.$primary_ap)" ]; then + no_reload=0 + [ "${NEW_MD5}" = "${OLD_MD5}" ] || { + ubus call hostapd.$primary_ap reload + no_reload=$? + if [ "$no_reload" != "0" ]; then + mac80211_vap_cleanup hostapd "${OLDAPLIST}" + mac80211_vap_cleanup wpa_supplicant "$(uci -q -P /var/state get wireless._${phy}.splist)" + mac80211_vap_cleanup none "$(uci -q -P /var/state get wireless._${phy}.umlist)" + sleep 2 + mac80211_iw_interface_add "$phy" "${NEWAPLIST%% *}" __ap + for_each_interface "sta adhoc mesh monitor" mac80211_prepare_vif + fi + } + fi + if [ "$no_reload" != "0" ]; then + add_ap=1 + ubus wait_for hostapd + local hostapd_res="$(ubus call hostapd config_add "{\"iface\":\"$primary_ap\", \"config\":\"${hostapd_conf_file}\"}")" + ret="$?" + [ "$ret" != 0 -o -z "$hostapd_res" ] && { + wireless_setup_failed HOSTAPD_START_FAILED + return + } + wireless_add_process "$(jsonfilter -s "$hostapd_res" -l 1 -e @.pid)" "/usr/sbin/hostapd" 1 1 + fi + } + uci -q -P /var/state set wireless._${phy}.aplist="${NEWAPLIST}" + uci -q -P /var/state set wireless._${phy}.md5="${NEW_MD5}" + + [ "${add_ap}" = 1 ] && sleep 1 + for_each_interface "ap" mac80211_setup_vif + + NEWSPLIST= + NEWUMLIST= + + for_each_interface "sta adhoc mesh monitor" mac80211_setup_vif + + uci -q -P /var/state set wireless._${phy}.splist="${NEWSPLIST}" + uci -q -P /var/state set wireless._${phy}.umlist="${NEWUMLIST}" + + local foundvap + local dropvap="" + for oldvap in $OLDSPLIST; do + foundvap=0 + for newvap in $NEWSPLIST; do + [ "$oldvap" = "$newvap" ] && foundvap=1 + done + [ "$foundvap" = "0" ] && dropvap="$dropvap $oldvap" + done + [ -n "$dropvap" ] && mac80211_vap_cleanup wpa_supplicant "$dropvap" + wireless_set_up +} + +_list_phy_interfaces() { + local phy="$1" + if [ -d "/sys/class/ieee80211/${phy}/device/net" ]; then + ls "/sys/class/ieee80211/${phy}/device/net" 2>/dev/null; + else + ls "/sys/class/ieee80211/${phy}/device" 2>/dev/null | grep net: | sed -e 's,net:,,g' + fi +} + +list_phy_interfaces() { + local phy="$1" + + for dev in $(_list_phy_interfaces "$phy"); do + readlink "/sys/class/net/${dev}/phy80211" | grep -q "/${phy}\$" || continue + echo "$dev" + done +} + +drv_mac80211_teardown() { + json_select data + json_get_vars phy + json_select .. + [ -n "$phy" ] || { + echo "Bug: PHY is undefined for device '$1'" + return 1 + } + + mac80211_interface_cleanup "$phy" + uci -q -P /var/state revert wireless._${phy} +} + +add_driver mac80211 diff --git a/package/kernel/mac80211/files/lib/wifi/mac80211.sh b/package/kernel/mac80211/files/lib/wifi/mac80211.sh new file mode 100644 index 000000000..4c5981850 --- /dev/null +++ b/package/kernel/mac80211/files/lib/wifi/mac80211.sh @@ -0,0 +1,191 @@ +#!/bin/sh + +append DRIVERS "mac80211" + +lookup_phy() { + [ -n "$phy" ] && { + [ -d /sys/class/ieee80211/$phy ] && return + } + + local devpath + config_get devpath "$device" path + [ -n "$devpath" ] && { + phy="$(iwinfo nl80211 phyname "path=$devpath")" + [ -n "$phy" ] && return + } + + local macaddr="$(config_get "$device" macaddr | tr 'A-Z' 'a-z')" + [ -n "$macaddr" ] && { + for _phy in /sys/class/ieee80211/*; do + [ -e "$_phy" ] || continue + + [ "$macaddr" = "$(cat ${_phy}/macaddress)" ] || continue + phy="${_phy##*/}" + return + done + } + phy= + return +} + +find_mac80211_phy() { + local device="$1" + + config_get phy "$device" phy + lookup_phy + [ -n "$phy" -a -d "/sys/class/ieee80211/$phy" ] || { + echo "PHY for wifi device $1 not found" + return 1 + } + config_set "$device" phy "$phy" + + config_get macaddr "$device" macaddr + [ -z "$macaddr" ] && { + config_set "$device" macaddr "$(cat /sys/class/ieee80211/${phy}/macaddress)" + } + + return 0 +} + +check_mac80211_device() { + config_get phy "$1" phy + [ -z "$phy" ] && { + find_mac80211_phy "$1" >/dev/null || return 0 + config_get phy "$1" phy + } + [ "$phy" = "$dev" ] && found=1 +} + + +__get_band_defaults() { + local phy="$1" + + ( iw phy "$phy" info; echo ) | awk ' +BEGIN { + bands = "" +} + +($1 == "Band" || $1 == "") && band { + if (channel) { + mode="NOHT" + if (ht) mode="HT20" + if (vht && band != "1:") mode="VHT80" + if (he) mode="HE80" + if (he && band == "1:") mode="HE20" + sub("\\[", "", channel) + sub("\\]", "", channel) + bands = bands band channel ":" mode " " + } + band="" +} + +$1 == "Band" { + band = $2 + channel = "" + vht = "" + ht = "" + he = "" +} + +$0 ~ "Capabilities:" { + ht=1 +} + +$0 ~ "VHT Capabilities" { + vht=1 +} + +$0 ~ "HE Iftypes" { + he=1 +} + +$1 == "*" && $3 == "MHz" && $0 !~ /disabled/ && band && !channel { + channel = $4 +} + +END { + print bands +}' +} + +get_band_defaults() { + local phy="$1" + + for c in $(__get_band_defaults "$phy"); do + local band="${c%%:*}" + c="${c#*:}" + local chan="${c%%:*}" + c="${c#*:}" + local mode="${c%%:*}" + + case "$band" in + 1) band=2g;; + 2) band=5g;; + 3) band=60g;; + 4) band=6g;; + *) band="";; + esac + + [ -n "$band" ] || continue + [ -n "$mode_band" -a "$band" = "6g" ] && return + + mode_band="$band" + channel="$chan" + htmode="$mode" + done +} + +detect_mac80211() { + devidx=0 + config_load wireless + while :; do + config_get type "radio$devidx" type + [ -n "$type" ] || break + devidx=$(($devidx + 1)) + done + + for _dev in /sys/class/ieee80211/*; do + [ -e "$_dev" ] || continue + + dev="${_dev##*/}" + + found=0 + config_foreach check_mac80211_device wifi-device + [ "$found" -gt 0 ] && continue + + mode_band="" + channel="" + htmode="" + ht_capab="" + + get_band_defaults "$dev" + + path="$(iwinfo nl80211 path "$dev")" + if [ -n "$path" ]; then + dev_id="set wireless.radio${devidx}.path='$path'" + else + dev_id="set wireless.radio${devidx}.macaddr=$(cat /sys/class/ieee80211/${dev}/macaddress)" + fi + + uci -q batch <<-EOF + set wireless.radio${devidx}=wifi-device + set wireless.radio${devidx}.type=mac80211 + ${dev_id} + set wireless.radio${devidx}.channel=${channel} + set wireless.radio${devidx}.band=${mode_band} + set wireless.radio${devidx}.htmode=$htmode + set wireless.radio${devidx}.disabled=0 + set wireless.radio${devidx}.country=US + + set wireless.default_radio${devidx}=wifi-iface + set wireless.default_radio${devidx}.device=radio${devidx} + set wireless.default_radio${devidx}.network=lan + set wireless.default_radio${devidx}.mode=ap + set wireless.default_radio${devidx}.ssid=OpenWrt + set wireless.default_radio${devidx}.encryption=none +EOF + uci -q commit wireless + + devidx=$(($devidx + 1)) + done +} diff --git a/package/kernel/mac80211/files/mac80211.hotplug b/package/kernel/mac80211/files/mac80211.hotplug new file mode 100644 index 000000000..b86555266 --- /dev/null +++ b/package/kernel/mac80211/files/mac80211.hotplug @@ -0,0 +1,5 @@ +#!/bin/sh + +[ "${ACTION}" = "add" ] && { + /sbin/wifi config +} diff --git a/package/kernel/mac80211/intel.mk b/package/kernel/mac80211/intel.mk index 63b19a55c..8d374d73e 100644 --- a/package/kernel/mac80211/intel.mk +++ b/package/kernel/mac80211/intel.mk @@ -6,7 +6,7 @@ config-$(CONFIG_PACKAGE_IWLWIFI_DEBUGFS)+= IWLWIFI_DEBUGFS define KernelPackage/iwlwifi $(call KernelPackage/mac80211/Default) - DEPENDS:= +kmod-mac80211 +kmod-ptp @PCI_SUPPORT +@DRIVER_11AC_SUPPORT +@DRIVER_11AX_SUPPORT @!LINUX_5_15 + DEPENDS:= +kmod-mac80211 @PCI_SUPPORT +@DRIVER_11AC_SUPPORT +@DRIVER_11AX_SUPPORT TITLE:=Intel AGN Wireless support FILES:= \ $(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlwifi/iwlwifi.ko \ diff --git a/package/kernel/mac80211/patches/ath/400-ath_move_debug_code.patch b/package/kernel/mac80211/patches/ath/400-ath_move_debug_code.patch index 23b7340e2..eacc72776 100644 --- a/package/kernel/mac80211/patches/ath/400-ath_move_debug_code.patch +++ b/package/kernel/mac80211/patches/ath/400-ath_move_debug_code.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/Makefile +++ b/drivers/net/wireless/ath/Makefile -@@ -16,10 +16,10 @@ ath-objs := main.o \ +@@ -15,10 +15,10 @@ ath-objs := main.o \ regd.o \ hw.o \ key.o \ @@ -14,7 +14,7 @@ CFLAGS_trace.o := -I$(src) --- a/drivers/net/wireless/ath/ath.h +++ b/drivers/net/wireless/ath/ath.h -@@ -321,14 +321,7 @@ void _ath_dbg(struct ath_common *common, +@@ -317,14 +317,7 @@ void _ath_dbg(struct ath_common *common, #endif /* CPTCFG_ATH_DEBUG */ /** Returns string describing opmode, or NULL if unknown mode. */ diff --git a/package/kernel/mac80211/patches/ath/402-ath_regd_optional.patch b/package/kernel/mac80211/patches/ath/402-ath_regd_optional.patch index 0f6a570cb..fd5493de7 100644 --- a/package/kernel/mac80211/patches/ath/402-ath_regd_optional.patch +++ b/package/kernel/mac80211/patches/ath/402-ath_regd_optional.patch @@ -82,7 +82,7 @@ help --- a/local-symbols +++ b/local-symbols -@@ -94,6 +94,7 @@ ADM8211= +@@ -102,6 +102,7 @@ ADM8211= ATH_COMMON= WLAN_VENDOR_ATH= ATH_DEBUG= diff --git a/package/kernel/mac80211/patches/ath/404-regd_no_assoc_hints.patch b/package/kernel/mac80211/patches/ath/404-regd_no_assoc_hints.patch index 895e2ff8d..8d83921a3 100644 --- a/package/kernel/mac80211/patches/ath/404-regd_no_assoc_hints.patch +++ b/package/kernel/mac80211/patches/ath/404-regd_no_assoc_hints.patch @@ -1,6 +1,6 @@ --- a/net/wireless/reg.c +++ b/net/wireless/reg.c -@@ -3364,6 +3364,8 @@ void regulatory_hint_country_ie(struct w +@@ -3370,6 +3370,8 @@ void regulatory_hint_country_ie(struct w enum environment_cap env = ENVIRON_ANY; struct regulatory_request *request = NULL, *lr; @@ -9,7 +9,7 @@ /* IE len must be evenly divisible by 2 */ if (country_ie_len & 0x01) return; -@@ -3615,6 +3617,7 @@ static bool is_wiphy_all_set_reg_flag(en +@@ -3621,6 +3623,7 @@ static bool is_wiphy_all_set_reg_flag(en void regulatory_hint_disconnect(void) { diff --git a/package/kernel/mac80211/patches/ath/431-add_platform_eeprom_support_to_ath5k.patch b/package/kernel/mac80211/patches/ath/431-add_platform_eeprom_support_to_ath5k.patch index c762aa6d6..136be1989 100644 --- a/package/kernel/mac80211/patches/ath/431-add_platform_eeprom_support_to_ath5k.patch +++ b/package/kernel/mac80211/patches/ath/431-add_platform_eeprom_support_to_ath5k.patch @@ -18,7 +18,7 @@ static bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) @@ -79,6 +80,19 @@ ath5k_pci_eeprom_read(struct ath_common - struct ath5k_hw *ah = common->ah; + struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; u32 status, timeout; + struct ath5k_platform_data *pdata = NULL; diff --git a/package/kernel/mac80211/patches/ath10k/080-ath10k_thermal_config.patch b/package/kernel/mac80211/patches/ath10k/080-ath10k_thermal_config.patch index c41bfa888..41ad6006b 100644 --- a/package/kernel/mac80211/patches/ath10k/080-ath10k_thermal_config.patch +++ b/package/kernel/mac80211/patches/ath10k/080-ath10k_thermal_config.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath10k/Kconfig +++ b/drivers/net/wireless/ath/ath10k/Kconfig -@@ -88,6 +88,12 @@ config ATH10K_TRACING +@@ -86,6 +86,12 @@ config ATH10K_TRACING help Select this to ath10k use tracing infrastructure. @@ -37,7 +37,7 @@ void ath10k_thermal_event_temperature(struct ath10k *ar, int temperature); --- a/local-symbols +++ b/local-symbols -@@ -153,6 +153,7 @@ ATH10K_SNOC= +@@ -161,6 +161,7 @@ ATH10K_SNOC= ATH10K_DEBUG= ATH10K_DEBUGFS= ATH10K_SPECTRAL= diff --git a/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch b/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch new file mode 100644 index 000000000..8ca8f3b55 --- /dev/null +++ b/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch @@ -0,0 +1,12 @@ +--- a/drivers/net/wireless/ath/ath10k/debug.c ++++ b/drivers/net/wireless/ath/ath10k/debug.c +@@ -1260,6 +1260,9 @@ static int ath10k_debug_cal_data_fetch(s + if (ar->hw_params.cal_data_len == 0) + return -EOPNOTSUPP; + ++ if (ar->hif.bus == ATH10K_BUS_SDIO) ++ return -EINVAL; ++ + hi_addr = host_interest_item_address(HI_ITEM(hi_board_data)); + + ret = ath10k_hif_diag_read(ar, hi_addr, &addr, sizeof(addr)); diff --git a/package/kernel/mac80211/patches/ath10k/921-ath10k_init_devices_synchronously.patch b/package/kernel/mac80211/patches/ath10k/921-ath10k_init_devices_synchronously.patch index 479c74e47..f5e702195 100644 --- a/package/kernel/mac80211/patches/ath10k/921-ath10k_init_devices_synchronously.patch +++ b/package/kernel/mac80211/patches/ath10k/921-ath10k_init_devices_synchronously.patch @@ -14,7 +14,7 @@ Signed-off-by: Sven Eckelmann --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c -@@ -3527,6 +3527,16 @@ int ath10k_core_register(struct ath10k * +@@ -3516,6 +3516,17 @@ int ath10k_core_register(struct ath10k * queue_work(ar->workqueue, &ar->register_work); @@ -26,7 +26,8 @@ Signed-off-by: Sven Eckelmann + * Forcing the work to be done immediately works around this problem + * but may also delay the boot when firmware images cannot be found. + */ -+ flush_workqueue(ar->workqueue); ++ if (ar->hif.bus != ATH10K_BUS_SDIO) ++ flush_workqueue(ar->workqueue); + return 0; } diff --git a/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch b/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch index c9ad4018c..e8beed17e 100644 --- a/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch +++ b/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -9918,6 +9918,21 @@ static int ath10k_mac_init_rd(struct ath +@@ -9909,6 +9909,21 @@ static int ath10k_mac_init_rd(struct ath return 0; } @@ -22,7 +22,7 @@ int ath10k_mac_register(struct ath10k *ar) { static const u32 cipher_suites[] = { -@@ -10280,6 +10295,12 @@ int ath10k_mac_register(struct ath10k *a +@@ -10267,6 +10282,12 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; diff --git a/package/kernel/mac80211/patches/ath10k/974-wifi-ath10k-add-LED-and-GPIO-controlling-support-for.patch b/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch similarity index 67% rename from package/kernel/mac80211/patches/ath10k/974-wifi-ath10k-add-LED-and-GPIO-controlling-support-for.patch rename to package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch index a9eb38e57..fd5b44811 100644 --- a/package/kernel/mac80211/patches/ath10k/974-wifi-ath10k-add-LED-and-GPIO-controlling-support-for.patch +++ b/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch @@ -1,52 +1,103 @@ -From 8e1debd82466a3fe711784ab37e6b54e56011267 Mon Sep 17 00:00:00 2001 -From: Sebastian Gottschall -Date: Mon, 13 May 2024 17:22:25 +0300 -Subject: [PATCH] wifi: ath10k: add LED and GPIO controlling support for - various chipsets +From: Sebastian Gottschall + +Adds LED and GPIO Control support for 988x, 9887, 9888, 99x0, 9984 based +chipsets with on chipset connected led's using WMI Firmware API. The LED +device will get available named as "ath10k-phyX" at sysfs and can be controlled +with various triggers. adds also debugfs interface for gpio control. + +This patch is specific for OpenWRt base, as is use old backported package +with old wireless source. Support for QCA9984 is removed and a simbol +is added to local-simbol file to export the actually compile the code +with the ATH10K_LEDS simbol. -Adds LED and GPIO Control support for 988x, 9887, 9888, 99x0, 9984 -based chipsets with on chipset connected led's using WMI Firmware API. -The LED device will get available named as "ath10k-phyX" at sysfs and -can be controlled with various triggers. -Adds also debugfs interface for gpio control. Signed-off-by: Sebastian Gottschall Reviewed-by: Steve deRosier [kvalo: major reorg and cleanup] Signed-off-by: Kalle Valo -[ansuel: rebase and small cleanup] -Signed-off-by: Christian Marangi -Tested-by: Stefan Lippers-Hollmann -Signed-off-by: Kalle Valo -Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com +Signed-off-by: Ansuel Smith --- - drivers/net/wireless/ath/ath10k/Kconfig | 6 ++ - drivers/net/wireless/ath/ath10k/Makefile | 1 + - drivers/net/wireless/ath/ath10k/core.c | 32 ++++++++ - drivers/net/wireless/ath/ath10k/core.h | 8 ++ - drivers/net/wireless/ath/ath10k/hw.h | 1 + - drivers/net/wireless/ath/ath10k/leds.c | 90 +++++++++++++++++++++++ - drivers/net/wireless/ath/ath10k/leds.h | 34 +++++++++ - drivers/net/wireless/ath/ath10k/mac.c | 1 + - drivers/net/wireless/ath/ath10k/wmi-ops.h | 32 ++++++++ - drivers/net/wireless/ath/ath10k/wmi-tlv.c | 2 + - drivers/net/wireless/ath/ath10k/wmi.c | 54 ++++++++++++++ - drivers/net/wireless/ath/ath10k/wmi.h | 35 +++++++++ - 12 files changed, 296 insertions(+) + +v13: + +* only compile tested! + +* fix all checkpatch warnings + +* fix commit log + +* sizeof(struct ath10k_gpiocontrol) -> sizeof(*gpio) + +* unsigned -> unsigned int + +* remove GPIOLIB code, that should be added in a separate patch + +* rename gpio.c to leds.c + +* add leds.h + +* rename some functions: + + ath10k_attach_led() -> ath10k_leds_register() + ath10k_unregister_led() -> ath10k_leds_unregister() + ath10k_reset_led_pin() -> ath10k_leds_start() + +* call ath10k_leds_unregister() before ath10k_thermal_unregister() to preserve ordering + +* call ath10k_leds_start() only from ath10k_core_start() and not from mac.c + +* rename struct ath10k_gpiocontrol as anonymous function under struct + ath10k::leds, no need for memory allocation + +* merge ath10k_add_led() to ath10k_attach_led(), which is it's only caller + +* remove #if IS_ENABLED() checks from most of places, memory savings from those were not worth it + +* Kconfig help text improvement and move it lower in the menu, also don't enable it by default + +* switch to set_brightness_blocking() so that the callback can sleep, + then no need to use ath10k_wmi_cmd_send_nowait() and can take mutex + to access ar->state + +* don't touch ath10k_wmi_pdev_get_temperature() + +* as QCA6174/QCA9377 are not (yet) supported don't add the command to WMI-TLV interface + +* remove debugfs interface, that should be added in another patch + +* cleanup includes + + + drivers/net/wireless/ath/ath10k/Kconfig | 10 +++ + drivers/net/wireless/ath/ath10k/Makefile | 1 + + drivers/net/wireless/ath/ath10k/core.c | 22 +++++++ + drivers/net/wireless/ath/ath10k/core.h | 9 ++- + drivers/net/wireless/ath/ath10k/hw.h | 1 + + drivers/net/wireless/ath/ath10k/leds.c | 103 ++++++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath10k/leds.h | 45 +++++++++++++ + drivers/net/wireless/ath/ath10k/mac.c | 1 + + drivers/net/wireless/ath/ath10k/wmi-ops.h | 32 ++++++++++ + drivers/net/wireless/ath/ath10k/wmi-tlv.c | 2 + + drivers/net/wireless/ath/ath10k/wmi.c | 54 ++++++++++++++++ + drivers/net/wireless/ath/ath10k/wmi.h | 35 ++++++++++ + 12 files changed, 314 insertions(+), 1 deletion(-) create mode 100644 drivers/net/wireless/ath/ath10k/leds.c create mode 100644 drivers/net/wireless/ath/ath10k/leds.h - --- a/drivers/net/wireless/ath/ath10k/Kconfig +++ b/drivers/net/wireless/ath/ath10k/Kconfig -@@ -73,6 +73,12 @@ config ATH10K_DEBUGFS +@@ -71,6 +71,16 @@ config ATH10K_DEBUGFS If unsure, say Y to make it easier to debug problems. +config ATH10K_LEDS -+ bool ++ bool "Atheros ath10k LED support" + depends on ATH10K -+ depends on LEDS_CLASS=y || LEDS_CLASS=MAC80211 ++ select MAC80211_LEDS ++ select LEDS_CLASS ++ select NEW_LEDS + default y ++ ---help--- ++ This option is necessary, if you want LED support for chipset connected led pins. If unsure, say N. + config ATH10K_SPECTRAL bool "Atheros ath10k spectral scan support" @@ -63,7 +114,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com ath10k_core-$(CONFIG_DEV_COREDUMP) += coredump.o --- a/local-symbols +++ b/local-symbols -@@ -154,6 +154,7 @@ ATH10K_DEBUG= +@@ -162,6 +162,7 @@ ATH10K_DEBUG= ATH10K_DEBUGFS= ATH10K_SPECTRAL= ATH10K_THERMAL= @@ -73,7 +124,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com WCN36XX= --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c -@@ -27,6 +27,7 @@ +@@ -26,6 +26,7 @@ #include "testmode.h" #include "wmi-ops.h" #include "coredump.h" @@ -81,135 +132,47 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com unsigned int ath10k_debug_mask; EXPORT_SYMBOL(ath10k_debug_mask); -@@ -68,6 +69,7 @@ static const struct ath10k_hw_params ath +@@ -65,6 +66,7 @@ static const struct ath10k_hw_params ath + .dev_id = QCA988X_2_0_DEVICE_ID, + .bus = ATH10K_BUS_PCI, .name = "qca988x hw2.0", - .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, - .uart_pin = 7, + .led_pin = 1, - .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, -@@ -109,6 +111,7 @@ static const struct ath10k_hw_params ath - .name = "qca988x hw2.0 ubiquiti", .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, .uart_pin = 7, -+ .led_pin = 0, .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, -@@ -151,6 +154,7 @@ static const struct ath10k_hw_params ath +@@ -146,6 +148,7 @@ static const struct ath10k_hw_params ath + .dev_id = QCA9887_1_0_DEVICE_ID, + .bus = ATH10K_BUS_PCI, .name = "qca9887 hw1.0", ++ .led_pin = 1, .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, .uart_pin = 7, -+ .led_pin = 1, .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, -@@ -193,6 +197,7 @@ static const struct ath10k_hw_params ath - .name = "qca6174 hw3.2 sdio", - .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, - .uart_pin = 19, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -230,6 +235,7 @@ static const struct ath10k_hw_params ath - .name = "qca6164 hw2.1", - .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, - .uart_pin = 6, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -271,6 +277,7 @@ static const struct ath10k_hw_params ath - .name = "qca6174 hw2.1", - .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, - .uart_pin = 6, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -312,6 +319,7 @@ static const struct ath10k_hw_params ath - .name = "qca6174 hw3.0", - .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, - .uart_pin = 6, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -353,6 +361,7 @@ static const struct ath10k_hw_params ath - .name = "qca6174 hw3.2", - .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, - .uart_pin = 6, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -398,6 +407,7 @@ static const struct ath10k_hw_params ath +@@ -387,6 +390,7 @@ static const struct ath10k_hw_params ath + .dev_id = QCA99X0_2_0_DEVICE_ID, + .bus = ATH10K_BUS_PCI, .name = "qca99x0 hw2.0", ++ .led_pin = 17, .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, .uart_pin = 7, -+ .led_pin = 17, .otp_exe_param = 0x00000700, - .continuous_frag_desc = true, - .cck_rate_map_rev2 = true, -@@ -445,6 +455,7 @@ static const struct ath10k_hw_params ath +@@ -433,6 +437,7 @@ static const struct ath10k_hw_params ath + .dev_id = QCA9984_1_0_DEVICE_ID, + .bus = ATH10K_BUS_PCI, .name = "qca9984/qca9994 hw1.0", ++ .led_pin = 17, .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, .uart_pin = 7, -+ .led_pin = 17, .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, - .otp_exe_param = 0x00000700, - .continuous_frag_desc = true, -@@ -499,6 +510,7 @@ static const struct ath10k_hw_params ath +@@ -486,6 +491,7 @@ static const struct ath10k_hw_params ath + .dev_id = QCA9888_2_0_DEVICE_ID, + .bus = ATH10K_BUS_PCI, .name = "qca9888 hw2.0", ++ .led_pin = 17, .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, .uart_pin = 7, -+ .led_pin = 17, .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, - .otp_exe_param = 0x00000700, - .continuous_frag_desc = true, -@@ -550,6 +562,7 @@ static const struct ath10k_hw_params ath - .name = "qca9377 hw1.0", - .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, - .uart_pin = 6, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -591,6 +604,7 @@ static const struct ath10k_hw_params ath - .name = "qca9377 hw1.1", - .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, - .uart_pin = 6, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -634,6 +648,7 @@ static const struct ath10k_hw_params ath - .name = "qca9377 hw1.1 sdio", - .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, - .uart_pin = 19, -+ .led_pin = 0, - .otp_exe_param = 0, - .channel_counters_freq_hz = 88000, - .max_probe_resp_desc_thres = 0, -@@ -668,6 +683,7 @@ static const struct ath10k_hw_params ath - .name = "qca4019 hw1.0", - .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, - .uart_pin = 7, -+ .led_pin = 0, - .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, - .otp_exe_param = 0x0010000, - .continuous_frag_desc = true, -@@ -714,6 +730,7 @@ static const struct ath10k_hw_params ath - .dev_id = 0, - .bus = ATH10K_BUS_SNOC, - .name = "wcn3990 hw1.0", -+ .led_pin = 0, - .continuous_frag_desc = true, - .tx_chain_mask = 0x7, - .rx_chain_mask = 0x7, -@@ -3242,6 +3259,10 @@ int ath10k_core_start(struct ath10k *ar, +@@ -3231,6 +3237,10 @@ int ath10k_core_start(struct ath10k *ar, goto err_hif_stop; } @@ -220,7 +183,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com return 0; err_hif_stop: -@@ -3500,9 +3521,18 @@ static void ath10k_core_register_work(st +@@ -3489,9 +3499,18 @@ static void ath10k_core_register_work(st goto err_spectral_destroy; } @@ -239,7 +202,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com err_spectral_destroy: ath10k_spectral_destroy(ar); err_debug_destroy: -@@ -3548,6 +3578,8 @@ void ath10k_core_unregister(struct ath10 +@@ -3538,6 +3557,8 @@ void ath10k_core_unregister(struct ath10 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) return; @@ -250,7 +213,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com * relayfs debugfs file cleanly. Otherwise the parent debugfs tree --- a/drivers/net/wireless/ath/ath10k/core.h +++ b/drivers/net/wireless/ath/ath10k/core.h -@@ -15,6 +15,7 @@ +@@ -14,6 +14,7 @@ #include #include #include @@ -258,7 +221,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com #include "htt.h" #include "htc.h" -@@ -1257,6 +1258,13 @@ struct ath10k { +@@ -1253,6 +1254,13 @@ struct ath10k { } testmode; struct { @@ -274,7 +237,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com u32 fw_crash_counter; --- a/drivers/net/wireless/ath/ath10k/hw.h +++ b/drivers/net/wireless/ath/ath10k/hw.h -@@ -521,6 +521,7 @@ struct ath10k_hw_params { +@@ -519,6 +519,7 @@ struct ath10k_hw_params { const char *name; u32 patch_load_addr; int uart_pin; @@ -284,13 +247,24 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com /* Type of hw cycle counter wraparound logic, for more info --- /dev/null +++ b/drivers/net/wireless/ath/ath10k/leds.c -@@ -0,0 +1,90 @@ -+// SPDX-License-Identifier: ISC +@@ -0,0 +1,103 @@ +/* + * Copyright (c) 2005-2011 Atheros Communications Inc. + * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. + * Copyright (c) 2018 Sebastian Gottschall -+ * Copyright (c) 2018 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2018, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include @@ -357,6 +331,8 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com + + ar->leds.cdev.name = ar->leds.label; + ar->leds.cdev.brightness_set_blocking = ath10k_leds_set_brightness_blocking; ++ ++ /* FIXME: this assignment doesn't make sense as it's NULL, remove it? */ + ar->leds.cdev.default_trigger = ar->leds.wifi_led.default_trigger; + + ret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev); @@ -377,15 +353,22 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com + --- /dev/null +++ b/drivers/net/wireless/ath/ath10k/leds.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: ISC */ +@@ -0,0 +1,41 @@ +/* -+ * Copyright (c) 2005-2011 Atheros Communications Inc. -+ * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. -+ * Copyright (c) 2018 Sebastian Gottschall -+ * Copyright (c) 2018 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2018, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ -+ +#ifndef _LEDS_H_ +#define _LEDS_H_ + @@ -414,7 +397,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com +#endif /* _LEDS_H_ */ --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -25,6 +25,7 @@ +@@ -24,6 +24,7 @@ #include "wmi-tlv.h" #include "wmi-ops.h" #include "wow.h" @@ -473,7 +456,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com { --- a/drivers/net/wireless/ath/ath10k/wmi-tlv.c +++ b/drivers/net/wireless/ath/ath10k/wmi-tlv.c -@@ -4606,6 +4606,8 @@ static const struct wmi_ops wmi_tlv_ops +@@ -4594,6 +4594,8 @@ static const struct wmi_ops wmi_tlv_ops .gen_echo = ath10k_wmi_tlv_op_gen_echo, .gen_vdev_spectral_conf = ath10k_wmi_tlv_op_gen_vdev_spectral_conf, .gen_vdev_spectral_enable = ath10k_wmi_tlv_op_gen_vdev_spectral_enable, @@ -484,7 +467,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = { --- a/drivers/net/wireless/ath/ath10k/wmi.c +++ b/drivers/net/wireless/ath/ath10k/wmi.c -@@ -7493,6 +7493,49 @@ ath10k_wmi_op_gen_peer_set_param(struct +@@ -7472,6 +7472,49 @@ ath10k_wmi_op_gen_peer_set_param(struct return skb; } @@ -534,7 +517,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com static struct sk_buff * ath10k_wmi_op_gen_set_psmode(struct ath10k *ar, u32 vdev_id, enum wmi_sta_ps_mode psmode) -@@ -9157,6 +9200,9 @@ static const struct wmi_ops wmi_ops = { +@@ -9160,6 +9203,9 @@ static const struct wmi_ops wmi_ops = { .fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill, .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, .gen_echo = ath10k_wmi_op_gen_echo, @@ -544,7 +527,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ -@@ -9227,6 +9273,8 @@ static const struct wmi_ops wmi_10_1_ops +@@ -9230,6 +9276,8 @@ static const struct wmi_ops wmi_10_1_ops .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, .gen_echo = ath10k_wmi_op_gen_echo, @@ -553,7 +536,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ -@@ -9299,6 +9347,8 @@ static const struct wmi_ops wmi_10_2_ops +@@ -9302,6 +9350,8 @@ static const struct wmi_ops wmi_10_2_ops .gen_delba_send = ath10k_wmi_op_gen_delba_send, .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, @@ -562,7 +545,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com /* .gen_pdev_enable_adaptive_cca not implemented */ }; -@@ -9370,6 +9420,8 @@ static const struct wmi_ops wmi_10_2_4_o +@@ -9373,6 +9423,8 @@ static const struct wmi_ops wmi_10_2_4_o ath10k_wmi_op_gen_pdev_enable_adaptive_cca, .get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype, .gen_bb_timing = ath10k_wmi_10_2_4_op_gen_bb_timing, @@ -571,7 +554,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ -@@ -9451,6 +9503,8 @@ static const struct wmi_ops wmi_10_4_ops +@@ -9454,6 +9506,8 @@ static const struct wmi_ops wmi_10_4_ops .gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info, .gen_echo = ath10k_wmi_op_gen_echo, .gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config, @@ -582,11 +565,11 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com int ath10k_wmi_attach(struct ath10k *ar) --- a/drivers/net/wireless/ath/ath10k/wmi.h +++ b/drivers/net/wireless/ath/ath10k/wmi.h -@@ -3034,6 +3034,41 @@ enum wmi_10_4_feature_mask { +@@ -3030,6 +3030,41 @@ enum wmi_10_4_feature_mask { }; -+/* WMI_GPIO_CPTCFG_CMDID */ ++/* WMI_GPIO_CONFIG_CMDID */ +enum { + WMI_GPIO_PULL_NONE, + WMI_GPIO_PULL_UP, @@ -602,7 +585,7 @@ Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com + WMI_GPIO_INTTYPE_LEVEL_HIGH +}; + -+/* WMI_GPIO_CPTCFG_CMDID */ ++/* WMI_GPIO_CONFIG_CMDID */ +struct wmi_gpio_config_cmd { + __le32 gpio_num; /* GPIO number to be setup */ + __le32 input; /* 0 - Output/ 1 - Input */ diff --git a/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch b/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch index 5bd9186d1..4c1f9aa81 100644 --- a/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch +++ b/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch @@ -16,7 +16,7 @@ Signed-off-by: Mathias Kresin --- a/drivers/net/wireless/ath/ath10k/core.h +++ b/drivers/net/wireless/ath/ath10k/core.h -@@ -1313,6 +1313,10 @@ struct ath10k { +@@ -1309,6 +1309,10 @@ struct ath10k { s32 tx_power_2g_limit; s32 tx_power_5g_limit; @@ -29,10 +29,12 @@ Signed-off-by: Mathias Kresin }; --- a/drivers/net/wireless/ath/ath10k/leds.c +++ b/drivers/net/wireless/ath/ath10k/leds.c -@@ -70,7 +70,7 @@ int ath10k_leds_register(struct ath10k * +@@ -81,9 +81,7 @@ int ath10k_leds_register(struct ath10k * ar->leds.cdev.name = ar->leds.label; ar->leds.cdev.brightness_set_blocking = ath10k_leds_set_brightness_blocking; +- +- /* FIXME: this assignment doesn't make sense as it's NULL, remove it? */ - ar->leds.cdev.default_trigger = ar->leds.wifi_led.default_trigger; + ar->leds.cdev.default_trigger = ar->led_default_trigger; @@ -40,7 +42,7 @@ Signed-off-by: Mathias Kresin if (ret) --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -10297,7 +10297,7 @@ int ath10k_mac_register(struct ath10k *a +@@ -10284,7 +10284,7 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; #ifdef CPTCFG_MAC80211_LEDS diff --git a/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch b/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch index f1770cfbe..3626debf1 100644 --- a/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch +++ b/package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch @@ -28,7 +28,7 @@ Forwarded: no --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -1022,6 +1022,40 @@ static inline int ath10k_vdev_setup_sync +@@ -1028,6 +1028,40 @@ static inline int ath10k_vdev_setup_sync return ar->last_wmi_vdev_start_status; } @@ -69,7 +69,7 @@ Forwarded: no static int ath10k_monitor_vdev_start(struct ath10k *ar, int vdev_id) { struct cfg80211_chan_def *chandef = NULL; -@@ -1054,7 +1088,8 @@ static int ath10k_monitor_vdev_start(str +@@ -1060,7 +1094,8 @@ static int ath10k_monitor_vdev_start(str arg.channel.min_power = 0; arg.channel.max_power = channel->max_power * 2; arg.channel.max_reg_power = channel->max_reg_power * 2; @@ -79,7 +79,7 @@ Forwarded: no reinit_completion(&ar->vdev_setup_done); reinit_completion(&ar->vdev_delete_done); -@@ -1500,7 +1535,8 @@ static int ath10k_vdev_start_restart(str +@@ -1506,7 +1541,8 @@ static int ath10k_vdev_start_restart(str arg.channel.min_power = 0; arg.channel.max_power = chandef->chan->max_power * 2; arg.channel.max_reg_power = chandef->chan->max_reg_power * 2; @@ -89,7 +89,7 @@ Forwarded: no if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { arg.ssid = arvif->u.ap.ssid; -@@ -3431,7 +3467,8 @@ static int ath10k_update_channel_list(st +@@ -3437,7 +3473,8 @@ static int ath10k_update_channel_list(st ch->min_power = 0; ch->max_power = channel->max_power * 2; ch->max_reg_power = channel->max_reg_power * 2; diff --git a/package/kernel/mac80211/patches/ath10k/984-ath10k-Try-to-get-mac-address-from-dts.patch b/package/kernel/mac80211/patches/ath10k/984-ath10k-Try-to-get-mac-address-from-dts.patch index 5d70df15a..084e28a2d 100644 --- a/package/kernel/mac80211/patches/ath10k/984-ath10k-Try-to-get-mac-address-from-dts.patch +++ b/package/kernel/mac80211/patches/ath10k/984-ath10k-Try-to-get-mac-address-from-dts.patch @@ -18,7 +18,7 @@ Signed-off-by: Ansuel Smith --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c -@@ -9,6 +9,7 @@ +@@ -8,6 +8,7 @@ #include #include #include @@ -26,7 +26,7 @@ Signed-off-by: Ansuel Smith #include #include #include -@@ -3429,6 +3430,8 @@ static int ath10k_core_probe_fw(struct a +@@ -3407,6 +3408,8 @@ static int ath10k_core_probe_fw(struct a device_get_mac_address(ar->dev, ar->mac_addr); diff --git a/package/kernel/mac80211/patches/ath10k/985-ath10k-allow-vht-on-2g.patch b/package/kernel/mac80211/patches/ath10k/985-ath10k-allow-vht-on-2g.patch new file mode 100644 index 000000000..3fb26bff9 --- /dev/null +++ b/package/kernel/mac80211/patches/ath10k/985-ath10k-allow-vht-on-2g.patch @@ -0,0 +1,10 @@ +--- a/drivers/net/wireless/ath/ath10k/mac.c ++++ b/drivers/net/wireless/ath/ath10k/mac.c +@@ -5034,6 +5034,7 @@ static void ath10k_mac_setup_ht_vht_cap( + if (ar->phy_capability & WHAL_WLAN_11G_CAPABILITY) { + band = &ar->mac.sbands[NL80211_BAND_2GHZ]; + band->ht_cap = ht_cap; ++ band->vht_cap = vht_cap; + } + if (ar->phy_capability & WHAL_WLAN_11A_CAPABILITY) { + band = &ar->mac.sbands[NL80211_BAND_5GHZ]; diff --git a/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch b/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch index b9cdae7e1..f4b1ded15 100644 --- a/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch +++ b/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch @@ -18,7 +18,7 @@ Signed-off-by: David Bauer --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -10089,7 +10089,6 @@ int ath10k_mac_register(struct ath10k *a +@@ -10081,7 +10081,6 @@ int ath10k_mac_register(struct ath10k *a ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); ieee80211_hw_set(ar->hw, QUEUE_CONTROL); ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG); diff --git a/package/kernel/mac80211/patches/ath10k/990-ath10k-small-buffers.patch b/package/kernel/mac80211/patches/ath10k/990-ath10k-small-buffers.patch index 755982a7d..2f560c70a 100644 --- a/package/kernel/mac80211/patches/ath10k/990-ath10k-small-buffers.patch +++ b/package/kernel/mac80211/patches/ath10k/990-ath10k-small-buffers.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath10k/htt.h +++ b/drivers/net/wireless/ath/ath10k/htt.h -@@ -236,7 +236,11 @@ enum htt_rx_ring_flags { +@@ -235,7 +235,11 @@ enum htt_rx_ring_flags { }; #define HTT_RX_RING_SIZE_MIN 128 @@ -14,7 +14,7 @@ #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) --- a/drivers/net/wireless/ath/ath10k/pci.c +++ b/drivers/net/wireless/ath/ath10k/pci.c -@@ -132,7 +132,11 @@ static const struct ce_attr pci_host_ce_ +@@ -131,7 +131,11 @@ static const struct ce_attr pci_host_ce_ .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, @@ -26,7 +26,7 @@ .recv_cb = ath10k_pci_htt_htc_rx_cb, }, -@@ -141,7 +145,11 @@ static const struct ce_attr pci_host_ce_ +@@ -140,7 +144,11 @@ static const struct ce_attr pci_host_ce_ .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, @@ -38,7 +38,7 @@ .recv_cb = ath10k_pci_htc_rx_cb, }, -@@ -168,7 +176,11 @@ static const struct ce_attr pci_host_ce_ +@@ -167,7 +175,11 @@ static const struct ce_attr pci_host_ce_ .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 512, @@ -50,7 +50,7 @@ .recv_cb = ath10k_pci_htt_rx_cb, }, -@@ -193,7 +205,11 @@ static const struct ce_attr pci_host_ce_ +@@ -192,7 +204,11 @@ static const struct ce_attr pci_host_ce_ .flags = CE_ATTR_FLAGS, .src_nentries = 0, .src_sz_max = 2048, diff --git a/package/kernel/mac80211/patches/ath11k/0001-wifi-ath11k-stop-tx-queues-immediately-upon-firmware.patch b/package/kernel/mac80211/patches/ath11k/0001-wifi-ath11k-stop-tx-queues-immediately-upon-firmware.patch new file mode 100644 index 000000000..d0dc04feb --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0001-wifi-ath11k-stop-tx-queues-immediately-upon-firmware.patch @@ -0,0 +1,78 @@ +From 81e60b2dfb2744ab6642c4aa62534b4f711fdc5d Mon Sep 17 00:00:00 2001 +From: Aditya Kumar Singh +Date: Tue, 27 Sep 2022 09:18:54 +0300 +Subject: [PATCH] wifi: ath11k: stop tx queues immediately upon firmware exit + +Currently, recovery flag is set immediately upon firmware +exit but tx queues are stopped once firmware arrives back +and is ready which is during ath11k_core_restart. Once +ieee80211 hw restart is completed, tx queues are resumed. +If during the time delta between firmware exit and firmware +ready, mac80211 send packets, currently ath11k will drop it +since recovery flag will be set. But warning prints will +come - + "ath11k c000000.wifi: failed to transmit frame -108" + +If more tx packets are there, this could lead to flooding +of above print. + +However, actually tx queues should be stopped immediately +when firmware leaves. This will prevent packets to get +dropped when firmware is recovering. + +Add fix to stop tx queues immediately after firmware exit. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220923170235.18873-1-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 5 +---- + drivers/net/wireless/ath/ath11k/core.h | 1 + + drivers/net/wireless/ath/ath11k/qmi.c | 3 +++ + 3 files changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -1641,7 +1641,7 @@ static void ath11k_update_11d(struct wor + } + } + +-static void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) ++void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) + { + struct ath11k *ar; + struct ath11k_pdev *pdev; +@@ -1730,9 +1730,6 @@ static void ath11k_core_restart(struct w + struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); + int ret; + +- if (!ab->is_reset) +- ath11k_core_pre_reconfigure_recovery(ab); +- + ret = ath11k_core_reconfigure_on_crash(ab); + if (ret) { + ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -1158,6 +1158,7 @@ int ath11k_core_check_smbios(struct ath1 + void ath11k_core_halt(struct ath11k *ar); + int ath11k_core_resume(struct ath11k_base *ab); + int ath11k_core_suspend(struct ath11k_base *ab); ++void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab); + + const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, + const char *filename); +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -3164,6 +3164,9 @@ static void ath11k_qmi_driver_event_work + case ATH11K_QMI_EVENT_SERVER_EXIT: + set_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); + set_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); ++ ++ if (!ab->is_reset) ++ ath11k_core_pre_reconfigure_recovery(ab); + break; + case ATH11K_QMI_EVENT_REQUEST_MEM: + ret = ath11k_qmi_event_mem_request(qmi); diff --git a/package/kernel/mac80211/patches/ath11k/0002-wifi-ath11k-Don-t-exit-on-wakeup-failure.patch b/package/kernel/mac80211/patches/ath11k/0002-wifi-ath11k-Don-t-exit-on-wakeup-failure.patch new file mode 100644 index 000000000..47385e045 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0002-wifi-ath11k-Don-t-exit-on-wakeup-failure.patch @@ -0,0 +1,45 @@ +From 45d2e268369b0c768d5a644f319758bcfd370521 Mon Sep 17 00:00:00 2001 +From: Baochen Qiang +Date: Wed, 28 Sep 2022 09:51:40 +0800 +Subject: [PATCH] wifi: ath11k: Don't exit on wakeup failure + +Currently, ath11k_pcic_read() returns an error if wakeup() +fails, this makes firmware crash debug quite hard because we can +get nothing. + +Change to go ahead on wakeup failure, in that case we still may +get something valid to check. There should be no mislead due +to incorrect content because we are aware of the failure with the +log printed. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 + +Signed-off-by: Baochen Qiang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220928015140.5431-1-quic_bqiang@quicinc.com +--- + drivers/net/wireless/ath/ath11k/pcic.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/pcic.c ++++ b/drivers/net/wireless/ath/ath11k/pcic.c +@@ -218,9 +218,16 @@ int ath11k_pcic_read(struct ath11k_base + if (wakeup_required && ab->pci.ops->wakeup) { + ret = ab->pci.ops->wakeup(ab); + if (ret) { +- ath11k_warn(ab, "failed to wakeup for read from 0x%x: %d\n", +- start, ret); +- return ret; ++ ath11k_warn(ab, ++ "wakeup failed, data may be invalid: %d", ++ ret); ++ /* Even though wakeup() failed, continue processing rather ++ * than returning because some parts of the data may still ++ * be valid and useful in some cases, e.g. could give us ++ * some clues on firmware crash. ++ * Mislead due to invalid data could be avoided because we ++ * are aware of the wakeup failure. ++ */ + } + } + diff --git a/package/kernel/mac80211/patches/ath11k/0005-wifi-ath11k-Fix-spelling-mistake-chnange-change.patch b/package/kernel/mac80211/patches/ath11k/0005-wifi-ath11k-Fix-spelling-mistake-chnange-change.patch new file mode 100644 index 000000000..4b52252ef --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0005-wifi-ath11k-Fix-spelling-mistake-chnange-change.patch @@ -0,0 +1,25 @@ +From a797f479bf3e02c6d179c2e6aeace7f9b22b0acd Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Wed, 28 Sep 2022 15:38:34 +0100 +Subject: [PATCH] wifi: ath11k: Fix spelling mistake "chnange" -> "change" + +There is a spelling mistake in an ath11k_dbg debug message. Fix it. + +Signed-off-by: Colin Ian King +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220928143834.35189-1-colin.i.king@gmail.com +--- + drivers/net/wireless/ath/ath11k/wmi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -6829,7 +6829,7 @@ static void ath11k_wmi_event_peer_sta_ps + } + + ath11k_dbg(ab, ATH11K_DBG_WMI, +- "peer sta ps chnange ev addr %pM state %u sup_bitmap %x ps_valid %u ts %u\n", ++ "peer sta ps change ev addr %pM state %u sup_bitmap %x ps_valid %u ts %u\n", + ev->peer_macaddr.addr, ev->peer_ps_state, + ev->ps_supported_bitmap, ev->peer_ps_valid, + ev->peer_ps_timestamp); diff --git a/package/kernel/mac80211/patches/ath11k/0007-wifi-ath11k-suppress-add-interface-error.patch b/package/kernel/mac80211/patches/ath11k/0007-wifi-ath11k-suppress-add-interface-error.patch new file mode 100644 index 000000000..fbef0abb8 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0007-wifi-ath11k-suppress-add-interface-error.patch @@ -0,0 +1,52 @@ +From 638b26652b0438563a76ec90014c8cba34db982b Mon Sep 17 00:00:00 2001 +From: Karthikeyan Periyasamy +Date: Thu, 6 Oct 2022 06:28:42 +0530 +Subject: [PATCH 7/9] wifi: ath11k: suppress add interface error + +In the VIF (other than monitor type) creation request, we should not +throw the error code when the monitor VIF creation fails, since the +actual VIF creation succeeds. If we throw the error code from driver +then the actual VIF creation get fail. So suppress the monitor VIF +creation error by throwing warning message instead of error code. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.6.0.1-00760-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Karthikeyan Periyasamy +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221006005842.8599-1-quic_periyasa@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -6421,18 +6421,16 @@ static int ath11k_mac_op_add_interface(s + + ath11k_dp_vdev_tx_attach(ar, arvif); + ++ ath11k_debugfs_add_interface(arvif); ++ + if (vif->type != NL80211_IFTYPE_MONITOR && + test_bit(ATH11K_FLAG_MONITOR_CONF_ENABLED, &ar->monitor_flags)) { + ret = ath11k_mac_monitor_vdev_create(ar); +- if (ret) { ++ if (ret) + ath11k_warn(ar->ab, "failed to create monitor vdev during add interface: %d", + ret); +- goto err_peer_del; +- } + } + +- ath11k_debugfs_add_interface(arvif); +- + mutex_unlock(&ar->conf_mutex); + + return 0; +@@ -6457,7 +6455,6 @@ err_vdev_del: + spin_unlock_bh(&ar->data_lock); + + err: +- ath11k_debugfs_remove_interface(arvif); + mutex_unlock(&ar->conf_mutex); + + return ret; diff --git a/package/kernel/mac80211/patches/ath11k/0008-wifi-ath11k-add-support-to-configure-channel-dwell-t.patch b/package/kernel/mac80211/patches/ath11k/0008-wifi-ath11k-add-support-to-configure-channel-dwell-t.patch new file mode 100644 index 000000000..d0b19fe59 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0008-wifi-ath11k-add-support-to-configure-channel-dwell-t.patch @@ -0,0 +1,102 @@ +From c362daa213cdeb0a9e7c2ed84849544c24505720 Mon Sep 17 00:00:00 2001 +From: Manikanta Pubbisetty +Date: Fri, 7 Oct 2022 10:41:30 +0530 +Subject: [PATCH 8/9] wifi: ath11k: add support to configure channel dwell time + +Add support to configure channel dwell time during scan. +Dwell time help to stay on the channel for a specified duration +during scan and aid userspace in finding WiFi networks. Very +useful in passive scans where longer dwell times are needed +to find the WiFi networks. + +Configure channel dwell time from duration of the scan request +received from mac80211 when the duration is non-zero. When the +scan request does not have duration value, use the default ones, +the current implementation. + +Advertise corresponding feature flag NL80211_EXT_FEATURE_SET_SCAN_DWELL +to enable the feature. + +Change is applicable for all ath11k hardware. + +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 + +Signed-off-by: Manikanta Pubbisetty +Reviewed-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221007051130.6067-1-quic_mpubbise@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 33 +++++++++++++++++++++++---- + 1 file changed, 29 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -241,7 +241,10 @@ const struct htt_rx_ring_tlv_filter ath1 + #define ath11k_a_rates (ath11k_legacy_rates + 4) + #define ath11k_a_rates_size (ARRAY_SIZE(ath11k_legacy_rates) - 4) + +-#define ATH11K_MAC_SCAN_TIMEOUT_MSECS 200 /* in msecs */ ++#define ATH11K_MAC_SCAN_CMD_EVT_OVERHEAD 200 /* in msecs */ ++ ++/* Overhead due to the processing of channel switch events from FW */ ++#define ATH11K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD 10 /* in msecs */ + + static const u32 ath11k_smps_map[] = { + [WLAN_HT_CAP_SM_PS_STATIC] = WMI_PEER_SMPS_STATIC, +@@ -3612,6 +3615,7 @@ static int ath11k_mac_op_hw_scan(struct + struct scan_req_params arg; + int ret = 0; + int i; ++ u32 scan_timeout; + + mutex_lock(&ar->conf_mutex); + +@@ -3681,6 +3685,26 @@ static int ath11k_mac_op_hw_scan(struct + ether_addr_copy(arg.mac_mask.addr, req->mac_addr_mask); + } + ++ /* if duration is set, default dwell times will be overwritten */ ++ if (req->duration) { ++ arg.dwell_time_active = req->duration; ++ arg.dwell_time_active_2g = req->duration; ++ arg.dwell_time_active_6g = req->duration; ++ arg.dwell_time_passive = req->duration; ++ arg.dwell_time_passive_6g = req->duration; ++ arg.burst_duration = req->duration; ++ ++ scan_timeout = min_t(u32, arg.max_rest_time * ++ (arg.num_chan - 1) + (req->duration + ++ ATH11K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD) * ++ arg.num_chan, arg.max_scan_time); ++ } else { ++ scan_timeout = arg.max_scan_time; ++ } ++ ++ /* Add a margin to account for event/command processing */ ++ scan_timeout += ATH11K_MAC_SCAN_CMD_EVT_OVERHEAD; ++ + ret = ath11k_start_scan(ar, &arg); + if (ret) { + ath11k_warn(ar->ab, "failed to start hw scan: %d\n", ret); +@@ -3689,10 +3713,8 @@ static int ath11k_mac_op_hw_scan(struct + spin_unlock_bh(&ar->data_lock); + } + +- /* Add a 200ms margin to account for event/command processing */ + ieee80211_queue_delayed_work(ar->hw, &ar->scan.timeout, +- msecs_to_jiffies(arg.max_scan_time + +- ATH11K_MAC_SCAN_TIMEOUT_MSECS)); ++ msecs_to_jiffies(scan_timeout)); + + exit: + kfree(arg.chan_list); +@@ -9060,6 +9082,9 @@ static int __ath11k_mac_register(struct + NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); + } + ++ wiphy_ext_feature_set(ar->hw->wiphy, ++ NL80211_EXT_FEATURE_SET_SCAN_DWELL); ++ + ath11k_reg_init(ar); + + if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { diff --git a/package/kernel/mac80211/patches/ath11k/0010-wifi-ath11k-Fix-firmware-crash-on-vdev-delete-race-c.patch b/package/kernel/mac80211/patches/ath11k/0010-wifi-ath11k-Fix-firmware-crash-on-vdev-delete-race-c.patch new file mode 100644 index 000000000..7275af06e --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0010-wifi-ath11k-Fix-firmware-crash-on-vdev-delete-race-c.patch @@ -0,0 +1,116 @@ +From 3811fa1f231f1a3e29759efef4992116604aab8b Mon Sep 17 00:00:00 2001 +From: Sowmiya Sree Elavalagan +Date: Tue, 11 Oct 2022 15:23:46 +0530 +Subject: [PATCH] wifi: ath11k: Fix firmware crash on vdev delete race + condition + +Current code does not wait for vdev delete completion on vdev create +failures and tries to send another vdev create followed by vdev set +param to firmware with same vdev id. This causes firmware crash. +Fix this crash by waiting for vdev delete completion on vdev +create failures. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.6.0.1-00905-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sowmiya Sree Elavalagan +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221011095346.3901-1-quic_ssreeela@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 60 +++++++++++++++++---------- + 1 file changed, 37 insertions(+), 23 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -6233,6 +6233,40 @@ void ath11k_mac_11d_scan_stop_all(struct + } + } + ++static int ath11k_mac_vdev_delete(struct ath11k *ar, struct ath11k_vif *arvif) ++{ ++ unsigned long time_left; ++ struct ieee80211_vif *vif = arvif->vif; ++ int ret = 0; ++ ++ lockdep_assert_held(&ar->conf_mutex); ++ ++ reinit_completion(&ar->vdev_delete_done); ++ ++ ret = ath11k_wmi_vdev_delete(ar, arvif->vdev_id); ++ if (ret) { ++ ath11k_warn(ar->ab, "failed to delete WMI vdev %d: %d\n", ++ arvif->vdev_id, ret); ++ return ret; ++ } ++ ++ time_left = wait_for_completion_timeout(&ar->vdev_delete_done, ++ ATH11K_VDEV_DELETE_TIMEOUT_HZ); ++ if (time_left == 0) { ++ ath11k_warn(ar->ab, "Timeout in receiving vdev delete response\n"); ++ return -ETIMEDOUT; ++ } ++ ++ ar->ab->free_vdev_map |= 1LL << (arvif->vdev_id); ++ ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); ++ ar->num_created_vdevs--; ++ ++ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "vdev %pM deleted, vdev_id %d\n", ++ vif->addr, arvif->vdev_id); ++ ++ return ret; ++} ++ + static int ath11k_mac_op_add_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) + { +@@ -6468,10 +6502,7 @@ err_peer_del: + } + + err_vdev_del: +- ath11k_wmi_vdev_delete(ar, arvif->vdev_id); +- ar->num_created_vdevs--; +- ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); +- ab->free_vdev_map |= 1LL << arvif->vdev_id; ++ ath11k_mac_vdev_delete(ar, arvif); + spin_lock_bh(&ar->data_lock); + list_del(&arvif->list); + spin_unlock_bh(&ar->data_lock); +@@ -6499,7 +6530,6 @@ static void ath11k_mac_op_remove_interfa + struct ath11k *ar = hw->priv; + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); + struct ath11k_base *ab = ar->ab; +- unsigned long time_left; + int ret; + int i; + +@@ -6520,29 +6550,13 @@ static void ath11k_mac_op_remove_interfa + arvif->vdev_id, ret); + } + +- reinit_completion(&ar->vdev_delete_done); +- +- ret = ath11k_wmi_vdev_delete(ar, arvif->vdev_id); ++ ret = ath11k_mac_vdev_delete(ar, arvif); + if (ret) { +- ath11k_warn(ab, "failed to delete WMI vdev %d: %d\n", ++ ath11k_warn(ab, "failed to delete vdev %d: %d\n", + arvif->vdev_id, ret); + goto err_vdev_del; + } + +- time_left = wait_for_completion_timeout(&ar->vdev_delete_done, +- ATH11K_VDEV_DELETE_TIMEOUT_HZ); +- if (time_left == 0) { +- ath11k_warn(ab, "Timeout in receiving vdev delete response\n"); +- goto err_vdev_del; +- } +- +- ab->free_vdev_map |= 1LL << (arvif->vdev_id); +- ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); +- ar->num_created_vdevs--; +- +- ath11k_dbg(ab, ATH11K_DBG_MAC, "vdev %pM deleted, vdev_id %d\n", +- vif->addr, arvif->vdev_id); +- + if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); + ar->monitor_vdev_id = -1; diff --git a/package/kernel/mac80211/patches/ath11k/0011-wifi-ath11k-fix-monitor-vdev-creation-with-firmware-.patch b/package/kernel/mac80211/patches/ath11k/0011-wifi-ath11k-fix-monitor-vdev-creation-with-firmware-.patch new file mode 100644 index 000000000..2f066d0a5 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0011-wifi-ath11k-fix-monitor-vdev-creation-with-firmware-.patch @@ -0,0 +1,40 @@ +From f3ca72b0327101a074a871539e61775d43908ca4 Mon Sep 17 00:00:00 2001 +From: Nagarajan Maran +Date: Fri, 14 Oct 2022 21:20:54 +0530 +Subject: [PATCH] wifi: ath11k: fix monitor vdev creation with firmware + recovery + +During firmware recovery, the monitor interface is not +getting created in the driver and firmware since +the respective flags are not updated properly. + +So after firmware recovery is successful, when monitor +interface is brought down manually, firmware assertion +is observed, since we are trying to bring down the +interface which is not yet created in the firmware. + +Fix this by updating the monitor flags properly per +phy#, during firmware recovery. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Nagarajan Maran +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221014155054.11471-1-quic_nmaran@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -1677,6 +1677,10 @@ void ath11k_core_pre_reconfigure_recover + ath11k_mac_tx_mgmt_pending_free, ar); + idr_destroy(&ar->txmgmt_idr); + wake_up(&ar->txmgmt_empty_waitq); ++ ++ ar->monitor_vdev_id = -1; ++ clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); ++ clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); + } + + wake_up(&ab->wmi_ab.tx_credits_wq); diff --git a/package/kernel/mac80211/patches/ath11k/0012-wifi-ath11k-Fix-qmi_msg_handler-data-structure-initi.patch b/package/kernel/mac80211/patches/ath11k/0012-wifi-ath11k-Fix-qmi_msg_handler-data-structure-initi.patch new file mode 100644 index 000000000..fccfa4385 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0012-wifi-ath11k-Fix-qmi_msg_handler-data-structure-initi.patch @@ -0,0 +1,33 @@ +From ed3725e15a154ebebf44e0c34806c57525483f92 Mon Sep 17 00:00:00 2001 +From: Rahul Bhattacharjee +Date: Fri, 21 Oct 2022 14:31:26 +0530 +Subject: [PATCH] wifi: ath11k: Fix qmi_msg_handler data structure + initialization + +qmi_msg_handler is required to be null terminated by QMI module. +There might be a case where a handler for a msg id is not present in the +handlers array which can lead to infinite loop while searching the handler +and therefore out of bound access in qmi_invoke_handler(). +Hence update the initialization in qmi_msg_handler data structure. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Rahul Bhattacharjee +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221021090126.28626-1-quic_rbhattac@quicinc.com +--- + drivers/net/wireless/ath/ath11k/qmi.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -1702,6 +1702,9 @@ static struct qmi_elem_info qmi_wlfw_fw_ + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + }, ++ ++ /* end of list */ ++ {}, + }; + + static int ath11k_qmi_host_cap_send(struct ath11k_base *ab) diff --git a/package/kernel/mac80211/patches/ath11k/0013-wifi-ath11k-synchronize-ath11k_mac_he_gi_to_nl80211_.patch b/package/kernel/mac80211/patches/ath11k/0013-wifi-ath11k-synchronize-ath11k_mac_he_gi_to_nl80211_.patch new file mode 100644 index 000000000..1e89b4d4f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0013-wifi-ath11k-synchronize-ath11k_mac_he_gi_to_nl80211_.patch @@ -0,0 +1,42 @@ +From dd1c2322694522f674c874f5fa02ac5ae39135dd Mon Sep 17 00:00:00 2001 +From: "Jiri Slaby (SUSE)" +Date: Mon, 31 Oct 2022 12:43:41 +0100 +Subject: [PATCH] wifi: ath11k: synchronize + ath11k_mac_he_gi_to_nl80211_he_gi()'s return type + +ath11k_mac_he_gi_to_nl80211_he_gi() generates a valid warning with gcc-13: + drivers/net/wireless/ath/ath11k/mac.c:321:20: error: conflicting types for 'ath11k_mac_he_gi_to_nl80211_he_gi' due to enum/integer mismatch; have 'enum nl80211_he_gi(u8)' + drivers/net/wireless/ath/ath11k/mac.h:166:5: note: previous declaration of 'ath11k_mac_he_gi_to_nl80211_he_gi' with type 'u32(u8)' + +I.e. the type of the return value ath11k_mac_he_gi_to_nl80211_he_gi() in +the declaration is u32, while the definition spells enum nl80211_he_gi. +Synchronize them to the latter. + +Cc: Martin Liska +Cc: Kalle Valo +Cc: "David S. Miller" +Cc: Eric Dumazet +Cc: Jakub Kicinski +Cc: Paolo Abeni +Cc: ath11k@lists.infradead.org +Cc: linux-wireless@vger.kernel.org +Cc: netdev@vger.kernel.org +Signed-off-by: Jiri Slaby (SUSE) +Reviewed-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221031114341.10377-1-jirislaby@kernel.org +--- + drivers/net/wireless/ath/ath11k/mac.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.h ++++ b/drivers/net/wireless/ath/ath11k/mac.h +@@ -163,7 +163,7 @@ void ath11k_mac_drain_tx(struct ath11k * + void ath11k_mac_peer_cleanup_all(struct ath11k *ar); + int ath11k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx); + u8 ath11k_mac_bw_to_mac80211_bw(u8 bw); +-u32 ath11k_mac_he_gi_to_nl80211_he_gi(u8 sgi); ++enum nl80211_he_gi ath11k_mac_he_gi_to_nl80211_he_gi(u8 sgi); + enum nl80211_he_ru_alloc ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(u16 ru_phy); + enum nl80211_he_ru_alloc ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones); + enum ath11k_supported_bw ath11k_mac_mac80211_bw_to_ath11k_bw(enum rate_info_bw bw); diff --git a/package/kernel/mac80211/patches/ath11k/0016-wifi-ath11k-Make-QMI-message-rules-const.patch b/package/kernel/mac80211/patches/ath11k/0016-wifi-ath11k-Make-QMI-message-rules-const.patch new file mode 100644 index 000000000..1f48df73f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0016-wifi-ath11k-Make-QMI-message-rules-const.patch @@ -0,0 +1,341 @@ +From 93c1592889fca46d09d833455628bab05516cdbf Mon Sep 17 00:00:00 2001 +From: Jeff Johnson +Date: Wed, 14 Sep 2022 17:23:03 -0700 +Subject: [PATCH] wifi: ath11k: Make QMI message rules const + +Commit ff6d365898d4 ("soc: qcom: qmi: use const for struct +qmi_elem_info") allows QMI message encoding/decoding rules to be +const, so do that for ath11k. + +Compile tested only. + +Signed-off-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20220915002303.12206-1-quic_jjohnson@quicinc.com +--- + drivers/net/wireless/ath/ath11k/qmi.c | 72 +++++++++++++-------------- + 1 file changed, 36 insertions(+), 36 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -29,7 +29,7 @@ module_param_named(cold_boot_cal, ath11k + MODULE_PARM_DESC(cold_boot_cal, + "Decrease the channel switch time but increase the driver load time (Default: true)"); + +-static struct qmi_elem_info qmi_wlanfw_host_cap_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_host_cap_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, +@@ -280,7 +280,7 @@ static struct qmi_elem_info qmi_wlanfw_h + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_host_cap_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_host_cap_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -297,7 +297,7 @@ static struct qmi_elem_info qmi_wlanfw_h + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_ind_register_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_ind_register_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, +@@ -522,7 +522,7 @@ static struct qmi_elem_info qmi_wlanfw_i + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_ind_register_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_ind_register_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -558,7 +558,7 @@ static struct qmi_elem_info qmi_wlanfw_i + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_mem_cfg_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_mem_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, +@@ -590,7 +590,7 @@ static struct qmi_elem_info qmi_wlanfw_m + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_mem_seg_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_mem_seg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -632,7 +632,7 @@ static struct qmi_elem_info qmi_wlanfw_m + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_request_mem_ind_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_request_mem_ind_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, +@@ -659,7 +659,7 @@ static struct qmi_elem_info qmi_wlanfw_r + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_mem_seg_resp_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_mem_seg_resp_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, +@@ -699,7 +699,7 @@ static struct qmi_elem_info qmi_wlanfw_m + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_respond_mem_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_respond_mem_req_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, +@@ -726,7 +726,7 @@ static struct qmi_elem_info qmi_wlanfw_r + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_respond_mem_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_respond_mem_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -744,7 +744,7 @@ static struct qmi_elem_info qmi_wlanfw_r + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_cap_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_cap_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, +@@ -752,7 +752,7 @@ static struct qmi_elem_info qmi_wlanfw_c + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_device_info_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_device_info_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, +@@ -760,7 +760,7 @@ static struct qmi_elem_info qmi_wlanfw_d + }, + }; + +-static struct qmi_elem_info qmi_wlfw_device_info_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlfw_device_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -814,7 +814,7 @@ static struct qmi_elem_info qmi_wlfw_dev + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_rf_chip_info_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_rf_chip_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -840,7 +840,7 @@ static struct qmi_elem_info qmi_wlanfw_r + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_rf_board_info_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_rf_board_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -857,7 +857,7 @@ static struct qmi_elem_info qmi_wlanfw_r + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_soc_info_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_soc_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -873,7 +873,7 @@ static struct qmi_elem_info qmi_wlanfw_s + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_fw_version_info_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_fw_version_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -899,7 +899,7 @@ static struct qmi_elem_info qmi_wlanfw_f + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_cap_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_cap_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -1100,7 +1100,7 @@ static struct qmi_elem_info qmi_wlanfw_c + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_bdf_download_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_bdf_download_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, +@@ -1235,7 +1235,7 @@ static struct qmi_elem_info qmi_wlanfw_b + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_bdf_download_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_bdf_download_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -1253,7 +1253,7 @@ static struct qmi_elem_info qmi_wlanfw_b + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_m3_info_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_m3_info_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, +@@ -1277,7 +1277,7 @@ static struct qmi_elem_info qmi_wlanfw_m + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_m3_info_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_m3_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -1294,7 +1294,7 @@ static struct qmi_elem_info qmi_wlanfw_m + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_ce_tgt_pipe_cfg_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_ce_tgt_pipe_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -1347,7 +1347,7 @@ static struct qmi_elem_info qmi_wlanfw_c + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_ce_svc_pipe_cfg_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_ce_svc_pipe_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -1382,7 +1382,7 @@ static struct qmi_elem_info qmi_wlanfw_c + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_shadow_reg_cfg_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_shadow_reg_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, +@@ -1406,7 +1406,7 @@ static struct qmi_elem_info qmi_wlanfw_s + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_shadow_reg_v2_cfg_s_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_shadow_reg_v2_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -1423,7 +1423,7 @@ static struct qmi_elem_info qmi_wlanfw_s + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_wlan_mode_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_wlan_mode_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, +@@ -1458,7 +1458,7 @@ static struct qmi_elem_info qmi_wlanfw_w + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_wlan_mode_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_wlan_mode_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -1476,7 +1476,7 @@ static struct qmi_elem_info qmi_wlanfw_w + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_wlan_cfg_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_wlan_cfg_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, +@@ -1615,7 +1615,7 @@ static struct qmi_elem_info qmi_wlanfw_w + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_wlan_cfg_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_wlan_cfg_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -1632,28 +1632,28 @@ static struct qmi_elem_info qmi_wlanfw_w + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_mem_ready_ind_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_mem_ready_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_fw_ready_ind_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_fw_ready_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_cold_boot_cal_done_ind_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_cold_boot_cal_done_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_wlan_ini_req_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_wlan_ini_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, +@@ -1679,7 +1679,7 @@ static struct qmi_elem_info qmi_wlanfw_w + }, + }; + +-static struct qmi_elem_info qmi_wlanfw_wlan_ini_resp_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlanfw_wlan_ini_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, +@@ -1697,7 +1697,7 @@ static struct qmi_elem_info qmi_wlanfw_w + }, + }; + +-static struct qmi_elem_info qmi_wlfw_fw_init_done_ind_msg_v01_ei[] = { ++static const struct qmi_elem_info qmi_wlfw_fw_init_done_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, diff --git a/package/kernel/mac80211/patches/ath11k/0017-wifi-ath11k-Trigger-sta-disconnect-on-hardware-resta.patch b/package/kernel/mac80211/patches/ath11k/0017-wifi-ath11k-Trigger-sta-disconnect-on-hardware-resta.patch new file mode 100644 index 000000000..f95e5027b --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0017-wifi-ath11k-Trigger-sta-disconnect-on-hardware-resta.patch @@ -0,0 +1,119 @@ +From a018750a2cceaf4427c4ee3d9ce3e83a171d5bd6 Mon Sep 17 00:00:00 2001 +From: Youghandhar Chintala +Date: Fri, 4 Nov 2022 14:24:03 +0530 +Subject: [PATCH] wifi: ath11k: Trigger sta disconnect on hardware restart + +Currently after the hardware restart triggered from the driver, the +station interface connection remains intact, since a disconnect trigger +is not sent to userspace. This can lead to a problem in targets where +the wifi mac sequence is added by the firmware. + +After the target restart, its wifi mac sequence number gets reset to +zero. Hence AP to which our device is connected will receive frames with +a wifi mac sequence number jump to the past, thereby resulting in the +AP dropping all these frames, until the frame arrives with a wifi mac +sequence number which AP was expecting. + +To avoid such frame drops, its better to trigger a station disconnect +upon target hardware restart which can be done with API +ieee80211_reconfig_disconnect exposed to mac80211. + +The other targets are not affected by this change, since the hardware +params flag is not set. + +Reported-by: kernel test robot + +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 + +Signed-off-by: Youghandhar Chintala +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221104085403.11025-1-quic_youghand@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 6 ++++++ + drivers/net/wireless/ath/ath11k/hw.h | 1 + + drivers/net/wireless/ath/ath11k/mac.c | 7 +++++++ + 3 files changed, 14 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -195,6 +195,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, ++ .support_fw_mac_sequence = false, + }, + { + .name = "qca6390 hw2.0", +@@ -277,6 +278,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, ++ .support_fw_mac_sequence = true, + }, + { + .name = "qcn9074 hw1.0", +@@ -356,6 +358,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, ++ .support_fw_mac_sequence = false, + }, + { + .name = "wcn6855 hw2.0", +@@ -438,6 +441,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, ++ .support_fw_mac_sequence = true, + }, + { + .name = "wcn6855 hw2.1", +@@ -519,6 +523,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, ++ .support_fw_mac_sequence = true, + }, + { + .name = "wcn6750 hw1.0", +@@ -597,6 +602,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = false, + .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, + .smp2p_wow_exit = true, ++ .support_fw_mac_sequence = true, + }, + }; + +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -219,6 +219,7 @@ struct ath11k_hw_params { + bool tcl_ring_retry; + u32 tx_ring_size; + bool smp2p_wow_exit; ++ bool support_fw_mac_sequence; + }; + + struct ath11k_hw_ops { +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -8010,6 +8010,7 @@ ath11k_mac_op_reconfig_complete(struct i + struct ath11k *ar = hw->priv; + struct ath11k_base *ab = ar->ab; + int recovery_count; ++ struct ath11k_vif *arvif; + + if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART) + return; +@@ -8045,6 +8046,12 @@ ath11k_mac_op_reconfig_complete(struct i + ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset success\n"); + } + } ++ if (ar->ab->hw_params.support_fw_mac_sequence) { ++ list_for_each_entry(arvif, &ar->arvifs, list) { ++ if (arvif->is_up && arvif->vdev_type == WMI_VDEV_TYPE_STA) ++ ieee80211_hw_restart_disconnect(arvif->vif); ++ } ++ } + } + + mutex_unlock(&ar->conf_mutex); diff --git a/package/kernel/mac80211/patches/ath11k/0018-wifi-ath11k-Fix-race-condition-with-struct-htt_ppdu_.patch b/package/kernel/mac80211/patches/ath11k/0018-wifi-ath11k-Fix-race-condition-with-struct-htt_ppdu_.patch new file mode 100644 index 000000000..cef61ee34 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0018-wifi-ath11k-Fix-race-condition-with-struct-htt_ppdu_.patch @@ -0,0 +1,103 @@ +From e44de90453bb2b46a523df78c39eb896bab35dcd Mon Sep 17 00:00:00 2001 +From: Govindaraj Saminathan +Date: Tue, 29 Nov 2022 13:04:02 +0200 +Subject: [PATCH] wifi: ath11k: Fix race condition with struct + htt_ppdu_stats_info + +A crash happens when running the traffic with multiple clients: + +Crash Signature : Unable to handle kernel paging request at +virtual address ffffffd700970918 During the crash, PC points to +"ieee80211_tx_rate_update+0x30/0x68 [mac80211]" +LR points to "ath11k_dp_htt_htc_t2h_msg_handler+0x5a8/0x8a0 [ath11k]". + +Struct ppdu_stats_info is allocated and accessed from event callback via copy +engine tasklet, this has a problem when freeing it from ath11k_mac_op_stop(). + +Use data_lock during entire ath11k_dp_htt_get_ppdu_desc() call to protect +struct htt_ppdu_stats_info access and to avoid race condition when accessing it +from ath11k_mac_op_stop(). + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Govindaraj Saminathan +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221124071104.22506-1-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -1535,13 +1535,12 @@ struct htt_ppdu_stats_info *ath11k_dp_ht + { + struct htt_ppdu_stats_info *ppdu_info; + +- spin_lock_bh(&ar->data_lock); ++ lockdep_assert_held(&ar->data_lock); ++ + if (!list_empty(&ar->ppdu_stats_info)) { + list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { +- if (ppdu_info->ppdu_id == ppdu_id) { +- spin_unlock_bh(&ar->data_lock); ++ if (ppdu_info->ppdu_id == ppdu_id) + return ppdu_info; +- } + } + + if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { +@@ -1553,16 +1552,13 @@ struct htt_ppdu_stats_info *ath11k_dp_ht + kfree(ppdu_info); + } + } +- spin_unlock_bh(&ar->data_lock); + + ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); + if (!ppdu_info) + return NULL; + +- spin_lock_bh(&ar->data_lock); + list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); + ar->ppdu_stat_list_depth++; +- spin_unlock_bh(&ar->data_lock); + + return ppdu_info; + } +@@ -1586,16 +1582,17 @@ static int ath11k_htt_pull_ppdu_stats(st + ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); + if (!ar) { + ret = -EINVAL; +- goto exit; ++ goto out; + } + + if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) + trace_ath11k_htt_ppdu_stats(ar, skb->data, len); + ++ spin_lock_bh(&ar->data_lock); + ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); + if (!ppdu_info) { + ret = -EINVAL; +- goto exit; ++ goto out_unlock_data; + } + + ppdu_info->ppdu_id = ppdu_id; +@@ -1604,10 +1601,13 @@ static int ath11k_htt_pull_ppdu_stats(st + (void *)ppdu_info); + if (ret) { + ath11k_warn(ab, "Failed to parse tlv %d\n", ret); +- goto exit; ++ goto out_unlock_data; + } + +-exit: ++out_unlock_data: ++ spin_unlock_bh(&ar->data_lock); ++ ++out: + rcu_read_unlock(); + + return ret; diff --git a/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-update-hw-params-for-IPQ5018.patch b/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-update-hw-params-for-IPQ5018.patch new file mode 100644 index 000000000..25d39ddb0 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0019-wifi-ath11k-update-hw-params-for-IPQ5018.patch @@ -0,0 +1,125 @@ +From 8dfe875aa24aec68baf6702018633c84c2c1feca Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:13 +0200 +Subject: [PATCH] wifi: ath11k: update hw params for IPQ5018 + +Add new compatible string for IPQ5018 and add +required hw params for IPQ5018. The hw descriptors size and +datapath ops are similar to QCN9074, hence reuse the same. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-3-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 71 ++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath11k/core.h | 8 +++ + 2 files changed, 79 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -604,6 +604,77 @@ static const struct ath11k_hw_params ath + .smp2p_wow_exit = true, + .support_fw_mac_sequence = true, + }, ++ { ++ .hw_rev = ATH11K_HW_IPQ5018_HW10, ++ .name = "ipq5018 hw1.0", ++ .fw = { ++ .dir = "IPQ5018/hw1.0", ++ .board_size = 256 * 1024, ++ .cal_offset = 128 * 1024, ++ }, ++ .max_radios = MAX_RADIOS_5018, ++ .bdf_addr = 0x4BA00000, ++ /* hal_desc_sz and hw ops are similar to qcn9074 */ ++ .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), ++ .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, ++ .ring_mask = &ath11k_hw_ring_mask_ipq8074, ++ .credit_flow = false, ++ .max_tx_ring = 1, ++ .spectral = { ++ .fft_sz = 2, ++ .fft_pad_sz = 0, ++ .summary_pad_sz = 16, ++ .fft_hdr_len = 24, ++ .max_fft_bins = 1024, ++ }, ++ .internal_sleep_clock = false, ++ .host_ce_config = ath11k_host_ce_config_qcn9074, ++ .ce_count = CE_CNT_5018, ++ .rxdma1_enable = true, ++ .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, ++ .rx_mac_buf_ring = false, ++ .vdev_start_delay = false, ++ .htt_peer_map_v2 = true, ++ .interface_modes = BIT(NL80211_IFTYPE_STATION) | ++ BIT(NL80211_IFTYPE_AP) | ++ BIT(NL80211_IFTYPE_MESH_POINT), ++ .supports_monitor = false, ++ .supports_sta_ps = false, ++ .supports_shadow_regs = false, ++ .fw_mem_mode = 0, ++ .num_vdevs = 16 + 1, ++ .num_peers = 512, ++ .supports_regdb = false, ++ .idle_ps = false, ++ .supports_suspend = false, ++ .hal_params = &ath11k_hw_hal_params_ipq8074, ++ .single_pdev_only = false, ++ .cold_boot_calib = true, ++ .fix_l1ss = true, ++ .supports_dynamic_smps_6ghz = false, ++ .alloc_cacheable_memory = true, ++ .supports_rssi_stats = false, ++ .fw_wmi_diag_event = false, ++ .current_cc_support = false, ++ .dbr_debug_support = true, ++ .global_reset = false, ++ .bios_sar_capa = NULL, ++ .m3_fw_support = false, ++ .fixed_bdf_addr = true, ++ .fixed_mem_region = true, ++ .static_window_map = false, ++ .hybrid_bus_type = false, ++ .fixed_fw_mem = false, ++ .support_off_channel_tx = false, ++ .supports_multi_bssid = false, ++ ++ .sram_dump = {}, ++ ++ .tcl_ring_retry = true, ++ .tx_ring_size = DP_TCL_DATA_RING_SIZE, ++ .smp2p_wow_exit = false, ++ .support_fw_mac_sequence = false, ++ }, + }; + + static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -142,6 +142,7 @@ enum ath11k_hw_rev { + ATH11K_HW_WCN6855_HW20, + ATH11K_HW_WCN6855_HW21, + ATH11K_HW_WCN6750_HW10, ++ ATH11K_HW_IPQ5018_HW10, + }; + + enum ath11k_firmware_mode { +@@ -230,6 +231,13 @@ struct ath11k_he { + + #define MAX_RADIOS 3 + ++/* ipq5018 hw param macros */ ++#define MAX_RADIOS_5018 1 ++#define CE_CNT_5018 6 ++#define TARGET_CE_CNT_5018 9 ++#define SVC_CE_MAP_LEN_5018 17 ++#define RXDMA_PER_PDEV_5018 1 ++ + enum { + WMI_HOST_TP_SCALE_MAX = 0, + WMI_HOST_TP_SCALE_50 = 1, diff --git a/package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-update-ce-configurations-for-IPQ5018.patch b/package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-update-ce-configurations-for-IPQ5018.patch new file mode 100644 index 000000000..95643a95f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0020-wifi-ath11k-update-ce-configurations-for-IPQ5018.patch @@ -0,0 +1,246 @@ +From 26af7aabd2d8225c6b2056234626ba5099610871 Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:14 +0200 +Subject: [PATCH] wifi: ath11k: update ce configurations for IPQ5018 + +IPQ5018 is a single pdev device. Update host +and target CE configurations accordingly. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-4-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 4 + + drivers/net/wireless/ath/ath11k/core.h | 3 + + drivers/net/wireless/ath/ath11k/hw.c | 191 +++++++++++++++++++++++++ + 3 files changed, 198 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -630,6 +630,10 @@ static const struct ath11k_hw_params ath + .internal_sleep_clock = false, + .host_ce_config = ath11k_host_ce_config_qcn9074, + .ce_count = CE_CNT_5018, ++ .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, ++ .target_ce_count = TARGET_CE_CNT_5018, ++ .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, ++ .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, + .rxdma1_enable = true, + .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, + .rx_mac_buf_ring = false, +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -1145,6 +1145,9 @@ extern const struct service_to_pipe ath1 + extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[]; + extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[]; + ++extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[]; ++extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[]; ++ + extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[]; + extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[]; + int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab); +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -1972,6 +1972,197 @@ const struct ath11k_hw_ring_mask ath11k_ + }, + }; + ++/* Target firmware's Copy Engine configuration for IPQ5018 */ ++const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[] = { ++ /* CE0: host->target HTC control and raw streams */ ++ { ++ .pipenum = __cpu_to_le32(0), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(2048), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE1: target->host HTT + HTC control */ ++ { ++ .pipenum = __cpu_to_le32(1), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(2048), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE2: target->host WMI */ ++ { ++ .pipenum = __cpu_to_le32(2), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(2048), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE3: host->target WMI */ ++ { ++ .pipenum = __cpu_to_le32(3), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(2048), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE4: host->target HTT */ ++ { ++ .pipenum = __cpu_to_le32(4), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), ++ .nentries = __cpu_to_le32(256), ++ .nbytes_max = __cpu_to_le32(256), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE5: target->host Pktlog */ ++ { ++ .pipenum = __cpu_to_le32(5), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(2048), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE6: Reserved for target autonomous hif_memcpy */ ++ { ++ .pipenum = __cpu_to_le32(6), ++ .pipedir = __cpu_to_le32(PIPEDIR_INOUT), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(16384), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE7 used only by Host */ ++ { ++ .pipenum = __cpu_to_le32(7), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(2048), ++ .flags = __cpu_to_le32(0x2000), ++ .reserved = __cpu_to_le32(0), ++ }, ++ ++ /* CE8 target->host used only by IPA */ ++ { ++ .pipenum = __cpu_to_le32(8), ++ .pipedir = __cpu_to_le32(PIPEDIR_INOUT), ++ .nentries = __cpu_to_le32(32), ++ .nbytes_max = __cpu_to_le32(16384), ++ .flags = __cpu_to_le32(CE_ATTR_FLAGS), ++ .reserved = __cpu_to_le32(0), ++ }, ++}; ++ ++/* Map from service/endpoint to Copy Engine for IPQ5018. ++ * This table is derived from the CE TABLE, above. ++ * It is passed to the Target at startup for use by firmware. ++ */ ++const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[] = { ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(3), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(2), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(3), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(2), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(3), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(2), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(3), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(2), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(3), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(2), ++ }, ++ ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(0), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(1), ++ }, ++ ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(0), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(1), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), ++ .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ ++ .pipenum = __cpu_to_le32(4), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(1), ++ }, ++ { ++ .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), ++ .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ ++ .pipenum = __cpu_to_le32(5), ++ }, ++ ++ /* (Additions here) */ ++ ++ { /* terminator entry */ } ++}; ++ + const struct ath11k_hw_regs ipq8074_regs = { + /* SW2TCL(x) R0 ring configuration address */ + .hal_tcl1_ring_base_lsb = 0x00000510, diff --git a/package/kernel/mac80211/patches/ath11k/0021-wifi-ath11k-remap-ce-register-space-for-IPQ5018.patch b/package/kernel/mac80211/patches/ath11k/0021-wifi-ath11k-remap-ce-register-space-for-IPQ5018.patch new file mode 100644 index 000000000..d07a258ac --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0021-wifi-ath11k-remap-ce-register-space-for-IPQ5018.patch @@ -0,0 +1,351 @@ +From b42b3678c91f3ca6e0888bf5a15c1e8678fd5f2d Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:14 +0200 +Subject: [PATCH] wifi: ath11k: remap ce register space for IPQ5018 + +In IPQ5018 ce register space is moved out of wcss unlike +ipq8074 or ipq6018 and the space is not contiguous, +hence remap the CE registers to a new space to access them. + +Register read/write is modified to check if the register to be written +falls in the CE register space and corresponding register is written. +Also adjust the interrupt register address to ce irq enable/disable. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-5-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 44 ++++++++++++++++++++++---- + drivers/net/wireless/ath/ath11k/ce.h | 16 ++++++++++ + drivers/net/wireless/ath/ath11k/core.c | 8 +++++ + drivers/net/wireless/ath/ath11k/core.h | 1 + + drivers/net/wireless/ath/ath11k/hal.c | 17 ++++++---- + drivers/net/wireless/ath/ath11k/hal.h | 5 +++ + drivers/net/wireless/ath/ath11k/hw.c | 17 ++++++++++ + drivers/net/wireless/ath/ath11k/hw.h | 9 ++++++ + drivers/net/wireless/ath/ath11k/pci.c | 2 ++ + 9 files changed, 107 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -267,30 +267,42 @@ static void ath11k_ahb_clearbit32(struct + static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) + { + const struct ce_attr *ce_attr; ++ const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr; ++ u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr; ++ ++ ie1_reg_addr = ce_ie_addr->ie1_reg_addr + ATH11K_CE_OFFSET(ab); ++ ie2_reg_addr = ce_ie_addr->ie2_reg_addr + ATH11K_CE_OFFSET(ab); ++ ie3_reg_addr = ce_ie_addr->ie3_reg_addr + ATH11K_CE_OFFSET(ab); + + ce_attr = &ab->hw_params.host_ce_config[ce_id]; + if (ce_attr->src_nentries) +- ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_ADDRESS); ++ ath11k_ahb_setbit32(ab, ce_id, ie1_reg_addr); + + if (ce_attr->dest_nentries) { +- ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); ++ ath11k_ahb_setbit32(ab, ce_id, ie2_reg_addr); + ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, +- CE_HOST_IE_3_ADDRESS); ++ ie3_reg_addr); + } + } + + static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) + { + const struct ce_attr *ce_attr; ++ const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr; ++ u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr; ++ ++ ie1_reg_addr = ce_ie_addr->ie1_reg_addr + ATH11K_CE_OFFSET(ab); ++ ie2_reg_addr = ce_ie_addr->ie2_reg_addr + ATH11K_CE_OFFSET(ab); ++ ie3_reg_addr = ce_ie_addr->ie3_reg_addr + ATH11K_CE_OFFSET(ab); + + ce_attr = &ab->hw_params.host_ce_config[ce_id]; + if (ce_attr->src_nentries) +- ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_ADDRESS); ++ ath11k_ahb_clearbit32(ab, ce_id, ie1_reg_addr); + + if (ce_attr->dest_nentries) { +- ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); ++ ath11k_ahb_clearbit32(ab, ce_id, ie2_reg_addr); + ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, +- CE_HOST_IE_3_ADDRESS); ++ ie3_reg_addr); + } + } + +@@ -1142,10 +1154,26 @@ static int ath11k_ahb_probe(struct platf + goto err_core_free; + } + ++ ab->mem_ce = ab->mem; ++ + ret = ath11k_core_pre_init(ab); + if (ret) + goto err_core_free; + ++ if (ab->hw_params.ce_remap) { ++ const struct ce_remap *ce_remap = ab->hw_params.ce_remap; ++ /* ce register space is moved out of wcss unlike ipq8074 or ipq6018 ++ * and the space is not contiguous, hence remapping the CE registers ++ * to a new space for accessing them. ++ */ ++ ab->mem_ce = ioremap(ce_remap->base, ce_remap->size); ++ if (IS_ERR(ab->mem_ce)) { ++ dev_err(&pdev->dev, "ce ioremap error\n"); ++ ret = -ENOMEM; ++ goto err_core_free; ++ } ++ } ++ + ret = ath11k_ahb_setup_resources(ab); + if (ret) + goto err_core_free; +@@ -1236,6 +1264,10 @@ static void ath11k_ahb_free_resources(st + ath11k_ahb_release_smp2p_handle(ab); + ath11k_ahb_fw_resource_deinit(ab); + ath11k_ce_free_pipes(ab); ++ ++ if (ab->hw_params.ce_remap) ++ iounmap(ab->mem_ce); ++ + ath11k_core_free(ab); + platform_set_drvdata(pdev, NULL); + } +--- a/drivers/net/wireless/ath/ath11k/ce.h ++++ b/drivers/net/wireless/ath/ath11k/ce.h +@@ -49,6 +49,11 @@ void ath11k_ce_byte_swap(void *mem, u32 + #define CE_HOST_IE_2_ADDRESS 0x00A18040 + #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS + ++/* CE IE registers are different for IPQ5018 */ ++#define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C ++#define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050 ++#define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS ++ + #define CE_HOST_IE_3_SHIFT 0xC + + #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) +@@ -84,6 +89,17 @@ struct ce_pipe_config { + __le32 reserved; + }; + ++struct ce_ie_addr { ++ u32 ie1_reg_addr; ++ u32 ie2_reg_addr; ++ u32 ie3_reg_addr; ++}; ++ ++struct ce_remap { ++ u32 base; ++ u32 size; ++}; ++ + struct ce_attr { + /* CE_ATTR_* values */ + unsigned int flags; +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -54,6 +54,7 @@ static const struct ath11k_hw_params ath + .target_ce_count = 11, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, + .svc_to_ce_map_len = 21, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, + .single_pdev_only = false, + .rxdma1_enable = true, + .num_rxmda_per_pdev = 1, +@@ -137,6 +138,7 @@ static const struct ath11k_hw_params ath + .target_ce_count = 11, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, + .svc_to_ce_map_len = 19, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, + .single_pdev_only = false, + .rxdma1_enable = true, + .num_rxmda_per_pdev = 1, +@@ -218,6 +220,7 @@ static const struct ath11k_hw_params ath + .target_ce_count = 9, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, + .svc_to_ce_map_len = 14, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, + .single_pdev_only = true, + .rxdma1_enable = false, + .num_rxmda_per_pdev = 2, +@@ -301,6 +304,7 @@ static const struct ath11k_hw_params ath + .target_ce_count = 9, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, + .svc_to_ce_map_len = 18, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, + .rxdma1_enable = true, + .num_rxmda_per_pdev = 1, + .rx_mac_buf_ring = false, +@@ -381,6 +385,7 @@ static const struct ath11k_hw_params ath + .target_ce_count = 9, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, + .svc_to_ce_map_len = 14, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, + .single_pdev_only = true, + .rxdma1_enable = false, + .num_rxmda_per_pdev = 2, +@@ -546,6 +551,7 @@ static const struct ath11k_hw_params ath + .target_ce_count = 9, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, + .svc_to_ce_map_len = 14, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, + .single_pdev_only = true, + .rxdma1_enable = false, + .num_rxmda_per_pdev = 1, +@@ -634,6 +640,8 @@ static const struct ath11k_hw_params ath + .target_ce_count = TARGET_CE_CNT_5018, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, + .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, ++ .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, ++ .ce_remap = &ath11k_ce_remap_ipq5018, + .rxdma1_enable = true, + .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, + .rx_mac_buf_ring = false, +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -851,6 +851,7 @@ struct ath11k_base { + struct ath11k_dp dp; + + void __iomem *mem; ++ void __iomem *mem_ce; + unsigned long mem_len; + + struct { +--- a/drivers/net/wireless/ath/ath11k/hal.c ++++ b/drivers/net/wireless/ath/ath11k/hal.c +@@ -1220,16 +1220,20 @@ static int ath11k_hal_srng_create_config + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; + + s = &hal->srng_config[HAL_CE_SRC]; +- s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB; +- s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP; ++ s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB + ++ ATH11K_CE_OFFSET(ab); ++ s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP + ++ ATH11K_CE_OFFSET(ab); + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); + + s = &hal->srng_config[HAL_CE_DST]; +- s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB; +- s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP; ++ s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB + ++ ATH11K_CE_OFFSET(ab); ++ s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP + ++ ATH11K_CE_OFFSET(ab); + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - +@@ -1237,8 +1241,9 @@ static int ath11k_hal_srng_create_config + + s = &hal->srng_config[HAL_CE_DST_STATUS]; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + +- HAL_CE_DST_STATUS_RING_BASE_LSB; +- s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP; ++ HAL_CE_DST_STATUS_RING_BASE_LSB + ATH11K_CE_OFFSET(ab); ++ s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP + ++ ATH11K_CE_OFFSET(ab); + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - +--- a/drivers/net/wireless/ath/ath11k/hal.h ++++ b/drivers/net/wireless/ath/ath11k/hal.h +@@ -321,6 +321,10 @@ struct ath11k_base; + #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff + #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff + ++/* IPQ5018 ce registers */ ++#define HAL_IPQ5018_CE_WFSS_REG_BASE 0x08400000 ++#define HAL_IPQ5018_CE_SIZE 0x200000 ++ + /* Add any other errors here and return them in + * ath11k_hal_rx_desc_get_err(). + */ +@@ -519,6 +523,7 @@ enum hal_srng_dir { + #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 + #define HAL_SRNG_FLAGS_CACHED 0x20000000 + #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 ++#define HAL_SRNG_FLAGS_REMAP_CE_RING 0x10000000 + + #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) + #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -2163,6 +2163,23 @@ const struct service_to_pipe ath11k_targ + { /* terminator entry */ } + }; + ++const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074 = { ++ .ie1_reg_addr = CE_HOST_IE_ADDRESS, ++ .ie2_reg_addr = CE_HOST_IE_2_ADDRESS, ++ .ie3_reg_addr = CE_HOST_IE_3_ADDRESS, ++}; ++ ++const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018 = { ++ .ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, ++ .ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, ++ .ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, ++}; ++ ++const struct ce_remap ath11k_ce_remap_ipq5018 = { ++ .base = HAL_IPQ5018_CE_WFSS_REG_BASE, ++ .size = HAL_IPQ5018_CE_SIZE, ++}; ++ + const struct ath11k_hw_regs ipq8074_regs = { + /* SW2TCL(x) R0 ring configuration address */ + .hal_tcl1_ring_base_lsb = 0x00000510, +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -80,6 +80,8 @@ + #define ATH11K_M3_FILE "m3.bin" + #define ATH11K_REGDB_FILE_NAME "regdb.bin" + ++#define ATH11K_CE_OFFSET(ab) (ab->mem_ce - ab->mem) ++ + enum ath11k_hw_rate_cck { + ATH11K_HW_RATE_CCK_LP_11M = 0, + ATH11K_HW_RATE_CCK_LP_5_5M, +@@ -158,6 +160,8 @@ struct ath11k_hw_params { + u32 target_ce_count; + const struct service_to_pipe *svc_to_ce_map; + u32 svc_to_ce_map_len; ++ const struct ce_ie_addr *ce_ie_addr; ++ const struct ce_remap *ce_remap; + + bool single_pdev_only; + +@@ -277,6 +281,11 @@ extern const struct ath11k_hw_ring_mask + extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074; + extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750; + ++extern const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074; ++extern const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018; ++ ++extern const struct ce_remap ath11k_ce_remap_ipq5018; ++ + extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074; + extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390; + extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750; +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -543,6 +543,8 @@ static int ath11k_pci_claim(struct ath11 + goto clear_master; + } + ++ ab->mem_ce = ab->mem; ++ + ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); + return 0; + diff --git a/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-update-hal-srng-regs-for-IPQ5018.patch b/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-update-hal-srng-regs-for-IPQ5018.patch new file mode 100644 index 000000000..35ea20a3c --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-update-hal-srng-regs-for-IPQ5018.patch @@ -0,0 +1,130 @@ +From 711b80acbdfb9667a9cf8374e13320a6e624ce73 Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:14 +0200 +Subject: [PATCH] wifi: ath11k: update hal srng regs for IPQ5018 + +IPQ5018 hal srng register address & offsets are not +similar to IPQ8074/IPQ6018/QCN9074, hence define a +new set of srng register group data for IPQ5018. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-6-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 1 + + drivers/net/wireless/ath/ath11k/hw.c | 79 ++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath11k/hw.h | 1 + + 3 files changed, 81 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -634,6 +634,7 @@ static const struct ath11k_hw_params ath + .max_fft_bins = 1024, + }, + .internal_sleep_clock = false, ++ .regs = &ipq5018_regs, + .host_ce_config = ath11k_host_ce_config_qcn9074, + .ce_count = CE_CNT_5018, + .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -2645,6 +2645,85 @@ static const struct ath11k_hw_tcl2wbm_rb + }, + }; + ++const struct ath11k_hw_regs ipq5018_regs = { ++ /* SW2TCL(x) R0 ring configuration address */ ++ .hal_tcl1_ring_base_lsb = 0x00000694, ++ .hal_tcl1_ring_base_msb = 0x00000698, ++ .hal_tcl1_ring_id = 0x0000069c, ++ .hal_tcl1_ring_misc = 0x000006a4, ++ .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, ++ .hal_tcl1_ring_tp_addr_msb = 0x000006b4, ++ .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, ++ .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, ++ .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, ++ .hal_tcl1_ring_msi1_base_msb = 0x000006e0, ++ .hal_tcl1_ring_msi1_data = 0x000006e4, ++ .hal_tcl2_ring_base_lsb = 0x000006ec, ++ .hal_tcl_ring_base_lsb = 0x0000079c, ++ ++ /* TCL STATUS ring address */ ++ .hal_tcl_status_ring_base_lsb = 0x000008a4, ++ ++ /* REO2SW(x) R0 ring configuration address */ ++ .hal_reo1_ring_base_lsb = 0x000001ec, ++ .hal_reo1_ring_base_msb = 0x000001f0, ++ .hal_reo1_ring_id = 0x000001f4, ++ .hal_reo1_ring_misc = 0x000001fc, ++ .hal_reo1_ring_hp_addr_lsb = 0x00000200, ++ .hal_reo1_ring_hp_addr_msb = 0x00000204, ++ .hal_reo1_ring_producer_int_setup = 0x00000210, ++ .hal_reo1_ring_msi1_base_lsb = 0x00000234, ++ .hal_reo1_ring_msi1_base_msb = 0x00000238, ++ .hal_reo1_ring_msi1_data = 0x0000023c, ++ .hal_reo2_ring_base_lsb = 0x00000244, ++ .hal_reo1_aging_thresh_ix_0 = 0x00000564, ++ .hal_reo1_aging_thresh_ix_1 = 0x00000568, ++ .hal_reo1_aging_thresh_ix_2 = 0x0000056c, ++ .hal_reo1_aging_thresh_ix_3 = 0x00000570, ++ ++ /* REO2SW(x) R2 ring pointers (head/tail) address */ ++ .hal_reo1_ring_hp = 0x00003028, ++ .hal_reo1_ring_tp = 0x0000302c, ++ .hal_reo2_ring_hp = 0x00003030, ++ ++ /* REO2TCL R0 ring configuration address */ ++ .hal_reo_tcl_ring_base_lsb = 0x000003fc, ++ .hal_reo_tcl_ring_hp = 0x00003058, ++ ++ /* SW2REO ring address */ ++ .hal_sw2reo_ring_base_lsb = 0x0000013c, ++ .hal_sw2reo_ring_hp = 0x00003018, ++ ++ /* REO CMD ring address */ ++ .hal_reo_cmd_ring_base_lsb = 0x000000e4, ++ .hal_reo_cmd_ring_hp = 0x00003010, ++ ++ /* REO status address */ ++ .hal_reo_status_ring_base_lsb = 0x00000504, ++ .hal_reo_status_hp = 0x00003070, ++ ++ /* WCSS relative address */ ++ .hal_seq_wcss_umac_ce0_src_reg = 0x08400000 ++ - HAL_IPQ5018_CE_WFSS_REG_BASE, ++ .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000 ++ - HAL_IPQ5018_CE_WFSS_REG_BASE, ++ .hal_seq_wcss_umac_ce1_src_reg = 0x08402000 ++ - HAL_IPQ5018_CE_WFSS_REG_BASE, ++ .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000 ++ - HAL_IPQ5018_CE_WFSS_REG_BASE, ++ ++ /* WBM Idle address */ ++ .hal_wbm_idle_link_ring_base_lsb = 0x00000874, ++ .hal_wbm_idle_link_ring_misc = 0x00000884, ++ ++ /* SW2WBM release address */ ++ .hal_wbm_release_ring_base_lsb = 0x000001ec, ++ ++ /* WBM2SW release address */ ++ .hal_wbm0_release_ring_base_lsb = 0x00000924, ++ .hal_wbm1_release_ring_base_lsb = 0x0000097c, ++}; ++ + const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { + .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, + .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -415,6 +415,7 @@ extern const struct ath11k_hw_regs qca63 + extern const struct ath11k_hw_regs qcn9074_regs; + extern const struct ath11k_hw_regs wcn6855_regs; + extern const struct ath11k_hw_regs wcn6750_regs; ++extern const struct ath11k_hw_regs ipq5018_regs; + + static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type) + { diff --git a/package/kernel/mac80211/patches/ath11k/0023-wifi-ath11k-initialize-hw_ops-for-IPQ5018.patch b/package/kernel/mac80211/patches/ath11k/0023-wifi-ath11k-initialize-hw_ops-for-IPQ5018.patch new file mode 100644 index 000000000..5ef701a44 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0023-wifi-ath11k-initialize-hw_ops-for-IPQ5018.patch @@ -0,0 +1,90 @@ +From ba60f2793d3a37a00da14bb56a26558a902d2831 Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:14 +0200 +Subject: [PATCH] wifi: ath11k: initialize hw_ops for IPQ5018 + +The ipq5018_ops is initialized for IPQ5018. This is different from +other platforms. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-7-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 1 + + drivers/net/wireless/ath/ath11k/hw.c | 40 ++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath11k/hw.h | 1 + + 3 files changed, 42 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -635,6 +635,7 @@ static const struct ath11k_hw_params ath + }, + .internal_sleep_clock = false, + .regs = &ipq5018_regs, ++ .hw_ops = &ipq5018_ops, + .host_ce_config = ath11k_host_ce_config_qcn9074, + .ce_count = CE_CNT_5018, + .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -1084,6 +1084,46 @@ const struct ath11k_hw_ops wcn6750_ops = + .get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector, + }; + ++/* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */ ++const struct ath11k_hw_ops ipq5018_ops = { ++ .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, ++ .wmi_init_config = ath11k_init_wmi_config_ipq8074, ++ .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, ++ .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, ++ .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, ++ .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, ++ .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, ++ .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, ++ .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, ++ .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, ++ .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, ++ .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, ++ .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, ++ .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, ++ .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, ++ .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, ++ .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, ++ .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, ++ .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, ++ .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, ++ .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, ++ .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, ++ .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, ++ .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, ++ .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, ++ .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, ++ .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, ++ .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, ++ .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, ++ .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, ++ .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, ++ .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, ++ .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, ++ .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, ++ .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, ++ ++}; ++ + #define ATH11K_TX_RING_MASK_0 BIT(0) + #define ATH11K_TX_RING_MASK_1 BIT(1) + #define ATH11K_TX_RING_MASK_2 BIT(2) +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -275,6 +275,7 @@ extern const struct ath11k_hw_ops qca639 + extern const struct ath11k_hw_ops qcn9074_ops; + extern const struct ath11k_hw_ops wcn6855_ops; + extern const struct ath11k_hw_ops wcn6750_ops; ++extern const struct ath11k_hw_ops ipq5018_ops; + + extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074; + extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390; diff --git a/package/kernel/mac80211/patches/ath11k/0024-wifi-ath11k-add-new-hw-ops-for-IPQ5018-to-get-rx-des.patch b/package/kernel/mac80211/patches/ath11k/0024-wifi-ath11k-add-new-hw-ops-for-IPQ5018-to-get-rx-des.patch new file mode 100644 index 000000000..64531f13f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0024-wifi-ath11k-add-new-hw-ops-for-IPQ5018-to-get-rx-des.patch @@ -0,0 +1,84 @@ +From 69968f88f1770d61cae0febef805fd00d66cf6a1 Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:15 +0200 +Subject: [PATCH] wifi: ath11k: add new hw ops for IPQ5018 to get rx dest ring + hashmap + +The Destination ring control register is different +for IPQ5018 when compared to IPQ8074/IPQ6018/QCN9074. +Hence create a new hw ops to fetch the hash ring map +for different device variants. ipq5018 hw ops +is similar to qcn9074 except for this change, so reuse +all the qcn9074 ops for ipq5018. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-8-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/hw.c | 44 ++++++++++++++++++++++++++++ + 1 file changed, 44 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -791,6 +791,49 @@ static void ath11k_hw_wcn6855_reo_setup( + ring_hash_map); + } + ++static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab) ++{ ++ u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; ++ u32 val; ++ ++ /* Each hash entry uses three bits to map to a particular ring. */ ++ u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | ++ HAL_HASH_ROUTING_RING_SW2 << 4 | ++ HAL_HASH_ROUTING_RING_SW3 << 8 | ++ HAL_HASH_ROUTING_RING_SW4 << 12 | ++ HAL_HASH_ROUTING_RING_SW1 << 16 | ++ HAL_HASH_ROUTING_RING_SW2 << 20 | ++ HAL_HASH_ROUTING_RING_SW3 << 24 | ++ HAL_HASH_ROUTING_RING_SW4 << 28; ++ ++ val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); ++ ++ val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; ++ val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, ++ HAL_SRNG_RING_ID_REO2SW1) | ++ FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | ++ FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); ++ ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), ++ HAL_DEFAULT_REO_TIMEOUT_USEC); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), ++ HAL_DEFAULT_REO_TIMEOUT_USEC); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), ++ HAL_DEFAULT_REO_TIMEOUT_USEC); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), ++ HAL_DEFAULT_REO_TIMEOUT_USEC); ++ ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, ++ ring_hash_map); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, ++ ring_hash_map); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, ++ ring_hash_map); ++ ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, ++ ring_hash_map); ++} ++ + static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) + { + u16 peer_id = 0; +@@ -1117,6 +1160,7 @@ const struct ath11k_hw_ops ipq5018_ops = + .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, + .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, + .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, ++ .reo_setup = ath11k_hw_ipq5018_reo_setup, + .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, + .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, + .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, diff --git a/package/kernel/mac80211/patches/ath11k/0025-wifi-ath11k-add-ipq5018-device-support.patch b/package/kernel/mac80211/patches/ath11k/0025-wifi-ath11k-add-ipq5018-device-support.patch new file mode 100644 index 000000000..5b930e8d4 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0025-wifi-ath11k-add-ipq5018-device-support.patch @@ -0,0 +1,31 @@ +From 25edca7bb18a2a40cc7e54c6f522e9b3c917e2c5 Mon Sep 17 00:00:00 2001 +From: Sriram R +Date: Fri, 2 Dec 2022 23:37:15 +0200 +Subject: [PATCH] wifi: ath11k: add ipq5018 device support + +ipq5018 is a ahb 2ghz device, enable the compatible support for +ipq5018 in ahb. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sriram R +Co-developed-by: Karthikeyan Kathirvel +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221122132152.17771-9-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -32,6 +32,9 @@ static const struct of_device_id ath11k_ + { .compatible = "qcom,wcn6750-wifi", + .data = (void *)ATH11K_HW_WCN6750_HW10, + }, ++ { .compatible = "qcom,ipq5018-wifi", ++ .data = (void *)ATH11K_HW_IPQ5018_HW10, ++ }, + { } + }; + diff --git a/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch b/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch new file mode 100644 index 000000000..50c14e7b9 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0026-wifi-ath11k-Fix-scan-request-param-frame-size-warnin.patch @@ -0,0 +1,161 @@ +From d45daa6d1a8da080f1b516c570a8428a7b9225e4 Mon Sep 17 00:00:00 2001 +From: Karthikeyan Kathirvel +Date: Tue, 6 Dec 2022 00:51:25 +0530 +Subject: [PATCH] wifi: ath11k: Fix scan request param frame size warning + +Following warning was observed + +drivers/net/wireless/ath/ath11k/mac.c:2351:1: warning: the frame +size of 1184 bytes is larger than 1024 bytes [-Wframe-larger-than=] + +A local variable is declared with a size larger than 1024 bytes +this causing a compilation warning. Change the local variable to +heap memory to fix the warning. + +Tested-on: IPQ8074 AHB WLAN.HK.2.7.0.1-01701-QCAHKSWPL_SILICONZ-1 v2 + +Signed-off-by: Karthikeyan Kathirvel +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221205192125.13533-1-quic_kathirve@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 83 +++++++++++++++------------ + 1 file changed, 45 insertions(+), 38 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3612,7 +3612,7 @@ static int ath11k_mac_op_hw_scan(struct + struct ath11k *ar = hw->priv; + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); + struct cfg80211_scan_request *req = &hw_req->req; +- struct scan_req_params arg; ++ struct scan_req_params *arg = NULL; + int ret = 0; + int i; + u32 scan_timeout; +@@ -3640,72 +3640,78 @@ static int ath11k_mac_op_hw_scan(struct + if (ret) + goto exit; + +- memset(&arg, 0, sizeof(arg)); +- ath11k_wmi_start_scan_init(ar, &arg); +- arg.vdev_id = arvif->vdev_id; +- arg.scan_id = ATH11K_SCAN_ID; ++ arg = kzalloc(sizeof(*arg), GFP_KERNEL); ++ ++ if (!arg) { ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ ath11k_wmi_start_scan_init(ar, arg); ++ arg->vdev_id = arvif->vdev_id; ++ arg->scan_id = ATH11K_SCAN_ID; + + if (req->ie_len) { +- arg.extraie.ptr = kmemdup(req->ie, req->ie_len, GFP_KERNEL); +- if (!arg.extraie.ptr) { ++ arg->extraie.ptr = kmemdup(req->ie, req->ie_len, GFP_KERNEL); ++ if (!arg->extraie.ptr) { + ret = -ENOMEM; + goto exit; + } +- arg.extraie.len = req->ie_len; ++ arg->extraie.len = req->ie_len; + } + + if (req->n_ssids) { +- arg.num_ssids = req->n_ssids; +- for (i = 0; i < arg.num_ssids; i++) { +- arg.ssid[i].length = req->ssids[i].ssid_len; +- memcpy(&arg.ssid[i].ssid, req->ssids[i].ssid, ++ arg->num_ssids = req->n_ssids; ++ for (i = 0; i < arg->num_ssids; i++) { ++ arg->ssid[i].length = req->ssids[i].ssid_len; ++ memcpy(&arg->ssid[i].ssid, req->ssids[i].ssid, + req->ssids[i].ssid_len); + } + } else { +- arg.scan_flags |= WMI_SCAN_FLAG_PASSIVE; ++ arg->scan_flags |= WMI_SCAN_FLAG_PASSIVE; + } + + if (req->n_channels) { +- arg.num_chan = req->n_channels; +- arg.chan_list = kcalloc(arg.num_chan, sizeof(*arg.chan_list), +- GFP_KERNEL); ++ arg->num_chan = req->n_channels; ++ arg->chan_list = kcalloc(arg->num_chan, sizeof(*arg->chan_list), ++ GFP_KERNEL); + +- if (!arg.chan_list) { ++ if (!arg->chan_list) { + ret = -ENOMEM; + goto exit; + } + +- for (i = 0; i < arg.num_chan; i++) +- arg.chan_list[i] = req->channels[i]->center_freq; ++ for (i = 0; i < arg->num_chan; i++) ++ arg->chan_list[i] = req->channels[i]->center_freq; + } + + if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { +- arg.scan_f_add_spoofed_mac_in_probe = 1; +- ether_addr_copy(arg.mac_addr.addr, req->mac_addr); +- ether_addr_copy(arg.mac_mask.addr, req->mac_addr_mask); ++ arg->scan_f_add_spoofed_mac_in_probe = 1; ++ ether_addr_copy(arg->mac_addr.addr, req->mac_addr); ++ ether_addr_copy(arg->mac_mask.addr, req->mac_addr_mask); + } + + /* if duration is set, default dwell times will be overwritten */ + if (req->duration) { +- arg.dwell_time_active = req->duration; +- arg.dwell_time_active_2g = req->duration; +- arg.dwell_time_active_6g = req->duration; +- arg.dwell_time_passive = req->duration; +- arg.dwell_time_passive_6g = req->duration; +- arg.burst_duration = req->duration; ++ arg->dwell_time_active = req->duration; ++ arg->dwell_time_active_2g = req->duration; ++ arg->dwell_time_active_6g = req->duration; ++ arg->dwell_time_passive = req->duration; ++ arg->dwell_time_passive_6g = req->duration; ++ arg->burst_duration = req->duration; + +- scan_timeout = min_t(u32, arg.max_rest_time * +- (arg.num_chan - 1) + (req->duration + ++ scan_timeout = min_t(u32, arg->max_rest_time * ++ (arg->num_chan - 1) + (req->duration + + ATH11K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD) * +- arg.num_chan, arg.max_scan_time); ++ arg->num_chan, arg->max_scan_time); + } else { +- scan_timeout = arg.max_scan_time; ++ scan_timeout = arg->max_scan_time; + } + + /* Add a margin to account for event/command processing */ + scan_timeout += ATH11K_MAC_SCAN_CMD_EVT_OVERHEAD; + +- ret = ath11k_start_scan(ar, &arg); ++ ret = ath11k_start_scan(ar, arg); + if (ret) { + ath11k_warn(ar->ab, "failed to start hw scan: %d\n", ret); + spin_lock_bh(&ar->data_lock); +@@ -3717,10 +3723,11 @@ static int ath11k_mac_op_hw_scan(struct + msecs_to_jiffies(scan_timeout)); + + exit: +- kfree(arg.chan_list); +- +- if (req->ie_len) +- kfree(arg.extraie.ptr); ++ if (arg) { ++ kfree(arg->chan_list); ++ kfree(arg->extraie.ptr); ++ kfree(arg); ++ } + + mutex_unlock(&ar->conf_mutex); + diff --git a/package/kernel/mac80211/patches/ath11k/0029-wifi-ath11k-Add-support-to-configure-FTM-responder-r.patch b/package/kernel/mac80211/patches/ath11k/0029-wifi-ath11k-Add-support-to-configure-FTM-responder-r.patch new file mode 100644 index 000000000..f652d689b --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0029-wifi-ath11k-Add-support-to-configure-FTM-responder-r.patch @@ -0,0 +1,169 @@ +From a27c6a5853eb9d4f293b99be73a6891fe88263c7 Mon Sep 17 00:00:00 2001 +From: Sowmiya Sree Elavalagan +Date: Tue, 10 Jan 2023 15:30:57 +0200 +Subject: [PATCH] wifi: ath11k: Add support to configure FTM responder role + +Fine Timing Measurement(FTM) support is used to measure round trip +time between two nodes. + +Enable FTM responder feature using hw_params on supported device. +Since FTM functionality is offloaded to firmware, adding the +interface allows user space to enable or disable FTM responder. +Also add support for advertising the same in extended capabilities. + +QCA6390, WCN6855 and WCN6750 do not support this feature. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sowmiya Sree Elavalagan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221220044435.10506-1-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 8 ++++++++ + drivers/net/wireless/ath/ath11k/core.h | 1 + + drivers/net/wireless/ath/ath11k/hw.h | 1 + + drivers/net/wireless/ath/ath11k/mac.c | 20 +++++++++++++++++++- + drivers/net/wireless/ath/ath11k/wmi.h | 1 + + 5 files changed, 30 insertions(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -116,6 +116,7 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, ++ .ftm_responder = true, + }, + { + .hw_rev = ATH11K_HW_IPQ6018_HW10, +@@ -198,6 +199,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = false, ++ .ftm_responder = true, + }, + { + .name = "qca6390 hw2.0", +@@ -282,6 +284,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = true, ++ .ftm_responder = false, + }, + { + .name = "qcn9074 hw1.0", +@@ -363,6 +366,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = false, ++ .ftm_responder = true, + }, + { + .name = "wcn6855 hw2.0", +@@ -447,6 +451,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = true, ++ .ftm_responder = false, + }, + { + .name = "wcn6855 hw2.1", +@@ -529,6 +534,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = true, ++ .ftm_responder = false, + }, + { + .name = "wcn6750 hw1.0", +@@ -609,6 +615,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, + .smp2p_wow_exit = true, + .support_fw_mac_sequence = true, ++ .ftm_responder = false, + }, + { + .hw_rev = ATH11K_HW_IPQ5018_HW10, +@@ -688,6 +695,7 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = false, ++ .ftm_responder = true, + }, + }; + +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -346,6 +346,7 @@ struct ath11k_vif { + + bool is_started; + bool is_up; ++ bool ftm_responder; + bool spectral_enabled; + bool ps; + u32 aid; +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -224,6 +224,7 @@ struct ath11k_hw_params { + u32 tx_ring_size; + bool smp2p_wow_exit; + bool support_fw_mac_sequence; ++ bool ftm_responder; + }; + + struct ath11k_hw_ops { +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3110,7 +3110,7 @@ static void ath11k_mac_op_bss_info_chang + u16 bitrate; + int ret = 0; + u8 rateidx; +- u32 rate; ++ u32 rate, param; + u32 ipv4_cnt; + + mutex_lock(&ar->conf_mutex); +@@ -3412,6 +3412,20 @@ static void ath11k_mac_op_bss_info_chang + } + } + ++ if (changed & BSS_CHANGED_FTM_RESPONDER && ++ arvif->ftm_responder != info->ftm_responder && ++ ar->ab->hw_params.ftm_responder && ++ (vif->type == NL80211_IFTYPE_AP || ++ vif->type == NL80211_IFTYPE_MESH_POINT)) { ++ arvif->ftm_responder = info->ftm_responder; ++ param = WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE; ++ ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, ++ arvif->ftm_responder); ++ if (ret) ++ ath11k_warn(ar->ab, "Failed to set ftm responder %i: %d\n", ++ arvif->vdev_id, ret); ++ } ++ + if (changed & BSS_CHANGED_FILS_DISCOVERY || + changed & BSS_CHANGED_UNSOL_BCAST_PROBE_RESP) + ath11k_mac_fils_discovery(arvif, info); +@@ -9113,6 +9127,10 @@ static int __ath11k_mac_register(struct + wiphy_ext_feature_set(ar->hw->wiphy, + NL80211_EXT_FEATURE_SET_SCAN_DWELL); + ++ if (ab->hw_params.ftm_responder) ++ wiphy_ext_feature_set(ar->hw->wiphy, ++ NL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER); ++ + ath11k_reg_init(ar); + + if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -1073,6 +1073,7 @@ enum wmi_tlv_vdev_param { + WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, + WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, + WMI_VDEV_PARAM_HE_LTF = 0x74, ++ WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, + WMI_VDEV_PARAM_BA_MODE = 0x7e, + WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, + WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, diff --git a/package/kernel/mac80211/patches/ath11k/0030-wifi-ath11k-add-channel-177-into-5-GHz-channel-list.patch b/package/kernel/mac80211/patches/ath11k/0030-wifi-ath11k-add-channel-177-into-5-GHz-channel-list.patch new file mode 100644 index 000000000..d0ed9c54b --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0030-wifi-ath11k-add-channel-177-into-5-GHz-channel-list.patch @@ -0,0 +1,41 @@ +From e5e94d10c85653609a2893c8d0ef24a27471b68f Mon Sep 17 00:00:00 2001 +From: Wen Gong +Date: Tue, 10 Jan 2023 15:30:58 +0200 +Subject: [PATCH] wifi: ath11k: add channel 177 into 5 GHz channel list + +Add support for the 5 GHz channel 177 with center frequency 5885 MHz and +operating class 125 per IEEE Std 802.11ax-2021, Table E-4. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3 + +Signed-off-by: Wen Gong +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221220101912.30816-1-quic_wgong@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.h | 4 ++-- + drivers/net/wireless/ath/ath11k/mac.c | 1 + + 2 files changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -521,8 +521,8 @@ struct ath11k_sta { + #define ATH11K_MIN_5G_FREQ 4150 + #define ATH11K_MIN_6G_FREQ 5925 + #define ATH11K_MAX_6G_FREQ 7115 +-#define ATH11K_NUM_CHANS 101 +-#define ATH11K_MAX_5G_CHAN 173 ++#define ATH11K_NUM_CHANS 102 ++#define ATH11K_MAX_5G_CHAN 177 + + enum ath11k_state { + ATH11K_STATE_OFF, +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -96,6 +96,7 @@ static const struct ieee80211_channel at + CHAN5G(165, 5825, 0), + CHAN5G(169, 5845, 0), + CHAN5G(173, 5865, 0), ++ CHAN5G(177, 5885, 0), + }; + + static const struct ieee80211_channel ath11k_6ghz_channels[] = { diff --git a/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-fix-ce-memory-mapping-for-ahb-devices.patch b/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-fix-ce-memory-mapping-for-ahb-devices.patch new file mode 100644 index 000000000..278679997 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0031-wifi-ath11k-fix-ce-memory-mapping-for-ahb-devices.patch @@ -0,0 +1,114 @@ +From 53a998c4d7284debd77734d01e1466e59a1d03b2 Mon Sep 17 00:00:00 2001 +From: Raj Kumar Bhagat +Date: Fri, 13 Jan 2023 12:02:09 +0530 +Subject: [PATCH] wifi: ath11k: fix ce memory mapping for ahb devices + +Currently ath11k_ahb module is not loaded successfully and the wifi +interface is not created. Kernel trace is seen while loading the +ath11k_ahb module. The issue is seen in all ath11k AHB devices except +in IPQ5018. + +This happens because in ath11k_ahb_probe(), ab->mem_ce is initialized +with the value of ab->mem. However, at this instant ab->mem is not +yet set. + +Later, during write to a particular memory via ath11k_ahb_write32() +this ab->mem_ce is used with particular offset. Since ab->mem_ce is +not set properly this possibly leads to memory conflict to handle +kernel paging request and the below trace is seen. + +[ 93.035047] Unable to handle kernel paging request at virtual address ffff800100a00000 +[ 93.035083] Mem abort info: +[ 93.041869] ESR = 0x0000000096000045 +[ 93.044561] EC = 0x25: DABT (current EL), IL = 32 bits +[ 93.048377] SET = 0, FnV = 0 +[ 93.053840] EA = 0, S1PTW = 0 +[ 93.056704] FSC = 0x05: level 1 translation fault +[ 93.059745] Data abort info: +[ 93.064603] ISV = 0, ISS = 0x00000045 +[ 93.067729] CM = 0, WnR = 1 +[ 93.071287] swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000042219000 +[ 93.074409] [ffff800100a00000] pgd=100000007ffff003, p4d=100000007ffff003, pud=0000000000000000 +[ 93.081195] Internal error: Oops: 0000000096000045 [#1] PREEMPT SMP +[ 93.089598] Modules linked in: ath11k_ahb ath11k_pci ath11k qmi_helpers +[ 93.095851] CPU: 2 PID: 66 Comm: kworker/u8:3 Not tainted 6.1.0-rc8-wt-ath-658126-g58e4b9df840c-dirty #2 +[ 93.102454] Hardware name: Qualcomm Technologies, Inc. IPQ8074/AP-HK14 (DT) +[ 93.112171] Workqueue: ath11k_qmi_driver_event ath11k_qmi_driver_event_work [ath11k] +[ 93.118856] pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) +[ 93.126838] pc : ath11k_ahb_write32+0xc/0x18 [ath11k_ahb] +[ 93.133520] lr : ath11k_hal_srng_setup+0x860/0x8f0 [ath11k] +[ 93.139075] sp : ffff80000aaebb70 +[ 93.144452] x29: ffff80000aaebb70 x28: 0000000000000020 x27: ffff80000aaebc50 +[ 93.147934] x26: ffff000004923750 x25: ffff000004921200 x24: ffff000004928000 +[ 93.155051] x23: 0000000000000020 x22: ffff000004930000 x21: ffff000004923200 +[ 93.162170] x20: ffff000004920000 x19: 00000000eea00000 x18: ffff0000049200f0 +[ 93.169288] x17: 0000000000000000 x16: 0000000000000000 x15: 000000000000025e +[ 93.176405] x14: ffff000003c414f0 x13: 0000000000000000 x12: 0000000000000008 +[ 93.183524] x11: ffff000003c41488 x10: 0000000000000040 x9 : 0000000000000000 +[ 93.190641] x8 : ffff80000a9dd100 x7 : 0000000000000000 x6 : 000000000000003f +[ 93.197759] x5 : ffff800100a00400 x4 : ffff8000031f4018 x3 : 0000000000000004 +[ 93.204877] x2 : 0000000047b62000 x1 : ffff800100a00000 x0 : ffff800012000000 +[ 93.211996] Call trace: +[ 93.219104] ath11k_ahb_write32+0xc/0x18 [ath11k_ahb] +[ 93.221366] ath11k_ce_init_ring+0x184/0x278 [ath11k] +[ 93.226576] ath11k_ce_init_pipes+0x4c/0x1a0 [ath11k] +[ 93.231610] ath11k_core_qmi_firmware_ready+0x3c/0x568 [ath11k] +[ 93.236646] ath11k_qmi_driver_event_work+0x168/0x4f8 [ath11k] +[ 93.242376] process_one_work+0x144/0x350 +[ 93.248275] worker_thread+0x120/0x430 +[ 93.252352] kthread+0xf4/0x110 +[ 93.255997] ret_from_fork+0x10/0x20 +[ 93.259043] Code: d503201f f94e1c00 8b214001 d50332bf (b9000022) +[ 93.262863] ---[ end trace 0000000000000000 ]--- + +However, for the device IPQ5018 ath11k_hw_params .ce_remap is +defined. This parameter is used to recalculate ab->mem_ce and hence, +this issue is not seen in IPQ5018. + +Hence, fix this by initializing ab->mem_ce after ab->mem is set. +ab->mem is set inside the ath11k_ahb_setup_resources() therefore +initialize ab->mem_ce after ath11k_ahb_setup_resources(). + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Fixes: b42b3678c91f ("wifi: ath11k: remap ce register space for IPQ5018") + +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230113063209.7256-1-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -1157,12 +1157,16 @@ static int ath11k_ahb_probe(struct platf + goto err_core_free; + } + +- ab->mem_ce = ab->mem; +- + ret = ath11k_core_pre_init(ab); + if (ret) + goto err_core_free; + ++ ret = ath11k_ahb_setup_resources(ab); ++ if (ret) ++ goto err_core_free; ++ ++ ab->mem_ce = ab->mem; ++ + if (ab->hw_params.ce_remap) { + const struct ce_remap *ce_remap = ab->hw_params.ce_remap; + /* ce register space is moved out of wcss unlike ipq8074 or ipq6018 +@@ -1177,10 +1181,6 @@ static int ath11k_ahb_probe(struct platf + } + } + +- ret = ath11k_ahb_setup_resources(ab); +- if (ret) +- goto err_core_free; +- + ret = ath11k_ahb_fw_resources_init(ab); + if (ret) + goto err_core_free; diff --git a/package/kernel/mac80211/patches/ath11k/0033-wifi-ath11k-Set-ext-passive-scan-flag-to-adjust-pass.patch b/package/kernel/mac80211/patches/ath11k/0033-wifi-ath11k-Set-ext-passive-scan-flag-to-adjust-pass.patch new file mode 100644 index 000000000..79b79e105 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0033-wifi-ath11k-Set-ext-passive-scan-flag-to-adjust-pass.patch @@ -0,0 +1,73 @@ +From cf8f3d4deb02a8fdc806c46d4112b69868544697 Mon Sep 17 00:00:00 2001 +From: Tamizh Chelvam Raja +Date: Wed, 15 Feb 2023 20:31:36 +0200 +Subject: [PATCH] wifi: ath11k: Set ext passive scan flag to adjust passive + scan start time + +Set the WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE flag +while sending the scan command. If this flag is enabled when the +incoming scan request comes with a strict start time and its duration +overlaps with next TBTT, then target adjust the start time accordingly +for passive scan. Target supporting this feature will advertise +WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-01467-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Tamizh Chelvam Raja +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221222131720.11368-1-quic_tamizhr@quicinc.com +--- + drivers/net/wireless/ath/ath11k/wmi.c | 8 ++++++++ + drivers/net/wireless/ath/ath11k/wmi.h | 3 +++ + 2 files changed, 11 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -2068,6 +2068,12 @@ void ath11k_wmi_start_scan_init(struct a + WMI_SCAN_EVENT_FOREIGN_CHAN | + WMI_SCAN_EVENT_DEQUEUED; + arg->scan_flags |= WMI_SCAN_CHAN_STAT_EVENT; ++ ++ if (test_bit(WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE, ++ ar->ab->wmi_ab.svc_map)) ++ arg->scan_ctrl_flags_ext |= ++ WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE; ++ + arg->num_bssid = 1; + + /* fill bssid_list[0] with 0xff, otherwise bssid and RA will be +@@ -2149,6 +2155,8 @@ ath11k_wmi_copy_scan_event_cntrl_flags(s + /* for adaptive scan mode using 3 bits (21 - 23 bits) */ + WMI_SCAN_SET_DWELL_MODE(cmd->scan_ctrl_flags, + param->adaptive_dwell_time_mode); ++ ++ cmd->scan_ctrl_flags_ext = param->scan_ctrl_flags_ext; + } + + int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar, +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2093,6 +2093,7 @@ enum wmi_tlv_service { + WMI_TLV_SERVICE_EXT2_MSG = 220, + WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, + WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, ++ WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, + + /* The second 128 bits */ + WMI_MAX_EXT_SERVICE = 256, +@@ -3223,6 +3224,7 @@ struct wmi_start_scan_cmd { + + #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 + #define WMI_SCAN_DWELL_MODE_SHIFT 21 ++#define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800 + + enum { + WMI_SCAN_DWELL_MODE_DEFAULT = 0, +@@ -3270,6 +3272,7 @@ struct scan_req_params { + }; + u32 scan_events; + }; ++ u32 scan_ctrl_flags_ext; + u32 dwell_time_active; + u32 dwell_time_active_2g; + u32 dwell_time_passive; diff --git a/package/kernel/mac80211/patches/ath11k/0034-wifi-ath11k-fix-return-value-check-in-ath11k_ahb_pro.patch b/package/kernel/mac80211/patches/ath11k/0034-wifi-ath11k-fix-return-value-check-in-ath11k_ahb_pro.patch new file mode 100644 index 000000000..59132913b --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0034-wifi-ath11k-fix-return-value-check-in-ath11k_ahb_pro.patch @@ -0,0 +1,27 @@ +From 342fcde9d91460f01f65707e16368a1571271a3a Mon Sep 17 00:00:00 2001 +From: Yang Yingliang +Date: Fri, 17 Feb 2023 11:00:31 +0800 +Subject: [PATCH] wifi: ath11k: fix return value check in ath11k_ahb_probe() + +ioremap() returns NULL pointer not PTR_ERR() when it fails, +so replace the IS_ERR() check with NULL pointer check. + +Fixes: b42b3678c91f ("wifi: ath11k: remap ce register space for IPQ5018") +Signed-off-by: Yang Yingliang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230217030031.4021289-1-yangyingliang@huawei.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -1174,7 +1174,7 @@ static int ath11k_ahb_probe(struct platf + * to a new space for accessing them. + */ + ab->mem_ce = ioremap(ce_remap->base, ce_remap->size); +- if (IS_ERR(ab->mem_ce)) { ++ if (!ab->mem_ce) { + dev_err(&pdev->dev, "ce ioremap error\n"); + ret = -ENOMEM; + goto err_core_free; diff --git a/package/kernel/mac80211/patches/ath11k/0035-wifi-ath11k-Use-platform_get_irq-to-get-the-interrup.patch b/package/kernel/mac80211/patches/ath11k/0035-wifi-ath11k-Use-platform_get_irq-to-get-the-interrup.patch new file mode 100644 index 000000000..93a9da8fc --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0035-wifi-ath11k-Use-platform_get_irq-to-get-the-interrup.patch @@ -0,0 +1,50 @@ +From f117276638b7600b981b3fe28550823cfbe1ef23 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 1 Feb 2023 08:54:42 -0800 +Subject: [PATCH] wifi: ath11k: Use platform_get_irq() to get the interrupt + +As of commit a1a2b7125e10 ("of/platform: Drop static setup of IRQ +resource from DT core"), we need to use platform_get_irq() instead of +platform_get_resource() to get our IRQs because +platform_get_resource() simply won't get them anymore. + +This was already fixed in several other Atheros WiFi drivers, +apparently in response to Zeal Robot reports. An example of another +fix is commit 9503a1fc123d ("ath9k: Use platform_get_irq() to get the +interrupt"). ath11k seems to have been missed in this effort, though. + +Without this change, WiFi wasn't coming up on my Qualcomm sc7280-based +hardware. Specifically, "platform_get_resource(pdev, IORESOURCE_IRQ, +i)" was failing even for i=0. + +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 + +Fixes: a1a2b7125e10 ("of/platform: Drop static setup of IRQ resource from DT core") +Fixes: 00402f49d26f ("ath11k: Add support for WCN6750 device") +Signed-off-by: Douglas Anderson +Tested-by: Jun Yu +Reviewed-by: Lad Prabhakar +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230201084131.v2.1.I69cf3d56c97098287fe3a70084ee515098390b70@changeid +--- + drivers/net/wireless/ath/ath11k/ahb.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -874,11 +874,11 @@ static int ath11k_ahb_setup_msi_resource + ab->pci.msi.ep_base_data = int_prop + 32; + + for (i = 0; i < ab->pci.msi.config->total_vectors; i++) { +- res = platform_get_resource(pdev, IORESOURCE_IRQ, i); +- if (!res) +- return -ENODEV; ++ ret = platform_get_irq(pdev, i); ++ if (ret < 0) ++ return ret; + +- ab->pci.msi.irqs[i] = res->start; ++ ab->pci.msi.irqs[i] = ret; + } + + set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); diff --git a/package/kernel/mac80211/patches/ath11k/0036-wifi-ath11k-fix-SAC-bug-on-peer-addition-with-sta-ba.patch b/package/kernel/mac80211/patches/ath11k/0036-wifi-ath11k-fix-SAC-bug-on-peer-addition-with-sta-ba.patch new file mode 100644 index 000000000..b37f070ba --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0036-wifi-ath11k-fix-SAC-bug-on-peer-addition-with-sta-ba.patch @@ -0,0 +1,53 @@ +From 60b7d62ba8cdbd073997bff0f1cdae8d844002c0 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 9 Feb 2023 23:26:22 +0100 +Subject: [PATCH] wifi: ath11k: fix SAC bug on peer addition with sta band + migration + +Fix sleep in atomic context warning detected by Smatch static checker +analyzer. + +Following the locking pattern for peer_rhash_add lock tbl_mtx_lock mutex +always even if sta is not transitioning to another band. +This is peer_add function and a more secure locking should not cause +performance regression. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1-01208-QCAHKSWPL_SILICONZ-1 + +Fixes: d673cb6fe6c0 ("wifi: ath11k: fix peer addition/deletion error on sta band migration") +Reported-by: Dan Carpenter +Signed-off-by: Christian Marangi +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230209222622.1751-1-ansuelsmth@gmail.com +--- + drivers/net/wireless/ath/ath11k/peer.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/peer.c ++++ b/drivers/net/wireless/ath/ath11k/peer.c +@@ -382,22 +382,23 @@ int ath11k_peer_create(struct ath11k *ar + return -ENOBUFS; + } + ++ mutex_lock(&ar->ab->tbl_mtx_lock); + spin_lock_bh(&ar->ab->base_lock); + peer = ath11k_peer_find_by_addr(ar->ab, param->peer_addr); + if (peer) { + if (peer->vdev_id == param->vdev_id) { + spin_unlock_bh(&ar->ab->base_lock); ++ mutex_unlock(&ar->ab->tbl_mtx_lock); + return -EINVAL; + } + + /* Assume sta is transitioning to another band. + * Remove here the peer from rhash. + */ +- mutex_lock(&ar->ab->tbl_mtx_lock); + ath11k_peer_rhash_delete(ar->ab, peer); +- mutex_unlock(&ar->ab->tbl_mtx_lock); + } + spin_unlock_bh(&ar->ab->base_lock); ++ mutex_unlock(&ar->ab->tbl_mtx_lock); + + ret = ath11k_wmi_send_peer_create_cmd(ar, param); + if (ret) { diff --git a/package/kernel/mac80211/patches/ath11k/0037-wifi-ath11k-allow-system-suspend-to-survive-ath11k.patch b/package/kernel/mac80211/patches/ath11k/0037-wifi-ath11k-allow-system-suspend-to-survive-ath11k.patch new file mode 100644 index 000000000..fa680954e --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0037-wifi-ath11k-allow-system-suspend-to-survive-ath11k.patch @@ -0,0 +1,43 @@ +From 7c15430822e71e90203d87e6d0cfe83fa058b0dc Mon Sep 17 00:00:00 2001 +From: Len Brown +Date: Wed, 1 Feb 2023 12:32:01 -0600 +Subject: [PATCH] wifi: ath11k: allow system suspend to survive ath11k + +When ath11k runs into internal errors upon suspend, +it returns an error code to pci_pm_suspend, which +aborts the entire system suspend. + +The driver should not abort system suspend, but should +keep its internal errors to itself, and allow the system +to suspend. Otherwise, a user can suspend a laptop +by closing the lid and sealing it into a case, assuming +that is will suspend, rather than heating up and draining +the battery when in transit. + +In practice, the ath11k device seems to have plenty of transient +errors, and subsequent suspend cycles after this failure +often succeed. + +https://bugzilla.kernel.org/show_bug.cgi?id=216968 + +Fixes: d1b0c33850d29 ("ath11k: implement suspend for QCA6390 PCI devices") + +Signed-off-by: Len Brown +Cc: stable@vger.kernel.org +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230201183201.14431-1-len.brown@intel.com +--- + drivers/net/wireless/ath/ath11k/pci.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -998,7 +998,7 @@ static __maybe_unused int ath11k_pci_pm_ + if (ret) + ath11k_warn(ab, "failed to resume core: %d\n", ret); + +- return ret; ++ return 0; + } + + static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, diff --git a/package/kernel/mac80211/patches/ath11k/0038-wifi-ath11k-modify-accessor-macros-to-match-index-si.patch b/package/kernel/mac80211/patches/ath11k/0038-wifi-ath11k-modify-accessor-macros-to-match-index-si.patch new file mode 100644 index 000000000..42bf170a0 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0038-wifi-ath11k-modify-accessor-macros-to-match-index-si.patch @@ -0,0 +1,61 @@ +From a96f10422e74cde27c100b321b127ec32ae75747 Mon Sep 17 00:00:00 2001 +From: Muna Sinada +Date: Fri, 24 Feb 2023 12:28:03 +0200 +Subject: [PATCH] wifi: ath11k: modify accessor macros to match index size + +HE PHY is only 11 bytes, therefore it should be using byte indexes +instead of dword. Change corresponding macros to reflect this. + +Signed-off-by: Muna Sinada +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/1666128501-12364-2-git-send-email-quic_msinada@quicinc.com +--- + drivers/net/wireless/ath/ath11k/wmi.h | 24 +++++++++++++----------- + 1 file changed, 13 insertions(+), 11 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2859,30 +2859,32 @@ struct rx_reorder_queue_remove_params { + #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) + #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) + +-#define HECAP_PHYDWORD_0 0 +-#define HECAP_PHYDWORD_1 1 +-#define HECAP_PHYDWORD_2 2 ++#define HE_PHYCAP_BYTE_0 0 ++#define HE_PHYCAP_BYTE_1 1 ++#define HE_PHYCAP_BYTE_2 2 ++#define HE_PHYCAP_BYTE_3 3 ++#define HE_PHYCAP_BYTE_4 4 + +-#define HECAP_PHY_SU_BFER BIT(31) ++#define HECAP_PHY_SU_BFER BIT(7) + #define HECAP_PHY_SU_BFEE BIT(0) + #define HECAP_PHY_MU_BFER BIT(1) +-#define HECAP_PHY_UL_MUMIMO BIT(22) +-#define HECAP_PHY_UL_MUOFDMA BIT(23) ++#define HECAP_PHY_UL_MUMIMO BIT(6) ++#define HECAP_PHY_UL_MUOFDMA BIT(7) + + #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ +- FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HECAP_PHYDWORD_0]) ++ FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3]) + + #define HECAP_PHY_SUBFME_GET(hecap_phy) \ +- FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HECAP_PHYDWORD_1]) ++ FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4]) + + #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ +- FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HECAP_PHYDWORD_1]) ++ FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4]) + + #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ +- FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HECAP_PHYDWORD_0]) ++ FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2]) + + #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ +- FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HECAP_PHYDWORD_0]) ++ FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2]) + + #define HE_MODE_SU_TX_BFEE BIT(0) + #define HE_MODE_SU_TX_BFER BIT(1) diff --git a/package/kernel/mac80211/patches/ath11k/0039-wifi-ath11k-push-MU-MIMO-params-from-hostapd-to-hard.patch b/package/kernel/mac80211/patches/ath11k/0039-wifi-ath11k-push-MU-MIMO-params-from-hostapd-to-hard.patch new file mode 100644 index 000000000..298ce1a61 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0039-wifi-ath11k-push-MU-MIMO-params-from-hostapd-to-hard.patch @@ -0,0 +1,300 @@ +From 38dfe775d0abf511341f37c1cb77b919a3ad410b Mon Sep 17 00:00:00 2001 +From: Muna Sinada +Date: Fri, 24 Feb 2023 12:28:04 +0200 +Subject: [PATCH] wifi: ath11k: push MU-MIMO params from hostapd to hardware + +In the previous behaviour only HE IE in management frames are changed +regarding MU-MIMO configurations and not in hardware. Adding push of +MU-MIMO configurations to the hardware as well. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00356-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: Anilkumar Kolli +Signed-off-by: Anilkumar Kolli +Signed-off-by: Muna Sinada +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/1666128501-12364-3-git-send-email-quic_msinada@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 200 ++++++++++++++++---------- + drivers/net/wireless/ath/ath11k/wmi.h | 3 + + 2 files changed, 130 insertions(+), 73 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -2699,6 +2699,117 @@ static int ath11k_setup_peer_smps(struct + ath11k_smps_map[smps]); + } + ++static bool ath11k_mac_set_he_txbf_conf(struct ath11k_vif *arvif) ++{ ++ struct ath11k *ar = arvif->ar; ++ u32 param, value; ++ int ret; ++ ++ if (!arvif->vif->bss_conf.he_support) ++ return true; ++ ++ param = WMI_VDEV_PARAM_SET_HEMU_MODE; ++ value = 0; ++ if (arvif->vif->bss_conf.he_su_beamformer) { ++ value |= FIELD_PREP(HE_MODE_SU_TX_BFER, HE_SU_BFER_ENABLE); ++ if (arvif->vif->bss_conf.he_mu_beamformer && ++ arvif->vdev_type == WMI_VDEV_TYPE_AP) ++ value |= FIELD_PREP(HE_MODE_MU_TX_BFER, HE_MU_BFER_ENABLE); ++ } ++ ++ if (arvif->vif->type != NL80211_IFTYPE_MESH_POINT) { ++ value |= FIELD_PREP(HE_MODE_DL_OFDMA, HE_DL_MUOFDMA_ENABLE) | ++ FIELD_PREP(HE_MODE_UL_OFDMA, HE_UL_MUOFDMA_ENABLE); ++ ++ if (arvif->vif->bss_conf.he_full_ul_mumimo) ++ value |= FIELD_PREP(HE_MODE_UL_MUMIMO, HE_UL_MUMIMO_ENABLE); ++ ++ if (arvif->vif->bss_conf.he_su_beamformee) ++ value |= FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE); ++ } ++ ++ ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, value); ++ if (ret) { ++ ath11k_warn(ar->ab, "failed to set vdev %d HE MU mode: %d\n", ++ arvif->vdev_id, ret); ++ return false; ++ } ++ ++ param = WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE; ++ value = FIELD_PREP(HE_VHT_SOUNDING_MODE, HE_VHT_SOUNDING_MODE_ENABLE) | ++ FIELD_PREP(HE_TRIG_NONTRIG_SOUNDING_MODE, ++ HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE); ++ ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, ++ param, value); ++ if (ret) { ++ ath11k_warn(ar->ab, "failed to set vdev %d sounding mode: %d\n", ++ arvif->vdev_id, ret); ++ return false; ++ } ++ return true; ++} ++ ++static bool ath11k_mac_vif_recalc_sta_he_txbf(struct ath11k *ar, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta_he_cap *he_cap) ++{ ++ struct ath11k_vif *arvif = (void *)vif->drv_priv; ++ struct ieee80211_he_cap_elem he_cap_elem = {0}; ++ struct ieee80211_sta_he_cap *cap_band = NULL; ++ struct cfg80211_chan_def def; ++ u32 param = WMI_VDEV_PARAM_SET_HEMU_MODE; ++ u32 hemode = 0; ++ int ret; ++ ++ if (!vif->bss_conf.he_support) ++ return true; ++ ++ if (vif->type != NL80211_IFTYPE_STATION) ++ return false; ++ ++ if (WARN_ON(ath11k_mac_vif_chan(vif, &def))) ++ return false; ++ ++ if (def.chan->band == NL80211_BAND_2GHZ) ++ cap_band = &ar->mac.iftype[NL80211_BAND_2GHZ][vif->type].he_cap; ++ else ++ cap_band = &ar->mac.iftype[NL80211_BAND_5GHZ][vif->type].he_cap; ++ ++ memcpy(&he_cap_elem, &cap_band->he_cap_elem, sizeof(he_cap_elem)); ++ ++ if (HECAP_PHY_SUBFME_GET(he_cap_elem.phy_cap_info)) { ++ if (HECAP_PHY_SUBFMR_GET(he_cap->he_cap_elem.phy_cap_info)) ++ hemode |= FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE); ++ if (HECAP_PHY_MUBFMR_GET(he_cap->he_cap_elem.phy_cap_info)) ++ hemode |= FIELD_PREP(HE_MODE_MU_TX_BFEE, HE_MU_BFEE_ENABLE); ++ } ++ ++ if (vif->type != NL80211_IFTYPE_MESH_POINT) { ++ hemode |= FIELD_PREP(HE_MODE_DL_OFDMA, HE_DL_MUOFDMA_ENABLE) | ++ FIELD_PREP(HE_MODE_UL_OFDMA, HE_UL_MUOFDMA_ENABLE); ++ ++ if (HECAP_PHY_ULMUMIMO_GET(he_cap_elem.phy_cap_info)) ++ if (HECAP_PHY_ULMUMIMO_GET(he_cap->he_cap_elem.phy_cap_info)) ++ hemode |= FIELD_PREP(HE_MODE_UL_MUMIMO, ++ HE_UL_MUMIMO_ENABLE); ++ ++ if (FIELD_GET(HE_MODE_MU_TX_BFEE, hemode)) ++ hemode |= FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE); ++ ++ if (FIELD_GET(HE_MODE_MU_TX_BFER, hemode)) ++ hemode |= FIELD_PREP(HE_MODE_SU_TX_BFER, HE_SU_BFER_ENABLE); ++ } ++ ++ ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, hemode); ++ if (ret) { ++ ath11k_warn(ar->ab, "failed to submit vdev param txbf 0x%x: %d\n", ++ hemode, ret); ++ return false; ++ } ++ ++ return true; ++} ++ + static void ath11k_bss_assoc(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *bss_conf) +@@ -2709,6 +2820,7 @@ static void ath11k_bss_assoc(struct ieee + struct ieee80211_sta *ap_sta; + struct ath11k_peer *peer; + bool is_auth = false; ++ struct ieee80211_sta_he_cap he_cap; + int ret; + + lockdep_assert_held(&ar->conf_mutex); +@@ -2726,6 +2838,9 @@ static void ath11k_bss_assoc(struct ieee + return; + } + ++ /* he_cap here is updated at assoc success for sta mode only */ ++ he_cap = ap_sta->deflink.he_cap; ++ + ath11k_peer_assoc_prepare(ar, vif, ap_sta, &peer_arg, false); + + rcu_read_unlock(); +@@ -2753,6 +2868,12 @@ static void ath11k_bss_assoc(struct ieee + return; + } + ++ if (!ath11k_mac_vif_recalc_sta_he_txbf(ar, vif, &he_cap)) { ++ ath11k_warn(ar->ab, "failed to recalc he txbf for vdev %i on bss %pM\n", ++ arvif->vdev_id, bss_conf->bssid); ++ return; ++ } ++ + WARN_ON(arvif->is_up); + + arvif->aid = vif->cfg.aid; +@@ -3202,6 +3323,8 @@ static void ath11k_mac_op_bss_info_chang + ether_addr_copy(arvif->bssid, info->bssid); + + if (changed & BSS_CHANGED_BEACON_ENABLED) { ++ if (info->enable_beacon) ++ ath11k_mac_set_he_txbf_conf(arvif); + ath11k_control_beaconing(arvif, info); + + if (arvif->is_up && vif->bss_conf.he_support && +@@ -5392,6 +5515,10 @@ static int ath11k_mac_copy_he_cap(struct + + he_cap_elem->mac_cap_info[1] &= + IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_MASK; ++ he_cap_elem->phy_cap_info[0] &= ++ ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; ++ he_cap_elem->phy_cap_info[0] &= ++ ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; + + he_cap_elem->phy_cap_info[5] &= + ~IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; +@@ -6026,69 +6153,6 @@ ath11k_mac_setup_vdev_create_params(stru + } + } + +-static u32 +-ath11k_mac_prepare_he_mode(struct ath11k_pdev *pdev, u32 viftype) +-{ +- struct ath11k_pdev_cap *pdev_cap = &pdev->cap; +- struct ath11k_band_cap *cap_band = NULL; +- u32 *hecap_phy_ptr = NULL; +- u32 hemode = 0; +- +- if (pdev->cap.supported_bands & WMI_HOST_WLAN_2G_CAP) +- cap_band = &pdev_cap->band[NL80211_BAND_2GHZ]; +- else +- cap_band = &pdev_cap->band[NL80211_BAND_5GHZ]; +- +- hecap_phy_ptr = &cap_band->he_cap_phy_info[0]; +- +- hemode = FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE) | +- FIELD_PREP(HE_MODE_SU_TX_BFER, HECAP_PHY_SUBFMR_GET(hecap_phy_ptr)) | +- FIELD_PREP(HE_MODE_UL_MUMIMO, HECAP_PHY_ULMUMIMO_GET(hecap_phy_ptr)); +- +- /* TODO WDS and other modes */ +- if (viftype == NL80211_IFTYPE_AP) { +- hemode |= FIELD_PREP(HE_MODE_MU_TX_BFER, +- HECAP_PHY_MUBFMR_GET(hecap_phy_ptr)) | +- FIELD_PREP(HE_MODE_DL_OFDMA, HE_DL_MUOFDMA_ENABLE) | +- FIELD_PREP(HE_MODE_UL_OFDMA, HE_UL_MUOFDMA_ENABLE); +- } else { +- hemode |= FIELD_PREP(HE_MODE_MU_TX_BFEE, HE_MU_BFEE_ENABLE); +- } +- +- return hemode; +-} +- +-static int ath11k_set_he_mu_sounding_mode(struct ath11k *ar, +- struct ath11k_vif *arvif) +-{ +- u32 param_id, param_value; +- struct ath11k_base *ab = ar->ab; +- int ret = 0; +- +- param_id = WMI_VDEV_PARAM_SET_HEMU_MODE; +- param_value = ath11k_mac_prepare_he_mode(ar->pdev, arvif->vif->type); +- ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- param_id, param_value); +- if (ret) { +- ath11k_warn(ab, "failed to set vdev %d HE MU mode: %d param_value %x\n", +- arvif->vdev_id, ret, param_value); +- return ret; +- } +- param_id = WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE; +- param_value = +- FIELD_PREP(HE_VHT_SOUNDING_MODE, HE_VHT_SOUNDING_MODE_ENABLE) | +- FIELD_PREP(HE_TRIG_NONTRIG_SOUNDING_MODE, +- HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE); +- ret = ath11k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- param_id, param_value); +- if (ret) { +- ath11k_warn(ab, "failed to set vdev %d HE MU mode: %d\n", +- arvif->vdev_id, ret); +- return ret; +- } +- return ret; +-} +- + static void ath11k_mac_op_update_vif_offload(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) + { +@@ -6757,7 +6821,6 @@ ath11k_mac_vdev_start_restart(struct ath + struct ath11k_base *ab = ar->ab; + struct wmi_vdev_start_req_arg arg = {}; + const struct cfg80211_chan_def *chandef = &ctx->def; +- int he_support = arvif->vif->bss_conf.he_support; + int ret = 0; + + lockdep_assert_held(&ar->conf_mutex); +@@ -6798,15 +6861,6 @@ ath11k_mac_vdev_start_restart(struct ath + spin_lock_bh(&ab->base_lock); + arg.regdomain = ar->ab->dfs_region; + spin_unlock_bh(&ab->base_lock); +- +- if (he_support) { +- ret = ath11k_set_he_mu_sounding_mode(ar, arvif); +- if (ret) { +- ath11k_warn(ar->ab, "failed to set he mode vdev %i\n", +- arg.vdev_id); +- return ret; +- } +- } + } + + arg.channel.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2897,8 +2897,11 @@ struct rx_reorder_queue_remove_params { + #define HE_DL_MUOFDMA_ENABLE 1 + #define HE_UL_MUOFDMA_ENABLE 1 + #define HE_DL_MUMIMO_ENABLE 1 ++#define HE_UL_MUMIMO_ENABLE 1 + #define HE_MU_BFEE_ENABLE 1 + #define HE_SU_BFEE_ENABLE 1 ++#define HE_MU_BFER_ENABLE 1 ++#define HE_SU_BFER_ENABLE 1 + + #define HE_VHT_SOUNDING_MODE_ENABLE 1 + #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 diff --git a/package/kernel/mac80211/patches/ath11k/0040-wifi-ath11k-move-HE-MCS-mapper-to-a-separate-functio.patch b/package/kernel/mac80211/patches/ath11k/0040-wifi-ath11k-move-HE-MCS-mapper-to-a-separate-functio.patch new file mode 100644 index 000000000..6bc9880e1 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0040-wifi-ath11k-move-HE-MCS-mapper-to-a-separate-functio.patch @@ -0,0 +1,67 @@ +From 8077c1bbbc28e527fb29143c46f32c6a9d6cadf0 Mon Sep 17 00:00:00 2001 +From: Muna Sinada +Date: Fri, 24 Feb 2023 12:28:04 +0200 +Subject: [PATCH] wifi: ath11k: move HE MCS mapper to a separate function + +Move HE MCS mapper to a separate function and call new function +in ath11k_mac_copy_he_cap(). + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00356-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Muna Sinada +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/1666128501-12364-4-git-send-email-quic_msinada@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 34 +++++++++++++++++---------- + 1 file changed, 22 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -5483,6 +5483,27 @@ static __le16 ath11k_mac_setup_he_6ghz_c + return cpu_to_le16(bcap->he_6ghz_capa); + } + ++static void ath11k_mac_set_hemcsmap(struct ath11k *ar, ++ struct ath11k_pdev_cap *cap, ++ struct ieee80211_sta_he_cap *he_cap, ++ int band) ++{ ++ struct ath11k_band_cap *band_cap = &cap->band[band]; ++ ++ he_cap->he_mcs_nss_supp.rx_mcs_80 = ++ cpu_to_le16(band_cap->he_mcs & 0xffff); ++ he_cap->he_mcs_nss_supp.tx_mcs_80 = ++ cpu_to_le16(band_cap->he_mcs & 0xffff); ++ he_cap->he_mcs_nss_supp.rx_mcs_160 = ++ cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ he_cap->he_mcs_nss_supp.tx_mcs_160 = ++ cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ he_cap->he_mcs_nss_supp.rx_mcs_80p80 = ++ cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ he_cap->he_mcs_nss_supp.tx_mcs_80p80 = ++ cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++} ++ + static int ath11k_mac_copy_he_cap(struct ath11k *ar, + struct ath11k_pdev_cap *cap, + struct ieee80211_sband_iftype_data *data, +@@ -5544,18 +5565,7 @@ static int ath11k_mac_copy_he_cap(struct + break; + } + +- he_cap->he_mcs_nss_supp.rx_mcs_80 = +- cpu_to_le16(band_cap->he_mcs & 0xffff); +- he_cap->he_mcs_nss_supp.tx_mcs_80 = +- cpu_to_le16(band_cap->he_mcs & 0xffff); +- he_cap->he_mcs_nss_supp.rx_mcs_160 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- he_cap->he_mcs_nss_supp.tx_mcs_160 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- he_cap->he_mcs_nss_supp.rx_mcs_80p80 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- he_cap->he_mcs_nss_supp.tx_mcs_80p80 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ ath11k_mac_set_hemcsmap(ar, cap, he_cap, band); + + memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); + if (he_cap_elem->phy_cap_info[6] & diff --git a/package/kernel/mac80211/patches/ath11k/0041-wifi-ath11k-generate-rx-and-tx-mcs-maps-for-supporte.patch b/package/kernel/mac80211/patches/ath11k/0041-wifi-ath11k-generate-rx-and-tx-mcs-maps-for-supporte.patch new file mode 100644 index 000000000..5cb7801b2 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0041-wifi-ath11k-generate-rx-and-tx-mcs-maps-for-supporte.patch @@ -0,0 +1,64 @@ +From ebf82988f844dd98e6b007cffcc5e95986056995 Mon Sep 17 00:00:00 2001 +From: Muna Sinada +Date: Fri, 24 Feb 2023 12:28:04 +0200 +Subject: [PATCH] wifi: ath11k: generate rx and tx mcs maps for supported HE + mcs + +Generate rx and tx mcs maps in ath11k_mac_set_hemcsmap() and set them +in supported mcs/nss for HE capabilities. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00356-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Muna Sinada +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/1666128501-12364-5-git-send-email-quic_msinada@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 30 ++++++++++++++++++++------- + 1 file changed, 23 insertions(+), 7 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -5488,20 +5488,36 @@ static void ath11k_mac_set_hemcsmap(stru + struct ieee80211_sta_he_cap *he_cap, + int band) + { +- struct ath11k_band_cap *band_cap = &cap->band[band]; ++ u16 txmcs_map, rxmcs_map; ++ u32 i; + ++ rxmcs_map = 0; ++ txmcs_map = 0; ++ for (i = 0; i < 8; i++) { ++ if (i < ar->num_tx_chains && ++ (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) ++ txmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ txmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ ++ if (i < ar->num_rx_chains && ++ (ar->cfg_rx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) ++ rxmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ rxmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ } + he_cap->he_mcs_nss_supp.rx_mcs_80 = +- cpu_to_le16(band_cap->he_mcs & 0xffff); ++ cpu_to_le16(rxmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.tx_mcs_80 = +- cpu_to_le16(band_cap->he_mcs & 0xffff); ++ cpu_to_le16(txmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.rx_mcs_160 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ cpu_to_le16(rxmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.tx_mcs_160 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ cpu_to_le16(txmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.rx_mcs_80p80 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ cpu_to_le16(rxmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.tx_mcs_80p80 = +- cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ cpu_to_le16(txmcs_map & 0xffff); + } + + static int ath11k_mac_copy_he_cap(struct ath11k *ar, diff --git a/package/kernel/mac80211/patches/ath11k/0042-wifi-ath11k-Add-tx-ack-signal-support-for-management.patch b/package/kernel/mac80211/patches/ath11k/0042-wifi-ath11k-Add-tx-ack-signal-support-for-management.patch new file mode 100644 index 000000000..8d4165731 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0042-wifi-ath11k-Add-tx-ack-signal-support-for-management.patch @@ -0,0 +1,150 @@ +From 01c6c9fccbd51c1d9eab0f5794b0271b026178df Mon Sep 17 00:00:00 2001 +From: Abinaya Kalaiselvan +Date: Mon, 19 Dec 2022 11:08:44 +0530 +Subject: [PATCH] wifi: ath11k: Add tx ack signal support for management + packets + +Add support to notify tx ack signal values for management +packets to userspace through nl80211 interface. + +Advertise NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT flag +to enable this feature and it will be used for data +packets as well. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Abinaya Kalaiselvan +Signed-off-by: Maharaja Kennadyrajan +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20221219053844.4084486-1-quic_mkenna@quicinc.com +--- + drivers/net/wireless/ath/ath11k/hw.c | 1 + + drivers/net/wireless/ath/ath11k/mac.c | 5 +++++ + drivers/net/wireless/ath/ath11k/wmi.c | 27 ++++++++++++++++----------- + drivers/net/wireless/ath/ath11k/wmi.h | 3 +++ + 4 files changed, 25 insertions(+), 11 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -201,6 +201,7 @@ static void ath11k_init_wmi_config_ipq80 + config->twt_ap_pdev_count = ab->num_radios; + config->twt_ap_sta_count = 1000; + config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; ++ config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI; + } + + static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -9174,6 +9174,11 @@ static int __ath11k_mac_register(struct + goto err_free_if_combs; + } + ++ if (test_bit(WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI, ++ ar->ab->wmi_ab.svc_map)) ++ wiphy_ext_feature_set(ar->hw->wiphy, ++ NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); ++ + ar->hw->queues = ATH11K_HW_MAX_QUEUES; + ar->hw->wiphy->tx_queue_len = ATH11K_QUEUE_LEN; + ar->hw->offchannel_tx_hw_queue = ATH11K_HW_MAX_QUEUES - 1; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -5229,8 +5229,8 @@ static int ath11k_pull_mgmt_rx_params_tl + return 0; + } + +-static int wmi_process_mgmt_tx_comp(struct ath11k *ar, u32 desc_id, +- u32 status) ++static int wmi_process_mgmt_tx_comp(struct ath11k *ar, ++ struct wmi_mgmt_tx_compl_event *tx_compl_param) + { + struct sk_buff *msdu; + struct ieee80211_tx_info *info; +@@ -5238,24 +5238,29 @@ static int wmi_process_mgmt_tx_comp(stru + int num_mgmt; + + spin_lock_bh(&ar->txmgmt_idr_lock); +- msdu = idr_find(&ar->txmgmt_idr, desc_id); ++ msdu = idr_find(&ar->txmgmt_idr, tx_compl_param->desc_id); + + if (!msdu) { + ath11k_warn(ar->ab, "received mgmt tx compl for invalid msdu_id: %d\n", +- desc_id); ++ tx_compl_param->desc_id); + spin_unlock_bh(&ar->txmgmt_idr_lock); + return -ENOENT; + } + +- idr_remove(&ar->txmgmt_idr, desc_id); ++ idr_remove(&ar->txmgmt_idr, tx_compl_param->desc_id); + spin_unlock_bh(&ar->txmgmt_idr_lock); + + skb_cb = ATH11K_SKB_CB(msdu); + dma_unmap_single(ar->ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); + + info = IEEE80211_SKB_CB(msdu); +- if ((!(info->flags & IEEE80211_TX_CTL_NO_ACK)) && !status) ++ if ((!(info->flags & IEEE80211_TX_CTL_NO_ACK)) && ++ !tx_compl_param->status) { + info->flags |= IEEE80211_TX_STAT_ACK; ++ if (test_bit(WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI, ++ ar->ab->wmi_ab.svc_map)) ++ info->status.ack_signal = tx_compl_param->ack_rssi; ++ } + + ieee80211_tx_status_irqsafe(ar->hw, msdu); + +@@ -5267,7 +5272,7 @@ static int wmi_process_mgmt_tx_comp(stru + + ath11k_dbg(ar->ab, ATH11K_DBG_WMI, + "wmi mgmt tx comp pending %d desc id %d\n", +- num_mgmt, desc_id); ++ num_mgmt, tx_compl_param->desc_id); + + if (!num_mgmt) + wake_up(&ar->txmgmt_empty_waitq); +@@ -5300,6 +5305,7 @@ static int ath11k_pull_mgmt_tx_compl_par + param->pdev_id = ev->pdev_id; + param->desc_id = ev->desc_id; + param->status = ev->status; ++ param->ack_rssi = ev->ack_rssi; + + kfree(tb); + return 0; +@@ -7070,13 +7076,12 @@ static void ath11k_mgmt_tx_compl_event(s + goto exit; + } + +- wmi_process_mgmt_tx_comp(ar, tx_compl_param.desc_id, +- tx_compl_param.status); ++ wmi_process_mgmt_tx_comp(ar, &tx_compl_param); + + ath11k_dbg(ab, ATH11K_DBG_MGMT, +- "mgmt tx compl ev pdev_id %d, desc_id %d, status %d", ++ "mgmt tx compl ev pdev_id %d, desc_id %d, status %d ack_rssi %d", + tx_compl_param.pdev_id, tx_compl_param.desc_id, +- tx_compl_param.status); ++ tx_compl_param.status, tx_compl_param.ack_rssi); + + exit: + rcu_read_unlock(); +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2311,6 +2311,7 @@ struct wmi_init_cmd { + } __packed; + + #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) ++#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) + + struct wmi_resource_config { + u32 tlv_header; +@@ -4550,6 +4551,8 @@ struct wmi_mgmt_tx_compl_event { + u32 desc_id; + u32 status; + u32 pdev_id; ++ u32 ppdu_id; ++ u32 ack_rssi; + } __packed; + + struct wmi_scan_event { diff --git a/package/kernel/mac80211/patches/ath11k/0043-wifi-ath11k-use-proper-regulatory-reference-for-band.patch b/package/kernel/mac80211/patches/ath11k/0043-wifi-ath11k-use-proper-regulatory-reference-for-band.patch new file mode 100644 index 000000000..5bc195528 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0043-wifi-ath11k-use-proper-regulatory-reference-for-band.patch @@ -0,0 +1,216 @@ +From 25e289e1f52e1f4fb1d07622c6a24f8d8a8e420d Mon Sep 17 00:00:00 2001 +From: Aditya Kumar Singh +Date: Wed, 1 Mar 2023 16:20:58 +0200 +Subject: [PATCH] wifi: ath11k: use proper regulatory reference for bands + +Currently, during regulatory event, 2 GHz/5 GHz is referred +to as 2G/5G including variable names. However, there is no +such entity as 2G or 5G. + +Re-name such occurences to its proper name. No functional changes. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230110121024.14051-2-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/reg.c | 20 ++++----- + drivers/net/wireless/ath/ath11k/wmi.c | 58 ++++++++++++++------------- + drivers/net/wireless/ath/ath11k/wmi.h | 28 ++++++------- + 3 files changed, 54 insertions(+), 52 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/reg.c ++++ b/drivers/net/wireless/ath/ath11k/reg.c +@@ -619,7 +619,7 @@ ath11k_reg_build_regd(struct ath11k_base + u32 flags; + char alpha2[3]; + +- num_rules = reg_info->num_5g_reg_rules + reg_info->num_2g_reg_rules; ++ num_rules = reg_info->num_5ghz_reg_rules + reg_info->num_2ghz_reg_rules; + + if (!num_rules) + goto ret; +@@ -644,20 +644,20 @@ ath11k_reg_build_regd(struct ath11k_base + alpha2, ath11k_reg_get_regdom_str(tmp_regd->dfs_region), + reg_info->dfs_region, num_rules); + /* Update reg_rules[] below. Firmware is expected to +- * send these rules in order(2G rules first and then 5G) ++ * send these rules in order(2 GHz rules first and then 5 GHz) + */ + for (; i < num_rules; i++) { +- if (reg_info->num_2g_reg_rules && +- (i < reg_info->num_2g_reg_rules)) { +- reg_rule = reg_info->reg_rules_2g_ptr + i; ++ if (reg_info->num_2ghz_reg_rules && ++ (i < reg_info->num_2ghz_reg_rules)) { ++ reg_rule = reg_info->reg_rules_2ghz_ptr + i; + max_bw = min_t(u16, reg_rule->max_bw, +- reg_info->max_bw_2g); ++ reg_info->max_bw_2ghz); + flags = 0; +- } else if (reg_info->num_5g_reg_rules && +- (j < reg_info->num_5g_reg_rules)) { +- reg_rule = reg_info->reg_rules_5g_ptr + j++; ++ } else if (reg_info->num_5ghz_reg_rules && ++ (j < reg_info->num_5ghz_reg_rules)) { ++ reg_rule = reg_info->reg_rules_5ghz_ptr + j++; + max_bw = min_t(u16, reg_rule->max_bw, +- reg_info->max_bw_5g); ++ reg_info->max_bw_5ghz); + + /* FW doesn't pass NL80211_RRF_AUTO_BW flag for + * BW Auto correction, we can enable this by default +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -4959,7 +4959,7 @@ static int ath11k_pull_reg_chan_list_upd + const void **tb; + const struct wmi_reg_chan_list_cc_event *chan_list_event_hdr; + struct wmi_regulatory_rule_struct *wmi_reg_rule; +- u32 num_2g_reg_rules, num_5g_reg_rules; ++ u32 num_2ghz_reg_rules, num_5ghz_reg_rules; + int ret; + + ath11k_dbg(ab, ATH11K_DBG_WMI, "processing regulatory channel list\n"); +@@ -4978,10 +4978,10 @@ static int ath11k_pull_reg_chan_list_upd + return -EPROTO; + } + +- reg_info->num_2g_reg_rules = chan_list_event_hdr->num_2g_reg_rules; +- reg_info->num_5g_reg_rules = chan_list_event_hdr->num_5g_reg_rules; ++ reg_info->num_2ghz_reg_rules = chan_list_event_hdr->num_2ghz_reg_rules; ++ reg_info->num_5ghz_reg_rules = chan_list_event_hdr->num_5ghz_reg_rules; + +- if (!(reg_info->num_2g_reg_rules + reg_info->num_5g_reg_rules)) { ++ if (!(reg_info->num_2ghz_reg_rules + reg_info->num_5ghz_reg_rules)) { + ath11k_warn(ab, "No regulatory rules available in the event info\n"); + kfree(tb); + return -EINVAL; +@@ -5008,46 +5008,48 @@ static int ath11k_pull_reg_chan_list_upd + else if (chan_list_event_hdr->status_code == WMI_REG_SET_CC_STATUS_FAIL) + reg_info->status_code = REG_SET_CC_STATUS_FAIL; + +- reg_info->min_bw_2g = chan_list_event_hdr->min_bw_2g; +- reg_info->max_bw_2g = chan_list_event_hdr->max_bw_2g; +- reg_info->min_bw_5g = chan_list_event_hdr->min_bw_5g; +- reg_info->max_bw_5g = chan_list_event_hdr->max_bw_5g; ++ reg_info->min_bw_2ghz = chan_list_event_hdr->min_bw_2ghz; ++ reg_info->max_bw_2ghz = chan_list_event_hdr->max_bw_2ghz; ++ reg_info->min_bw_5ghz = chan_list_event_hdr->min_bw_5ghz; ++ reg_info->max_bw_5ghz = chan_list_event_hdr->max_bw_5ghz; + +- num_2g_reg_rules = reg_info->num_2g_reg_rules; +- num_5g_reg_rules = reg_info->num_5g_reg_rules; ++ num_2ghz_reg_rules = reg_info->num_2ghz_reg_rules; ++ num_5ghz_reg_rules = reg_info->num_5ghz_reg_rules; + + ath11k_dbg(ab, ATH11K_DBG_WMI, +- "%s:cc %s dsf %d BW: min_2g %d max_2g %d min_5g %d max_5g %d", ++ "%s:cc %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d", + __func__, reg_info->alpha2, reg_info->dfs_region, +- reg_info->min_bw_2g, reg_info->max_bw_2g, +- reg_info->min_bw_5g, reg_info->max_bw_5g); ++ reg_info->min_bw_2ghz, reg_info->max_bw_2ghz, ++ reg_info->min_bw_5ghz, reg_info->max_bw_5ghz); + + ath11k_dbg(ab, ATH11K_DBG_WMI, +- "%s: num_2g_reg_rules %d num_5g_reg_rules %d", __func__, +- num_2g_reg_rules, num_5g_reg_rules); ++ "%s: num_2ghz_reg_rules %d num_5ghz_reg_rules %d", __func__, ++ num_2ghz_reg_rules, num_5ghz_reg_rules); + + wmi_reg_rule = + (struct wmi_regulatory_rule_struct *)((u8 *)chan_list_event_hdr + + sizeof(*chan_list_event_hdr) + + sizeof(struct wmi_tlv)); + +- if (num_2g_reg_rules) { +- reg_info->reg_rules_2g_ptr = create_reg_rules_from_wmi(num_2g_reg_rules, +- wmi_reg_rule); +- if (!reg_info->reg_rules_2g_ptr) { ++ if (num_2ghz_reg_rules) { ++ reg_info->reg_rules_2ghz_ptr = ++ create_reg_rules_from_wmi(num_2ghz_reg_rules, ++ wmi_reg_rule); ++ if (!reg_info->reg_rules_2ghz_ptr) { + kfree(tb); +- ath11k_warn(ab, "Unable to Allocate memory for 2g rules\n"); ++ ath11k_warn(ab, "Unable to Allocate memory for 2 GHz rules\n"); + return -ENOMEM; + } + } + +- if (num_5g_reg_rules) { +- wmi_reg_rule += num_2g_reg_rules; +- reg_info->reg_rules_5g_ptr = create_reg_rules_from_wmi(num_5g_reg_rules, +- wmi_reg_rule); +- if (!reg_info->reg_rules_5g_ptr) { ++ if (num_5ghz_reg_rules) { ++ wmi_reg_rule += num_2ghz_reg_rules; ++ reg_info->reg_rules_5ghz_ptr = ++ create_reg_rules_from_wmi(num_5ghz_reg_rules, ++ wmi_reg_rule); ++ if (!reg_info->reg_rules_5ghz_ptr) { + kfree(tb); +- ath11k_warn(ab, "Unable to Allocate memory for 5g rules\n"); ++ ath11k_warn(ab, "Unable to Allocate memory for 5 GHz rules\n"); + return -ENOMEM; + } + } +@@ -6619,8 +6621,8 @@ fallback: + WARN_ON(1); + mem_free: + if (reg_info) { +- kfree(reg_info->reg_rules_2g_ptr); +- kfree(reg_info->reg_rules_5g_ptr); ++ kfree(reg_info->reg_rules_2ghz_ptr); ++ kfree(reg_info->reg_rules_5ghz_ptr); + kfree(reg_info); + } + return ret; +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -4129,14 +4129,14 @@ struct cur_regulatory_info { + u8 alpha2[REG_ALPHA2_LEN + 1]; + u32 dfs_region; + u32 phybitmap; +- u32 min_bw_2g; +- u32 max_bw_2g; +- u32 min_bw_5g; +- u32 max_bw_5g; +- u32 num_2g_reg_rules; +- u32 num_5g_reg_rules; +- struct cur_reg_rule *reg_rules_2g_ptr; +- struct cur_reg_rule *reg_rules_5g_ptr; ++ u32 min_bw_2ghz; ++ u32 max_bw_2ghz; ++ u32 min_bw_5ghz; ++ u32 max_bw_5ghz; ++ u32 num_2ghz_reg_rules; ++ u32 num_5ghz_reg_rules; ++ struct cur_reg_rule *reg_rules_2ghz_ptr; ++ struct cur_reg_rule *reg_rules_5ghz_ptr; + }; + + struct wmi_reg_chan_list_cc_event { +@@ -4148,12 +4148,12 @@ struct wmi_reg_chan_list_cc_event { + u32 domain_code; + u32 dfs_region; + u32 phybitmap; +- u32 min_bw_2g; +- u32 max_bw_2g; +- u32 min_bw_5g; +- u32 max_bw_5g; +- u32 num_2g_reg_rules; +- u32 num_5g_reg_rules; ++ u32 min_bw_2ghz; ++ u32 max_bw_2ghz; ++ u32 min_bw_5ghz; ++ u32 max_bw_5ghz; ++ u32 num_2ghz_reg_rules; ++ u32 num_5ghz_reg_rules; + } __packed; + + struct wmi_regulatory_rule_struct { diff --git a/package/kernel/mac80211/patches/ath11k/0044-wifi-ath11k-add-support-to-parse-new-WMI-event-for-6.patch b/package/kernel/mac80211/patches/ath11k/0044-wifi-ath11k-add-support-to-parse-new-WMI-event-for-6.patch new file mode 100644 index 000000000..e165c09dc --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0044-wifi-ath11k-add-support-to-parse-new-WMI-event-for-6.patch @@ -0,0 +1,844 @@ +From 91fa00fa69224aae5afb720c5e68b22e4c4f7333 Mon Sep 17 00:00:00 2001 +From: Aditya Kumar Singh +Date: Wed, 1 Mar 2023 16:20:59 +0200 +Subject: [PATCH] wifi: ath11k: add support to parse new WMI event for 6 GHz + +In order to support different power levels of 6 GHz AP and client, +new WMI event for regulatory - WMI_REG_CHAN_LIST_CC_EXT_EVENTID is +added in firmware. This event provides new parameters required for +6 GHz regulatory rules. + +Add support for parsing 2.4 GHz, 5 GHz and 6 GHz reg rules and other +parameters from WMI_REG_CHAN_LIST_CC_EXT_EVENTID. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Lavanya Suresh +Signed-off-by: Wen Gong +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230110121024.14051-3-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/reg.c | 37 ++- + drivers/net/wireless/ath/ath11k/wmi.c | 418 +++++++++++++++++++++++++- + drivers/net/wireless/ath/ath11k/wmi.h | 163 +++++++++- + 3 files changed, 584 insertions(+), 34 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/reg.c ++++ b/drivers/net/wireless/ath/ath11k/reg.c +@@ -613,7 +613,7 @@ ath11k_reg_build_regd(struct ath11k_base + { + struct ieee80211_regdomain *tmp_regd, *default_regd, *new_regd = NULL; + struct cur_reg_rule *reg_rule; +- u8 i = 0, j = 0; ++ u8 i = 0, j = 0, k = 0; + u8 num_rules; + u16 max_bw; + u32 flags; +@@ -621,6 +621,12 @@ ath11k_reg_build_regd(struct ath11k_base + + num_rules = reg_info->num_5ghz_reg_rules + reg_info->num_2ghz_reg_rules; + ++ /* FIXME: Currently taking reg rules for 6 GHz only from Indoor AP mode list. ++ * This can be updated after complete 6 GHz regulatory support is added. ++ */ ++ if (reg_info->is_ext_reg_event) ++ num_rules += reg_info->num_6ghz_rules_ap[WMI_REG_INDOOR_AP]; ++ + if (!num_rules) + goto ret; + +@@ -666,6 +672,14 @@ ath11k_reg_build_regd(struct ath11k_base + * per other BW rule flags we pass from here + */ + flags = NL80211_RRF_AUTO_BW; ++ } else if (reg_info->is_ext_reg_event && ++ reg_info->num_6ghz_rules_ap[WMI_REG_INDOOR_AP] && ++ (k < reg_info->num_6ghz_rules_ap[WMI_REG_INDOOR_AP])) { ++ reg_rule = reg_info->reg_rules_6ghz_ap_ptr[WMI_REG_INDOOR_AP] + ++ k++; ++ max_bw = min_t(u16, reg_rule->max_bw, ++ reg_info->max_bw_6ghz_ap[WMI_REG_INDOOR_AP]); ++ flags = NL80211_RRF_AUTO_BW; + } else { + break; + } +@@ -693,12 +707,21 @@ ath11k_reg_build_regd(struct ath11k_base + continue; + } + +- ath11k_dbg(ab, ATH11K_DBG_REG, +- "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n", +- i + 1, reg_rule->start_freq, reg_rule->end_freq, +- max_bw, reg_rule->ant_gain, reg_rule->reg_power, +- tmp_regd->reg_rules[i].dfs_cac_ms, +- flags); ++ if (reg_info->is_ext_reg_event) { ++ ath11k_dbg(ab, ATH11K_DBG_REG, ++ "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d) (%d, %d)\n", ++ i + 1, reg_rule->start_freq, reg_rule->end_freq, ++ max_bw, reg_rule->ant_gain, reg_rule->reg_power, ++ tmp_regd->reg_rules[i].dfs_cac_ms, flags, ++ reg_rule->psd_flag, reg_rule->psd_eirp); ++ } else { ++ ath11k_dbg(ab, ATH11K_DBG_REG, ++ "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n", ++ i + 1, reg_rule->start_freq, reg_rule->end_freq, ++ max_bw, reg_rule->ant_gain, reg_rule->reg_power, ++ tmp_regd->reg_rules[i].dfs_cac_ms, ++ flags); ++ } + } + + tmp_regd->n_reg_rules = i; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -105,6 +105,8 @@ static const struct wmi_tlv_policy wmi_t + = { .min_len = sizeof(struct wmi_vdev_stopped_event) }, + [WMI_TAG_REG_CHAN_LIST_CC_EVENT] + = { .min_len = sizeof(struct wmi_reg_chan_list_cc_event) }, ++ [WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT] ++ = { .min_len = sizeof(struct wmi_reg_chan_list_cc_ext_event) }, + [WMI_TAG_MGMT_RX_HDR] + = { .min_len = sizeof(struct wmi_mgmt_rx_hdr) }, + [WMI_TAG_MGMT_TX_COMPL_EVENT] +@@ -3974,6 +3976,10 @@ ath11k_wmi_copy_resource_config(struct w + wmi_cfg->sched_params = tg_cfg->sched_params; + wmi_cfg->twt_ap_pdev_count = tg_cfg->twt_ap_pdev_count; + wmi_cfg->twt_ap_sta_count = tg_cfg->twt_ap_sta_count; ++ wmi_cfg->host_service_flags &= ++ ~(1 << WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT); ++ wmi_cfg->host_service_flags |= (tg_cfg->is_reg_cc_ext_event_supported << ++ WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT); + } + + static int ath11k_init_cmd_send(struct ath11k_pdev_wmi *wmi, +@@ -4192,6 +4198,10 @@ int ath11k_wmi_cmd_init(struct ath11k_ba + + ab->hw_params.hw_ops->wmi_init_config(ab, &config); + ++ if (test_bit(WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT, ++ ab->wmi_ab.svc_map)) ++ config.is_reg_cc_ext_event_supported = 1; ++ + memcpy(&wmi_sc->wlan_resource_config, &config, sizeof(config)); + + init_param.res_cfg = &wmi_sc->wlan_resource_config; +@@ -4995,18 +5005,11 @@ static int ath11k_pull_reg_chan_list_upd + reg_info->phy_id = chan_list_event_hdr->phy_id; + reg_info->ctry_code = chan_list_event_hdr->country_id; + reg_info->reg_dmn_pair = chan_list_event_hdr->domain_code; +- if (chan_list_event_hdr->status_code == WMI_REG_SET_CC_STATUS_PASS) +- reg_info->status_code = REG_SET_CC_STATUS_PASS; +- else if (chan_list_event_hdr->status_code == WMI_REG_CURRENT_ALPHA2_NOT_FOUND) +- reg_info->status_code = REG_CURRENT_ALPHA2_NOT_FOUND; +- else if (chan_list_event_hdr->status_code == WMI_REG_INIT_ALPHA2_NOT_FOUND) +- reg_info->status_code = REG_INIT_ALPHA2_NOT_FOUND; +- else if (chan_list_event_hdr->status_code == WMI_REG_SET_CC_CHANGE_NOT_ALLOWED) +- reg_info->status_code = REG_SET_CC_CHANGE_NOT_ALLOWED; +- else if (chan_list_event_hdr->status_code == WMI_REG_SET_CC_STATUS_NO_MEMORY) +- reg_info->status_code = REG_SET_CC_STATUS_NO_MEMORY; +- else if (chan_list_event_hdr->status_code == WMI_REG_SET_CC_STATUS_FAIL) +- reg_info->status_code = REG_SET_CC_STATUS_FAIL; ++ ++ reg_info->status_code = ++ ath11k_wmi_cc_setting_code_to_reg(chan_list_event_hdr->status_code); ++ ++ reg_info->is_ext_reg_event = false; + + reg_info->min_bw_2ghz = chan_list_event_hdr->min_bw_2ghz; + reg_info->max_bw_2ghz = chan_list_event_hdr->max_bw_2ghz; +@@ -5060,6 +5063,372 @@ static int ath11k_pull_reg_chan_list_upd + return 0; + } + ++static struct cur_reg_rule ++*create_ext_reg_rules_from_wmi(u32 num_reg_rules, ++ struct wmi_regulatory_ext_rule *wmi_reg_rule) ++{ ++ struct cur_reg_rule *reg_rule_ptr; ++ u32 count; ++ ++ reg_rule_ptr = kcalloc(num_reg_rules, sizeof(*reg_rule_ptr), GFP_ATOMIC); ++ ++ if (!reg_rule_ptr) ++ return NULL; ++ ++ for (count = 0; count < num_reg_rules; count++) { ++ reg_rule_ptr[count].start_freq = ++ u32_get_bits(wmi_reg_rule[count].freq_info, ++ REG_RULE_START_FREQ); ++ reg_rule_ptr[count].end_freq = ++ u32_get_bits(wmi_reg_rule[count].freq_info, ++ REG_RULE_END_FREQ); ++ reg_rule_ptr[count].max_bw = ++ u32_get_bits(wmi_reg_rule[count].bw_pwr_info, ++ REG_RULE_MAX_BW); ++ reg_rule_ptr[count].reg_power = ++ u32_get_bits(wmi_reg_rule[count].bw_pwr_info, ++ REG_RULE_REG_PWR); ++ reg_rule_ptr[count].ant_gain = ++ u32_get_bits(wmi_reg_rule[count].bw_pwr_info, ++ REG_RULE_ANT_GAIN); ++ reg_rule_ptr[count].flags = ++ u32_get_bits(wmi_reg_rule[count].flag_info, ++ REG_RULE_FLAGS); ++ reg_rule_ptr[count].psd_flag = ++ u32_get_bits(wmi_reg_rule[count].psd_power_info, ++ REG_RULE_PSD_INFO); ++ reg_rule_ptr[count].psd_eirp = ++ u32_get_bits(wmi_reg_rule[count].psd_power_info, ++ REG_RULE_PSD_EIRP); ++ } ++ ++ return reg_rule_ptr; ++} ++ ++static u8 ++ath11k_invalid_5ghz_reg_ext_rules_from_wmi(u32 num_reg_rules, ++ const struct wmi_regulatory_ext_rule *rule) ++{ ++ u8 num_invalid_5ghz_rules = 0; ++ u32 count, start_freq; ++ ++ for (count = 0; count < num_reg_rules; count++) { ++ start_freq = u32_get_bits(rule[count].freq_info, ++ REG_RULE_START_FREQ); ++ ++ if (start_freq >= ATH11K_MIN_6G_FREQ) ++ num_invalid_5ghz_rules++; ++ } ++ ++ return num_invalid_5ghz_rules; ++} ++ ++static int ath11k_pull_reg_chan_list_ext_update_ev(struct ath11k_base *ab, ++ struct sk_buff *skb, ++ struct cur_regulatory_info *reg_info) ++{ ++ const void **tb; ++ const struct wmi_reg_chan_list_cc_ext_event *ext_chan_list_event_hdr; ++ struct wmi_regulatory_ext_rule *ext_wmi_reg_rule; ++ u32 num_2ghz_reg_rules, num_5ghz_reg_rules; ++ u32 num_6ghz_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; ++ u32 num_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; ++ u32 total_reg_rules = 0; ++ int ret, i, j, num_invalid_5ghz_ext_rules = 0; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, "processing regulatory ext channel list\n"); ++ ++ tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); ++ if (IS_ERR(tb)) { ++ ret = PTR_ERR(tb); ++ ath11k_warn(ab, "failed to parse tlv: %d\n", ret); ++ return ret; ++ } ++ ++ ext_chan_list_event_hdr = tb[WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT]; ++ if (!ext_chan_list_event_hdr) { ++ ath11k_warn(ab, "failed to fetch reg chan list ext update ev\n"); ++ kfree(tb); ++ return -EPROTO; ++ } ++ ++ reg_info->num_2ghz_reg_rules = ++ ext_chan_list_event_hdr->num_2ghz_reg_rules; ++ reg_info->num_5ghz_reg_rules = ++ ext_chan_list_event_hdr->num_5ghz_reg_rules; ++ reg_info->num_6ghz_rules_ap[WMI_REG_INDOOR_AP] = ++ ext_chan_list_event_hdr->num_6ghz_reg_rules_ap_lpi; ++ reg_info->num_6ghz_rules_ap[WMI_REG_STANDARD_POWER_AP] = ++ ext_chan_list_event_hdr->num_6ghz_reg_rules_ap_sp; ++ reg_info->num_6ghz_rules_ap[WMI_REG_VERY_LOW_POWER_AP] = ++ ext_chan_list_event_hdr->num_6ghz_reg_rules_ap_vlp; ++ ++ for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { ++ reg_info->num_6ghz_rules_client[WMI_REG_INDOOR_AP][i] = ++ ext_chan_list_event_hdr->num_6ghz_reg_rules_client_lpi[i]; ++ reg_info->num_6ghz_rules_client[WMI_REG_STANDARD_POWER_AP][i] = ++ ext_chan_list_event_hdr->num_6ghz_reg_rules_client_sp[i]; ++ reg_info->num_6ghz_rules_client[WMI_REG_VERY_LOW_POWER_AP][i] = ++ ext_chan_list_event_hdr->num_6ghz_reg_rules_client_vlp[i]; ++ } ++ ++ num_2ghz_reg_rules = reg_info->num_2ghz_reg_rules; ++ num_5ghz_reg_rules = reg_info->num_5ghz_reg_rules; ++ ++ total_reg_rules += num_2ghz_reg_rules; ++ total_reg_rules += num_5ghz_reg_rules; ++ ++ if ((num_2ghz_reg_rules > MAX_REG_RULES) || ++ (num_5ghz_reg_rules > MAX_REG_RULES)) { ++ ath11k_warn(ab, "Num reg rules for 2.4 GHz/5 GHz exceeds max limit (num_2ghz_reg_rules: %d num_5ghz_reg_rules: %d max_rules: %d)\n", ++ num_2ghz_reg_rules, num_5ghz_reg_rules, MAX_REG_RULES); ++ kfree(tb); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) { ++ num_6ghz_reg_rules_ap[i] = reg_info->num_6ghz_rules_ap[i]; ++ ++ if (num_6ghz_reg_rules_ap[i] > MAX_6GHZ_REG_RULES) { ++ ath11k_warn(ab, "Num 6 GHz reg rules for AP mode(%d) exceeds max limit (num_6ghz_reg_rules_ap: %d, max_rules: %d)\n", ++ i, num_6ghz_reg_rules_ap[i], MAX_6GHZ_REG_RULES); ++ kfree(tb); ++ return -EINVAL; ++ } ++ ++ total_reg_rules += num_6ghz_reg_rules_ap[i]; ++ } ++ ++ for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { ++ num_6ghz_client[WMI_REG_INDOOR_AP][i] = ++ reg_info->num_6ghz_rules_client[WMI_REG_INDOOR_AP][i]; ++ total_reg_rules += num_6ghz_client[WMI_REG_INDOOR_AP][i]; ++ ++ num_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = ++ reg_info->num_6ghz_rules_client[WMI_REG_STANDARD_POWER_AP][i]; ++ total_reg_rules += num_6ghz_client[WMI_REG_STANDARD_POWER_AP][i]; ++ ++ num_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = ++ reg_info->num_6ghz_rules_client[WMI_REG_VERY_LOW_POWER_AP][i]; ++ total_reg_rules += num_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i]; ++ ++ if ((num_6ghz_client[WMI_REG_INDOOR_AP][i] > MAX_6GHZ_REG_RULES) || ++ (num_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] > ++ MAX_6GHZ_REG_RULES) || ++ (num_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] > ++ MAX_6GHZ_REG_RULES)) { ++ ath11k_warn(ab, ++ "Num 6 GHz client reg rules exceeds max limit, for client(type: %d)\n", ++ i); ++ kfree(tb); ++ return -EINVAL; ++ } ++ } ++ ++ if (!total_reg_rules) { ++ ath11k_warn(ab, "No reg rules available\n"); ++ kfree(tb); ++ return -EINVAL; ++ } ++ ++ memcpy(reg_info->alpha2, &ext_chan_list_event_hdr->alpha2, ++ REG_ALPHA2_LEN); ++ ++ reg_info->dfs_region = ext_chan_list_event_hdr->dfs_region; ++ reg_info->phybitmap = ext_chan_list_event_hdr->phybitmap; ++ reg_info->num_phy = ext_chan_list_event_hdr->num_phy; ++ reg_info->phy_id = ext_chan_list_event_hdr->phy_id; ++ reg_info->ctry_code = ext_chan_list_event_hdr->country_id; ++ reg_info->reg_dmn_pair = ext_chan_list_event_hdr->domain_code; ++ ++ reg_info->status_code = ++ ath11k_wmi_cc_setting_code_to_reg(ext_chan_list_event_hdr->status_code); ++ ++ reg_info->is_ext_reg_event = true; ++ ++ reg_info->min_bw_2ghz = ext_chan_list_event_hdr->min_bw_2ghz; ++ reg_info->max_bw_2ghz = ext_chan_list_event_hdr->max_bw_2ghz; ++ reg_info->min_bw_5ghz = ext_chan_list_event_hdr->min_bw_5ghz; ++ reg_info->max_bw_5ghz = ext_chan_list_event_hdr->max_bw_5ghz; ++ ++ reg_info->min_bw_6ghz_ap[WMI_REG_INDOOR_AP] = ++ ext_chan_list_event_hdr->min_bw_6ghz_ap_lpi; ++ reg_info->max_bw_6ghz_ap[WMI_REG_INDOOR_AP] = ++ ext_chan_list_event_hdr->max_bw_6ghz_ap_lpi; ++ reg_info->min_bw_6ghz_ap[WMI_REG_STANDARD_POWER_AP] = ++ ext_chan_list_event_hdr->min_bw_6ghz_ap_sp; ++ reg_info->max_bw_6ghz_ap[WMI_REG_STANDARD_POWER_AP] = ++ ext_chan_list_event_hdr->max_bw_6ghz_ap_sp; ++ reg_info->min_bw_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP] = ++ ext_chan_list_event_hdr->min_bw_6ghz_ap_vlp; ++ reg_info->max_bw_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP] = ++ ext_chan_list_event_hdr->max_bw_6ghz_ap_vlp; ++ ++ for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { ++ reg_info->min_bw_6ghz_client[WMI_REG_INDOOR_AP][i] = ++ ext_chan_list_event_hdr->min_bw_6ghz_client_lpi[i]; ++ reg_info->max_bw_6ghz_client[WMI_REG_INDOOR_AP][i] = ++ ext_chan_list_event_hdr->max_bw_6ghz_client_lpi[i]; ++ reg_info->min_bw_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = ++ ext_chan_list_event_hdr->min_bw_6ghz_client_sp[i]; ++ reg_info->max_bw_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = ++ ext_chan_list_event_hdr->max_bw_6ghz_client_sp[i]; ++ reg_info->min_bw_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = ++ ext_chan_list_event_hdr->min_bw_6ghz_client_vlp[i]; ++ reg_info->max_bw_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = ++ ext_chan_list_event_hdr->max_bw_6ghz_client_vlp[i]; ++ } ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "%s:cc_ext %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d", ++ __func__, reg_info->alpha2, reg_info->dfs_region, ++ reg_info->min_bw_2ghz, reg_info->max_bw_2ghz, ++ reg_info->min_bw_5ghz, reg_info->max_bw_5ghz); ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "num_2ghz_reg_rules %d num_5ghz_reg_rules %d", ++ num_2ghz_reg_rules, num_5ghz_reg_rules); ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "num_6ghz_reg_rules_ap_lpi: %d num_6ghz_reg_rules_ap_sp: %d num_6ghz_reg_rules_ap_vlp: %d", ++ num_6ghz_reg_rules_ap[WMI_REG_INDOOR_AP], ++ num_6ghz_reg_rules_ap[WMI_REG_STANDARD_POWER_AP], ++ num_6ghz_reg_rules_ap[WMI_REG_VERY_LOW_POWER_AP]); ++ ++ j = WMI_REG_DEFAULT_CLIENT; ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz Regular client: num_6ghz_reg_rules_lpi: %d num_6ghz_reg_rules_sp: %d num_6ghz_reg_rules_vlp: %d", ++ num_6ghz_client[WMI_REG_INDOOR_AP][j], ++ num_6ghz_client[WMI_REG_STANDARD_POWER_AP][j], ++ num_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][j]); ++ ++ j = WMI_REG_SUBORDINATE_CLIENT; ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz Subordinate client: num_6ghz_reg_rules_lpi: %d num_6ghz_reg_rules_sp: %d num_6ghz_reg_rules_vlp: %d", ++ num_6ghz_client[WMI_REG_INDOOR_AP][j], ++ num_6ghz_client[WMI_REG_STANDARD_POWER_AP][j], ++ num_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][j]); ++ ++ ext_wmi_reg_rule = ++ (struct wmi_regulatory_ext_rule *)((u8 *)ext_chan_list_event_hdr ++ + sizeof(*ext_chan_list_event_hdr) ++ + sizeof(struct wmi_tlv)); ++ if (num_2ghz_reg_rules) { ++ reg_info->reg_rules_2ghz_ptr = ++ create_ext_reg_rules_from_wmi(num_2ghz_reg_rules, ++ ext_wmi_reg_rule); ++ ++ if (!reg_info->reg_rules_2ghz_ptr) { ++ kfree(tb); ++ ath11k_warn(ab, "Unable to Allocate memory for 2 GHz rules\n"); ++ return -ENOMEM; ++ } ++ } ++ ++ ext_wmi_reg_rule += num_2ghz_reg_rules; ++ ++ /* Firmware might include 6 GHz reg rule in 5 GHz rule list ++ * for few countries along with separate 6 GHz rule. ++ * Having same 6 GHz reg rule in 5 GHz and 6 GHz rules list ++ * causes intersect check to be true, and same rules will be ++ * shown multiple times in iw cmd. ++ * Hence, avoid parsing 6 GHz rule from 5 GHz reg rule list ++ */ ++ num_invalid_5ghz_ext_rules = ++ ath11k_invalid_5ghz_reg_ext_rules_from_wmi(num_5ghz_reg_rules, ++ ext_wmi_reg_rule); ++ ++ if (num_invalid_5ghz_ext_rules) { ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "CC: %s 5 GHz reg rules number %d from fw, %d number of invalid 5 GHz rules", ++ reg_info->alpha2, reg_info->num_5ghz_reg_rules, ++ num_invalid_5ghz_ext_rules); ++ ++ num_5ghz_reg_rules = num_5ghz_reg_rules - num_invalid_5ghz_ext_rules; ++ reg_info->num_5ghz_reg_rules = num_5ghz_reg_rules; ++ } ++ ++ if (num_5ghz_reg_rules) { ++ reg_info->reg_rules_5ghz_ptr = ++ create_ext_reg_rules_from_wmi(num_5ghz_reg_rules, ++ ext_wmi_reg_rule); ++ ++ if (!reg_info->reg_rules_5ghz_ptr) { ++ kfree(tb); ++ ath11k_warn(ab, "Unable to Allocate memory for 5 GHz rules\n"); ++ return -ENOMEM; ++ } ++ } ++ ++ /* We have adjusted the number of 5 GHz reg rules above. But still those ++ * many rules needs to be adjusted in ext_wmi_reg_rule. ++ * ++ * NOTE: num_invalid_5ghz_ext_rules will be 0 for rest other cases. ++ */ ++ ext_wmi_reg_rule += (num_5ghz_reg_rules + num_invalid_5ghz_ext_rules); ++ ++ for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) { ++ reg_info->reg_rules_6ghz_ap_ptr[i] = ++ create_ext_reg_rules_from_wmi(num_6ghz_reg_rules_ap[i], ++ ext_wmi_reg_rule); ++ ++ if (!reg_info->reg_rules_6ghz_ap_ptr[i]) { ++ kfree(tb); ++ ath11k_warn(ab, "Unable to Allocate memory for 6 GHz AP rules\n"); ++ return -ENOMEM; ++ } ++ ++ ext_wmi_reg_rule += num_6ghz_reg_rules_ap[i]; ++ } ++ ++ for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) { ++ for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { ++ reg_info->reg_rules_6ghz_client_ptr[j][i] = ++ create_ext_reg_rules_from_wmi(num_6ghz_client[j][i], ++ ext_wmi_reg_rule); ++ ++ if (!reg_info->reg_rules_6ghz_client_ptr[j][i]) { ++ kfree(tb); ++ ath11k_warn(ab, "Unable to Allocate memory for 6 GHz client rules\n"); ++ return -ENOMEM; ++ } ++ ++ ext_wmi_reg_rule += num_6ghz_client[j][i]; ++ } ++ } ++ ++ reg_info->client_type = ext_chan_list_event_hdr->client_type; ++ reg_info->rnr_tpe_usable = ext_chan_list_event_hdr->rnr_tpe_usable; ++ reg_info->unspecified_ap_usable = ++ ext_chan_list_event_hdr->unspecified_ap_usable; ++ reg_info->domain_code_6ghz_ap[WMI_REG_INDOOR_AP] = ++ ext_chan_list_event_hdr->domain_code_6ghz_ap_lpi; ++ reg_info->domain_code_6ghz_ap[WMI_REG_STANDARD_POWER_AP] = ++ ext_chan_list_event_hdr->domain_code_6ghz_ap_sp; ++ reg_info->domain_code_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP] = ++ ext_chan_list_event_hdr->domain_code_6ghz_ap_vlp; ++ ++ for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { ++ reg_info->domain_code_6ghz_client[WMI_REG_INDOOR_AP][i] = ++ ext_chan_list_event_hdr->domain_code_6ghz_client_lpi[i]; ++ reg_info->domain_code_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = ++ ext_chan_list_event_hdr->domain_code_6ghz_client_sp[i]; ++ reg_info->domain_code_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = ++ ext_chan_list_event_hdr->domain_code_6ghz_client_vlp[i]; ++ } ++ ++ reg_info->domain_code_6ghz_super_id = ++ ext_chan_list_event_hdr->domain_code_6ghz_super_id; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, "6 GHz client_type: %d domain_code_6ghz_super_id: %d", ++ reg_info->client_type, reg_info->domain_code_6ghz_super_id); ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, "processed regulatory ext channel list\n"); ++ ++ kfree(tb); ++ return 0; ++} ++ + static int ath11k_pull_peer_del_resp_ev(struct ath11k_base *ab, struct sk_buff *skb, + struct wmi_peer_delete_resp_event *peer_del_resp) + { +@@ -6507,12 +6876,14 @@ static bool ath11k_reg_is_world_alpha(ch + return false; + } + +-static int ath11k_reg_chan_list_event(struct ath11k_base *ab, struct sk_buff *skb) ++static int ath11k_reg_chan_list_event(struct ath11k_base *ab, ++ struct sk_buff *skb, ++ enum wmi_reg_chan_list_cmd_type id) + { + struct cur_regulatory_info *reg_info = NULL; + struct ieee80211_regdomain *regd = NULL; + bool intersect = false; +- int ret = 0, pdev_idx; ++ int ret = 0, pdev_idx, i, j; + struct ath11k *ar; + + reg_info = kzalloc(sizeof(*reg_info), GFP_ATOMIC); +@@ -6521,7 +6892,11 @@ static int ath11k_reg_chan_list_event(st + goto fallback; + } + +- ret = ath11k_pull_reg_chan_list_update_ev(ab, skb, reg_info); ++ if (id == WMI_REG_CHAN_LIST_CC_ID) ++ ret = ath11k_pull_reg_chan_list_update_ev(ab, skb, reg_info); ++ else ++ ret = ath11k_pull_reg_chan_list_ext_update_ev(ab, skb, reg_info); ++ + if (ret) { + ath11k_warn(ab, "failed to extract regulatory info from received event\n"); + goto fallback; +@@ -6623,6 +6998,14 @@ mem_free: + if (reg_info) { + kfree(reg_info->reg_rules_2ghz_ptr); + kfree(reg_info->reg_rules_5ghz_ptr); ++ if (reg_info->is_ext_reg_event) { ++ for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) ++ kfree(reg_info->reg_rules_6ghz_ap_ptr[i]); ++ ++ for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) ++ for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) ++ kfree(reg_info->reg_rules_6ghz_client_ptr[j][i]); ++ } + kfree(reg_info); + } + return ret; +@@ -8054,7 +8437,10 @@ static void ath11k_wmi_tlv_op_rx(struct + ath11k_service_ready_ext2_event(ab, skb); + break; + case WMI_REG_CHAN_LIST_CC_EVENTID: +- ath11k_reg_chan_list_event(ab, skb); ++ ath11k_reg_chan_list_event(ab, skb, WMI_REG_CHAN_LIST_CC_ID); ++ break; ++ case WMI_REG_CHAN_LIST_CC_EXT_EVENTID: ++ ath11k_reg_chan_list_event(ab, skb, WMI_REG_CHAN_LIST_CC_EXT_ID); + break; + case WMI_READY_EVENTID: + ath11k_ready_event(ab, skb); +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -797,6 +797,7 @@ enum wmi_tlv_event_id { + WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), + WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), + WMI_11D_NEW_COUNTRY_EVENTID, ++ WMI_REG_CHAN_LIST_CC_EXT_EVENTID, + WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), + WMI_NDP_INITIATOR_RSP_EVENTID, + WMI_NDP_RESPONDER_RSP_EVENTID, +@@ -1865,6 +1866,8 @@ enum wmi_tlv_tag { + WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, + WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, + WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, ++ WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, ++ WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, + WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, + WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, + WMI_TAG_MAX +@@ -2097,6 +2100,7 @@ enum wmi_tlv_service { + + /* The second 128 bits */ + WMI_MAX_EXT_SERVICE = 256, ++ WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, + WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, + + /* The third 128 bits */ +@@ -2313,6 +2317,8 @@ struct wmi_init_cmd { + #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) + #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) + ++#define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 ++ + struct wmi_resource_config { + u32 tlv_header; + u32 num_vdevs; +@@ -2372,6 +2378,15 @@ struct wmi_resource_config { + u32 sched_params; + u32 twt_ap_pdev_count; + u32 twt_ap_sta_count; ++ u32 max_nlo_ssids; ++ u32 num_pkt_filters; ++ u32 num_max_sta_vdevs; ++ u32 max_bssid_indicator; ++ u32 ul_resp_config; ++ u32 msdu_flow_override_config0; ++ u32 msdu_flow_override_config1; ++ u32 flags2; ++ u32 host_service_flags; + } __packed; + + struct wmi_service_ready_event { +@@ -2854,6 +2869,8 @@ struct rx_reorder_queue_remove_params { + #define REG_RULE_MAX_BW 0x0000ffff + #define REG_RULE_REG_PWR 0x00ff0000 + #define REG_RULE_ANT_GAIN 0xff000000 ++#define REG_RULE_PSD_INFO BIT(0) ++#define REG_RULE_PSD_EIRP 0xff0000 + + #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) + #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) +@@ -4049,6 +4066,7 @@ struct wmi_he_rate_set { + + #define MAX_REG_RULES 10 + #define REG_ALPHA2_LEN 2 ++#define MAX_6GHZ_REG_RULES 5 + + enum wmi_start_event_param { + WMI_VDEV_START_RESP_EVENT = 0, +@@ -4079,16 +4097,6 @@ enum wmi_vdev_start_resp_status_code { + WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, + }; + +-; +-enum cc_setting_code { +- REG_SET_CC_STATUS_PASS = 0, +- REG_CURRENT_ALPHA2_NOT_FOUND = 1, +- REG_INIT_ALPHA2_NOT_FOUND = 2, +- REG_SET_CC_CHANGE_NOT_ALLOWED = 3, +- REG_SET_CC_STATUS_NO_MEMORY = 4, +- REG_SET_CC_STATUS_FAIL = 5, +-}; +- + /* Regaulatory Rule Flags Passed by FW */ + #define REGULATORY_CHAN_DISABLED BIT(0) + #define REGULATORY_CHAN_NO_IR BIT(1) +@@ -4102,13 +4110,72 @@ enum cc_setting_code { + #define REGULATORY_CHAN_NO_20MHZ BIT(11) + #define REGULATORY_CHAN_NO_10MHZ BIT(12) + +-enum { ++enum wmi_reg_chan_list_cmd_type { ++ WMI_REG_CHAN_LIST_CC_ID = 0, ++ WMI_REG_CHAN_LIST_CC_EXT_ID = 1, ++}; ++ ++enum wmi_reg_cc_setting_code { + WMI_REG_SET_CC_STATUS_PASS = 0, + WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, + WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, + WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, + WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, + WMI_REG_SET_CC_STATUS_FAIL = 5, ++ ++ /* add new setting code above, update in ++ * @enum cc_setting_code as well. ++ * Also handle it in ath11k_wmi_cc_setting_code_to_reg() ++ */ ++}; ++ ++enum cc_setting_code { ++ REG_SET_CC_STATUS_PASS = 0, ++ REG_CURRENT_ALPHA2_NOT_FOUND = 1, ++ REG_INIT_ALPHA2_NOT_FOUND = 2, ++ REG_SET_CC_CHANGE_NOT_ALLOWED = 3, ++ REG_SET_CC_STATUS_NO_MEMORY = 4, ++ REG_SET_CC_STATUS_FAIL = 5, ++ ++ /* add new setting code above, update in ++ * @enum wmi_reg_cc_setting_code as well. ++ */ ++}; ++ ++static inline enum cc_setting_code ++ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code) ++{ ++ switch (status_code) { ++ case WMI_REG_SET_CC_STATUS_PASS: ++ return REG_SET_CC_STATUS_PASS; ++ case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: ++ return REG_CURRENT_ALPHA2_NOT_FOUND; ++ case WMI_REG_INIT_ALPHA2_NOT_FOUND: ++ return REG_INIT_ALPHA2_NOT_FOUND; ++ case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: ++ return REG_SET_CC_CHANGE_NOT_ALLOWED; ++ case WMI_REG_SET_CC_STATUS_NO_MEMORY: ++ return REG_SET_CC_STATUS_NO_MEMORY; ++ case WMI_REG_SET_CC_STATUS_FAIL: ++ return REG_SET_CC_STATUS_FAIL; ++ } ++ ++ return REG_SET_CC_STATUS_FAIL; ++} ++ ++enum wmi_reg_6ghz_ap_type { ++ WMI_REG_INDOOR_AP = 0, ++ WMI_REG_STANDARD_POWER_AP = 1, ++ WMI_REG_VERY_LOW_POWER_AP = 2, ++ ++ WMI_REG_CURRENT_MAX_AP_TYPE, ++ WMI_REG_MAX_AP_TYPE = 7, ++}; ++ ++enum wmi_reg_6ghz_client_type { ++ WMI_REG_DEFAULT_CLIENT = 0, ++ WMI_REG_SUBORDINATE_CLIENT = 1, ++ WMI_REG_MAX_CLIENT_TYPE = 2, + }; + + struct cur_reg_rule { +@@ -4118,6 +4185,8 @@ struct cur_reg_rule { + u8 reg_power; + u8 ant_gain; + u16 flags; ++ bool psd_flag; ++ s8 psd_eirp; + }; + + struct cur_regulatory_info { +@@ -4137,6 +4206,22 @@ struct cur_regulatory_info { + u32 num_5ghz_reg_rules; + struct cur_reg_rule *reg_rules_2ghz_ptr; + struct cur_reg_rule *reg_rules_5ghz_ptr; ++ bool is_ext_reg_event; ++ enum wmi_reg_6ghz_client_type client_type; ++ bool rnr_tpe_usable; ++ bool unspecified_ap_usable; ++ u8 domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; ++ u8 domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; ++ u32 domain_code_6ghz_super_id; ++ u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; ++ u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; ++ u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; ++ u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; ++ u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; ++ u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; ++ struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; ++ struct cur_reg_rule *reg_rules_6ghz_client_ptr ++ [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; + }; + + struct wmi_reg_chan_list_cc_event { +@@ -4163,6 +4248,61 @@ struct wmi_regulatory_rule_struct { + u32 flag_info; + }; + ++#define WMI_REG_CLIENT_MAX 4 ++ ++struct wmi_reg_chan_list_cc_ext_event { ++ u32 status_code; ++ u32 phy_id; ++ u32 alpha2; ++ u32 num_phy; ++ u32 country_id; ++ u32 domain_code; ++ u32 dfs_region; ++ u32 phybitmap; ++ u32 min_bw_2ghz; ++ u32 max_bw_2ghz; ++ u32 min_bw_5ghz; ++ u32 max_bw_5ghz; ++ u32 num_2ghz_reg_rules; ++ u32 num_5ghz_reg_rules; ++ u32 client_type; ++ u32 rnr_tpe_usable; ++ u32 unspecified_ap_usable; ++ u32 domain_code_6ghz_ap_lpi; ++ u32 domain_code_6ghz_ap_sp; ++ u32 domain_code_6ghz_ap_vlp; ++ u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; ++ u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX]; ++ u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; ++ u32 domain_code_6ghz_super_id; ++ u32 min_bw_6ghz_ap_sp; ++ u32 max_bw_6ghz_ap_sp; ++ u32 min_bw_6ghz_ap_lpi; ++ u32 max_bw_6ghz_ap_lpi; ++ u32 min_bw_6ghz_ap_vlp; ++ u32 max_bw_6ghz_ap_vlp; ++ u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; ++ u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; ++ u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; ++ u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; ++ u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; ++ u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; ++ u32 num_6ghz_reg_rules_ap_sp; ++ u32 num_6ghz_reg_rules_ap_lpi; ++ u32 num_6ghz_reg_rules_ap_vlp; ++ u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; ++ u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; ++ u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; ++} __packed; ++ ++struct wmi_regulatory_ext_rule { ++ u32 tlv_header; ++ u32 freq_info; ++ u32 bw_pwr_info; ++ u32 flag_info; ++ u32 psd_power_info; ++} __packed; ++ + struct wmi_vdev_delete_resp_event { + u32 vdev_id; + } __packed; +@@ -5358,6 +5498,7 @@ struct target_resource_config { + u32 sched_params; + u32 twt_ap_pdev_count; + u32 twt_ap_sta_count; ++ u8 is_reg_cc_ext_event_supported; + }; + + enum wmi_debug_log_param { diff --git a/package/kernel/mac80211/patches/ath11k/0045-wifi-ath11k-add-debug-prints-in-regulatory-WMI-event.patch b/package/kernel/mac80211/patches/ath11k/0045-wifi-ath11k-add-debug-prints-in-regulatory-WMI-event.patch new file mode 100644 index 000000000..b88e51928 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0045-wifi-ath11k-add-debug-prints-in-regulatory-WMI-event.patch @@ -0,0 +1,567 @@ +From e238e62ba8868a784e485eb94451c87cd1b85cee Mon Sep 17 00:00:00 2001 +From: Aditya Kumar Singh +Date: Wed, 1 Mar 2023 16:20:59 +0200 +Subject: [PATCH] wifi: ath11k: add debug prints in regulatory WMI event + processing + +Add some more debug prints in processing regulatory WMI event in order to +increase more debuggability. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230110121024.14051-4-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/reg.c | 2 +- + drivers/net/wireless/ath/ath11k/wmi.c | 207 ++++++++++++++++++-------- + drivers/net/wireless/ath/ath11k/wmi.h | 142 ++++++++++++++++++ + 3 files changed, 291 insertions(+), 60 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/reg.c ++++ b/drivers/net/wireless/ath/ath11k/reg.c +@@ -646,7 +646,7 @@ ath11k_reg_build_regd(struct ath11k_base + tmp_regd->dfs_region = ath11k_map_fw_dfs_region(reg_info->dfs_region); + + ath11k_dbg(ab, ATH11K_DBG_REG, +- "\r\nCountry %s, CFG Regdomain %s FW Regdomain %d, num_reg_rules %d\n", ++ "Country %s, CFG Regdomain %s FW Regdomain %d, num_reg_rules %d\n", + alpha2, ath11k_reg_get_regdom_str(tmp_regd->dfs_region), + reg_info->dfs_region, num_rules); + /* Update reg_rules[] below. Firmware is expected to +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -4925,6 +4925,26 @@ static int ath11k_pull_vdev_start_resp_t + return 0; + } + ++static void ath11k_print_reg_rule(struct ath11k_base *ab, const char *band, ++ u32 num_reg_rules, ++ struct cur_reg_rule *reg_rule_ptr) ++{ ++ struct cur_reg_rule *reg_rule = reg_rule_ptr; ++ u32 count; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, "number of reg rules in %s band: %d\n", ++ band, num_reg_rules); ++ ++ for (count = 0; count < num_reg_rules; count++) { ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "reg rule %d: (%d - %d @ %d) (%d, %d) (FLAGS %d)\n", ++ count + 1, reg_rule->start_freq, reg_rule->end_freq, ++ reg_rule->max_bw, reg_rule->ant_gain, ++ reg_rule->reg_power, reg_rule->flags); ++ reg_rule++; ++ } ++} ++ + static struct cur_reg_rule + *create_reg_rules_from_wmi(u32 num_reg_rules, + struct wmi_regulatory_rule_struct *wmi_reg_rule) +@@ -5006,6 +5026,10 @@ static int ath11k_pull_reg_chan_list_upd + reg_info->ctry_code = chan_list_event_hdr->country_id; + reg_info->reg_dmn_pair = chan_list_event_hdr->domain_code; + ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "status_code %s", ++ ath11k_cc_status_to_str(reg_info->status_code)); ++ + reg_info->status_code = + ath11k_wmi_cc_setting_code_to_reg(chan_list_event_hdr->status_code); + +@@ -5020,13 +5044,13 @@ static int ath11k_pull_reg_chan_list_upd + num_5ghz_reg_rules = reg_info->num_5ghz_reg_rules; + + ath11k_dbg(ab, ATH11K_DBG_WMI, +- "%s:cc %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d", +- __func__, reg_info->alpha2, reg_info->dfs_region, ++ "cc %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d", ++ reg_info->alpha2, reg_info->dfs_region, + reg_info->min_bw_2ghz, reg_info->max_bw_2ghz, + reg_info->min_bw_5ghz, reg_info->max_bw_5ghz); + + ath11k_dbg(ab, ATH11K_DBG_WMI, +- "%s: num_2ghz_reg_rules %d num_5ghz_reg_rules %d", __func__, ++ "num_2ghz_reg_rules %d num_5ghz_reg_rules %d", + num_2ghz_reg_rules, num_5ghz_reg_rules); + + wmi_reg_rule = +@@ -5043,6 +5067,10 @@ static int ath11k_pull_reg_chan_list_upd + ath11k_warn(ab, "Unable to Allocate memory for 2 GHz rules\n"); + return -ENOMEM; + } ++ ++ ath11k_print_reg_rule(ab, "2 GHz", ++ num_2ghz_reg_rules, ++ reg_info->reg_rules_2ghz_ptr); + } + + if (num_5ghz_reg_rules) { +@@ -5055,6 +5083,10 @@ static int ath11k_pull_reg_chan_list_upd + ath11k_warn(ab, "Unable to Allocate memory for 5 GHz rules\n"); + return -ENOMEM; + } ++ ++ ath11k_print_reg_rule(ab, "5 GHz", ++ num_5ghz_reg_rules, ++ reg_info->reg_rules_5ghz_ptr); + } + + ath11k_dbg(ab, ATH11K_DBG_WMI, "processed regulatory channel list\n"); +@@ -5128,7 +5160,7 @@ static int ath11k_pull_reg_chan_list_ext + struct cur_regulatory_info *reg_info) + { + const void **tb; +- const struct wmi_reg_chan_list_cc_ext_event *ext_chan_list_event_hdr; ++ const struct wmi_reg_chan_list_cc_ext_event *ev; + struct wmi_regulatory_ext_rule *ext_wmi_reg_rule; + u32 num_2ghz_reg_rules, num_5ghz_reg_rules; + u32 num_6ghz_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; +@@ -5145,31 +5177,29 @@ static int ath11k_pull_reg_chan_list_ext + return ret; + } + +- ext_chan_list_event_hdr = tb[WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT]; +- if (!ext_chan_list_event_hdr) { ++ ev = tb[WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT]; ++ if (!ev) { + ath11k_warn(ab, "failed to fetch reg chan list ext update ev\n"); + kfree(tb); + return -EPROTO; + } + +- reg_info->num_2ghz_reg_rules = +- ext_chan_list_event_hdr->num_2ghz_reg_rules; +- reg_info->num_5ghz_reg_rules = +- ext_chan_list_event_hdr->num_5ghz_reg_rules; ++ reg_info->num_2ghz_reg_rules = ev->num_2ghz_reg_rules; ++ reg_info->num_5ghz_reg_rules = ev->num_5ghz_reg_rules; + reg_info->num_6ghz_rules_ap[WMI_REG_INDOOR_AP] = +- ext_chan_list_event_hdr->num_6ghz_reg_rules_ap_lpi; ++ ev->num_6ghz_reg_rules_ap_lpi; + reg_info->num_6ghz_rules_ap[WMI_REG_STANDARD_POWER_AP] = +- ext_chan_list_event_hdr->num_6ghz_reg_rules_ap_sp; ++ ev->num_6ghz_reg_rules_ap_sp; + reg_info->num_6ghz_rules_ap[WMI_REG_VERY_LOW_POWER_AP] = +- ext_chan_list_event_hdr->num_6ghz_reg_rules_ap_vlp; ++ ev->num_6ghz_reg_rules_ap_vlp; + + for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { + reg_info->num_6ghz_rules_client[WMI_REG_INDOOR_AP][i] = +- ext_chan_list_event_hdr->num_6ghz_reg_rules_client_lpi[i]; ++ ev->num_6ghz_reg_rules_client_lpi[i]; + reg_info->num_6ghz_rules_client[WMI_REG_STANDARD_POWER_AP][i] = +- ext_chan_list_event_hdr->num_6ghz_reg_rules_client_sp[i]; ++ ev->num_6ghz_reg_rules_client_sp[i]; + reg_info->num_6ghz_rules_client[WMI_REG_VERY_LOW_POWER_AP][i] = +- ext_chan_list_event_hdr->num_6ghz_reg_rules_client_vlp[i]; ++ ev->num_6ghz_reg_rules_client_vlp[i]; + } + + num_2ghz_reg_rules = reg_info->num_2ghz_reg_rules; +@@ -5231,57 +5261,79 @@ static int ath11k_pull_reg_chan_list_ext + return -EINVAL; + } + +- memcpy(reg_info->alpha2, &ext_chan_list_event_hdr->alpha2, +- REG_ALPHA2_LEN); ++ memcpy(reg_info->alpha2, &ev->alpha2, REG_ALPHA2_LEN); ++ ++ reg_info->dfs_region = ev->dfs_region; ++ reg_info->phybitmap = ev->phybitmap; ++ reg_info->num_phy = ev->num_phy; ++ reg_info->phy_id = ev->phy_id; ++ reg_info->ctry_code = ev->country_id; ++ reg_info->reg_dmn_pair = ev->domain_code; + +- reg_info->dfs_region = ext_chan_list_event_hdr->dfs_region; +- reg_info->phybitmap = ext_chan_list_event_hdr->phybitmap; +- reg_info->num_phy = ext_chan_list_event_hdr->num_phy; +- reg_info->phy_id = ext_chan_list_event_hdr->phy_id; +- reg_info->ctry_code = ext_chan_list_event_hdr->country_id; +- reg_info->reg_dmn_pair = ext_chan_list_event_hdr->domain_code; ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "status_code %s", ++ ath11k_cc_status_to_str(reg_info->status_code)); + + reg_info->status_code = +- ath11k_wmi_cc_setting_code_to_reg(ext_chan_list_event_hdr->status_code); ++ ath11k_wmi_cc_setting_code_to_reg(ev->status_code); + + reg_info->is_ext_reg_event = true; + +- reg_info->min_bw_2ghz = ext_chan_list_event_hdr->min_bw_2ghz; +- reg_info->max_bw_2ghz = ext_chan_list_event_hdr->max_bw_2ghz; +- reg_info->min_bw_5ghz = ext_chan_list_event_hdr->min_bw_5ghz; +- reg_info->max_bw_5ghz = ext_chan_list_event_hdr->max_bw_5ghz; ++ reg_info->min_bw_2ghz = ev->min_bw_2ghz; ++ reg_info->max_bw_2ghz = ev->max_bw_2ghz; ++ reg_info->min_bw_5ghz = ev->min_bw_5ghz; ++ reg_info->max_bw_5ghz = ev->max_bw_5ghz; + + reg_info->min_bw_6ghz_ap[WMI_REG_INDOOR_AP] = +- ext_chan_list_event_hdr->min_bw_6ghz_ap_lpi; ++ ev->min_bw_6ghz_ap_lpi; + reg_info->max_bw_6ghz_ap[WMI_REG_INDOOR_AP] = +- ext_chan_list_event_hdr->max_bw_6ghz_ap_lpi; ++ ev->max_bw_6ghz_ap_lpi; + reg_info->min_bw_6ghz_ap[WMI_REG_STANDARD_POWER_AP] = +- ext_chan_list_event_hdr->min_bw_6ghz_ap_sp; ++ ev->min_bw_6ghz_ap_sp; + reg_info->max_bw_6ghz_ap[WMI_REG_STANDARD_POWER_AP] = +- ext_chan_list_event_hdr->max_bw_6ghz_ap_sp; ++ ev->max_bw_6ghz_ap_sp; + reg_info->min_bw_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP] = +- ext_chan_list_event_hdr->min_bw_6ghz_ap_vlp; ++ ev->min_bw_6ghz_ap_vlp; + reg_info->max_bw_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP] = +- ext_chan_list_event_hdr->max_bw_6ghz_ap_vlp; ++ ev->max_bw_6ghz_ap_vlp; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz AP BW: LPI (%d - %d), SP (%d - %d), VLP (%d - %d)\n", ++ reg_info->min_bw_6ghz_ap[WMI_REG_INDOOR_AP], ++ reg_info->max_bw_6ghz_ap[WMI_REG_INDOOR_AP], ++ reg_info->min_bw_6ghz_ap[WMI_REG_STANDARD_POWER_AP], ++ reg_info->max_bw_6ghz_ap[WMI_REG_STANDARD_POWER_AP], ++ reg_info->min_bw_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP], ++ reg_info->max_bw_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP]); + + for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { + reg_info->min_bw_6ghz_client[WMI_REG_INDOOR_AP][i] = +- ext_chan_list_event_hdr->min_bw_6ghz_client_lpi[i]; ++ ev->min_bw_6ghz_client_lpi[i]; + reg_info->max_bw_6ghz_client[WMI_REG_INDOOR_AP][i] = +- ext_chan_list_event_hdr->max_bw_6ghz_client_lpi[i]; ++ ev->max_bw_6ghz_client_lpi[i]; + reg_info->min_bw_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = +- ext_chan_list_event_hdr->min_bw_6ghz_client_sp[i]; ++ ev->min_bw_6ghz_client_sp[i]; + reg_info->max_bw_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = +- ext_chan_list_event_hdr->max_bw_6ghz_client_sp[i]; ++ ev->max_bw_6ghz_client_sp[i]; + reg_info->min_bw_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = +- ext_chan_list_event_hdr->min_bw_6ghz_client_vlp[i]; ++ ev->min_bw_6ghz_client_vlp[i]; + reg_info->max_bw_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = +- ext_chan_list_event_hdr->max_bw_6ghz_client_vlp[i]; ++ ev->max_bw_6ghz_client_vlp[i]; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz %s BW: LPI (%d - %d), SP (%d - %d), VLP (%d - %d)\n", ++ ath11k_6ghz_client_type_to_str(i), ++ reg_info->min_bw_6ghz_client[WMI_REG_INDOOR_AP][i], ++ reg_info->max_bw_6ghz_client[WMI_REG_INDOOR_AP][i], ++ reg_info->min_bw_6ghz_client[WMI_REG_STANDARD_POWER_AP][i], ++ reg_info->max_bw_6ghz_client[WMI_REG_STANDARD_POWER_AP][i], ++ reg_info->min_bw_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i], ++ reg_info->max_bw_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i]); + } + + ath11k_dbg(ab, ATH11K_DBG_WMI, +- "%s:cc_ext %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d", +- __func__, reg_info->alpha2, reg_info->dfs_region, ++ "cc_ext %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d", ++ reg_info->alpha2, reg_info->dfs_region, + reg_info->min_bw_2ghz, reg_info->max_bw_2ghz, + reg_info->min_bw_5ghz, reg_info->max_bw_5ghz); + +@@ -5310,9 +5362,8 @@ static int ath11k_pull_reg_chan_list_ext + num_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][j]); + + ext_wmi_reg_rule = +- (struct wmi_regulatory_ext_rule *)((u8 *)ext_chan_list_event_hdr +- + sizeof(*ext_chan_list_event_hdr) +- + sizeof(struct wmi_tlv)); ++ (struct wmi_regulatory_ext_rule *)((u8 *)ev + sizeof(*ev) + ++ sizeof(struct wmi_tlv)); + if (num_2ghz_reg_rules) { + reg_info->reg_rules_2ghz_ptr = + create_ext_reg_rules_from_wmi(num_2ghz_reg_rules, +@@ -5323,6 +5374,10 @@ static int ath11k_pull_reg_chan_list_ext + ath11k_warn(ab, "Unable to Allocate memory for 2 GHz rules\n"); + return -ENOMEM; + } ++ ++ ath11k_print_reg_rule(ab, "2 GHz", ++ num_2ghz_reg_rules, ++ reg_info->reg_rules_2ghz_ptr); + } + + ext_wmi_reg_rule += num_2ghz_reg_rules; +@@ -5358,6 +5413,10 @@ static int ath11k_pull_reg_chan_list_ext + ath11k_warn(ab, "Unable to Allocate memory for 5 GHz rules\n"); + return -ENOMEM; + } ++ ++ ath11k_print_reg_rule(ab, "5 GHz", ++ num_5ghz_reg_rules, ++ reg_info->reg_rules_5ghz_ptr); + } + + /* We have adjusted the number of 5 GHz reg rules above. But still those +@@ -5378,10 +5437,17 @@ static int ath11k_pull_reg_chan_list_ext + return -ENOMEM; + } + ++ ath11k_print_reg_rule(ab, ath11k_6ghz_ap_type_to_str(i), ++ num_6ghz_reg_rules_ap[i], ++ reg_info->reg_rules_6ghz_ap_ptr[i]); ++ + ext_wmi_reg_rule += num_6ghz_reg_rules_ap[i]; + } + + for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) { ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz AP type %s", ath11k_6ghz_ap_type_to_str(j)); ++ + for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { + reg_info->reg_rules_6ghz_client_ptr[j][i] = + create_ext_reg_rules_from_wmi(num_6ghz_client[j][i], +@@ -5393,35 +5459,58 @@ static int ath11k_pull_reg_chan_list_ext + return -ENOMEM; + } + ++ ath11k_print_reg_rule(ab, ++ ath11k_6ghz_client_type_to_str(i), ++ num_6ghz_client[j][i], ++ reg_info->reg_rules_6ghz_client_ptr[j][i]); ++ + ext_wmi_reg_rule += num_6ghz_client[j][i]; + } + } + +- reg_info->client_type = ext_chan_list_event_hdr->client_type; +- reg_info->rnr_tpe_usable = ext_chan_list_event_hdr->rnr_tpe_usable; ++ reg_info->client_type = ev->client_type; ++ reg_info->rnr_tpe_usable = ev->rnr_tpe_usable; + reg_info->unspecified_ap_usable = +- ext_chan_list_event_hdr->unspecified_ap_usable; ++ ev->unspecified_ap_usable; + reg_info->domain_code_6ghz_ap[WMI_REG_INDOOR_AP] = +- ext_chan_list_event_hdr->domain_code_6ghz_ap_lpi; ++ ev->domain_code_6ghz_ap_lpi; + reg_info->domain_code_6ghz_ap[WMI_REG_STANDARD_POWER_AP] = +- ext_chan_list_event_hdr->domain_code_6ghz_ap_sp; ++ ev->domain_code_6ghz_ap_sp; + reg_info->domain_code_6ghz_ap[WMI_REG_VERY_LOW_POWER_AP] = +- ext_chan_list_event_hdr->domain_code_6ghz_ap_vlp; ++ ev->domain_code_6ghz_ap_vlp; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz reg info client type %s rnr_tpe_usable %d unspecified_ap_usable %d AP sub domain: lpi %s, sp %s, vlp %s\n", ++ ath11k_6ghz_client_type_to_str(reg_info->client_type), ++ reg_info->rnr_tpe_usable, ++ reg_info->unspecified_ap_usable, ++ ath11k_sub_reg_6ghz_to_str(ev->domain_code_6ghz_ap_lpi), ++ ath11k_sub_reg_6ghz_to_str(ev->domain_code_6ghz_ap_sp), ++ ath11k_sub_reg_6ghz_to_str(ev->domain_code_6ghz_ap_vlp)); + + for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { + reg_info->domain_code_6ghz_client[WMI_REG_INDOOR_AP][i] = +- ext_chan_list_event_hdr->domain_code_6ghz_client_lpi[i]; ++ ev->domain_code_6ghz_client_lpi[i]; + reg_info->domain_code_6ghz_client[WMI_REG_STANDARD_POWER_AP][i] = +- ext_chan_list_event_hdr->domain_code_6ghz_client_sp[i]; ++ ev->domain_code_6ghz_client_sp[i]; + reg_info->domain_code_6ghz_client[WMI_REG_VERY_LOW_POWER_AP][i] = +- ext_chan_list_event_hdr->domain_code_6ghz_client_vlp[i]; ++ ev->domain_code_6ghz_client_vlp[i]; ++ ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz client type %s client sub domain: lpi %s, sp %s, vlp %s\n", ++ ath11k_6ghz_client_type_to_str(i), ++ ath11k_sub_reg_6ghz_to_str(ev->domain_code_6ghz_client_lpi[i]), ++ ath11k_sub_reg_6ghz_to_str(ev->domain_code_6ghz_client_sp[i]), ++ ath11k_sub_reg_6ghz_to_str(ev->domain_code_6ghz_client_vlp[i]) ++ ); + } + +- reg_info->domain_code_6ghz_super_id = +- ext_chan_list_event_hdr->domain_code_6ghz_super_id; ++ reg_info->domain_code_6ghz_super_id = ev->domain_code_6ghz_super_id; + +- ath11k_dbg(ab, ATH11K_DBG_WMI, "6 GHz client_type: %d domain_code_6ghz_super_id: %d", +- reg_info->client_type, reg_info->domain_code_6ghz_super_id); ++ ath11k_dbg(ab, ATH11K_DBG_WMI, ++ "6 GHz client_type %s 6 GHz super domain %s", ++ ath11k_6ghz_client_type_to_str(reg_info->client_type), ++ ath11k_super_reg_6ghz_to_str(reg_info->domain_code_6ghz_super_id)); + + ath11k_dbg(ab, ATH11K_DBG_WMI, "processed regulatory ext channel list\n"); + +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -4139,6 +4139,7 @@ enum cc_setting_code { + + /* add new setting code above, update in + * @enum wmi_reg_cc_setting_code as well. ++ * Also handle it in ath11k_cc_status_to_str() + */ + }; + +@@ -4163,21 +4164,162 @@ ath11k_wmi_cc_setting_code_to_reg(enum w + return REG_SET_CC_STATUS_FAIL; + } + ++static inline const char *ath11k_cc_status_to_str(enum cc_setting_code code) ++{ ++ switch (code) { ++ case REG_SET_CC_STATUS_PASS: ++ return "REG_SET_CC_STATUS_PASS"; ++ case REG_CURRENT_ALPHA2_NOT_FOUND: ++ return "REG_CURRENT_ALPHA2_NOT_FOUND"; ++ case REG_INIT_ALPHA2_NOT_FOUND: ++ return "REG_INIT_ALPHA2_NOT_FOUND"; ++ case REG_SET_CC_CHANGE_NOT_ALLOWED: ++ return "REG_SET_CC_CHANGE_NOT_ALLOWED"; ++ case REG_SET_CC_STATUS_NO_MEMORY: ++ return "REG_SET_CC_STATUS_NO_MEMORY"; ++ case REG_SET_CC_STATUS_FAIL: ++ return "REG_SET_CC_STATUS_FAIL"; ++ } ++ ++ return "Unknown CC status"; ++} ++ + enum wmi_reg_6ghz_ap_type { + WMI_REG_INDOOR_AP = 0, + WMI_REG_STANDARD_POWER_AP = 1, + WMI_REG_VERY_LOW_POWER_AP = 2, + ++ /* add AP type above, handle in ath11k_6ghz_ap_type_to_str() ++ */ + WMI_REG_CURRENT_MAX_AP_TYPE, + WMI_REG_MAX_AP_TYPE = 7, + }; + ++static inline const char * ++ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type) ++{ ++ switch (type) { ++ case WMI_REG_INDOOR_AP: ++ return "INDOOR AP"; ++ case WMI_REG_STANDARD_POWER_AP: ++ return "STANDARD POWER AP"; ++ case WMI_REG_VERY_LOW_POWER_AP: ++ return "VERY LOW POWER AP"; ++ case WMI_REG_CURRENT_MAX_AP_TYPE: ++ return "CURRENT_MAX_AP_TYPE"; ++ case WMI_REG_MAX_AP_TYPE: ++ return "MAX_AP_TYPE"; ++ } ++ ++ return "unknown 6 GHz AP type"; ++} ++ + enum wmi_reg_6ghz_client_type { + WMI_REG_DEFAULT_CLIENT = 0, + WMI_REG_SUBORDINATE_CLIENT = 1, + WMI_REG_MAX_CLIENT_TYPE = 2, ++ ++ /* add client type above, handle it in ++ * ath11k_6ghz_client_type_to_str() ++ */ ++}; ++ ++static inline const char * ++ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type) ++{ ++ switch (type) { ++ case WMI_REG_DEFAULT_CLIENT: ++ return "DEFAULT CLIENT"; ++ case WMI_REG_SUBORDINATE_CLIENT: ++ return "SUBORDINATE CLIENT"; ++ case WMI_REG_MAX_CLIENT_TYPE: ++ return "MAX_CLIENT_TYPE"; ++ } ++ ++ return "unknown 6 GHz client type"; ++} ++ ++enum reg_subdomains_6ghz { ++ EMPTY_6GHZ = 0x0, ++ FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01, ++ FCC1_CLIENT_SP_6GHZ = 0x02, ++ FCC1_AP_LPI_6GHZ = 0x03, ++ FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ, ++ FCC1_AP_SP_6GHZ = 0x04, ++ ETSI1_LPI_6GHZ = 0x10, ++ ETSI1_VLP_6GHZ = 0x11, ++ ETSI2_LPI_6GHZ = 0x12, ++ ETSI2_VLP_6GHZ = 0x13, ++ APL1_LPI_6GHZ = 0x20, ++ APL1_VLP_6GHZ = 0x21, ++ ++ /* add sub-domain above, handle it in ++ * ath11k_sub_reg_6ghz_to_str() ++ */ ++}; ++ ++static inline const char * ++ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id) ++{ ++ switch (sub_id) { ++ case EMPTY_6GHZ: ++ return "N/A"; ++ case FCC1_CLIENT_LPI_REGULAR_6GHZ: ++ return "FCC1_CLIENT_LPI_REGULAR_6GHZ"; ++ case FCC1_CLIENT_SP_6GHZ: ++ return "FCC1_CLIENT_SP_6GHZ"; ++ case FCC1_AP_LPI_6GHZ: ++ return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE"; ++ case FCC1_AP_SP_6GHZ: ++ return "FCC1_AP_SP_6GHZ"; ++ case ETSI1_LPI_6GHZ: ++ return "ETSI1_LPI_6GHZ"; ++ case ETSI1_VLP_6GHZ: ++ return "ETSI1_VLP_6GHZ"; ++ case ETSI2_LPI_6GHZ: ++ return "ETSI2_LPI_6GHZ"; ++ case ETSI2_VLP_6GHZ: ++ return "ETSI2_VLP_6GHZ"; ++ case APL1_LPI_6GHZ: ++ return "APL1_LPI_6GHZ"; ++ case APL1_VLP_6GHZ: ++ return "APL1_VLP_6GHZ"; ++ } ++ ++ return "unknown sub reg id"; ++} ++ ++enum reg_super_domain_6ghz { ++ FCC1_6GHZ = 0x01, ++ ETSI1_6GHZ = 0x02, ++ ETSI2_6GHZ = 0x03, ++ APL1_6GHZ = 0x04, ++ FCC1_6GHZ_CL = 0x05, ++ ++ /* add super domain above, handle it in ++ * ath11k_super_reg_6ghz_to_str() ++ */ + }; + ++static inline const char * ++ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id) ++{ ++ switch (domain_id) { ++ case FCC1_6GHZ: ++ return "FCC1_6GHZ"; ++ case ETSI1_6GHZ: ++ return "ETSI1_6GHZ"; ++ case ETSI2_6GHZ: ++ return "ETSI2_6GHZ"; ++ case APL1_6GHZ: ++ return "APL1_6GHZ"; ++ case FCC1_6GHZ_CL: ++ return "FCC1_6GHZ_CL"; ++ } ++ ++ return "unknown domain id"; ++} ++ + struct cur_reg_rule { + u16 start_freq; + u16 end_freq; diff --git a/package/kernel/mac80211/patches/ath11k/0046-wifi-ath11k-Replace-fake-flex-array-with-flexible-ar.patch b/package/kernel/mac80211/patches/ath11k/0046-wifi-ath11k-Replace-fake-flex-array-with-flexible-ar.patch new file mode 100644 index 000000000..bd1617856 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0046-wifi-ath11k-Replace-fake-flex-array-with-flexible-ar.patch @@ -0,0 +1,246 @@ +From 3b1088a09ec9438523c251d8435e78988824bc0d Mon Sep 17 00:00:00 2001 +From: "Gustavo A. R. Silva" +Date: Tue, 7 Mar 2023 16:22:39 -0600 +Subject: [PATCH] wifi: ath11k: Replace fake flex-array with flexible-array + member +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Zero-length arrays as fake flexible arrays are deprecated and we are +moving towards adopting C99 flexible-array members instead. + +Address 25 of the following warnings found with GCC-13 and +-fstrict-flex-arrays=3 enabled: +drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c:30:51: warning: array subscript is outside array bounds of ‘const u32[0]’ {aka ‘const unsigned int[]’} [-Warray-bounds=] + +This helps with the ongoing efforts to tighten the FORTIFY_SOURCE +routines on memcpy() and help us make progress towards globally +enabling -fstrict-flex-arrays=3 [1]. + +Link: https://github.com/KSPP/linux/issues/21 +Link: https://github.com/KSPP/linux/issues/266 +Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602902.html [1] +Signed-off-by: Gustavo A. R. Silva +Reviewed-by: Simon Horman +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/ZAe5L5DtmsQxzqRH@work +--- + .../wireless/ath/ath11k/debugfs_htt_stats.h | 73 +++++++++++-------- + 1 file changed, 43 insertions(+), 30 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h ++++ b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h +@@ -143,7 +143,8 @@ enum htt_tx_pdev_underrun_enum { + /* Bytes stored in little endian order */ + /* Length should be multiple of DWORD */ + struct htt_stats_string_tlv { +- u32 data[0]; /* Can be variable length */ ++ /* Can be variable length */ ++ DECLARE_FLEX_ARRAY(u32, data); + } __packed; + + #define HTT_STATS_MAC_ID GENMASK(7, 0) +@@ -205,27 +206,32 @@ struct htt_tx_pdev_stats_cmn_tlv { + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_pdev_stats_urrn_tlv_v { +- u32 urrn_stats[0]; /* HTT_TX_PDEV_MAX_URRN_STATS */ ++ /* HTT_TX_PDEV_MAX_URRN_STATS */ ++ DECLARE_FLEX_ARRAY(u32, urrn_stats); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_pdev_stats_flush_tlv_v { +- u32 flush_errs[0]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ ++ /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ ++ DECLARE_FLEX_ARRAY(u32, flush_errs); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_pdev_stats_sifs_tlv_v { +- u32 sifs_status[0]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ ++ /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ ++ DECLARE_FLEX_ARRAY(u32, sifs_status); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_pdev_stats_phy_err_tlv_v { +- u32 phy_errs[0]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ ++ /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ ++ DECLARE_FLEX_ARRAY(u32, phy_errs); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_pdev_stats_sifs_hist_tlv_v { +- u32 sifs_hist_status[0]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ ++ /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ ++ DECLARE_FLEX_ARRAY(u32, sifs_hist_status); + }; + + struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v { +@@ -590,20 +596,20 @@ struct htt_tx_hwq_difs_latency_stats_tlv + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_hwq_cmd_result_stats_tlv_v { +- /* Histogram of sched cmd result */ +- u32 cmd_result[0]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ ++ /* Histogram of sched cmd result, HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ ++ DECLARE_FLEX_ARRAY(u32, cmd_result); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_hwq_cmd_stall_stats_tlv_v { +- /* Histogram of various pause conitions */ +- u32 cmd_stall_status[0]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ ++ /* Histogram of various pause conitions, HTT_TX_HWQ_MAX_CMD_STALL_STATS */ ++ DECLARE_FLEX_ARRAY(u32, cmd_stall_status); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_hwq_fes_result_stats_tlv_v { +- /* Histogram of number of user fes result */ +- u32 fes_result[0]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ ++ /* Histogram of number of user fes result, HTT_TX_HWQ_MAX_FES_RESULT_STATS */ ++ DECLARE_FLEX_ARRAY(u32, fes_result); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size +@@ -635,8 +641,8 @@ struct htt_tx_hwq_tried_mpdu_cnt_hist_tl + * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) + */ + struct htt_tx_hwq_txop_used_cnt_hist_tlv_v { +- /* Histogram of txop used cnt */ +- u32 txop_used_cnt_hist[0]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ ++ /* Histogram of txop used cnt, HTT_TX_HWQ_TXOP_USED_CNT_HIST */ ++ DECLARE_FLEX_ARRAY(u32, txop_used_cnt_hist); + }; + + /* == TX SELFGEN STATS == */ +@@ -804,17 +810,20 @@ struct htt_tx_pdev_mpdu_stats_tlv { + /* == TX SCHED STATS == */ + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_sched_txq_cmd_posted_tlv_v { +- u32 sched_cmd_posted[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ ++ /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ ++ DECLARE_FLEX_ARRAY(u32, sched_cmd_posted); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_sched_txq_cmd_reaped_tlv_v { +- u32 sched_cmd_reaped[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ ++ /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ ++ DECLARE_FLEX_ARRAY(u32, sched_cmd_reaped); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_sched_txq_sched_order_su_tlv_v { +- u32 sched_order_su[0]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ ++ /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ ++ DECLARE_FLEX_ARRAY(u32, sched_order_su); + }; + + enum htt_sched_txq_sched_ineligibility_tlv_enum { +@@ -842,7 +851,7 @@ enum htt_sched_txq_sched_ineligibility_t + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_sched_txq_sched_ineligibility_tlv_v { + /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ +- u32 sched_ineligibility[0]; ++ DECLARE_FLEX_ARRAY(u32, sched_ineligibility); + }; + + #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) +@@ -888,18 +897,20 @@ struct htt_stats_tx_sched_cmn_tlv { + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_tqm_gen_mpdu_stats_tlv_v { +- u32 gen_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ ++ /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ ++ DECLARE_FLEX_ARRAY(u32, gen_mpdu_end_reason); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_tqm_list_mpdu_stats_tlv_v { +- u32 list_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ ++ /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ ++ DECLARE_FLEX_ARRAY(u32, list_mpdu_end_reason); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_tx_tqm_list_mpdu_cnt_tlv_v { +- u32 list_mpdu_cnt_hist[0]; +- /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ ++ /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ ++ DECLARE_FLEX_ARRAY(u32, list_mpdu_cnt_hist); + }; + + struct htt_tx_tqm_pdev_stats_tlv_v { +@@ -1098,7 +1109,7 @@ struct htt_tx_de_compl_stats_tlv { + * ENTRIES_PER_BIN_COUNT) + */ + struct htt_tx_de_fw2wbm_ring_full_hist_tlv { +- u32 fw2wbm_ring_full_hist[0]; ++ DECLARE_FLEX_ARRAY(u32, fw2wbm_ring_full_hist); + }; + + struct htt_tx_de_cmn_stats_tlv { +@@ -1151,7 +1162,7 @@ struct htt_ring_if_cmn_tlv { + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_sfm_client_user_tlv_v { + /* Number of DWORDS used per user and per client */ +- u32 dwords_used_by_user_n[0]; ++ DECLARE_FLEX_ARRAY(u32, dwords_used_by_user_n); + }; + + struct htt_sfm_client_tlv { +@@ -1436,12 +1447,14 @@ struct htt_rx_soc_fw_stats_tlv { + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_rx_soc_fw_refill_ring_empty_tlv_v { +- u32 refill_ring_empty_cnt[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ ++ /* HTT_RX_STATS_REFILL_MAX_RING */ ++ DECLARE_FLEX_ARRAY(u32, refill_ring_empty_cnt); + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v { +- u32 refill_ring_num_refill[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ ++ /* HTT_RX_STATS_REFILL_MAX_RING */ ++ DECLARE_FLEX_ARRAY(u32, refill_ring_num_refill); + }; + + /* RXDMA error code from WBM released packets */ +@@ -1473,7 +1486,7 @@ enum htt_rx_rxdma_error_code_enum { + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v { +- u32 rxdma_err[0]; /* HTT_RX_RXDMA_MAX_ERR_CODE */ ++ DECLARE_FLEX_ARRAY(u32, rxdma_err); /* HTT_RX_RXDMA_MAX_ERR_CODE */ + }; + + /* REO error code from WBM released packets */ +@@ -1505,7 +1518,7 @@ enum htt_rx_reo_error_code_enum { + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v { +- u32 reo_err[0]; /* HTT_RX_REO_MAX_ERR_CODE */ ++ DECLARE_FLEX_ARRAY(u32, reo_err); /* HTT_RX_REO_MAX_ERR_CODE */ + }; + + /* == RX PDEV STATS == */ +@@ -1622,13 +1635,13 @@ struct htt_rx_pdev_fw_stats_phy_err_tlv + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v { + /* Num error MPDU for each RxDMA error type */ +- u32 fw_ring_mpdu_err[0]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ ++ DECLARE_FLEX_ARRAY(u32, fw_ring_mpdu_err); /* HTT_RX_STATS_RXDMA_MAX_ERR */ + }; + + /* NOTE: Variable length TLV, use length spec to infer array size */ + struct htt_rx_pdev_fw_mpdu_drop_tlv_v { + /* Num MPDU dropped */ +- u32 fw_mpdu_drop[0]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ ++ DECLARE_FLEX_ARRAY(u32, fw_mpdu_drop); /* HTT_RX_STATS_FW_DROP_REASON_MAX */ + }; + + #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) diff --git a/package/kernel/mac80211/patches/ath11k/0047-wifi-ath11k-fix-deinitialization-of-firmware-resourc.patch b/package/kernel/mac80211/patches/ath11k/0047-wifi-ath11k-fix-deinitialization-of-firmware-resourc.patch new file mode 100644 index 000000000..eec11f50e --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0047-wifi-ath11k-fix-deinitialization-of-firmware-resourc.patch @@ -0,0 +1,79 @@ +From 5a78ac33e3cb8822da64dd1af196e83664b332b0 Mon Sep 17 00:00:00 2001 +From: Aditya Kumar Singh +Date: Thu, 9 Mar 2023 15:23:08 +0530 +Subject: [PATCH] wifi: ath11k: fix deinitialization of firmware resources + +Currently, in ath11k_ahb_fw_resources_init(), iommu domain +mapping is done only for the chipsets having fixed firmware +memory. Also, for such chipsets, mapping is done only if it +does not have TrustZone support. + +During deinitialization, only if TrustZone support is not there, +iommu is unmapped back. However, for non fixed firmware memory +chipsets, TrustZone support is not there and this makes the +condition check to true and it tries to unmap the memory which +was not mapped during initialization. + +This leads to the following trace - + +[ 83.198790] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000008 +[ 83.259537] Modules linked in: ath11k_ahb ath11k qmi_helpers +.. snip .. +[ 83.280286] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) +[ 83.287228] pc : __iommu_unmap+0x30/0x140 +[ 83.293907] lr : iommu_unmap+0x5c/0xa4 +[ 83.298072] sp : ffff80000b3abad0 +.. snip .. +[ 83.369175] Call trace: +[ 83.376282] __iommu_unmap+0x30/0x140 +[ 83.378541] iommu_unmap+0x5c/0xa4 +[ 83.382360] ath11k_ahb_fw_resource_deinit.part.12+0x2c/0xac [ath11k_ahb] +[ 83.385666] ath11k_ahb_free_resources+0x140/0x17c [ath11k_ahb] +[ 83.392521] ath11k_ahb_shutdown+0x34/0x40 [ath11k_ahb] +[ 83.398248] platform_shutdown+0x20/0x2c +[ 83.403455] device_shutdown+0x16c/0x1c4 +[ 83.407621] kernel_restart_prepare+0x34/0x3c +[ 83.411529] kernel_restart+0x14/0x74 +[ 83.415781] __do_sys_reboot+0x1c4/0x22c +[ 83.419427] __arm64_sys_reboot+0x1c/0x24 +[ 83.423420] invoke_syscall+0x44/0xfc +[ 83.427326] el0_svc_common.constprop.3+0xac/0xe8 +[ 83.430974] do_el0_svc+0xa0/0xa8 +[ 83.435659] el0_svc+0x1c/0x44 +[ 83.438957] el0t_64_sync_handler+0x60/0x144 +[ 83.441910] el0t_64_sync+0x15c/0x160 +[ 83.446343] Code: aa0103f4 f9400001 f90027a1 d2800001 (f94006a0) +[ 83.449903] ---[ end trace 0000000000000000 ]--- + +This can be reproduced by probing an AHB chipset which is not +having a fixed memory region. During reboot (or rmmod) trace +can be seen. + +Fix this issue by adding a condition check on firmware fixed memory +hw_param as done in the counter initialization function. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Fixes: f9eec4947add ("ath11k: Add support for targets without trustzone") +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230309095308.24937-1-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -1078,6 +1078,12 @@ static int ath11k_ahb_fw_resource_deinit + struct iommu_domain *iommu; + size_t unmapped_size; + ++ /* Chipsets not requiring MSA would have not initialized ++ * MSA resources, return success in such cases. ++ */ ++ if (!ab->hw_params.fixed_fw_mem) ++ return 0; ++ + if (ab_ahb->fw.use_tz) + return 0; + diff --git a/package/kernel/mac80211/patches/ath11k/0048-wifi-ath11k-fix-BUFFER_DONE-read-on-monitor-ring-rx-.patch b/package/kernel/mac80211/patches/ath11k/0048-wifi-ath11k-fix-BUFFER_DONE-read-on-monitor-ring-rx-.patch new file mode 100644 index 000000000..3e2264533 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0048-wifi-ath11k-fix-BUFFER_DONE-read-on-monitor-ring-rx-.patch @@ -0,0 +1,130 @@ +From 68e93ac5a31d4975b25f819b2dfe914c72abc3bb Mon Sep 17 00:00:00 2001 +From: Harshitha Prem +Date: Wed, 15 Mar 2023 12:24:43 +0200 +Subject: [PATCH] wifi: ath11k: fix BUFFER_DONE read on monitor ring rx buffer + +Perform dma_sync_single_for_cpu() on monitor ring rx buffer before +reading BUFFER_DONE tag and do dma_unmap_single() only after device +had set BUFFER_DONE tag to the buffer. + +Also when BUFFER_DONE tag is not set, allow the buffer to get read +next time without freeing skb. + +This helps to fix AP+Monitor VAP with flood traffic scenario to see +monitor ring rx buffer overrun missing BUFFER_DONE tag to be set. + +Also remove redundant rx dma buf free performed on DP +rx_mon_status_refill_ring. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sathishkumar Muruganandam +Signed-off-by: Harshitha Prem +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230309164434.32660-1-quic_hprem@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 57 ++++++++++--------------- + 1 file changed, 23 insertions(+), 34 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -435,7 +435,6 @@ fail_free_skb: + static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, + struct dp_rxdma_ring *rx_ring) + { +- struct ath11k_pdev_dp *dp = &ar->dp; + struct sk_buff *skb; + int buf_id; + +@@ -453,28 +452,6 @@ static int ath11k_dp_rxdma_buf_ring_free + idr_destroy(&rx_ring->bufs_idr); + spin_unlock_bh(&rx_ring->idr_lock); + +- /* if rxdma1_enable is false, mon_status_refill_ring +- * isn't setup, so don't clean. +- */ +- if (!ar->ab->hw_params.rxdma1_enable) +- return 0; +- +- rx_ring = &dp->rx_mon_status_refill_ring[0]; +- +- spin_lock_bh(&rx_ring->idr_lock); +- idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { +- idr_remove(&rx_ring->bufs_idr, buf_id); +- /* XXX: Understand where internal driver does this dma_unmap +- * of rxdma_buffer. +- */ +- dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, +- skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL); +- dev_kfree_skb_any(skb); +- } +- +- idr_destroy(&rx_ring->bufs_idr); +- spin_unlock_bh(&rx_ring->idr_lock); +- + return 0; + } + +@@ -3029,39 +3006,51 @@ static int ath11k_dp_rx_reap_mon_status_ + + spin_lock_bh(&rx_ring->idr_lock); + skb = idr_find(&rx_ring->bufs_idr, buf_id); ++ spin_unlock_bh(&rx_ring->idr_lock); ++ + if (!skb) { + ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", + buf_id); +- spin_unlock_bh(&rx_ring->idr_lock); + pmon->buf_state = DP_MON_STATUS_REPLINISH; + goto move_next; + } + +- idr_remove(&rx_ring->bufs_idr, buf_id); +- spin_unlock_bh(&rx_ring->idr_lock); +- + rxcb = ATH11K_SKB_RXCB(skb); + +- dma_unmap_single(ab->dev, rxcb->paddr, +- skb->len + skb_tailroom(skb), +- DMA_FROM_DEVICE); ++ dma_sync_single_for_cpu(ab->dev, rxcb->paddr, ++ skb->len + skb_tailroom(skb), ++ DMA_FROM_DEVICE); + + tlv = (struct hal_tlv_hdr *)skb->data; + if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != + HAL_RX_STATUS_BUFFER_DONE) { +- ath11k_warn(ab, "mon status DONE not set %lx\n", ++ ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n", + FIELD_GET(HAL_TLV_HDR_TAG, +- tlv->tl)); +- dev_kfree_skb_any(skb); ++ tlv->tl), buf_id); ++ /* If done status is missing, hold onto status ++ * ring until status is done for this status ++ * ring buffer. ++ * Keep HP in mon_status_ring unchanged, ++ * and break from here. ++ * Check status for same buffer for next time ++ */ + pmon->buf_state = DP_MON_STATUS_NO_DMA; +- goto move_next; ++ break; + } + ++ spin_lock_bh(&rx_ring->idr_lock); ++ idr_remove(&rx_ring->bufs_idr, buf_id); ++ spin_unlock_bh(&rx_ring->idr_lock); + if (ab->hw_params.full_monitor_mode) { + ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv); + if (paddr == pmon->mon_status_paddr) + pmon->buf_state = DP_MON_STATUS_MATCH; + } ++ ++ dma_unmap_single(ab->dev, rxcb->paddr, ++ skb->len + skb_tailroom(skb), ++ DMA_FROM_DEVICE); ++ + __skb_queue_tail(skb_list, skb); + } else { + pmon->buf_state = DP_MON_STATUS_REPLINISH; diff --git a/package/kernel/mac80211/patches/ath11k/0049-wifi-ath11k-Optimize-6-GHz-scan-time.patch b/package/kernel/mac80211/patches/ath11k/0049-wifi-ath11k-Optimize-6-GHz-scan-time.patch new file mode 100644 index 000000000..f468990fe --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0049-wifi-ath11k-Optimize-6-GHz-scan-time.patch @@ -0,0 +1,101 @@ +From 8b4d2f080afbd4280ecca0f4b3ceea943a7a86d0 Mon Sep 17 00:00:00 2001 +From: Manikanta Pubbisetty +Date: Thu, 23 Mar 2023 11:39:13 +0530 +Subject: [PATCH] wifi: ath11k: Optimize 6 GHz scan time + +Currently, time taken to scan all supported channels on WCN6750 +is ~8 seconds and connection time is almost 10 seconds. WCN6750 +supports three Wi-Fi bands (i.e., 2.4/5/6 GHz) and the numbers of +channels for scan come around ~100 channels (default case). +Since the chip doesn't have support for DBS (Dual Band Simultaneous), +scans cannot be parallelized resulting in longer scan times. + +Among the 100 odd channels, ~60 channels are in 6 GHz band. Therefore, +optimizing the scan for 6 GHz channels will bring down the overall +scan time. + +WCN6750 firmware has support to scan a 6 GHz channel based on co-located +AP information i.e., RNR IE which is found in the legacy 2.4/5 GHz scan +results. When a scan request with all supported channel list is enqueued +to the firmware, then based on WMI_SCAN_CHAN_FLAG_SCAN_ONLY_IF_RNR_FOUND +scan channel flag, firmware will scan only those 6 GHz channels for which +RNR IEs are found in the legacy scan results. + +In the proposed design, based on NL80211_SCAN_FLAG_COLOCATED_6GHZ scan +flag, driver will set the WMI_SCAN_CHAN_FLAG_SCAN_ONLY_IF_RNR_FOUND flag +for non-PSC channels. Since there is high probability to find 6 GHz APs +on PSC channels, these channels are always scanned. Only non-PSC channels +are selectively scanned based on cached RNR information from the legacy +scan results. + +If NL80211_SCAN_FLAG_COLOCATED_6GHZ is not set in the scan flags, +then scan will happen on all supported channels (default behavior). + +With these optimizations, scan time is improved by 1.5-1.8 seconds on +WCN6750. Similar savings have been observed on WCN6855. + +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 +Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.16 + +Signed-off-by: Manikanta Pubbisetty +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230323060913.10097-1-quic_mpubbise@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 25 +++++++++++++++++++++++-- + drivers/net/wireless/ath/ath11k/wmi.h | 4 ++++ + 2 files changed, 27 insertions(+), 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3819,8 +3819,29 @@ static int ath11k_mac_op_hw_scan(struct + goto exit; + } + +- for (i = 0; i < arg->num_chan; i++) +- arg->chan_list[i] = req->channels[i]->center_freq; ++ for (i = 0; i < arg->num_chan; i++) { ++ if (test_bit(WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL, ++ ar->ab->wmi_ab.svc_map)) { ++ arg->chan_list[i] = ++ u32_encode_bits(req->channels[i]->center_freq, ++ WMI_SCAN_CONFIG_PER_CHANNEL_MASK); ++ ++ /* If NL80211_SCAN_FLAG_COLOCATED_6GHZ is set in scan ++ * flags, then scan all PSC channels in 6 GHz band and ++ * those non-PSC channels where RNR IE is found during ++ * the legacy 2.4/5 GHz scan. ++ * If NL80211_SCAN_FLAG_COLOCATED_6GHZ is not set, ++ * then all channels in 6 GHz will be scanned. ++ */ ++ if (req->channels[i]->band == NL80211_BAND_6GHZ && ++ req->flags & NL80211_SCAN_FLAG_COLOCATED_6GHZ && ++ !cfg80211_channel_is_psc(req->channels[i])) ++ arg->chan_list[i] |= ++ WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND; ++ } else { ++ arg->chan_list[i] = req->channels[i]->center_freq; ++ } ++ } + } + + if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) { +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2100,6 +2100,7 @@ enum wmi_tlv_service { + + /* The second 128 bits */ + WMI_MAX_EXT_SERVICE = 256, ++ WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, + WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, + WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, + +@@ -3249,6 +3250,9 @@ struct wmi_start_scan_cmd { + #define WMI_SCAN_DWELL_MODE_SHIFT 21 + #define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800 + ++#define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0) ++#define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20) ++ + enum { + WMI_SCAN_DWELL_MODE_DEFAULT = 0, + WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, diff --git a/package/kernel/mac80211/patches/ath11k/0050-wifi-ath11k-Configure-the-FTM-responder-role-using-f.patch b/package/kernel/mac80211/patches/ath11k/0050-wifi-ath11k-Configure-the-FTM-responder-role-using-f.patch new file mode 100644 index 000000000..bca08b177 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0050-wifi-ath11k-Configure-the-FTM-responder-role-using-f.patch @@ -0,0 +1,117 @@ +From 813968c24126cc5c8320cd5db0e262069a535063 Mon Sep 17 00:00:00 2001 +From: Ganesh Babu Jothiram +Date: Fri, 24 Mar 2023 16:57:00 +0200 +Subject: [PATCH] wifi: ath11k: Configure the FTM responder role using firmware + capability flag + +Fine Time Measurement(FTM) is offloaded feature to firmware. +Hence, the configuration of FTM responder role is done using +firmware capability flag instead of hw param. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Ganesh Babu Jothiram +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230317072034.8217-1-quic_gjothira@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 8 -------- + drivers/net/wireless/ath/ath11k/hw.h | 1 - + drivers/net/wireless/ath/ath11k/mac.c | 4 ++-- + 3 files changed, 2 insertions(+), 11 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -116,7 +116,6 @@ static const struct ath11k_hw_params ath + .tcl_ring_retry = true, + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, +- .ftm_responder = true, + }, + { + .hw_rev = ATH11K_HW_IPQ6018_HW10, +@@ -199,7 +198,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = false, +- .ftm_responder = true, + }, + { + .name = "qca6390 hw2.0", +@@ -284,7 +282,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = true, +- .ftm_responder = false, + }, + { + .name = "qcn9074 hw1.0", +@@ -366,7 +363,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = false, +- .ftm_responder = true, + }, + { + .name = "wcn6855 hw2.0", +@@ -451,7 +447,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = true, +- .ftm_responder = false, + }, + { + .name = "wcn6855 hw2.1", +@@ -534,7 +529,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = true, +- .ftm_responder = false, + }, + { + .name = "wcn6750 hw1.0", +@@ -615,7 +609,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, + .smp2p_wow_exit = true, + .support_fw_mac_sequence = true, +- .ftm_responder = false, + }, + { + .hw_rev = ATH11K_HW_IPQ5018_HW10, +@@ -695,7 +688,6 @@ static const struct ath11k_hw_params ath + .tx_ring_size = DP_TCL_DATA_RING_SIZE, + .smp2p_wow_exit = false, + .support_fw_mac_sequence = false, +- .ftm_responder = true, + }, + }; + +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -224,7 +224,6 @@ struct ath11k_hw_params { + u32 tx_ring_size; + bool smp2p_wow_exit; + bool support_fw_mac_sequence; +- bool ftm_responder; + }; + + struct ath11k_hw_ops { +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3538,7 +3538,7 @@ static void ath11k_mac_op_bss_info_chang + + if (changed & BSS_CHANGED_FTM_RESPONDER && + arvif->ftm_responder != info->ftm_responder && +- ar->ab->hw_params.ftm_responder && ++ test_bit(WMI_TLV_SERVICE_RTT, ar->ab->wmi_ab.svc_map) && + (vif->type == NL80211_IFTYPE_AP || + vif->type == NL80211_IFTYPE_MESH_POINT)) { + arvif->ftm_responder = info->ftm_responder; +@@ -9234,7 +9234,7 @@ static int __ath11k_mac_register(struct + wiphy_ext_feature_set(ar->hw->wiphy, + NL80211_EXT_FEATURE_SET_SCAN_DWELL); + +- if (ab->hw_params.ftm_responder) ++ if (test_bit(WMI_TLV_SERVICE_RTT, ar->ab->wmi_ab.svc_map)) + wiphy_ext_feature_set(ar->hw->wiphy, + NL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER); + diff --git a/package/kernel/mac80211/patches/ath11k/0051-wifi-ath11k-fix-rssi-station-dump-not-updated-in-QCN.patch b/package/kernel/mac80211/patches/ath11k/0051-wifi-ath11k-fix-rssi-station-dump-not-updated-in-QCN.patch new file mode 100644 index 000000000..835dece1f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0051-wifi-ath11k-fix-rssi-station-dump-not-updated-in-QCN.patch @@ -0,0 +1,158 @@ +From 031ffa6c2cd305a57ccc6d610f2decd956b2e7f6 Mon Sep 17 00:00:00 2001 +From: P Praneesh +Date: Fri, 24 Mar 2023 16:57:00 +0200 +Subject: [PATCH] wifi: ath11k: fix rssi station dump not updated in QCN9074 + +In QCN9074, station dump signal values display default value which +is -95 dbm, since there is firmware header change for HAL_RX_MPDU_START +between QCN9074 and IPQ8074 which cause wrong peer_id fetch from msdu. +Fix this by updating hal_rx_mpdu_info with corresponding QCN9074 tlv +format. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-01695-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: P Praneesh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230320110312.20639-1-quic_ppranees@quicinc.com +--- + drivers/net/wireless/ath/ath11k/hal_rx.c | 10 ++++++++- + drivers/net/wireless/ath/ath11k/hal_rx.h | 18 +++++++++++++++- + drivers/net/wireless/ath/ath11k/hw.c | 27 ++++++++++++++++-------- + drivers/net/wireless/ath/ath11k/hw.h | 2 +- + 4 files changed, 45 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/hal_rx.c ++++ b/drivers/net/wireless/ath/ath11k/hal_rx.c +@@ -865,6 +865,12 @@ ath11k_hal_rx_populate_mu_user_info(void + ath11k_hal_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); + } + ++static u16 ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base *ab, ++ struct hal_rx_mpdu_info *mpdu_info) ++{ ++ return ab->hw_params.hw_ops->mpdu_info_get_peerid(mpdu_info); ++} ++ + static enum hal_rx_mon_status + ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab, + struct hal_rx_mon_ppdu_info *ppdu_info, +@@ -1459,9 +1465,11 @@ ath11k_hal_rx_parse_mon_status_tlv(struc + break; + } + case HAL_RX_MPDU_START: { ++ struct hal_rx_mpdu_info *mpdu_info = ++ (struct hal_rx_mpdu_info *)tlv_data; + u16 peer_id; + +- peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data); ++ peer_id = ath11k_hal_rx_mpduinfo_get_peerid(ab, mpdu_info); + if (peer_id) + ppdu_info->peer_id = peer_id; + break; +--- a/drivers/net/wireless/ath/ath11k/hal_rx.h ++++ b/drivers/net/wireless/ath/ath11k/hal_rx.h +@@ -405,7 +405,7 @@ struct hal_rx_phyrx_rssi_legacy_info { + #define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0) + #define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN GENMASK(13, 0) + +-struct hal_rx_mpdu_info { ++struct hal_rx_mpdu_info_ipq8074 { + __le32 rsvd0; + __le32 info0; + __le32 rsvd1[11]; +@@ -413,12 +413,28 @@ struct hal_rx_mpdu_info { + __le32 rsvd2[9]; + } __packed; + ++struct hal_rx_mpdu_info_qcn9074 { ++ __le32 rsvd0[10]; ++ __le32 info0; ++ __le32 rsvd1[2]; ++ __le32 info1; ++ __le32 rsvd2[9]; ++} __packed; ++ + struct hal_rx_mpdu_info_wcn6855 { + __le32 rsvd0[8]; + __le32 info0; + __le32 rsvd1[14]; + } __packed; + ++struct hal_rx_mpdu_info { ++ union { ++ struct hal_rx_mpdu_info_ipq8074 ipq8074; ++ struct hal_rx_mpdu_info_qcn9074 qcn9074; ++ struct hal_rx_mpdu_info_wcn6855 wcn6855; ++ } u; ++} __packed; ++ + #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0) + struct hal_rx_ppdu_end_duration { + __le32 rsvd0[9]; +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -835,26 +835,35 @@ static void ath11k_hw_ipq5018_reo_setup( + ring_hash_map); + } + +-static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) ++static u16 ++ath11k_hw_ipq8074_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info) + { + u16 peer_id = 0; +- struct hal_rx_mpdu_info *mpdu_info = +- (struct hal_rx_mpdu_info *)tlv_data; + + peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, +- __le32_to_cpu(mpdu_info->info0)); ++ __le32_to_cpu(mpdu_info->u.ipq8074.info0)); + + return peer_id; + } + +-static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) ++static u16 ++ath11k_hw_qcn9074_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info) ++{ ++ u16 peer_id = 0; ++ ++ peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, ++ __le32_to_cpu(mpdu_info->u.qcn9074.info0)); ++ ++ return peer_id; ++} ++ ++static u16 ++ath11k_hw_wcn6855_mpdu_info_get_peerid(struct hal_rx_mpdu_info *mpdu_info) + { + u16 peer_id = 0; +- struct hal_rx_mpdu_info_wcn6855 *mpdu_info = +- (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; + + peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, +- __le32_to_cpu(mpdu_info->info0)); ++ __le32_to_cpu(mpdu_info->u.wcn6855.info0)); + return peer_id; + } + +@@ -1042,7 +1051,7 @@ const struct ath11k_hw_ops qcn9074_ops = + .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, + .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, + .reo_setup = ath11k_hw_ipq8074_reo_setup, +- .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, ++ .mpdu_info_get_peerid = ath11k_hw_qcn9074_mpdu_info_get_peerid, + .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, + .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, + .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -263,7 +263,7 @@ struct ath11k_hw_ops { + struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc); + u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); + void (*reo_setup)(struct ath11k_base *ab); +- u16 (*mpdu_info_get_peerid)(u8 *tlv_data); ++ u16 (*mpdu_info_get_peerid)(struct hal_rx_mpdu_info *mpdu_info); + bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc); + u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc); + u32 (*get_ring_selector)(struct sk_buff *skb); diff --git a/package/kernel/mac80211/patches/ath11k/0052-wifi-ath11k-Fix-invalid-management-rx-frame-length-i.patch b/package/kernel/mac80211/patches/ath11k/0052-wifi-ath11k-Fix-invalid-management-rx-frame-length-i.patch new file mode 100644 index 000000000..0c1637fb0 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0052-wifi-ath11k-Fix-invalid-management-rx-frame-length-i.patch @@ -0,0 +1,115 @@ +From 447b0398a9cd41ca343dfd43e555af92d6214487 Mon Sep 17 00:00:00 2001 +From: Bhagavathi Perumal S +Date: Fri, 24 Mar 2023 16:57:00 +0200 +Subject: [PATCH] wifi: ath11k: Fix invalid management rx frame length issue + +The WMI management rx event has multiple arrays of TLVs, however the common +WMI TLV parser won't handle multiple TLV tags of same type. +So the multiple array tags of WMI management rx TLV is parsed incorrectly +and the length calculated becomes wrong when the target sends multiple +array tags. + +Add separate TLV parser to handle multiple arrays for WMI management rx +TLV. This fixes invalid length issue when the target sends multiple array +tags. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Bhagavathi Perumal S +Co-developed-by: Nagarajan Maran +Signed-off-by: Nagarajan Maran +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230320133840.30162-1-quic_nmaran@quicinc.com +--- + drivers/net/wireless/ath/ath11k/wmi.c | 45 +++++++++++++++++++++------ + 1 file changed, 35 insertions(+), 10 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -82,6 +82,12 @@ struct wmi_tlv_fw_stats_parse { + bool chain_rssi_done; + }; + ++struct wmi_tlv_mgmt_rx_parse { ++ const struct wmi_mgmt_rx_hdr *fixed; ++ const u8 *frame_buf; ++ bool frame_buf_done; ++}; ++ + static const struct wmi_tlv_policy wmi_tlv_policies[] = { + [WMI_TAG_ARRAY_BYTE] + = { .min_len = 0 }, +@@ -5633,28 +5639,49 @@ static int ath11k_pull_vdev_stopped_para + return 0; + } + ++static int ath11k_wmi_tlv_mgmt_rx_parse(struct ath11k_base *ab, ++ u16 tag, u16 len, ++ const void *ptr, void *data) ++{ ++ struct wmi_tlv_mgmt_rx_parse *parse = data; ++ ++ switch (tag) { ++ case WMI_TAG_MGMT_RX_HDR: ++ parse->fixed = ptr; ++ break; ++ case WMI_TAG_ARRAY_BYTE: ++ if (!parse->frame_buf_done) { ++ parse->frame_buf = ptr; ++ parse->frame_buf_done = true; ++ } ++ break; ++ } ++ return 0; ++} ++ + static int ath11k_pull_mgmt_rx_params_tlv(struct ath11k_base *ab, + struct sk_buff *skb, + struct mgmt_rx_event_params *hdr) + { +- const void **tb; ++ struct wmi_tlv_mgmt_rx_parse parse = { }; + const struct wmi_mgmt_rx_hdr *ev; + const u8 *frame; + int ret; + +- tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); +- if (IS_ERR(tb)) { +- ret = PTR_ERR(tb); +- ath11k_warn(ab, "failed to parse tlv: %d\n", ret); ++ ret = ath11k_wmi_tlv_iter(ab, skb->data, skb->len, ++ ath11k_wmi_tlv_mgmt_rx_parse, ++ &parse); ++ if (ret) { ++ ath11k_warn(ab, "failed to parse mgmt rx tlv %d\n", ++ ret); + return ret; + } + +- ev = tb[WMI_TAG_MGMT_RX_HDR]; +- frame = tb[WMI_TAG_ARRAY_BYTE]; ++ ev = parse.fixed; ++ frame = parse.frame_buf; + + if (!ev || !frame) { + ath11k_warn(ab, "failed to fetch mgmt rx hdr"); +- kfree(tb); + return -EPROTO; + } + +@@ -5673,7 +5700,6 @@ static int ath11k_pull_mgmt_rx_params_tl + + if (skb->len < (frame - skb->data) + hdr->buf_len) { + ath11k_warn(ab, "invalid length in mgmt rx hdr ev"); +- kfree(tb); + return -EPROTO; + } + +@@ -5685,7 +5711,6 @@ static int ath11k_pull_mgmt_rx_params_tl + + ath11k_ce_byte_swap(skb->data, hdr->buf_len); + +- kfree(tb); + return 0; + } + diff --git a/package/kernel/mac80211/patches/ath11k/0053-wifi-ath11k-fix-writing-to-unintended-memory-region.patch b/package/kernel/mac80211/patches/ath11k/0053-wifi-ath11k-fix-writing-to-unintended-memory-region.patch new file mode 100644 index 000000000..7b8a7d454 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0053-wifi-ath11k-fix-writing-to-unintended-memory-region.patch @@ -0,0 +1,43 @@ +From 756a7f90878f0866fd2fe167ef37e90b47326b96 Mon Sep 17 00:00:00 2001 +From: P Praneesh +Date: Fri, 24 Mar 2023 16:57:01 +0200 +Subject: [PATCH] wifi: ath11k: fix writing to unintended memory region + +While initializing spectral, the magic value is getting written to the +invalid memory address leading to random boot-up crash. This occurs +due to the incorrect index increment in ath11k_dbring_fill_magic_value +function. Fix it by replacing the existing logic with memset32 to ensure +there is no invalid memory access. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1-01838-QCAHKSWPL_SILICONZ-1 + +Fixes: d3d358efc553 ("ath11k: add spectral/CFR buffer validation support") +Signed-off-by: P Praneesh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230321052900.16895-1-quic_ppranees@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dbring.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/dbring.c ++++ b/drivers/net/wireless/ath/ath11k/dbring.c +@@ -26,13 +26,13 @@ int ath11k_dbring_validate_buffer(struct + static void ath11k_dbring_fill_magic_value(struct ath11k *ar, + void *buffer, u32 size) + { +- u32 *temp; +- int idx; ++ /* memset32 function fills buffer payload with the ATH11K_DB_MAGIC_VALUE ++ * and the variable size is expected to be the number of u32 values ++ * to be stored, not the number of bytes. ++ */ ++ size = size / sizeof(u32); + +- size = size >> 2; +- +- for (idx = 0, temp = buffer; idx < size; idx++, temp++) +- *temp++ = ATH11K_DB_MAGIC_VALUE; ++ memset32(buffer, ATH11K_DB_MAGIC_VALUE, size); + } + + static int ath11k_dbring_bufs_replenish(struct ath11k *ar, diff --git a/package/kernel/mac80211/patches/ath11k/0054-wifi-ath11k-Send-11d-scan-start-before-WMI_START_SCA.patch b/package/kernel/mac80211/patches/ath11k/0054-wifi-ath11k-Send-11d-scan-start-before-WMI_START_SCA.patch new file mode 100644 index 000000000..0f8e63759 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0054-wifi-ath11k-Send-11d-scan-start-before-WMI_START_SCA.patch @@ -0,0 +1,61 @@ +From e89a51aedf380bc60219dc9afa96c36507060fb3 Mon Sep 17 00:00:00 2001 +From: Manikanta Pubbisetty +Date: Wed, 15 Mar 2023 21:48:17 +0530 +Subject: [PATCH] wifi: ath11k: Send 11d scan start before WMI_START_SCAN_CMDID + +Firmwares advertising the support of triggering 11d algorithm on the +scan results of a regular scan expects driver to send +WMI_11D_SCAN_START_CMDID before sending WMI_START_SCAN_CMDID. +Triggering 11d algorithm on the scan results of a normal scan helps +in completely avoiding a separate 11d scan for determining regdomain. +This indirectly helps in speeding up connections on station +interfaces on the chipsets supporting 11D scan. + +To enable this feature, send WMI_11D_SCAN_START_CMDID just before +sending WMI_START_SCAN_CMDID if the firmware advertises +WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN service flag. + +WCN6750 & WCN6855 supports this feature. + +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-01160-QCAMSLSWPLZ-1 +Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 + +Signed-off-by: Manikanta Pubbisetty +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230315161817.29627-1-quic_mpubbise@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 12 ++++++++++++ + drivers/net/wireless/ath/ath11k/wmi.h | 1 + + 2 files changed, 13 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -3755,6 +3755,18 @@ static int ath11k_mac_op_hw_scan(struct + int i; + u32 scan_timeout; + ++ /* Firmwares advertising the support of triggering 11D algorithm ++ * on the scan results of a regular scan expects driver to send ++ * WMI_11D_SCAN_START_CMDID before sending WMI_START_SCAN_CMDID. ++ * With this feature, separate 11D scan can be avoided since ++ * regdomain can be determined with the scan results of the ++ * regular scan. ++ */ ++ if (ar->state_11d == ATH11K_11D_PREPARING && ++ test_bit(WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN, ++ ar->ab->wmi_ab.svc_map)) ++ ath11k_mac_11d_scan_start(ar, arvif->vdev_id); ++ + mutex_lock(&ar->conf_mutex); + + spin_lock_bh(&ar->data_lock); +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2103,6 +2103,7 @@ enum wmi_tlv_service { + WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, + WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, + WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, ++ WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, + + /* The third 128 bits */ + WMI_MAX_EXT2_SERVICE = 384 diff --git a/package/kernel/mac80211/patches/ath11k/0055-wifi-ath11k-Remove-redundant-pci_clear_master.patch b/package/kernel/mac80211/patches/ath11k/0055-wifi-ath11k-Remove-redundant-pci_clear_master.patch new file mode 100644 index 000000000..0439727e7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0055-wifi-ath11k-Remove-redundant-pci_clear_master.patch @@ -0,0 +1,58 @@ +From f812e2a9f85d6bea78957ccb5197e4491316848b Mon Sep 17 00:00:00 2001 +From: Cai Huoqing +Date: Thu, 23 Mar 2023 19:26:09 +0800 +Subject: [PATCH] wifi: ath11k: Remove redundant pci_clear_master + +Remove pci_clear_master to simplify the code, +the bus-mastering is also cleared in do_pci_disable_device, +like this: +./drivers/pci/pci.c:2197 +static void do_pci_disable_device(struct pci_dev *dev) +{ + u16 pci_command; + + pci_read_config_word(dev, PCI_COMMAND, &pci_command); + if (pci_command & PCI_COMMAND_MASTER) { + pci_command &= ~PCI_COMMAND_MASTER; + pci_write_config_word(dev, PCI_COMMAND, pci_command); + } + + pcibios_disable_device(dev); +}. +And dev->is_busmaster is set to 0 in pci_disable_device. + +Signed-off-by: Cai Huoqing +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230323112613.7550-1-cai.huoqing@linux.dev +--- + drivers/net/wireless/ath/ath11k/pci.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -540,7 +540,7 @@ static int ath11k_pci_claim(struct ath11 + if (!ab->mem) { + ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); + ret = -EIO; +- goto clear_master; ++ goto release_region; + } + + ab->mem_ce = ab->mem; +@@ -548,8 +548,6 @@ static int ath11k_pci_claim(struct ath11 + ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); + return 0; + +-clear_master: +- pci_clear_master(pdev); + release_region: + pci_release_region(pdev, ATH11K_PCI_BAR_NUM); + disable_device: +@@ -565,7 +563,6 @@ static void ath11k_pci_free_region(struc + + pci_iounmap(pci_dev, ab->mem); + ab->mem = NULL; +- pci_clear_master(pci_dev); + pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); + if (pci_is_enabled(pci_dev)) + pci_disable_device(pci_dev); diff --git a/package/kernel/mac80211/patches/ath11k/0056-wifi-ath11k-Disable-Spectral-scan-upon-removing-inte.patch b/package/kernel/mac80211/patches/ath11k/0056-wifi-ath11k-Disable-Spectral-scan-upon-removing-inte.patch new file mode 100644 index 000000000..44532a4d7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0056-wifi-ath11k-Disable-Spectral-scan-upon-removing-inte.patch @@ -0,0 +1,36 @@ +From 5c690db63b45c6c4c4932b13173af71df369dba5 Mon Sep 17 00:00:00 2001 +From: Tamizh Chelvam Raja +Date: Tue, 28 Mar 2023 12:41:50 +0530 +Subject: [PATCH] wifi: ath11k: Disable Spectral scan upon removing interface + +Host might receive spectral events during interface +down sequence and this might create below errors. + +failed to handle dma buf release event -22 +failed to handle dma buf release event -22 + +Fix this by disabling spectral config during remove interface. + +Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Tamizh Chelvam Raja +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230328071150.29645-1-quic_tamizhr@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -6685,6 +6685,11 @@ static void ath11k_mac_op_remove_interfa + ath11k_dbg(ab, ATH11K_DBG_MAC, "mac remove interface (vdev %d)\n", + arvif->vdev_id); + ++ ret = ath11k_spectral_vif_stop(arvif); ++ if (ret) ++ ath11k_warn(ab, "failed to stop spectral for vdev %i: %d\n", ++ arvif->vdev_id, ret); ++ + if (arvif->vdev_type == WMI_VDEV_TYPE_STA) + ath11k_mac_11d_scan_stop(ar); + diff --git a/package/kernel/mac80211/patches/ath11k/0057-wifi-ath11k-enable-SAR-support-on-WCN6750.patch b/package/kernel/mac80211/patches/ath11k/0057-wifi-ath11k-enable-SAR-support-on-WCN6750.patch new file mode 100644 index 000000000..5e64e552c --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0057-wifi-ath11k-enable-SAR-support-on-WCN6750.patch @@ -0,0 +1,29 @@ +From abf57d84973ce1abcb67504ac0df8aea1fe09a76 Mon Sep 17 00:00:00 2001 +From: Youghandhar Chintala +Date: Tue, 28 Mar 2023 17:04:55 +0530 +Subject: [PATCH] wifi: ath11k: enable SAR support on WCN6750 + +Currently, SAR is enabled only on WCN6855, enable this for WCN6750 too. This +functionality gets triggered, when the user space application calls +NL80211_CMD_SET_SAR_SPECS. + +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 + +Signed-off-by: Youghandhar Chintala +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230328113455.11252-1-quic_youghand@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -593,7 +593,7 @@ static const struct ath11k_hw_params ath + .current_cc_support = true, + .dbr_debug_support = false, + .global_reset = false, +- .bios_sar_capa = NULL, ++ .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, + .m3_fw_support = false, + .fixed_bdf_addr = false, + .fixed_mem_region = false, diff --git a/package/kernel/mac80211/patches/ath11k/0058-wifi-ath11k-pci-Add-more-MODULE_FIRMWARE-entries.patch b/package/kernel/mac80211/patches/ath11k/0058-wifi-ath11k-pci-Add-more-MODULE_FIRMWARE-entries.patch new file mode 100644 index 000000000..585864eff --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0058-wifi-ath11k-pci-Add-more-MODULE_FIRMWARE-entries.patch @@ -0,0 +1,36 @@ +From 06c58473969239e00d76b683edd511952060ca56 Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Thu, 30 Mar 2023 16:37:18 +0200 +Subject: [PATCH] wifi: ath11k: pci: Add more MODULE_FIRMWARE() entries + +As there are a few more models supported by the driver, let's add the +missing MODULE_FIRMWARE() entries for them. The lack of them resulted +in the missing device enablement on some systems, such as the +installation image of openSUSE. + +While we are at it, use the wildcard instead of listing each firmware +files individually for each. + +Signed-off-by: Takashi Iwai +Reviewed-by: Simon Horman +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230330143718.19511-1-tiwai@suse.de +--- + drivers/net/wireless/ath/ath11k/pci.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -1036,7 +1036,8 @@ module_exit(ath11k_pci_exit); + MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); + MODULE_LICENSE("Dual BSD/GPL"); + +-/* QCA639x 2.0 firmware files */ +-MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE); +-MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE); +-MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE); ++/* firmware files */ ++MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*"); ++MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*"); ++MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*"); ++MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*"); diff --git a/package/kernel/mac80211/patches/ath11k/0059-wifi-ath11k-print-a-warning-when-crypto_alloc_shash-.patch b/package/kernel/mac80211/patches/ath11k/0059-wifi-ath11k-print-a-warning-when-crypto_alloc_shash-.patch new file mode 100644 index 000000000..fab52a0fa --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0059-wifi-ath11k-print-a-warning-when-crypto_alloc_shash-.patch @@ -0,0 +1,34 @@ +From a87a9110ac0dcbfd9458b6665c141fa1c16a669d Mon Sep 17 00:00:00 2001 +From: Kalle Valo +Date: Wed, 5 Apr 2023 12:04:25 +0300 +Subject: [PATCH] wifi: ath11k: print a warning when crypto_alloc_shash() fails + +Christoph reported that ath11k failed to initialise when michael_mic.ko +module was not installed. To make it easier to notice that case print a +warning when crypto_alloc_shash() fails. + +Compile tested only. + +Reported-by: Christoph Hellwig +Link: https://lore.kernel.org/all/20221130133016.GC3055@lst.de/ +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405090425.1351-1-kvalo@kernel.org +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -3106,8 +3106,11 @@ int ath11k_peer_rx_frag_setup(struct ath + int i; + + tfm = crypto_alloc_shash("michael_mic", 0, 0); +- if (IS_ERR(tfm)) ++ if (IS_ERR(tfm)) { ++ ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n", ++ PTR_ERR(tfm)); + return PTR_ERR(tfm); ++ } + + spin_lock_bh(&ab->base_lock); + diff --git a/package/kernel/mac80211/patches/ath11k/0060-wifi-ath11k-Ignore-frags-from-uninitialized-peer-in-.patch b/package/kernel/mac80211/patches/ath11k/0060-wifi-ath11k-Ignore-frags-from-uninitialized-peer-in-.patch new file mode 100644 index 000000000..5bbf9e04a --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0060-wifi-ath11k-Ignore-frags-from-uninitialized-peer-in-.patch @@ -0,0 +1,104 @@ +From a06bfb3c9f69f303692cdae87bc0899d2ae8b2a6 Mon Sep 17 00:00:00 2001 +From: Harshitha Prem +Date: Tue, 4 Apr 2023 00:11:54 +0530 +Subject: [PATCH] wifi: ath11k: Ignore frags from uninitialized peer in dp. + +When max virtual ap interfaces are configured in all the bands with +ACS and hostapd restart is done every 60s, a crash is observed at +random times. +In this certain scenario, a fragmented packet is received for +self peer, for which rx_tid and rx_frags are not initialized in +datapath. While handling this fragment, crash is observed as the +rx_frag list is uninitialised and when we walk in +ath11k_dp_rx_h_sort_frags, skb null leads to exception. + +To address this, before processing received fragments we check +dp_setup_done flag is set to ensure that peer has completed its +dp peer setup for fragment queue, else ignore processing the +fragments. + +Call trace: + ath11k_dp_process_rx_err+0x550/0x1084 [ath11k] + ath11k_dp_service_srng+0x70/0x370 [ath11k] + 0xffffffc009693a04 + __napi_poll+0x30/0xa4 + net_rx_action+0x118/0x270 + __do_softirq+0x10c/0x244 + irq_exit+0x64/0xb4 + __handle_domain_irq+0x88/0xac + gic_handle_irq+0x74/0xbc + el1_irq+0xf0/0x1c0 + arch_cpu_idle+0x10/0x18 + do_idle+0x104/0x248 + cpu_startup_entry+0x20/0x64 + rest_init+0xd0/0xdc + arch_call_rest_init+0xc/0x14 + start_kernel+0x480/0x4b8 + Code: f9400281 f94066a2 91405021 b94a0023 (f9406401) + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Harshitha Prem +Signed-off-by: Nagarajan Maran +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403184155.8670-2-quic_nmaran@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp.c | 4 +++- + drivers/net/wireless/ath/ath11k/dp_rx.c | 8 ++++++++ + drivers/net/wireless/ath/ath11k/peer.h | 1 + + 3 files changed, 12 insertions(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/dp.c ++++ b/drivers/net/wireless/ath/ath11k/dp.c +@@ -36,6 +36,7 @@ void ath11k_dp_peer_cleanup(struct ath11 + } + + ath11k_peer_rx_tid_cleanup(ar, peer); ++ peer->dp_setup_done = false; + crypto_free_shash(peer->tfm_mmic); + spin_unlock_bh(&ab->base_lock); + } +@@ -72,7 +73,8 @@ int ath11k_dp_peer_setup(struct ath11k * + ret = ath11k_peer_rx_frag_setup(ar, addr, vdev_id); + if (ret) { + ath11k_warn(ab, "failed to setup rx defrag context\n"); +- return ret; ++ tid--; ++ goto peer_clean; + } + + /* TODO: Setup other peer specific resource used in data path */ +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -3130,6 +3130,7 @@ int ath11k_peer_rx_frag_setup(struct ath + } + + peer->tfm_mmic = tfm; ++ peer->dp_setup_done = true; + spin_unlock_bh(&ab->base_lock); + + return 0; +@@ -3575,6 +3576,13 @@ static int ath11k_dp_rx_frag_h_mpdu(stru + ret = -ENOENT; + goto out_unlock; + } ++ if (!peer->dp_setup_done) { ++ ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", ++ peer->addr, peer_id); ++ ret = -ENOENT; ++ goto out_unlock; ++ } ++ + rx_tid = &peer->rx_tid[tid]; + + if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || +--- a/drivers/net/wireless/ath/ath11k/peer.h ++++ b/drivers/net/wireless/ath/ath11k/peer.h +@@ -35,6 +35,7 @@ struct ath11k_peer { + u16 sec_type; + u16 sec_type_grp; + bool is_authorized; ++ bool dp_setup_done; + }; + + void ath11k_peer_unmap_event(struct ath11k_base *ab, u16 peer_id); diff --git a/package/kernel/mac80211/patches/ath11k/0061-wifi-ath11k-fix-undefined-behavior-with-__fls-in-dp.patch b/package/kernel/mac80211/patches/ath11k/0061-wifi-ath11k-fix-undefined-behavior-with-__fls-in-dp.patch new file mode 100644 index 000000000..d68c19f16 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0061-wifi-ath11k-fix-undefined-behavior-with-__fls-in-dp.patch @@ -0,0 +1,29 @@ +From 41e02bf4ae32cf2ac47b08b4caaa9c1a032e4ce7 Mon Sep 17 00:00:00 2001 +From: Harshitha Prem +Date: Tue, 4 Apr 2023 00:11:55 +0530 +Subject: [PATCH] wifi: ath11k: fix undefined behavior with __fls in dp + +"__fls" would have an undefined behavior if the argument is passed +as "0". Hence, added changes to handle the same. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Harshitha Prem +Signed-off-by: Nagarajan Maran +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403184155.8670-3-quic_nmaran@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -3598,7 +3598,7 @@ static int ath11k_dp_rx_frag_h_mpdu(stru + goto out_unlock; + } + +- if (frag_no > __fls(rx_tid->rx_frag_bitmap)) ++ if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap))) + __skb_queue_tail(&rx_tid->rx_frags, msdu); + else + ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu); diff --git a/package/kernel/mac80211/patches/ath11k/0062-wifi-ath11k-fix-double-free-of-peer-rx_tid-during-re.patch b/package/kernel/mac80211/patches/ath11k/0062-wifi-ath11k-fix-double-free-of-peer-rx_tid-during-re.patch new file mode 100644 index 000000000..dd37b1e4f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0062-wifi-ath11k-fix-double-free-of-peer-rx_tid-during-re.patch @@ -0,0 +1,144 @@ +From 93a91f40c25c3d0e61f8540a7accf105090f9995 Mon Sep 17 00:00:00 2001 +From: Harshitha Prem +Date: Mon, 17 Apr 2023 13:35:00 +0300 +Subject: [PATCH] wifi: ath11k: fix double free of peer rx_tid during reo cmd + failure + +Peer rx_tid is locally copied thrice during peer_rx_tid_cleanup to +send REO_CMD_UPDATE_RX_QUEUE followed by REO_CMD_FLUSH_CACHE to flush +all aged REO descriptors from HW cache. + +When sending REO_CMD_FLUSH_CACHE fails, we do dma unmap of already +mapped rx_tid->vaddr and free it. This is not checked during +reo_cmd_list_cleanup() and dp_reo_cmd_free() before trying to free and +unmap again. + +Fix this by setting rx_tid->vaddr NULL in rx tid delete and also +wherever freeing it to check in reo_cmd_list_cleanup() and +reo_cmd_free() before trying to free again. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sathishkumar Muruganandam +Signed-off-by: Harshitha Prem +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403182420.23375-2-quic_hprem@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 43 ++++++++++++++++++------- + 1 file changed, 31 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -668,13 +668,18 @@ void ath11k_dp_reo_cmd_list_cleanup(stru + struct ath11k_dp *dp = &ab->dp; + struct dp_reo_cmd *cmd, *tmp; + struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; ++ struct dp_rx_tid *rx_tid; + + spin_lock_bh(&dp->reo_cmd_lock); + list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { + list_del(&cmd->list); +- dma_unmap_single(ab->dev, cmd->data.paddr, +- cmd->data.size, DMA_BIDIRECTIONAL); +- kfree(cmd->data.vaddr); ++ rx_tid = &cmd->data; ++ if (rx_tid->vaddr) { ++ dma_unmap_single(ab->dev, rx_tid->paddr, ++ rx_tid->size, DMA_BIDIRECTIONAL); ++ kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; ++ } + kfree(cmd); + } + +@@ -682,9 +687,13 @@ void ath11k_dp_reo_cmd_list_cleanup(stru + &dp->reo_cmd_cache_flush_list, list) { + list_del(&cmd_cache->list); + dp->reo_cmd_cache_flush_count--; +- dma_unmap_single(ab->dev, cmd_cache->data.paddr, +- cmd_cache->data.size, DMA_BIDIRECTIONAL); +- kfree(cmd_cache->data.vaddr); ++ rx_tid = &cmd_cache->data; ++ if (rx_tid->vaddr) { ++ dma_unmap_single(ab->dev, rx_tid->paddr, ++ rx_tid->size, DMA_BIDIRECTIONAL); ++ kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; ++ } + kfree(cmd_cache); + } + spin_unlock_bh(&dp->reo_cmd_lock); +@@ -698,10 +707,12 @@ static void ath11k_dp_reo_cmd_free(struc + if (status != HAL_REO_CMD_SUCCESS) + ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", + rx_tid->tid, status); +- +- dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, +- DMA_BIDIRECTIONAL); +- kfree(rx_tid->vaddr); ++ if (rx_tid->vaddr) { ++ dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, ++ DMA_BIDIRECTIONAL); ++ kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; ++ } + } + + static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, +@@ -740,6 +751,7 @@ static void ath11k_dp_reo_cache_flush(st + dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, + DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; + } + } + +@@ -792,6 +804,7 @@ free_desc: + dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, + DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; + } + + void ath11k_peer_rx_tid_delete(struct ath11k *ar, +@@ -804,6 +817,8 @@ void ath11k_peer_rx_tid_delete(struct at + if (!rx_tid->active) + return; + ++ rx_tid->active = false; ++ + cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; + cmd.addr_lo = lower_32_bits(rx_tid->paddr); + cmd.addr_hi = upper_32_bits(rx_tid->paddr); +@@ -818,9 +833,11 @@ void ath11k_peer_rx_tid_delete(struct at + dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, + DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; + } + +- rx_tid->active = false; ++ rx_tid->paddr = 0; ++ rx_tid->size = 0; + } + + static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, +@@ -967,6 +984,7 @@ static void ath11k_dp_rx_tid_mem_free(st + dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, + DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; + + rx_tid->active = false; + +@@ -1067,7 +1085,8 @@ int ath11k_peer_rx_tid_setup(struct ath1 + return ret; + + err_mem_free: +- kfree(vaddr); ++ kfree(rx_tid->vaddr); ++ rx_tid->vaddr = NULL; + + return ret; + } diff --git a/package/kernel/mac80211/patches/ath11k/0063-wifi-ath11k-Prevent-REO-cmd-failures.patch b/package/kernel/mac80211/patches/ath11k/0063-wifi-ath11k-Prevent-REO-cmd-failures.patch new file mode 100644 index 000000000..4b9af1806 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0063-wifi-ath11k-Prevent-REO-cmd-failures.patch @@ -0,0 +1,43 @@ +From a8ae833657a45746debde85c38bb7f070d344026 Mon Sep 17 00:00:00 2001 +From: Harshitha Prem +Date: Mon, 17 Apr 2023 13:35:01 +0300 +Subject: [PATCH] wifi: ath11k: Prevent REO cmd failures + +Prevent REO cmd failures causing double free by increasing REO cmd +ring size and moving REO status ring mask to IRQ group 3 from group +0 to separate from tx completion ring on IRQ group 0 which may delay +reo status processing. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sathishkumar Muruganandam +Signed-off-by: Harshitha Prem +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403182420.23375-3-quic_hprem@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp.h | 2 +- + drivers/net/wireless/ath/ath11k/hw.c | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/dp.h ++++ b/drivers/net/wireless/ath/ath11k/dp.h +@@ -214,7 +214,7 @@ struct ath11k_pdev_dp { + #define DP_REO_REINJECT_RING_SIZE 32 + #define DP_RX_RELEASE_RING_SIZE 1024 + #define DP_REO_EXCEPTION_RING_SIZE 128 +-#define DP_REO_CMD_RING_SIZE 128 ++#define DP_REO_CMD_RING_SIZE 256 + #define DP_REO_STATUS_RING_SIZE 2048 + #define DP_RXDMA_BUF_RING_SIZE 4096 + #define DP_RXDMA_REFILL_RING_SIZE 2048 +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -1233,6 +1233,7 @@ const struct ath11k_hw_ring_mask ath11k_ + ATH11K_RX_WBM_REL_RING_MASK_0, + }, + .reo_status = { ++ 0, 0, 0, + ATH11K_REO_STATUS_RING_MASK_0, + }, + .rxdma2host = { diff --git a/package/kernel/mac80211/patches/ath11k/0064-wifi-ath11k-add-peer-mac-information-in-failure-case.patch b/package/kernel/mac80211/patches/ath11k/0064-wifi-ath11k-add-peer-mac-information-in-failure-case.patch new file mode 100644 index 000000000..fbcbdfff7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0064-wifi-ath11k-add-peer-mac-information-in-failure-case.patch @@ -0,0 +1,74 @@ +From 20487cc3ff36bbfa9505f0a078ba98f09abfc717 Mon Sep 17 00:00:00 2001 +From: Harshitha Prem +Date: Mon, 17 Apr 2023 13:35:01 +0300 +Subject: [PATCH] wifi: ath11k: add peer mac information in failure cases + +During reo command failure, the peer mac detail for which the reo +command was not successful is unknown. Hence, to improve the +debuggability, add the peer mac information in the failure cases +which would be useful during multi client cases. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sathishkumar Muruganandam +Signed-off-by: Harshitha Prem +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403182420.23375-4-quic_hprem@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 16 ++++++++++------ + 1 file changed, 10 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -1009,7 +1009,8 @@ int ath11k_peer_rx_tid_setup(struct ath1 + + peer = ath11k_peer_find(ab, vdev_id, peer_mac); + if (!peer) { +- ath11k_warn(ab, "failed to find the peer to set up rx tid\n"); ++ ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n", ++ peer_mac); + spin_unlock_bh(&ab->base_lock); + return -ENOENT; + } +@@ -1022,7 +1023,8 @@ int ath11k_peer_rx_tid_setup(struct ath1 + ba_win_sz, ssn, true); + spin_unlock_bh(&ab->base_lock); + if (ret) { +- ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid); ++ ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d", ++ peer_mac, tid, ret); + return ret; + } + +@@ -1030,8 +1032,8 @@ int ath11k_peer_rx_tid_setup(struct ath1 + peer_mac, paddr, + tid, 1, ba_win_sz); + if (ret) +- ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n", +- tid, ret); ++ ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n", ++ peer_mac, tid, ret); + return ret; + } + +@@ -1064,6 +1066,8 @@ int ath11k_peer_rx_tid_setup(struct ath1 + ret = dma_mapping_error(ab->dev, paddr); + if (ret) { + spin_unlock_bh(&ab->base_lock); ++ ath11k_warn(ab, "failed to setup dma map for peer %pM rx tid %d: %d\n", ++ peer_mac, tid, ret); + goto err_mem_free; + } + +@@ -1077,8 +1081,8 @@ int ath11k_peer_rx_tid_setup(struct ath1 + ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, + paddr, tid, 1, ba_win_sz); + if (ret) { +- ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n", +- tid, ret); ++ ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n", ++ peer_mac, tid, ret); + ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); + } + diff --git a/package/kernel/mac80211/patches/ath11k/0065-wifi-ath11k-fix-tx-status-reporting-in-encap-offload.patch b/package/kernel/mac80211/patches/ath11k/0065-wifi-ath11k-fix-tx-status-reporting-in-encap-offload.patch new file mode 100644 index 000000000..e2fe41915 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0065-wifi-ath11k-fix-tx-status-reporting-in-encap-offload.patch @@ -0,0 +1,119 @@ +From 6257c702264c44d74c6b71f0c62a7665da2dc356 Mon Sep 17 00:00:00 2001 +From: Pradeep Kumar Chitrapu +Date: Mon, 17 Apr 2023 13:35:02 +0300 +Subject: [PATCH] wifi: ath11k: fix tx status reporting in encap offload mode + +ieee80211_tx_status() treats packets in 802.11 frame format and +tries to extract sta address from packet header. When tx encap +offload is enabled, this becomes invalid operation. Hence, switch +to using ieee80211_tx_status_ext() after filling in station +address for handling both 802.11 and 802.3 frames. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Pradeep Kumar Chitrapu +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403195738.25367-2-quic_pradeepc@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp.h | 4 +++ + drivers/net/wireless/ath/ath11k/dp_tx.c | 33 ++++++++++++++++++++++++- + drivers/net/wireless/ath/ath11k/dp_tx.h | 1 + + 3 files changed, 37 insertions(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/dp.h ++++ b/drivers/net/wireless/ath/ath11k/dp.h +@@ -303,12 +303,16 @@ struct ath11k_dp { + + #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 + ++#define HTT_INVALID_PEER_ID 0xffff ++ + /* HTT tx completion is overlaid in wbm_release_ring */ + #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) + #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) + #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) + + #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) ++#define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0) ++#define HTT_TX_WBM_COMP_INFO2_VALID BIT(21) + + struct htt_tx_wbm_completion { + u32 info0; +--- a/drivers/net/wireless/ath/ath11k/dp_tx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_tx.c +@@ -316,10 +316,12 @@ ath11k_dp_tx_htt_tx_complete_buf(struct + struct dp_tx_ring *tx_ring, + struct ath11k_dp_htt_wbm_tx_status *ts) + { ++ struct ieee80211_tx_status status = { 0 }; + struct sk_buff *msdu; + struct ieee80211_tx_info *info; + struct ath11k_skb_cb *skb_cb; + struct ath11k *ar; ++ struct ath11k_peer *peer; + + spin_lock(&tx_ring->tx_idr_lock); + msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); +@@ -341,6 +343,11 @@ ath11k_dp_tx_htt_tx_complete_buf(struct + + dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); + ++ if (!skb_cb->vif) { ++ dev_kfree_skb_any(msdu); ++ return; ++ } ++ + memset(&info->status, 0, sizeof(info->status)); + + if (ts->acked) { +@@ -355,7 +362,23 @@ ath11k_dp_tx_htt_tx_complete_buf(struct + } + } + +- ieee80211_tx_status(ar->hw, msdu); ++ spin_lock_bh(&ab->base_lock); ++ peer = ath11k_peer_find_by_id(ab, ts->peer_id); ++ if (!peer || !peer->sta) { ++ ath11k_dbg(ab, ATH11K_DBG_DATA, ++ "dp_tx: failed to find the peer with peer_id %d\n", ++ ts->peer_id); ++ spin_unlock_bh(&ab->base_lock); ++ dev_kfree_skb_any(msdu); ++ return; ++ } ++ spin_unlock_bh(&ab->base_lock); ++ ++ status.sta = peer->sta; ++ status.info = info; ++ status.skb = msdu; ++ ++ ieee80211_tx_status_ext(ar->hw, &status); + } + + static void +@@ -379,7 +402,15 @@ ath11k_dp_tx_process_htt_tx_complete(str + ts.msdu_id = msdu_id; + ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, + status_desc->info1); ++ ++ if (FIELD_GET(HTT_TX_WBM_COMP_INFO2_VALID, status_desc->info2)) ++ ts.peer_id = FIELD_GET(HTT_TX_WBM_COMP_INFO2_SW_PEER_ID, ++ status_desc->info2); ++ else ++ ts.peer_id = HTT_INVALID_PEER_ID; ++ + ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); ++ + break; + case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: + case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: +--- a/drivers/net/wireless/ath/ath11k/dp_tx.h ++++ b/drivers/net/wireless/ath/ath11k/dp_tx.h +@@ -13,6 +13,7 @@ struct ath11k_dp_htt_wbm_tx_status { + u32 msdu_id; + bool acked; + int ack_rssi; ++ u16 peer_id; + }; + + void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts); diff --git a/package/kernel/mac80211/patches/ath11k/0066-wifi-ath11k-Fix-incorrect-update-of-radiotap-fields.patch b/package/kernel/mac80211/patches/ath11k/0066-wifi-ath11k-Fix-incorrect-update-of-radiotap-fields.patch new file mode 100644 index 000000000..4f9458010 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0066-wifi-ath11k-Fix-incorrect-update-of-radiotap-fields.patch @@ -0,0 +1,49 @@ +From 2f0c9ac8362da09c80f1cd422ef7fd6fa9b252b9 Mon Sep 17 00:00:00 2001 +From: Pradeep Kumar Chitrapu +Date: Mon, 17 Apr 2023 13:35:02 +0300 +Subject: [PATCH] wifi: ath11k: Fix incorrect update of radiotap fields + +Fix incorrect update of ppdu stats causing incorrect radiotap +fields. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Pradeep Kumar Chitrapu +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403195738.25367-3-quic_pradeepc@quicinc.com +--- + drivers/net/wireless/ath/ath11k/hal_rx.c | 4 ++-- + drivers/net/wireless/ath/ath11k/hal_rx.h | 2 +- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/hal_rx.c ++++ b/drivers/net/wireless/ath/ath11k/hal_rx.c +@@ -1029,7 +1029,7 @@ ath11k_hal_rx_parse_mon_status_tlv(struc + info1 = __le32_to_cpu(vht_sig->info1); + + ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, +- info0); ++ info1); + ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS, + info1); + gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING, +@@ -1452,7 +1452,7 @@ ath11k_hal_rx_parse_mon_status_tlv(struc + * PHYRX_OTHER_RECEIVE_INFO TLV. + */ + ppdu_info->rssi_comb = +- FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB, ++ FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB, + __le32_to_cpu(rssi->info0)); + + if (db2dbm) { +--- a/drivers/net/wireless/ath/ath11k/hal_rx.h ++++ b/drivers/net/wireless/ath/ath11k/hal_rx.h +@@ -385,7 +385,7 @@ struct hal_rx_he_sig_b2_ofdma_info { + __le32 info0; + } __packed; + +-#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8) ++#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB GENMASK(15, 8) + + #define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 GENMASK(7, 0) + diff --git a/package/kernel/mac80211/patches/ath11k/0067-wifi-ath11k-Fix-SKB-corruption-in-REO-destination-ri.patch b/package/kernel/mac80211/patches/ath11k/0067-wifi-ath11k-Fix-SKB-corruption-in-REO-destination-ri.patch new file mode 100644 index 000000000..8b300f3a7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0067-wifi-ath11k-Fix-SKB-corruption-in-REO-destination-ri.patch @@ -0,0 +1,70 @@ +From f9fff67d2d7ca6fa8066132003a3deef654c55b1 Mon Sep 17 00:00:00 2001 +From: Nagarajan Maran +Date: Mon, 17 Apr 2023 13:35:02 +0300 +Subject: [PATCH] wifi: ath11k: Fix SKB corruption in REO destination ring + +While running traffics for a long time, randomly an RX descriptor +filled with value "0" from REO destination ring is received. +This descriptor which is invalid causes the wrong SKB (SKB stored in +the IDR lookup with buffer id "0") to be fetched which in turn +causes SKB memory corruption issue and the same leads to crash +after some time. + +Changed the start id for idr allocation to "1" and the buffer id "0" +is reserved for error validation. Introduced Sanity check to validate +the descriptor, before processing the SKB. + +Crash Signature : + +Unable to handle kernel paging request at virtual address 3f004900 +PC points to "b15_dma_inv_range+0x30/0x50" +LR points to "dma_cache_maint_page+0x8c/0x128". +The Backtrace obtained is as follows: +[<8031716c>] (b15_dma_inv_range) from [<80313a4c>] (dma_cache_maint_page+0x8c/0x128) +[<80313a4c>] (dma_cache_maint_page) from [<80313b90>] (__dma_page_dev_to_cpu+0x28/0xcc) +[<80313b90>] (__dma_page_dev_to_cpu) from [<7fb5dd68>] (ath11k_dp_process_rx+0x1e8/0x4a4 [ath11k]) +[<7fb5dd68>] (ath11k_dp_process_rx [ath11k]) from [<7fb53c20>] (ath11k_dp_service_srng+0xb0/0x2ac [ath11k]) +[<7fb53c20>] (ath11k_dp_service_srng [ath11k]) from [<7f67bba4>] (ath11k_pci_ext_grp_napi_poll+0x1c/0x78 [ath11k_pci]) +[<7f67bba4>] (ath11k_pci_ext_grp_napi_poll [ath11k_pci]) from [<807d5cf4>] (__napi_poll+0x28/0xb8) +[<807d5cf4>] (__napi_poll) from [<807d5f28>] (net_rx_action+0xf0/0x280) +[<807d5f28>] (net_rx_action) from [<80302148>] (__do_softirq+0xd0/0x280) +[<80302148>] (__do_softirq) from [<80320408>] (irq_exit+0x74/0xd4) +[<80320408>] (irq_exit) from [<803638a4>] (__handle_domain_irq+0x90/0xb4) +[<803638a4>] (__handle_domain_irq) from [<805bedec>] (gic_handle_irq+0x58/0x90) +[<805bedec>] (gic_handle_irq) from [<80301a78>] (__irq_svc+0x58/0x8c) + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Nagarajan Maran +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230403191533.28114-1-quic_nmaran@quicinc.com +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -389,10 +389,10 @@ int ath11k_dp_rxbufs_replenish(struct at + goto fail_free_skb; + + spin_lock_bh(&rx_ring->idr_lock); +- buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, +- rx_ring->bufs_max * 3, GFP_ATOMIC); ++ buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1, ++ (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC); + spin_unlock_bh(&rx_ring->idr_lock); +- if (buf_id < 0) ++ if (buf_id <= 0) + goto fail_dma_unmap; + + desc = ath11k_hal_srng_src_get_next_entry(ab, srng); +@@ -2665,6 +2665,9 @@ try_again: + cookie); + mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); + ++ if (unlikely(buf_id == 0)) ++ continue; ++ + ar = ab->pdevs[mac_id].ar; + rx_ring = &ar->dp.rx_refill_buf_ring; + spin_lock_bh(&rx_ring->idr_lock); diff --git a/package/kernel/mac80211/patches/ath11k/0068-wifi-ath11k-Remove-disabling-of-80-80-and-160-MHz.patch b/package/kernel/mac80211/patches/ath11k/0068-wifi-ath11k-Remove-disabling-of-80-80-and-160-MHz.patch new file mode 100644 index 000000000..ce5ffd273 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0068-wifi-ath11k-Remove-disabling-of-80-80-and-160-MHz.patch @@ -0,0 +1,49 @@ +From b100722a777f6455d913666a376f81342b2cb995 Mon Sep 17 00:00:00 2001 +From: Muna Sinada +Date: Mon, 17 Apr 2023 13:22:27 -0700 +Subject: [PATCH] wifi: ath11k: Remove disabling of 80+80 and 160 MHz + +This is a regression fix for 80+80 and 160 MHz support bits being +cleared, therefore not adverised. Remove disable of 80+80 and 160 MHz +capability flags and assign valid center frequency 2 similar to +VHT80_80. + +Fixes: 38dfe775d0ab ("wifi: ath11k: push MU-MIMO params from hostapd to hardware") +Reported-by: Robert Marko +Tested-by: Robert Marko # IPQ8074 WLAN.HK.2.9.0.1-01385-QCAHKSWPL_SILICONZ-1 +Link: https://bugzilla.kernel.org/show_bug.cgi?id=217299 +Co-developed-by: P Praneesh +Signed-off-by: P Praneesh +Signed-off-by: Muna Sinada +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/1681762947-13882-1-git-send-email-quic_msinada@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 4 ---- + drivers/net/wireless/ath/ath11k/wmi.c | 3 ++- + 2 files changed, 2 insertions(+), 5 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -5585,10 +5585,6 @@ static int ath11k_mac_copy_he_cap(struct + + he_cap_elem->mac_cap_info[1] &= + IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_MASK; +- he_cap_elem->phy_cap_info[0] &= +- ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; +- he_cap_elem->phy_cap_info[0] &= +- ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; + + he_cap_elem->phy_cap_info[5] &= + ~IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -871,7 +871,8 @@ static void ath11k_wmi_put_wmi_channel(s + + chan->band_center_freq2 = arg->channel.band_center_freq1; + +- } else if (arg->channel.mode == MODE_11AC_VHT80_80) { ++ } else if ((arg->channel.mode == MODE_11AC_VHT80_80) || ++ (arg->channel.mode == MODE_11AX_HE80_80)) { + chan->band_center_freq2 = arg->channel.band_center_freq2; + } else { + chan->band_center_freq2 = 0; diff --git a/package/kernel/mac80211/patches/ath11k/0069-wifi-ath11k-fix-registration-of-6Ghz-only-phy-withou.patch b/package/kernel/mac80211/patches/ath11k/0069-wifi-ath11k-fix-registration-of-6Ghz-only-phy-withou.patch new file mode 100644 index 000000000..32468dbc4 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0069-wifi-ath11k-fix-registration-of-6Ghz-only-phy-withou.patch @@ -0,0 +1,61 @@ +From e2ceb1de2f83aafd8003f0b72dfd4b7441e97d14 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon +Date: Fri, 21 Apr 2023 16:54:45 +0200 +Subject: [PATCH] wifi: ath11k: fix registration of 6Ghz-only phy without the + full channel range + +Because of what seems to be a typo, a 6Ghz-only phy for which the BDF +does not allow the 7115Mhz channel will fail to register: + + WARNING: CPU: 2 PID: 106 at net/wireless/core.c:907 wiphy_register+0x914/0x954 + Modules linked in: ath11k_pci sbsa_gwdt + CPU: 2 PID: 106 Comm: kworker/u8:5 Not tainted 6.3.0-rc7-next-20230418-00549-g1e096a17625a-dirty #9 + Hardware name: Freebox V7R Board (DT) + Workqueue: ath11k_qmi_driver_event ath11k_qmi_driver_event_work + pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + pc : wiphy_register+0x914/0x954 + lr : ieee80211_register_hw+0x67c/0xc10 + sp : ffffff800b123aa0 + x29: ffffff800b123aa0 x28: 0000000000000000 x27: 0000000000000000 + x26: 0000000000000000 x25: 0000000000000006 x24: ffffffc008d51418 + x23: ffffffc008cb0838 x22: ffffff80176c2460 x21: 0000000000000168 + x20: ffffff80176c0000 x19: ffffff80176c03e0 x18: 0000000000000014 + x17: 00000000cbef338c x16: 00000000d2a26f21 x15: 00000000ad6bb85f + x14: 0000000000000020 x13: 0000000000000020 x12: 00000000ffffffbd + x11: 0000000000000208 x10: 00000000fffffdf7 x9 : ffffffc009394718 + x8 : ffffff80176c0528 x7 : 000000007fffffff x6 : 0000000000000006 + x5 : 0000000000000005 x4 : ffffff800b304284 x3 : ffffff800b304284 + x2 : ffffff800b304d98 x1 : 0000000000000000 x0 : 0000000000000000 + Call trace: + wiphy_register+0x914/0x954 + ieee80211_register_hw+0x67c/0xc10 + ath11k_mac_register+0x7c4/0xe10 + ath11k_core_qmi_firmware_ready+0x1f4/0x570 + ath11k_qmi_driver_event_work+0x198/0x590 + process_one_work+0x1b8/0x328 + worker_thread+0x6c/0x414 + kthread+0x100/0x104 + ret_from_fork+0x10/0x20 + ---[ end trace 0000000000000000 ]--- + ath11k_pci 0002:01:00.0: ieee80211 registration failed: -22 + ath11k_pci 0002:01:00.0: failed register the radio with mac80211: -22 + ath11k_pci 0002:01:00.0: failed to create pdev core: -22 + +Signed-off-by: Maxime Bizon +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230421145445.2612280-1-mbizon@freebox.fr +--- + drivers/net/wireless/ath/ath11k/mac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -8892,7 +8892,7 @@ static int ath11k_mac_setup_channels_rat + } + + if (supported_bands & WMI_HOST_WLAN_5G_CAP) { +- if (reg_cap->high_5ghz_chan >= ATH11K_MAX_6G_FREQ) { ++ if (reg_cap->high_5ghz_chan >= ATH11K_MIN_6G_FREQ) { + channels = kmemdup(ath11k_6ghz_channels, + sizeof(ath11k_6ghz_channels), GFP_KERNEL); + if (!channels) { diff --git a/package/kernel/mac80211/patches/ath11k/0070-wifi-ath-work-around-false-positive-stringop-overrea.patch b/package/kernel/mac80211/patches/ath11k/0070-wifi-ath-work-around-false-positive-stringop-overrea.patch new file mode 100644 index 000000000..aa4df16a9 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0070-wifi-ath-work-around-false-positive-stringop-overrea.patch @@ -0,0 +1,84 @@ +From 695df2f417d25202bdac9cde3c82d2acb6492b4d Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Fri, 5 May 2023 16:11:25 +0300 +Subject: [PATCH] wifi: ath: work around false-positive stringop-overread + warning + +In a rare arm64 randconfig build, I got multiple warnings for ath11k +and ath12k: + +In function 'ath11k_peer_assoc_h_ht', + inlined from 'ath11k_peer_assoc_prepare' at drivers/net/wireless/ath/ath11k/mac.c:2665:2: +drivers/net/wireless/ath/ath11k/mac.c:1709:13: error: 'ath11k_peer_assoc_h_ht_masked' reading 10 bytes from a region of size 0 [-Werror=stringop-overread] + 1709 | if (ath11k_peer_assoc_h_ht_masked(ht_mcs_mask)) + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This happens whenever gcc-13 fails to inline one of the functions +that take a fixed-length array argument but gets passed a pointer. + +Change these functions to all take a regular pointer argument +instead. + +Signed-off-by: Arnd Bergmann +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230417205447.1800912-1-arnd@kernel.org +--- + drivers/net/wireless/ath/ath11k/mac.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -433,7 +433,7 @@ u8 ath11k_mac_bitrate_to_idx(const struc + } + + static u32 +-ath11k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN]) ++ath11k_mac_max_ht_nss(const u8 *ht_mcs_mask) + { + int nss; + +@@ -445,7 +445,7 @@ ath11k_mac_max_ht_nss(const u8 ht_mcs_ma + } + + static u32 +-ath11k_mac_max_vht_nss(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX]) ++ath11k_mac_max_vht_nss(const u16 *vht_mcs_mask) + { + int nss; + +@@ -457,7 +457,7 @@ ath11k_mac_max_vht_nss(const u16 vht_mcs + } + + static u32 +-ath11k_mac_max_he_nss(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) ++ath11k_mac_max_he_nss(const u16 *he_mcs_mask) + { + int nss; + +@@ -1658,7 +1658,7 @@ static void ath11k_peer_assoc_h_rates(st + } + + static bool +-ath11k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN]) ++ath11k_peer_assoc_h_ht_masked(const u8 *ht_mcs_mask) + { + int nss; + +@@ -1670,7 +1670,7 @@ ath11k_peer_assoc_h_ht_masked(const u8 h + } + + static bool +-ath11k_peer_assoc_h_vht_masked(const u16 vht_mcs_mask[]) ++ath11k_peer_assoc_h_vht_masked(const u16 *vht_mcs_mask) + { + int nss; + +@@ -2065,7 +2065,7 @@ static u16 ath11k_peer_assoc_h_he_limit( + } + + static bool +-ath11k_peer_assoc_h_he_masked(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) ++ath11k_peer_assoc_h_he_masked(const u16 *he_mcs_mask) + { + int nss; + diff --git a/package/kernel/mac80211/patches/ath11k/0071-wifi-ath11k-driver-settings-for-MBSSID-and-EMA.patch b/package/kernel/mac80211/patches/ath11k/0071-wifi-ath11k-driver-settings-for-MBSSID-and-EMA.patch new file mode 100644 index 000000000..bede4819c --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0071-wifi-ath11k-driver-settings-for-MBSSID-and-EMA.patch @@ -0,0 +1,133 @@ +From a08dbb04d7365a04d52882143cf196005bfc88c3 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:27 +0300 +Subject: [PATCH 71/77] wifi: ath11k: driver settings for MBSSID and EMA + +Advertise the driver support for multiple BSSID (MBSSID) and +enhanced multi-BSSID advertisements (EMA) by setting extended +capabilities. + +Configure mbssid_max_interfaces and ema_max_profile_periodicity +fields in structure wiphy which are used to advertise maximum number +of interfaces and profile periodicity supported by the driver. + +Add new WMI fields to configure maximum vdev count supported for +MBSSID and profile periodicity in case of EMA. +Setting WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET flag +indicates that the firmware should track and update the DTIM counts +for each non-transmitted profile. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Co-developed-by: John Crispin +Signed-off-by: John Crispin +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-2-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/hw.c | 3 +++ + drivers/net/wireless/ath/ath11k/hw.h | 1 + + drivers/net/wireless/ath/ath11k/mac.c | 7 +++++++ + drivers/net/wireless/ath/ath11k/wmi.c | 3 +++ + drivers/net/wireless/ath/ath11k/wmi.h | 6 ++++++ + 5 files changed, 20 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -202,6 +202,9 @@ static void ath11k_init_wmi_config_ipq80 + config->twt_ap_sta_count = 1000; + config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; + config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI; ++ config->ema_max_vap_cnt = ab->num_radios; ++ config->ema_max_profile_period = TARGET_EMA_MAX_PROFILE_PERIOD; ++ config->beacon_tx_offload_max_vdev += config->ema_max_vap_cnt; + } + + static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -64,6 +64,7 @@ + #define TARGET_NUM_WDS_ENTRIES 32 + #define TARGET_DMA_BURST_SIZE 1 + #define TARGET_RX_BATCHMODE 1 ++#define TARGET_EMA_MAX_PROFILE_PERIOD 8 + + #define ATH11K_HW_MAX_QUEUES 4 + #define ATH11K_QUEUE_LEN 4096 +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -9001,19 +9001,23 @@ static int ath11k_mac_setup_iface_combin + + static const u8 ath11k_if_types_ext_capa[] = { + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, ++ [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, + [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, + }; + + static const u8 ath11k_if_types_ext_capa_sta[] = { + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, ++ [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, + [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, + [9] = WLAN_EXT_CAPA10_TWT_REQUESTER_SUPPORT, + }; + + static const u8 ath11k_if_types_ext_capa_ap[] = { + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, ++ [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, + [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, + [9] = WLAN_EXT_CAPA10_TWT_RESPONDER_SUPPORT, ++ [10] = WLAN_EXT_CAPA11_EMA_SUPPORT, + }; + + static const struct wiphy_iftype_ext_capab ath11k_iftypes_ext_capa[] = { +@@ -9251,6 +9255,9 @@ static int __ath11k_mac_register(struct + wiphy_ext_feature_set(ar->hw->wiphy, + NL80211_EXT_FEATURE_ENABLE_FTM_RESPONDER); + ++ ar->hw->wiphy->mbssid_max_interfaces = TARGET_NUM_VDEVS(ab); ++ ar->hw->wiphy->ema_max_profile_periodicity = TARGET_EMA_MAX_PROFILE_PERIOD; ++ + ath11k_reg_init(ar); + + if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -3987,6 +3987,9 @@ ath11k_wmi_copy_resource_config(struct w + ~(1 << WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT); + wmi_cfg->host_service_flags |= (tg_cfg->is_reg_cc_ext_event_supported << + WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT); ++ wmi_cfg->flags2 = WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET; ++ wmi_cfg->ema_max_vap_cnt = tg_cfg->ema_max_vap_cnt; ++ wmi_cfg->ema_max_profile_period = tg_cfg->ema_max_profile_period; + } + + static int ath11k_init_cmd_send(struct ath11k_pdev_wmi *wmi, +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2317,6 +2317,7 @@ struct wmi_init_cmd { + } __packed; + + #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) ++#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9) + #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) + + #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 +@@ -2389,6 +2390,9 @@ struct wmi_resource_config { + u32 msdu_flow_override_config1; + u32 flags2; + u32 host_service_flags; ++ u32 max_rnr_neighbours; ++ u32 ema_max_vap_cnt; ++ u32 ema_max_profile_period; + } __packed; + + struct wmi_service_ready_event { +@@ -5646,6 +5650,8 @@ struct target_resource_config { + u32 twt_ap_pdev_count; + u32 twt_ap_sta_count; + u8 is_reg_cc_ext_event_supported; ++ u32 ema_max_vap_cnt; ++ u32 ema_max_profile_period; + }; + + enum wmi_debug_log_param { diff --git a/package/kernel/mac80211/patches/ath11k/0072-wifi-ath11k-MBSSID-configuration-during-vdev-create-.patch b/package/kernel/mac80211/patches/ath11k/0072-wifi-ath11k-MBSSID-configuration-during-vdev-create-.patch new file mode 100644 index 000000000..4ba071731 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0072-wifi-ath11k-MBSSID-configuration-during-vdev-create-.patch @@ -0,0 +1,215 @@ +From 5a81610acf66c4ad6e1a1fbd09f3f555fca863b1 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:27 +0300 +Subject: [PATCH 72/77] wifi: ath11k: MBSSID configuration during vdev + create/start + +Configure multiple BSSID flags and index of the transmitting interface +in vdev create/start commands depending on the service bit +WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Co-developed-by: John Crispin +Signed-off-by: John Crispin +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-3-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 70 +++++++++++++++++++++++++-- + drivers/net/wireless/ath/ath11k/wmi.c | 5 ++ + drivers/net/wireless/ath/ath11k/wmi.h | 19 ++++++++ + 3 files changed, 90 insertions(+), 4 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -6181,17 +6181,62 @@ static void ath11k_mac_op_stop(struct ie + atomic_set(&ar->num_pending_mgmt_tx, 0); + } + +-static void +-ath11k_mac_setup_vdev_create_params(struct ath11k_vif *arvif, +- struct vdev_create_params *params) ++static int ath11k_mac_setup_vdev_params_mbssid(struct ath11k_vif *arvif, ++ u32 *flags, u32 *tx_vdev_id) ++{ ++ struct ath11k *ar = arvif->ar; ++ struct ath11k_vif *tx_arvif; ++ struct ieee80211_vif *tx_vif; ++ ++ *tx_vdev_id = 0; ++ tx_vif = arvif->vif->mbssid_tx_vif; ++ if (!tx_vif) { ++ *flags = WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP; ++ return 0; ++ } ++ ++ tx_arvif = (void *)tx_vif->drv_priv; ++ ++ if (arvif->vif->bss_conf.nontransmitted) { ++ if (ar->hw->wiphy != ieee80211_vif_to_wdev(tx_vif)->wiphy) ++ return -EINVAL; ++ ++ *flags = WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP; ++ *tx_vdev_id = ath11k_vif_to_arvif(tx_vif)->vdev_id; ++ } else if (tx_arvif == arvif) { ++ *flags = WMI_HOST_VDEV_FLAGS_TRANSMIT_AP; ++ } else { ++ return -EINVAL; ++ } ++ ++ if (arvif->vif->bss_conf.ema_ap) ++ *flags |= WMI_HOST_VDEV_FLAGS_EMA_MODE; ++ ++ return 0; ++} ++ ++static int ath11k_mac_setup_vdev_create_params(struct ath11k_vif *arvif, ++ struct vdev_create_params *params) + { + struct ath11k *ar = arvif->ar; + struct ath11k_pdev *pdev = ar->pdev; ++ int ret; + + params->if_id = arvif->vdev_id; + params->type = arvif->vdev_type; + params->subtype = arvif->vdev_subtype; + params->pdev_id = pdev->pdev_id; ++ params->mbssid_flags = 0; ++ params->mbssid_tx_vdev_id = 0; ++ ++ if (!test_bit(WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT, ++ ar->ab->wmi_ab.svc_map)) { ++ ret = ath11k_mac_setup_vdev_params_mbssid(arvif, ++ ¶ms->mbssid_flags, ++ ¶ms->mbssid_tx_vdev_id); ++ if (ret) ++ return ret; ++ } + + if (pdev->cap.supported_bands & WMI_HOST_WLAN_2G_CAP) { + params->chains[NL80211_BAND_2GHZ].tx = ar->num_tx_chains; +@@ -6206,6 +6251,7 @@ ath11k_mac_setup_vdev_create_params(stru + params->chains[NL80211_BAND_6GHZ].tx = ar->num_tx_chains; + params->chains[NL80211_BAND_6GHZ].rx = ar->num_rx_chains; + } ++ return 0; + } + + static void ath11k_mac_op_update_vif_offload(struct ieee80211_hw *hw, +@@ -6500,7 +6546,12 @@ static int ath11k_mac_op_add_interface(s + for (i = 0; i < ARRAY_SIZE(vif->hw_queue); i++) + vif->hw_queue[i] = i % (ATH11K_HW_MAX_QUEUES - 1); + +- ath11k_mac_setup_vdev_create_params(arvif, &vdev_param); ++ ret = ath11k_mac_setup_vdev_create_params(arvif, &vdev_param); ++ if (ret) { ++ ath11k_warn(ab, "failed to create vdev parameters %d: %d\n", ++ arvif->vdev_id, ret); ++ goto err; ++ } + + ret = ath11k_wmi_vdev_create(ar, vif->addr, &vdev_param); + if (ret) { +@@ -6905,6 +6956,17 @@ ath11k_mac_vdev_start_restart(struct ath + arg.pref_tx_streams = ar->num_tx_chains; + arg.pref_rx_streams = ar->num_rx_chains; + ++ arg.mbssid_flags = 0; ++ arg.mbssid_tx_vdev_id = 0; ++ if (test_bit(WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT, ++ ar->ab->wmi_ab.svc_map)) { ++ ret = ath11k_mac_setup_vdev_params_mbssid(arvif, ++ &arg.mbssid_flags, ++ &arg.mbssid_tx_vdev_id); ++ if (ret) ++ return ret; ++ } ++ + if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { + arg.ssid = arvif->u.ap.ssid; + arg.ssid_len = arvif->u.ap.ssid_len; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -724,6 +724,9 @@ int ath11k_wmi_vdev_create(struct ath11k + cmd->vdev_subtype = param->subtype; + cmd->num_cfg_txrx_streams = WMI_NUM_SUPPORTED_BAND_MAX; + cmd->pdev_id = param->pdev_id; ++ cmd->mbssid_flags = param->mbssid_flags; ++ cmd->mbssid_tx_vdev_id = param->mbssid_tx_vdev_id; ++ + ether_addr_copy(cmd->vdev_macaddr.addr, macaddr); + + ptr = skb->data + sizeof(*cmd); +@@ -941,6 +944,8 @@ int ath11k_wmi_vdev_start(struct ath11k + cmd->cac_duration_ms = arg->cac_duration_ms; + cmd->regdomain = arg->regdomain; + cmd->he_ops = arg->he_ops; ++ cmd->mbssid_flags = arg->mbssid_flags; ++ cmd->mbssid_tx_vdev_id = arg->mbssid_tx_vdev_id; + + if (!restart) { + if (arg->ssid) { +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -137,6 +137,14 @@ enum { + WMI_AUTORATE_3200NS_GI = BIT(11), + }; + ++enum { ++ WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, ++ WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, ++ WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, ++ WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, ++ WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, ++}; ++ + /* + * wmi command groups. + */ +@@ -2096,6 +2104,7 @@ enum wmi_tlv_service { + WMI_TLV_SERVICE_EXT2_MSG = 220, + WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, + WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, ++ WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, + WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, + + /* The second 128 bits */ +@@ -2583,6 +2592,8 @@ struct vdev_create_params { + u8 rx; + } chains[NUM_NL80211_BANDS]; + u32 pdev_id; ++ u32 mbssid_flags; ++ u32 mbssid_tx_vdev_id; + }; + + struct wmi_vdev_create_cmd { +@@ -2593,6 +2604,8 @@ struct wmi_vdev_create_cmd { + struct wmi_mac_addr vdev_macaddr; + u32 num_cfg_txrx_streams; + u32 pdev_id; ++ u32 mbssid_flags; ++ u32 mbssid_tx_vdev_id; + } __packed; + + struct wmi_vdev_txrx_streams { +@@ -2656,6 +2669,9 @@ struct wmi_vdev_start_request_cmd { + u32 he_ops; + u32 cac_duration_ms; + u32 regdomain; ++ u32 min_data_rate; ++ u32 mbssid_flags; ++ u32 mbssid_tx_vdev_id; + } __packed; + + #define MGMT_TX_DL_FRM_LEN 64 +@@ -2825,6 +2841,9 @@ struct wmi_vdev_start_req_arg { + u32 pref_rx_streams; + u32 pref_tx_streams; + u32 num_noa_descriptors; ++ u32 min_data_rate; ++ u32 mbssid_flags; ++ u32 mbssid_tx_vdev_id; + }; + + struct peer_create_params { diff --git a/package/kernel/mac80211/patches/ath11k/0073-wifi-ath11k-rename-MBSSID-fields-in-wmi_vdev_up_cmd.patch b/package/kernel/mac80211/patches/ath11k/0073-wifi-ath11k-rename-MBSSID-fields-in-wmi_vdev_up_cmd.patch new file mode 100644 index 000000000..023a1dbb9 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0073-wifi-ath11k-rename-MBSSID-fields-in-wmi_vdev_up_cmd.patch @@ -0,0 +1,52 @@ +From cf604e72bc6e6db68c7fcaa8779b03ec14b8d2fa Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:27 +0300 +Subject: [PATCH 73/77] wifi: ath11k: rename MBSSID fields in wmi_vdev_up_cmd + +Rename trans_bssid to tx_vdev_bssid to make it similar to vdev_bssid. + +Rename profile_num to nontx_profile_cnt, and profile_idx to +nontx_profile_idx which makes it clear that these store configurations +related to MBSSID non-transmitting profiles. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-4-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/wmi.c | 6 +++--- + drivers/net/wireless/ath/ath11k/wmi.h | 6 +++--- + 2 files changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -1029,10 +1029,10 @@ int ath11k_wmi_vdev_up(struct ath11k *ar + bss_conf = &arvif->vif->bss_conf; + + if (bss_conf->nontransmitted) { +- ether_addr_copy(cmd->trans_bssid.addr, ++ ether_addr_copy(cmd->tx_vdev_bssid.addr, + bss_conf->transmitter_bssid); +- cmd->profile_idx = bss_conf->bssid_index; +- cmd->profile_num = bss_conf->bssid_indicator; ++ cmd->nontx_profile_idx = bss_conf->bssid_index; ++ cmd->nontx_profile_cnt = bss_conf->bssid_indicator; + } + } + +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -2625,9 +2625,9 @@ struct wmi_vdev_up_cmd { + u32 vdev_id; + u32 vdev_assoc_id; + struct wmi_mac_addr vdev_bssid; +- struct wmi_mac_addr trans_bssid; +- u32 profile_idx; +- u32 profile_num; ++ struct wmi_mac_addr tx_vdev_bssid; ++ u32 nontx_profile_idx; ++ u32 nontx_profile_cnt; + } __packed; + + struct wmi_vdev_stop_cmd { diff --git a/package/kernel/mac80211/patches/ath11k/0074-wifi-ath11k-MBSSID-parameter-configuration-in-AP-mod.patch b/package/kernel/mac80211/patches/ath11k/0074-wifi-ath11k-MBSSID-parameter-configuration-in-AP-mod.patch new file mode 100644 index 000000000..d93e27dd4 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0074-wifi-ath11k-MBSSID-parameter-configuration-in-AP-mod.patch @@ -0,0 +1,138 @@ +From c82dc33f252fd8883be66f2d0230af0fd734c683 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:27 +0300 +Subject: [PATCH 74/77] wifi: ath11k: MBSSID parameter configuration in AP mode + +Include MBSSID parameters in WMI vdev up operation. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Co-developed-by: John Crispin +Signed-off-by: John Crispin +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-5-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 29 +++++++++++++++++++++------ + drivers/net/wireless/ath/ath11k/wmi.c | 8 +++++++- + drivers/net/wireless/ath/ath11k/wmi.h | 3 ++- + 3 files changed, 32 insertions(+), 8 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -964,7 +964,7 @@ static int ath11k_mac_monitor_vdev_start + return ret; + } + +- ret = ath11k_wmi_vdev_up(ar, vdev_id, 0, ar->mac_addr); ++ ret = ath11k_wmi_vdev_up(ar, vdev_id, 0, ar->mac_addr, NULL, 0, 0); + if (ret) { + ath11k_warn(ar->ab, "failed to put up monitor vdev %i: %d\n", + vdev_id, ret); +@@ -1423,6 +1423,7 @@ static void ath11k_control_beaconing(str + struct ieee80211_bss_conf *info) + { + struct ath11k *ar = arvif->ar; ++ struct ath11k_vif *tx_arvif = NULL; + int ret = 0; + + lockdep_assert_held(&arvif->ar->conf_mutex); +@@ -1451,8 +1452,14 @@ static void ath11k_control_beaconing(str + + ether_addr_copy(arvif->bssid, info->bssid); + ++ if (arvif->vif->mbssid_tx_vif) ++ tx_arvif = (struct ath11k_vif *)arvif->vif->mbssid_tx_vif->drv_priv; ++ + ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, +- arvif->bssid); ++ arvif->bssid, ++ tx_arvif ? tx_arvif->bssid : NULL, ++ info->bssid_index, ++ 1 << info->bssid_indicator); + if (ret) { + ath11k_warn(ar->ab, "failed to bring up vdev %d: %i\n", + arvif->vdev_id, ret); +@@ -2879,7 +2886,8 @@ static void ath11k_bss_assoc(struct ieee + arvif->aid = vif->cfg.aid; + ether_addr_copy(arvif->bssid, bss_conf->bssid); + +- ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, arvif->aid, arvif->bssid); ++ ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, arvif->aid, arvif->bssid, ++ NULL, 0, 0); + if (ret) { + ath11k_warn(ar->ab, "failed to set vdev %d up: %d\n", + arvif->vdev_id, ret); +@@ -7133,7 +7141,8 @@ ath11k_mac_update_vif_chan(struct ath11k + int n_vifs) + { + struct ath11k_base *ab = ar->ab; +- struct ath11k_vif *arvif; ++ struct ath11k_vif *arvif, *tx_arvif = NULL; ++ struct ieee80211_vif *mbssid_tx_vif; + int ret; + int i; + bool monitor_vif = false; +@@ -7187,8 +7196,15 @@ ath11k_mac_update_vif_chan(struct ath11k + ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n", + ret); + ++ mbssid_tx_vif = arvif->vif->mbssid_tx_vif; ++ if (mbssid_tx_vif) ++ tx_arvif = (struct ath11k_vif *)mbssid_tx_vif->drv_priv; ++ + ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, +- arvif->bssid); ++ arvif->bssid, ++ tx_arvif ? tx_arvif->bssid : NULL, ++ arvif->vif->bss_conf.bssid_index, ++ 1 << arvif->vif->bss_conf.bssid_indicator); + if (ret) { + ath11k_warn(ab, "failed to bring vdev up %d: %d\n", + arvif->vdev_id, ret); +@@ -7306,7 +7322,8 @@ static int ath11k_start_vdev_delay(struc + } + + if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { +- ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, 0, ar->mac_addr); ++ ret = ath11k_wmi_vdev_up(ar, arvif->vdev_id, 0, ar->mac_addr, ++ NULL, 0, 0); + if (ret) { + ath11k_warn(ab, "failed put monitor up: %d\n", ret); + return ret; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -1001,7 +1001,8 @@ int ath11k_wmi_vdev_start(struct ath11k + return ret; + } + +-int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, const u8 *bssid) ++int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, const u8 *bssid, ++ u8 *tx_bssid, u32 nontx_profile_idx, u32 nontx_profile_cnt) + { + struct ath11k_pdev_wmi *wmi = ar->wmi; + struct wmi_vdev_up_cmd *cmd; +@@ -1025,6 +1026,11 @@ int ath11k_wmi_vdev_up(struct ath11k *ar + + ether_addr_copy(cmd->vdev_bssid.addr, bssid); + ++ cmd->nontx_profile_idx = nontx_profile_idx; ++ cmd->nontx_profile_cnt = nontx_profile_cnt; ++ if (tx_bssid) ++ ether_addr_copy(cmd->tx_vdev_bssid.addr, tx_bssid); ++ + if (arvif && arvif->vif->type == NL80211_IFTYPE_STATION) { + bss_conf = &arvif->vif->bss_conf; + +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -6301,7 +6301,8 @@ int ath11k_wmi_bcn_tmpl(struct ath11k *a + struct sk_buff *bcn); + int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id); + int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, +- const u8 *bssid); ++ const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx, ++ u32 nontx_profile_cnt); + int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id); + int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg, + bool restart); diff --git a/package/kernel/mac80211/patches/ath11k/0075-wifi-ath11k-refactor-vif-parameter-configurations.patch b/package/kernel/mac80211/patches/ath11k/0075-wifi-ath11k-refactor-vif-parameter-configurations.patch new file mode 100644 index 000000000..8509e5597 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0075-wifi-ath11k-refactor-vif-parameter-configurations.patch @@ -0,0 +1,86 @@ +From cb9bea773c85e372931cd7a177db4165adf29d95 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:28 +0300 +Subject: [PATCH 75/77] wifi: ath11k: refactor vif parameter configurations + +Security parameters for each non-transmitting profile can be +different when MBSSID is enabled and this information is included +in the MBSSID element in the Beacon frame. Current implementation +to set rsnie_present and wpaie_present does not parse this element +hence it applies only to the transmitting interface. + +Move the code to a separate function to make additions for +non-transmitting interfaces cleaner. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-6-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 41 ++++++++++++++++----------- + 1 file changed, 24 insertions(+), 17 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -1351,28 +1351,14 @@ err_mon_del: + return ret; + } + +-static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) ++static void ath11k_mac_set_vif_params(struct ath11k_vif *arvif, ++ struct sk_buff *bcn) + { +- struct ath11k *ar = arvif->ar; +- struct ath11k_base *ab = ar->ab; +- struct ieee80211_hw *hw = ar->hw; +- struct ieee80211_vif *vif = arvif->vif; +- struct ieee80211_mutable_offsets offs = {}; +- struct sk_buff *bcn; + struct ieee80211_mgmt *mgmt; + u8 *ies; +- int ret; +- +- if (arvif->vdev_type != WMI_VDEV_TYPE_AP) +- return 0; +- +- bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0); +- if (!bcn) { +- ath11k_warn(ab, "failed to get beacon template from mac80211\n"); +- return -EPERM; +- } + + ies = bcn->data + ieee80211_get_hdrlen_from_skb(bcn); ++ mgmt = (struct ieee80211_mgmt *)bcn->data; + ies += sizeof(mgmt->u.beacon); + + if (cfg80211_find_ie(WLAN_EID_RSN, ies, (skb_tail_pointer(bcn) - ies))) +@@ -1386,7 +1372,28 @@ static int ath11k_mac_setup_bcn_tmpl(str + arvif->wpaie_present = true; + else + arvif->wpaie_present = false; ++} ++ ++static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) ++{ ++ struct ath11k *ar = arvif->ar; ++ struct ath11k_base *ab = ar->ab; ++ struct ieee80211_hw *hw = ar->hw; ++ struct ieee80211_vif *vif = arvif->vif; ++ struct ieee80211_mutable_offsets offs = {}; ++ struct sk_buff *bcn; ++ int ret; ++ ++ if (arvif->vdev_type != WMI_VDEV_TYPE_AP) ++ return 0; ++ ++ bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0); ++ if (!bcn) { ++ ath11k_warn(ab, "failed to get beacon template from mac80211\n"); ++ return -EPERM; ++ } + ++ ath11k_mac_set_vif_params(arvif, bcn); + ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn); + + kfree_skb(bcn); diff --git a/package/kernel/mac80211/patches/ath11k/0076-wifi-ath11k-MBSSID-beacon-support.patch b/package/kernel/mac80211/patches/ath11k/0076-wifi-ath11k-MBSSID-beacon-support.patch new file mode 100644 index 000000000..d23ea8dee --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0076-wifi-ath11k-MBSSID-beacon-support.patch @@ -0,0 +1,190 @@ +From 335a92765d308dfe22826f5562cd4b4389b45e71 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:28 +0300 +Subject: [PATCH 76/77] wifi: ath11k: MBSSID beacon support + +- Split ath11k_mac_setup_bcn_tmpl() to move the beacon retrieval and + WMI command to a new function, ath11k_mac_setup_bcn_tmpl_legacy(). + In the original function add checks to use the transmitting interface + when MBSSID is enabled. +- Set rsnie_present and wpaie_present fields for the non-transmitting + interfaces when MBSSID is enabled. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Co-developed-by: John Crispin +Signed-off-by: John Crispin +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-7-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 116 ++++++++++++++++++++++++-- + drivers/net/wireless/ath/ath11k/wmi.c | 1 + + 2 files changed, 112 insertions(+), 5 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -1351,6 +1351,84 @@ err_mon_del: + return ret; + } + ++static void ath11k_mac_setup_nontx_vif_rsnie(struct ath11k_vif *arvif, ++ bool tx_arvif_rsnie_present, ++ const u8 *profile, u8 profile_len) ++{ ++ if (cfg80211_find_ie(WLAN_EID_RSN, profile, profile_len)) { ++ arvif->rsnie_present = true; ++ } else if (tx_arvif_rsnie_present) { ++ int i; ++ u8 nie_len; ++ const u8 *nie = cfg80211_find_ext_ie(WLAN_EID_EXT_NON_INHERITANCE, ++ profile, profile_len); ++ if (!nie) ++ return; ++ ++ nie_len = nie[1]; ++ nie += 2; ++ for (i = 0; i < nie_len; i++) { ++ if (nie[i] == WLAN_EID_RSN) { ++ arvif->rsnie_present = false; ++ break; ++ } ++ } ++ } ++} ++ ++static bool ath11k_mac_set_nontx_vif_params(struct ath11k_vif *tx_arvif, ++ struct ath11k_vif *arvif, ++ struct sk_buff *bcn) ++{ ++ struct ieee80211_mgmt *mgmt; ++ const u8 *ies, *profile, *next_profile; ++ int ies_len; ++ ++ ies = bcn->data + ieee80211_get_hdrlen_from_skb(bcn); ++ mgmt = (struct ieee80211_mgmt *)bcn->data; ++ ies += sizeof(mgmt->u.beacon); ++ ies_len = skb_tail_pointer(bcn) - ies; ++ ++ ies = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, ies, ies_len); ++ arvif->rsnie_present = tx_arvif->rsnie_present; ++ ++ while (ies) { ++ u8 mbssid_len; ++ ++ ies_len -= (2 + ies[1]); ++ mbssid_len = ies[1] - 1; ++ profile = &ies[3]; ++ ++ while (mbssid_len) { ++ u8 profile_len; ++ ++ profile_len = profile[1]; ++ next_profile = profile + (2 + profile_len); ++ mbssid_len -= (2 + profile_len); ++ ++ profile += 2; ++ profile_len -= (2 + profile[1]); ++ profile += (2 + profile[1]); /* nontx capabilities */ ++ profile_len -= (2 + profile[1]); ++ profile += (2 + profile[1]); /* SSID */ ++ if (profile[2] == arvif->vif->bss_conf.bssid_index) { ++ profile_len -= 5; ++ profile = profile + 5; ++ ath11k_mac_setup_nontx_vif_rsnie(arvif, ++ tx_arvif->rsnie_present, ++ profile, ++ profile_len); ++ return true; ++ } ++ profile = next_profile; ++ } ++ ies = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, profile, ++ ies_len); ++ } ++ ++ return false; ++} ++ + static void ath11k_mac_set_vif_params(struct ath11k_vif *arvif, + struct sk_buff *bcn) + { +@@ -1374,18 +1452,26 @@ static void ath11k_mac_set_vif_params(st + arvif->wpaie_present = false; + } + +-static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) ++static int ath11k_mac_setup_bcn_tmpl_mbssid(struct ath11k_vif *arvif) + { + struct ath11k *ar = arvif->ar; + struct ath11k_base *ab = ar->ab; ++ struct ath11k_vif *tx_arvif = arvif; + struct ieee80211_hw *hw = ar->hw; + struct ieee80211_vif *vif = arvif->vif; + struct ieee80211_mutable_offsets offs = {}; + struct sk_buff *bcn; + int ret; + +- if (arvif->vdev_type != WMI_VDEV_TYPE_AP) +- return 0; ++ if (arvif->vif->mbssid_tx_vif) { ++ tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv; ++ if (tx_arvif != arvif) { ++ ar = tx_arvif->ar; ++ ab = ar->ab; ++ hw = ar->hw; ++ vif = tx_arvif->vif; ++ } ++ } + + bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0); + if (!bcn) { +@@ -1393,9 +1479,12 @@ static int ath11k_mac_setup_bcn_tmpl(str + return -EPERM; + } + +- ath11k_mac_set_vif_params(arvif, bcn); +- ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn); ++ if (tx_arvif == arvif) ++ ath11k_mac_set_vif_params(tx_arvif, bcn); ++ else if (!ath11k_mac_set_nontx_vif_params(tx_arvif, arvif, bcn)) ++ return -EINVAL; + ++ ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn); + kfree_skb(bcn); + + if (ret) +@@ -1405,6 +1494,23 @@ static int ath11k_mac_setup_bcn_tmpl(str + return ret; + } + ++static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) ++{ ++ struct ieee80211_vif *vif = arvif->vif; ++ ++ if (arvif->vdev_type != WMI_VDEV_TYPE_AP) ++ return 0; ++ ++ /* Target does not expect beacon templates for the already up ++ * non-transmitting interfaces, and results in a crash if sent. ++ */ ++ if (vif->mbssid_tx_vif && ++ arvif != (void *)vif->mbssid_tx_vif->drv_priv && arvif->is_up) ++ return 0; ++ ++ return ath11k_mac_setup_bcn_tmpl_mbssid(arvif); ++} ++ + void ath11k_mac_bcn_tx_event(struct ath11k_vif *arvif) + { + struct ieee80211_vif *vif = arvif->vif; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -1737,6 +1737,7 @@ int ath11k_wmi_bcn_tmpl(struct ath11k *a + } + + cmd->buf_len = bcn->len; ++ cmd->mbssid_ie_offset = offs->mbssid_off; + + ptr = skb->data + sizeof(*cmd); + diff --git a/package/kernel/mac80211/patches/ath11k/0077-wifi-ath11k-EMA-beacon-support.patch b/package/kernel/mac80211/patches/ath11k/0077-wifi-ath11k-EMA-beacon-support.patch new file mode 100644 index 000000000..51353fa3e --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0077-wifi-ath11k-EMA-beacon-support.patch @@ -0,0 +1,156 @@ +From 87bd401138161008fdb82fbca6e213af117bfeb9 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Fri, 5 May 2023 16:11:28 +0300 +Subject: [PATCH 77/77] wifi: ath11k: EMA beacon support + +Add new function ath11k_mac_setup_bcn_tmpl_ema() which invokes the new +API provided by MAC80211 to retrieve EMA beacons. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aloka Dixit +Co-developed-by: John Crispin +Signed-off-by: John Crispin +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230405221648.17950-8-quic_alokad@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 59 ++++++++++++++++++++++++++- + drivers/net/wireless/ath/ath11k/wmi.c | 3 +- + drivers/net/wireless/ath/ath11k/wmi.h | 11 ++++- + 3 files changed, 70 insertions(+), 3 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -1452,6 +1452,60 @@ static void ath11k_mac_set_vif_params(st + arvif->wpaie_present = false; + } + ++static int ath11k_mac_setup_bcn_tmpl_ema(struct ath11k_vif *arvif) ++{ ++ struct ath11k_vif *tx_arvif; ++ struct ieee80211_ema_beacons *beacons; ++ int ret = 0; ++ bool nontx_vif_params_set = false; ++ u32 params = 0; ++ u8 i = 0; ++ ++ tx_arvif = (void *)arvif->vif->mbssid_tx_vif->drv_priv; ++ ++ beacons = ieee80211_beacon_get_template_ema_list(tx_arvif->ar->hw, ++ tx_arvif->vif, 0); ++ if (!beacons || !beacons->cnt) { ++ ath11k_warn(arvif->ar->ab, ++ "failed to get ema beacon templates from mac80211\n"); ++ return -EPERM; ++ } ++ ++ if (tx_arvif == arvif) ++ ath11k_mac_set_vif_params(tx_arvif, beacons->bcn[0].skb); ++ else ++ arvif->wpaie_present = tx_arvif->wpaie_present; ++ ++ for (i = 0; i < beacons->cnt; i++) { ++ if (tx_arvif != arvif && !nontx_vif_params_set) ++ nontx_vif_params_set = ++ ath11k_mac_set_nontx_vif_params(tx_arvif, arvif, ++ beacons->bcn[i].skb); ++ ++ params = beacons->cnt; ++ params |= (i << WMI_EMA_TMPL_IDX_SHIFT); ++ params |= ((!i ? 1 : 0) << WMI_EMA_FIRST_TMPL_SHIFT); ++ params |= ((i + 1 == beacons->cnt ? 1 : 0) << WMI_EMA_LAST_TMPL_SHIFT); ++ ++ ret = ath11k_wmi_bcn_tmpl(tx_arvif->ar, tx_arvif->vdev_id, ++ &beacons->bcn[i].offs, ++ beacons->bcn[i].skb, params); ++ if (ret) { ++ ath11k_warn(tx_arvif->ar->ab, ++ "failed to set ema beacon template id %i error %d\n", ++ i, ret); ++ break; ++ } ++ } ++ ++ ieee80211_beacon_free_ema_list(beacons); ++ ++ if (tx_arvif != arvif && !nontx_vif_params_set) ++ return -EINVAL; /* Profile not found in the beacons */ ++ ++ return ret; ++} ++ + static int ath11k_mac_setup_bcn_tmpl_mbssid(struct ath11k_vif *arvif) + { + struct ath11k *ar = arvif->ar; +@@ -1484,7 +1538,7 @@ static int ath11k_mac_setup_bcn_tmpl_mbs + else if (!ath11k_mac_set_nontx_vif_params(tx_arvif, arvif, bcn)) + return -EINVAL; + +- ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn); ++ ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn, 0); + kfree_skb(bcn); + + if (ret) +@@ -1508,6 +1562,9 @@ static int ath11k_mac_setup_bcn_tmpl(str + arvif != (void *)vif->mbssid_tx_vif->drv_priv && arvif->is_up) + return 0; + ++ if (vif->bss_conf.ema_ap && vif->mbssid_tx_vif) ++ return ath11k_mac_setup_bcn_tmpl_ema(arvif); ++ + return ath11k_mac_setup_bcn_tmpl_mbssid(arvif); + } + +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -1699,7 +1699,7 @@ int ath11k_wmi_send_bcn_offload_control_ + + int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id, + struct ieee80211_mutable_offsets *offs, +- struct sk_buff *bcn) ++ struct sk_buff *bcn, u32 ema_params) + { + struct ath11k_pdev_wmi *wmi = ar->wmi; + struct wmi_bcn_tmpl_cmd *cmd; +@@ -1738,6 +1738,7 @@ int ath11k_wmi_bcn_tmpl(struct ath11k *a + + cmd->buf_len = bcn->len; + cmd->mbssid_ie_offset = offs->mbssid_off; ++ cmd->ema_params = ema_params; + + ptr = skb->data + sizeof(*cmd); + +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -3566,6 +3566,10 @@ struct wmi_get_pdev_temperature_cmd { + + #define WMI_BEACON_TX_BUFFER_SIZE 512 + ++#define WMI_EMA_TMPL_IDX_SHIFT 8 ++#define WMI_EMA_FIRST_TMPL_SHIFT 16 ++#define WMI_EMA_LAST_TMPL_SHIFT 24 ++ + struct wmi_bcn_tmpl_cmd { + u32 tlv_header; + u32 vdev_id; +@@ -3576,6 +3580,11 @@ struct wmi_bcn_tmpl_cmd { + u32 csa_event_bitmap; + u32 mbssid_ie_offset; + u32 esp_ie_offset; ++ u32 csc_switch_count_offset; ++ u32 csc_event_bitmap; ++ u32 mu_edca_ie_offset; ++ u32 feature_enable_bitmap; ++ u32 ema_params; + } __packed; + + struct wmi_key_seq_counter { +@@ -6298,7 +6307,7 @@ int ath11k_wmi_mgmt_send(struct ath11k * + struct sk_buff *frame); + int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id, + struct ieee80211_mutable_offsets *offs, +- struct sk_buff *bcn); ++ struct sk_buff *bcn, u32 ema_param); + int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id); + int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, + const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx, diff --git a/package/kernel/mac80211/patches/ath11k/0078-wifi-ath11k-Relocate-the-func-ath11k_mac_bitrate_mas.patch b/package/kernel/mac80211/patches/ath11k/0078-wifi-ath11k-Relocate-the-func-ath11k_mac_bitrate_mas.patch new file mode 100644 index 000000000..610bf7251 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0078-wifi-ath11k-Relocate-the-func-ath11k_mac_bitrate_mas.patch @@ -0,0 +1,75 @@ +From 570eec3d40505c30babbe3b8f85a38496c975ab2 Mon Sep 17 00:00:00 2001 +From: Maharaja Kennadyrajan +Date: Tue, 9 May 2023 20:07:23 +0300 +Subject: [PATCH] wifi: ath11k: Relocate the func + ath11k_mac_bitrate_mask_num_ht_rates() and change hweight16 to hweight8 + +Relocate the function ath11k_mac_bitrate_mask_num_ht_rates() definition +to call this function from other functions which helps to avoid the +compilation error (function not defined). + +ht_mcs[] is 1 byte array and it is enough to use hweight8() instead +of hweight16(). Hence, fixed the same. + +Tested on: Compile tested only. + +Signed-off-by: Maharaja Kennadyrajan +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230504092033.3542456-2-quic_mkenna@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 30 +++++++++++++-------------- + 1 file changed, 15 insertions(+), 15 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -4338,6 +4338,20 @@ exit: + } + + static int ++ath11k_mac_bitrate_mask_num_ht_rates(struct ath11k *ar, ++ enum nl80211_band band, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ int num_rates = 0; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) ++ num_rates += hweight8(mask->control[band].ht_mcs[i]); ++ ++ return num_rates; ++} ++ ++static int + ath11k_mac_bitrate_mask_num_vht_rates(struct ath11k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +@@ -7791,20 +7805,6 @@ static void ath11k_mac_op_flush(struct i + ath11k_mac_flush_tx_complete(ar); + } + +-static int +-ath11k_mac_bitrate_mask_num_ht_rates(struct ath11k *ar, +- enum nl80211_band band, +- const struct cfg80211_bitrate_mask *mask) +-{ +- int num_rates = 0; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) +- num_rates += hweight16(mask->control[band].ht_mcs[i]); +- +- return num_rates; +-} +- + static bool + ath11k_mac_has_single_legacy_rate(struct ath11k *ar, + enum nl80211_band band, diff --git a/package/kernel/mac80211/patches/ath11k/0079-wifi-ath11k-Send-HT-fixed-rate-in-WMI-peer-fixed-par.patch b/package/kernel/mac80211/patches/ath11k/0079-wifi-ath11k-Send-HT-fixed-rate-in-WMI-peer-fixed-par.patch new file mode 100644 index 000000000..6282f4462 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0079-wifi-ath11k-Send-HT-fixed-rate-in-WMI-peer-fixed-par.patch @@ -0,0 +1,141 @@ +From df8e3729ffc0aa645839693f74ee7b6d999cdf64 Mon Sep 17 00:00:00 2001 +From: Maharaja Kennadyrajan +Date: Tue, 9 May 2023 20:07:24 +0300 +Subject: [PATCH] wifi: ath11k: Send HT fixed rate in WMI peer fixed param + +Due to the firmware behavior with HT fixed rate setting, +HT fixed rate MCS with NSS > 1 are treated as NSS = 1 +HT rates in the firmware and enables the HT fixed rate of +NSS = 1. + +This leads to HT fixed rate is always configured for NSS = 1 +even though the user sets NSS = 2 or > 1 HT fixed MCS in the +set bitrate command. + +Currently HT fixed MCS is sent via WMI peer assoc command. +Fix this issue, by sending the HT fixed rate MCS in WMI peer +fixed param instead of sending in peer assoc command. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Maharaja Kennadyrajan +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230504092033.3542456-3-quic_mkenna@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 63 ++++++++++++++++++++++++++- + 1 file changed, 61 insertions(+), 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -4480,6 +4480,54 @@ ath11k_mac_set_peer_he_fixed_rate(struct + return ret; + } + ++static int ++ath11k_mac_set_peer_ht_fixed_rate(struct ath11k_vif *arvif, ++ struct ieee80211_sta *sta, ++ const struct cfg80211_bitrate_mask *mask, ++ enum nl80211_band band) ++{ ++ struct ath11k *ar = arvif->ar; ++ u8 ht_rate, nss = 0; ++ u32 rate_code; ++ int ret, i; ++ ++ lockdep_assert_held(&ar->conf_mutex); ++ ++ for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) { ++ if (hweight8(mask->control[band].ht_mcs[i]) == 1) { ++ nss = i + 1; ++ ht_rate = ffs(mask->control[band].ht_mcs[i]) - 1; ++ } ++ } ++ ++ if (!nss) { ++ ath11k_warn(ar->ab, "No single HT Fixed rate found to set for %pM", ++ sta->addr); ++ return -EINVAL; ++ } ++ ++ /* Avoid updating invalid nss as fixed rate*/ ++ if (nss > sta->deflink.rx_nss) ++ return -EINVAL; ++ ++ ath11k_dbg(ar->ab, ATH11K_DBG_MAC, ++ "Setting Fixed HT Rate for peer %pM. Device will not switch to any other selected rates", ++ sta->addr); ++ ++ rate_code = ATH11K_HW_RATE_CODE(ht_rate, nss - 1, ++ WMI_RATE_PREAMBLE_HT); ++ ret = ath11k_wmi_set_peer_param(ar, sta->addr, ++ arvif->vdev_id, ++ WMI_PEER_PARAM_FIXED_RATE, ++ rate_code); ++ if (ret) ++ ath11k_warn(ar->ab, ++ "failed to update STA %pM HT Fixed Rate %d: %d\n", ++ sta->addr, rate_code, ret); ++ ++ return ret; ++} ++ + static int ath11k_station_assoc(struct ath11k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, +@@ -4491,7 +4539,7 @@ static int ath11k_station_assoc(struct a + struct cfg80211_chan_def def; + enum nl80211_band band; + struct cfg80211_bitrate_mask *mask; +- u8 num_vht_rates, num_he_rates; ++ u8 num_ht_rates, num_vht_rates, num_he_rates; + + lockdep_assert_held(&ar->conf_mutex); + +@@ -4519,6 +4567,7 @@ static int ath11k_station_assoc(struct a + + num_vht_rates = ath11k_mac_bitrate_mask_num_vht_rates(ar, band, mask); + num_he_rates = ath11k_mac_bitrate_mask_num_he_rates(ar, band, mask); ++ num_ht_rates = ath11k_mac_bitrate_mask_num_ht_rates(ar, band, mask); + + /* If single VHT/HE rate is configured (by set_bitrate_mask()), + * peer_assoc will disable VHT/HE. This is now enabled by a peer specific +@@ -4535,6 +4584,11 @@ static int ath11k_station_assoc(struct a + band); + if (ret) + return ret; ++ } else if (sta->deflink.ht_cap.ht_supported && num_ht_rates == 1) { ++ ret = ath11k_mac_set_peer_ht_fixed_rate(arvif, sta, mask, ++ band); ++ if (ret) ++ return ret; + } + + /* Re-assoc is run only to update supported rates for given station. It +@@ -4608,7 +4662,7 @@ static void ath11k_sta_rc_update_wk(stru + const u16 *vht_mcs_mask; + const u16 *he_mcs_mask; + u32 changed, bw, nss, smps, bw_prev; +- int err, num_vht_rates, num_he_rates; ++ int err, num_ht_rates, num_vht_rates, num_he_rates; + const struct cfg80211_bitrate_mask *mask; + struct peer_assoc_params peer_arg; + enum wmi_phy_mode peer_phymode; +@@ -4724,6 +4778,8 @@ static void ath11k_sta_rc_update_wk(stru + + if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) { + mask = &arvif->bitrate_mask; ++ num_ht_rates = ath11k_mac_bitrate_mask_num_ht_rates(ar, band, ++ mask); + num_vht_rates = ath11k_mac_bitrate_mask_num_vht_rates(ar, band, + mask); + num_he_rates = ath11k_mac_bitrate_mask_num_he_rates(ar, band, +@@ -4746,6 +4802,9 @@ static void ath11k_sta_rc_update_wk(stru + } else if (sta->deflink.he_cap.has_he && num_he_rates == 1) { + ath11k_mac_set_peer_he_fixed_rate(arvif, sta, mask, + band); ++ } else if (sta->deflink.ht_cap.ht_supported && num_ht_rates == 1) { ++ ath11k_mac_set_peer_ht_fixed_rate(arvif, sta, mask, ++ band); + } else { + /* If the peer is non-VHT/HE or no fixed VHT/HE rate + * is provided in the new bitrate mask we set the diff --git a/package/kernel/mac80211/patches/ath11k/0080-wifi-ath11k-add-support-default-regdb-while-searchin.patch b/package/kernel/mac80211/patches/ath11k/0080-wifi-ath11k-add-support-default-regdb-while-searchin.patch new file mode 100644 index 000000000..5ff40aac7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0080-wifi-ath11k-add-support-default-regdb-while-searchin.patch @@ -0,0 +1,127 @@ +From 88ca89202f8e8afb5225eb5244d79cd67c15d744 Mon Sep 17 00:00:00 2001 +From: Wen Gong +Date: Fri, 26 May 2023 12:41:06 +0300 +Subject: [PATCH] wifi: ath11k: add support default regdb while searching + board-2.bin for WCN6855 + +Sometimes board-2.bin does not have the regdb data which matched the +parameters such as vendor, device, subsystem-vendor, subsystem-device +and etc. Add default regdb data with 'bus=%s' into board-2.bin for +WCN6855, then ath11k use 'bus=pci' to search regdb data in board-2.bin +for WCN6855. + +kernel: [ 122.515808] ath11k_pci 0000:03:00.0: boot using board name 'bus=pci,vendor=17cb,device=1103,subsystem-vendor=17cb,subsystem-device=3374,qmi-chip-id=2,qmi-board-id=262' +kernel: [ 122.517240] ath11k_pci 0000:03:00.0: boot firmware request ath11k/WCN6855/hw2.0/board-2.bin size 6179564 +kernel: [ 122.517280] ath11k_pci 0000:03:00.0: failed to fetch regdb data for bus=pci,vendor=17cb,device=1103,subsystem-vendor=17cb,subsystem-device=3374,qmi-chip-id=2,qmi-board-id=262 from ath11k/WCN6855/hw2.0/board-2.bin +kernel: [ 122.517464] ath11k_pci 0000:03:00.0: boot using board name 'bus=pci' +kernel: [ 122.518901] ath11k_pci 0000:03:00.0: boot firmware request ath11k/WCN6855/hw2.0/board-2.bin size 6179564 +kernel: [ 122.518915] ath11k_pci 0000:03:00.0: board name +kernel: [ 122.518917] ath11k_pci 0000:03:00.0: 00000000: 62 75 73 3d 70 63 69 bus=pci +kernel: [ 122.518918] ath11k_pci 0000:03:00.0: boot found match regdb data for name 'bus=pci' +kernel: [ 122.518920] ath11k_pci 0000:03:00.0: boot found regdb data for 'bus=pci' +kernel: [ 122.518921] ath11k_pci 0000:03:00.0: fetched regdb + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3 + +Signed-off-by: Wen Gong +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230517133959.8224-1-quic_wgong@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 53 +++++++++++++++++++------- + 1 file changed, 40 insertions(+), 13 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -961,7 +961,8 @@ int ath11k_core_check_dt(struct ath11k_b + } + + static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, +- size_t name_len, bool with_variant) ++ size_t name_len, bool with_variant, ++ bool bus_type_mode) + { + /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ + char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; +@@ -972,15 +973,20 @@ static int __ath11k_core_create_board_na + + switch (ab->id.bdf_search) { + case ATH11K_BDF_SEARCH_BUS_AND_BOARD: +- scnprintf(name, name_len, +- "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", +- ath11k_bus_str(ab->hif.bus), +- ab->id.vendor, ab->id.device, +- ab->id.subsystem_vendor, +- ab->id.subsystem_device, +- ab->qmi.target.chip_id, +- ab->qmi.target.board_id, +- variant); ++ if (bus_type_mode) ++ scnprintf(name, name_len, ++ "bus=%s", ++ ath11k_bus_str(ab->hif.bus)); ++ else ++ scnprintf(name, name_len, ++ "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", ++ ath11k_bus_str(ab->hif.bus), ++ ab->id.vendor, ab->id.device, ++ ab->id.subsystem_vendor, ++ ab->id.subsystem_device, ++ ab->qmi.target.chip_id, ++ ab->qmi.target.board_id, ++ variant); + break; + default: + scnprintf(name, name_len, +@@ -999,13 +1005,19 @@ static int __ath11k_core_create_board_na + static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, true); ++ return __ath11k_core_create_board_name(ab, name, name_len, true, false); + } + + static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, false); ++ return __ath11k_core_create_board_name(ab, name, name_len, false, false); ++} ++ ++static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, ++ size_t name_len) ++{ ++ return __ath11k_core_create_board_name(ab, name, name_len, false, true); + } + + const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, +@@ -1309,7 +1321,7 @@ success: + + int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) + { +- char boardname[BOARD_NAME_SIZE]; ++ char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; + int ret; + + ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); +@@ -1323,6 +1335,21 @@ int ath11k_core_fetch_regdb(struct ath11 + ATH11K_BD_IE_REGDB, + ATH11K_BD_IE_REGDB_NAME, + ATH11K_BD_IE_REGDB_DATA); ++ if (!ret) ++ goto exit; ++ ++ ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, ++ BOARD_NAME_SIZE); ++ if (ret) { ++ ath11k_dbg(ab, ATH11K_DBG_BOOT, ++ "failed to create default board name for regdb: %d", ret); ++ goto exit; ++ } ++ ++ ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, ++ ATH11K_BD_IE_REGDB, ++ ATH11K_BD_IE_REGDB_NAME, ++ ATH11K_BD_IE_REGDB_DATA); + if (!ret) + goto exit; + diff --git a/package/kernel/mac80211/patches/ath11k/0081-wifi-ath11k-remove-unused-function-ath11k_tm_event_w.patch b/package/kernel/mac80211/patches/ath11k/0081-wifi-ath11k-remove-unused-function-ath11k_tm_event_w.patch new file mode 100644 index 000000000..b5dc83f00 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0081-wifi-ath11k-remove-unused-function-ath11k_tm_event_w.patch @@ -0,0 +1,128 @@ +From 86f85575a3f6a20cef1c8bb98e78585fe3a53ccc Mon Sep 17 00:00:00 2001 +From: Govindaraj Saminathan +Date: Fri, 26 May 2023 12:41:06 +0300 +Subject: [PATCH 82/84] wifi: ath11k: remove unused function + ath11k_tm_event_wmi() + +The function ath11k_tm_event_wmi() is only defined and it is not used +anywhere. Hence remove the unused. + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Govindaraj Saminathan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230517135934.16408-2-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/testmode.c | 64 +--------------------- + drivers/net/wireless/ath/ath11k/testmode.h | 8 +-- + 2 files changed, 2 insertions(+), 70 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/testmode.c ++++ b/drivers/net/wireless/ath/ath11k/testmode.c +@@ -1,6 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include "testmode.h" +@@ -20,69 +21,6 @@ static const struct nla_policy ath11k_tm + [ATH11K_TM_ATTR_VERSION_MINOR] = { .type = NLA_U32 }, + }; + +-/* Returns true if callee consumes the skb and the skb should be discarded. +- * Returns false if skb is not used. Does not sleep. +- */ +-bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb) +-{ +- struct sk_buff *nl_skb; +- bool consumed; +- int ret; +- +- ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, +- "testmode event wmi cmd_id %d skb %pK skb->len %d\n", +- cmd_id, skb, skb->len); +- +- ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", skb->data, skb->len); +- +- spin_lock_bh(&ar->data_lock); +- +- consumed = true; +- +- nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy, +- 2 * sizeof(u32) + skb->len, +- GFP_ATOMIC); +- if (!nl_skb) { +- ath11k_warn(ar->ab, +- "failed to allocate skb for testmode wmi event\n"); +- goto out; +- } +- +- ret = nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD, ATH11K_TM_CMD_WMI); +- if (ret) { +- ath11k_warn(ar->ab, +- "failed to put testmode wmi event cmd attribute: %d\n", +- ret); +- kfree_skb(nl_skb); +- goto out; +- } +- +- ret = nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id); +- if (ret) { +- ath11k_warn(ar->ab, +- "failed to put testmode wmi even cmd_id: %d\n", +- ret); +- kfree_skb(nl_skb); +- goto out; +- } +- +- ret = nla_put(nl_skb, ATH11K_TM_ATTR_DATA, skb->len, skb->data); +- if (ret) { +- ath11k_warn(ar->ab, +- "failed to copy skb to testmode wmi event: %d\n", +- ret); +- kfree_skb(nl_skb); +- goto out; +- } +- +- cfg80211_testmode_event(nl_skb, GFP_ATOMIC); +- +-out: +- spin_unlock_bh(&ar->data_lock); +- +- return consumed; +-} +- + static int ath11k_tm_cmd_get_version(struct ath11k *ar, struct nlattr *tb[]) + { + struct sk_buff *skb; +--- a/drivers/net/wireless/ath/ath11k/testmode.h ++++ b/drivers/net/wireless/ath/ath11k/testmode.h +@@ -1,24 +1,18 @@ + /* SPDX-License-Identifier: BSD-3-Clause-Clear */ + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include "core.h" + + #ifdef CPTCFG_NL80211_TESTMODE + +-bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb); + int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + void *data, int len); + + #else + +-static inline bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, +- struct sk_buff *skb) +-{ +- return false; +-} +- + static inline int ath11k_tm_cmd(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + void *data, int len) diff --git a/package/kernel/mac80211/patches/ath11k/0082-wifi-ath11k-factory-test-mode-support.patch b/package/kernel/mac80211/patches/ath11k/0082-wifi-ath11k-factory-test-mode-support.patch new file mode 100644 index 000000000..f1b262724 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0082-wifi-ath11k-factory-test-mode-support.patch @@ -0,0 +1,850 @@ +From b43310e44edc823a7f02af1e1e2b4e8a9abc7d91 Mon Sep 17 00:00:00 2001 +From: Govindaraj Saminathan +Date: Fri, 26 May 2023 12:41:07 +0300 +Subject: [PATCH 83/84] wifi: ath11k: factory test mode support + +Add support to process factory test mode commands (FTM) for calibration. +By default firmware start with NORMAL mode and to process the FTM commands +firmware needs to be restarted in FTM mode using module parameter ftm_mode. +The pre-request is all the radios should be down before starting the test. + +When start command ATH11K_TM_CMD_TESTMODE_START is received, ar->state +is set to Test Mode. If the FTM command or event length is greater +than 256 bytes, it will be broken down into multiple segments and +encoded with TLV header if it is segmented commands, else it is sent +to firmware as it is. + +On receiving UTF event from firmware, if it is segmented event, the driver +will wait until it receives all the segments and notify the complete +data to user application. In case the segmented sequence are missed or +lost from the firmware, driver will skip the already received partial data. + +In case of unsegmented UTF event from firmware, driver notifies the +data to the user application as it comes. Applications handles +the data further. + +Command to boot in ftm mode: + +insmod ath11k ftm_mode=1 + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Govindaraj Saminathan +Co-developed-by: Sowmiya Sree Elavalagan +Signed-off-by: Sowmiya Sree Elavalagan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230517135934.16408-4-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 3 +- + drivers/net/wireless/ath/ath11k/core.c | 21 +- + drivers/net/wireless/ath/ath11k/core.h | 16 +- + drivers/net/wireless/ath/ath11k/debug.h | 1 + + drivers/net/wireless/ath/ath11k/mac.c | 11 +- + drivers/net/wireless/ath/ath11k/pci.c | 3 +- + drivers/net/wireless/ath/ath11k/testmode.c | 350 ++++++++++++++++++- + drivers/net/wireless/ath/ath11k/testmode.h | 6 + + drivers/net/wireless/ath/ath11k/testmode_i.h | 18 +- + drivers/net/wireless/ath/ath11k/wmi.c | 11 +- + drivers/net/wireless/ath/ath11k/wmi.h | 22 ++ + drivers/net/wireless/ath/ath11k/wow.c | 3 +- + 12 files changed, 444 insertions(+), 21 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -1155,6 +1155,7 @@ static int ath11k_ahb_probe(struct platf + ab->hif.ops = hif_ops; + ab->pdev = pdev; + ab->hw_rev = hw_rev; ++ ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL; + platform_set_drvdata(pdev, ab); + + ret = ath11k_pcic_register_pci_ops(ab, pci_ops); +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -32,6 +32,10 @@ module_param_named(frame_mode, ath11k_fr + MODULE_PARM_DESC(frame_mode, + "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); + ++bool ath11k_ftm_mode; ++module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); ++MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); ++ + static const struct ath11k_hw_params ath11k_hw_params[] = { + { + .hw_rev = ATH11K_HW_IPQ8074, +@@ -1381,6 +1385,11 @@ static int ath11k_core_soc_create(struct + { + int ret; + ++ if (ath11k_ftm_mode) { ++ ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; ++ ath11k_info(ab, "Booting in factory test mode\n"); ++ } ++ + ret = ath11k_qmi_init_service(ab); + if (ret) { + ath11k_err(ab, "failed to initialize qmi :%d\n", ret); +@@ -1607,7 +1616,7 @@ int ath11k_core_qmi_firmware_ready(struc + { + int ret; + +- ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL); ++ ret = ath11k_core_start_firmware(ab, ab->fw_mode); + if (ret) { + ath11k_err(ab, "failed to start firmware: %d\n", ret); + return ret; +@@ -1772,7 +1781,8 @@ void ath11k_core_pre_reconfigure_recover + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; +- if (!ar || ar->state == ATH11K_STATE_OFF) ++ if (!ar || ar->state == ATH11K_STATE_OFF || ++ ar->state == ATH11K_STATE_FTM) + continue; + + ieee80211_stop_queues(ar->hw); +@@ -1841,7 +1851,12 @@ static void ath11k_core_post_reconfigure + ath11k_warn(ab, + "device is wedged, will not restart radio %d\n", i); + break; ++ case ATH11K_STATE_FTM: ++ ath11k_dbg(ab, ATH11K_DBG_TESTMODE, ++ "fw mode reset done radio %d\n", i); ++ break; + } ++ + mutex_unlock(&ar->conf_mutex); + } + complete(&ab->driver_recovery); +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -1,7 +1,7 @@ + /* SPDX-License-Identifier: BSD-3-Clause-Clear */ + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #ifndef ATH11K_CORE_H +@@ -52,6 +52,7 @@ + #define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_" + + extern unsigned int ath11k_frame_mode; ++extern bool ath11k_ftm_mode; + + #define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ) + +@@ -277,6 +278,7 @@ enum ath11k_dev_flags { + ATH11K_FLAG_FIXED_MEM_RGN, + ATH11K_FLAG_DEVICE_INIT_DONE, + ATH11K_FLAG_MULTI_MSI_VECTORS, ++ ATH11K_FLAG_FTM_SEGMENTED, + }; + + enum ath11k_monitor_flags { +@@ -530,6 +532,7 @@ enum ath11k_state { + ATH11K_STATE_RESTARTING, + ATH11K_STATE_RESTARTED, + ATH11K_STATE_WEDGED, ++ ATH11K_STATE_FTM, + /* Add other states as required */ + }; + +@@ -709,6 +712,8 @@ struct ath11k { + u32 last_ppdu_id; + u32 cached_ppdu_id; + int monitor_vdev_id; ++ struct completion fw_mode_reset; ++ u8 ftm_msgref; + #ifdef CPTCFG_ATH11K_DEBUGFS + struct ath11k_debug debug; + #endif +@@ -838,6 +843,7 @@ struct ath11k_msi_config { + /* Master structure to hold the hw data which may be used in core module */ + struct ath11k_base { + enum ath11k_hw_rev hw_rev; ++ enum ath11k_firmware_mode fw_mode; + struct platform_device *pdev; + struct device *dev; + struct ath11k_qmi qmi; +@@ -978,6 +984,14 @@ struct ath11k_base { + const struct ath11k_pci_ops *ops; + } pci; + ++#ifdef CPTCFG_NL80211_TESTMODE ++ struct { ++ u32 data_pos; ++ u32 expected_seq; ++ u8 *eventdata; ++ } testmode; ++#endif ++ + /* must be last */ + u8 drv_priv[] __aligned(sizeof(void *)); + }; +--- a/drivers/net/wireless/ath/ath11k/debug.h ++++ b/drivers/net/wireless/ath/ath11k/debug.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: BSD-3-Clause-Clear */ + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #ifndef _ATH11K_DEBUG_H_ +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -643,7 +643,10 @@ struct ath11k *ath11k_mac_get_ar_by_pdev + return NULL; + + for (i = 0; i < ab->num_radios; i++) { +- pdev = rcu_dereference(ab->pdevs_active[i]); ++ if (ab->fw_mode == ATH11K_FIRMWARE_MODE_FTM) ++ pdev = &ab->pdevs[i]; ++ else ++ pdev = rcu_dereference(ab->pdevs_active[i]); + + if (pdev && pdev->pdev_id == pdev_id) + return (pdev->ar ? pdev->ar : NULL); +@@ -6271,6 +6274,11 @@ static int ath11k_mac_op_start(struct ie + struct ath11k_pdev *pdev = ar->pdev; + int ret; + ++ if (ath11k_ftm_mode) { ++ ath11k_warn(ab, "mac operations not supported in factory test mode\n"); ++ return -EOPNOTSUPP; ++ } ++ + ath11k_mac_drain_tx(ar); + mutex_lock(&ar->conf_mutex); + +@@ -6285,6 +6293,7 @@ static int ath11k_mac_op_start(struct ie + case ATH11K_STATE_RESTARTED: + case ATH11K_STATE_WEDGED: + case ATH11K_STATE_ON: ++ case ATH11K_STATE_FTM: + WARN_ON(1); + ret = -EINVAL; + goto err; +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. +- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -745,6 +745,7 @@ static int ath11k_pci_probe(struct pci_d + ab_pci->ab = ab; + ab_pci->pdev = pdev; + ab->hif.ops = &ath11k_pci_hif_ops; ++ ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL; + pci_set_drvdata(pdev, ab); + spin_lock_init(&ab_pci->window_lock); + +--- a/drivers/net/wireless/ath/ath11k/testmode.c ++++ b/drivers/net/wireless/ath/ath11k/testmode.c +@@ -12,6 +12,9 @@ + #include "core.h" + #include "testmode_i.h" + ++#define ATH11K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0) ++#define ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4) ++ + static const struct nla_policy ath11k_tm_policy[ATH11K_TM_ATTR_MAX + 1] = { + [ATH11K_TM_ATTR_CMD] = { .type = NLA_U32 }, + [ATH11K_TM_ATTR_DATA] = { .type = NLA_BINARY, +@@ -21,13 +24,217 @@ static const struct nla_policy ath11k_tm + [ATH11K_TM_ATTR_VERSION_MINOR] = { .type = NLA_U32 }, + }; + ++static struct ath11k *ath11k_tm_get_ar(struct ath11k_base *ab) ++{ ++ struct ath11k_pdev *pdev; ++ struct ath11k *ar = NULL; ++ int i; ++ ++ for (i = 0; i < ab->num_radios; i++) { ++ pdev = &ab->pdevs[i]; ++ ar = pdev->ar; ++ ++ if (ar && ar->state == ATH11K_STATE_FTM) ++ break; ++ } ++ ++ return ar; ++} ++ ++/* This function handles unsegmented events. Data in various events are aggregated ++ * in application layer, this event is unsegmented from host perspective. ++ */ ++static void ath11k_tm_wmi_event_unsegmented(struct ath11k_base *ab, u32 cmd_id, ++ struct sk_buff *skb) ++{ ++ struct sk_buff *nl_skb; ++ struct ath11k *ar; ++ ++ ath11k_dbg(ab, ATH11K_DBG_TESTMODE, ++ "event wmi cmd_id %d skb length %d\n", ++ cmd_id, skb->len); ++ ath11k_dbg_dump(ab, ATH11K_DBG_TESTMODE, NULL, "", skb->data, skb->len); ++ ++ ar = ath11k_tm_get_ar(ab); ++ if (!ar) { ++ ath11k_warn(ab, "testmode event not handled due to invalid pdev\n"); ++ return; ++ } ++ ++ spin_lock_bh(&ar->data_lock); ++ ++ nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy, ++ 2 * nla_total_size(sizeof(u32)) + ++ nla_total_size(skb->len), ++ GFP_ATOMIC); ++ if (!nl_skb) { ++ ath11k_warn(ab, ++ "failed to allocate skb for unsegmented testmode wmi event\n"); ++ goto out; ++ } ++ ++ if (nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD, ATH11K_TM_CMD_WMI) || ++ nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id) || ++ nla_put(nl_skb, ATH11K_TM_ATTR_DATA, skb->len, skb->data)) { ++ ath11k_warn(ab, "failed to populate testmode unsegmented event\n"); ++ kfree_skb(nl_skb); ++ goto out; ++ } ++ ++ cfg80211_testmode_event(nl_skb, GFP_ATOMIC); ++ spin_unlock_bh(&ar->data_lock); ++ return; ++ ++out: ++ spin_unlock_bh(&ar->data_lock); ++ ath11k_warn(ab, "Failed to send testmode event to higher layers\n"); ++} ++ ++/* This function handles segmented events. Data of various events received ++ * from firmware is aggregated and sent to application layer ++ */ ++static int ath11k_tm_process_event(struct ath11k_base *ab, u32 cmd_id, ++ const struct wmi_ftm_event_msg *ftm_msg, ++ u16 length) ++{ ++ struct sk_buff *nl_skb; ++ int ret = 0; ++ struct ath11k *ar; ++ u8 const *buf_pos; ++ u16 datalen; ++ u8 total_segments, current_seq; ++ u32 data_pos; ++ u32 pdev_id; ++ ++ ath11k_dbg(ab, ATH11K_DBG_TESTMODE, ++ "event wmi cmd_id %d ftm event msg %pK datalen %d\n", ++ cmd_id, ftm_msg, length); ++ ath11k_dbg_dump(ab, ATH11K_DBG_TESTMODE, NULL, "", ftm_msg, length); ++ pdev_id = DP_HW2SW_MACID(ftm_msg->seg_hdr.pdev_id); ++ ++ if (pdev_id >= ab->num_radios) { ++ ath11k_warn(ab, "testmode event not handled due to invalid pdev id: %d\n", ++ pdev_id); ++ return -EINVAL; ++ } ++ ++ ar = ab->pdevs[pdev_id].ar; ++ if (!ar) { ++ ath11k_warn(ab, "testmode event not handled due to absence of pdev\n"); ++ return -ENODEV; ++ } ++ ++ current_seq = FIELD_GET(ATH11K_FTM_SEGHDR_CURRENT_SEQ, ++ ftm_msg->seg_hdr.segmentinfo); ++ total_segments = FIELD_GET(ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS, ++ ftm_msg->seg_hdr.segmentinfo); ++ datalen = length - (sizeof(struct wmi_ftm_seg_hdr)); ++ buf_pos = ftm_msg->data; ++ ++ spin_lock_bh(&ar->data_lock); ++ ++ if (current_seq == 0) { ++ ab->testmode.expected_seq = 0; ++ ab->testmode.data_pos = 0; ++ } ++ ++ data_pos = ab->testmode.data_pos; ++ ++ if ((data_pos + datalen) > ATH11K_FTM_EVENT_MAX_BUF_LENGTH) { ++ ath11k_warn(ab, "Invalid ftm event length at %d: %d\n", ++ data_pos, datalen); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ memcpy(&ab->testmode.eventdata[data_pos], buf_pos, datalen); ++ data_pos += datalen; ++ ++ if (++ab->testmode.expected_seq != total_segments) { ++ ab->testmode.data_pos = data_pos; ++ ath11k_dbg(ab, ATH11K_DBG_TESTMODE, ++ "partial data received current_seq %d total_seg %d\n", ++ current_seq, total_segments); ++ goto out; ++ } ++ ++ ath11k_dbg(ab, ATH11K_DBG_TESTMODE, ++ "total data length pos %d len %d\n", ++ data_pos, ftm_msg->seg_hdr.len); ++ nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy, ++ 2 * nla_total_size(sizeof(u32)) + ++ nla_total_size(data_pos), ++ GFP_ATOMIC); ++ if (!nl_skb) { ++ ath11k_warn(ab, ++ "failed to allocate skb for segmented testmode wmi event\n"); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ if (nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD, ++ ATH11K_TM_CMD_WMI_FTM) || ++ nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id) || ++ nla_put(nl_skb, ATH11K_TM_ATTR_DATA, data_pos, ++ &ab->testmode.eventdata[0])) { ++ ath11k_warn(ab, "failed to populate segmented testmode event"); ++ kfree_skb(nl_skb); ++ ret = -ENOBUFS; ++ goto out; ++ } ++ ++ cfg80211_testmode_event(nl_skb, GFP_ATOMIC); ++ ++out: ++ spin_unlock_bh(&ar->data_lock); ++ return ret; ++} ++ ++static void ath11k_tm_wmi_event_segmented(struct ath11k_base *ab, u32 cmd_id, ++ struct sk_buff *skb) ++{ ++ const void **tb; ++ const struct wmi_ftm_event_msg *ev; ++ u16 length; ++ int ret; ++ ++ tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); ++ if (IS_ERR(tb)) { ++ ret = PTR_ERR(tb); ++ ath11k_warn(ab, "failed to parse ftm event tlv: %d\n", ret); ++ return; ++ } ++ ++ ev = tb[WMI_TAG_ARRAY_BYTE]; ++ if (!ev) { ++ ath11k_warn(ab, "failed to fetch ftm msg\n"); ++ kfree(tb); ++ return; ++ } ++ ++ length = skb->len - TLV_HDR_SIZE; ++ ret = ath11k_tm_process_event(ab, cmd_id, ev, length); ++ if (ret) ++ ath11k_warn(ab, "Failed to process ftm event\n"); ++ ++ kfree(tb); ++} ++ ++void ath11k_tm_wmi_event(struct ath11k_base *ab, u32 cmd_id, struct sk_buff *skb) ++{ ++ if (test_bit(ATH11K_FLAG_FTM_SEGMENTED, &ab->dev_flags)) ++ ath11k_tm_wmi_event_segmented(ab, cmd_id, skb); ++ else ++ ath11k_tm_wmi_event_unsegmented(ab, cmd_id, skb); ++} ++ + static int ath11k_tm_cmd_get_version(struct ath11k *ar, struct nlattr *tb[]) + { + struct sk_buff *skb; + int ret; + + ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, +- "testmode cmd get version_major %d version_minor %d\n", ++ "cmd get version_major %d version_minor %d\n", + ATH11K_TESTMODE_VERSION_MAJOR, + ATH11K_TESTMODE_VERSION_MINOR); + +@@ -53,6 +260,43 @@ static int ath11k_tm_cmd_get_version(str + return cfg80211_testmode_reply(skb); + } + ++static int ath11k_tm_cmd_testmode_start(struct ath11k *ar, struct nlattr *tb[]) ++{ ++ int ret; ++ ++ mutex_lock(&ar->conf_mutex); ++ ++ if (ar->state == ATH11K_STATE_FTM) { ++ ret = -EALREADY; ++ goto err; ++ } ++ ++ /* start utf only when the driver is not in use */ ++ if (ar->state != ATH11K_STATE_OFF) { ++ ret = -EBUSY; ++ goto err; ++ } ++ ++ ar->ab->testmode.eventdata = kzalloc(ATH11K_FTM_EVENT_MAX_BUF_LENGTH, ++ GFP_KERNEL); ++ if (!ar->ab->testmode.eventdata) { ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ ar->state = ATH11K_STATE_FTM; ++ ar->ftm_msgref = 0; ++ ++ mutex_unlock(&ar->conf_mutex); ++ ++ ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, "cmd start\n"); ++ return 0; ++ ++err: ++ mutex_unlock(&ar->conf_mutex); ++ return ret; ++} ++ + static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[]) + { + struct ath11k_pdev_wmi *wmi = ar->wmi; +@@ -63,11 +307,6 @@ static int ath11k_tm_cmd_wmi(struct ath1 + + mutex_lock(&ar->conf_mutex); + +- if (ar->state != ATH11K_STATE_ON) { +- ret = -ENETDOWN; +- goto out; +- } +- + if (!tb[ATH11K_TM_ATTR_DATA]) { + ret = -EINVAL; + goto out; +@@ -80,11 +319,17 @@ static int ath11k_tm_cmd_wmi(struct ath1 + + buf = nla_data(tb[ATH11K_TM_ATTR_DATA]); + buf_len = nla_len(tb[ATH11K_TM_ATTR_DATA]); ++ if (!buf_len) { ++ ath11k_warn(ar->ab, "No data present in testmode wmi command\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ + cmd_id = nla_get_u32(tb[ATH11K_TM_ATTR_WMI_CMDID]); + + ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, +- "testmode cmd wmi cmd_id %d buf %pK buf_len %d\n", +- cmd_id, buf, buf_len); ++ "cmd wmi cmd_id %d buf length %d\n", ++ cmd_id, buf_len); + + ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", buf, buf_len); + +@@ -111,6 +356,91 @@ out: + return ret; + } + ++static int ath11k_tm_cmd_wmi_ftm(struct ath11k *ar, struct nlattr *tb[]) ++{ ++ struct ath11k_pdev_wmi *wmi = ar->wmi; ++ struct ath11k_base *ab = ar->ab; ++ struct sk_buff *skb; ++ u32 cmd_id, buf_len, hdr_info; ++ int ret; ++ void *buf; ++ u8 segnumber = 0, seginfo; ++ u16 chunk_len, total_bytes, num_segments; ++ u8 *bufpos; ++ struct wmi_ftm_cmd *ftm_cmd; ++ ++ set_bit(ATH11K_FLAG_FTM_SEGMENTED, &ab->dev_flags); ++ ++ mutex_lock(&ar->conf_mutex); ++ ++ if (ar->state != ATH11K_STATE_FTM) { ++ ret = -ENETDOWN; ++ goto out; ++ } ++ ++ if (!tb[ATH11K_TM_ATTR_DATA]) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ buf = nla_data(tb[ATH11K_TM_ATTR_DATA]); ++ buf_len = nla_len(tb[ATH11K_TM_ATTR_DATA]); ++ cmd_id = WMI_PDEV_UTF_CMDID; ++ ++ ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, ++ "cmd wmi ftm cmd_id %d buffer length %d\n", ++ cmd_id, buf_len); ++ ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", buf, buf_len); ++ ++ bufpos = buf; ++ total_bytes = buf_len; ++ num_segments = total_bytes / MAX_WMI_UTF_LEN; ++ ++ if (buf_len - (num_segments * MAX_WMI_UTF_LEN)) ++ num_segments++; ++ ++ while (buf_len) { ++ chunk_len = min_t(u16, buf_len, MAX_WMI_UTF_LEN); ++ ++ skb = ath11k_wmi_alloc_skb(wmi->wmi_ab, (chunk_len + ++ sizeof(struct wmi_ftm_cmd))); ++ if (!skb) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ ftm_cmd = (struct wmi_ftm_cmd *)skb->data; ++ hdr_info = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_BYTE) | ++ FIELD_PREP(WMI_TLV_LEN, (chunk_len + ++ sizeof(struct wmi_ftm_seg_hdr))); ++ ftm_cmd->tlv_header = hdr_info; ++ ftm_cmd->seg_hdr.len = total_bytes; ++ ftm_cmd->seg_hdr.msgref = ar->ftm_msgref; ++ seginfo = FIELD_PREP(ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS, num_segments) | ++ FIELD_PREP(ATH11K_FTM_SEGHDR_CURRENT_SEQ, segnumber); ++ ftm_cmd->seg_hdr.segmentinfo = seginfo; ++ segnumber++; ++ ++ memcpy(&ftm_cmd->data, bufpos, chunk_len); ++ ++ ret = ath11k_wmi_cmd_send(wmi, skb, cmd_id); ++ if (ret) { ++ ath11k_warn(ar->ab, "failed to send wmi ftm command: %d\n", ret); ++ goto out; ++ } ++ ++ buf_len -= chunk_len; ++ bufpos += chunk_len; ++ } ++ ++ ar->ftm_msgref++; ++ ret = 0; ++ ++out: ++ mutex_unlock(&ar->conf_mutex); ++ return ret; ++} ++ + int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + void *data, int len) + { +@@ -131,6 +461,10 @@ int ath11k_tm_cmd(struct ieee80211_hw *h + return ath11k_tm_cmd_get_version(ar, tb); + case ATH11K_TM_CMD_WMI: + return ath11k_tm_cmd_wmi(ar, tb); ++ case ATH11K_TM_CMD_TESTMODE_START: ++ return ath11k_tm_cmd_testmode_start(ar, tb); ++ case ATH11K_TM_CMD_WMI_FTM: ++ return ath11k_tm_cmd_wmi_ftm(ar, tb); + default: + return -EOPNOTSUPP; + } +--- a/drivers/net/wireless/ath/ath11k/testmode.h ++++ b/drivers/net/wireless/ath/ath11k/testmode.h +@@ -8,11 +8,17 @@ + + #ifdef CPTCFG_NL80211_TESTMODE + ++void ath11k_tm_wmi_event(struct ath11k_base *ab, u32 cmd_id, struct sk_buff *skb); + int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + void *data, int len); + + #else + ++static inline void ath11k_tm_wmi_event(struct ath11k_base *ab, u32 cmd_id, ++ struct sk_buff *skb) ++{ ++} ++ + static inline int ath11k_tm_cmd(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + void *data, int len) +--- a/drivers/net/wireless/ath/ath11k/testmode_i.h ++++ b/drivers/net/wireless/ath/ath11k/testmode_i.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: BSD-3-Clause-Clear */ + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + /* "API" level of the ath11k testmode interface. Bump it after every +@@ -11,9 +12,10 @@ + /* Bump this after every _compatible_ interface change, for example + * addition of a new command or an attribute. + */ +-#define ATH11K_TESTMODE_VERSION_MINOR 0 ++#define ATH11K_TESTMODE_VERSION_MINOR 1 + + #define ATH11K_TM_DATA_MAX_LEN 5000 ++#define ATH11K_FTM_EVENT_MAX_BUF_LENGTH 2048 + + enum ath11k_tm_attr { + __ATH11K_TM_ATTR_INVALID = 0, +@@ -47,4 +49,18 @@ enum ath11k_tm_cmd { + * ATH11K_TM_ATTR_DATA. + */ + ATH11K_TM_CMD_WMI = 1, ++ ++ /* Boots the UTF firmware, the netdev interface must be down at the ++ * time. ++ */ ++ ATH11K_TM_CMD_TESTMODE_START = 2, ++ ++ /* The command used to transmit a FTM WMI command to the firmware ++ * and the event to receive WMI events from the firmware. The data ++ * received only contain the payload, need to add the tlv header ++ * and send the cmd to firmware with command id WMI_PDEV_UTF_CMDID. ++ * The data payload size could be large and the driver needs to ++ * send segmented data to firmware. ++ */ ++ ATH11K_TM_CMD_WMI_FTM = 3, + }; +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2021, 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + #include + #include +@@ -19,6 +19,7 @@ + #include "mac.h" + #include "hw.h" + #include "peer.h" ++#include "testmode.h" + + struct wmi_tlv_policy { + size_t min_len; +@@ -237,9 +238,8 @@ static int ath11k_wmi_tlv_parse(struct a + (void *)tb); + } + +-static const void ** +-ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr, +- size_t len, gfp_t gfp) ++const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr, ++ size_t len, gfp_t gfp) + { + const void **tb; + int ret; +@@ -8628,6 +8628,9 @@ static void ath11k_wmi_tlv_op_rx(struct + case WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID: + ath11k_wmi_pdev_csa_switch_count_status_event(ab, skb); + break; ++ case WMI_PDEV_UTF_EVENTID: ++ ath11k_tm_wmi_event(ab, id, skb); ++ break; + case WMI_PDEV_TEMPERATURE_EVENTID: + ath11k_wmi_pdev_temperature_event(ab, skb); + break; +--- a/drivers/net/wireless/ath/ath11k/wmi.h ++++ b/drivers/net/wireless/ath/ath11k/wmi.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: BSD-3-Clause-Clear */ + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #ifndef ATH11K_WMI_H +@@ -68,6 +69,7 @@ struct wmi_tlv { + + #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 + ++#define MAX_WMI_UTF_LEN 252 + #define WMI_BA_MODE_BUFFER_SIZE_256 3 + /* + * HW mode config type replicated from FW header +@@ -3564,6 +3566,24 @@ struct wmi_get_pdev_temperature_cmd { + u32 pdev_id; + } __packed; + ++struct wmi_ftm_seg_hdr { ++ u32 len; ++ u32 msgref; ++ u32 segmentinfo; ++ u32 pdev_id; ++} __packed; ++ ++struct wmi_ftm_cmd { ++ u32 tlv_header; ++ struct wmi_ftm_seg_hdr seg_hdr; ++ u8 data[]; ++} __packed; ++ ++struct wmi_ftm_event_msg { ++ struct wmi_ftm_seg_hdr seg_hdr; ++ u8 data[]; ++} __packed; ++ + #define WMI_BEACON_TX_BUFFER_SIZE 512 + + #define WMI_EMA_TMPL_IDX_SHIFT 8 +@@ -6300,6 +6320,8 @@ enum wmi_sta_keepalive_method { + #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 + #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 + ++const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr, ++ size_t len, gfp_t gfp); + int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb, + u32 cmd_id); + struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len); +--- a/drivers/net/wireless/ath/ath11k/wow.c ++++ b/drivers/net/wireless/ath/ath11k/wow.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. +- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -838,6 +838,7 @@ exit: + case ATH11K_STATE_RESTARTING: + case ATH11K_STATE_RESTARTED: + case ATH11K_STATE_WEDGED: ++ case ATH11K_STATE_FTM: + ath11k_warn(ar->ab, "encountered unexpected device state %d on resume, cannot recover\n", + ar->state); + ret = -EIO; diff --git a/package/kernel/mac80211/patches/ath11k/0083-wifi-ath11k-Allow-ath11k-to-boot-without-caldata-in-.patch b/package/kernel/mac80211/patches/ath11k/0083-wifi-ath11k-Allow-ath11k-to-boot-without-caldata-in-.patch new file mode 100644 index 000000000..5a1fa8829 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0083-wifi-ath11k-Allow-ath11k-to-boot-without-caldata-in-.patch @@ -0,0 +1,47 @@ +From 8aeba427296bff6a6051686f1d139c89a0b00e4c Mon Sep 17 00:00:00 2001 +From: Sowmiya Sree Elavalagan +Date: Fri, 26 May 2023 12:41:07 +0300 +Subject: [PATCH 84/84] wifi: ath11k: Allow ath11k to boot without caldata in + ftm mode + +Currently, if ath11k is unable to load the calibration data file it will +always exit. However the calibration data may not be present in factory +test mode, so update the logic to allow the driver to execute in FTM mode +even if downloading the calibration data fails. + +Tested-on : IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Sowmiya Sree Elavalagan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230517135934.16408-5-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/qmi.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: BSD-3-Clause-Clear + /* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. +- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -2460,6 +2460,14 @@ static int ath11k_qmi_load_bdf_qmi(struc + + fw_entry = ath11k_core_firmware_request(ab, ATH11K_DEFAULT_CAL_FILE); + if (IS_ERR(fw_entry)) { ++ /* Caldata may not be present during first time calibration in ++ * factory hence allow to boot without loading caldata in ftm mode ++ */ ++ if (ath11k_ftm_mode) { ++ ath11k_info(ab, ++ "Booting without cal data file in factory test mode\n"); ++ return 0; ++ } + ret = PTR_ERR(fw_entry); + ath11k_warn(ab, + "qmi failed to load CAL data file:%s\n", diff --git a/package/kernel/mac80211/patches/ath11k/0084-wifi-ath11k-Add-HTT-stats-for-PHY-reset-case.patch b/package/kernel/mac80211/patches/ath11k/0084-wifi-ath11k-Add-HTT-stats-for-PHY-reset-case.patch new file mode 100644 index 000000000..946f5f7b5 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0084-wifi-ath11k-Add-HTT-stats-for-PHY-reset-case.patch @@ -0,0 +1,261 @@ +From 2d4f9093e2d8531ad0a2bb98fe5b36dc8addf2a2 Mon Sep 17 00:00:00 2001 +From: Nidhi Jain +Date: Fri, 26 May 2023 12:41:07 +0300 +Subject: [PATCH] wifi: ath11k: Add HTT stats for PHY reset case + +New HTT stats are added with stats type 37 to +provide PHY reset stats and PHY reset counter stats. + +PHY reset stats are used to display the current +PHY-related operation information such as band, CCA +threshold, current operating channel etc., + +PHY reset counter stats are used to display the +PHY reset counter values like calibration counts, +temperature based recalibration counts etc., + +Usage: +echo 37 > /sys/kernel/debug/ieee80211/phyX/ath11k/htt_stats_type +cat /sys/kernel/debug/ieee80211/phyx/ath11k/htt_stats + +Output: + +HTT_PHY_RESET_STATS_TLV: +pdev_id = 0 +chan_mhz = 5180 +chan_band_center_freq1 = 5210 +chan_band_center_freq2 = 0 +chan_phy_mode = 18 +chan_flags = 0x8 +chan_num = 36 +reset_cause = 0x50000 +prev_reset_cause = 0x50000 +phy_warm_reset_src = 0x0 +rx_gain_tbl_mode = 0 +xbar_val = 0xfac688 +force_calibration = 0 +phyrf_mode = 0 +phy_homechan = 0 +phy_tx_ch_mask = 0x3 +phy_rx_ch_mask = 0x3 +phybb_ini_mask = 0x5 +phyrf_ini_mask = 0x0 +phy_dfs_en_mask = 0x0 +phy_sscan_en_mask = 0x0 +phy_synth_sel_mask = 0x0 +phy_adfs_freq = 0 +cck_fir_settings = 0x0 +phy_dyn_pri_chan = 6 +cca_thresh = 0x26232020 +dyn_cca_status = 0 +rxdesense_thresh_hw = 0xcfe0afe +rxdesense_thresh_sw = 0xcfe0afe + +HTT_PHY_RESET_COUNTERS_TLV: +pdev_id = 0 +cf_active_low_fail_cnt = 0 +cf_active_low_pass_cnt = 0 +phy_off_through_vreg_cnt = 0 +force_calibration_cnt = 0 +rf_mode_switch_phy_off_cnt = 0 + +Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Nidhi Jain +Signed-off-by: Maharaja Kennadyrajan +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230517141242.2754293-1-quic_mkenna@quicinc.com +--- + .../wireless/ath/ath11k/debugfs_htt_stats.c | 114 ++++++++++++++++++ + .../wireless/ath/ath11k/debugfs_htt_stats.h | 43 +++++++ + 2 files changed, 157 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c ++++ b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c +@@ -4011,6 +4011,114 @@ void htt_print_phy_stats_tlv(const void + stats_req->buf_len = len; + } + ++static inline void ++htt_print_phy_reset_counters_tlv(const void *tag_buf, ++ u16 tag_len, ++ struct debug_htt_stats_req *stats_req) ++{ ++ const struct htt_phy_reset_counters_tlv *htt_stats_buf = tag_buf; ++ u8 *buf = stats_req->buf; ++ u32 len = stats_req->buf_len; ++ u32 buf_len = ATH11K_HTT_STATS_BUF_SIZE; ++ ++ if (tag_len < sizeof(*htt_stats_buf)) ++ return; ++ ++ len += scnprintf(buf + len, buf_len - len, "HTT_PHY_RESET_COUNTERS_TLV:\n"); ++ ++ len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n", ++ htt_stats_buf->pdev_id); ++ len += scnprintf(buf + len, buf_len - len, "cf_active_low_fail_cnt = %u\n", ++ htt_stats_buf->cf_active_low_fail_cnt); ++ len += scnprintf(buf + len, buf_len - len, "cf_active_low_pass_cnt = %u\n", ++ htt_stats_buf->cf_active_low_pass_cnt); ++ len += scnprintf(buf + len, buf_len - len, "phy_off_through_vreg_cnt = %u\n", ++ htt_stats_buf->phy_off_through_vreg_cnt); ++ len += scnprintf(buf + len, buf_len - len, "force_calibration_cnt = %u\n", ++ htt_stats_buf->force_calibration_cnt); ++ len += scnprintf(buf + len, buf_len - len, "rf_mode_switch_phy_off_cnt = %u\n", ++ htt_stats_buf->rf_mode_switch_phy_off_cnt); ++ ++ stats_req->buf_len = len; ++} ++ ++static inline void ++htt_print_phy_reset_stats_tlv(const void *tag_buf, ++ u16 tag_len, ++ struct debug_htt_stats_req *stats_req) ++{ ++ const struct htt_phy_reset_stats_tlv *htt_stats_buf = tag_buf; ++ u8 *buf = stats_req->buf; ++ u32 len = stats_req->buf_len; ++ u32 buf_len = ATH11K_HTT_STATS_BUF_SIZE; ++ ++ if (tag_len < sizeof(*htt_stats_buf)) ++ return; ++ ++ len += scnprintf(buf + len, buf_len - len, "HTT_PHY_RESET_STATS_TLV:\n"); ++ ++ len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n", ++ htt_stats_buf->pdev_id); ++ len += scnprintf(buf + len, buf_len - len, "chan_mhz = %u\n", ++ htt_stats_buf->chan_mhz); ++ len += scnprintf(buf + len, buf_len - len, "chan_band_center_freq1 = %u\n", ++ htt_stats_buf->chan_band_center_freq1); ++ len += scnprintf(buf + len, buf_len - len, "chan_band_center_freq2 = %u\n", ++ htt_stats_buf->chan_band_center_freq2); ++ len += scnprintf(buf + len, buf_len - len, "chan_phy_mode = %u\n", ++ htt_stats_buf->chan_phy_mode); ++ len += scnprintf(buf + len, buf_len - len, "chan_flags = 0x%0x\n", ++ htt_stats_buf->chan_flags); ++ len += scnprintf(buf + len, buf_len - len, "chan_num = %u\n", ++ htt_stats_buf->chan_num); ++ len += scnprintf(buf + len, buf_len - len, "reset_cause = 0x%0x\n", ++ htt_stats_buf->reset_cause); ++ len += scnprintf(buf + len, buf_len - len, "prev_reset_cause = 0x%0x\n", ++ htt_stats_buf->prev_reset_cause); ++ len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_src = 0x%0x\n", ++ htt_stats_buf->phy_warm_reset_src); ++ len += scnprintf(buf + len, buf_len - len, "rx_gain_tbl_mode = %d\n", ++ htt_stats_buf->rx_gain_tbl_mode); ++ len += scnprintf(buf + len, buf_len - len, "xbar_val = 0x%0x\n", ++ htt_stats_buf->xbar_val); ++ len += scnprintf(buf + len, buf_len - len, "force_calibration = %u\n", ++ htt_stats_buf->force_calibration); ++ len += scnprintf(buf + len, buf_len - len, "phyrf_mode = %u\n", ++ htt_stats_buf->phyrf_mode); ++ len += scnprintf(buf + len, buf_len - len, "phy_homechan = %u\n", ++ htt_stats_buf->phy_homechan); ++ len += scnprintf(buf + len, buf_len - len, "phy_tx_ch_mask = 0x%0x\n", ++ htt_stats_buf->phy_tx_ch_mask); ++ len += scnprintf(buf + len, buf_len - len, "phy_rx_ch_mask = 0x%0x\n", ++ htt_stats_buf->phy_rx_ch_mask); ++ len += scnprintf(buf + len, buf_len - len, "phybb_ini_mask = 0x%0x\n", ++ htt_stats_buf->phybb_ini_mask); ++ len += scnprintf(buf + len, buf_len - len, "phyrf_ini_mask = 0x%0x\n", ++ htt_stats_buf->phyrf_ini_mask); ++ len += scnprintf(buf + len, buf_len - len, "phy_dfs_en_mask = 0x%0x\n", ++ htt_stats_buf->phy_dfs_en_mask); ++ len += scnprintf(buf + len, buf_len - len, "phy_sscan_en_mask = 0x%0x\n", ++ htt_stats_buf->phy_sscan_en_mask); ++ len += scnprintf(buf + len, buf_len - len, "phy_synth_sel_mask = 0x%0x\n", ++ htt_stats_buf->phy_synth_sel_mask); ++ len += scnprintf(buf + len, buf_len - len, "phy_adfs_freq = %u\n", ++ htt_stats_buf->phy_adfs_freq); ++ len += scnprintf(buf + len, buf_len - len, "cck_fir_settings = 0x%0x\n", ++ htt_stats_buf->cck_fir_settings); ++ len += scnprintf(buf + len, buf_len - len, "phy_dyn_pri_chan = %u\n", ++ htt_stats_buf->phy_dyn_pri_chan); ++ len += scnprintf(buf + len, buf_len - len, "cca_thresh = 0x%0x\n", ++ htt_stats_buf->cca_thresh); ++ len += scnprintf(buf + len, buf_len - len, "dyn_cca_status = %u\n", ++ htt_stats_buf->dyn_cca_status); ++ len += scnprintf(buf + len, buf_len - len, "rxdesense_thresh_hw = 0x%x\n", ++ htt_stats_buf->rxdesense_thresh_hw); ++ len += scnprintf(buf + len, buf_len - len, "rxdesense_thresh_sw = 0x%x\n", ++ htt_stats_buf->rxdesense_thresh_sw); ++ ++ stats_req->buf_len = len; ++} ++ + static inline + void htt_print_peer_ctrl_path_txrx_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +@@ -4425,6 +4533,12 @@ static int ath11k_dbg_htt_ext_stats_pars + case HTT_STATS_PHY_STATS_TAG: + htt_print_phy_stats_tlv(tag_buf, stats_req); + break; ++ case HTT_STATS_PHY_RESET_COUNTERS_TAG: ++ htt_print_phy_reset_counters_tlv(tag_buf, len, stats_req); ++ break; ++ case HTT_STATS_PHY_RESET_STATS_TAG: ++ htt_print_phy_reset_stats_tlv(tag_buf, len, stats_req); ++ break; + case HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG: + htt_print_peer_ctrl_path_txrx_stats_tlv(tag_buf, stats_req); + break; +--- a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h ++++ b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h +@@ -111,6 +111,8 @@ enum htt_tlv_tag_t { + HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, + HTT_STATS_PHY_COUNTERS_TAG = 121, + HTT_STATS_PHY_STATS_TAG = 122, ++ HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, ++ HTT_STATS_PHY_RESET_STATS_TAG = 124, + + HTT_STATS_MAX_TAG, + }; +@@ -1964,6 +1966,47 @@ struct htt_phy_stats_tlv { + u32 fw_run_time; + }; + ++struct htt_phy_reset_counters_tlv { ++ u32 pdev_id; ++ u32 cf_active_low_fail_cnt; ++ u32 cf_active_low_pass_cnt; ++ u32 phy_off_through_vreg_cnt; ++ u32 force_calibration_cnt; ++ u32 rf_mode_switch_phy_off_cnt; ++}; ++ ++struct htt_phy_reset_stats_tlv { ++ u32 pdev_id; ++ u32 chan_mhz; ++ u32 chan_band_center_freq1; ++ u32 chan_band_center_freq2; ++ u32 chan_phy_mode; ++ u32 chan_flags; ++ u32 chan_num; ++ u32 reset_cause; ++ u32 prev_reset_cause; ++ u32 phy_warm_reset_src; ++ u32 rx_gain_tbl_mode; ++ u32 xbar_val; ++ u32 force_calibration; ++ u32 phyrf_mode; ++ u32 phy_homechan; ++ u32 phy_tx_ch_mask; ++ u32 phy_rx_ch_mask; ++ u32 phybb_ini_mask; ++ u32 phyrf_ini_mask; ++ u32 phy_dfs_en_mask; ++ u32 phy_sscan_en_mask; ++ u32 phy_synth_sel_mask; ++ u32 phy_adfs_freq; ++ u32 cck_fir_settings; ++ u32 phy_dyn_pri_chan; ++ u32 cca_thresh; ++ u32 dyn_cca_status; ++ u32 rxdesense_thresh_hw; ++ u32 rxdesense_thresh_sw; ++}; ++ + struct htt_peer_ctrl_path_txrx_stats_tlv { + /* peer mac address */ + u8 peer_mac_addr[ETH_ALEN]; diff --git a/package/kernel/mac80211/patches/ath11k/0085-wifi-ath11k-fix-memory-leak-in-WMI-firmware-stats.patch b/package/kernel/mac80211/patches/ath11k/0085-wifi-ath11k-fix-memory-leak-in-WMI-firmware-stats.patch new file mode 100644 index 000000000..dde30b962 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0085-wifi-ath11k-fix-memory-leak-in-WMI-firmware-stats.patch @@ -0,0 +1,51 @@ +From 6aafa1c2d3e3fea2ebe84c018003f2a91722e607 Mon Sep 17 00:00:00 2001 +From: P Praneesh +Date: Tue, 6 Jun 2023 14:41:28 +0530 +Subject: [PATCH] wifi: ath11k: fix memory leak in WMI firmware stats + +Memory allocated for firmware pdev, vdev and beacon statistics +are not released during rmmod. + +Fix it by calling ath11k_fw_stats_free() function before hardware +unregister. + +While at it, avoid calling ath11k_fw_stats_free() while processing +the firmware stats received in the WMI event because the local list +is getting spliced and reinitialised and hence there are no elements +in the list after splicing. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: P Praneesh +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230606091128.14202-1-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 1 + + drivers/net/wireless/ath/ath11k/wmi.c | 5 +++++ + 2 files changed, 6 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -9792,6 +9792,7 @@ void ath11k_mac_destroy(struct ath11k_ba + if (!ar) + continue; + ++ ath11k_fw_stats_free(&ar->fw_stats); + ieee80211_free_hw(ar->hw); + pdev->ar = NULL; + } +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -8119,6 +8119,11 @@ complete: + rcu_read_unlock(); + spin_unlock_bh(&ar->data_lock); + ++ /* Since the stats's pdev, vdev and beacon list are spliced and reinitialised ++ * at this point, no need to free the individual list. ++ */ ++ return; ++ + free: + ath11k_fw_stats_free(&stats); + } diff --git a/package/kernel/mac80211/patches/ath11k/0086-wifi-ath11k-Add-missing-check-for-ioremap.patch b/package/kernel/mac80211/patches/ath11k/0086-wifi-ath11k-Add-missing-check-for-ioremap.patch new file mode 100644 index 000000000..e536c3bd6 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0086-wifi-ath11k-Add-missing-check-for-ioremap.patch @@ -0,0 +1,38 @@ +From 16e0077e14a73866e9b0f4a6bf4ad3d4a5cb0f2a Mon Sep 17 00:00:00 2001 +From: Jiasheng Jiang +Date: Tue, 13 Jun 2023 12:19:40 +0300 +Subject: [PATCH] wifi: ath11k: Add missing check for ioremap + +Add check for ioremap() and return the error if it fails in order to +guarantee the success of ioremap(), same as in +ath11k_qmi_load_file_target_mem(). + +Fixes: 6ac04bdc5edb ("ath11k: Use reserved host DDR addresses from DT for PCI devices") +Signed-off-by: Jiasheng Jiang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230608022858.27405-1-jiasheng@iscas.ac.cn +--- + drivers/net/wireless/ath/ath11k/qmi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -2061,6 +2061,9 @@ static int ath11k_qmi_assign_target_mem_ + ab->qmi.target_mem[idx].iaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); ++ if (!ab->qmi.target_mem[idx].iaddr) ++ return -EIO; ++ + ab->qmi.target_mem[idx].size = ab->qmi.target_mem[i].size; + host_ddr_sz = ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = ab->qmi.target_mem[i].type; +@@ -2086,6 +2089,8 @@ static int ath11k_qmi_assign_target_mem_ + ab->qmi.target_mem[idx].iaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); ++ if (!ab->qmi.target_mem[idx].iaddr) ++ return -EIO; + } else { + ab->qmi.target_mem[idx].paddr = + ATH11K_QMI_CALDB_ADDRESS; diff --git a/package/kernel/mac80211/patches/ath11k/0087-wifi-ath11k-Add-missing-ops-config-for-IPQ5018-in.patch b/package/kernel/mac80211/patches/ath11k/0087-wifi-ath11k-Add-missing-ops-config-for-IPQ5018-in.patch new file mode 100644 index 000000000..fa539ef45 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0087-wifi-ath11k-Add-missing-ops-config-for-IPQ5018-in.patch @@ -0,0 +1,30 @@ +From 469ddb20cae61cad9c4f208a4c8682305905a511 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Thu, 15 Jun 2023 14:41:47 +0300 +Subject: [PATCH] wifi: ath11k: Add missing ops config for IPQ5018 in + ath11k_ahb_probe() + +Without this patch, the IPQ5018 WiFi will fail and print the following +logs: + + [ 11.033179] ath11k c000000.wifi: unsupported device type 7 + [ 11.033223] ath11k: probe of c000000.wifi failed with error -95 + +Fixes: 25edca7bb18a ("wifi: ath11k: add ipq5018 device support") +Signed-off-by: Ziyang Huang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/TYZPR01MB5556D7AA10ABEDDDD2D8F39EC953A@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -1127,6 +1127,7 @@ static int ath11k_ahb_probe(struct platf + switch (hw_rev) { + case ATH11K_HW_IPQ8074: + case ATH11K_HW_IPQ6018_HW10: ++ case ATH11K_HW_IPQ5018_HW10: + hif_ops = &ath11k_ahb_hif_ops_ipq8074; + pci_ops = NULL; + break; diff --git a/package/kernel/mac80211/patches/ath11k/0088-wifi-ath11k-Restart-firmware-after-cold-boot-calibration.patch b/package/kernel/mac80211/patches/ath11k/0088-wifi-ath11k-Restart-firmware-after-cold-boot-calibration.patch new file mode 100644 index 000000000..4a9385218 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0088-wifi-ath11k-Restart-firmware-after-cold-boot-calibration.patch @@ -0,0 +1,47 @@ +From 80c5390e1f5e5b16d820512265530ef26073d8e0 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Thu, 15 Jun 2023 14:41:48 +0300 +Subject: [PATCH] wifi: ath11k: Restart firmware after cold boot calibration + for IPQ5018 + +Restart is required after cold boot calibration on IPQ5018. Otherwise, +we get the following exception: + + [ 14.412829] qcom-q6-mpd cd00000.remoteproc: fatal error received: err_smem_ver.2.1: + [ 14.412829] QC Image Version : QC_IMAGE_VERSION_STRING=WLAN.HK.2.6.0.1-00974-QCAHKSWPL_SILICONZ-1 + [ 14.412829] Image Variant : IMAGE_VARIANT_STRING=5018.wlanfw2.map_spr_spr_evalQ + [ 14.412829] DALSysLogEvent.c:174 Assertion 0 failed param0 :zero,param1 :zero,param2 :zero + [ 14.412829] Thread ID : 0x00000048 Thread name : WLAN RT0 Process ID : 0x00000001 Process name :wlan0 + [ 14.412829] + [ 14.412829] Registers: + [ 14.412829] SP : 0x4c81c120 + [ 14.412829] FP : 0x4c81c138 + [ 14.412829] PC : 0xb022c590 + [ 14.412829] SSR : 0x00000000 + [ 14.412829] BADVA : 0x00000000 + [ 14.412829] LR : 0xb0008490 + [ 14.412829] + [ 14.412829] StackDump + [ 14.412829] from:0x4c81c120 + [ 14.412829] to: 0x00000000: + [ 14.412829] + [ 14.463006] remoteproc remoteproc0: crash detected in cd00000.remoteproc: type fatal error + +Fixes: 8dfe875aa24a ("wifi: ath11k: update hw params for IPQ5018") +Signed-off-by: Ziyang Huang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/TYZPR01MB55566969818BD4B49E770445C953A@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +--- + drivers/net/wireless/ath/ath11k/core.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -668,6 +668,7 @@ static const struct ath11k_hw_params ath + .hal_params = &ath11k_hw_hal_params_ipq8074, + .single_pdev_only = false, + .cold_boot_calib = true, ++ .cbcal_restart_fw = true, + .fix_l1ss = true, + .supports_dynamic_smps_6ghz = false, + .alloc_cacheable_memory = true, diff --git a/package/kernel/mac80211/patches/ath11k/0089-wifi-ath11k-Add-missing-hw_ops-get_ring_selector-for.patch b/package/kernel/mac80211/patches/ath11k/0089-wifi-ath11k-Add-missing-hw_ops-get_ring_selector-for.patch new file mode 100644 index 000000000..cb6667f14 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0089-wifi-ath11k-Add-missing-hw_ops-get_ring_selector-for.patch @@ -0,0 +1,58 @@ +From ce282d8de71f07f0056ea319541141152c65f552 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Thu, 15 Jun 2023 14:41:48 +0300 +Subject: [PATCH] wifi: ath11k: Add missing hw_ops->get_ring_selector() for + IPQ5018 + +During sending data after clients connected, hw_ops->get_ring_selector() +will be called. But for IPQ5018, this member isn't set, and the +following NULL pointer exception will be occurred: + + [ 38.840478] 8<--- cut here --- + [ 38.840517] Unable to handle kernel NULL pointer dereference at virtual address 00000000 + ... + [ 38.923161] PC is at 0x0 + [ 38.927930] LR is at ath11k_dp_tx+0x70/0x730 [ath11k] + ... + [ 39.063264] Process hostapd (pid: 1034, stack limit = 0x801ceb3d) + [ 39.068994] Stack: (0x856a9a68 to 0x856aa000) + ... + [ 39.438467] [<7f323804>] (ath11k_dp_tx [ath11k]) from [<7f314e6c>] (ath11k_mac_op_tx+0x80/0x190 [ath11k]) + [ 39.446607] [<7f314e6c>] (ath11k_mac_op_tx [ath11k]) from [<7f17dbe0>] (ieee80211_handle_wake_tx_queue+0x7c/0xc0 [mac80211]) + [ 39.456162] [<7f17dbe0>] (ieee80211_handle_wake_tx_queue [mac80211]) from [<7f174450>] (ieee80211_probereq_get+0x584/0x704 [mac80211]) + [ 39.467443] [<7f174450>] (ieee80211_probereq_get [mac80211]) from [<7f178c40>] (ieee80211_tx_prepare_skb+0x1f8/0x248 [mac80211]) + [ 39.479334] [<7f178c40>] (ieee80211_tx_prepare_skb [mac80211]) from [<7f179e28>] (__ieee80211_subif_start_xmit+0x32c/0x3d4 [mac80211]) + [ 39.491053] [<7f179e28>] (__ieee80211_subif_start_xmit [mac80211]) from [<7f17af08>] (ieee80211_tx_control_port+0x19c/0x288 [mac80211]) + [ 39.502946] [<7f17af08>] (ieee80211_tx_control_port [mac80211]) from [<7f0fc704>] (nl80211_tx_control_port+0x174/0x1d4 [cfg80211]) + [ 39.515017] [<7f0fc704>] (nl80211_tx_control_port [cfg80211]) from [<808ceac4>] (genl_rcv_msg+0x154/0x340) + [ 39.526814] [<808ceac4>] (genl_rcv_msg) from [<808cdb74>] (netlink_rcv_skb+0xb8/0x11c) + [ 39.536446] [<808cdb74>] (netlink_rcv_skb) from [<808ce1d0>] (genl_rcv+0x28/0x34) + [ 39.544344] [<808ce1d0>] (genl_rcv) from [<808cd234>] (netlink_unicast+0x174/0x274) + [ 39.551895] [<808cd234>] (netlink_unicast) from [<808cd510>] (netlink_sendmsg+0x1dc/0x440) + [ 39.559362] [<808cd510>] (netlink_sendmsg) from [<808596e0>] (____sys_sendmsg+0x1a8/0x1fc) + [ 39.567697] [<808596e0>] (____sys_sendmsg) from [<8085b1a8>] (___sys_sendmsg+0xa4/0xdc) + [ 39.575941] [<8085b1a8>] (___sys_sendmsg) from [<8085b310>] (sys_sendmsg+0x44/0x74) + [ 39.583841] [<8085b310>] (sys_sendmsg) from [<80300060>] (ret_fast_syscall+0x0/0x40) + ... + [ 39.620734] Code: bad PC value + [ 39.625869] ---[ end trace 8aef983ad3cbc032 ]--- + +Fixes: ba60f2793d3a ("wifi: ath11k: initialize hw_ops for IPQ5018") +Signed-off-by: Ziyang Huang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/TYZPR01MB5556D6E3F63EAB5129D11420C953A@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +--- + drivers/net/wireless/ath/ath11k/hw.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -1178,7 +1178,7 @@ const struct ath11k_hw_ops ipq5018_ops = + .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, + .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, + .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, +- ++ .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, + }; + + #define ATH11K_TX_RING_MASK_0 BIT(0) diff --git a/package/kernel/mac80211/patches/ath11k/0090-Revert-wifi-ath11k-Enable-threaded-NAPI.patch b/package/kernel/mac80211/patches/ath11k/0090-Revert-wifi-ath11k-Enable-threaded-NAPI.patch new file mode 100644 index 000000000..313c18c55 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0090-Revert-wifi-ath11k-Enable-threaded-NAPI.patch @@ -0,0 +1,44 @@ +From d265ebe41c911314bd273c218a37088835959fa1 Mon Sep 17 00:00:00 2001 +From: Kalle Valo +Date: Thu, 20 Jul 2023 18:14:44 +0300 +Subject: [PATCH] Revert "wifi: ath11k: Enable threaded NAPI" + +This reverts commit 13aa2fb692d3717767303817f35b3e650109add3. + +This commit broke QCN9074 initialisation: + +[ 358.960477] ath11k_pci 0000:04:00.0: ce desc not available for wmi command 36866 +[ 358.960481] ath11k_pci 0000:04:00.0: failed to send WMI_STA_POWERSAVE_PARAM_CMDID +[ 358.960484] ath11k_pci 0000:04:00.0: could not set uapsd params -105 + +As there's no fix available let's just revert it to get QCN9074 working again. + +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217536 +Signed-off-by: Kalle Valo +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230720151444.2016637-1-kvalo@kernel.org +--- + drivers/net/wireless/ath/ath11k/ahb.c | 1 - + drivers/net/wireless/ath/ath11k/pcic.c | 1 - + 2 files changed, 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -376,7 +376,6 @@ static void ath11k_ahb_ext_irq_enable(st + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + if (!irq_grp->napi_enabled) { +- dev_set_threaded(&irq_grp->napi_ndev, true); + napi_enable(&irq_grp->napi); + irq_grp->napi_enabled = true; + } +--- a/drivers/net/wireless/ath/ath11k/pcic.c ++++ b/drivers/net/wireless/ath/ath11k/pcic.c +@@ -466,7 +466,6 @@ void ath11k_pcic_ext_irq_enable(struct a + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + if (!irq_grp->napi_enabled) { +- dev_set_threaded(&irq_grp->napi_ndev, true); + napi_enable(&irq_grp->napi); + irq_grp->napi_enabled = true; + } diff --git a/package/kernel/mac80211/patches/ath11k/0091-wifi-ath11k-Split-coldboot-calibration-hw_param.patch b/package/kernel/mac80211/patches/ath11k/0091-wifi-ath11k-Split-coldboot-calibration-hw_param.patch new file mode 100644 index 000000000..470535468 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0091-wifi-ath11k-Split-coldboot-calibration-hw_param.patch @@ -0,0 +1,180 @@ +From 011e5a3052a22d3758d17442bf0c04c68bf79bea Mon Sep 17 00:00:00 2001 +From: Seevalamuthu Mariappan +Date: Wed, 26 Jul 2023 19:40:30 +0530 +Subject: [PATCH 3/5] wifi: ath11k: Split coldboot calibration hw_param + +QCN9074 enables coldboot calibration only in Factory Test Mode (FTM). +Hence, split cold_boot_calib to two hw_params for mission and FTM +mode. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Seevalamuthu Mariappan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230726141032.3061-2-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 3 +-- + drivers/net/wireless/ath/ath11k/core.c | 36 ++++++++++++++++++++------ + drivers/net/wireless/ath/ath11k/core.h | 1 + + drivers/net/wireless/ath/ath11k/hw.h | 3 ++- + drivers/net/wireless/ath/ath11k/qmi.c | 6 ++--- + 5 files changed, 35 insertions(+), 14 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -422,8 +422,7 @@ static int ath11k_ahb_fwreset_from_cold_ + { + int timeout; + +- if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done || +- ab->hw_params.cold_boot_calib == 0 || ++ if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || + ab->hw_params.cbcal_restart_fw == 0) + return 0; + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -86,7 +86,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = true, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -167,7 +168,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = true, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -248,7 +250,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -332,7 +335,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 2, + .num_vdevs = 8, +@@ -413,7 +417,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -495,7 +500,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -578,7 +584,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -667,7 +674,8 @@ static const struct ath11k_hw_params ath + .supports_suspend = false, + .hal_params = &ath11k_hw_hal_params_ipq8074, + .single_pdev_only = false, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = true, + .fix_l1ss = true, + .supports_dynamic_smps_6ghz = false, +@@ -749,6 +757,18 @@ void ath11k_fw_stats_free(struct ath11k_ + ath11k_fw_stats_bcn_free(&stats->bcn); + } + ++bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) ++{ ++ if (!ath11k_cold_boot_cal) ++ return false; ++ ++ if (ath11k_ftm_mode) ++ return ab->hw_params.coldboot_cal_ftm; ++ ++ else ++ return ab->hw_params.coldboot_cal_mm; ++} ++ + int ath11k_core_suspend(struct ath11k_base *ab) + { + int ret; +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -1186,6 +1186,7 @@ void ath11k_core_halt(struct ath11k *ar) + int ath11k_core_resume(struct ath11k_base *ab); + int ath11k_core_suspend(struct ath11k_base *ab); + void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab); ++bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab); + + const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, + const char *filename); +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -187,7 +187,8 @@ struct ath11k_hw_params { + bool supports_shadow_regs; + bool idle_ps; + bool supports_sta_ps; +- bool cold_boot_calib; ++ bool coldboot_cal_mm; ++ bool coldboot_cal_ftm; + bool cbcal_restart_fw; + int fw_mem_mode; + u32 num_vdevs; +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -2082,7 +2082,7 @@ static int ath11k_qmi_assign_target_mem_ + return -EINVAL; + } + +- if (ath11k_cold_boot_cal && ab->hw_params.cold_boot_calib) { ++ if (ath11k_core_coldboot_cal_support(ab)) { + if (hremote_node) { + ab->qmi.target_mem[idx].paddr = + res.start + host_ddr_sz; +@@ -3212,8 +3212,8 @@ static void ath11k_qmi_driver_event_work + break; + } + +- if (ath11k_cold_boot_cal && ab->qmi.cal_done == 0 && +- ab->hw_params.cold_boot_calib) { ++ if (ab->qmi.cal_done == 0 && ++ ath11k_core_coldboot_cal_support(ab)) { + ath11k_qmi_process_coldboot_calibration(ab); + } else { + clear_bit(ATH11K_FLAG_CRASH_FLUSH, diff --git a/package/kernel/mac80211/patches/ath11k/0092-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch b/package/kernel/mac80211/patches/ath11k/0092-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch new file mode 100644 index 000000000..31b11ddee --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0092-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch @@ -0,0 +1,176 @@ +From bdfc967bf5fcd762473a01d39edb81f1165ba290 Mon Sep 17 00:00:00 2001 +From: Anilkumar Kolli +Date: Wed, 26 Jul 2023 19:40:31 +0530 +Subject: [PATCH 4/5] wifi: ath11k: Add coldboot calibration support for + QCN9074 + +QCN9074 supports 6 GHz, which has increased number of channels +compared to 5 GHz/2 GHz. So, to support coldboot calibration in +QCN9074 ATH11K_COLD_BOOT_FW_RESET_DELAY extended to 60 seconds. To +avoid code redundancy, fwreset_from_cold_boot moved to QMI and made +common for both ahb and pci. Coldboot calibration is enabled only in +FTM mode for QCN9074. QCN9074 requires firmware restart after coldboot, +hence enable cbcal_restart_fw in hw_params. + +This support can be enabled/disabled using hw params for different +hardware. Currently it is not enabled for QCA6390. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Anilkumar Kolli +Signed-off-by: Seevalamuthu Mariappan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230726141032.3061-3-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 28 ++------------------------ + drivers/net/wireless/ath/ath11k/core.c | 4 ++-- + drivers/net/wireless/ath/ath11k/pci.c | 2 ++ + drivers/net/wireless/ath/ath11k/qmi.c | 28 ++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath11k/qmi.h | 3 ++- + 5 files changed, 36 insertions(+), 29 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -14,6 +14,7 @@ + #include "ahb.h" + #include "debug.h" + #include "hif.h" ++#include "qmi.h" + #include + #include "pcic.h" + #include +@@ -418,31 +419,6 @@ static void ath11k_ahb_power_down(struct + rproc_shutdown(ab_ahb->tgt_rproc); + } + +-static int ath11k_ahb_fwreset_from_cold_boot(struct ath11k_base *ab) +-{ +- int timeout; +- +- if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || +- ab->hw_params.cbcal_restart_fw == 0) +- return 0; +- +- ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n"); +- timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, +- (ab->qmi.cal_done == 1), +- ATH11K_COLD_BOOT_FW_RESET_DELAY); +- if (timeout <= 0) { +- ath11k_cold_boot_cal = 0; +- ath11k_warn(ab, "Coldboot Calibration failed timed out\n"); +- } +- +- /* reset the firmware */ +- ath11k_ahb_power_down(ab); +- ath11k_ahb_power_up(ab); +- +- ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n"); +- return 0; +-} +- + static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab) + { + struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; +@@ -1225,7 +1201,7 @@ static int ath11k_ahb_probe(struct platf + goto err_ce_free; + } + +- ath11k_ahb_fwreset_from_cold_boot(ab); ++ ath11k_qmi_fwreset_from_cold_boot(ab); + + return 0; + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -336,8 +336,8 @@ static const struct ath11k_hw_params ath + .idle_ps = false, + .supports_sta_ps = false, + .coldboot_cal_mm = false, +- .coldboot_cal_ftm = false, +- .cbcal_restart_fw = false, ++ .coldboot_cal_ftm = true, ++ .cbcal_restart_fw = true, + .fw_mem_mode = 2, + .num_vdevs = 8, + .num_peers = 128, +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -15,6 +15,7 @@ + #include "mhi.h" + #include "debug.h" + #include "pcic.h" ++#include "qmi.h" + + #define ATH11K_PCI_BAR_NUM 0 + #define ATH11K_PCI_DMA_MASK 32 +@@ -897,6 +898,7 @@ unsupported_wcn6855_soc: + ath11k_err(ab, "failed to init core: %d\n", ret); + goto err_irq_affinity_cleanup; + } ++ ath11k_qmi_fwreset_from_cold_boot(ab); + return 0; + + err_irq_affinity_cleanup: +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -9,6 +9,7 @@ + #include "qmi.h" + #include "core.h" + #include "debug.h" ++#include "hif.h" + #include + #include + #include +@@ -2842,6 +2843,33 @@ int ath11k_qmi_firmware_start(struct ath + return 0; + } + ++int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab) ++{ ++ int timeout; ++ ++ if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || ++ ab->hw_params.cbcal_restart_fw == 0) ++ return 0; ++ ++ ath11k_dbg(ab, ATH11K_DBG_QMI, "wait for cold boot done\n"); ++ ++ timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, ++ (ab->qmi.cal_done == 1), ++ ATH11K_COLD_BOOT_FW_RESET_DELAY); ++ ++ if (timeout <= 0) { ++ ath11k_warn(ab, "Coldboot Calibration timed out\n"); ++ return -ETIMEDOUT; ++ } ++ ++ /* reset the firmware */ ++ ath11k_hif_power_down(ab); ++ ath11k_hif_power_up(ab); ++ ath11k_dbg(ab, ATH11K_DBG_QMI, "exit wait for cold boot done\n"); ++ return 0; ++} ++EXPORT_SYMBOL(ath11k_qmi_fwreset_from_cold_boot); ++ + static int ath11k_qmi_process_coldboot_calibration(struct ath11k_base *ab) + { + int timeout; +--- a/drivers/net/wireless/ath/ath11k/qmi.h ++++ b/drivers/net/wireless/ath/ath11k/qmi.h +@@ -37,7 +37,7 @@ + + #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 + #define ATH11K_FIRMWARE_MODE_OFF 4 +-#define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) ++#define ATH11K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) + + #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 + +@@ -519,5 +519,6 @@ void ath11k_qmi_msg_recv_work(struct wor + void ath11k_qmi_deinit_service(struct ath11k_base *ab); + int ath11k_qmi_init_service(struct ath11k_base *ab); + void ath11k_qmi_free_resource(struct ath11k_base *ab); ++int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab); + + #endif diff --git a/package/kernel/mac80211/patches/ath11k/0093-wifi-ath11k-Remove-cal_done-check-during-probe.patch b/package/kernel/mac80211/patches/ath11k/0093-wifi-ath11k-Remove-cal_done-check-during-probe.patch new file mode 100644 index 000000000..513ea3f0b --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0093-wifi-ath11k-Remove-cal_done-check-during-probe.patch @@ -0,0 +1,33 @@ +From 13329d0cb7212b058bd8451a99d215a8f97645ea Mon Sep 17 00:00:00 2001 +From: Seevalamuthu Mariappan +Date: Wed, 26 Jul 2023 19:40:32 +0530 +Subject: [PATCH] wifi: ath11k: Remove cal_done check during probe + +In some race conditions, calibration done QMI message is received even +before host wait starts for calibration to be done. +Due to this, resetting firmware was not performed after calibration. + +Hence, remove cal_done check in ath11k_qmi_fwreset_from_cold_boot() +as this is called only from probe. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Seevalamuthu Mariappan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230726141032.3061-4-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/qmi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -2847,7 +2847,7 @@ int ath11k_qmi_fwreset_from_cold_boot(st + { + int timeout; + +- if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || ++ if (!ath11k_core_coldboot_cal_support(ab) || + ab->hw_params.cbcal_restart_fw == 0) + return 0; + diff --git a/package/kernel/mac80211/patches/ath11k/0094-wifi-ath11k-mhi-add-a-warning-message-for-MHI_CB_EE.patch b/package/kernel/mac80211/patches/ath11k/0094-wifi-ath11k-mhi-add-a-warning-message-for-MHI_CB_EE.patch new file mode 100644 index 000000000..e1286c953 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0094-wifi-ath11k-mhi-add-a-warning-message-for-MHI_CB_EE.patch @@ -0,0 +1,34 @@ +From 4a93b554cf9fa64faa7cf164c0d32fc3ce67108b Mon Sep 17 00:00:00 2001 +From: Arowa Suliman +Date: Sat, 26 Aug 2023 08:42:42 +0300 +Subject: [PATCH] wifi: ath11k: mhi: add a warning message for MHI_CB_EE_RDDM + crash + +Currently, the ath11k driver does not print a crash signature when a +MHI_CB_EE_RDDM crash happens. Checked by triggering a simulated crash using the +command and checking dmesg for logs: + +echo assert > /sys/kernel/debug/ath11k/../simulate_fw_crash + +Add a warning when firmware crash MHI_CB_EE_RDDM happens. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 + +Signed-off-by: Arowa Suliman +Reviewed-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230714001126.463127-1-arowa@chromium.org +--- + drivers/net/wireless/ath/ath11k/mhi.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/mhi.c ++++ b/drivers/net/wireless/ath/ath11k/mhi.c +@@ -333,6 +333,7 @@ static void ath11k_mhi_op_status_cb(stru + ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); + break; + case MHI_CB_EE_RDDM: ++ ath11k_warn(ab, "firmware crashed: MHI_CB_EE_RDDM\n"); + if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags))) + queue_work(ab->workqueue_aux, &ab->reset_work); + break; diff --git a/package/kernel/mac80211/patches/ath11k/0095-wifi-ath11k-add-chip-id-board-name-while-searching-b.patch b/package/kernel/mac80211/patches/ath11k/0095-wifi-ath11k-add-chip-id-board-name-while-searching-b.patch new file mode 100644 index 000000000..662e28f4e --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0095-wifi-ath11k-add-chip-id-board-name-while-searching-b.patch @@ -0,0 +1,214 @@ +From 1133af5aea588a58043244a4ecb5ce511b310356 Mon Sep 17 00:00:00 2001 +From: Wen Gong +Date: Wed, 30 Aug 2023 02:02:26 -0400 +Subject: [PATCH] wifi: ath11k: add chip id board name while searching + board-2.bin for WCN6855 + +Sometimes board-2.bin does not have the board data which matched the +parameters such as bus type, vendor, device, subsystem-vendor, +subsystem-device, qmi-chip-id and qmi-board-id, then wlan will load fail. + +Hence add another type which only matches the bus type and qmi-chip-id, +then the ratio of missing board data reduced. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 + +Signed-off-by: Wen Gong +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230830060226.18664-1-quic_wgong@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 108 ++++++++++++++++++++----- + 1 file changed, 87 insertions(+), 21 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -985,9 +985,15 @@ int ath11k_core_check_dt(struct ath11k_b + return 0; + } + ++enum ath11k_bdf_name_type { ++ ATH11K_BDF_NAME_FULL, ++ ATH11K_BDF_NAME_BUS_NAME, ++ ATH11K_BDF_NAME_CHIP_ID, ++}; ++ + static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, + size_t name_len, bool with_variant, +- bool bus_type_mode) ++ enum ath11k_bdf_name_type name_type) + { + /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ + char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; +@@ -998,11 +1004,8 @@ static int __ath11k_core_create_board_na + + switch (ab->id.bdf_search) { + case ATH11K_BDF_SEARCH_BUS_AND_BOARD: +- if (bus_type_mode) +- scnprintf(name, name_len, +- "bus=%s", +- ath11k_bus_str(ab->hif.bus)); +- else ++ switch (name_type) { ++ case ATH11K_BDF_NAME_FULL: + scnprintf(name, name_len, + "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", + ath11k_bus_str(ab->hif.bus), +@@ -1012,6 +1015,19 @@ static int __ath11k_core_create_board_na + ab->qmi.target.chip_id, + ab->qmi.target.board_id, + variant); ++ break; ++ case ATH11K_BDF_NAME_BUS_NAME: ++ scnprintf(name, name_len, ++ "bus=%s", ++ ath11k_bus_str(ab->hif.bus)); ++ break; ++ case ATH11K_BDF_NAME_CHIP_ID: ++ scnprintf(name, name_len, ++ "bus=%s,qmi-chip-id=%d", ++ ath11k_bus_str(ab->hif.bus), ++ ab->qmi.target.chip_id); ++ break; ++ } + break; + default: + scnprintf(name, name_len, +@@ -1030,19 +1046,29 @@ static int __ath11k_core_create_board_na + static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, true, false); ++ return __ath11k_core_create_board_name(ab, name, name_len, true, ++ ATH11K_BDF_NAME_FULL); + } + + static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, false, false); ++ return __ath11k_core_create_board_name(ab, name, name_len, false, ++ ATH11K_BDF_NAME_FULL); + } + + static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, false, true); ++ return __ath11k_core_create_board_name(ab, name, name_len, false, ++ ATH11K_BDF_NAME_BUS_NAME); ++} ++ ++static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name, ++ size_t name_len) ++{ ++ return __ath11k_core_create_board_name(ab, name, name_len, false, ++ ATH11K_BDF_NAME_CHIP_ID); + } + + const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, +@@ -1289,16 +1315,21 @@ int ath11k_core_fetch_board_data_api_1(s + #define BOARD_NAME_SIZE 200 + int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) + { +- char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; ++ char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL; + char *filename, filepath[100]; +- int ret; ++ int ret = 0; + + filename = ATH11K_BOARD_API2_FILE; ++ boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); ++ if (!boardname) { ++ ret = -ENOMEM; ++ goto exit; ++ } + +- ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); ++ ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); + if (ret) { + ath11k_err(ab, "failed to create board name: %d", ret); +- return ret; ++ goto exit; + } + + ab->bd_api = 2; +@@ -1307,13 +1338,19 @@ int ath11k_core_fetch_bdf(struct ath11k_ + ATH11K_BD_IE_BOARD_NAME, + ATH11K_BD_IE_BOARD_DATA); + if (!ret) +- goto success; ++ goto exit; ++ ++ fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); ++ if (!fallback_boardname) { ++ ret = -ENOMEM; ++ goto exit; ++ } + + ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, +- sizeof(fallback_boardname)); ++ BOARD_NAME_SIZE); + if (ret) { + ath11k_err(ab, "failed to create fallback board name: %d", ret); +- return ret; ++ goto exit; + } + + ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, +@@ -1321,7 +1358,28 @@ int ath11k_core_fetch_bdf(struct ath11k_ + ATH11K_BD_IE_BOARD_NAME, + ATH11K_BD_IE_BOARD_DATA); + if (!ret) +- goto success; ++ goto exit; ++ ++ chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); ++ if (!chip_id_boardname) { ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname, ++ BOARD_NAME_SIZE); ++ if (ret) { ++ ath11k_err(ab, "failed to create chip id board name: %d", ret); ++ goto exit; ++ } ++ ++ ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname, ++ ATH11K_BD_IE_BOARD, ++ ATH11K_BD_IE_BOARD_NAME, ++ ATH11K_BD_IE_BOARD_DATA); ++ ++ if (!ret) ++ goto exit; + + ab->bd_api = 1; + ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); +@@ -1334,14 +1392,22 @@ int ath11k_core_fetch_bdf(struct ath11k_ + ath11k_err(ab, "failed to fetch board data for %s from %s\n", + fallback_boardname, filepath); + ++ ath11k_err(ab, "failed to fetch board data for %s from %s\n", ++ chip_id_boardname, filepath); ++ + ath11k_err(ab, "failed to fetch board.bin from %s\n", + ab->hw_params.fw.dir); +- return ret; + } + +-success: +- ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); +- return 0; ++exit: ++ kfree(boardname); ++ kfree(fallback_boardname); ++ kfree(chip_id_boardname); ++ ++ if (!ret) ++ ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); ++ ++ return ret; + } + + int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) diff --git a/package/kernel/mac80211/patches/ath11k/0096-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch b/package/kernel/mac80211/patches/ath11k/0096-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch new file mode 100644 index 000000000..9101a1ea1 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0096-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch @@ -0,0 +1,103 @@ +From 39564b475ac5a589e6c22c43a08cbd283c295d2c Mon Sep 17 00:00:00 2001 +From: Baochen Qiang +Date: Thu, 7 Sep 2023 09:56:06 +0800 +Subject: [PATCH] wifi: ath11k: fix boot failure with one MSI vector + +Commit 5b32b6dd96633 ("ath11k: Remove core PCI references from +PCI common code") breaks with one MSI vector because it moves +affinity setting after IRQ request, see below log: + +[ 1417.278835] ath11k_pci 0000:02:00.0: failed to receive control response completion, polling.. +[ 1418.302829] ath11k_pci 0000:02:00.0: Service connect timeout +[ 1418.302833] ath11k_pci 0000:02:00.0: failed to connect to HTT: -110 +[ 1418.303669] ath11k_pci 0000:02:00.0: failed to start core: -110 + +The detail is, if do affinity request after IRQ activated, +which is done in request_irq(), kernel caches that request and +returns success directly. Later when a subsequent MHI interrupt is +fired, kernel will do the real affinity setting work, as a result, +changs the MSI vector. However at that time host has configured +old vector to hardware, so host never receives CE or DP interrupts. + +Fix it by setting affinity before registering MHI controller +where host is, for the first time, doing IRQ request. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3 +Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-01160-QCAMSLSWPLZ-1 + +Fixes: 5b32b6dd9663 ("ath11k: Remove core PCI references from PCI common code") +Signed-off-by: Baochen Qiang +Acked-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230907015606.16297-1-quic_bqiang@quicinc.com +--- + drivers/net/wireless/ath/ath11k/pci.c | 24 ++++++++++++------------ + 1 file changed, 12 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -852,10 +852,16 @@ unsupported_wcn6855_soc: + if (ret) + goto err_pci_disable_msi; + ++ ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); ++ if (ret) { ++ ath11k_err(ab, "failed to set irq affinity %d\n", ret); ++ goto err_pci_disable_msi; ++ } ++ + ret = ath11k_mhi_register(ab_pci); + if (ret) { + ath11k_err(ab, "failed to register mhi: %d\n", ret); +- goto err_pci_disable_msi; ++ goto err_irq_affinity_cleanup; + } + + ret = ath11k_hal_srng_init(ab); +@@ -876,12 +882,6 @@ unsupported_wcn6855_soc: + goto err_ce_free; + } + +- ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); +- if (ret) { +- ath11k_err(ab, "failed to set irq affinity %d\n", ret); +- goto err_free_irq; +- } +- + /* kernel may allocate a dummy vector before request_irq and + * then allocate a real vector when request_irq is called. + * So get msi_data here again to avoid spurious interrupt +@@ -890,20 +890,17 @@ unsupported_wcn6855_soc: + ret = ath11k_pci_config_msi_data(ab_pci); + if (ret) { + ath11k_err(ab, "failed to config msi_data: %d\n", ret); +- goto err_irq_affinity_cleanup; ++ goto err_free_irq; + } + + ret = ath11k_core_init(ab); + if (ret) { + ath11k_err(ab, "failed to init core: %d\n", ret); +- goto err_irq_affinity_cleanup; ++ goto err_free_irq; + } + ath11k_qmi_fwreset_from_cold_boot(ab); + return 0; + +-err_irq_affinity_cleanup: +- ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); +- + err_free_irq: + ath11k_pcic_free_irq(ab); + +@@ -916,6 +913,9 @@ err_hal_srng_deinit: + err_mhi_unregister: + ath11k_mhi_unregister(ab_pci); + ++err_irq_affinity_cleanup: ++ ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); ++ + err_pci_disable_msi: + ath11k_pci_free_msi(ab_pci); + diff --git a/package/kernel/mac80211/patches/ath11k/0906-wifi-ath11k-disable-coldboot-for-ipq6018.patch b/package/kernel/mac80211/patches/ath11k/0906-wifi-ath11k-disable-coldboot-for-ipq6018.patch deleted file mode 100644 index 325724e68..000000000 --- a/package/kernel/mac80211/patches/ath11k/0906-wifi-ath11k-disable-coldboot-for-ipq6018.patch +++ /dev/null @@ -1,26 +0,0 @@ -From a3be23672b4a81256d275af31afc6edcce5c5a26 Mon Sep 17 00:00:00 2001 -From: Mantas Pucka -Date: Mon, 22 Jan 2024 11:38:28 +0200 -Subject: [PATCH] wifi: ath11k: disable coldboot for ipq6018 - -Coldboot calibration does not work at the moment and causes failure during -wifi startup. - -Signed-off-by: Mantas Pucka ---- - drivers/net/wireless/ath/ath11k/core.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/wireless/ath/ath11k/core.c -+++ b/drivers/net/wireless/ath/ath11k/core.c -@@ -170,8 +170,8 @@ static const struct ath11k_hw_params ath - .supports_shadow_regs = false, - .idle_ps = false, - .supports_sta_ps = false, -- .coldboot_cal_mm = true, -- .coldboot_cal_ftm = true, -+ .coldboot_cal_mm = false, -+ .coldboot_cal_ftm = false, - .cbcal_restart_fw = true, - .fw_mem_mode = 0, - .num_vdevs = 16 + 1, diff --git a/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch b/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch index f1583b6e9..30472b322 100644 --- a/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch +++ b/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch @@ -49,7 +49,7 @@ Signed-off-by: Robert Marko --- a/drivers/net/wireless/ath/ath11k/mhi.c +++ b/drivers/net/wireless/ath/ath11k/mhi.c -@@ -239,6 +239,34 @@ static void ath11k_mhi_op_runtime_put(st +@@ -294,6 +294,34 @@ static void ath11k_mhi_op_runtime_put(st { } @@ -84,7 +84,7 @@ Signed-off-by: Robert Marko static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason) { switch (reason) { -@@ -260,6 +288,8 @@ static char *ath11k_mhi_op_callback_to_s +@@ -315,6 +343,8 @@ static char *ath11k_mhi_op_callback_to_s return "MHI_CB_FATAL_ERROR"; case MHI_CB_BW_REQ: return "MHI_CB_BW_REQ"; @@ -93,7 +93,7 @@ Signed-off-by: Robert Marko default: return "UNKNOWN"; } -@@ -282,27 +312,14 @@ static void ath11k_mhi_op_status_cb(stru +@@ -337,27 +367,14 @@ static void ath11k_mhi_op_status_cb(stru if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags))) queue_work(ab->workqueue_aux, &ab->reset_work); break; @@ -126,7 +126,7 @@ Signed-off-by: Robert Marko struct device_node *np; --- a/drivers/net/wireless/ath/ath11k/mhi.h +++ b/drivers/net/wireless/ath/ath11k/mhi.h -@@ -17,6 +17,9 @@ +@@ -16,6 +16,9 @@ #define MHICTRL 0x38 #define MHICTRL_RESET_MASK 0x2 @@ -138,7 +138,7 @@ Signed-off-by: Robert Marko int ath11k_mhi_register(struct ath11k_pci *ar_pci); --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c -@@ -374,13 +374,20 @@ static void ath11k_pci_sw_reset(struct a +@@ -371,13 +371,20 @@ static void ath11k_pci_sw_reset(struct a static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) { struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; diff --git a/package/kernel/mac80211/patches/ath11k/101-wifi-ath11k-add-support-DT-ieee80211-freq-limit.patch b/package/kernel/mac80211/patches/ath11k/101-wifi-ath11k-add-support-DT-ieee80211-freq-limit.patch deleted file mode 100644 index 6088b26e6..000000000 --- a/package/kernel/mac80211/patches/ath11k/101-wifi-ath11k-add-support-DT-ieee80211-freq-limit.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 1338da257f299d35b4d954b9fda2cc7e0a54a69d Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 11 Jun 2023 14:37:32 +0200 -Subject: [PATCH] wifi: ath11k: add support DT ieee80211-freq-limit - -The common DT property can be used to limit the available -channels/frequencies. But ath11k has to manually call -wiphy_read_of_freq_limits(). - -Signed-off-by: Christian Lamparter ---- - drivers/net/wireless/ath/ath11k/mac.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/wireless/ath/ath11k/mac.c -+++ b/drivers/net/wireless/ath/ath11k/mac.c -@@ -10034,6 +10034,7 @@ static int __ath11k_mac_register(struct - if (ret) - goto err; - -+ wiphy_read_of_freq_limits(ar->hw->wiphy); - ath11k_mac_setup_ht_vht_cap(ar, cap, &ht_cap); - ath11k_mac_setup_he_cap(ar, cap); - diff --git a/package/kernel/mac80211/patches/ath11k/900-ath11k-control-thermal-support-via-symbol.patch b/package/kernel/mac80211/patches/ath11k/900-ath11k-control-thermal-support-via-symbol.patch index 6b351cc81..60720a721 100644 --- a/package/kernel/mac80211/patches/ath11k/900-ath11k-control-thermal-support-via-symbol.patch +++ b/package/kernel/mac80211/patches/ath11k/900-ath11k-control-thermal-support-via-symbol.patch @@ -34,7 +34,7 @@ Signed-off-by: Robert Marko + Enable ath11k thermal sensors and throttling support. --- a/drivers/net/wireless/ath/ath11k/Makefile +++ b/drivers/net/wireless/ath/ath11k/Makefile -@@ -23,7 +23,7 @@ ath11k-y += core.o \ +@@ -22,7 +22,7 @@ ath11k-y += core.o \ ath11k-$(CPTCFG_ATH11K_DEBUGFS) += debugfs.o debugfs_htt_stats.o debugfs_sta.o ath11k-$(CPTCFG_NL80211_TESTMODE) += testmode.o ath11k-$(CPTCFG_ATH11K_TRACING) += trace.o @@ -45,22 +45,22 @@ Signed-off-by: Robert Marko --- a/drivers/net/wireless/ath/ath11k/thermal.h +++ b/drivers/net/wireless/ath/ath11k/thermal.h -@@ -26,7 +26,7 @@ struct ath11k_thermal { +@@ -25,7 +25,7 @@ struct ath11k_thermal { int temperature; }; -#if IS_REACHABLE(CONFIG_THERMAL) +#if IS_REACHABLE(CPTCFG_ATH11K_THERMAL) - int ath11k_thermal_register(struct ath11k_base *ab); - void ath11k_thermal_unregister(struct ath11k_base *ab); + int ath11k_thermal_register(struct ath11k_base *sc); + void ath11k_thermal_unregister(struct ath11k_base *sc); int ath11k_thermal_set_throttling(struct ath11k *ar, u32 throttle_state); --- a/local-symbols +++ b/local-symbols -@@ -166,6 +166,7 @@ ATH11K_DEBUG= +@@ -174,6 +174,7 @@ ATH11K_DEBUG= ATH11K_DEBUGFS= ATH11K_TRACING= ATH11K_SPECTRAL= +ATH11K_THERMAL= - ATH12K= - ATH12K_DEBUG= - ATH12K_TRACING= + WLAN_VENDOR_ATMEL= + ATMEL= + PCI_ATMEL= diff --git a/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch b/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch new file mode 100644 index 000000000..9a0ca8009 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch @@ -0,0 +1,29 @@ +From 04178918e7f6b5f34dde81ec79ee8a1ccace3be3 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 17 Oct 2022 11:45:03 +0200 +Subject: [PATCH] wifi: ath11k: pci: fix compilation in 5.16 and older + +Commit ("genirq/msi, treewide: Use a named struct for PCI/MSI attributes") +changed the msi_desc structure a bit, however that is only available in +kernels 5.17 and newer, so check for kernel version to allow compilation +in 5.16 and older. + +Signed-off-by: Robert Marko +--- + drivers/net/wireless/ath/ath11k/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -459,7 +459,11 @@ static int ath11k_pci_alloc_msi(struct a + pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, + &ab->pci.msi.addr_lo); + ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 17, 0)) + if (msi_desc->pci.msi_attrib.is_64) { ++#else ++ if (msi_desc->msi_attrib.is_64) { ++#endif + pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, + &ab->pci.msi.addr_hi); + } else { diff --git a/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch b/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch new file mode 100644 index 000000000..0c92fa914 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch @@ -0,0 +1,26 @@ +From dd3b9c59cfa1e9e0b73a575f4646be905691eaef Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 16 Oct 2021 19:34:10 +0200 +Subject: [PATCH 241/241] ath11k: Disable coldboot calibration for IPQ8074 + +There is a bug with the remoteproc reset after coldboot calibration, +so until that is resolved disabled it to allow using the radio. + +Signed-off-by: Robert Marko +--- + drivers/net/wireless/ath/ath11k/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -86,8 +86,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .coldboot_cal_mm = true, +- .coldboot_cal_ftm = true, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = true, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, diff --git a/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch b/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch index dcf1f5f27..71373b213 100644 --- a/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch +++ b/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch @@ -22,7 +22,7 @@ Signed-off-by: Robert Marko --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c -@@ -37,7 +37,7 @@ bool ath11k_ftm_mode; +@@ -36,7 +36,7 @@ bool ath11k_ftm_mode; module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); @@ -31,7 +31,7 @@ Signed-off-by: Robert Marko { .hw_rev = ATH11K_HW_IPQ8074, .name = "ipq8074 hw2.0", -@@ -2138,7 +2138,8 @@ static void ath11k_core_reset(struct wor +@@ -2040,7 +2040,8 @@ static void ath11k_core_reset(struct wor static int ath11k_init_hw_params(struct ath11k_base *ab) { const struct ath11k_hw_params *hw_params = NULL; @@ -41,7 +41,7 @@ Signed-off-by: Robert Marko for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { hw_params = &ath11k_hw_params[i]; -@@ -2154,7 +2155,31 @@ static int ath11k_init_hw_params(struct +@@ -2056,7 +2057,31 @@ static int ath11k_init_hw_params(struct ab->hw_params = *hw_params; diff --git a/package/kernel/mac80211/patches/ath11k/905-ath11k-remove-intersection-support-for-regulatory-ru.patch b/package/kernel/mac80211/patches/ath11k/905-ath11k-remove-intersection-support-for-regulatory-ru.patch index 19f4e7dbe..b0ceb00ba 100644 --- a/package/kernel/mac80211/patches/ath11k/905-ath11k-remove-intersection-support-for-regulatory-ru.patch +++ b/package/kernel/mac80211/patches/ath11k/905-ath11k-remove-intersection-support-for-regulatory-ru.patch @@ -23,7 +23,7 @@ Signed-off-by: Aditya Kumar Singh --- a/drivers/net/wireless/ath/ath11k/reg.c +++ b/drivers/net/wireless/ath/ath11k/reg.c -@@ -363,134 +363,6 @@ static u32 ath11k_map_fw_phy_flags(u32 p +@@ -352,129 +352,6 @@ static u32 ath11k_map_fw_reg_flags(u16 r return flags; } @@ -89,11 +89,6 @@ Signed-off-by: Aditya Kumar Singh - /* Use the flags of both the rules */ - new_rule->flags = rule1->flags | rule2->flags; - -- if ((rule1->flags & NL80211_RRF_PSD) && (rule2->flags & NL80211_RRF_PSD)) -- new_rule->psd = min_t(s8, rule1->psd, rule2->psd); -- else -- new_rule->flags &= ~NL80211_RRF_PSD; -- - /* To be safe, lts use the max cac timeout of both rules */ - new_rule->dfs_cac_ms = max_t(u32, rule1->dfs_cac_ms, - rule2->dfs_cac_ms); @@ -158,22 +153,20 @@ Signed-off-by: Aditya Kumar Singh static const char * ath11k_reg_get_regdom_str(enum nl80211_dfs_regions dfs_region) { -@@ -641,11 +513,11 @@ ath11k_reg_ap_pwr_convert(enum ieee80211 +@@ -609,9 +486,9 @@ ath11k_reg_update_weather_radar_band(str struct ieee80211_regdomain * ath11k_reg_build_regd(struct ath11k_base *ab, -- struct cur_regulatory_info *reg_info, bool intersect, -+ struct cur_regulatory_info *reg_info, - enum wmi_vdev_type vdev_type, - enum ieee80211_ap_reg_power power_type) +- struct cur_regulatory_info *reg_info, bool intersect) ++ struct cur_regulatory_info *reg_info) { - struct ieee80211_regdomain *tmp_regd, *default_regd, *new_regd = NULL; + struct ieee80211_regdomain *new_regd = NULL; - struct cur_reg_rule *reg_rule, *reg_rule_6ghz; + struct cur_reg_rule *reg_rule; u8 i = 0, j = 0, k = 0; u8 num_rules; -@@ -688,26 +560,26 @@ ath11k_reg_build_regd(struct ath11k_base - } +@@ -628,26 +505,26 @@ ath11k_reg_build_regd(struct ath11k_base + num_rules += reg_info->num_6ghz_rules_ap[WMI_REG_INDOOR_AP]; if (!num_rules) - goto ret; @@ -206,16 +199,16 @@ Signed-off-by: Aditya Kumar Singh reg_info->dfs_region, num_rules); /* Update reg_rules[] below. Firmware is expected to * send these rules in order(2 GHz rules first and then 5 GHz) -@@ -746,7 +618,7 @@ ath11k_reg_build_regd(struct ath11k_base +@@ -686,7 +563,7 @@ ath11k_reg_build_regd(struct ath11k_base + flags |= ath11k_map_fw_reg_flags(reg_rule->flags); - flags |= ath11k_map_fw_phy_flags(reg_info->phybitmap); - ath11k_reg_update_rule(tmp_regd->reg_rules + i, + ath11k_reg_update_rule(new_regd->reg_rules + i, reg_rule->start_freq, reg_rule->end_freq, max_bw, reg_rule->ant_gain, reg_rule->reg_power, -@@ -761,7 +633,7 @@ ath11k_reg_build_regd(struct ath11k_base +@@ -701,7 +578,7 @@ ath11k_reg_build_regd(struct ath11k_base reg_info->dfs_region == ATH11K_DFS_REG_ETSI && (reg_rule->end_freq > ETSI_WEATHER_RADAR_BAND_LOW && reg_rule->start_freq < ETSI_WEATHER_RADAR_BAND_HIGH)){ @@ -224,7 +217,7 @@ Signed-off-by: Aditya Kumar Singh reg_rule, &i, flags, max_bw); continue; -@@ -772,51 +644,23 @@ ath11k_reg_build_regd(struct ath11k_base +@@ -712,37 +589,20 @@ ath11k_reg_build_regd(struct ath11k_base "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d) (%d, %d)\n", i + 1, reg_rule->start_freq, reg_rule->end_freq, max_bw, reg_rule->ant_gain, reg_rule->reg_power, @@ -243,8 +236,7 @@ Signed-off-by: Aditya Kumar Singh } - tmp_regd->n_reg_rules = i; -+ new_regd->n_reg_rules = i; - +- - if (intersect) { - default_regd = ab->default_regd[reg_info->phy_id]; - @@ -260,11 +252,29 @@ Signed-off-by: Aditya Kumar Singh - } else { - new_regd = tmp_regd; - } -- ++ new_regd->n_reg_rules = i; + -ret: return new_regd; } +--- a/drivers/net/wireless/ath/ath11k/reg.h ++++ b/drivers/net/wireless/ath/ath11k/reg.h +@@ -30,7 +30,7 @@ void ath11k_reg_free(struct ath11k_base + void ath11k_regd_update_work(struct work_struct *work); + struct ieee80211_regdomain * + ath11k_reg_build_regd(struct ath11k_base *ab, +- struct cur_regulatory_info *reg_info, bool intersect); ++ struct cur_regulatory_info *reg_info); + int ath11k_regd_update(struct ath11k *ar); + int ath11k_reg_update_chan_list(struct ath11k *ar, bool wait); + #endif +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -6996,24 +6996,12 @@ static void ath11k_wmi_htc_tx_complete(s + wake_up(&wmi->tx_ce_desc_wq); + } + -static bool ath11k_reg_is_world_alpha(char *alpha) -{ - if (alpha[0] == '0' && alpha[1] == '0') @@ -276,20 +286,19 @@ Signed-off-by: Aditya Kumar Singh - return false; -} - - static enum wmi_vdev_type ath11k_reg_get_ar_vdev_type(struct ath11k *ar) + static int ath11k_reg_chan_list_event(struct ath11k_base *ab, + struct sk_buff *skb, + enum wmi_reg_chan_list_cmd_type id) { - struct ath11k_vif *arvif; -@@ -839,7 +683,6 @@ int ath11k_reg_handle_chan_list(struct a - enum ieee80211_ap_reg_power power_type) - { - struct ieee80211_regdomain *regd; + struct cur_regulatory_info *reg_info = NULL; + struct ieee80211_regdomain *regd = NULL; - bool intersect = false; - int pdev_idx; + int ret = 0, pdev_idx, i, j; struct ath11k *ar; - enum wmi_vdev_type vdev_type; -@@ -891,24 +734,14 @@ int ath11k_reg_handle_chan_list(struct a + +@@ -7075,17 +7063,7 @@ static int ath11k_reg_chan_list_event(st (char *)reg_info->alpha2, 2)) - goto retfail; + goto mem_free; - /* Intersect new rules with default regd if a new country setting was - * requested, i.e a default regd was already set during initialization @@ -301,28 +310,8 @@ Signed-off-by: Aditya Kumar Singh - !ath11k_reg_is_world_alpha((char *)reg_info->alpha2)) - intersect = true; - - ar = ab->pdevs[pdev_idx].ar; - vdev_type = ath11k_reg_get_ar_vdev_type(ar); - - ath11k_dbg(ab, ATH11K_DBG_WMI, -- "wmi handle chan list power type %d vdev type %d intersect %d\n", -- power_type, vdev_type, intersect); -+ "wmi handle chan list power type %d vdev type %d\n", -+ power_type, vdev_type); - -- regd = ath11k_reg_build_regd(ab, reg_info, intersect, vdev_type, power_type); -+ regd = ath11k_reg_build_regd(ab, reg_info, vdev_type, power_type); +- regd = ath11k_reg_build_regd(ab, reg_info, intersect); ++ regd = ath11k_reg_build_regd(ab, reg_info); if (!regd) { ath11k_warn(ab, "failed to build regd from reg_info\n"); goto fallback; ---- a/drivers/net/wireless/ath/ath11k/reg.h -+++ b/drivers/net/wireless/ath/ath11k/reg.h -@@ -35,7 +35,7 @@ void ath11k_reg_free(struct ath11k_base - void ath11k_regd_update_work(struct work_struct *work); - struct ieee80211_regdomain * - ath11k_reg_build_regd(struct ath11k_base *ab, -- struct cur_regulatory_info *reg_info, bool intersect, -+ struct cur_regulatory_info *reg_info, - enum wmi_vdev_type vdev_type, - enum ieee80211_ap_reg_power power_type); - int ath11k_regd_update(struct ath11k *ar); diff --git a/package/kernel/mac80211/patches/ath11k/906-ath11k-Disable-coldboot-calibration-for-IPQ6018.patch b/package/kernel/mac80211/patches/ath11k/906-ath11k-Disable-coldboot-calibration-for-IPQ6018.patch new file mode 100644 index 000000000..39a11d722 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/906-ath11k-Disable-coldboot-calibration-for-IPQ6018.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -168,8 +168,8 @@ static struct ath11k_hw_params ath11k_hw + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .coldboot_cal_mm = true, +- .coldboot_cal_ftm = true, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = true, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, diff --git a/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch b/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch index 6ff95f95a..a63f0c881 100644 --- a/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch +++ b/package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch @@ -109,7 +109,7 @@ drivers/net/wireless/ath/ath5k/debug.c | 86 ++++++++++++++++++++++++++++++++ /* debugfs: queues etc */ -@@ -995,6 +1086,8 @@ ath5k_debug_init_device(struct ath5k_hw +@@ -997,6 +1088,8 @@ ath5k_debug_init_device(struct ath5k_hw debugfs_create_file("queue", 0600, phydir, ah, &fops_queue); debugfs_create_bool("32khz_clock", 0600, phydir, &ah->ah_use_32khz_clock); diff --git a/package/kernel/mac80211/patches/ath9k/351-ath9k_hw-issue-external-reset-for-QCA955x.patch b/package/kernel/mac80211/patches/ath9k/351-ath9k_hw-issue-external-reset-for-QCA955x.patch index aac7e1392..53b7ba08b 100644 --- a/package/kernel/mac80211/patches/ath9k/351-ath9k_hw-issue-external-reset-for-QCA955x.patch +++ b/package/kernel/mac80211/patches/ath9k/351-ath9k_hw-issue-external-reset-for-QCA955x.patch @@ -75,7 +75,7 @@ Signed-off-by: Felix Fietkau + ath_dbg(ath9k_hw_common(ah), RESET, + "reset MAC via external reset\n"); -- REG_WRITE(ah, AR_RTC_RESET(ah), 1); +- REG_WRITE(ah, AR_RTC_RESET, 1); + err = ah->external_reset(); + if (err) { + ath_err(ath9k_hw_common(ah), @@ -84,11 +84,11 @@ Signed-off-by: Felix Fietkau } + if (AR_SREV_9550(ah)) { -+ REG_WRITE(ah, AR_RTC_RESET(ah), 0); ++ REG_WRITE(ah, AR_RTC_RESET, 0); + udelay(10); + } + -+ REG_WRITE(ah, AR_RTC_RESET(ah), 1); ++ REG_WRITE(ah, AR_RTC_RESET, 1); + udelay(10); + return true; @@ -124,6 +124,6 @@ Signed-off-by: Felix Fietkau + if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) + REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); + - REG_WRITE(ah, AR_RTC_RC(ah), rst_flags); + REG_WRITE(ah, AR_RTC_RC, rst_flags); REGWRITE_BUFFER_FLUSH(ah); diff --git a/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch b/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch index a0ec7ef97..e2bbb4a1b 100644 --- a/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch +++ b/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch @@ -1,24 +1,14 @@ --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1431,6 +1431,7 @@ int ath9k_init_debug(struct ath_hw *ah) - - ath9k_cmn_debug_base_eeprom(sc->debug.debugfs_phy, sc->sc_ah); - ath9k_cmn_debug_modal_eeprom(sc->debug.debugfs_phy, sc->sc_ah); -+ ath9k_cmn_debug_eeprom(sc->debug.debugfs_phy, sc->sc_ah); - - debugfs_create_u32("gpio_mask", 0600, - sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask); ---- a/drivers/net/wireless/ath/ath9k/common-debug.c -+++ b/drivers/net/wireless/ath/ath9k/common-debug.c -@@ -260,3 +260,58 @@ void ath9k_cmn_debug_phy_err(struct dent - &fops_phy_err); +@@ -1413,6 +1413,53 @@ void ath9k_deinit_debug(struct ath_softc + ath9k_cmn_spectral_deinit_debug(&sc->spec_priv); } - EXPORT_SYMBOL(ath9k_cmn_debug_phy_err); -+ + +static ssize_t read_file_eeprom(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ -+ struct ath_hw *ah = file->private_data; ++ struct ath_softc *sc = file->private_data; ++ struct ath_hw *ah = sc->sc_ah; + struct ath_common *common = ath9k_hw_common(ah); + int bytes = 0; + int pos = *ppos; @@ -49,8 +39,7 @@ + } else { + bytes = 2; + } -+ if (copy_to_user(user_buf, from, bytes)) -+ return -EFAULT; ++ copy_to_user(user_buf, from, bytes); + user_buf += bytes; + } + return *ppos - pos; @@ -62,31 +51,15 @@ + .owner = THIS_MODULE +}; + -+void ath9k_cmn_debug_eeprom(struct dentry *debugfs_phy, -+ struct ath_hw *ah) -+{ -+ debugfs_create_file("eeprom", S_IRUSR, debugfs_phy, ah, + int ath9k_init_debug(struct ath_hw *ah) + { + struct ath_common *common = ath9k_hw_common(ah); +@@ -1432,6 +1479,8 @@ int ath9k_init_debug(struct ath_hw *ah) + ath9k_tx99_init_debug(sc); + ath9k_cmn_spectral_init_debug(&sc->spec_priv, sc->debug.debugfs_phy); + ++ debugfs_create_file("eeprom", S_IRUSR, sc->debug.debugfs_phy, sc, + &fops_eeprom); -+} -+EXPORT_SYMBOL(ath9k_cmn_debug_eeprom); ---- a/drivers/net/wireless/ath/ath9k/common-debug.h -+++ b/drivers/net/wireless/ath/ath9k/common-debug.h -@@ -69,6 +69,8 @@ void ath9k_cmn_debug_modal_eeprom(struct - struct ath_hw *ah); - void ath9k_cmn_debug_base_eeprom(struct dentry *debugfs_phy, - struct ath_hw *ah); -+void ath9k_cmn_debug_eeprom(struct dentry *debugfs_phy, -+ struct ath_hw *ah); - void ath9k_cmn_debug_stat_rx(struct ath_rx_stats *rxstats, - struct ath_rx_status *rs); - void ath9k_cmn_debug_recv(struct dentry *debugfs_phy, ---- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c -+++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c -@@ -514,6 +514,7 @@ int ath9k_htc_init_debug(struct ath_hw * - - ath9k_cmn_debug_base_eeprom(priv->debug.debugfs_phy, priv->ah); - ath9k_cmn_debug_modal_eeprom(priv->debug.debugfs_phy, priv->ah); -+ ath9k_cmn_debug_eeprom(priv->debug.debugfs_phy, priv->ah); - - return 0; - } + debugfs_create_devm_seqfile(sc->dev, "dma", sc->debug.debugfs_phy, + read_file_dma); + debugfs_create_devm_seqfile(sc->dev, "interrupt", sc->debug.debugfs_phy, diff --git a/package/kernel/mac80211/patches/ath9k/511-ath9k_reduce_rxbuf.patch b/package/kernel/mac80211/patches/ath9k/511-ath9k_reduce_rxbuf.patch index 3abf16b03..15b8d7b86 100644 --- a/package/kernel/mac80211/patches/ath9k/511-ath9k_reduce_rxbuf.patch +++ b/package/kernel/mac80211/patches/ath9k/511-ath9k_reduce_rxbuf.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/ath9k.h +++ b/drivers/net/wireless/ath/ath9k/ath9k.h -@@ -89,7 +89,7 @@ int ath_descdma_setup(struct ath_softc * +@@ -88,7 +88,7 @@ int ath_descdma_setup(struct ath_softc * (_l) &= ((_sz) - 1); \ } while (0) diff --git a/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch b/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch index 72eae8c7d..0c8b6920c 100644 --- a/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch +++ b/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch @@ -1,16 +1,70 @@ --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1432,6 +1432,7 @@ int ath9k_init_debug(struct ath_hw *ah) - ath9k_cmn_debug_base_eeprom(sc->debug.debugfs_phy, sc->sc_ah); - ath9k_cmn_debug_modal_eeprom(sc->debug.debugfs_phy, sc->sc_ah); - ath9k_cmn_debug_eeprom(sc->debug.debugfs_phy, sc->sc_ah); -+ ath9k_cmn_debug_chanbw(sc->debug.debugfs_phy, sc->sc_ah); +@@ -1460,6 +1460,52 @@ static const struct file_operations fops + .owner = THIS_MODULE + }; - debugfs_create_u32("gpio_mask", 0600, - sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask); ++ ++static ssize_t read_file_chan_bw(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) ++{ ++ struct ath_softc *sc = file->private_data; ++ struct ath_common *common = ath9k_hw_common(sc->sc_ah); ++ char buf[32]; ++ unsigned int len; ++ ++ len = sprintf(buf, "0x%08x\n", common->chan_bw); ++ return simple_read_from_buffer(user_buf, count, ppos, buf, len); ++} ++ ++static ssize_t write_file_chan_bw(struct file *file, const char __user *user_buf, ++ size_t count, loff_t *ppos) ++{ ++ struct ath_softc *sc = file->private_data; ++ struct ath_common *common = ath9k_hw_common(sc->sc_ah); ++ unsigned long chan_bw; ++ char buf[32]; ++ ssize_t len; ++ ++ len = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, len)) ++ return -EFAULT; ++ ++ buf[len] = '\0'; ++ if (kstrtoul(buf, 0, &chan_bw)) ++ return -EINVAL; ++ ++ common->chan_bw = chan_bw; ++ if (!test_bit(ATH_OP_INVALID, &common->op_flags)) ++ ath9k_ops.config(sc->hw, IEEE80211_CONF_CHANGE_CHANNEL); ++ ++ return count; ++} ++ ++static const struct file_operations fops_chanbw = { ++ .read = read_file_chan_bw, ++ .write = write_file_chan_bw, ++ .open = simple_open, ++ .owner = THIS_MODULE, ++ .llseek = default_llseek, ++}; ++ ++ + int ath9k_init_debug(struct ath_hw *ah) + { + struct ath_common *common = ath9k_hw_common(ah); +@@ -1481,6 +1527,8 @@ int ath9k_init_debug(struct ath_hw *ah) + + debugfs_create_file("eeprom", S_IRUSR, sc->debug.debugfs_phy, sc, + &fops_eeprom); ++ debugfs_create_file("chanbw", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, ++ sc, &fops_chanbw); + debugfs_create_devm_seqfile(sc->dev, "dma", sc->debug.debugfs_phy, + read_file_dma); + debugfs_create_devm_seqfile(sc->dev, "interrupt", sc->debug.debugfs_phy, --- a/drivers/net/wireless/ath/ath.h +++ b/drivers/net/wireless/ath/ath.h -@@ -151,6 +151,7 @@ struct ath_common { +@@ -149,6 +149,7 @@ struct ath_common { int debug_mask; enum ath_device_state state; unsigned long op_flags; @@ -18,14 +72,6 @@ struct ath_ani ani; -@@ -181,6 +182,7 @@ struct ath_common { - const struct ath_ops *ops; - const struct ath_bus_ops *bus_ops; - const struct ath_ps_ops *ps_ops; -+ const struct ieee80211_ops *ieee_ops; - - bool btcoex_enabled; - bool disable_ani; --- a/drivers/net/wireless/ath/ath9k/common.c +++ b/drivers/net/wireless/ath/ath9k/common.c @@ -297,11 +297,13 @@ EXPORT_SYMBOL(ath9k_cmn_get_hw_crypto_ke @@ -77,115 +123,3 @@ return channel; } ---- a/drivers/net/wireless/ath/ath9k/common-debug.c -+++ b/drivers/net/wireless/ath/ath9k/common-debug.c -@@ -315,3 +315,55 @@ void ath9k_cmn_debug_eeprom(struct dentr - &fops_eeprom); - } - EXPORT_SYMBOL(ath9k_cmn_debug_eeprom); -+ -+static ssize_t read_file_chan_bw(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ath_hw *ah = file->private_data; -+ struct ath_common *common = ath9k_hw_common(ah); -+ char buf[32]; -+ unsigned int len; -+ -+ len = sprintf(buf, "0x%08x\n", common->chan_bw); -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+} -+ -+static ssize_t write_file_chan_bw(struct file *file, const char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ath_hw *ah = file->private_data; -+ struct ath_common *common = ath9k_hw_common(ah); -+ unsigned long chan_bw; -+ char buf[32]; -+ ssize_t len; -+ -+ len = min(count, sizeof(buf) - 1); -+ if (copy_from_user(buf, user_buf, len)) -+ return -EFAULT; -+ -+ buf[len] = '\0'; -+ if (kstrtoul(buf, 0, &chan_bw)) -+ return -EINVAL; -+ -+ common->chan_bw = chan_bw; -+ if (!test_bit(ATH_OP_INVALID, &common->op_flags)) -+ common->ieee_ops->config(ah->hw, IEEE80211_CONF_CHANGE_CHANNEL); -+ -+ return count; -+} -+ -+static const struct file_operations fops_chanbw = { -+ .read = read_file_chan_bw, -+ .write = write_file_chan_bw, -+ .open = simple_open, -+ .owner = THIS_MODULE, -+ .llseek = default_llseek, -+}; -+ -+void ath9k_cmn_debug_chanbw(struct dentry *debugfs_phy, -+ struct ath_hw *ah) -+{ -+ debugfs_create_file("chanbw", S_IRUSR | S_IWUSR, debugfs_phy, ah, -+ &fops_chanbw); -+} -+EXPORT_SYMBOL(ath9k_cmn_debug_chanbw); ---- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c -+++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c -@@ -515,6 +515,7 @@ int ath9k_htc_init_debug(struct ath_hw * - ath9k_cmn_debug_base_eeprom(priv->debug.debugfs_phy, priv->ah); - ath9k_cmn_debug_modal_eeprom(priv->debug.debugfs_phy, priv->ah); - ath9k_cmn_debug_eeprom(priv->debug.debugfs_phy, priv->ah); -+ ath9k_cmn_debug_chanbw(priv->debug.debugfs_phy, priv->ah); - - return 0; - } ---- a/drivers/net/wireless/ath/ath9k/common-debug.h -+++ b/drivers/net/wireless/ath/ath9k/common-debug.h -@@ -71,6 +71,8 @@ void ath9k_cmn_debug_base_eeprom(struct - struct ath_hw *ah); - void ath9k_cmn_debug_eeprom(struct dentry *debugfs_phy, - struct ath_hw *ah); -+void ath9k_cmn_debug_chanbw(struct dentry *debugfs_phy, -+ struct ath_hw *ah); - void ath9k_cmn_debug_stat_rx(struct ath_rx_stats *rxstats, - struct ath_rx_status *rs); - void ath9k_cmn_debug_recv(struct dentry *debugfs_phy, ---- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c -+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c -@@ -631,6 +631,7 @@ static int ath9k_init_priv(struct ath9k_ - priv->ah = ah; - - common = ath9k_hw_common(ah); -+ common->ieee_ops = &ath9k_htc_ops; - common->ops = &ah->reg_ops; - common->ps_ops = &ath9k_htc_ps_ops; - common->bus_ops = &ath9k_usb_bus_ops; -@@ -746,9 +747,9 @@ static void ath9k_set_hw_capab(struct at - - hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN | - WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL | -- WIPHY_FLAG_HAS_CHANNEL_SWITCH; -- -- hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; -+ WIPHY_FLAG_HAS_CHANNEL_SWITCH | -+ WIPHY_FLAG_SUPPORTS_5_10_MHZ | -+ WIPHY_FLAG_SUPPORTS_TDLS; - - hw->queues = 4; - hw->max_listen_interval = 1; ---- a/drivers/net/wireless/ath/ath9k/init.c -+++ b/drivers/net/wireless/ath/ath9k/init.c -@@ -733,6 +733,7 @@ static int ath9k_init_softc(u16 devid, s - if (!ath9k_is_chanctx_enabled()) - sc->cur_chan->hw_queue_base = 0; - -+ common->ieee_ops = &ath9k_ops; - common->ops = &ah->reg_ops; - common->bus_ops = bus_ops; - common->ps_ops = &ath9k_ps_ops; diff --git a/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch b/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch index 1b2d4cb5d..1fe004102 100644 --- a/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch +++ b/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/ath9k.h +++ b/drivers/net/wireless/ath/ath9k/ath9k.h -@@ -844,6 +844,9 @@ static inline int ath9k_dump_btcoex(stru +@@ -843,6 +843,9 @@ static inline int ath9k_dump_btcoex(stru #ifdef CPTCFG_MAC80211_LEDS void ath_init_leds(struct ath_softc *sc); void ath_deinit_leds(struct ath_softc *sc); @@ -10,7 +10,7 @@ #else static inline void ath_init_leds(struct ath_softc *sc) { -@@ -980,6 +983,13 @@ void ath_ant_comb_scan(struct ath_softc +@@ -979,6 +982,13 @@ void ath_ant_comb_scan(struct ath_softc #define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */ @@ -24,7 +24,7 @@ struct ath_softc { struct ieee80211_hw *hw; struct device *dev; -@@ -1033,9 +1043,8 @@ struct ath_softc { +@@ -1032,9 +1042,8 @@ struct ath_softc { spinlock_t chan_lock; #ifdef CPTCFG_MAC80211_LEDS @@ -181,7 +181,7 @@ --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c -@@ -1089,7 +1089,7 @@ int ath9k_init_device(u16 devid, struct +@@ -1088,7 +1088,7 @@ int ath9k_init_device(u16 devid, struct #ifdef CPTCFG_MAC80211_LEDS /* must be initialized before ieee80211_register_hw */ @@ -192,9 +192,9 @@ #endif --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -123,6 +123,61 @@ static const struct file_operations fops - - #define DMA_BUF_LEN 1024 +@@ -1505,6 +1505,61 @@ static const struct file_operations fops + .llseek = default_llseek, + }; +#ifdef CONFIG_MAC80211_LEDS + @@ -252,12 +252,12 @@ +#endif + - static ssize_t read_file_ani(struct file *file, char __user *user_buf, - size_t count, loff_t *ppos) -@@ -1392,6 +1447,10 @@ int ath9k_init_debug(struct ath_hw *ah) - ath9k_tx99_init_debug(sc); - ath9k_cmn_spectral_init_debug(&sc->spec_priv, sc->debug.debugfs_phy); - + int ath9k_init_debug(struct ath_hw *ah) + { +@@ -1529,6 +1584,10 @@ int ath9k_init_debug(struct ath_hw *ah) + &fops_eeprom); + debugfs_create_file("chanbw", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, + sc, &fops_chanbw); +#ifdef CONFIG_MAC80211_LEDS + debugfs_create_file("gpio_led", S_IWUSR, + sc->debug.debugfs_phy, sc, &fops_gpio_led); diff --git a/package/kernel/mac80211/patches/ath9k/531-ath9k_extra_platform_leds.patch b/package/kernel/mac80211/patches/ath9k/531-ath9k_extra_platform_leds.patch index 1055bd335..8ed7ad8a0 100644 --- a/package/kernel/mac80211/patches/ath9k/531-ath9k_extra_platform_leds.patch +++ b/package/kernel/mac80211/patches/ath9k/531-ath9k_extra_platform_leds.patch @@ -1,3 +1,15 @@ +--- a/include/linux/ath9k_platform.h ++++ b/include/linux/ath9k_platform.h +@@ -46,6 +46,9 @@ struct ath9k_platform_data { + int (*external_reset)(void); + + bool use_eeprom; ++ ++ int num_leds; ++ const struct gpio_led *leds; + }; + + #endif /* _LINUX_ATH9K_PLATFORM_H */ --- a/drivers/net/wireless/ath/ath9k/gpio.c +++ b/drivers/net/wireless/ath/ath9k/gpio.c @@ -15,6 +15,7 @@ diff --git a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch index a0e5a24ed..70f7ee365 100644 --- a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch +++ b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch @@ -1,8 +1,8 @@ --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1428,6 +1428,50 @@ void ath9k_deinit_debug(struct ath_softc - ath9k_cmn_spectral_deinit_debug(&sc->spec_priv); - } +@@ -1561,6 +1561,50 @@ static const struct file_operations fops + #endif + +static ssize_t read_file_diag(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) @@ -51,7 +51,7 @@ int ath9k_init_debug(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); -@@ -1451,6 +1495,8 @@ int ath9k_init_debug(struct ath_hw *ah) +@@ -1588,6 +1632,8 @@ int ath9k_init_debug(struct ath_hw *ah) debugfs_create_file("gpio_led", S_IWUSR, sc->debug.debugfs_phy, sc, &fops_gpio_led); #endif @@ -125,7 +125,7 @@ REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c -@@ -537,6 +537,11 @@ irqreturn_t ath_isr(int irq, void *dev) +@@ -538,6 +538,11 @@ irqreturn_t ath_isr(int irq, void *dev) return IRQ_HANDLED; } diff --git a/package/kernel/mac80211/patches/ath9k/543-ath9k_entropy_from_adc.patch b/package/kernel/mac80211/patches/ath9k/543-ath9k_entropy_from_adc.patch index 0fedc7127..6acc864d1 100644 --- a/package/kernel/mac80211/patches/ath9k/543-ath9k_entropy_from_adc.patch +++ b/package/kernel/mac80211/patches/ath9k/543-ath9k_entropy_from_adc.patch @@ -18,7 +18,7 @@ void (*spectral_scan_trigger)(struct ath_hw *ah); --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c -@@ -1915,6 +1915,26 @@ void ar9003_hw_init_rate_txpower(struct +@@ -1918,6 +1918,26 @@ void ar9003_hw_init_rate_txpower(struct } } @@ -26,9 +26,9 @@ +{ + int i, j; + -+ REG_RMW_FIELD(ah, AR_PHY_TEST(ah), AR_PHY_TEST_BBB_OBS_SEL, 1); -+ REG_CLR_BIT(ah, AR_PHY_TEST(ah), AR_PHY_TEST_RX_OBS_SEL_BIT5); -+ REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS(ah), AR_PHY_TEST_CTL_RX_OBS_SEL, 0); ++ REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 1); ++ REG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5); ++ REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_RX_OBS_SEL, 0); + + memset(buf, 0, len); + for (i = 0; i < len; i++) { @@ -45,7 +45,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah) { struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); -@@ -1951,6 +1971,7 @@ void ar9003_hw_attach_phy_ops(struct ath +@@ -1954,6 +1974,7 @@ void ar9003_hw_attach_phy_ops(struct ath priv_ops->set_radar_params = ar9003_hw_set_radar_params; priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; @@ -55,7 +55,7 @@ ops->spectral_scan_config = ar9003_hw_spectral_scan_config; --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c -@@ -871,7 +871,8 @@ static void ath9k_init_txpower_limits(st +@@ -870,7 +870,8 @@ static void ath9k_init_txpower_limits(st if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ); @@ -65,7 +65,7 @@ } static const struct ieee80211_iface_limit if_limits[] = { -@@ -1049,6 +1050,18 @@ static void ath9k_set_hw_capab(struct at +@@ -1048,6 +1049,18 @@ static void ath9k_set_hw_capab(struct at wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); } @@ -84,7 +84,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, const struct ath_bus_ops *bus_ops) { -@@ -1096,6 +1109,8 @@ int ath9k_init_device(u16 devid, struct +@@ -1095,6 +1108,8 @@ int ath9k_init_device(u16 devid, struct wiphy_read_of_freq_limits(hw->wiphy); diff --git a/package/kernel/mac80211/patches/ath9k/545-ath9k_ani_ws_detect.patch b/package/kernel/mac80211/patches/ath9k/545-ath9k_ani_ws_detect.patch index 6027741cd..d3bf07ff9 100644 --- a/package/kernel/mac80211/patches/ath9k/545-ath9k_ani_ws_detect.patch +++ b/package/kernel/mac80211/patches/ath9k/545-ath9k_ani_ws_detect.patch @@ -79,7 +79,7 @@ static const u8 ofdm2pwr[] = { ALL_TARGET_LEGACY_6_24, ALL_TARGET_LEGACY_6_24, -@@ -1065,11 +1051,6 @@ static bool ar9003_hw_ani_control(struct +@@ -1068,11 +1054,6 @@ static bool ar9003_hw_ani_control(struct struct ath_common *common = ath9k_hw_common(ah); struct ath9k_channel *chan = ah->curchan; struct ar5416AniState *aniState = &ah->ani; @@ -91,7 +91,7 @@ s32 value, value2; switch (cmd & ah->ani_function) { -@@ -1083,61 +1064,6 @@ static bool ar9003_hw_ani_control(struct +@@ -1086,61 +1067,6 @@ static bool ar9003_hw_ani_control(struct */ u32 on = param ? 1 : 0; diff --git a/package/kernel/mac80211/patches/ath9k/548-ath9k_enable_gpio_chip.patch b/package/kernel/mac80211/patches/ath9k/548-ath9k_enable_gpio_chip.patch index 643d51285..78206d286 100644 --- a/package/kernel/mac80211/patches/ath9k/548-ath9k_enable_gpio_chip.patch +++ b/package/kernel/mac80211/patches/ath9k/548-ath9k_enable_gpio_chip.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- --- a/drivers/net/wireless/ath/ath9k/ath9k.h +++ b/drivers/net/wireless/ath/ath9k/ath9k.h -@@ -25,6 +25,7 @@ +@@ -24,6 +24,7 @@ #include #include #include @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau #include "common.h" #include "debug.h" -@@ -990,6 +991,14 @@ struct ath_led { +@@ -989,6 +990,14 @@ struct ath_led { struct led_classdev cdev; }; @@ -33,7 +33,7 @@ Signed-off-by: Felix Fietkau struct ath_softc { struct ieee80211_hw *hw; struct device *dev; -@@ -1045,6 +1054,9 @@ struct ath_softc { +@@ -1044,6 +1053,9 @@ struct ath_softc { #ifdef CPTCFG_MAC80211_LEDS const char *led_default_trigger; struct list_head leds; @@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau + gchip); + struct ath_hw *ah = gc->sc->sc_ah; + -+ return !((REG_READ(ah, AR_GPIO_OE_OUT(ah)) >> (offset * 2)) & 3); ++ return !((REG_READ(ah, AR_GPIO_OE_OUT) >> (offset * 2)) & 3); +} + +/* gpio_chip handler : get GPIO pin value */ diff --git a/package/kernel/mac80211/patches/ath9k/549-ath9k_enable_gpio_buttons.patch b/package/kernel/mac80211/patches/ath9k/549-ath9k_enable_gpio_buttons.patch index 0b2acf8af..716e09f35 100644 --- a/package/kernel/mac80211/patches/ath9k/549-ath9k_enable_gpio_buttons.patch +++ b/package/kernel/mac80211/patches/ath9k/549-ath9k_enable_gpio_buttons.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- --- a/drivers/net/wireless/ath/ath9k/ath9k.h +++ b/drivers/net/wireless/ath/ath9k/ath9k.h -@@ -1056,6 +1056,7 @@ struct ath_softc { +@@ -1055,6 +1055,7 @@ struct ath_softc { struct list_head leds; #ifdef CONFIG_GPIOLIB struct ath9k_gpio_chip *gpiochip; @@ -128,3 +128,16 @@ Signed-off-by: Felix Fietkau if (pdata && pdata->leds && pdata->num_leds) for (i = 0; i < pdata->num_leds; i++) { +--- a/include/linux/ath9k_platform.h ++++ b/include/linux/ath9k_platform.h +@@ -49,6 +49,10 @@ struct ath9k_platform_data { + + int num_leds; + const struct gpio_led *leds; ++ ++ unsigned num_btns; ++ const struct gpio_keys_button *btns; ++ unsigned btn_poll_interval; + }; + + #endif /* _LINUX_ATH9K_PLATFORM_H */ diff --git a/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch b/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch index 4e4cab986..efc4b9187 100644 --- a/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch +++ b/package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch @@ -339,7 +339,7 @@ static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u32 queues, bool drop); -@@ -658,6 +659,7 @@ void ath_reset_work(struct work_struct * +@@ -659,6 +660,7 @@ void ath_reset_work(struct work_struct * static int ath9k_start(struct ieee80211_hw *hw) { struct ath_softc *sc = hw->priv; @@ -347,7 +347,7 @@ struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; -@@ -736,6 +738,11 @@ static int ath9k_start(struct ieee80211_ +@@ -737,6 +739,11 @@ static int ath9k_start(struct ieee80211_ AR_GPIO_OUTPUT_MUX_AS_OUTPUT); } @@ -371,7 +371,7 @@ --- a/local-symbols +++ b/local-symbols -@@ -121,6 +121,7 @@ ATH9K_WOW= +@@ -129,6 +129,7 @@ ATH9K_WOW= ATH9K_RFKILL= ATH9K_CHANNEL_CONTEXT= ATH9K_PCOEM= @@ -400,4 +400,4 @@ + config ATH9K_DEBUGFS bool "Atheros ath9k debugging" - depends on ATH9K && DEBUG_FS && MAC80211_DEBUGFS + depends on ATH9K && DEBUG_FS diff --git a/package/kernel/mac80211/patches/ath9k/552-ath9k-ahb_of.patch b/package/kernel/mac80211/patches/ath9k/552-ath9k-ahb_of.patch index a4efdcd1b..57eef54e8 100644 --- a/package/kernel/mac80211/patches/ath9k/552-ath9k-ahb_of.patch +++ b/package/kernel/mac80211/patches/ath9k/552-ath9k-ahb_of.patch @@ -16,7 +16,7 @@ static const struct platform_device_id ath9k_platform_id_table[] = { { -@@ -69,6 +77,192 @@ static const struct ath_bus_ops ath_ahb_ +@@ -69,6 +77,236 @@ static const struct ath_bus_ops ath_ahb_ .eeprom_read = ath_ahb_eeprom_read, }; @@ -25,6 +25,47 @@ +#define QCA955X_DDR_CTL_CONFIG 0x108 +#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23) + ++static int of_get_wifi_cal(struct device_node *np, struct ath9k_platform_data *pdata) ++{ ++#ifdef CONFIG_MTD ++ struct device_node *mtd_np = NULL; ++ size_t retlen; ++ int size, ret; ++ struct mtd_info *mtd; ++ const char *part; ++ const __be32 *list; ++ phandle phandle; ++ ++ list = of_get_property(np, "mtd-cal-data", &size); ++ if (!list) ++ return 0; ++ ++ if (size != (2 * sizeof(*list))) ++ return 1; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return 1; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ mtd = get_mtd_device_nm(part); ++ if (IS_ERR(mtd)) ++ return 1; ++ ++ ret = mtd_read(mtd, be32_to_cpup(list), sizeof(pdata->eeprom_data), ++ &retlen, (u8*)pdata->eeprom_data); ++ put_mtd_device(mtd); ++ ++#endif ++ return 0; ++} ++ +static int ar913x_wmac_reset(void) +{ + ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); @@ -202,6 +243,9 @@ + + pdata->get_mac_revision = data->soc_revision; + ++ if (of_get_wifi_cal(pdev->dev.of_node, pdata)) ++ dev_err(&pdev->dev, "failed to load calibration data from mtd device\n"); ++ + return data->dev_id; +} +#endif @@ -209,7 +253,7 @@ static int ath_ahb_probe(struct platform_device *pdev) { void __iomem *mem; -@@ -80,6 +274,17 @@ static int ath_ahb_probe(struct platform +@@ -80,6 +318,17 @@ static int ath_ahb_probe(struct platform int ret = 0; struct ath_hw *ah; char hw_name[64]; @@ -227,7 +271,7 @@ if (!dev_get_platdata(&pdev->dev)) { dev_err(&pdev->dev, "no platform data specified\n"); -@@ -118,17 +323,23 @@ static int ath_ahb_probe(struct platform +@@ -118,13 +367,16 @@ static int ath_ahb_probe(struct platform sc->mem = mem; sc->irq = irq; @@ -245,15 +289,18 @@ if (ret) { dev_err(&pdev->dev, "failed to initialize device\n"); goto err_irq; +@@ -155,6 +407,9 @@ static int ath_ahb_remove(struct platfor + free_irq(sc->irq, sc); + ieee80211_free_hw(sc->hw); } +#ifdef CONFIG_OF + pdev->dev.platform_data = NULL; +#endif - ah = sc->sc_ah; - ath9k_hw_name(ah, hw_name, sizeof(hw_name)); -@@ -162,6 +373,9 @@ static struct platform_driver ath_ahb_dr - .remove_new = ath_ahb_remove, + return 0; + } +@@ -164,6 +419,9 @@ static struct platform_driver ath_ahb_dr + .remove = ath_ahb_remove, .driver = { .name = "ath9k", +#ifdef CONFIG_OF @@ -264,7 +311,7 @@ }; --- a/drivers/net/wireless/ath/ath9k/ath9k.h +++ b/drivers/net/wireless/ath/ath9k/ath9k.h -@@ -26,6 +26,7 @@ +@@ -25,6 +25,7 @@ #include #include #include @@ -272,7 +319,7 @@ #include "common.h" #include "debug.h" -@@ -1012,6 +1013,9 @@ struct ath_softc { +@@ -1011,6 +1012,9 @@ struct ath_softc { struct ath_hw *sc_ah; void __iomem *mem; int irq; diff --git a/package/kernel/mac80211/patches/ath9k/553-ath9k_of_gpio_mask.patch b/package/kernel/mac80211/patches/ath9k/553-ath9k_of_gpio_mask.patch index 752a4980a..6d1820ecb 100644 --- a/package/kernel/mac80211/patches/ath9k/553-ath9k_of_gpio_mask.patch +++ b/package/kernel/mac80211/patches/ath9k/553-ath9k_of_gpio_mask.patch @@ -13,7 +13,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, const struct ath_bus_ops *bus_ops) { -@@ -804,6 +810,9 @@ static int ath9k_init_softc(u16 devid, s +@@ -803,6 +809,9 @@ static int ath9k_init_softc(u16 devid, s if (ret) goto err_hw; diff --git a/package/kernel/mac80211/patches/brcm/810-b43-gpio-mask-module-option.patch b/package/kernel/mac80211/patches/brcm/810-b43-gpio-mask-module-option.patch index 295a4cca7..09ef50526 100644 --- a/package/kernel/mac80211/patches/brcm/810-b43-gpio-mask-module-option.patch +++ b/package/kernel/mac80211/patches/brcm/810-b43-gpio-mask-module-option.patch @@ -22,7 +22,7 @@ static int modparam_bad_frames_preempt; module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); MODULE_PARM_DESC(bad_frames_preempt, -@@ -2870,10 +2875,10 @@ static int b43_gpio_init(struct b43_wlde +@@ -2869,10 +2874,10 @@ static int b43_gpio_init(struct b43_wlde u32 mask, set; b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); diff --git a/package/kernel/mac80211/patches/brcm/812-b43-add-antenna-control.patch b/package/kernel/mac80211/patches/brcm/812-b43-add-antenna-control.patch index e9f915d2d..22b67c49d 100644 --- a/package/kernel/mac80211/patches/brcm/812-b43-add-antenna-control.patch +++ b/package/kernel/mac80211/patches/brcm/812-b43-add-antenna-control.patch @@ -9,7 +9,7 @@ antenna = b43_antenna_to_phyctl(antenna); ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); /* We can't send beacons with short preamble. Would get PHY errors. */ -@@ -3285,8 +3285,8 @@ static int b43_chip_init(struct b43_wlde +@@ -3284,8 +3284,8 @@ static int b43_chip_init(struct b43_wlde /* Select the antennae */ if (phy->ops->set_rx_antenna) @@ -20,7 +20,7 @@ if (phy->type == B43_PHYTYPE_B) { value16 = b43_read16(dev, 0x005E); -@@ -3988,7 +3988,6 @@ static int b43_op_config(struct ieee8021 +@@ -3986,7 +3986,6 @@ static int b43_op_config(struct ieee8021 struct b43_wldev *dev = wl->current_dev; struct b43_phy *phy = &dev->phy; struct ieee80211_conf *conf = &hw->conf; @@ -28,7 +28,7 @@ int err = 0; mutex_lock(&wl->mutex); -@@ -4031,11 +4030,9 @@ static int b43_op_config(struct ieee8021 +@@ -4029,11 +4028,9 @@ static int b43_op_config(struct ieee8021 } /* Antennas for RX and management frame TX. */ @@ -42,7 +42,7 @@ if (wl->radio_enabled != phy->radio_on) { if (wl->radio_enabled) { -@@ -5178,6 +5175,47 @@ static int b43_op_get_survey(struct ieee +@@ -5176,6 +5173,47 @@ static int b43_op_get_survey(struct ieee return 0; } @@ -88,9 +88,9 @@ +} + static const struct ieee80211_ops b43_hw_ops = { - .add_chanctx = ieee80211_emulate_add_chanctx, - .remove_chanctx = ieee80211_emulate_remove_chanctx, -@@ -5204,6 +5242,8 @@ static const struct ieee80211_ops b43_hw + .tx = b43_op_tx, + .wake_tx_queue = ieee80211_handle_wake_tx_queue, +@@ -5198,6 +5236,8 @@ static const struct ieee80211_ops b43_hw .sw_scan_complete = b43_op_sw_scan_complete_notifier, .get_survey = b43_op_get_survey, .rfkill_poll = b43_rfkill_poll, @@ -99,7 +99,7 @@ }; /* Hard-reset the chip. Do not call this directly. -@@ -5505,6 +5545,8 @@ static int b43_one_core_attach(struct b4 +@@ -5499,6 +5539,8 @@ static int b43_one_core_attach(struct b4 if (!wldev) goto out; @@ -108,7 +108,7 @@ wldev->use_pio = b43_modparam_pio; wldev->dev = dev; wldev->wl = wl; -@@ -5596,6 +5638,9 @@ static struct b43_wl *b43_wireless_init( +@@ -5590,6 +5632,9 @@ static struct b43_wl *b43_wireless_init( wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); diff --git a/package/kernel/mac80211/patches/brcm/814-b43-only-use-gpio-0-1-for-led.patch b/package/kernel/mac80211/patches/brcm/814-b43-only-use-gpio-0-1-for-led.patch index f7aa41320..9cb0a32fd 100644 --- a/package/kernel/mac80211/patches/brcm/814-b43-only-use-gpio-0-1-for-led.patch +++ b/package/kernel/mac80211/patches/brcm/814-b43-only-use-gpio-0-1-for-led.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/broadcom/b43/main.c +++ b/drivers/net/wireless/broadcom/b43/main.c -@@ -2887,6 +2887,14 @@ static int b43_gpio_init(struct b43_wlde +@@ -2886,6 +2886,14 @@ static int b43_gpio_init(struct b43_wlde } else if (dev->dev->chip_id == 0x5354) { /* Don't allow overtaking buttons GPIOs */ set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */ diff --git a/package/kernel/mac80211/patches/brcm/860-brcmfmac-register-wiphy-s-during-module_init.patch b/package/kernel/mac80211/patches/brcm/860-brcmfmac-register-wiphy-s-during-module_init.patch new file mode 100644 index 000000000..9d0f3e20b --- /dev/null +++ b/package/kernel/mac80211/patches/brcm/860-brcmfmac-register-wiphy-s-during-module_init.patch @@ -0,0 +1,64 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 8 Jun 2015 16:11:40 +0200 +Subject: [PATCH] brcmfmac: register wiphy(s) during module_init +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is needed by OpenWrt which expects all PHYs to be created after +module loads successfully. + +Signed-off-by: Rafał Miłecki +--- + +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c +@@ -459,6 +459,7 @@ struct brcmf_fw { + u32 curpos; + unsigned int board_index; + void (*done)(struct device *dev, int err, struct brcmf_fw_request *req); ++ struct completion *completion; + }; + + #ifdef CONFIG_EFI +@@ -686,6 +687,8 @@ static void brcmf_fw_request_done(const + fwctx->req = NULL; + } + fwctx->done(fwctx->dev, ret, fwctx->req); ++ if (fwctx->completion) ++ complete(fwctx->completion); + kfree(fwctx); + } + +@@ -751,6 +754,8 @@ int brcmf_fw_get_firmwares(struct device + { + struct brcmf_fw_item *first = &req->items[0]; + struct brcmf_fw *fwctx; ++ struct completion completion; ++ unsigned long time_left; + char *alt_path = NULL; + int ret; + +@@ -768,6 +773,9 @@ int brcmf_fw_get_firmwares(struct device + fwctx->dev = dev; + fwctx->req = req; + fwctx->done = fw_cb; ++ ++ init_completion(&completion); ++ fwctx->completion = &completion; + + /* First try alternative board-specific path if any */ + if (fwctx->req->board_types[0]) +@@ -787,6 +795,12 @@ int brcmf_fw_get_firmwares(struct device + if (ret < 0) + brcmf_fw_request_done(NULL, fwctx); + ++ ++ time_left = wait_for_completion_timeout(&completion, ++ msecs_to_jiffies(5000)); ++ if (!time_left && fwctx) ++ fwctx->completion = NULL; ++ + return 0; + } + diff --git a/package/kernel/mac80211/patches/brcm/861-brcmfmac-workaround-bug-with-some-inconsistent-BSSes.patch b/package/kernel/mac80211/patches/brcm/861-brcmfmac-workaround-bug-with-some-inconsistent-BSSes.patch index 84b989d85..b82b442a1 100644 --- a/package/kernel/mac80211/patches/brcm/861-brcmfmac-workaround-bug-with-some-inconsistent-BSSes.patch +++ b/package/kernel/mac80211/patches/brcm/861-brcmfmac-workaround-bug-with-some-inconsistent-BSSes.patch @@ -10,7 +10,7 @@ Signed-off-by: Rafał Miłecki --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c -@@ -980,8 +980,36 @@ static struct wireless_dev *brcmf_cfg802 +@@ -713,8 +713,36 @@ static struct wireless_dev *brcmf_cfg802 struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy); struct brcmf_pub *drvr = cfg->pub; struct wireless_dev *wdev; diff --git a/package/kernel/mac80211/patches/brcm/862-brcmfmac-Disable-power-management.patch b/package/kernel/mac80211/patches/brcm/862-brcmfmac-Disable-power-management.patch index 9f91b29c4..080ab8f7e 100644 --- a/package/kernel/mac80211/patches/brcm/862-brcmfmac-Disable-power-management.patch +++ b/package/kernel/mac80211/patches/brcm/862-brcmfmac-Disable-power-management.patch @@ -14,7 +14,7 @@ Signed-off-by: Phil Elwell --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c -@@ -3313,6 +3313,10 @@ brcmf_cfg80211_set_power_mgmt(struct wip +@@ -2976,6 +2976,10 @@ brcmf_cfg80211_set_power_mgmt(struct wip * preference in cfg struct to apply this to * FW later while initializing the dongle */ diff --git a/package/kernel/mac80211/patches/brcm/863-brcmfmac-add-in-driver-tables-with-country-codes.patch b/package/kernel/mac80211/patches/brcm/863-brcmfmac-add-in-driver-tables-with-country-codes.patch index f873528e2..25191b643 100644 --- a/package/kernel/mac80211/patches/brcm/863-brcmfmac-add-in-driver-tables-with-country-codes.patch +++ b/package/kernel/mac80211/patches/brcm/863-brcmfmac-add-in-driver-tables-with-country-codes.patch @@ -49,7 +49,7 @@ Signed-off-by: Rafał Miłecki void brcmf_of_probe(struct device *dev, enum brcmf_bus_type bus_type, struct brcmf_mp_device *settings) { -@@ -113,6 +143,8 @@ void brcmf_of_probe(struct device *dev, +@@ -106,6 +136,8 @@ void brcmf_of_probe(struct device *dev, of_node_put(root); } diff --git a/package/kernel/mac80211/patches/brcm/865-brcmfmac-Read-alternative-firmware-names-from-DT.patch b/package/kernel/mac80211/patches/brcm/865-brcmfmac-Read-alternative-firmware-names-from-DT.patch new file mode 100644 index 000000000..8ed81f600 --- /dev/null +++ b/package/kernel/mac80211/patches/brcm/865-brcmfmac-Read-alternative-firmware-names-from-DT.patch @@ -0,0 +1,187 @@ +From 4e32024cbb14230af3048e249e84f8c2b25ce45a Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 28 Oct 2021 15:03:16 +0100 +Subject: [PATCH] brcmfmac: Read alternative firmware names from DT + +Add the ability to load the names of alternative firmwares from the +Device Tree node. This permits separate firmwares for 43436s and 43438 +and allows downstream firmwares to coexist with upstream. + +Signed-off-by: Phil Elwell +--- + .../wireless/broadcom/brcm80211/brcmfmac/of.c | 36 ++++++++++++++ + .../wireless/broadcom/brcm80211/brcmfmac/of.h | 7 +++ + .../broadcom/brcm80211/brcmfmac/sdio.c | 47 +++++++++++++++++-- + 3 files changed, 87 insertions(+), 3 deletions(-) + +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c +@@ -11,6 +11,7 @@ + #include "debug.h" + #include "core.h" + #include "common.h" ++#include "firmware.h" + #include "of.h" + + static int brcmf_of_get_country_codes(struct device *dev, +@@ -168,3 +169,38 @@ void brcmf_of_probe(struct device *dev, + sdio->oob_irq_nr = irq; + sdio->oob_irq_flags = irqf; + } ++ ++struct brcmf_firmware_mapping * ++brcmf_of_fwnames(struct device *dev, u32 *fwname_count) ++{ ++ struct device_node *np = dev->of_node; ++ struct brcmf_firmware_mapping *fwnames; ++ struct device_node *map_np, *fw_np; ++ int of_count; ++ int count = 0; ++ ++ map_np = of_get_child_by_name(np, "firmwares"); ++ of_count = of_get_child_count(map_np); ++ if (!of_count) ++ return NULL; ++ ++ fwnames = devm_kcalloc(dev, of_count, ++ sizeof(struct brcmf_firmware_mapping), ++ GFP_KERNEL); ++ ++ for_each_child_of_node(map_np, fw_np) ++ { ++ struct brcmf_firmware_mapping *cur = &fwnames[count]; ++ ++ if (of_property_read_u32(fw_np, "chipid", &cur->chipid) || ++ of_property_read_u32(fw_np, "revmask", &cur->revmask)) ++ continue; ++ cur->fw_base = of_get_property(fw_np, "fw_base", NULL); ++ if (cur->fw_base) ++ count++; ++ } ++ ++ *fwname_count = count; ++ ++ return count ? fwnames : NULL; ++} +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.h ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.h +@@ -5,9 +5,16 @@ + #ifdef CONFIG_OF + void brcmf_of_probe(struct device *dev, enum brcmf_bus_type bus_type, + struct brcmf_mp_device *settings); ++struct brcmf_firmware_mapping * ++brcmf_of_fwnames(struct device *dev, u32 *map_count); + #else + static void brcmf_of_probe(struct device *dev, enum brcmf_bus_type bus_type, + struct brcmf_mp_device *settings) + { + } ++static struct brcmf_firmware_mapping * ++brcmf_of_fwnames(struct device *dev, u32 *map_count) ++{ ++ return NULL; ++} + #endif /* CONFIG_OF */ +--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +@@ -35,6 +35,7 @@ + #include "core.h" + #include "common.h" + #include "bcdc.h" ++#include "of.h" + + #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) + #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) +@@ -634,7 +635,7 @@ MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "b + /* per-board firmware binaries */ + MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin"); + +-static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { ++static const struct brcmf_firmware_mapping sdio_fwnames[] = { + BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), + BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), + BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), +@@ -662,6 +663,9 @@ static const struct brcmf_firmware_mappi + BRCMF_FW_ENTRY(CY_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752) + }; + ++static const struct brcmf_firmware_mapping *brcmf_sdio_fwnames = sdio_fwnames; ++static u32 brcmf_sdio_fwnames_count = ARRAY_SIZE(sdio_fwnames); ++ + #define TXCTL_CREDITS 2 + + static void pkt_align(struct sk_buff *p, int len, int align) +@@ -4193,6 +4197,9 @@ static const struct brcmf_bus_ops brcmf_ + #define BRCMF_SDIO_FW_NVRAM 1 + #define BRCMF_SDIO_FW_CLM 2 + ++static struct brcmf_fw_request * ++brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus); ++ + static void brcmf_sdio_firmware_callback(struct device *dev, int err, + struct brcmf_fw_request *fwreq) + { +@@ -4208,6 +4215,22 @@ static void brcmf_sdio_firmware_callback + + brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); + ++ if (err && brcmf_sdio_fwnames != sdio_fwnames) { ++ /* Try again with the standard firmware names */ ++ brcmf_sdio_fwnames = sdio_fwnames; ++ brcmf_sdio_fwnames_count = ARRAY_SIZE(sdio_fwnames); ++ kfree(fwreq); ++ fwreq = brcmf_sdio_prepare_fw_request(bus); ++ if (!fwreq) { ++ err = -ENOMEM; ++ goto fail; ++ } ++ err = brcmf_fw_get_firmwares(dev, fwreq, ++ brcmf_sdio_firmware_callback); ++ if (!err) ++ return; ++ } ++ + if (err) + goto fail; + +@@ -4418,7 +4441,7 @@ brcmf_sdio_prepare_fw_request(struct brc + + fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev, + brcmf_sdio_fwnames, +- ARRAY_SIZE(brcmf_sdio_fwnames), ++ brcmf_sdio_fwnames_count, + fwnames, ARRAY_SIZE(fwnames)); + if (!fwreq) + return NULL; +@@ -4438,6 +4461,9 @@ struct brcmf_sdio *brcmf_sdio_probe(stru + struct brcmf_sdio *bus; + struct workqueue_struct *wq; + struct brcmf_fw_request *fwreq; ++ struct brcmf_firmware_mapping *of_fwnames, *fwnames = NULL; ++ const int fwname_size = sizeof(struct brcmf_firmware_mapping); ++ u32 of_fw_count; + + brcmf_dbg(TRACE, "Enter\n"); + +@@ -4520,6 +4546,21 @@ struct brcmf_sdio *brcmf_sdio_probe(stru + + brcmf_dbg(INFO, "completed!!\n"); + ++ of_fwnames = brcmf_of_fwnames(sdiodev->dev, &of_fw_count); ++ if (of_fwnames) ++ fwnames = devm_kcalloc(sdiodev->dev, ++ of_fw_count + brcmf_sdio_fwnames_count, ++ fwname_size, GFP_KERNEL); ++ ++ if (fwnames) { ++ /* The array is scanned in order, so overrides come first */ ++ memcpy(fwnames, of_fwnames, of_fw_count * fwname_size); ++ memcpy(fwnames + of_fw_count, sdio_fwnames, ++ brcmf_sdio_fwnames_count * fwname_size); ++ brcmf_sdio_fwnames = fwnames; ++ brcmf_sdio_fwnames_count += of_fw_count; ++ } ++ + fwreq = brcmf_sdio_prepare_fw_request(bus); + if (!fwreq) { + ret = -ENOMEM; diff --git a/package/kernel/mac80211/patches/brcm/865-brcmfmac-disable-dump_survey-on-bcm2835.patch b/package/kernel/mac80211/patches/brcm/865-brcmfmac-disable-dump_survey-on-bcm2835.patch deleted file mode 100644 index 975647444..000000000 --- a/package/kernel/mac80211/patches/brcm/865-brcmfmac-disable-dump_survey-on-bcm2835.patch +++ /dev/null @@ -1,38 +0,0 @@ -brcmfmac: disable dump_survey on Raspberry Pi - -Enabling this causes slow iwinfo calls on Raspberry Pi and LuCI slows down -when wireless is enabled. -https://github.com/openwrt/openwrt/issues/14013 - -Signed-off-by: Álvaro Fernández Rojas ---- - ---- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c -+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c -@@ -7979,6 +7979,7 @@ static s32 brcmf_translate_country_code( - return 0; - } - -+#if !defined(CONFIG_ARCH_BCM2835) - static int - brcmf_parse_dump_obss(char *buf, struct brcmf_dump_survey *survey) - { -@@ -8201,6 +8202,7 @@ exit: - brcmf_set_mpc(ifp, 1); - return err; - } -+#endif /* CONFIG_ARCH_BCM2835 */ - - static void brcmf_cfg80211_reg_notifier(struct wiphy *wiphy, - struct regulatory_request *req) -@@ -8353,8 +8355,10 @@ struct brcmf_cfg80211_info *brcmf_cfg802 - if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_WOWL_GTK)) - ops->set_rekey_data = brcmf_cfg80211_set_rekey_data; - #endif -+#if !defined(CONFIG_ARCH_BCM2835) - if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_DUMP_OBSS)) - ops->dump_survey = brcmf_cfg80211_dump_survey; -+#endif /* CONFIG_ARCH_BCM2835 */ - - err = wiphy_register(wiphy); - if (err < 0) { diff --git a/package/kernel/mac80211/patches/build/001-fix_build.patch b/package/kernel/mac80211/patches/build/001-fix_build.patch index 085eae3cd..8f63d36e2 100644 --- a/package/kernel/mac80211/patches/build/001-fix_build.patch +++ b/package/kernel/mac80211/patches/build/001-fix_build.patch @@ -27,7 +27,7 @@ @set -e ; test -f local-symbols || ( \ echo "/--------------" ;\ echo "| You shouldn't run make in the backports tree, but only in" ;\ -@@ -60,57 +62,62 @@ mrproper: +@@ -60,58 +62,62 @@ mrproper: echo "| (that isn't currently running.)" ;\ echo "\\--" ;\ false) @@ -56,12 +56,13 @@ - done \ - ) > Kconfig.kernel ;\ - kver=$$($(MAKE) --no-print-directory -C $(KLIB_BUILD) M=$(BACKPORT_DIR) \ -- kernelversion | sed 's/^\(\([3-6]\|2\.6\)\.[0-9]\+\).*/\1/;t;d');\ +- kernelversion | sed 's/^\(\([3-5]\|2\.6\)\.[0-9]\+\).*/\1/;t;d');\ - test "$$kver" != "" || echo "Kernel version parse failed!" ;\ - test "$$kver" != "" ;\ +- kvers="$$(seq 14 39 | sed 's/^/2.6./')" ;\ +- kvers="$$kvers $$(seq 0 19 | sed 's/^/3./')" ;\ - kvers="$$kvers $$(seq 0 20 | sed 's/^/4./')" ;\ -- kvers="$$kvers $$(seq 0 19 | sed 's/^/5./')" ;\ -- kvers="$$kvers $$(seq 0 20 | sed 's/^/6./')" ;\ +- kvers="$$kvers $$(seq 0 99 | sed 's/^/5./')" ;\ - print=0 ;\ - for v in $$kvers ; do \ - if [ "$$print" = "1" ] ; then \ @@ -111,13 +112,14 @@ + @echo " done." + +Kconfig.versions: Kconfig.kernel -+ @kver=$$($(MAKE) --no-print-directory -C $(KLIB_BUILD) M=$(BACKPORT_DIR) \ -+ kernelversion | sed 's/^\(\([3-6]\|2\.6\)\.[0-9]\+\).*/\1/;t;d');\ ++ @kver=$$($(MAKE) --no-print-directory -C $(KLIB_BUILD) M=$(BACKPORT_DIR) \ ++ kernelversion | sed 's/^\(\([3-5]\|2\.6\)\.[0-9]\+\).*/\1/;t;d');\ + test "$$kver" != "" || echo "Kernel version parse failed!" ;\ + test "$$kver" != "" ;\ ++ kvers="$$(seq 14 39 | sed 's/^/2.6./')" ;\ ++ kvers="$$kvers $$(seq 0 19 | sed 's/^/3./')" ;\ + kvers="$$kvers $$(seq 0 20 | sed 's/^/4./')" ;\ -+ kvers="$$kvers $$(seq 0 19 | sed 's/^/5./')" ;\ -+ kvers="$$kvers $$(seq 0 20 | sed 's/^/6./')" ;\ ++ kvers="$$kvers $$(seq 0 99 | sed 's/^/5./')" ;\ + print=0 ;\ + for v in $$kvers ; do \ + if [ "$$print" = "1" ] ; then \ @@ -125,9 +127,8 @@ + echo " def_bool y" ;\ + fi ;\ + if [ "$$v" = "$$kver" ] ; then print=1 ; fi ;\ -+ done > Kconfig.versions ;\ -+ # RHEL as well, sadly we need to grep for it ;\ -+ RHEL_MAJOR=$$(grep '^RHEL_MAJOR' $(KERNEL_MAKEFILE) | \ ++ done > $@ ++ @RHEL_MAJOR=$$(grep '^RHEL_MAJOR' $(KERNEL_MAKEFILE) | \ + sed 's/.*=\s*\([0-9]*\)/\1/;t;d') ;\ + RHEL_MINOR=$$(grep '^RHEL_MINOR' $(KERNEL_MAKEFILE) | \ + sed 's/.*=\s*\([0-9]*\)/\1/;t;d') ;\ diff --git a/package/kernel/mac80211/patches/build/004-fix-kconf-compiling.patch b/package/kernel/mac80211/patches/build/004-fix-kconf-compiling.patch deleted file mode 100644 index 8bae8367f..000000000 --- a/package/kernel/mac80211/patches/build/004-fix-kconf-compiling.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/Makefile.real -+++ b/Makefile.real -@@ -6,6 +6,18 @@ else - export BACKPORTS_GIT_TRACKER_DEF= - endif - -+ifneq ($(LLVM),) -+ifneq ($(filter %/,$(LLVM)),) -+LLVM_PREFIX := $(LLVM) -+else ifneq ($(filter -%,$(LLVM)),) -+LLVM_SUFFIX := $(LLVM) -+endif -+ -+HOSTCC = $(LLVM_PREFIX)clang$(LLVM_SUFFIX) -+else -+HOSTCC = gcc -+endif -+ - # disable built-in rules for this file - .SUFFIXES: - -@@ -24,21 +36,21 @@ listnewconfig oldaskconfig oldconfig \ - silentoldconfig olddefconfig oldnoconfig \ - allnoconfig allyesconfig allmodconfig \ - alldefconfig randconfig: -- @$(MAKE) -C kconf conf -+ @$(MAKE) -C kconf CC=$(HOSTCC) conf - @./kconf/conf --$@ Kconfig - - .PHONY: usedefconfig - usedefconfig: -- @$(MAKE) -C kconf conf -+ @$(MAKE) -C kconf CC=$(HOSTCC) conf - @./kconf/conf --defconfig=defconfig Kconfig - - .PHONY: savedefconfig - savedefconfig: -- @$(MAKE) -C kconf conf -+ @$(MAKE) -C kconf CC=$(HOSTCC) conf - @./kconf/conf --savedefconfig=defconfig Kconfig - - defconfig-%:: -- @$(MAKE) -C kconf conf -+ @$(MAKE) -C kconf CC=$(HOSTCC) conf - @./kconf/conf --defconfig=defconfigs/$(@:defconfig-%=%) Kconfig - - .config: diff --git a/package/kernel/mac80211/patches/build/050-lib80211_option.patch b/package/kernel/mac80211/patches/build/050-lib80211_option.patch new file mode 100644 index 000000000..c1b1bc757 --- /dev/null +++ b/package/kernel/mac80211/patches/build/050-lib80211_option.patch @@ -0,0 +1,34 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -188,7 +188,7 @@ config CFG80211_WEXT_EXPORT + endif # CFG80211 + + config LIB80211 +- tristate ++ tristate "lib80211" + depends on m + default n + help +@@ -198,19 +198,19 @@ config LIB80211 + Drivers should select this themselves if needed. + + config LIB80211_CRYPT_WEP +- tristate ++ tristate "lib80211 WEP support" + depends on m + select BPAUTO_CRYPTO_LIB_ARC4 + + config LIB80211_CRYPT_CCMP +- tristate ++ tristate "lib80211 CCMP support" + depends on m + depends on CRYPTO + depends on CRYPTO_AES + depends on CRYPTO_CCM + + config LIB80211_CRYPT_TKIP +- tristate ++ tristate "lib80211 TKIP support" + depends on m + select BPAUTO_CRYPTO_LIB_ARC4 + diff --git a/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch b/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch index 0dad745b4..4ad2ac081 100644 --- a/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch +++ b/package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch @@ -1,6 +1,6 @@ --- a/local-symbols +++ b/local-symbols -@@ -471,43 +471,6 @@ USB_VL600= +@@ -470,43 +470,6 @@ USB_VL600= USB_NET_CH9200= USB_NET_AQC111= USB_RTL8153_ECM= @@ -90,7 +90,7 @@ config B43_PHY_G --- a/drivers/net/wireless/broadcom/b43/main.c +++ b/drivers/net/wireless/broadcom/b43/main.c -@@ -2854,7 +2854,7 @@ static struct ssb_device *b43_ssb_gpio_d +@@ -2853,7 +2853,7 @@ static struct ssb_device *b43_ssb_gpio_d { struct ssb_bus *bus = dev->dev->sdev->bus; @@ -99,7 +99,7 @@ return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); #else return bus->chipco.dev; -@@ -4873,7 +4873,7 @@ static int b43_wireless_core_init(struct +@@ -4871,7 +4871,7 @@ static int b43_wireless_core_init(struct } if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ @@ -171,7 +171,7 @@ depends on CORDIC --- a/Kconfig.local +++ b/Kconfig.local -@@ -1417,117 +1417,6 @@ config BACKPORTED_USB_NET_AQC111 +@@ -1414,117 +1414,6 @@ config BACKPORTED_USB_NET_AQC111 config BACKPORTED_USB_RTL8153_ECM tristate default USB_RTL8153_ECM @@ -303,7 +303,7 @@ source "$BACKPORT_DIR/drivers/staging/Kconfig" --- a/Makefile.kernel +++ b/Makefile.kernel -@@ -42,8 +42,6 @@ obj-$(CPTCFG_QRTR) += net/qrtr/ +@@ -43,8 +43,6 @@ obj-$(CPTCFG_QRTR) += net/qrtr/ obj-$(CPTCFG_QCOM_QMI_HELPERS) += drivers/soc/qcom/ obj-$(CPTCFG_MHI_BUS) += drivers/bus/mhi/ obj-$(CPTCFG_WLAN) += drivers/net/wireless/ diff --git a/package/kernel/mac80211/patches/build/080-resv_start_op.patch b/package/kernel/mac80211/patches/build/080-resv_start_op.patch new file mode 100644 index 000000000..40b8e94a2 --- /dev/null +++ b/package/kernel/mac80211/patches/build/080-resv_start_op.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/wireless/mac80211_hwsim.c ++++ b/drivers/net/wireless/mac80211_hwsim.c +@@ -5363,7 +5363,9 @@ static struct genl_family hwsim_genl_fam + .module = THIS_MODULE, + .small_ops = hwsim_ops, + .n_small_ops = ARRAY_SIZE(hwsim_ops), ++#if LINUX_VERSION_IS_GEQ(6,1,0) + .resv_start_op = HWSIM_CMD_DEL_MAC_ADDR + 1, ++#endif + .mcgrps = hwsim_mcgrps, + .n_mcgrps = ARRAY_SIZE(hwsim_mcgrps), + }; +--- a/net/wireless/nl80211.c ++++ b/net/wireless/nl80211.c +@@ -17233,7 +17233,9 @@ static struct genl_family nl80211_fam __ + .n_ops = ARRAY_SIZE(nl80211_ops), + .small_ops = nl80211_small_ops, + .n_small_ops = ARRAY_SIZE(nl80211_small_ops), ++#if LINUX_VERSION_IS_GEQ(6,1,0) + .resv_start_op = NL80211_CMD_REMOVE_LINK_STA + 1, ++#endif + .mcgrps = nl80211_mcgrps, + .n_mcgrps = ARRAY_SIZE(nl80211_mcgrps), + .parallel_ops = true, diff --git a/package/kernel/mac80211/patches/build/099-netlink-range.patch b/package/kernel/mac80211/patches/build/099-netlink-range.patch new file mode 100644 index 000000000..0df2b38fa --- /dev/null +++ b/package/kernel/mac80211/patches/build/099-netlink-range.patch @@ -0,0 +1,91 @@ +--- a/net/wireless/nl80211.c ++++ b/net/wireless/nl80211.c +@@ -421,8 +421,13 @@ static const struct nla_policy + nl80211_fils_discovery_policy[NL80211_FILS_DISCOVERY_ATTR_MAX + 1] = { + [NL80211_FILS_DISCOVERY_ATTR_INT_MIN] = NLA_POLICY_MAX(NLA_U32, 10000), + [NL80211_FILS_DISCOVERY_ATTR_INT_MAX] = NLA_POLICY_MAX(NLA_U32, 10000), ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_FILS_DISCOVERY_ATTR_TMPL] = + NLA_POLICY_BINARY_RANGE(NL80211_FILS_DISCOVERY_TMPL_MIN_LEN, IEEE80211_MAX_DATA_LEN), ++#else ++ [NL80211_FILS_DISCOVERY_ATTR_TMPL] = { .type = NLA_BINARY, ++ .len = IEEE80211_MAX_DATA_LEN }, ++#endif + }; + + static const struct nla_policy +@@ -533,7 +538,11 @@ static const struct nla_policy nl80211_p + [NL80211_ATTR_MPATH_NEXT_HOP] = NLA_POLICY_ETH_ADDR_COMPAT, + + /* allow 3 for NUL-termination, we used to declare this NLA_STRING */ ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_REG_ALPHA2] = NLA_POLICY_BINARY_RANGE(2, 3), ++#else ++ [NL80211_ATTR_REG_ALPHA2] = { .type = NLA_STRING, .len = 2 }, ++#endif + [NL80211_ATTR_REG_RULES] = { .type = NLA_NESTED }, + + [NL80211_ATTR_BSS_CTS_PROT] = { .type = NLA_U8 }, +@@ -679,14 +688,24 @@ static const struct nla_policy nl80211_p + * The value of the Length field of the Supported Operating + * Classes element is between 2 and 253. + */ ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES] = + NLA_POLICY_BINARY_RANGE(2, 253), ++#else ++ [NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES] = ++ { .type = NLA_BINARY }, ++#endif + [NL80211_ATTR_HANDLE_DFS] = { .type = NLA_FLAG }, + [NL80211_ATTR_OPMODE_NOTIF] = { .type = NLA_U8 }, + [NL80211_ATTR_VENDOR_ID] = { .type = NLA_U32 }, + [NL80211_ATTR_VENDOR_SUBCMD] = { .type = NLA_U32 }, + [NL80211_ATTR_VENDOR_DATA] = { .type = NLA_BINARY }, ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_QOS_MAP] = NLA_POLICY_BINARY_RANGE(IEEE80211_QOS_MAP_LEN_MIN, IEEE80211_QOS_MAP_LEN_MAX), ++#else ++ [NL80211_ATTR_QOS_MAP] = { .type = NLA_BINARY, ++ .len = IEEE80211_QOS_MAP_LEN_MAX }, ++#endif + [NL80211_ATTR_MAC_HINT] = NLA_POLICY_EXACT_LEN_WARN(ETH_ALEN), + [NL80211_ATTR_WIPHY_FREQ_HINT] = { .type = NLA_U32 }, + [NL80211_ATTR_TDLS_PEER_CAPABILITY] = { .type = NLA_U32 }, +@@ -741,9 +760,14 @@ static const struct nla_policy nl80211_p + [NL80211_ATTR_TXQ_LIMIT] = { .type = NLA_U32 }, + [NL80211_ATTR_TXQ_MEMORY_LIMIT] = { .type = NLA_U32 }, + [NL80211_ATTR_TXQ_QUANTUM] = { .type = NLA_U32 }, ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_HE_CAPABILITY] = + NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_he_capa, + NL80211_HE_MAX_CAPABILITY_LEN), ++#else ++ [NL80211_ATTR_HE_CAPABILITY] = { .type = NLA_BINARY, ++ .len = NL80211_HE_MAX_CAPABILITY_LEN }, ++#endif + [NL80211_ATTR_FTM_RESPONDER] = + NLA_POLICY_NESTED(nl80211_ftm_responder_policy), + [NL80211_ATTR_TIMEOUT] = NLA_POLICY_MIN(NLA_U32, 1), +@@ -16392,9 +16416,11 @@ static const struct genl_ops nl80211_ops + /* can be retrieved by unprivileged users */ + .internal_flags = IFLAGS(NL80211_FLAG_NEED_WIPHY), + }, ++#if LINUX_VERSION_IS_GEQ(5,10,0) + }; + + static const struct genl_small_ops nl80211_small_ops[] = { ++#endif + { + .cmd = NL80211_CMD_SET_WIPHY, + .validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP, +@@ -17231,8 +17257,10 @@ static struct genl_family nl80211_fam __ + .module = THIS_MODULE, + .ops = nl80211_ops, + .n_ops = ARRAY_SIZE(nl80211_ops), ++#if LINUX_VERSION_IS_GEQ(5,10,0) + .small_ops = nl80211_small_ops, + .n_small_ops = ARRAY_SIZE(nl80211_small_ops), ++#endif + #if LINUX_VERSION_IS_GEQ(6,1,0) + .resv_start_op = NL80211_CMD_REMOVE_LINK_STA + 1, + #endif diff --git a/package/kernel/mac80211/patches/build/100-backports-drop-QRTR-and-MHI.patch b/package/kernel/mac80211/patches/build/100-backports-drop-QRTR-and-MHI.patch index a3a65c2d2..b017a0ce1 100644 --- a/package/kernel/mac80211/patches/build/100-backports-drop-QRTR-and-MHI.patch +++ b/package/kernel/mac80211/patches/build/100-backports-drop-QRTR-and-MHI.patch @@ -32,7 +32,7 @@ Signed-off-by: Robert Marko source "$BACKPORT_DIR/drivers/net/usb/Kconfig" --- a/Makefile.kernel +++ b/Makefile.kernel -@@ -38,9 +38,7 @@ obj-y += compat/ +@@ -39,9 +39,7 @@ obj-y += compat/ obj-$(CPTCFG_CFG80211) += net/wireless/ obj-$(CPTCFG_MAC80211) += net/mac80211/ @@ -59,7 +59,7 @@ Signed-off-by: Robert Marko --- a/local-symbols +++ b/local-symbols -@@ -59,14 +59,6 @@ MAC80211_MESH_PS_DEBUG= +@@ -65,14 +65,6 @@ MAC80211_MESH_PS_DEBUG= MAC80211_TDLS_DEBUG= MAC80211_DEBUG_COUNTERS= MAC80211_STA_HASH_MAX_SIZE= @@ -73,4 +73,4 @@ Signed-off-by: Robert Marko -MHI_BUS_EP= QCOM_AOSS_QMP= QCOM_COMMAND_DB= - QCOM_GENI_SE= + QCOM_CPR= diff --git a/package/kernel/mac80211/patches/build/110-backport_namepace_const.patch b/package/kernel/mac80211/patches/build/110-backport_namepace_const.patch deleted file mode 100644 index 6dca708ed..000000000 --- a/package/kernel/mac80211/patches/build/110-backport_namepace_const.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/net/wireless/sysfs.c -+++ b/net/wireless/sysfs.c -@@ -154,7 +154,11 @@ static SIMPLE_DEV_PM_OPS(wiphy_pm_ops, w - #define WIPHY_PM_OPS NULL - #endif - -+#if LINUX_VERSION_IS_GEQ(6,2,0) - static const void *wiphy_namespace(const struct device *d) -+#else -+static const void *wiphy_namespace(struct device *d) -+#endif - { - struct wiphy *wiphy = container_of(d, struct wiphy, dev); - diff --git a/package/kernel/mac80211/patches/build/110-backport_napi_build_skb.patch b/package/kernel/mac80211/patches/build/110-backport_napi_build_skb.patch new file mode 100644 index 000000000..1e152fece --- /dev/null +++ b/package/kernel/mac80211/patches/build/110-backport_napi_build_skb.patch @@ -0,0 +1,11 @@ +--- a/backport-include/linux/skbuff.h ++++ b/backport-include/linux/skbuff.h +@@ -144,4 +144,8 @@ static inline u64 skb_get_kcov_handle(st + #define napi_build_skb build_skb + #endif + ++#if LINUX_VERSION_IS_LESS(5,11,0) ++#define napi_build_skb build_skb ++#endif ++ + #endif /* __BACKPORT_SKBUFF_H */ diff --git a/package/kernel/mac80211/patches/build/120-headers_version_fix.patch b/package/kernel/mac80211/patches/build/120-headers_version_fix.patch deleted file mode 100644 index 21cf0b313..000000000 --- a/package/kernel/mac80211/patches/build/120-headers_version_fix.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/backport-include/linux/random.h -+++ b/backport-include/linux/random.h -@@ -15,7 +15,7 @@ static inline u16 get_random_u16(void) - } - #endif - --#if LINUX_VERSION_IS_LESS(6,2,0) -+#if LINUX_VERSION_IS_LESS(6,1,4) - static inline u32 __get_random_u32_below(u32 ceil) - { - /* ---- a/backport-include/net/dropreason.h -+++ b/backport-include/net/dropreason.h -@@ -3,10 +3,9 @@ - - #include - -+#include - #if LINUX_VERSION_IS_GEQ(6,0,0) - #include_next --#else --#include - #endif - - #if LINUX_VERSION_IS_LESS(6,4,0) diff --git a/package/kernel/mac80211/patches/build/130-iommu_backport.patch b/package/kernel/mac80211/patches/build/130-iommu_backport.patch deleted file mode 100644 index 2d3ef88d6..000000000 --- a/package/kernel/mac80211/patches/build/130-iommu_backport.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- /dev/null -+++ b/backport-include/linux/iommu.h -@@ -0,0 +1,23 @@ -+#ifndef __BACKPORT_LINUX_IOMMU_H -+#define __BACKPORT_LINUX_IOMMU_H -+ -+#include_next -+#include -+ -+#if LINUX_VERSION_IS_LESS(6,3,0) -+ -+static inline int LINUX_BACKPORT(iommu_map)(struct iommu_domain *domain, -+ unsigned long iova, -+ phys_addr_t paddr, size_t size, -+ int prot, gfp_t gfp) -+{ -+ if (gfp == GFP_ATOMIC) -+ return iommu_map_atomic(domain, iova, paddr, size, prot); -+ -+ return iommu_map(domain, iova, paddr, size, prot); -+} -+#define iommu_map LINUX_BACKPORT(iommu_map) -+ -+#endif /* < 6.3 */ -+ -+#endif diff --git a/package/kernel/mac80211/patches/build/200-iwlwifi_thermal_backport.patch b/package/kernel/mac80211/patches/build/200-iwlwifi_thermal_backport.patch deleted file mode 100644 index ad398d4d9..000000000 --- a/package/kernel/mac80211/patches/build/200-iwlwifi_thermal_backport.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/net/wireless/intel/iwlwifi/mvm/tt.c -+++ b/drivers/net/wireless/intel/iwlwifi/mvm/tt.c -@@ -689,13 +689,23 @@ static void iwl_mvm_thermal_zone_registe - for (i = 0 ; i < IWL_MAX_DTS_TRIPS; i++) { - mvm->tz_device.trips[i].temperature = THERMAL_TEMP_INVALID; - mvm->tz_device.trips[i].type = THERMAL_TRIP_PASSIVE; -+#if LINUX_VERSION_IS_GEQ(6,9,0) - mvm->tz_device.trips[i].flags = THERMAL_TRIP_FLAG_RW_TEMP; -+#endif - } -+#if LINUX_VERSION_IS_GEQ(6,9,0) - mvm->tz_device.tzone = thermal_zone_device_register_with_trips(name, - mvm->tz_device.trips, - IWL_MAX_DTS_TRIPS, - mvm, &tzone_ops, - NULL, 0, 0); -+#else -+ mvm->tz_device.tzone = thermal_zone_device_register_with_trips(name, -+ mvm->tz_device.trips, -+ IWL_MAX_DTS_TRIPS, 0, -+ mvm, &tzone_ops, -+ NULL, 0, 0); -+#endif - if (IS_ERR(mvm->tz_device.tzone)) { - IWL_DEBUG_TEMP(mvm, - "Failed to register to thermal zone (err = %ld)\n", diff --git a/package/kernel/mac80211/patches/build/210-backport_genl_split_ops.patch b/package/kernel/mac80211/patches/build/210-backport_genl_split_ops.patch deleted file mode 100644 index d9d6b8a75..000000000 --- a/package/kernel/mac80211/patches/build/210-backport_genl_split_ops.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/net/wireless/nl80211.c -+++ b/net/wireless/nl80211.c -@@ -16383,9 +16383,14 @@ static u32 nl80211_internal_flags[] = { - #undef SELECTOR - }; - -+#if LINUX_VERSION_IS_LESS(6,2,0) -+static int nl80211_pre_doit(const struct genl_ops *ops, struct sk_buff *skb, -+ struct genl_info *info) -+#else - static int nl80211_pre_doit(const struct genl_split_ops *ops, - struct sk_buff *skb, - struct genl_info *info) -+#endif - { - struct cfg80211_registered_device *rdev = NULL; - struct wireless_dev *wdev = NULL; -@@ -16485,9 +16490,14 @@ out_unlock: - return err; - } - -+#if LINUX_VERSION_IS_LESS(6,2,0) -+static void nl80211_post_doit(const struct genl_ops *ops, struct sk_buff *skb, -+ struct genl_info *info) -+#else - static void nl80211_post_doit(const struct genl_split_ops *ops, - struct sk_buff *skb, - struct genl_info *info) -+#endif - { - u32 internal_flags = nl80211_internal_flags[ops->internal_flags]; - diff --git a/package/kernel/mac80211/patches/build/220-list-don-t-backport-list_count_nodes.patch b/package/kernel/mac80211/patches/build/220-list-don-t-backport-list_count_nodes.patch deleted file mode 100644 index 6d3000278..000000000 --- a/package/kernel/mac80211/patches/build/220-list-don-t-backport-list_count_nodes.patch +++ /dev/null @@ -1,26 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 15 Dec 2023 10:17:21 +0100 -Subject: [PATCH] list: don't backport list_count_nodes() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's redundant in OpenWrt as it backports it on its own. This fixes: -backport-include/linux/list.h:11:22: error: redefinition of 'list_count_nodes' - -Signed-off-by: Rafał Miłecki ---- - backport-include/linux/list.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/backport-include/linux/list.h -+++ b/backport-include/linux/list.h -@@ -3,7 +3,7 @@ - #include_next - #include - --#if LINUX_VERSION_IS_LESS(6,3,0) -+#if 0 /* OpenWrt backports list_count_nodes() on its own */ - /** - * list_count_nodes - count nodes in the list - * @head: the head for your list. diff --git a/package/kernel/mac80211/patches/build/230-brcmfmac_usb_driver_backport.patch b/package/kernel/mac80211/patches/build/230-brcmfmac_usb_driver_backport.patch deleted file mode 100644 index daeea3837..000000000 --- a/package/kernel/mac80211/patches/build/230-brcmfmac_usb_driver_backport.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c -+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c -@@ -1581,7 +1581,11 @@ static int brcmf_usb_reset_device(struct - - void brcmf_usb_exit(void) - { -+#if LINUX_VERSION_IS_GEQ(6,8,0) - struct device_driver *drv = &brcmf_usbdrvr.driver; -+#else -+ struct device_driver *drv = &brcmf_usbdrvr.drvwrap.driver; -+#endif - int ret; - - brcmf_dbg(USB, "Enter\n"); diff --git a/package/kernel/mac80211/patches/build/990-add_kernel_6.6_support.patch b/package/kernel/mac80211/patches/build/990-add_kernel_6.6_support.patch new file mode 100644 index 000000000..2ced0316d --- /dev/null +++ b/package/kernel/mac80211/patches/build/990-add_kernel_6.6_support.patch @@ -0,0 +1,113 @@ +--- a/net/wireless/sysfs.c ++++ b/net/wireless/sysfs.c +@@ -148,12 +148,21 @@ static SIMPLE_DEV_PM_OPS(wiphy_pm_ops, w + #define WIPHY_PM_OPS NULL + #endif + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) ++static const void *wiphy_namespace(const struct device *d) ++{ ++ struct wiphy *wiphy = container_of(d, struct wiphy, dev); ++ ++ return wiphy_net(wiphy); ++} ++#else + static const void *wiphy_namespace(struct device *d) + { + struct wiphy *wiphy = container_of(d, struct wiphy, dev); + + return wiphy_net(wiphy); + } ++#endif + + struct class ieee80211_class = { + .name = "ieee80211", +--- a/net/wireless/nl80211.c ++++ b/net/wireless/nl80211.c +@@ -16158,8 +16158,14 @@ static u32 nl80211_internal_flags[] = { + #undef SELECTOR + }; + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) ++static int nl80211_pre_doit(const struct genl_split_ops *ops, ++ struct sk_buff *skb, ++ struct genl_info *info) ++#else + static int nl80211_pre_doit(const struct genl_ops *ops, struct sk_buff *skb, + struct genl_info *info) ++#endif + { + struct cfg80211_registered_device *rdev = NULL; + struct wireless_dev *wdev = NULL; +@@ -16259,8 +16265,14 @@ out_unlock: + return err; + } + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) ++static void nl80211_post_doit(const struct genl_split_ops *ops, ++ struct sk_buff *skb, ++ struct genl_info *info) ++#else + static void nl80211_post_doit(const struct genl_ops *ops, struct sk_buff *skb, + struct genl_info *info) ++#endif + { + u32 internal_flags = nl80211_internal_flags[ops->internal_flags]; + +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -27,6 +27,10 @@ + #include + #include + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) ++#include ++#endif ++ + #include "ieee80211_i.h" + #include "driver-ops.h" + #include "led.h" +--- a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c +@@ -10,6 +10,10 @@ + #include + #include + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) ++#include ++#endif ++ + #include "iwl-trans.h" + #include "iwl-eeprom-parse.h" + #include "mvm.h" +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -1435,6 +1435,7 @@ enum mac80211_rx_encoding { + RX_ENC_HT, + RX_ENC_VHT, + RX_ENC_HE, ++ RX_ENC_EHT, + }; + + /** +@@ -1497,8 +1498,18 @@ struct ieee80211_rx_status { + u32 flag; + u16 freq: 13, freq_offset: 1; + u8 enc_flags; +- u8 encoding:2, bw:3, he_ru:3; +- u8 he_gi:2, he_dcm:1; ++ u8 encoding:3, bw:4; ++ union { ++ struct { ++ u8 he_ru:3; ++ u8 he_gi:2; ++ u8 he_dcm:1; ++ }; ++ struct { ++ u8 ru:4; ++ u8 gi:2; ++ } eht; ++ }; + u8 rate_idx; + u8 nss; + u8 rx_flags; diff --git a/package/kernel/mac80211/patches/mwl/700-mwl8k-missing-pci-id-for-WNR854T.patch b/package/kernel/mac80211/patches/mwl/700-mwl8k-missing-pci-id-for-WNR854T.patch index fb774b520..11536651b 100644 --- a/package/kernel/mac80211/patches/mwl/700-mwl8k-missing-pci-id-for-WNR854T.patch +++ b/package/kernel/mac80211/patches/mwl/700-mwl8k-missing-pci-id-for-WNR854T.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/marvell/mwl8k.c +++ b/drivers/net/wireless/marvell/mwl8k.c -@@ -5707,6 +5707,7 @@ MODULE_FIRMWARE("mwl8k/fmimage_8366.fw") +@@ -5703,6 +5703,7 @@ MODULE_FIRMWARE("mwl8k/fmimage_8366.fw") MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API)); static const struct pci_device_id mwl8k_pci_id_table[] = { diff --git a/package/kernel/mac80211/patches/mwl/801-libertas-configure-sysfs-links.patch b/package/kernel/mac80211/patches/mwl/801-libertas-configure-sysfs-links.patch index 4d9d3de46..1dbcb1bfe 100644 --- a/package/kernel/mac80211/patches/mwl/801-libertas-configure-sysfs-links.patch +++ b/package/kernel/mac80211/patches/mwl/801-libertas-configure-sysfs-links.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/marvell/libertas/cfg.c +++ b/drivers/net/wireless/marvell/libertas/cfg.c -@@ -2101,6 +2101,8 @@ struct wireless_dev *lbs_cfg_alloc(struc +@@ -2052,6 +2052,8 @@ struct wireless_dev *lbs_cfg_alloc(struc goto err_wiphy_new; } diff --git a/package/kernel/mac80211/patches/mwl/802-libertas-set-wireless-macaddr.patch b/package/kernel/mac80211/patches/mwl/802-libertas-set-wireless-macaddr.patch index 9aa559979..b47aee549 100644 --- a/package/kernel/mac80211/patches/mwl/802-libertas-set-wireless-macaddr.patch +++ b/package/kernel/mac80211/patches/mwl/802-libertas-set-wireless-macaddr.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/marvell/libertas/cfg.c +++ b/drivers/net/wireless/marvell/libertas/cfg.c -@@ -2178,6 +2178,8 @@ int lbs_cfg_register(struct lbs_private +@@ -2128,6 +2128,8 @@ int lbs_cfg_register(struct lbs_private wdev->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites); wdev->wiphy->reg_notifier = lbs_reg_notifier; diff --git a/package/kernel/mac80211/patches/mwl/940-mwl8k_init_devices_synchronously.patch b/package/kernel/mac80211/patches/mwl/940-mwl8k_init_devices_synchronously.patch index 06edc441e..c8d24283a 100644 --- a/package/kernel/mac80211/patches/mwl/940-mwl8k_init_devices_synchronously.patch +++ b/package/kernel/mac80211/patches/mwl/940-mwl8k_init_devices_synchronously.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/marvell/mwl8k.c +++ b/drivers/net/wireless/marvell/mwl8k.c -@@ -6293,6 +6293,8 @@ static int mwl8k_probe(struct pci_dev *p +@@ -6289,6 +6289,8 @@ static int mwl8k_probe(struct pci_dev *p priv->running_bsses = 0; @@ -9,7 +9,7 @@ return rc; err_stop_firmware: -@@ -6326,8 +6328,6 @@ static void mwl8k_remove(struct pci_dev +@@ -6322,8 +6324,6 @@ static void mwl8k_remove(struct pci_dev return; priv = hw->priv; diff --git a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch index a7ecabde8..98ed9e60e 100644 --- a/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch +++ b/package/kernel/mac80211/patches/mwl/950-mwifiex-Print-stringified-name-of-command-in-error-l.patch @@ -139,7 +139,7 @@ Signed-off-by: Pali Rohár mwifiex_init_fw_complete(adapter); return -1; } else if (adapter->last_init_cmd == cmdresp_no) -@@ -1265,8 +1345,8 @@ mwifiex_process_sleep_confirm_resp(struc +@@ -1273,8 +1353,8 @@ mwifiex_process_sleep_confirm_resp(struc if (command != HostCmd_CMD_802_11_PS_MODE_ENH) { mwifiex_dbg(adapter, ERROR, @@ -152,7 +152,7 @@ Signed-off-by: Pali Rohár --- a/drivers/net/wireless/marvell/mwifiex/main.h +++ b/drivers/net/wireless/marvell/mwifiex/main.h -@@ -1084,6 +1084,8 @@ void mwifiex_cancel_all_pending_cmd(stru +@@ -1099,6 +1099,8 @@ void mwifiex_cancel_all_pending_cmd(stru void mwifiex_cancel_pending_scan_cmd(struct mwifiex_adapter *adapter); void mwifiex_cancel_scan(struct mwifiex_adapter *adapter); @@ -177,7 +177,7 @@ Signed-off-by: Pali Rohár adapter->cmd_wait_q.status = -1; --- a/drivers/net/wireless/marvell/mwifiex/uap_cmd.c +++ b/drivers/net/wireless/marvell/mwifiex/uap_cmd.c -@@ -802,7 +802,8 @@ int mwifiex_uap_prepare_cmd(struct mwifi +@@ -794,7 +794,8 @@ int mwifiex_uap_prepare_cmd(struct mwifi break; default: mwifiex_dbg(priv->adapter, ERROR, diff --git a/package/kernel/mac80211/patches/rt2x00/602-02-wifi-rt2x00-Add-option-to-pass-EEPROM-file-name-from.patch b/package/kernel/mac80211/patches/rt2x00/602-02-wifi-rt2x00-Add-option-to-pass-EEPROM-file-name-from.patch deleted file mode 100644 index 90055b911..000000000 --- a/package/kernel/mac80211/patches/rt2x00/602-02-wifi-rt2x00-Add-option-to-pass-EEPROM-file-name-from.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 15329d8b206d9c04ffad49aecd37f5d0bfb85768 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Sun, 15 Oct 2023 14:23:19 +0200 -Subject: [PATCH 2/5] wifi: rt2x00: Add option to pass EEPROM file name from DT - -Add option to pass EEPROM file name from DT using ralink,eeprom binding. - -Signed-off-by: Christian Marangi ---- - drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -@@ -10,6 +10,7 @@ - - #include - #include -+#include - - #include "rt2x00.h" - #include "rt2x00soc.h" -@@ -18,10 +19,20 @@ static const char * - rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev) - { - struct rt2x00_platform_data *pdata = rt2x00dev->dev->platform_data; -+#ifdef CONFIG_OF -+ struct device_node *np; -+ const char *eep; -+#endif - - if (pdata && pdata->eeprom_file_name) - return pdata->eeprom_file_name; - -+#ifdef CONFIG_OF -+ np = rt2x00dev->dev->of_node; -+ if (np && !of_property_read_string(np, "ralink,eeprom", &eep)) -+ return eep; -+#endif -+ - return NULL; - } - diff --git a/package/kernel/mac80211/patches/rt2x00/602-04-wifi-rt2x00-Support-EEPROM-swap-binding.patch b/package/kernel/mac80211/patches/rt2x00/602-04-wifi-rt2x00-Support-EEPROM-swap-binding.patch deleted file mode 100644 index 392910d22..000000000 --- a/package/kernel/mac80211/patches/rt2x00/602-04-wifi-rt2x00-Support-EEPROM-swap-binding.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 9c9a3c27b96e057f3c3f47151d7a170d84e3bb5f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Sun, 15 Oct 2023 15:31:47 +0200 -Subject: [PATCH 4/5] wifi: rt2x00: Support EEPROM swap binding - -Add binding "ralink,eeprom-swap" to swap bytes of EEPROM before using -it. - -Signed-off-by: Christian Marangi ---- - drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -@@ -20,6 +20,19 @@ - #include "rt2x00soc.h" - - #if IS_ENABLED(CONFIG_MTD) -+static void rt2800lib_eeprom_swap(struct rt2x00_dev *rt2x00dev) -+{ -+ struct device_node *np = rt2x00dev->dev->of_node; -+ size_t len = rt2x00dev->ops->eeprom_size; -+ int i; -+ -+ if (!of_find_property(np, "ralink,eeprom-swap", NULL)) -+ return; -+ -+ for (i = 0; i < len / sizeof(u16); i++) -+ rt2x00dev->eeprom[i] = swab16(rt2x00dev->eeprom[i]); -+} -+ - static int rt2800lib_read_eeprom_mtd(struct rt2x00_dev *rt2x00dev) - { - int ret = -EINVAL; -@@ -66,6 +79,8 @@ static int rt2800lib_read_eeprom_mtd(str - return ret; - } - -+ rt2800lib_eeprom_swap(rt2x00dev); -+ - dev_info(rt2x00dev->dev, "loaded eeprom from mtd device \"%s\"\n", part); - #endif - diff --git a/package/kernel/mac80211/patches/rt2x00/602-05-wifi-rt2x00-support-loading-eeprom-from-NVMEM-cells.patch b/package/kernel/mac80211/patches/rt2x00/602-05-wifi-rt2x00-support-loading-eeprom-from-NVMEM-cells.patch deleted file mode 100644 index e6633363b..000000000 --- a/package/kernel/mac80211/patches/rt2x00/602-05-wifi-rt2x00-support-loading-eeprom-from-NVMEM-cells.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 9008cdacdc41f8233f4444b86cf3a17201686e2d Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Tue, 18 Jul 2023 20:18:16 +0800 -Subject: [PATCH 5/5] wifi: rt2x00: support loading eeprom from NVMEM cells - -This patch allows rt2x00 to load eeprom from "eeprom" NVMEM cell. - -Example: - -/* load eeprom from NVMEM provider 'eep' */ -&wmac { - nvmem-cells = <&eep>; - nvmem-cell-names = "eeprom"; -}; - -Signed-off-by: Shiji Yang -Signed-off-by: Christian Marangi ---- - .../net/wireless/ralink/rt2x00/rt2x00eeprom.c | 41 ++++++++++++++++++- - 1 file changed, 40 insertions(+), 1 deletion(-) - ---- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -@@ -14,12 +14,12 @@ - #include - #include - #endif -+#include - #include - - #include "rt2x00.h" - #include "rt2x00soc.h" - --#if IS_ENABLED(CONFIG_MTD) - static void rt2800lib_eeprom_swap(struct rt2x00_dev *rt2x00dev) - { - struct device_node *np = rt2x00dev->dev->of_node; -@@ -33,6 +33,7 @@ static void rt2800lib_eeprom_swap(struct - rt2x00dev->eeprom[i] = swab16(rt2x00dev->eeprom[i]); - } - -+#if IS_ENABLED(CONFIG_MTD) - static int rt2800lib_read_eeprom_mtd(struct rt2x00_dev *rt2x00dev) - { - int ret = -EINVAL; -@@ -88,6 +89,40 @@ static int rt2800lib_read_eeprom_mtd(str - } - #endif - -+static int rt2800lib_read_eeprom_nvmem(struct rt2x00_dev *rt2x00dev) -+{ -+ struct device_node *np = rt2x00dev->dev->of_node; -+ unsigned int len = rt2x00dev->ops->eeprom_size; -+ struct nvmem_cell *cell; -+ const void *data; -+ size_t retlen; -+ int ret = 0; -+ -+ cell = of_nvmem_cell_get(np, "eeprom"); -+ if (IS_ERR(cell)) -+ return PTR_ERR(cell); -+ -+ data = nvmem_cell_read(cell, &retlen); -+ nvmem_cell_put(cell); -+ -+ if (IS_ERR(data)) -+ return PTR_ERR(data); -+ -+ if (retlen != len) { -+ dev_err(rt2x00dev->dev, "invalid eeprom size, required: 0x%04x\n", len); -+ ret = -EINVAL; -+ goto exit; -+ } -+ -+ memcpy(rt2x00dev->eeprom, data, len); -+ -+ rt2800lib_eeprom_swap(rt2x00dev); -+ -+exit: -+ kfree(data); -+ return ret; -+} -+ - static const char * - rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev) - { -@@ -164,6 +199,10 @@ int rt2x00lib_read_eeprom(struct rt2x00_ - return 0; - #endif - -+ ret = rt2800lib_read_eeprom_nvmem(rt2x00dev); -+ if (!ret) -+ return 0; -+ - return rt2x00lib_read_eeprom_file(rt2x00dev); - } - EXPORT_SYMBOL_GPL(rt2x00lib_read_eeprom); diff --git a/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch b/package/kernel/mac80211/patches/rt2x00/602-rt2x00-introduce-rt2x00eeprom.patch similarity index 53% rename from package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch rename to package/kernel/mac80211/patches/rt2x00/602-rt2x00-introduce-rt2x00eeprom.patch index f90e109a8..ab0fa3670 100644 --- a/package/kernel/mac80211/patches/rt2x00/602-01-wifi-rt2x00-Add-support-for-loading-EEPROM-from-user.patch +++ b/package/kernel/mac80211/patches/rt2x00/602-rt2x00-introduce-rt2x00eeprom.patch @@ -1,27 +1,6 @@ -From 1046fc9e98936991aeb0b0656c84833d96a63c0f Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Sun, 15 Oct 2023 14:22:49 +0200 -Subject: [PATCH 1/5] wifi: rt2x00: Add support for loading EEPROM from - userspace - -Add support for loading EEPROM from userspace. - -Signed-off-by: Christian Marangi ---- - drivers/net/wireless/ralink/rt2x00/Kconfig | 5 ++ - drivers/net/wireless/ralink/rt2x00/Makefile | 1 + - .../net/wireless/ralink/rt2x00/rt2800soc.c | 15 +--- - drivers/net/wireless/ralink/rt2x00/rt2x00.h | 1 + - .../net/wireless/ralink/rt2x00/rt2x00dev.c | 9 +++ - .../net/wireless/ralink/rt2x00/rt2x00eeprom.c | 75 +++++++++++++++++++ - .../net/wireless/ralink/rt2x00/rt2x00soc.c | 1 + - .../net/wireless/ralink/rt2x00/rt2x00soc.h | 9 +++ - 8 files changed, 102 insertions(+), 14 deletions(-) - create mode 100644 drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c - --- a/local-symbols +++ b/local-symbols -@@ -334,6 +334,7 @@ RT2X00_LIB_FIRMWARE= +@@ -347,6 +347,7 @@ RT2X00_LIB_FIRMWARE= RT2X00_LIB_CRYPTO= RT2X00_LIB_LEDS= RT2X00_LIB_DEBUGFS= @@ -67,6 +46,33 @@ Signed-off-by: Christian Marangi obj-$(CPTCFG_RT2X00_LIB) += rt2x00lib.o obj-$(CPTCFG_RT2X00_LIB_MMIO) += rt2x00mmio.o +--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h +@@ -47,6 +47,8 @@ struct rt2800_drv_data { + struct ieee80211_sta *wcid_to_sta[STA_IDS_SIZE]; + }; + ++#include "rt2800.h" ++ + struct rt2800_ops { + u32 (*register_read)(struct rt2x00_dev *rt2x00dev, + const unsigned int offset); +@@ -145,6 +147,15 @@ static inline int rt2800_read_eeprom(str + { + const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv; + ++ if (rt2x00dev->eeprom_file) { ++ memcpy(rt2x00dev->eeprom, rt2x00dev->eeprom_file->data, ++ EEPROM_SIZE); ++ return 0; ++ } ++ ++ if (!rt2800ops->read_eeprom) ++ return -EINVAL; ++ + return rt2800ops->read_eeprom(rt2x00dev); + } + --- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c @@ -90,19 +90,6 @@ static int rt2800soc_set_device_state(st @@ -89,12 +95,11 @@ Signed-off-by: Christian Marangi /* Firmware functions */ static char *rt2800soc_get_firmware_name(struct rt2x00_dev *rt2x00dev) { -@@ -172,7 +159,7 @@ static const struct rt2800_ops rt2800soc +@@ -168,7 +155,6 @@ static const struct rt2800_ops rt2800soc .register_multiread = rt2x00mmio_register_multiread, .register_multiwrite = rt2x00mmio_register_multiwrite, .regbusy_read = rt2x00mmio_regbusy_read, - .read_eeprom = rt2800soc_read_eeprom, -+ .read_eeprom = rt2x00lib_read_eeprom, .hwcrypt_disabled = rt2800soc_hwcrypt_disabled, .drv_write_firmware = rt2800soc_write_firmware, .drv_init_registers = rt2800mmio_init_registers, @@ -108,24 +113,77 @@ Signed-off-by: Christian Marangi /* * Capabilities +@@ -980,6 +981,11 @@ struct rt2x00_dev { + const struct firmware *fw; + + /* ++ * EEPROM image. ++ */ ++ const struct firmware *eeprom_file; ++ ++ /* + * FIFO for storing tx status reports between isr and tasklet. + */ + DECLARE_KFIFO_PTR(txstatus_fifo, u32); +--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c +@@ -1419,6 +1419,10 @@ int rt2x00lib_probe_dev(struct rt2x00_de + INIT_DELAYED_WORK(&rt2x00dev->autowakeup_work, rt2x00lib_autowakeup); + INIT_WORK(&rt2x00dev->sleep_work, rt2x00lib_sleep); + ++ retval = rt2x00lib_load_eeprom_file(rt2x00dev); ++ if (retval) ++ goto exit; ++ + /* + * Let the driver probe the device to detect the capabilities. + */ +@@ -1559,6 +1563,11 @@ void rt2x00lib_remove_dev(struct rt2x00_ + * Free the driver data. + */ + kfree(rt2x00dev->drv_data); ++ ++ /* ++ * Free EEPROM image. ++ */ ++ rt2x00lib_free_eeprom_file(rt2x00dev); + } + EXPORT_SYMBOL_GPL(rt2x00lib_remove_dev); + --- /dev/null +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* Copyright (C) 2004 - 2009 Ivo van Doorn -+ * Copyright (C) 2004 - 2009 Gertjan van Wingerde -+ * +@@ -0,0 +1,106 @@ ++/* ++ Copyright (C) 2004 - 2009 Ivo van Doorn ++ Copyright (C) 2004 - 2009 Gertjan van Wingerde ++ ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the ++ Free Software Foundation, Inc., ++ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + -+/* Module: rt2x00lib -+ * Abstract: rt2x00 eeprom file loading routines. ++/* ++ Module: rt2x00lib ++ Abstract: rt2x00 eeprom file loading routines. + */ + +#include +#include + +#include "rt2x00.h" -+#include "rt2x00soc.h" ++#include "rt2x00lib.h" + +static const char * +rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev) @@ -138,7 +196,7 @@ Signed-off-by: Christian Marangi + return NULL; +} + -+static int rt2x00lib_read_eeprom_file(struct rt2x00_dev *rt2x00dev) ++static int rt2x00lib_request_eeprom_file(struct rt2x00_dev *rt2x00dev) +{ + const struct firmware *ee; + const char *ee_name; @@ -175,7 +233,8 @@ Signed-off-by: Christian Marangi + goto err_release_ee; + } + -+ memcpy(rt2x00dev->eeprom, ee->data, rt2x00dev->ops->eeprom_size); ++ rt2x00dev->eeprom_file = ee; ++ return 0; + +err_release_ee: + release_firmware(ee); @@ -183,11 +242,48 @@ Signed-off-by: Christian Marangi + return retval; +} + -+int rt2x00lib_read_eeprom(struct rt2x00_dev *rt2x00dev) ++int rt2x00lib_load_eeprom_file(struct rt2x00_dev *rt2x00dev) +{ -+ return rt2x00lib_read_eeprom_file(rt2x00dev); ++ int retval; ++ ++ retval = rt2x00lib_request_eeprom_file(rt2x00dev); ++ if (retval) ++ return retval; ++ ++ return 0; +} -+EXPORT_SYMBOL_GPL(rt2x00lib_read_eeprom); ++ ++void rt2x00lib_free_eeprom_file(struct rt2x00_dev *rt2x00dev) ++{ ++ if (rt2x00dev->eeprom_file && rt2x00dev->eeprom_file->size) ++ release_firmware(rt2x00dev->eeprom_file); ++ rt2x00dev->eeprom_file = NULL; ++} +--- a/drivers/net/wireless/ralink/rt2x00/rt2x00lib.h ++++ b/drivers/net/wireless/ralink/rt2x00/rt2x00lib.h +@@ -286,6 +286,22 @@ static inline void rt2x00lib_free_firmwa + #endif /* CPTCFG_RT2X00_LIB_FIRMWARE */ + + /* ++ * EEPROM file handlers. ++ */ ++#ifdef CPTCFG_RT2X00_LIB_EEPROM ++int rt2x00lib_load_eeprom_file(struct rt2x00_dev *rt2x00dev); ++void rt2x00lib_free_eeprom_file(struct rt2x00_dev *rt2x00dev); ++#else ++static inline int rt2x00lib_load_eeprom_file(struct rt2x00_dev *rt2x00dev) ++{ ++ return 0; ++} ++static inline void rt2x00lib_free_eeprom_file(struct rt2x00_dev *rt2x00dev) ++{ ++} ++#endif /* CPTCFG_RT2X00_LIB_EEPROM */ ++ ++/* + * Debugfs handlers. + */ + #ifdef CPTCFG_RT2X00_LIB_DEBUGFS --- a/drivers/net/wireless/ralink/rt2x00/rt2x00soc.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00soc.c @@ -86,6 +86,7 @@ int rt2x00soc_probe(struct platform_devi @@ -198,19 +294,3 @@ Signed-off-by: Christian Marangi rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC); retval = rt2x00soc_alloc_reg(rt2x00dev); ---- a/drivers/net/wireless/ralink/rt2x00/rt2x00soc.h -+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00soc.h -@@ -26,4 +26,13 @@ int rt2x00soc_resume(struct platform_dev - #define rt2x00soc_resume NULL - #endif /* CONFIG_PM */ - -+/* -+ * EEPROM file handlers. -+ */ -+#ifdef CPTCFG_RT2X00_LIB_EEPROM -+int rt2x00lib_read_eeprom(struct rt2x00_dev *rt2x00dev); -+#else -+#define rt2x00lib_read_eeprom NULL -+#endif /* CPTCFG_RT2X00_LIB_EEPROM */ -+ - #endif /* RT2X00SOC_H */ diff --git a/package/kernel/mac80211/patches/rt2x00/603-rt2x00-of_load_eeprom_filename.patch b/package/kernel/mac80211/patches/rt2x00/603-rt2x00-of_load_eeprom_filename.patch new file mode 100644 index 000000000..431e09023 --- /dev/null +++ b/package/kernel/mac80211/patches/rt2x00/603-rt2x00-of_load_eeprom_filename.patch @@ -0,0 +1,31 @@ +--- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c +@@ -26,6 +26,7 @@ + + #include + #include ++#include + + #include "rt2x00.h" + #include "rt2x00lib.h" +@@ -34,10 +35,20 @@ static const char * + rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev) + { + struct rt2x00_platform_data *pdata = rt2x00dev->dev->platform_data; ++#ifdef CONFIG_OF ++ struct device_node *np; ++ const char *eep; ++#endif + + if (pdata && pdata->eeprom_file_name) + return pdata->eeprom_file_name; + ++#ifdef CONFIG_OF ++ np = rt2x00dev->dev->of_node; ++ if (np && of_property_read_string(np, "ralink,eeprom", &eep) == 0) ++ return eep; ++#endif ++ + return NULL; + } + diff --git a/package/kernel/mac80211/patches/rt2x00/602-03-wifi-rt2x00-Add-support-for-loading-EEPROM-from-MTD.patch b/package/kernel/mac80211/patches/rt2x00/604-rt2x00-load-eeprom-on-SoC-from-a-mtd-device-defines-.patch similarity index 63% rename from package/kernel/mac80211/patches/rt2x00/602-03-wifi-rt2x00-Add-support-for-loading-EEPROM-from-MTD.patch rename to package/kernel/mac80211/patches/rt2x00/604-rt2x00-load-eeprom-on-SoC-from-a-mtd-device-defines-.patch index fab4bf39c..7338eb15b 100644 --- a/package/kernel/mac80211/patches/rt2x00/602-03-wifi-rt2x00-Add-support-for-loading-EEPROM-from-MTD.patch +++ b/package/kernel/mac80211/patches/rt2x00/604-rt2x00-load-eeprom-on-SoC-from-a-mtd-device-defines-.patch @@ -1,16 +1,14 @@ -From 71261ca81b491a4c3b08690347c12e96a75ad0d0 Mon Sep 17 00:00:00 2001 +From 339fe73f340161a624cc08e738d2244814852c3e Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 17 Mar 2013 00:55:04 +0100 -Subject: [PATCH 3/5] wifi: rt2x00: Add support for loading EEPROM from MTD - -Add support for loading EEPROM from MTD. +Subject: [PATCH] rt2x00: load eeprom on SoC from a mtd device defines inside + OF Signed-off-by: John Crispin -Signed-off-by: Christian Marangi --- - drivers/net/wireless/ralink/rt2x00/Kconfig | 1 + - .../net/wireless/ralink/rt2x00/rt2x00eeprom.c | 66 +++++++++++++++++++ - 2 files changed, 67 insertions(+) + drivers/net/wireless/ralink/rt2x00/Kconfig | 1 + + drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c | 65 +++++++++++++++++++++++ + 2 files changed, 66 insertions(+) --- a/drivers/net/wireless/ralink/rt2x00/Kconfig +++ b/drivers/net/wireless/ralink/rt2x00/Kconfig @@ -24,7 +22,7 @@ Signed-off-by: Christian Marangi Supported chips: RT2880, RT3050, RT3052, RT3350, RT3352. --- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c -@@ -10,11 +10,69 @@ +@@ -26,11 +26,76 @@ #include #include @@ -35,20 +33,21 @@ Signed-off-by: Christian Marangi #include #include "rt2x00.h" - #include "rt2x00soc.h" + #include "rt2x00lib.h" +#if IS_ENABLED(CONFIG_MTD) +static int rt2800lib_read_eeprom_mtd(struct rt2x00_dev *rt2x00dev) +{ + int ret = -EINVAL; +#ifdef CONFIG_OF ++ static struct firmware mtd_fw; + struct device_node *np = rt2x00dev->dev->of_node, *mtd_np = NULL; -+ int size, offset = 0; ++ size_t retlen, len = rt2x00dev->ops->eeprom_size; ++ int i, size, offset = 0; + struct mtd_info *mtd; + const char *part; + const __be32 *list; + phandle phandle; -+ size_t retlen; + + list = of_get_property(np, "ralink,mtd-eeprom", &size); + if (!list) @@ -75,15 +74,21 @@ Signed-off-by: Christian Marangi + if (size > sizeof(*list)) + offset = be32_to_cpup(list); + -+ ret = mtd_read(mtd, offset, rt2x00dev->ops->eeprom_size, -+ &retlen, (u_char *)rt2x00dev->eeprom); ++ ret = mtd_read(mtd, offset, len, &retlen, (u_char *) rt2x00dev->eeprom); + put_mtd_device(mtd); + -+ if (retlen != rt2x00dev->ops->eeprom_size || ret) { ++ if ((retlen != rt2x00dev->ops->eeprom_size) || ret) { + dev_err(rt2x00dev->dev, "failed to load eeprom from device \"%s\"\n", part); + return ret; + } + ++ if (of_find_property(np, "ralink,mtd-eeprom-swap", NULL)) ++ for (i = 0; i < len/sizeof(u16); i++) ++ rt2x00dev->eeprom[i] = swab16(rt2x00dev->eeprom[i]); ++ ++ rt2x00dev->eeprom_file = &mtd_fw; ++ mtd_fw.data = (const u8 *) rt2x00dev->eeprom; ++ + dev_info(rt2x00dev->dev, "loaded eeprom from mtd device \"%s\"\n", part); +#endif + @@ -94,18 +99,15 @@ Signed-off-by: Christian Marangi static const char * rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev) { -@@ -83,6 +141,14 @@ err_exit: +@@ -58,6 +123,11 @@ static int rt2x00lib_request_eeprom_file + const char *ee_name; + int retval; - int rt2x00lib_read_eeprom(struct rt2x00_dev *rt2x00dev) - { -+ int ret; -+ +#if IS_ENABLED(CONFIG_MTD) -+ ret = rt2800lib_read_eeprom_mtd(rt2x00dev); -+ if (!ret) ++ if (!rt2800lib_read_eeprom_mtd(rt2x00dev)) + return 0; +#endif + - return rt2x00lib_read_eeprom_file(rt2x00dev); - } - EXPORT_SYMBOL_GPL(rt2x00lib_read_eeprom); + ee_name = rt2x00lib_get_eeprom_file_name(rt2x00dev); + if (!ee_name && test_bit(REQUIRE_EEPROM_FILE, &rt2x00dev->cap_flags)) { + rt2x00_err(rt2x00dev, "Required EEPROM name is missing."); diff --git a/package/kernel/mac80211/patches/rt2x00/606-rt2x00-allow_disabling_bands_through_platform_data.patch b/package/kernel/mac80211/patches/rt2x00/606-rt2x00-allow_disabling_bands_through_platform_data.patch index ab09a6829..ffee2189d 100644 --- a/package/kernel/mac80211/patches/rt2x00/606-rt2x00-allow_disabling_bands_through_platform_data.patch +++ b/package/kernel/mac80211/patches/rt2x00/606-rt2x00-allow_disabling_bands_through_platform_data.patch @@ -12,7 +12,7 @@ #endif /* _RT2X00_PLATFORM_H */ --- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c -@@ -1008,6 +1008,22 @@ static int rt2x00lib_probe_hw_modes(stru +@@ -1007,6 +1007,22 @@ static int rt2x00lib_probe_hw_modes(stru unsigned int num_rates; unsigned int i; diff --git a/package/kernel/mac80211/patches/rt2x00/607-rt2x00-add_platform_data_mac_addr.patch b/package/kernel/mac80211/patches/rt2x00/607-rt2x00-add_platform_data_mac_addr.patch index 79f99ffdf..37553bb80 100644 --- a/package/kernel/mac80211/patches/rt2x00/607-rt2x00-add_platform_data_mac_addr.patch +++ b/package/kernel/mac80211/patches/rt2x00/607-rt2x00-add_platform_data_mac_addr.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c -@@ -990,6 +990,12 @@ static void rt2x00lib_rate(struct ieee80 +@@ -989,6 +989,12 @@ static void rt2x00lib_rate(struct ieee80 void rt2x00lib_set_mac_address(struct rt2x00_dev *rt2x00dev, u8 *eeprom_mac_addr) { diff --git a/package/kernel/mac80211/patches/rt2x00/608-rt2x00-allow_disabling_bands_through_dts.patch b/package/kernel/mac80211/patches/rt2x00/608-rt2x00-allow_disabling_bands_through_dts.patch index 31f2f0261..6211809c0 100644 --- a/package/kernel/mac80211/patches/rt2x00/608-rt2x00-allow_disabling_bands_through_dts.patch +++ b/package/kernel/mac80211/patches/rt2x00/608-rt2x00-allow_disabling_bands_through_dts.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c -@@ -1013,6 +1013,16 @@ static int rt2x00lib_probe_hw_modes(stru +@@ -1012,6 +1012,16 @@ static int rt2x00lib_probe_hw_modes(stru struct ieee80211_rate *rates; unsigned int num_rates; unsigned int i; diff --git a/package/kernel/mac80211/patches/rt2x00/609-rt2x00-make-wmac-loadable-via-OF-on-rt288x-305x-SoC.patch b/package/kernel/mac80211/patches/rt2x00/609-rt2x00-make-wmac-loadable-via-OF-on-rt288x-305x-SoC.patch index de2cf2dca..8964f8bf1 100644 --- a/package/kernel/mac80211/patches/rt2x00/609-rt2x00-make-wmac-loadable-via-OF-on-rt288x-305x-SoC.patch +++ b/package/kernel/mac80211/patches/rt2x00/609-rt2x00-make-wmac-loadable-via-OF-on-rt288x-305x-SoC.patch @@ -13,7 +13,7 @@ Signed-off-by: John Crispin --- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c -@@ -230,10 +230,17 @@ static int rt2800soc_probe(struct platfo +@@ -225,10 +225,17 @@ static int rt2800soc_probe(struct platfo return rt2x00soc_probe(pdev, &rt2800soc_ops); } diff --git a/package/kernel/mac80211/patches/rt2x00/610-rt2x00-change-led-polarity-from-OF.patch b/package/kernel/mac80211/patches/rt2x00/610-rt2x00-change-led-polarity-from-OF.patch index 4a819039d..acc8a8edb 100644 --- a/package/kernel/mac80211/patches/rt2x00/610-rt2x00-change-led-polarity-from-OF.patch +++ b/package/kernel/mac80211/patches/rt2x00/610-rt2x00-change-led-polarity-from-OF.patch @@ -8,7 +8,7 @@ #include "rt2x00.h" #include "rt2800lib.h" -@@ -11282,6 +11283,17 @@ static int rt2800_init_eeprom(struct rt2 +@@ -11131,6 +11132,17 @@ static int rt2800_init_eeprom(struct rt2 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); diff --git a/package/kernel/mac80211/patches/rt2x00/611-rt2x00-add-AP+STA-support.patch b/package/kernel/mac80211/patches/rt2x00/611-rt2x00-add-AP+STA-support.patch index 9564f02ed..5ef5fc8de 100644 --- a/package/kernel/mac80211/patches/rt2x00/611-rt2x00-add-AP+STA-support.patch +++ b/package/kernel/mac80211/patches/rt2x00/611-rt2x00-add-AP+STA-support.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c -@@ -1362,7 +1362,7 @@ static inline void rt2x00lib_set_if_comb +@@ -1358,7 +1358,7 @@ static inline void rt2x00lib_set_if_comb */ if_limit = &rt2x00dev->if_limits_ap; if_limit->max = rt2x00dev->ops->max_ap_intf; diff --git a/package/kernel/mac80211/patches/rt2x00/994-rt2x00-import-support-for-external-LNA-on-MT7620.patch b/package/kernel/mac80211/patches/rt2x00/994-rt2x00-import-support-for-external-LNA-on-MT7620.patch index 5b950539b..deaa03be6 100644 --- a/package/kernel/mac80211/patches/rt2x00/994-rt2x00-import-support-for-external-LNA-on-MT7620.patch +++ b/package/kernel/mac80211/patches/rt2x00/994-rt2x00-import-support-for-external-LNA-on-MT7620.patch @@ -27,7 +27,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c -@@ -305,6 +305,24 @@ static void rt2800_rf_write(struct rt2x0 +@@ -304,6 +304,24 @@ static void rt2800_rf_write(struct rt2x0 mutex_unlock(&rt2x00dev->csr_mutex); } @@ -52,27 +52,67 @@ Signed-off-by: Daniel Golle static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { [EEPROM_CHIP_ID] = 0x0000, [EEPROM_VERSION] = 0x0001, -@@ -10404,8 +10422,10 @@ static void rt2800_calibration_rt6352(st - u32 reg; +@@ -4469,6 +4487,29 @@ static void rt2800_config_channel(struct + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, + 0x6C6C6B6C); + } ++ ++ if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); ++ reg |= 0x00000101; ++ rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); ++ ++ reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); ++ reg |= 0x00000101; ++ rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); ++ ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42); ++ rt2800_bbp_write(rt2x00dev, 75, 0x68); ++ rt2800_bbp_write(rt2x00dev, 76, 0x4C); ++ rt2800_bbp_write(rt2x00dev, 79, 0x1C); ++ rt2800_bbp_write(rt2x00dev, 80, 0x0C); ++ rt2800_bbp_write(rt2x00dev, 82, 0xB6); ++ /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in ++ * config channel function in dependence of channel and ++ * HT20/HT40 so don't touch it ++ */ ++ } + } - if (rt2x00_has_cap_external_pa(rt2x00dev) || -- rt2x00_has_cap_external_lna_bg(rt2x00dev)) -+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) { -+ rt6352_enable_pa_pin(rt2x00dev, 0); - rt2800_restore_rf_bbp_rt6352(rt2x00dev); -+ } + bbp = rt2800_bbp_read(rt2x00dev, 4); +@@ -10583,6 +10624,7 @@ static void rt2800_init_rfcsr_6352(struc + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); ++ rt6352_enable_pa_pin(rt2x00dev, 0); rt2800_r_calibration(rt2x00dev); rt2800_rf_self_txdc_cal(rt2x00dev); -@@ -10423,6 +10443,8 @@ static void rt2800_calibration_rt6352(st - !rt2x00_has_cap_external_lna_bg(rt2x00dev)) - return; - + rt2800_rxdcoc_calibration(rt2x00dev); +@@ -10590,6 +10632,22 @@ static void rt2800_init_rfcsr_6352(struc + rt2800_bw_filter_calibration(rt2x00dev, false); + rt2800_loft_iq_calibration(rt2x00dev); + rt2800_rxiq_calibration(rt2x00dev); + rt6352_enable_pa_pin(rt2x00dev, 1); + - if (rt2x00_has_cap_external_pa(rt2x00dev)) { - reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); - reg |= 0x00000101; ++ if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20); ++ rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42); ++ rt2800_bbp_write(rt2x00dev, 75, 0x68); ++ rt2800_bbp_write(rt2x00dev, 76, 0x4C); ++ rt2800_bbp_write(rt2x00dev, 79, 0x1C); ++ rt2800_bbp_write(rt2x00dev, 80, 0x0C); ++ rt2800_bbp_write(rt2x00dev, 82, 0xB6); ++ /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in config ++ * channel function in dependence of channel and HT20/HT40, ++ * so don't touch them here. ++ */ ++ } + } + + static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h @@ -28,6 +28,7 @@ @@ -83,7 +123,7 @@ Signed-off-by: Daniel Golle #include #include -@@ -1027,6 +1028,11 @@ struct rt2x00_dev { +@@ -1029,6 +1030,11 @@ struct rt2x00_dev { /* Clock for System On Chip devices. */ struct clk *clk; diff --git a/package/kernel/mac80211/patches/rt2x00/995-rt2x00-mt7620-introduce-accessors-for-CHIP_VER-register.patch b/package/kernel/mac80211/patches/rt2x00/995-rt2x00-mt7620-introduce-accessors-for-CHIP_VER-register.patch index b3828052e..97a56de2b 100644 --- a/package/kernel/mac80211/patches/rt2x00/995-rt2x00-mt7620-introduce-accessors-for-CHIP_VER-register.patch +++ b/package/kernel/mac80211/patches/rt2x00/995-rt2x00-mt7620-introduce-accessors-for-CHIP_VER-register.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h -@@ -76,6 +76,9 @@ struct rt2800_ops { +@@ -78,6 +78,9 @@ struct rt2800_ops { int (*drv_init_registers)(struct rt2x00_dev *rt2x00dev); __le32 *(*drv_get_txwi)(struct queue_entry *entry); unsigned int (*drv_get_dma_done)(struct data_queue *queue); @@ -10,7 +10,7 @@ }; static inline u32 rt2800_register_read(struct rt2x00_dev *rt2x00dev, -@@ -184,6 +187,27 @@ static inline unsigned int rt2800_drv_ge +@@ -195,6 +198,27 @@ static inline unsigned int rt2800_drv_ge return rt2800ops->drv_get_dma_done(queue); } @@ -49,9 +49,9 @@ +static int rt2800pci_get_chipeco(void) { return 0; } + static const struct ieee80211_ops rt2800pci_mac80211_ops = { - .add_chanctx = ieee80211_emulate_add_chanctx, - .remove_chanctx = ieee80211_emulate_remove_chanctx, -@@ -333,6 +337,9 @@ static const struct rt2800_ops rt2800pci + .tx = rt2x00mac_tx, + .wake_tx_queue = ieee80211_handle_wake_tx_queue, +@@ -329,6 +333,9 @@ static const struct rt2800_ops rt2800pci .drv_init_registers = rt2800mmio_init_registers, .drv_get_txwi = rt2800mmio_get_txwi, .drv_get_dma_done = rt2800mmio_get_dma_done, @@ -102,9 +102,9 @@ +#endif + static const struct ieee80211_ops rt2800soc_mac80211_ops = { - .add_chanctx = ieee80211_emulate_add_chanctx, - .remove_chanctx = ieee80211_emulate_remove_chanctx, -@@ -165,6 +192,9 @@ static const struct rt2800_ops rt2800soc + .tx = rt2x00mac_tx, + .wake_tx_queue = ieee80211_handle_wake_tx_queue, +@@ -160,6 +187,9 @@ static const struct rt2800_ops rt2800soc .drv_init_registers = rt2800mmio_init_registers, .drv_get_txwi = rt2800mmio_get_txwi, .drv_get_dma_done = rt2800mmio_get_dma_done, @@ -125,9 +125,9 @@ +static int rt2800usb_get_chipeco(void) { return 0; } + static const struct ieee80211_ops rt2800usb_mac80211_ops = { - .add_chanctx = ieee80211_emulate_add_chanctx, - .remove_chanctx = ieee80211_emulate_remove_chanctx, -@@ -676,6 +680,9 @@ static const struct rt2800_ops rt2800usb + .tx = rt2x00mac_tx, + .wake_tx_queue = ieee80211_handle_wake_tx_queue, +@@ -672,6 +676,9 @@ static const struct rt2800_ops rt2800usb .drv_init_registers = rt2800usb_init_registers, .drv_get_txwi = rt2800usb_get_txwi, .drv_get_dma_done = rt2800usb_get_dma_done, diff --git a/package/kernel/mac80211/patches/rt2x00/996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch b/package/kernel/mac80211/patches/rt2x00/996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch index 4c07a1059..dab6e05ff 100644 --- a/package/kernel/mac80211/patches/rt2x00/996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch +++ b/package/kernel/mac80211/patches/rt2x00/996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h -@@ -1056,6 +1056,11 @@ +@@ -1044,6 +1044,11 @@ #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010) #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020) @@ -14,7 +14,7 @@ */ --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c -@@ -3836,14 +3836,16 @@ static void rt2800_config_channel_rf7620 +@@ -3778,14 +3778,16 @@ static void rt2800_config_channel_rf7620 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); @@ -39,7 +39,7 @@ rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, -@@ -3877,18 +3879,23 @@ static void rt2800_config_channel_rf7620 +@@ -3819,18 +3821,23 @@ static void rt2800_config_channel_rf7620 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); } @@ -73,7 +73,7 @@ if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { if (conf_is_ht40(conf)) { -@@ -4002,25 +4009,29 @@ static void rt2800_config_alc_rt6352(str +@@ -3929,25 +3936,29 @@ static void rt2800_config_alc(struct rt2 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n"); @@ -121,17 +121,7 @@ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); rt2800_vco_calibration(rt2x00dev); -@@ -4513,7 +4524,8 @@ static void rt2800_config_channel(struct - if (rt2x00_rt(rt2x00dev, RT6352)) { - /* BBP for GLRT BW */ - bbp = conf_is_ht40(conf) ? -- 0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ? -+ 0x10 : !rt2x00_has_cap_external_lna_bg(rt2x00dev) ? -+ 0x1a : rt2800_hw_get_chippkg(rt2x00dev) == 1 ? - 0x15 : 0x1a; - rt2800_bbp_glrt_write(rt2x00dev, 141, bbp); - -@@ -6017,18 +6029,33 @@ static int rt2800_init_registers(struct +@@ -6011,18 +6022,33 @@ static int rt2800_init_registers(struct } else if (rt2x00_rt(rt2x00dev, RT5350)) { rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); } else if (rt2x00_rt(rt2x00dev, RT6352)) { @@ -177,7 +167,7 @@ reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); -@@ -7141,14 +7168,16 @@ static void rt2800_init_bbp_6352(struct +@@ -7127,14 +7153,16 @@ static void rt2800_init_bbp_6352(struct rt2800_bbp_write(rt2x00dev, 188, 0x00); rt2800_bbp_write(rt2x00dev, 189, 0x00); @@ -202,27 +192,7 @@ /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); -@@ -10378,6 +10407,9 @@ static void rt2800_restore_rf_bbp_rt6352 - rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0); - } - -+ if (rt2800_hw_get_chippkg(rt2x00dev) != 1) -+ return; -+ - if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); - rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); -@@ -10455,6 +10487,9 @@ static void rt2800_calibration_rt6352(st - rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); - } - -+ if (rt2800_hw_get_chippkg(rt2x00dev) != 1) -+ return; -+ - if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66); - rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20); -@@ -10545,31 +10580,36 @@ static void rt2800_init_rfcsr_6352(struc +@@ -10408,31 +10436,36 @@ static void rt2800_init_rfcsr_6352(struc rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); rt2800_rfcsr_write(rt2x00dev, 43, 0x00); @@ -284,7 +254,7 @@ /* Initialize RF channel register to default value */ rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); -@@ -10635,63 +10675,71 @@ static void rt2800_init_rfcsr_6352(struc +@@ -10498,63 +10531,71 @@ static void rt2800_init_rfcsr_6352(struc rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); @@ -318,6 +288,33 @@ - rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); - rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); - rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); +- +- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); +- +- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); +- +- /* Initialize RF channel register for DRQFN */ +- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); +- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); + if (rt2800_hw_get_chipver(rt2x00dev) > 1) { + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); @@ -350,16 +347,7 @@ + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); + } - -- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); ++ + if (rt2800_hw_get_chipver(rt2x00dev) > 1 && + rt2800_hw_get_chipeco(rt2x00dev) >= 2) { + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); @@ -379,23 +367,7 @@ + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); + } - -- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); -- -- /* Initialize RF channel register for DRQFN */ -- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); -- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); ++ + if (rt2800_hw_get_chippkg(rt2x00dev) == 0 && + rt2800_hw_get_chipver(rt2x00dev) == 1) { + /* Initialize RF channel register for DRQFN */ @@ -411,7 +383,7 @@ /* Initialize RF DC calibration register to default value */ rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); -@@ -10754,12 +10802,17 @@ static void rt2800_init_rfcsr_6352(struc +@@ -10617,12 +10658,17 @@ static void rt2800_init_rfcsr_6352(struc rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); @@ -432,5 +404,5 @@ + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); + } - /* Do calibration and init PA/LNA */ - rt2800_calibration_rt6352(rt2x00dev); + rt6352_enable_pa_pin(rt2x00dev, 0); + rt2800_r_calibration(rt2x00dev); diff --git a/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch b/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch index c71f1f2ff..4d4a2a8f5 100644 --- a/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch +++ b/package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch @@ -9,16 +9,11 @@ Used for AP+STA support in OpenWrt - preserve AP mode keys across STA reconnect --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c -@@ -1647,12 +1647,6 @@ static int ieee80211_stop_ap(struct wiph +@@ -1519,7 +1519,6 @@ static int ieee80211_stop_ap(struct wiph + link_conf->bssid_indicator = 0; - __sta_info_flush(sdata, true, link_id); + __sta_info_flush(sdata, true); +- ieee80211_free_keys(sdata, true); -- ieee80211_remove_link_keys(link, &keys); -- if (!list_empty(&keys)) { -- synchronize_net(); -- ieee80211_free_key_list(local, &keys); -- } -- link_conf->enable_beacon = false; sdata->beacon_rate_set = false; - sdata->vif.cfg.ssid_len = 0; diff --git a/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch b/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch deleted file mode 100644 index d4341a135..000000000 --- a/package/kernel/mac80211/patches/subsys/130-disable_auto_vif.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/net/mac80211/main.c -+++ b/net/mac80211/main.c -@@ -1564,24 +1564,6 @@ int ieee80211_register_hw(struct ieee802 - - ieee80211_check_wbrf_support(local); - -- rtnl_lock(); -- wiphy_lock(hw->wiphy); -- -- /* add one default STA interface if supported */ -- if (local->hw.wiphy->interface_modes & BIT(NL80211_IFTYPE_STATION) && -- !ieee80211_hw_check(hw, NO_AUTO_VIF)) { -- struct vif_params params = {0}; -- -- result = ieee80211_if_add(local, "wlan%d", NET_NAME_ENUM, NULL, -- NL80211_IFTYPE_STATION, ¶ms); -- if (result) -- wiphy_warn(local->hw.wiphy, -- "Failed to add default virtual iface\n"); -- } -- -- wiphy_unlock(hw->wiphy); -- rtnl_unlock(); -- - #ifdef CONFIG_INET - local->ifa_notifier.notifier_call = ieee80211_ifa_changed; - result = register_inetaddr_notifier(&local->ifa_notifier); diff --git a/package/kernel/mac80211/patches/subsys/210-ap_scan.patch b/package/kernel/mac80211/patches/subsys/210-ap_scan.patch index a1f96cb3a..10b842d9a 100644 --- a/package/kernel/mac80211/patches/subsys/210-ap_scan.patch +++ b/package/kernel/mac80211/patches/subsys/210-ap_scan.patch @@ -8,7 +8,7 @@ Subject: [PATCH] mac80211: allow scans in access point mode (for site survey) --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c -@@ -2844,6 +2844,8 @@ static int ieee80211_scan(struct wiphy * +@@ -2727,6 +2727,8 @@ static int ieee80211_scan(struct wiphy * */ fallthrough; case NL80211_IFTYPE_AP: diff --git a/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch b/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch index d576661bd..63b217747 100644 --- a/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch +++ b/package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch @@ -28,15 +28,11 @@ Signed-off-by: Johannes Berg --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c -@@ -565,6 +565,11 @@ __sta_info_alloc(struct ieee80211_sub_if - spin_lock_init(&sta->ps_lock); +@@ -554,6 +554,7 @@ __sta_info_alloc(struct ieee80211_sub_if INIT_WORK(&sta->drv_deliver_wk, sta_deliver_ps_frames); - wiphy_work_init(&sta->ampdu_mlme.work, ieee80211_ba_session_work); -+#if LINUX_VERSION_IS_LESS(6,2,0) + INIT_WORK(&sta->ampdu_mlme.work, ieee80211_ba_session_work); + mutex_init(&sta->ampdu_mlme.mtx); + sta->ampdu_mlme.dialog_token_allocator = prandom_u32_max(U8_MAX); -+#else -+ sta->ampdu_mlme.dialog_token_allocator = get_random_u32_below(U8_MAX); -+#endif #ifdef CPTCFG_MAC80211_MESH if (ieee80211_vif_is_mesh(&sdata->vif)) { sta->mesh = kzalloc(sizeof(*sta->mesh), gfp); diff --git a/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch b/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch index 71ce340d3..0ac972955 100644 --- a/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch +++ b/package/kernel/mac80211/patches/subsys/305-mac80211-increase-quantum-for-airtime-scheduler.patch @@ -12,9 +12,9 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h -@@ -101,6 +101,8 @@ ieee80211_sta_keep_active(struct sta_inf - return time_before_eq(jiffies, sta->airtime[ac].last_active + HZ / 10); - } +@@ -90,6 +90,8 @@ extern const u8 ieee80211_ac_to_qos_mask + */ + #define AIRTIME_ACTIVE_DURATION (HZ / 10) +#define AIRTIME_QUANTUM_SHIFT 3 + @@ -23,7 +23,7 @@ Signed-off-by: Felix Fietkau --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c -@@ -4082,7 +4082,7 @@ struct ieee80211_txq *ieee80211_next_txq +@@ -3984,7 +3984,7 @@ struct ieee80211_txq *ieee80211_next_txq if (deficit < 0) sta->airtime[txqi->txq.ac].deficit += @@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau if (deficit < 0 || !aql_check) { list_move_tail(&txqi->schedule_order, -@@ -4225,7 +4225,8 @@ bool ieee80211_txq_may_transmit(struct i +@@ -4127,7 +4127,8 @@ bool ieee80211_txq_may_transmit(struct i } sta = container_of(iter->txq.sta, struct sta_info, sta); if (ieee80211_sta_deficit(sta, ac) < 0) @@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau list_move_tail(&iter->schedule_order, &local->active_txqs[ac]); } -@@ -4233,7 +4234,7 @@ bool ieee80211_txq_may_transmit(struct i +@@ -4135,7 +4136,7 @@ bool ieee80211_txq_may_transmit(struct i if (sta->airtime[ac].deficit >= 0) goto out; diff --git a/package/kernel/mac80211/patches/subsys/306-01-v6.2-wifi-mac80211-add-internal-handler-for-wake_tx_queue.patch b/package/kernel/mac80211/patches/subsys/306-01-v6.2-wifi-mac80211-add-internal-handler-for-wake_tx_queue.patch new file mode 100644 index 000000000..d14ba05e6 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/306-01-v6.2-wifi-mac80211-add-internal-handler-for-wake_tx_queue.patch @@ -0,0 +1,183 @@ +From: Alexander Wetzel +Date: Sun, 9 Oct 2022 18:30:38 +0200 +Subject: [PATCH] wifi: mac80211: add internal handler for wake_tx_queue + +Start to align the TX handling to only use internal TX queues (iTXQs): + +Provide a handler for drivers not having a custom wake_tx_queue +callback and update the documentation. + +Signed-off-by: Alexander Wetzel +Signed-off-by: Johannes Berg +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -89,15 +89,13 @@ + /** + * DOC: mac80211 software tx queueing + * +- * mac80211 provides an optional intermediate queueing implementation designed +- * to allow the driver to keep hardware queues short and provide some fairness +- * between different stations/interfaces. +- * In this model, the driver pulls data frames from the mac80211 queue instead +- * of letting mac80211 push them via drv_tx(). +- * Other frames (e.g. control or management) are still pushed using drv_tx(). ++ * mac80211 uses an intermediate queueing implementation, designed to allow the ++ * driver to keep hardware queues short and to provide some fairness between ++ * different stations/interfaces. + * +- * Drivers indicate that they use this model by implementing the .wake_tx_queue +- * driver operation. ++ * Drivers must provide the .wake_tx_queue driver operation by either ++ * linking it to ieee80211_handle_wake_tx_queue() or implementing a custom ++ * handler. + * + * Intermediate queues (struct ieee80211_txq) are kept per-sta per-tid, with + * another per-sta for non-data/non-mgmt and bufferable management frames, and +@@ -106,9 +104,12 @@ + * The driver is expected to initialize its private per-queue data for stations + * and interfaces in the .add_interface and .sta_add ops. + * +- * The driver can't access the queue directly. To dequeue a frame from a +- * txq, it calls ieee80211_tx_dequeue(). Whenever mac80211 adds a new frame to a +- * queue, it calls the .wake_tx_queue driver op. ++ * The driver can't access the internal TX queues (iTXQs) directly. ++ * Whenever mac80211 adds a new frame to a queue, it calls the .wake_tx_queue ++ * driver op. ++ * Drivers implementing a custom .wake_tx_queue op can get them by calling ++ * ieee80211_tx_dequeue(). Drivers using ieee80211_handle_wake_tx_queue() will ++ * simply get the individual frames pushed via the .tx driver operation. + * + * Drivers can optionally delegate responsibility for scheduling queues to + * mac80211, to take advantage of airtime fairness accounting. In this case, to +@@ -2248,8 +2249,8 @@ struct ieee80211_link_sta { + * For non MLO STA it will point to the deflink data. For MLO STA + * ieee80211_sta_recalc_aggregates() must be called to update it. + * @support_p2p_ps: indicates whether the STA supports P2P PS mechanism or not. +- * @txq: per-TID data TX queues (if driver uses the TXQ abstraction); note that +- * the last entry (%IEEE80211_NUM_TIDS) is used for non-data frames ++ * @txq: per-TID data TX queues; note that the last entry (%IEEE80211_NUM_TIDS) ++ * is used for non-data frames + * @deflink: This holds the default link STA information, for non MLO STA all link + * specific STA information is accessed through @deflink or through + * link[0] which points to address of @deflink. For MLO Link STA +@@ -5687,7 +5688,7 @@ void ieee80211_key_replay(struct ieee802 + * @hw: pointer as obtained from ieee80211_alloc_hw(). + * @queue: queue number (counted from zero). + * +- * Drivers should use this function instead of netif_wake_queue. ++ * Drivers must use this function instead of netif_wake_queue. + */ + void ieee80211_wake_queue(struct ieee80211_hw *hw, int queue); + +@@ -5696,7 +5697,7 @@ void ieee80211_wake_queue(struct ieee802 + * @hw: pointer as obtained from ieee80211_alloc_hw(). + * @queue: queue number (counted from zero). + * +- * Drivers should use this function instead of netif_stop_queue. ++ * Drivers must use this function instead of netif_stop_queue. + */ + void ieee80211_stop_queue(struct ieee80211_hw *hw, int queue); + +@@ -5705,7 +5706,7 @@ void ieee80211_stop_queue(struct ieee802 + * @hw: pointer as obtained from ieee80211_alloc_hw(). + * @queue: queue number (counted from zero). + * +- * Drivers should use this function instead of netif_stop_queue. ++ * Drivers must use this function instead of netif_queue_stopped. + * + * Return: %true if the queue is stopped. %false otherwise. + */ +@@ -5716,7 +5717,7 @@ int ieee80211_queue_stopped(struct ieee8 + * ieee80211_stop_queues - stop all queues + * @hw: pointer as obtained from ieee80211_alloc_hw(). + * +- * Drivers should use this function instead of netif_stop_queue. ++ * Drivers must use this function instead of netif_tx_stop_all_queues. + */ + void ieee80211_stop_queues(struct ieee80211_hw *hw); + +@@ -5724,7 +5725,7 @@ void ieee80211_stop_queues(struct ieee80 + * ieee80211_wake_queues - wake all queues + * @hw: pointer as obtained from ieee80211_alloc_hw(). + * +- * Drivers should use this function instead of netif_wake_queue. ++ * Drivers must use this function instead of netif_tx_wake_all_queues. + */ + void ieee80211_wake_queues(struct ieee80211_hw *hw); + +@@ -6946,6 +6947,18 @@ static inline struct sk_buff *ieee80211_ + } + + /** ++ * ieee80211_handle_wake_tx_queue - mac80211 handler for wake_tx_queue callback ++ * ++ * @hw: pointer as obtained from wake_tx_queue() callback(). ++ * @txq: pointer as obtained from wake_tx_queue() callback(). ++ * ++ * Drivers can use this function for the mandatory mac80211 wake_tx_queue ++ * callback in struct ieee80211_ops. They should not call this function. ++ */ ++void ieee80211_handle_wake_tx_queue(struct ieee80211_hw *hw, ++ struct ieee80211_txq *txq); ++ ++/** + * ieee80211_next_txq - get next tx queue to pull packets from + * + * @hw: pointer as obtained from ieee80211_alloc_hw() +--- a/net/mac80211/util.c ++++ b/net/mac80211/util.c +@@ -288,6 +288,52 @@ __le16 ieee80211_ctstoself_duration(stru + } + EXPORT_SYMBOL(ieee80211_ctstoself_duration); + ++static void wake_tx_push_queue(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ struct ieee80211_txq *queue) ++{ ++ int q = sdata->vif.hw_queue[queue->ac]; ++ struct ieee80211_tx_control control = { ++ .sta = queue->sta, ++ }; ++ struct sk_buff *skb; ++ unsigned long flags; ++ bool q_stopped; ++ ++ while (1) { ++ spin_lock_irqsave(&local->queue_stop_reason_lock, flags); ++ q_stopped = local->queue_stop_reasons[q]; ++ spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); ++ ++ if (q_stopped) ++ break; ++ ++ skb = ieee80211_tx_dequeue(&local->hw, queue); ++ if (!skb) ++ break; ++ ++ drv_tx(local, &control, skb); ++ } ++} ++ ++/* wake_tx_queue handler for driver not implementing a custom one*/ ++void ieee80211_handle_wake_tx_queue(struct ieee80211_hw *hw, ++ struct ieee80211_txq *txq) ++{ ++ struct ieee80211_local *local = hw_to_local(hw); ++ struct ieee80211_sub_if_data *sdata = vif_to_sdata(txq->vif); ++ struct ieee80211_txq *queue; ++ ++ /* Use ieee80211_next_txq() for airtime fairness accounting */ ++ ieee80211_txq_schedule_start(hw, txq->ac); ++ while ((queue = ieee80211_next_txq(hw, txq->ac))) { ++ wake_tx_push_queue(local, sdata, queue); ++ ieee80211_return_txq(hw, queue, false); ++ } ++ ieee80211_txq_schedule_end(hw, txq->ac); ++} ++EXPORT_SYMBOL(ieee80211_handle_wake_tx_queue); ++ + static void __ieee80211_wake_txqs(struct ieee80211_sub_if_data *sdata, int ac) + { + struct ieee80211_local *local = sdata->local; diff --git a/package/kernel/mac80211/patches/subsys/306-02-v6.2-wifi-mac80211-add-wake_tx_queue-callback-to-drivers.patch b/package/kernel/mac80211/patches/subsys/306-02-v6.2-wifi-mac80211-add-wake_tx_queue-callback-to-drivers.patch new file mode 100644 index 000000000..fee038d90 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/306-02-v6.2-wifi-mac80211-add-wake_tx_queue-callback-to-drivers.patch @@ -0,0 +1,396 @@ +From: Alexander Wetzel +Date: Sun, 9 Oct 2022 18:30:39 +0200 +Subject: [PATCH] wifi: mac80211: add wake_tx_queue callback to drivers + +mac80211 is fully switching over to the internal TX queue (iTXQ) +implementation. Update all drivers not yet providing the now mandatory +wake_tx_queue() callback. + +As an side effect the netdev interfaces of all updated drivers will +switch to the noqueue qdisc. + +Signed-off-by: Alexander Wetzel +[add staging drivers] +Signed-off-by: Johannes Berg +--- + +--- a/drivers/net/wireless/admtek/adm8211.c ++++ b/drivers/net/wireless/admtek/adm8211.c +@@ -1760,6 +1760,7 @@ static int adm8211_alloc_rings(struct ie + + static const struct ieee80211_ops adm8211_ops = { + .tx = adm8211_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = adm8211_start, + .stop = adm8211_stop, + .add_interface = adm8211_add_interface, +--- a/drivers/net/wireless/ath/ar5523/ar5523.c ++++ b/drivers/net/wireless/ath/ar5523/ar5523.c +@@ -1361,6 +1361,7 @@ static const struct ieee80211_ops ar5523 + .start = ar5523_start, + .stop = ar5523_stop, + .tx = ar5523_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .set_rts_threshold = ar5523_set_rts_threshold, + .add_interface = ar5523_add_interface, + .remove_interface = ar5523_remove_interface, +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -8587,6 +8587,7 @@ err_fallback: + + static const struct ieee80211_ops ath11k_ops = { + .tx = ath11k_mac_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = ath11k_mac_op_start, + .stop = ath11k_mac_op_stop, + .reconfig_complete = ath11k_mac_op_reconfig_complete, +--- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c ++++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c +@@ -781,6 +781,7 @@ static int ath5k_set_ringparam(struct ie + + const struct ieee80211_ops ath5k_hw_ops = { + .tx = ath5k_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = ath5k_start, + .stop = ath5k_stop, + .add_interface = ath5k_add_interface, +--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c ++++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c +@@ -1870,6 +1870,7 @@ static void ath9k_htc_channel_switch_bea + + struct ieee80211_ops ath9k_htc_ops = { + .tx = ath9k_htc_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = ath9k_htc_start, + .stop = ath9k_htc_stop, + .add_interface = ath9k_htc_add_interface, +--- a/drivers/net/wireless/ath/carl9170/main.c ++++ b/drivers/net/wireless/ath/carl9170/main.c +@@ -1715,6 +1715,7 @@ static const struct ieee80211_ops carl91 + .start = carl9170_op_start, + .stop = carl9170_op_stop, + .tx = carl9170_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .flush = carl9170_op_flush, + .add_interface = carl9170_op_add_interface, + .remove_interface = carl9170_op_remove_interface, +--- a/drivers/net/wireless/ath/wcn36xx/main.c ++++ b/drivers/net/wireless/ath/wcn36xx/main.c +@@ -1362,6 +1362,7 @@ static const struct ieee80211_ops wcn36x + .prepare_multicast = wcn36xx_prepare_multicast, + .configure_filter = wcn36xx_configure_filter, + .tx = wcn36xx_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .set_key = wcn36xx_set_key, + .hw_scan = wcn36xx_hw_scan, + .cancel_hw_scan = wcn36xx_cancel_hw_scan, +--- a/drivers/net/wireless/atmel/at76c50x-usb.c ++++ b/drivers/net/wireless/atmel/at76c50x-usb.c +@@ -2187,6 +2187,7 @@ static int at76_set_key(struct ieee80211 + + static const struct ieee80211_ops at76_ops = { + .tx = at76_mac80211_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .add_interface = at76_add_interface, + .remove_interface = at76_remove_interface, + .config = at76_config, +--- a/drivers/net/wireless/broadcom/b43/main.c ++++ b/drivers/net/wireless/broadcom/b43/main.c +@@ -5171,6 +5171,7 @@ static int b43_op_get_survey(struct ieee + + static const struct ieee80211_ops b43_hw_ops = { + .tx = b43_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .conf_tx = b43_op_conf_tx, + .add_interface = b43_op_add_interface, + .remove_interface = b43_op_remove_interface, +--- a/drivers/net/wireless/broadcom/b43legacy/main.c ++++ b/drivers/net/wireless/broadcom/b43legacy/main.c +@@ -3532,6 +3532,7 @@ static int b43legacy_op_get_survey(struc + + static const struct ieee80211_ops b43legacy_hw_ops = { + .tx = b43legacy_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .conf_tx = b43legacy_op_conf_tx, + .add_interface = b43legacy_op_add_interface, + .remove_interface = b43legacy_op_remove_interface, +--- a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c ++++ b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/mac80211_if.c +@@ -962,6 +962,7 @@ static int brcms_ops_beacon_set_tim(stru + + static const struct ieee80211_ops brcms_ops = { + .tx = brcms_ops_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = brcms_ops_start, + .stop = brcms_ops_stop, + .add_interface = brcms_ops_add_interface, +--- a/drivers/net/wireless/intel/iwlegacy/3945-mac.c ++++ b/drivers/net/wireless/intel/iwlegacy/3945-mac.c +@@ -3439,6 +3439,7 @@ static const struct attribute_group il39 + + static struct ieee80211_ops il3945_mac_ops __ro_after_init = { + .tx = il3945_mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = il3945_mac_start, + .stop = il3945_mac_stop, + .add_interface = il_mac_add_interface, +--- a/drivers/net/wireless/intel/iwlegacy/4965-mac.c ++++ b/drivers/net/wireless/intel/iwlegacy/4965-mac.c +@@ -6308,6 +6308,7 @@ il4965_tx_queue_set_status(struct il_pri + + static const struct ieee80211_ops il4965_mac_ops = { + .tx = il4965_mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = il4965_mac_start, + .stop = il4965_mac_stop, + .add_interface = il_mac_add_interface, +--- a/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c ++++ b/drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c +@@ -1571,6 +1571,7 @@ static void iwlagn_mac_sta_notify(struct + + const struct ieee80211_ops iwlagn_hw_ops = { + .tx = iwlagn_mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = iwlagn_mac_start, + .stop = iwlagn_mac_stop, + #ifdef CONFIG_PM_SLEEP +--- a/drivers/net/wireless/intersil/p54/main.c ++++ b/drivers/net/wireless/intersil/p54/main.c +@@ -705,6 +705,7 @@ static void p54_set_coverage_class(struc + + static const struct ieee80211_ops p54_ops = { + .tx = p54_tx_80211, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = p54_start, + .stop = p54_stop, + .add_interface = p54_add_interface, +--- a/drivers/net/wireless/mac80211_hwsim.c ++++ b/drivers/net/wireless/mac80211_hwsim.c +@@ -3109,6 +3109,7 @@ static int mac80211_hwsim_change_sta_lin + + #define HWSIM_COMMON_OPS \ + .tx = mac80211_hwsim_tx, \ ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, \ + .start = mac80211_hwsim_start, \ + .stop = mac80211_hwsim_stop, \ + .add_interface = mac80211_hwsim_add_interface, \ +--- a/drivers/net/wireless/marvell/libertas_tf/main.c ++++ b/drivers/net/wireless/marvell/libertas_tf/main.c +@@ -474,6 +474,7 @@ static int lbtf_op_get_survey(struct iee + + static const struct ieee80211_ops lbtf_ops = { + .tx = lbtf_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = lbtf_op_start, + .stop = lbtf_op_stop, + .add_interface = lbtf_op_add_interface, +--- a/drivers/net/wireless/marvell/mwl8k.c ++++ b/drivers/net/wireless/marvell/mwl8k.c +@@ -5611,6 +5611,7 @@ static void mwl8k_sw_scan_complete(struc + + static const struct ieee80211_ops mwl8k_ops = { + .tx = mwl8k_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = mwl8k_start, + .stop = mwl8k_stop, + .add_interface = mwl8k_add_interface, +--- a/drivers/net/wireless/mediatek/mt7601u/main.c ++++ b/drivers/net/wireless/mediatek/mt7601u/main.c +@@ -406,6 +406,7 @@ out: + + const struct ieee80211_ops mt7601u_ops = { + .tx = mt7601u_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = mt7601u_start, + .stop = mt7601u_stop, + .add_interface = mt7601u_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt2400pci.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2400pci.c +@@ -1706,6 +1706,7 @@ static int rt2400pci_tx_last_beacon(stru + + static const struct ieee80211_ops rt2400pci_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt2500pci.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2500pci.c +@@ -2004,6 +2004,7 @@ static int rt2500pci_tx_last_beacon(stru + + static const struct ieee80211_ops rt2500pci_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt2500usb.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2500usb.c +@@ -1795,6 +1795,7 @@ static int rt2500usb_probe_hw(struct rt2 + + static const struct ieee80211_ops rt2500usb_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt2800pci.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800pci.c +@@ -288,6 +288,7 @@ static int rt2800pci_read_eeprom(struct + + static const struct ieee80211_ops rt2800pci_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c +@@ -133,6 +133,7 @@ static int rt2800soc_write_firmware(stru + + static const struct ieee80211_ops rt2800soc_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c +@@ -630,6 +630,7 @@ static int rt2800usb_probe_hw(struct rt2 + + static const struct ieee80211_ops rt2800usb_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt61pci.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt61pci.c +@@ -2873,6 +2873,7 @@ static u64 rt61pci_get_tsf(struct ieee80 + + static const struct ieee80211_ops rt61pci_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/ralink/rt2x00/rt73usb.c ++++ b/drivers/net/wireless/ralink/rt2x00/rt73usb.c +@@ -2292,6 +2292,7 @@ static u64 rt73usb_get_tsf(struct ieee80 + + static const struct ieee80211_ops rt73usb_mac80211_ops = { + .tx = rt2x00mac_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rt2x00mac_start, + .stop = rt2x00mac_stop, + .add_interface = rt2x00mac_add_interface, +--- a/drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c ++++ b/drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c +@@ -1608,6 +1608,7 @@ static void rtl8180_configure_filter(str + + static const struct ieee80211_ops rtl8180_ops = { + .tx = rtl8180_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rtl8180_start, + .stop = rtl8180_stop, + .add_interface = rtl8180_add_interface, +--- a/drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c ++++ b/drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c +@@ -1378,6 +1378,7 @@ static int rtl8187_conf_tx(struct ieee80 + + static const struct ieee80211_ops rtl8187_ops = { + .tx = rtl8187_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rtl8187_start, + .stop = rtl8187_stop, + .add_interface = rtl8187_add_interface, +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +@@ -6548,6 +6548,7 @@ static void rtl8xxxu_stop(struct ieee802 + + static const struct ieee80211_ops rtl8xxxu_ops = { + .tx = rtl8xxxu_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .add_interface = rtl8xxxu_add_interface, + .remove_interface = rtl8xxxu_remove_interface, + .config = rtl8xxxu_config, +--- a/drivers/net/wireless/realtek/rtlwifi/core.c ++++ b/drivers/net/wireless/realtek/rtlwifi/core.c +@@ -1912,6 +1912,7 @@ const struct ieee80211_ops rtl_ops = { + .start = rtl_op_start, + .stop = rtl_op_stop, + .tx = rtl_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .add_interface = rtl_op_add_interface, + .remove_interface = rtl_op_remove_interface, + .change_interface = rtl_op_change_interface, +--- a/drivers/net/wireless/realtek/rtw88/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw88/mac80211.c +@@ -896,6 +896,7 @@ static void rtw_ops_sta_rc_update(struct + + const struct ieee80211_ops rtw_ops = { + .tx = rtw_ops_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .wake_tx_queue = rtw_ops_wake_tx_queue, + .start = rtw_ops_start, + .stop = rtw_ops_stop, +--- a/drivers/net/wireless/realtek/rtw89/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -918,6 +918,7 @@ static int rtw89_ops_set_tid_config(stru + + const struct ieee80211_ops rtw89_ops = { + .tx = rtw89_ops_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .wake_tx_queue = rtw89_ops_wake_tx_queue, + .start = rtw89_ops_start, + .stop = rtw89_ops_stop, +--- a/drivers/net/wireless/rsi/rsi_91x_mac80211.c ++++ b/drivers/net/wireless/rsi/rsi_91x_mac80211.c +@@ -1958,6 +1958,7 @@ static int rsi_mac80211_resume(struct ie + + static const struct ieee80211_ops mac80211_ops = { + .tx = rsi_mac80211_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = rsi_mac80211_start, + .stop = rsi_mac80211_stop, + .add_interface = rsi_mac80211_add_interface, +--- a/drivers/net/wireless/st/cw1200/main.c ++++ b/drivers/net/wireless/st/cw1200/main.c +@@ -209,6 +209,7 @@ static const struct ieee80211_ops cw1200 + .remove_interface = cw1200_remove_interface, + .change_interface = cw1200_change_interface, + .tx = cw1200_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .hw_scan = cw1200_hw_scan, + .set_tim = cw1200_set_tim, + .sta_notify = cw1200_sta_notify, +--- a/drivers/net/wireless/ti/wl1251/main.c ++++ b/drivers/net/wireless/ti/wl1251/main.c +@@ -1359,6 +1359,7 @@ static const struct ieee80211_ops wl1251 + .prepare_multicast = wl1251_op_prepare_multicast, + .configure_filter = wl1251_op_configure_filter, + .tx = wl1251_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .set_key = wl1251_op_set_key, + .hw_scan = wl1251_op_hw_scan, + .bss_info_changed = wl1251_op_bss_info_changed, +--- a/drivers/net/wireless/ti/wlcore/main.c ++++ b/drivers/net/wireless/ti/wlcore/main.c +@@ -5942,6 +5942,7 @@ static const struct ieee80211_ops wl1271 + .prepare_multicast = wl1271_op_prepare_multicast, + .configure_filter = wl1271_op_configure_filter, + .tx = wl1271_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .set_key = wlcore_op_set_key, + .hw_scan = wl1271_op_hw_scan, + .cancel_hw_scan = wl1271_op_cancel_hw_scan, +--- a/drivers/net/wireless/zydas/zd1211rw/zd_mac.c ++++ b/drivers/net/wireless/zydas/zd1211rw/zd_mac.c +@@ -1344,6 +1344,7 @@ static u64 zd_op_get_tsf(struct ieee8021 + + static const struct ieee80211_ops zd_ops = { + .tx = zd_op_tx, ++ .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .start = zd_op_start, + .stop = zd_op_stop, + .add_interface = zd_op_add_interface, diff --git a/package/kernel/mac80211/patches/subsys/306-03-v6.2-wifi-mac80211-Drop-support-for-TX-push-path.patch b/package/kernel/mac80211/patches/subsys/306-03-v6.2-wifi-mac80211-Drop-support-for-TX-push-path.patch new file mode 100644 index 000000000..f9f9977ce --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/306-03-v6.2-wifi-mac80211-Drop-support-for-TX-push-path.patch @@ -0,0 +1,683 @@ +From: Alexander Wetzel +Date: Sun, 9 Oct 2022 18:30:40 +0200 +Subject: [PATCH] wifi: mac80211: Drop support for TX push path + +All drivers are now using mac80211 internal queues (iTXQs). +Drop mac80211 internal support for the old push path. + +Signed-off-by: Alexander Wetzel +Signed-off-by: Johannes Berg +--- + +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -4346,9 +4346,6 @@ static int ieee80211_get_txq_stats(struc + struct ieee80211_sub_if_data *sdata; + int ret = 0; + +- if (!local->ops->wake_tx_queue) +- return 1; +- + spin_lock_bh(&local->fq.lock); + rcu_read_lock(); + +--- a/net/mac80211/debugfs.c ++++ b/net/mac80211/debugfs.c +@@ -663,9 +663,7 @@ void debugfs_hw_add(struct ieee80211_loc + DEBUGFS_ADD_MODE(force_tx_status, 0600); + DEBUGFS_ADD_MODE(aql_enable, 0600); + DEBUGFS_ADD(aql_pending); +- +- if (local->ops->wake_tx_queue) +- DEBUGFS_ADD_MODE(aqm, 0600); ++ DEBUGFS_ADD_MODE(aqm, 0600); + + DEBUGFS_ADD_MODE(airtime_flags, 0600); + +--- a/net/mac80211/debugfs_netdev.c ++++ b/net/mac80211/debugfs_netdev.c +@@ -677,8 +677,7 @@ static void add_common_files(struct ieee + DEBUGFS_ADD(rc_rateidx_vht_mcs_mask_5ghz); + DEBUGFS_ADD(hw_queues); + +- if (sdata->local->ops->wake_tx_queue && +- sdata->vif.type != NL80211_IFTYPE_P2P_DEVICE && ++ if (sdata->vif.type != NL80211_IFTYPE_P2P_DEVICE && + sdata->vif.type != NL80211_IFTYPE_NAN) + DEBUGFS_ADD(aqm); + } +--- a/net/mac80211/debugfs_sta.c ++++ b/net/mac80211/debugfs_sta.c +@@ -1057,10 +1057,8 @@ void ieee80211_sta_debugfs_add(struct st + DEBUGFS_ADD_COUNTER(rx_fragments, deflink.rx_stats.fragments); + DEBUGFS_ADD_COUNTER(tx_filtered, deflink.status_stats.filtered); + +- if (local->ops->wake_tx_queue) { +- DEBUGFS_ADD(aqm); +- DEBUGFS_ADD(airtime); +- } ++ DEBUGFS_ADD(aqm); ++ DEBUGFS_ADD(airtime); + + if (wiphy_ext_feature_isset(local->hw.wiphy, + NL80211_EXT_FEATURE_AQL)) +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -2294,7 +2294,6 @@ void ieee80211_wake_queue_by_reason(stru + void ieee80211_stop_queue_by_reason(struct ieee80211_hw *hw, int queue, + enum queue_stop_reason reason, + bool refcounted); +-void ieee80211_propagate_queue_wake(struct ieee80211_local *local, int queue); + void ieee80211_add_pending_skb(struct ieee80211_local *local, + struct sk_buff *skb); + void ieee80211_add_pending_skbs(struct ieee80211_local *local, +--- a/net/mac80211/iface.c ++++ b/net/mac80211/iface.c +@@ -460,12 +460,6 @@ static void ieee80211_do_stop(struct iee + if (cancel_scan) + ieee80211_scan_cancel(local); + +- /* +- * Stop TX on this interface first. +- */ +- if (!local->ops->wake_tx_queue && sdata->dev) +- netif_tx_stop_all_queues(sdata->dev); +- + ieee80211_roc_purge(local, sdata); + + switch (sdata->vif.type) { +@@ -813,13 +807,6 @@ static void ieee80211_uninit(struct net_ + ieee80211_teardown_sdata(IEEE80211_DEV_TO_SUB_IF(dev)); + } + +-static u16 ieee80211_netdev_select_queue(struct net_device *dev, +- struct sk_buff *skb, +- struct net_device *sb_dev) +-{ +- return ieee80211_select_queue(IEEE80211_DEV_TO_SUB_IF(dev), skb); +-} +- + static void + ieee80211_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) + { +@@ -833,7 +820,6 @@ static const struct net_device_ops ieee8 + .ndo_start_xmit = ieee80211_subif_start_xmit, + .ndo_set_rx_mode = ieee80211_set_multicast_list, + .ndo_set_mac_address = ieee80211_change_mac, +- .ndo_select_queue = ieee80211_netdev_select_queue, + .ndo_get_stats64 = ieee80211_get_stats64, + }; + +@@ -941,7 +927,6 @@ static const struct net_device_ops ieee8 + .ndo_start_xmit = ieee80211_subif_start_xmit_8023, + .ndo_set_rx_mode = ieee80211_set_multicast_list, + .ndo_set_mac_address = ieee80211_change_mac, +- .ndo_select_queue = ieee80211_netdev_select_queue, + .ndo_get_stats64 = ieee80211_get_stats64, + .ndo_fill_forward_path = ieee80211_netdev_fill_forward_path, + }; +@@ -1443,35 +1428,6 @@ int ieee80211_do_open(struct wireless_de + + ieee80211_recalc_ps(local); + +- if (sdata->vif.type == NL80211_IFTYPE_MONITOR || +- sdata->vif.type == NL80211_IFTYPE_AP_VLAN || +- local->ops->wake_tx_queue) { +- /* XXX: for AP_VLAN, actually track AP queues */ +- if (dev) +- netif_tx_start_all_queues(dev); +- } else if (dev) { +- unsigned long flags; +- int n_acs = IEEE80211_NUM_ACS; +- int ac; +- +- if (local->hw.queues < IEEE80211_NUM_ACS) +- n_acs = 1; +- +- spin_lock_irqsave(&local->queue_stop_reason_lock, flags); +- if (sdata->vif.cab_queue == IEEE80211_INVAL_HW_QUEUE || +- (local->queue_stop_reasons[sdata->vif.cab_queue] == 0 && +- skb_queue_empty(&local->pending[sdata->vif.cab_queue]))) { +- for (ac = 0; ac < n_acs; ac++) { +- int ac_queue = sdata->vif.hw_queue[ac]; +- +- if (local->queue_stop_reasons[ac_queue] == 0 && +- skb_queue_empty(&local->pending[ac_queue])) +- netif_start_subqueue(dev, ac); +- } +- } +- spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); +- } +- + set_bit(SDATA_STATE_RUNNING, &sdata->state); + + return 0; +@@ -1501,17 +1457,12 @@ static void ieee80211_if_setup(struct ne + { + ether_setup(dev); + dev->priv_flags &= ~IFF_TX_SKB_SHARING; ++ dev->priv_flags |= IFF_NO_QUEUE; + dev->netdev_ops = &ieee80211_dataif_ops; + dev->needs_free_netdev = true; + dev->priv_destructor = ieee80211_if_free; + } + +-static void ieee80211_if_setup_no_queue(struct net_device *dev) +-{ +- ieee80211_if_setup(dev); +- dev->priv_flags |= IFF_NO_QUEUE; +-} +- + static void ieee80211_iface_process_skb(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, + struct sk_buff *skb) +@@ -2096,9 +2047,7 @@ int ieee80211_if_add(struct ieee80211_lo + struct net_device *ndev = NULL; + struct ieee80211_sub_if_data *sdata = NULL; + struct txq_info *txqi; +- void (*if_setup)(struct net_device *dev); + int ret, i; +- int txqs = 1; + + ASSERT_RTNL(); + +@@ -2121,30 +2070,18 @@ int ieee80211_if_add(struct ieee80211_lo + sizeof(void *)); + int txq_size = 0; + +- if (local->ops->wake_tx_queue && +- type != NL80211_IFTYPE_AP_VLAN && ++ if (type != NL80211_IFTYPE_AP_VLAN && + (type != NL80211_IFTYPE_MONITOR || + (params->flags & MONITOR_FLAG_ACTIVE))) + txq_size += sizeof(struct txq_info) + + local->hw.txq_data_size; + +- if (local->ops->wake_tx_queue) { +- if_setup = ieee80211_if_setup_no_queue; +- } else { +- if_setup = ieee80211_if_setup; +- if (local->hw.queues >= IEEE80211_NUM_ACS) +- txqs = IEEE80211_NUM_ACS; +- } +- + ndev = alloc_netdev_mqs(size + txq_size, + name, name_assign_type, +- if_setup, txqs, 1); ++ ieee80211_if_setup, 1, 1); + if (!ndev) + return -ENOMEM; + +- if (!local->ops->wake_tx_queue && local->hw.wiphy->tx_queue_len) +- ndev->tx_queue_len = local->hw.wiphy->tx_queue_len; +- + dev_net_set(ndev, wiphy_net(local->hw.wiphy)); + + ndev->tstats = netdev_alloc_pcpu_stats(struct pcpu_sw_netstats); +--- a/net/mac80211/main.c ++++ b/net/mac80211/main.c +@@ -630,7 +630,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_ + + if (WARN_ON(!ops->tx || !ops->start || !ops->stop || !ops->config || + !ops->add_interface || !ops->remove_interface || +- !ops->configure_filter)) ++ !ops->configure_filter || !ops->wake_tx_queue)) + return NULL; + + if (WARN_ON(ops->sta_state && (ops->sta_add || ops->sta_remove))) +@@ -719,9 +719,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_ + if (!ops->set_key) + wiphy->flags |= WIPHY_FLAG_IBSS_RSN; + +- if (ops->wake_tx_queue) +- wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_TXQS); +- ++ wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_TXQS); + wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_RRM); + + wiphy->bss_priv_size = sizeof(struct ieee80211_bss); +@@ -834,10 +832,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_ + atomic_set(&local->agg_queue_stop[i], 0); + } + tasklet_setup(&local->tx_pending_tasklet, ieee80211_tx_pending); +- +- if (ops->wake_tx_queue) +- tasklet_setup(&local->wake_txqs_tasklet, ieee80211_wake_txqs); +- ++ tasklet_setup(&local->wake_txqs_tasklet, ieee80211_wake_txqs); + tasklet_setup(&local->tasklet, ieee80211_tasklet_handler); + + skb_queue_head_init(&local->skb_queue); +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -1571,9 +1571,6 @@ static void sta_ps_start(struct sta_info + + ieee80211_clear_fast_xmit(sta); + +- if (!sta->sta.txq[0]) +- return; +- + for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) { + struct ieee80211_txq *txq = sta->sta.txq[tid]; + struct txq_info *txqi = to_txq_info(txq); +--- a/net/mac80211/sta_info.c ++++ b/net/mac80211/sta_info.c +@@ -140,17 +140,15 @@ static void __cleanup_single_sta(struct + atomic_dec(&ps->num_sta_ps); + } + +- if (sta->sta.txq[0]) { +- for (i = 0; i < ARRAY_SIZE(sta->sta.txq); i++) { +- struct txq_info *txqi; ++ for (i = 0; i < ARRAY_SIZE(sta->sta.txq); i++) { ++ struct txq_info *txqi; + +- if (!sta->sta.txq[i]) +- continue; ++ if (!sta->sta.txq[i]) ++ continue; + +- txqi = to_txq_info(sta->sta.txq[i]); ++ txqi = to_txq_info(sta->sta.txq[i]); + +- ieee80211_txq_purge(local, txqi); +- } ++ ieee80211_txq_purge(local, txqi); + } + + for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { +@@ -425,8 +423,7 @@ void sta_info_free(struct ieee80211_loca + + sta_dbg(sta->sdata, "Destroyed STA %pM\n", sta->sta.addr); + +- if (sta->sta.txq[0]) +- kfree(to_txq_info(sta->sta.txq[0])); ++ kfree(to_txq_info(sta->sta.txq[0])); + kfree(rcu_dereference_raw(sta->sta.rates)); + #ifdef CPTCFG_MAC80211_MESH + kfree(sta->mesh); +@@ -527,6 +524,8 @@ __sta_info_alloc(struct ieee80211_sub_if + struct ieee80211_local *local = sdata->local; + struct ieee80211_hw *hw = &local->hw; + struct sta_info *sta; ++ void *txq_data; ++ int size; + int i; + + sta = kzalloc(sizeof(*sta) + hw->sta_data_size, gfp); +@@ -597,21 +596,18 @@ __sta_info_alloc(struct ieee80211_sub_if + + sta->last_connected = ktime_get_seconds(); + +- if (local->ops->wake_tx_queue) { +- void *txq_data; +- int size = sizeof(struct txq_info) + +- ALIGN(hw->txq_data_size, sizeof(void *)); ++ size = sizeof(struct txq_info) + ++ ALIGN(hw->txq_data_size, sizeof(void *)); + +- txq_data = kcalloc(ARRAY_SIZE(sta->sta.txq), size, gfp); +- if (!txq_data) +- goto free; ++ txq_data = kcalloc(ARRAY_SIZE(sta->sta.txq), size, gfp); ++ if (!txq_data) ++ goto free; + +- for (i = 0; i < ARRAY_SIZE(sta->sta.txq); i++) { +- struct txq_info *txq = txq_data + i * size; ++ for (i = 0; i < ARRAY_SIZE(sta->sta.txq); i++) { ++ struct txq_info *txq = txq_data + i * size; + +- /* might not do anything for the bufferable MMPDU TXQ */ +- ieee80211_txq_init(sdata, sta, txq, i); +- } ++ /* might not do anything for the (bufferable) MMPDU TXQ */ ++ ieee80211_txq_init(sdata, sta, txq, i); + } + + if (sta_prepare_rate_control(local, sta, gfp)) +@@ -685,8 +681,7 @@ __sta_info_alloc(struct ieee80211_sub_if + return sta; + + free_txq: +- if (sta->sta.txq[0]) +- kfree(to_txq_info(sta->sta.txq[0])); ++ kfree(to_txq_info(sta->sta.txq[0])); + free: + sta_info_free_link(&sta->deflink); + #ifdef CPTCFG_MAC80211_MESH +@@ -1960,9 +1955,6 @@ ieee80211_sta_ps_deliver_response(struct + * TIM recalculation. + */ + +- if (!sta->sta.txq[0]) +- return; +- + for (tid = 0; tid < ARRAY_SIZE(sta->sta.txq); tid++) { + if (!sta->sta.txq[tid] || + !(driver_release_tids & BIT(tid)) || +@@ -2447,7 +2439,7 @@ static void sta_set_tidstats(struct sta_ + tidstats->tx_msdu_failed = sta->deflink.status_stats.msdu_failed[tid]; + } + +- if (local->ops->wake_tx_queue && tid < IEEE80211_NUM_TIDS) { ++ if (tid < IEEE80211_NUM_TIDS) { + spin_lock_bh(&local->fq.lock); + rcu_read_lock(); + +@@ -2775,9 +2767,6 @@ unsigned long ieee80211_sta_last_active( + + static void sta_update_codel_params(struct sta_info *sta, u32 thr) + { +- if (!sta->sdata->local->ops->wake_tx_queue) +- return; +- + if (thr && thr < STA_SLOW_THRESHOLD * sta->local->num_sta) { + sta->cparams.target = MS2TIME(50); + sta->cparams.interval = MS2TIME(300); +--- a/net/mac80211/tdls.c ++++ b/net/mac80211/tdls.c +@@ -1016,7 +1016,6 @@ ieee80211_tdls_prep_mgmt_packet(struct w + skb->priority = 256 + 5; + break; + } +- skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, skb)); + + /* + * Set the WLAN_TDLS_TEARDOWN flag to indicate a teardown in progress. +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -1600,9 +1600,6 @@ int ieee80211_txq_setup_flows(struct iee + bool supp_vht = false; + enum nl80211_band band; + +- if (!local->ops->wake_tx_queue) +- return 0; +- + ret = fq_init(fq, 4096); + if (ret) + return ret; +@@ -1650,9 +1647,6 @@ void ieee80211_txq_teardown_flows(struct + { + struct fq *fq = &local->fq; + +- if (!local->ops->wake_tx_queue) +- return; +- + kfree(local->cvars); + local->cvars = NULL; + +@@ -1669,8 +1663,7 @@ static bool ieee80211_queue_skb(struct i + struct ieee80211_vif *vif; + struct txq_info *txqi; + +- if (!local->ops->wake_tx_queue || +- sdata->vif.type == NL80211_IFTYPE_MONITOR) ++ if (sdata->vif.type == NL80211_IFTYPE_MONITOR) + return false; + + if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) +@@ -4193,12 +4186,7 @@ void __ieee80211_subif_start_xmit(struct + if (IS_ERR(sta)) + sta = NULL; + +- if (local->ops->wake_tx_queue) { +- u16 queue = __ieee80211_select_queue(sdata, sta, skb); +- skb_set_queue_mapping(skb, queue); +- skb_get_hash(skb); +- } +- ++ skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, sta, skb)); + ieee80211_aggr_check(sdata, sta, skb); + + sk_pacing_shift_update(skb->sk, sdata->local->hw.tx_sk_pacing_shift); +@@ -4509,11 +4497,7 @@ static void ieee80211_8023_xmit(struct i + struct tid_ampdu_tx *tid_tx; + u8 tid; + +- if (local->ops->wake_tx_queue) { +- u16 queue = __ieee80211_select_queue(sdata, sta, skb); +- skb_set_queue_mapping(skb, queue); +- skb_get_hash(skb); +- } ++ skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, sta, skb)); + + if (unlikely(test_bit(SCAN_SW_SCANNING, &local->scanning)) && + test_bit(SDATA_STATE_OFFCHANNEL, &sdata->state)) +@@ -4767,9 +4751,6 @@ void ieee80211_tx_pending(struct tasklet + if (!txok) + break; + } +- +- if (skb_queue_empty(&local->pending[i])) +- ieee80211_propagate_queue_wake(local, i); + } + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); + +@@ -5962,10 +5943,9 @@ int ieee80211_tx_control_port(struct wip + } + + if (!IS_ERR(sta)) { +- u16 queue = __ieee80211_select_queue(sdata, sta, skb); ++ u16 queue = ieee80211_select_queue(sdata, sta, skb); + + skb_set_queue_mapping(skb, queue); +- skb_get_hash(skb); + + /* + * for MLO STA, the SA should be the AP MLD address, but +--- a/net/mac80211/util.c ++++ b/net/mac80211/util.c +@@ -444,39 +444,6 @@ void ieee80211_wake_txqs(struct tasklet_ + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); + } + +-void ieee80211_propagate_queue_wake(struct ieee80211_local *local, int queue) +-{ +- struct ieee80211_sub_if_data *sdata; +- int n_acs = IEEE80211_NUM_ACS; +- +- if (local->ops->wake_tx_queue) +- return; +- +- if (local->hw.queues < IEEE80211_NUM_ACS) +- n_acs = 1; +- +- list_for_each_entry_rcu(sdata, &local->interfaces, list) { +- int ac; +- +- if (!sdata->dev) +- continue; +- +- if (sdata->vif.cab_queue != IEEE80211_INVAL_HW_QUEUE && +- local->queue_stop_reasons[sdata->vif.cab_queue] != 0) +- continue; +- +- for (ac = 0; ac < n_acs; ac++) { +- int ac_queue = sdata->vif.hw_queue[ac]; +- +- if (ac_queue == queue || +- (sdata->vif.cab_queue == queue && +- local->queue_stop_reasons[ac_queue] == 0 && +- skb_queue_empty(&local->pending[ac_queue]))) +- netif_wake_subqueue(sdata->dev, ac); +- } +- } +-} +- + static void __ieee80211_wake_queue(struct ieee80211_hw *hw, int queue, + enum queue_stop_reason reason, + bool refcounted, +@@ -507,11 +474,7 @@ static void __ieee80211_wake_queue(struc + /* someone still has this queue stopped */ + return; + +- if (skb_queue_empty(&local->pending[queue])) { +- rcu_read_lock(); +- ieee80211_propagate_queue_wake(local, queue); +- rcu_read_unlock(); +- } else ++ if (!skb_queue_empty(&local->pending[queue])) + tasklet_schedule(&local->tx_pending_tasklet); + + /* +@@ -521,12 +484,10 @@ static void __ieee80211_wake_queue(struc + * release someone's lock, but it is fine because all the callers of + * __ieee80211_wake_queue call it right before releasing the lock. + */ +- if (local->ops->wake_tx_queue) { +- if (reason == IEEE80211_QUEUE_STOP_REASON_DRIVER) +- tasklet_schedule(&local->wake_txqs_tasklet); +- else +- _ieee80211_wake_txqs(local, flags); +- } ++ if (reason == IEEE80211_QUEUE_STOP_REASON_DRIVER) ++ tasklet_schedule(&local->wake_txqs_tasklet); ++ else ++ _ieee80211_wake_txqs(local, flags); + } + + void ieee80211_wake_queue_by_reason(struct ieee80211_hw *hw, int queue, +@@ -554,8 +515,6 @@ static void __ieee80211_stop_queue(struc + bool refcounted) + { + struct ieee80211_local *local = hw_to_local(hw); +- struct ieee80211_sub_if_data *sdata; +- int n_acs = IEEE80211_NUM_ACS; + + trace_stop_queue(local, queue, reason); + +@@ -567,27 +526,7 @@ static void __ieee80211_stop_queue(struc + else + local->q_stop_reasons[queue][reason]++; + +- if (__test_and_set_bit(reason, &local->queue_stop_reasons[queue])) +- return; +- +- if (local->hw.queues < IEEE80211_NUM_ACS) +- n_acs = 1; +- +- rcu_read_lock(); +- list_for_each_entry_rcu(sdata, &local->interfaces, list) { +- int ac; +- +- if (!sdata->dev) +- continue; +- +- for (ac = 0; ac < n_acs; ac++) { +- if (!local->ops->wake_tx_queue && +- (sdata->vif.hw_queue[ac] == queue || +- sdata->vif.cab_queue == queue)) +- netif_stop_subqueue(sdata->dev, ac); +- } +- } +- rcu_read_unlock(); ++ set_bit(reason, &local->queue_stop_reasons[queue]); + } + + void ieee80211_stop_queue_by_reason(struct ieee80211_hw *hw, int queue, +--- a/net/mac80211/wme.c ++++ b/net/mac80211/wme.c +@@ -122,6 +122,9 @@ u16 ieee80211_select_queue_80211(struct + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + u8 *p; + ++ /* Ensure hash is set prior to potential SW encryption */ ++ skb_get_hash(skb); ++ + if ((info->control.flags & IEEE80211_TX_CTRL_DONT_REORDER) || + local->hw.queues < IEEE80211_NUM_ACS) + return 0; +@@ -141,13 +144,16 @@ u16 ieee80211_select_queue_80211(struct + return ieee80211_downgrade_queue(sdata, NULL, skb); + } + +-u16 __ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, +- struct sta_info *sta, struct sk_buff *skb) ++u16 ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, struct sk_buff *skb) + { + const struct ethhdr *eth = (void *)skb->data; + struct mac80211_qos_map *qos_map; + bool qos; + ++ /* Ensure hash is set prior to potential SW encryption */ ++ skb_get_hash(skb); ++ + /* all mesh/ocb stations are required to support WME */ + if ((sdata->vif.type == NL80211_IFTYPE_MESH_POINT && + !is_multicast_ether_addr(eth->h_dest)) || +@@ -178,59 +184,6 @@ u16 __ieee80211_select_queue(struct ieee + return ieee80211_downgrade_queue(sdata, sta, skb); + } + +- +-/* Indicate which queue to use. */ +-u16 ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, +- struct sk_buff *skb) +-{ +- struct ieee80211_local *local = sdata->local; +- struct sta_info *sta = NULL; +- const u8 *ra = NULL; +- u16 ret; +- +- /* when using iTXQ, we can do this later */ +- if (local->ops->wake_tx_queue) +- return 0; +- +- if (local->hw.queues < IEEE80211_NUM_ACS || skb->len < 6) { +- skb->priority = 0; /* required for correct WPA/11i MIC */ +- return 0; +- } +- +- rcu_read_lock(); +- switch (sdata->vif.type) { +- case NL80211_IFTYPE_AP_VLAN: +- sta = rcu_dereference(sdata->u.vlan.sta); +- if (sta) +- break; +- fallthrough; +- case NL80211_IFTYPE_AP: +- ra = skb->data; +- break; +- case NL80211_IFTYPE_STATION: +- /* might be a TDLS station */ +- sta = sta_info_get(sdata, skb->data); +- if (sta) +- break; +- +- ra = sdata->deflink.u.mgd.bssid; +- break; +- case NL80211_IFTYPE_ADHOC: +- ra = skb->data; +- break; +- default: +- break; +- } +- +- if (!sta && ra && !is_multicast_ether_addr(ra)) +- sta = sta_info_get(sdata, ra); +- +- ret = __ieee80211_select_queue(sdata, sta, skb); +- +- rcu_read_unlock(); +- return ret; +-} +- + /** + * ieee80211_set_qos_hdr - Fill in the QoS header if there is one. + * +--- a/net/mac80211/wme.h ++++ b/net/mac80211/wme.h +@@ -13,10 +13,8 @@ + u16 ieee80211_select_queue_80211(struct ieee80211_sub_if_data *sdata, + struct sk_buff *skb, + struct ieee80211_hdr *hdr); +-u16 __ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, +- struct sta_info *sta, struct sk_buff *skb); + u16 ieee80211_select_queue(struct ieee80211_sub_if_data *sdata, +- struct sk_buff *skb); ++ struct sta_info *sta, struct sk_buff *skb); + void ieee80211_set_qos_hdr(struct ieee80211_sub_if_data *sdata, + struct sk_buff *skb); + diff --git a/package/kernel/mac80211/patches/subsys/306-04-v6.2-wifi-realtek-remove-duplicated-wake_tx_queue.patch b/package/kernel/mac80211/patches/subsys/306-04-v6.2-wifi-realtek-remove-duplicated-wake_tx_queue.patch new file mode 100644 index 000000000..f0dfc75a7 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/306-04-v6.2-wifi-realtek-remove-duplicated-wake_tx_queue.patch @@ -0,0 +1,32 @@ +From: Johannes Berg +Date: Mon, 10 Oct 2022 19:17:46 +0200 +Subject: [PATCH] wifi: realtek: remove duplicated wake_tx_queue + +By accident, the previous patch duplicated the initialization +of the wake_tx_queue callback. Fix that by removing the new +initializations. + +Fixes: a790cc3a4fad ("wifi: mac80211: add wake_tx_queue callback to drivers") +Signed-off-by: Johannes Berg +--- + +--- a/drivers/net/wireless/realtek/rtw88/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw88/mac80211.c +@@ -896,7 +896,6 @@ static void rtw_ops_sta_rc_update(struct + + const struct ieee80211_ops rtw_ops = { + .tx = rtw_ops_tx, +- .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .wake_tx_queue = rtw_ops_wake_tx_queue, + .start = rtw_ops_start, + .stop = rtw_ops_stop, +--- a/drivers/net/wireless/realtek/rtw89/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -918,7 +918,6 @@ static int rtw89_ops_set_tid_config(stru + + const struct ieee80211_ops rtw89_ops = { + .tx = rtw89_ops_tx, +- .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .wake_tx_queue = rtw89_ops_wake_tx_queue, + .start = rtw89_ops_start, + .stop = rtw89_ops_stop, diff --git a/package/kernel/mac80211/patches/subsys/306-wifi-mac80211-clear-vif-drv_priv-after-calling-remov.patch b/package/kernel/mac80211/patches/subsys/306-wifi-mac80211-clear-vif-drv_priv-after-calling-remov.patch deleted file mode 100644 index b0119988d..000000000 --- a/package/kernel/mac80211/patches/subsys/306-wifi-mac80211-clear-vif-drv_priv-after-calling-remov.patch +++ /dev/null @@ -1,29 +0,0 @@ -From: Felix Fietkau -Date: Wed, 3 Jul 2024 12:10:01 +0200 -Subject: [PATCH] wifi: mac80211: clear vif drv_priv after calling - remove_interface - -Avoid reusing stale driver data when an interface is brought down and up -again. In order to avoid having to duplicate the memset in every single -driver, do it here. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/mac80211/iface.c -+++ b/net/mac80211/iface.c -@@ -693,8 +693,12 @@ static void ieee80211_do_stop(struct iee - - fallthrough; - default: -- if (going_down) -- drv_remove_interface(local, sdata); -+ if (!going_down) -+ break; -+ drv_remove_interface(local, sdata); -+ -+ /* Clear private driver data to prevent reuse */ -+ memset(sdata->vif.drv_priv, 0, local->hw.vif_data_size); - } - - ieee80211_recalc_ps(local); diff --git a/package/kernel/mac80211/patches/subsys/310-v6.2-mac80211-add-support-for-restricting-netdev-features.patch b/package/kernel/mac80211/patches/subsys/310-v6.2-mac80211-add-support-for-restricting-netdev-features.patch new file mode 100644 index 000000000..812b12189 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/310-v6.2-mac80211-add-support-for-restricting-netdev-features.patch @@ -0,0 +1,506 @@ +From: Felix Fietkau +Date: Sun, 9 Oct 2022 20:15:46 +0200 +Subject: [PATCH] mac80211: add support for restricting netdev features per vif + +This can be used to selectively disable feature flags for checksum offload, +scatter/gather or GSO by changing vif->netdev_features. +Removing features from vif->netdev_features does not affect the netdev +features themselves, but instead fixes up skbs in the tx path so that the +offloads are not needed in the driver. + +Aside from making it easier to deal with vif type based hardware limitations, +this also makes it possible to optimize performance on hardware without native +GSO support by declaring GSO support in hw->netdev_features and removing it +from vif->netdev_features. This allows mac80211 to handle GSO segmentation +after the sta lookup, but before itxq enqueue, thus reducing the number of +unnecessary sta lookups, as well as some other per-packet processing. + +Signed-off-by: Felix Fietkau +--- + +--- a/include/net/fq_impl.h ++++ b/include/net/fq_impl.h +@@ -200,6 +200,7 @@ static void fq_tin_enqueue(struct fq *fq + fq_skb_free_t free_func) + { + struct fq_flow *flow; ++ struct sk_buff *next; + bool oom; + + lockdep_assert_held(&fq->lock); +@@ -214,11 +215,15 @@ static void fq_tin_enqueue(struct fq *fq + } + + flow->tin = tin; +- flow->backlog += skb->len; +- tin->backlog_bytes += skb->len; +- tin->backlog_packets++; +- fq->memory_usage += skb->truesize; +- fq->backlog++; ++ skb_list_walk_safe(skb, skb, next) { ++ skb_mark_not_on_list(skb); ++ flow->backlog += skb->len; ++ tin->backlog_bytes += skb->len; ++ tin->backlog_packets++; ++ fq->memory_usage += skb->truesize; ++ fq->backlog++; ++ __skb_queue_tail(&flow->queue, skb); ++ } + + if (list_empty(&flow->flowchain)) { + flow->deficit = fq->quantum; +@@ -226,7 +231,6 @@ static void fq_tin_enqueue(struct fq *fq + &tin->new_flows); + } + +- __skb_queue_tail(&flow->queue, skb); + oom = (fq->memory_usage > fq->memory_limit); + while (fq->backlog > fq->limit || oom) { + flow = fq_find_fattest_flow(fq); +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -1807,6 +1807,10 @@ struct ieee80211_vif_cfg { + * @addr: address of this interface + * @p2p: indicates whether this AP or STA interface is a p2p + * interface, i.e. a GO or p2p-sta respectively ++ * @netdev_features: tx netdev features supported by the hardware for this ++ * vif. mac80211 initializes this to hw->netdev_features, and the driver ++ * can mask out specific tx features. mac80211 will handle software fixup ++ * for masked offloads (GSO, CSUM) + * @driver_flags: flags/capabilities the driver has for this interface, + * these need to be set (or cleared) when the interface is added + * or, if supported by the driver, the interface type is changed +@@ -1846,6 +1850,7 @@ struct ieee80211_vif { + + struct ieee80211_txq *txq; + ++ netdev_features_t netdev_features; + u32 driver_flags; + u32 offload_flags; + +--- a/net/mac80211/iface.c ++++ b/net/mac80211/iface.c +@@ -2181,6 +2181,7 @@ int ieee80211_if_add(struct ieee80211_lo + ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; + ndev->hw_features |= ndev->features & + MAC80211_SUPPORTED_FEATURES_TX; ++ sdata->vif.netdev_features = local->hw.netdev_features; + + netdev_set_default_ethtool_ops(ndev, &ieee80211_ethtool_ops); + +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -1356,7 +1356,11 @@ static struct txq_info *ieee80211_get_tx + + static void ieee80211_set_skb_enqueue_time(struct sk_buff *skb) + { +- IEEE80211_SKB_CB(skb)->control.enqueue_time = codel_get_time(); ++ struct sk_buff *next; ++ codel_time_t now = codel_get_time(); ++ ++ skb_list_walk_safe(skb, skb, next) ++ IEEE80211_SKB_CB(skb)->control.enqueue_time = now; + } + + static u32 codel_skb_len_func(const struct sk_buff *skb) +@@ -3579,55 +3583,79 @@ ieee80211_xmit_fast_finish(struct ieee80 + return TX_CONTINUE; + } + +-static bool ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata, +- struct sta_info *sta, +- struct ieee80211_fast_tx *fast_tx, +- struct sk_buff *skb) ++static netdev_features_t ++ieee80211_sdata_netdev_features(struct ieee80211_sub_if_data *sdata) + { +- struct ieee80211_local *local = sdata->local; +- u16 ethertype = (skb->data[12] << 8) | skb->data[13]; +- int extra_head = fast_tx->hdr_len - (ETH_HLEN - 2); +- int hw_headroom = sdata->local->hw.extra_tx_headroom; +- struct ethhdr eth; +- struct ieee80211_tx_info *info; +- struct ieee80211_hdr *hdr = (void *)fast_tx->hdr; +- struct ieee80211_tx_data tx; +- ieee80211_tx_result r; +- struct tid_ampdu_tx *tid_tx = NULL; +- u8 tid = IEEE80211_NUM_TIDS; ++ if (sdata->vif.type != NL80211_IFTYPE_AP_VLAN) ++ return sdata->vif.netdev_features; + +- /* control port protocol needs a lot of special handling */ +- if (cpu_to_be16(ethertype) == sdata->control_port_protocol) +- return false; ++ if (!sdata->bss) ++ return 0; + +- /* only RFC 1042 SNAP */ +- if (ethertype < ETH_P_802_3_MIN) +- return false; ++ sdata = container_of(sdata->bss, struct ieee80211_sub_if_data, u.ap); ++ return sdata->vif.netdev_features; ++} + +- /* don't handle TX status request here either */ +- if (skb->sk && skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) +- return false; ++static struct sk_buff * ++ieee80211_tx_skb_fixup(struct sk_buff *skb, netdev_features_t features) ++{ ++ if (skb_is_gso(skb)) { ++ struct sk_buff *segs; + +- if (hdr->frame_control & cpu_to_le16(IEEE80211_STYPE_QOS_DATA)) { +- tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; +- tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); +- if (tid_tx) { +- if (!test_bit(HT_AGG_STATE_OPERATIONAL, &tid_tx->state)) +- return false; +- if (tid_tx->timeout) +- tid_tx->last_tx = jiffies; +- } ++ segs = skb_gso_segment(skb, features); ++ if (!segs) ++ return skb; ++ if (IS_ERR(segs)) ++ goto free; ++ ++ consume_skb(skb); ++ return segs; + } + +- /* after this point (skb is modified) we cannot return false */ ++ if (skb_needs_linearize(skb, features) && __skb_linearize(skb)) ++ goto free; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ int ofs = skb_checksum_start_offset(skb); ++ ++ if (skb->encapsulation) ++ skb_set_inner_transport_header(skb, ofs); ++ else ++ skb_set_transport_header(skb, ofs); ++ ++ if (skb_csum_hwoffload_help(skb, features)) ++ goto free; ++ } ++ ++ skb_mark_not_on_list(skb); ++ return skb; ++ ++free: ++ kfree_skb(skb); ++ return NULL; ++} ++ ++static void __ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, ++ struct ieee80211_fast_tx *fast_tx, ++ struct sk_buff *skb, u8 tid, bool ampdu) ++{ ++ struct ieee80211_local *local = sdata->local; ++ struct ieee80211_hdr *hdr = (void *)fast_tx->hdr; ++ struct ieee80211_tx_info *info; ++ struct ieee80211_tx_data tx; ++ ieee80211_tx_result r; ++ int hw_headroom = sdata->local->hw.extra_tx_headroom; ++ int extra_head = fast_tx->hdr_len - (ETH_HLEN - 2); ++ struct ethhdr eth; + + skb = skb_share_check(skb, GFP_ATOMIC); + if (unlikely(!skb)) +- return true; ++ return; + + if ((hdr->frame_control & cpu_to_le16(IEEE80211_STYPE_QOS_DATA)) && + ieee80211_amsdu_aggregate(sdata, sta, fast_tx, skb)) +- return true; ++ return; + + /* will not be crypto-handled beyond what we do here, so use false + * as the may-encrypt argument for the resize to not account for +@@ -3636,10 +3664,8 @@ static bool ieee80211_xmit_fast(struct i + if (unlikely(ieee80211_skb_resize(sdata, skb, + max_t(int, extra_head + hw_headroom - + skb_headroom(skb), 0), +- ENCRYPT_NO))) { +- kfree_skb(skb); +- return true; +- } ++ ENCRYPT_NO))) ++ goto free; + + memcpy(ð, skb->data, ETH_HLEN - 2); + hdr = skb_push(skb, extra_head); +@@ -3653,7 +3679,7 @@ static bool ieee80211_xmit_fast(struct i + info->control.vif = &sdata->vif; + info->flags = IEEE80211_TX_CTL_FIRST_FRAGMENT | + IEEE80211_TX_CTL_DONTFRAG | +- (tid_tx ? IEEE80211_TX_CTL_AMPDU : 0); ++ (ampdu ? IEEE80211_TX_CTL_AMPDU : 0); + info->control.flags = IEEE80211_TX_CTRL_FAST_XMIT | + u32_encode_bits(IEEE80211_LINK_UNSPECIFIED, + IEEE80211_TX_CTRL_MLO_LINK); +@@ -3677,16 +3703,14 @@ static bool ieee80211_xmit_fast(struct i + tx.key = fast_tx->key; + + if (ieee80211_queue_skb(local, sdata, sta, skb)) +- return true; ++ return; + + tx.skb = skb; + r = ieee80211_xmit_fast_finish(sdata, sta, fast_tx->pn_offs, + fast_tx->key, &tx); + tx.skb = NULL; +- if (r == TX_DROP) { +- kfree_skb(skb); +- return true; +- } ++ if (r == TX_DROP) ++ goto free; + + if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) + sdata = container_of(sdata->bss, +@@ -3694,6 +3718,56 @@ static bool ieee80211_xmit_fast(struct i + + __skb_queue_tail(&tx.skbs, skb); + ieee80211_tx_frags(local, &sdata->vif, sta, &tx.skbs, false); ++ return; ++ ++free: ++ kfree_skb(skb); ++} ++ ++static bool ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, ++ struct ieee80211_fast_tx *fast_tx, ++ struct sk_buff *skb) ++{ ++ u16 ethertype = (skb->data[12] << 8) | skb->data[13]; ++ struct ieee80211_hdr *hdr = (void *)fast_tx->hdr; ++ struct tid_ampdu_tx *tid_tx = NULL; ++ struct sk_buff *next; ++ u8 tid = IEEE80211_NUM_TIDS; ++ ++ /* control port protocol needs a lot of special handling */ ++ if (cpu_to_be16(ethertype) == sdata->control_port_protocol) ++ return false; ++ ++ /* only RFC 1042 SNAP */ ++ if (ethertype < ETH_P_802_3_MIN) ++ return false; ++ ++ /* don't handle TX status request here either */ ++ if (skb->sk && skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) ++ return false; ++ ++ if (hdr->frame_control & cpu_to_le16(IEEE80211_STYPE_QOS_DATA)) { ++ tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); ++ if (tid_tx) { ++ if (!test_bit(HT_AGG_STATE_OPERATIONAL, &tid_tx->state)) ++ return false; ++ if (tid_tx->timeout) ++ tid_tx->last_tx = jiffies; ++ } ++ } ++ ++ /* after this point (skb is modified) we cannot return false */ ++ skb = ieee80211_tx_skb_fixup(skb, ieee80211_sdata_netdev_features(sdata)); ++ if (!skb) ++ return true; ++ ++ skb_list_walk_safe(skb, skb, next) { ++ skb_mark_not_on_list(skb); ++ __ieee80211_xmit_fast(sdata, sta, fast_tx, skb, tid, tid_tx); ++ } ++ + return true; + } + +@@ -4201,31 +4275,14 @@ void __ieee80211_subif_start_xmit(struct + goto out; + } + +- if (skb_is_gso(skb)) { +- struct sk_buff *segs; +- +- segs = skb_gso_segment(skb, 0); +- if (IS_ERR(segs)) { +- goto out_free; +- } else if (segs) { +- consume_skb(skb); +- skb = segs; +- } +- } else { +- /* we cannot process non-linear frames on this path */ +- if (skb_linearize(skb)) +- goto out_free; +- +- /* the frame could be fragmented, software-encrypted, and other +- * things so we cannot really handle checksum offload with it - +- * fix it up in software before we handle anything else. +- */ +- if (skb->ip_summed == CHECKSUM_PARTIAL) { +- skb_set_transport_header(skb, +- skb_checksum_start_offset(skb)); +- if (skb_checksum_help(skb)) +- goto out_free; +- } ++ /* the frame could be fragmented, software-encrypted, and other ++ * things so we cannot really handle checksum or GSO offload. ++ * fix it up in software before we handle anything else. ++ */ ++ skb = ieee80211_tx_skb_fixup(skb, 0); ++ if (!skb) { ++ len = 0; ++ goto out; + } + + skb_list_walk_safe(skb, skb, next) { +@@ -4443,9 +4500,11 @@ normal: + return NETDEV_TX_OK; + } + +-static bool ieee80211_tx_8023(struct ieee80211_sub_if_data *sdata, +- struct sk_buff *skb, struct sta_info *sta, +- bool txpending) ++ ++ ++static bool __ieee80211_tx_8023(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, struct sta_info *sta, ++ bool txpending) + { + struct ieee80211_local *local = sdata->local; + struct ieee80211_tx_control control = {}; +@@ -4454,14 +4513,6 @@ static bool ieee80211_tx_8023(struct iee + unsigned long flags; + int q = info->hw_queue; + +- if (sta) +- sk_pacing_shift_update(skb->sk, local->hw.tx_sk_pacing_shift); +- +- ieee80211_tpt_led_trig_tx(local, skb->len); +- +- if (ieee80211_queue_skb(local, sdata, sta, skb)) +- return true; +- + spin_lock_irqsave(&local->queue_stop_reason_lock, flags); + + if (local->queue_stop_reasons[q] || +@@ -4488,6 +4539,26 @@ static bool ieee80211_tx_8023(struct iee + return true; + } + ++static bool ieee80211_tx_8023(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, struct sta_info *sta, ++ bool txpending) ++{ ++ struct ieee80211_local *local = sdata->local; ++ struct sk_buff *next; ++ bool ret = true; ++ ++ if (ieee80211_queue_skb(local, sdata, sta, skb)) ++ return true; ++ ++ skb_list_walk_safe(skb, skb, next) { ++ skb_mark_not_on_list(skb); ++ if (!__ieee80211_tx_8023(sdata, skb, sta, txpending)) ++ ret = false; ++ } ++ ++ return ret; ++} ++ + static void ieee80211_8023_xmit(struct ieee80211_sub_if_data *sdata, + struct net_device *dev, struct sta_info *sta, + struct ieee80211_key *key, struct sk_buff *skb) +@@ -4495,9 +4566,13 @@ static void ieee80211_8023_xmit(struct i + struct ieee80211_tx_info *info; + struct ieee80211_local *local = sdata->local; + struct tid_ampdu_tx *tid_tx; ++ struct sk_buff *seg, *next; ++ unsigned int skbs = 0, len = 0; ++ u16 queue; + u8 tid; + +- skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, sta, skb)); ++ queue = ieee80211_select_queue(sdata, sta, skb); ++ skb_set_queue_mapping(skb, queue); + + if (unlikely(test_bit(SCAN_SW_SCANNING, &local->scanning)) && + test_bit(SDATA_STATE_OFFCHANNEL, &sdata->state)) +@@ -4507,9 +4582,6 @@ static void ieee80211_8023_xmit(struct i + if (unlikely(!skb)) + return; + +- info = IEEE80211_SKB_CB(skb); +- memset(info, 0, sizeof(*info)); +- + ieee80211_aggr_check(sdata, sta, skb); + + tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; +@@ -4523,22 +4595,20 @@ static void ieee80211_8023_xmit(struct i + return; + } + +- info->flags |= IEEE80211_TX_CTL_AMPDU; + if (tid_tx->timeout) + tid_tx->last_tx = jiffies; + } + +- if (unlikely(skb->sk && +- skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS)) +- info->ack_frame_id = ieee80211_store_ack_skb(local, skb, +- &info->flags, NULL); ++ skb = ieee80211_tx_skb_fixup(skb, ieee80211_sdata_netdev_features(sdata)); ++ if (!skb) ++ return; + +- info->hw_queue = sdata->vif.hw_queue[skb_get_queue_mapping(skb)]; ++ info = IEEE80211_SKB_CB(skb); ++ memset(info, 0, sizeof(*info)); ++ if (tid_tx) ++ info->flags |= IEEE80211_TX_CTL_AMPDU; + +- dev_sw_netstats_tx_add(dev, 1, skb->len); +- +- sta->deflink.tx_stats.bytes[skb_get_queue_mapping(skb)] += skb->len; +- sta->deflink.tx_stats.packets[skb_get_queue_mapping(skb)]++; ++ info->hw_queue = sdata->vif.hw_queue[queue]; + + if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) + sdata = container_of(sdata->bss, +@@ -4550,6 +4620,24 @@ static void ieee80211_8023_xmit(struct i + if (key) + info->control.hw_key = &key->conf; + ++ skb_list_walk_safe(skb, seg, next) { ++ skbs++; ++ len += seg->len; ++ if (seg != skb) ++ memcpy(IEEE80211_SKB_CB(seg), info, sizeof(*info)); ++ } ++ ++ if (unlikely(skb->sk && ++ skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS)) ++ info->ack_frame_id = ieee80211_store_ack_skb(local, skb, ++ &info->flags, NULL); ++ ++ dev_sw_netstats_tx_add(dev, skbs, len); ++ sta->deflink.tx_stats.packets[queue] += skbs; ++ sta->deflink.tx_stats.bytes[queue] += len; ++ ++ ieee80211_tpt_led_trig_tx(local, len); ++ + ieee80211_tx_8023(sdata, skb, sta, false); + + return; +@@ -4591,6 +4679,7 @@ netdev_tx_t ieee80211_subif_start_xmit_8 + key->conf.cipher == WLAN_CIPHER_SUITE_TKIP)) + goto skip_offload; + ++ sk_pacing_shift_update(skb->sk, sdata->local->hw.tx_sk_pacing_shift); + ieee80211_8023_xmit(sdata, dev, sta, key, skb); + goto out; + diff --git a/package/kernel/mac80211/patches/subsys/311-v6.2-wifi-mac80211-fix-and-simplify-unencrypted-drop-chec.patch b/package/kernel/mac80211/patches/subsys/311-v6.2-wifi-mac80211-fix-and-simplify-unencrypted-drop-chec.patch new file mode 100644 index 000000000..804b02eb3 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/311-v6.2-wifi-mac80211-fix-and-simplify-unencrypted-drop-chec.patch @@ -0,0 +1,87 @@ +From: Felix Fietkau +Date: Thu, 1 Dec 2022 14:57:30 +0100 +Subject: [PATCH] wifi: mac80211: fix and simplify unencrypted drop check for + mesh + +ieee80211_drop_unencrypted is called from ieee80211_rx_h_mesh_fwding and +ieee80211_frame_allowed. + +Since ieee80211_rx_h_mesh_fwding can forward packets for other mesh nodes +and is called earlier, it needs to check the decryptions status and if the +packet is using the control protocol on its own, instead of deferring to +the later call from ieee80211_frame_allowed. + +Because of that, ieee80211_drop_unencrypted has a mesh specific check +that skips over the mesh header in order to check the payload protocol. +This code is invalid when called from ieee80211_frame_allowed, since that +happens after the 802.11->802.3 conversion. + +Fix this by moving the mesh specific check directly into +ieee80211_rx_h_mesh_fwding. + +Signed-off-by: Felix Fietkau +Link: https://lore.kernel.org/r/20221201135730.19723-1-nbd@nbd.name +Signed-off-by: Johannes Berg +--- + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2403,7 +2403,6 @@ static int ieee80211_802_1x_port_control + + static int ieee80211_drop_unencrypted(struct ieee80211_rx_data *rx, __le16 fc) + { +- struct ieee80211_hdr *hdr = (void *)rx->skb->data; + struct sk_buff *skb = rx->skb; + struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); + +@@ -2414,31 +2413,6 @@ static int ieee80211_drop_unencrypted(st + if (status->flag & RX_FLAG_DECRYPTED) + return 0; + +- /* check mesh EAPOL frames first */ +- if (unlikely(rx->sta && ieee80211_vif_is_mesh(&rx->sdata->vif) && +- ieee80211_is_data(fc))) { +- struct ieee80211s_hdr *mesh_hdr; +- u16 hdr_len = ieee80211_hdrlen(fc); +- u16 ethertype_offset; +- __be16 ethertype; +- +- if (!ether_addr_equal(hdr->addr1, rx->sdata->vif.addr)) +- goto drop_check; +- +- /* make sure fixed part of mesh header is there, also checks skb len */ +- if (!pskb_may_pull(rx->skb, hdr_len + 6)) +- goto drop_check; +- +- mesh_hdr = (struct ieee80211s_hdr *)(skb->data + hdr_len); +- ethertype_offset = hdr_len + ieee80211_get_mesh_hdrlen(mesh_hdr) + +- sizeof(rfc1042_header); +- +- if (skb_copy_bits(rx->skb, ethertype_offset, ðertype, 2) == 0 && +- ethertype == rx->sdata->control_port_protocol) +- return 0; +- } +- +-drop_check: + /* Drop unencrypted frames if key is set. */ + if (unlikely(!ieee80211_has_protected(fc) && + !ieee80211_is_any_nullfunc(fc) && +@@ -2892,8 +2866,16 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 + hdr = (struct ieee80211_hdr *) skb->data; + mesh_hdr = (struct ieee80211s_hdr *) (skb->data + hdrlen); + +- if (ieee80211_drop_unencrypted(rx, hdr->frame_control)) +- return RX_DROP_MONITOR; ++ if (ieee80211_drop_unencrypted(rx, hdr->frame_control)) { ++ int offset = hdrlen + ieee80211_get_mesh_hdrlen(mesh_hdr) + ++ sizeof(rfc1042_header); ++ __be16 ethertype; ++ ++ if (!ether_addr_equal(hdr->addr1, rx->sdata->vif.addr) || ++ skb_copy_bits(rx->skb, offset, ðertype, 2) != 0 || ++ ethertype != rx->sdata->control_port_protocol) ++ return RX_DROP_MONITOR; ++ } + + /* frame is in RMC, don't forward */ + if (ieee80211_is_data(hdr->frame_control) && diff --git a/package/kernel/mac80211/patches/subsys/312-v6.3-wifi-cfg80211-move-A-MSDU-check-in-ieee80211_data_to.patch b/package/kernel/mac80211/patches/subsys/312-v6.3-wifi-cfg80211-move-A-MSDU-check-in-ieee80211_data_to.patch new file mode 100644 index 000000000..f668905cc --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/312-v6.3-wifi-cfg80211-move-A-MSDU-check-in-ieee80211_data_to.patch @@ -0,0 +1,25 @@ +From: Felix Fietkau +Date: Fri, 2 Dec 2022 13:53:11 +0100 +Subject: [PATCH] wifi: cfg80211: move A-MSDU check in + ieee80211_data_to_8023_exthdr + +When parsing the outer A-MSDU header, don't check for inner bridge tunnel +or RFC1042 headers. This is handled by ieee80211_amsdu_to_8023s already. + +Signed-off-by: Felix Fietkau +--- + +--- a/net/wireless/util.c ++++ b/net/wireless/util.c +@@ -631,8 +631,9 @@ int ieee80211_data_to_8023_exthdr(struct + break; + } + +- if (likely(skb_copy_bits(skb, hdrlen, &payload, sizeof(payload)) == 0 && +- ((!is_amsdu && ether_addr_equal(payload.hdr, rfc1042_header) && ++ if (likely(!is_amsdu && ++ skb_copy_bits(skb, hdrlen, &payload, sizeof(payload)) == 0 && ++ ((ether_addr_equal(payload.hdr, rfc1042_header) && + payload.proto != htons(ETH_P_AARP) && + payload.proto != htons(ETH_P_IPX)) || + ether_addr_equal(payload.hdr, bridge_tunnel_header)))) { diff --git a/package/kernel/mac80211/patches/subsys/313-v6.3-wifi-cfg80211-factor-out-bridge-tunnel-RFC1042-heade.patch b/package/kernel/mac80211/patches/subsys/313-v6.3-wifi-cfg80211-factor-out-bridge-tunnel-RFC1042-heade.patch new file mode 100644 index 000000000..864105786 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/313-v6.3-wifi-cfg80211-factor-out-bridge-tunnel-RFC1042-heade.patch @@ -0,0 +1,76 @@ +From: Felix Fietkau +Date: Fri, 2 Dec 2022 13:54:15 +0100 +Subject: [PATCH] wifi: cfg80211: factor out bridge tunnel / RFC1042 header + check + +The same check is done in multiple places, unify it. + +Signed-off-by: Felix Fietkau +--- + +--- a/net/wireless/util.c ++++ b/net/wireless/util.c +@@ -542,6 +542,21 @@ unsigned int ieee80211_get_mesh_hdrlen(s + } + EXPORT_SYMBOL(ieee80211_get_mesh_hdrlen); + ++static bool ieee80211_get_8023_tunnel_proto(const void *hdr, __be16 *proto) ++{ ++ const __be16 *hdr_proto = hdr + ETH_ALEN; ++ ++ if (!(ether_addr_equal(hdr, rfc1042_header) && ++ *hdr_proto != htons(ETH_P_AARP) && ++ *hdr_proto != htons(ETH_P_IPX)) && ++ !ether_addr_equal(hdr, bridge_tunnel_header)) ++ return false; ++ ++ *proto = *hdr_proto; ++ ++ return true; ++} ++ + int ieee80211_data_to_8023_exthdr(struct sk_buff *skb, struct ethhdr *ehdr, + const u8 *addr, enum nl80211_iftype iftype, + u8 data_offset, bool is_amsdu) +@@ -633,14 +648,9 @@ int ieee80211_data_to_8023_exthdr(struct + + if (likely(!is_amsdu && + skb_copy_bits(skb, hdrlen, &payload, sizeof(payload)) == 0 && +- ((ether_addr_equal(payload.hdr, rfc1042_header) && +- payload.proto != htons(ETH_P_AARP) && +- payload.proto != htons(ETH_P_IPX)) || +- ether_addr_equal(payload.hdr, bridge_tunnel_header)))) { +- /* remove RFC1042 or Bridge-Tunnel encapsulation and +- * replace EtherType */ ++ ieee80211_get_8023_tunnel_proto(&payload, &tmp.h_proto))) { ++ /* remove RFC1042 or Bridge-Tunnel encapsulation */ + hdrlen += ETH_ALEN + 2; +- tmp.h_proto = payload.proto; + skb_postpull_rcsum(skb, &payload, ETH_ALEN + 2); + } else { + tmp.h_proto = htons(skb->len - hdrlen); +@@ -756,8 +766,6 @@ void ieee80211_amsdu_to_8023s(struct sk_ + { + unsigned int hlen = ALIGN(extra_headroom, 4); + struct sk_buff *frame = NULL; +- u16 ethertype; +- u8 *payload; + int offset = 0, remaining; + struct ethhdr eth; + bool reuse_frag = skb->head_frag && !skb_has_frag_list(skb); +@@ -811,14 +819,8 @@ void ieee80211_amsdu_to_8023s(struct sk_ + frame->dev = skb->dev; + frame->priority = skb->priority; + +- payload = frame->data; +- ethertype = (payload[6] << 8) | payload[7]; +- if (likely((ether_addr_equal(payload, rfc1042_header) && +- ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || +- ether_addr_equal(payload, bridge_tunnel_header))) { +- eth.h_proto = htons(ethertype); ++ if (likely(ieee80211_get_8023_tunnel_proto(frame->data, ð.h_proto))) + skb_pull(frame, ETH_ALEN + 2); +- } + + memcpy(skb_push(frame, sizeof(eth)), ð, sizeof(eth)); + __skb_queue_tail(list, frame); diff --git a/package/kernel/mac80211/patches/subsys/314-v6.3-wifi-mac80211-remove-mesh-forwarding-congestion-chec.patch b/package/kernel/mac80211/patches/subsys/314-v6.3-wifi-mac80211-remove-mesh-forwarding-congestion-chec.patch new file mode 100644 index 000000000..515176f0d --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/314-v6.3-wifi-mac80211-remove-mesh-forwarding-congestion-chec.patch @@ -0,0 +1,54 @@ +From: Felix Fietkau +Date: Fri, 2 Dec 2022 17:01:46 +0100 +Subject: [PATCH] wifi: mac80211: remove mesh forwarding congestion check + +Now that all drivers use iTXQ, it does not make sense to check to drop +tx forwarding packets when the driver has stopped the queues. +fq_codel will take care of dropping packets when the queues fill up + +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/debugfs_netdev.c ++++ b/net/mac80211/debugfs_netdev.c +@@ -603,8 +603,6 @@ IEEE80211_IF_FILE(fwded_mcast, u.mesh.ms + IEEE80211_IF_FILE(fwded_unicast, u.mesh.mshstats.fwded_unicast, DEC); + IEEE80211_IF_FILE(fwded_frames, u.mesh.mshstats.fwded_frames, DEC); + IEEE80211_IF_FILE(dropped_frames_ttl, u.mesh.mshstats.dropped_frames_ttl, DEC); +-IEEE80211_IF_FILE(dropped_frames_congestion, +- u.mesh.mshstats.dropped_frames_congestion, DEC); + IEEE80211_IF_FILE(dropped_frames_no_route, + u.mesh.mshstats.dropped_frames_no_route, DEC); + +@@ -740,7 +738,6 @@ static void add_mesh_stats(struct ieee80 + MESHSTATS_ADD(fwded_frames); + MESHSTATS_ADD(dropped_frames_ttl); + MESHSTATS_ADD(dropped_frames_no_route); +- MESHSTATS_ADD(dropped_frames_congestion); + #undef MESHSTATS_ADD + } + +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -329,7 +329,6 @@ struct mesh_stats { + __u32 fwded_frames; /* Mesh total forwarded frames */ + __u32 dropped_frames_ttl; /* Not transmitted since mesh_ttl == 0*/ + __u32 dropped_frames_no_route; /* Not transmitted, no route found */ +- __u32 dropped_frames_congestion;/* Not forwarded due to congestion */ + }; + + #define PREQ_Q_F_START 0x1 +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2926,11 +2926,6 @@ ieee80211_rx_h_mesh_fwding(struct ieee80 + return RX_CONTINUE; + + ac = ieee802_1d_to_ac[skb->priority]; +- q = sdata->vif.hw_queue[ac]; +- if (ieee80211_queue_stopped(&local->hw, q)) { +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, dropped_frames_congestion); +- return RX_DROP_MONITOR; +- } + skb_set_queue_mapping(skb, ac); + + if (!--mesh_hdr->ttl) { diff --git a/package/kernel/mac80211/patches/subsys/315-v6.3-wifi-mac80211-fix-receiving-A-MSDU-frames-on-mesh-in.patch b/package/kernel/mac80211/patches/subsys/315-v6.3-wifi-mac80211-fix-receiving-A-MSDU-frames-on-mesh-in.patch new file mode 100644 index 000000000..59b799b6b --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/315-v6.3-wifi-mac80211-fix-receiving-A-MSDU-frames-on-mesh-in.patch @@ -0,0 +1,762 @@ +From 986e43b19ae9176093da35e0a844e65c8bf9ede7 Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Mon, 13 Feb 2023 11:08:54 +0100 +Subject: [PATCH] wifi: mac80211: fix receiving A-MSDU frames on mesh + interfaces + +The current mac80211 mesh A-MSDU receive path fails to parse A-MSDU packets +on mesh interfaces, because it assumes that the Mesh Control field is always +directly after the 802.11 header. +802.11-2020 9.3.2.2.2 Figure 9-70 shows that the Mesh Control field is +actually part of the A-MSDU subframe header. +This makes more sense, since it allows packets for multiple different +destinations to be included in the same A-MSDU, as long as RA and TID are +still the same. +Another issue is the fact that the A-MSDU subframe length field was apparently +accidentally defined as little-endian in the standard. + +In order to fix this, the mesh forwarding path needs happen at a different +point in the receive path. + +ieee80211_data_to_8023_exthdr is changed to ignore the mesh control field +and leave it in after the ethernet header. This also affects the source/dest +MAC address fields, which now in the case of mesh point to the mesh SA/DA. + +ieee80211_amsdu_to_8023s is changed to deal with the endian difference and +to add the Mesh Control length to the subframe length, since it's not covered +by the MSDU length field. + +With these changes, the mac80211 will get the same packet structure for +converted regular data packets and unpacked A-MSDU subframes. + +The mesh forwarding checks are now only performed after the A-MSDU decap. +For locally received packets, the Mesh Control header is stripped away. +For forwarded packets, a new 802.11 header gets added. + +Signed-off-by: Felix Fietkau +Link: https://lore.kernel.org/r/20230213100855.34315-4-nbd@nbd.name +[fix fortify build error] +Signed-off-by: Johannes Berg +--- + .../wireless/marvell/mwifiex/11n_rxreorder.c | 2 +- + include/net/cfg80211.h | 27 +- + net/mac80211/rx.c | 350 ++++++++++-------- + net/wireless/util.c | 120 +++--- + 4 files changed, 297 insertions(+), 202 deletions(-) + +--- a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c ++++ b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c +@@ -33,7 +33,7 @@ static int mwifiex_11n_dispatch_amsdu_pk + skb_trim(skb, le16_to_cpu(local_rx_pd->rx_pkt_length)); + + ieee80211_amsdu_to_8023s(skb, &list, priv->curr_addr, +- priv->wdev.iftype, 0, NULL, NULL); ++ priv->wdev.iftype, 0, NULL, NULL, false); + + while (!skb_queue_empty(&list)) { + struct rx_packet_hdr *rx_hdr; +--- a/include/net/cfg80211.h ++++ b/include/net/cfg80211.h +@@ -6208,11 +6208,36 @@ static inline int ieee80211_data_to_8023 + * @extra_headroom: The hardware extra headroom for SKBs in the @list. + * @check_da: DA to check in the inner ethernet header, or NULL + * @check_sa: SA to check in the inner ethernet header, or NULL ++ * @mesh_control: A-MSDU subframe header includes the mesh control field + */ + void ieee80211_amsdu_to_8023s(struct sk_buff *skb, struct sk_buff_head *list, + const u8 *addr, enum nl80211_iftype iftype, + const unsigned int extra_headroom, +- const u8 *check_da, const u8 *check_sa); ++ const u8 *check_da, const u8 *check_sa, ++ bool mesh_control); ++ ++/** ++ * ieee80211_get_8023_tunnel_proto - get RFC1042 or bridge tunnel encap protocol ++ * ++ * Check for RFC1042 or bridge tunnel header and fetch the encapsulated ++ * protocol. ++ * ++ * @hdr: pointer to the MSDU payload ++ * @proto: destination pointer to store the protocol ++ * Return: true if encapsulation was found ++ */ ++bool ieee80211_get_8023_tunnel_proto(const void *hdr, __be16 *proto); ++ ++/** ++ * ieee80211_strip_8023_mesh_hdr - strip mesh header from converted 802.3 frames ++ * ++ * Strip the mesh header, which was left in by ieee80211_data_to_8023 as part ++ * of the MSDU data. Also move any source/destination addresses from the mesh ++ * header to the ethernet header (if present). ++ * ++ * @skb: The 802.3 frame with embedded mesh header ++ */ ++int ieee80211_strip_8023_mesh_hdr(struct sk_buff *skb); + + /** + * cfg80211_classify8021d - determine the 802.1p/1d tag for a data frame +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2720,6 +2720,174 @@ ieee80211_deliver_skb(struct ieee80211_r + } + } + ++static ieee80211_rx_result ++ieee80211_rx_mesh_data(struct ieee80211_sub_if_data *sdata, struct sta_info *sta, ++ struct sk_buff *skb) ++{ ++#ifdef CPTCFG_MAC80211_MESH ++ struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; ++ struct ieee80211_local *local = sdata->local; ++ uint16_t fc = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA; ++ struct ieee80211_hdr hdr = { ++ .frame_control = cpu_to_le16(fc) ++ }; ++ struct ieee80211_hdr *fwd_hdr; ++ struct ieee80211s_hdr *mesh_hdr; ++ struct ieee80211_tx_info *info; ++ struct sk_buff *fwd_skb; ++ struct ethhdr *eth; ++ bool multicast; ++ int tailroom = 0; ++ int hdrlen, mesh_hdrlen; ++ u8 *qos; ++ ++ if (!ieee80211_vif_is_mesh(&sdata->vif)) ++ return RX_CONTINUE; ++ ++ if (!pskb_may_pull(skb, sizeof(*eth) + 6)) ++ return RX_DROP_MONITOR; ++ ++ mesh_hdr = (struct ieee80211s_hdr *)(skb->data + sizeof(*eth)); ++ mesh_hdrlen = ieee80211_get_mesh_hdrlen(mesh_hdr); ++ ++ if (!pskb_may_pull(skb, sizeof(*eth) + mesh_hdrlen)) ++ return RX_DROP_MONITOR; ++ ++ eth = (struct ethhdr *)skb->data; ++ multicast = is_multicast_ether_addr(eth->h_dest); ++ ++ mesh_hdr = (struct ieee80211s_hdr *)(eth + 1); ++ if (!mesh_hdr->ttl) ++ return RX_DROP_MONITOR; ++ ++ /* frame is in RMC, don't forward */ ++ if (is_multicast_ether_addr(eth->h_dest) && ++ mesh_rmc_check(sdata, eth->h_source, mesh_hdr)) ++ return RX_DROP_MONITOR; ++ ++ /* Frame has reached destination. Don't forward */ ++ if (ether_addr_equal(sdata->vif.addr, eth->h_dest)) ++ goto rx_accept; ++ ++ if (!ifmsh->mshcfg.dot11MeshForwarding) { ++ if (is_multicast_ether_addr(eth->h_dest)) ++ goto rx_accept; ++ ++ return RX_DROP_MONITOR; ++ } ++ ++ /* forward packet */ ++ if (sdata->crypto_tx_tailroom_needed_cnt) ++ tailroom = IEEE80211_ENCRYPT_TAILROOM; ++ ++ if (!--mesh_hdr->ttl) { ++ if (multicast) ++ goto rx_accept; ++ ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, dropped_frames_ttl); ++ return RX_DROP_MONITOR; ++ } ++ ++ if (mesh_hdr->flags & MESH_FLAGS_AE) { ++ struct mesh_path *mppath; ++ char *proxied_addr; ++ ++ if (multicast) ++ proxied_addr = mesh_hdr->eaddr1; ++ else if ((mesh_hdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6) ++ /* has_a4 already checked in ieee80211_rx_mesh_check */ ++ proxied_addr = mesh_hdr->eaddr2; ++ else ++ return RX_DROP_MONITOR; ++ ++ rcu_read_lock(); ++ mppath = mpp_path_lookup(sdata, proxied_addr); ++ if (!mppath) { ++ mpp_path_add(sdata, proxied_addr, eth->h_source); ++ } else { ++ spin_lock_bh(&mppath->state_lock); ++ if (!ether_addr_equal(mppath->mpp, eth->h_source)) ++ memcpy(mppath->mpp, eth->h_source, ETH_ALEN); ++ mppath->exp_time = jiffies; ++ spin_unlock_bh(&mppath->state_lock); ++ } ++ rcu_read_unlock(); ++ } ++ ++ skb_set_queue_mapping(skb, ieee802_1d_to_ac[skb->priority]); ++ ++ ieee80211_fill_mesh_addresses(&hdr, &hdr.frame_control, ++ eth->h_dest, eth->h_source); ++ hdrlen = ieee80211_hdrlen(hdr.frame_control); ++ if (multicast) { ++ int extra_head = sizeof(struct ieee80211_hdr) - sizeof(*eth); ++ ++ fwd_skb = skb_copy_expand(skb, local->tx_headroom + extra_head + ++ IEEE80211_ENCRYPT_HEADROOM, ++ tailroom, GFP_ATOMIC); ++ if (!fwd_skb) ++ goto rx_accept; ++ } else { ++ fwd_skb = skb; ++ skb = NULL; ++ ++ if (skb_cow_head(fwd_skb, hdrlen - sizeof(struct ethhdr))) ++ return RX_DROP_UNUSABLE; ++ } ++ ++ fwd_hdr = skb_push(fwd_skb, hdrlen - sizeof(struct ethhdr)); ++ memcpy(fwd_hdr, &hdr, hdrlen - 2); ++ qos = ieee80211_get_qos_ctl(fwd_hdr); ++ qos[0] = qos[1] = 0; ++ ++ skb_reset_mac_header(fwd_skb); ++ hdrlen += mesh_hdrlen; ++ if (ieee80211_get_8023_tunnel_proto(fwd_skb->data + hdrlen, ++ &fwd_skb->protocol)) ++ hdrlen += ETH_ALEN; ++ else ++ fwd_skb->protocol = htons(fwd_skb->len - hdrlen); ++ skb_set_network_header(fwd_skb, hdrlen); ++ ++ info = IEEE80211_SKB_CB(fwd_skb); ++ memset(info, 0, sizeof(*info)); ++ info->control.flags |= IEEE80211_TX_INTCFL_NEED_TXPROCESSING; ++ info->control.vif = &sdata->vif; ++ info->control.jiffies = jiffies; ++ if (multicast) { ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_mcast); ++ memcpy(fwd_hdr->addr2, sdata->vif.addr, ETH_ALEN); ++ /* update power mode indication when forwarding */ ++ ieee80211_mps_set_frame_flags(sdata, NULL, fwd_hdr); ++ } else if (!mesh_nexthop_lookup(sdata, fwd_skb)) { ++ /* mesh power mode flags updated in mesh_nexthop_lookup */ ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_unicast); ++ } else { ++ /* unable to resolve next hop */ ++ if (sta) ++ mesh_path_error_tx(sdata, ifmsh->mshcfg.element_ttl, ++ hdr.addr3, 0, ++ WLAN_REASON_MESH_PATH_NOFORWARD, ++ sta->sta.addr); ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, dropped_frames_no_route); ++ kfree_skb(fwd_skb); ++ goto rx_accept; ++ } ++ ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_frames); ++ fwd_skb->dev = sdata->dev; ++ ieee80211_add_pending_skb(local, fwd_skb); ++ ++rx_accept: ++ if (!skb) ++ return RX_QUEUED; ++ ++ ieee80211_strip_8023_mesh_hdr(skb); ++#endif ++ ++ return RX_CONTINUE; ++} ++ + static ieee80211_rx_result debug_noinline + __ieee80211_rx_h_amsdu(struct ieee80211_rx_data *rx, u8 data_offset) + { +@@ -2728,8 +2896,10 @@ __ieee80211_rx_h_amsdu(struct ieee80211_ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + __le16 fc = hdr->frame_control; + struct sk_buff_head frame_list; ++ static ieee80211_rx_result res; + struct ethhdr ethhdr; + const u8 *check_da = ethhdr.h_dest, *check_sa = ethhdr.h_source; ++ bool mesh = false; + + if (unlikely(ieee80211_has_a4(hdr->frame_control))) { + check_da = NULL; +@@ -2746,6 +2916,8 @@ __ieee80211_rx_h_amsdu(struct ieee80211_ + break; + case NL80211_IFTYPE_MESH_POINT: + check_sa = NULL; ++ check_da = NULL; ++ mesh = true; + break; + default: + break; +@@ -2763,17 +2935,29 @@ __ieee80211_rx_h_amsdu(struct ieee80211_ + ieee80211_amsdu_to_8023s(skb, &frame_list, dev->dev_addr, + rx->sdata->vif.type, + rx->local->hw.extra_tx_headroom, +- check_da, check_sa); ++ check_da, check_sa, mesh); + + while (!skb_queue_empty(&frame_list)) { + rx->skb = __skb_dequeue(&frame_list); + +- if (!ieee80211_frame_allowed(rx, fc)) { +- dev_kfree_skb(rx->skb); ++ res = ieee80211_rx_mesh_data(rx->sdata, rx->sta, rx->skb); ++ switch (res) { ++ case RX_QUEUED: + continue; ++ case RX_CONTINUE: ++ break; ++ default: ++ goto free; + } + ++ if (!ieee80211_frame_allowed(rx, fc)) ++ goto free; ++ + ieee80211_deliver_skb(rx); ++ continue; ++ ++free: ++ dev_kfree_skb(rx->skb); + } + + return RX_QUEUED; +@@ -2806,6 +2990,8 @@ ieee80211_rx_h_amsdu(struct ieee80211_rx + if (!rx->sdata->u.mgd.use_4addr) + return RX_DROP_UNUSABLE; + break; ++ case NL80211_IFTYPE_MESH_POINT: ++ break; + default: + return RX_DROP_UNUSABLE; + } +@@ -2834,155 +3020,6 @@ ieee80211_rx_h_amsdu(struct ieee80211_rx + return __ieee80211_rx_h_amsdu(rx, 0); + } + +-#ifdef CPTCFG_MAC80211_MESH +-static ieee80211_rx_result +-ieee80211_rx_h_mesh_fwding(struct ieee80211_rx_data *rx) +-{ +- struct ieee80211_hdr *fwd_hdr, *hdr; +- struct ieee80211_tx_info *info; +- struct ieee80211s_hdr *mesh_hdr; +- struct sk_buff *skb = rx->skb, *fwd_skb; +- struct ieee80211_local *local = rx->local; +- struct ieee80211_sub_if_data *sdata = rx->sdata; +- struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; +- u16 ac, q, hdrlen; +- int tailroom = 0; +- +- hdr = (struct ieee80211_hdr *) skb->data; +- hdrlen = ieee80211_hdrlen(hdr->frame_control); +- +- /* make sure fixed part of mesh header is there, also checks skb len */ +- if (!pskb_may_pull(rx->skb, hdrlen + 6)) +- return RX_DROP_MONITOR; +- +- mesh_hdr = (struct ieee80211s_hdr *) (skb->data + hdrlen); +- +- /* make sure full mesh header is there, also checks skb len */ +- if (!pskb_may_pull(rx->skb, +- hdrlen + ieee80211_get_mesh_hdrlen(mesh_hdr))) +- return RX_DROP_MONITOR; +- +- /* reload pointers */ +- hdr = (struct ieee80211_hdr *) skb->data; +- mesh_hdr = (struct ieee80211s_hdr *) (skb->data + hdrlen); +- +- if (ieee80211_drop_unencrypted(rx, hdr->frame_control)) { +- int offset = hdrlen + ieee80211_get_mesh_hdrlen(mesh_hdr) + +- sizeof(rfc1042_header); +- __be16 ethertype; +- +- if (!ether_addr_equal(hdr->addr1, rx->sdata->vif.addr) || +- skb_copy_bits(rx->skb, offset, ðertype, 2) != 0 || +- ethertype != rx->sdata->control_port_protocol) +- return RX_DROP_MONITOR; +- } +- +- /* frame is in RMC, don't forward */ +- if (ieee80211_is_data(hdr->frame_control) && +- is_multicast_ether_addr(hdr->addr1) && +- mesh_rmc_check(rx->sdata, hdr->addr3, mesh_hdr)) +- return RX_DROP_MONITOR; +- +- if (!ieee80211_is_data(hdr->frame_control)) +- return RX_CONTINUE; +- +- if (!mesh_hdr->ttl) +- return RX_DROP_MONITOR; +- +- if (mesh_hdr->flags & MESH_FLAGS_AE) { +- struct mesh_path *mppath; +- char *proxied_addr; +- char *mpp_addr; +- +- if (is_multicast_ether_addr(hdr->addr1)) { +- mpp_addr = hdr->addr3; +- proxied_addr = mesh_hdr->eaddr1; +- } else if ((mesh_hdr->flags & MESH_FLAGS_AE) == +- MESH_FLAGS_AE_A5_A6) { +- /* has_a4 already checked in ieee80211_rx_mesh_check */ +- mpp_addr = hdr->addr4; +- proxied_addr = mesh_hdr->eaddr2; +- } else { +- return RX_DROP_MONITOR; +- } +- +- rcu_read_lock(); +- mppath = mpp_path_lookup(sdata, proxied_addr); +- if (!mppath) { +- mpp_path_add(sdata, proxied_addr, mpp_addr); +- } else { +- spin_lock_bh(&mppath->state_lock); +- if (!ether_addr_equal(mppath->mpp, mpp_addr)) +- memcpy(mppath->mpp, mpp_addr, ETH_ALEN); +- mppath->exp_time = jiffies; +- spin_unlock_bh(&mppath->state_lock); +- } +- rcu_read_unlock(); +- } +- +- /* Frame has reached destination. Don't forward */ +- if (!is_multicast_ether_addr(hdr->addr1) && +- ether_addr_equal(sdata->vif.addr, hdr->addr3)) +- return RX_CONTINUE; +- +- ac = ieee802_1d_to_ac[skb->priority]; +- skb_set_queue_mapping(skb, ac); +- +- if (!--mesh_hdr->ttl) { +- if (!is_multicast_ether_addr(hdr->addr1)) +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, +- dropped_frames_ttl); +- goto out; +- } +- +- if (!ifmsh->mshcfg.dot11MeshForwarding) +- goto out; +- +- if (sdata->crypto_tx_tailroom_needed_cnt) +- tailroom = IEEE80211_ENCRYPT_TAILROOM; +- +- fwd_skb = skb_copy_expand(skb, local->tx_headroom + +- IEEE80211_ENCRYPT_HEADROOM, +- tailroom, GFP_ATOMIC); +- if (!fwd_skb) +- goto out; +- +- fwd_skb->dev = sdata->dev; +- fwd_hdr = (struct ieee80211_hdr *) fwd_skb->data; +- fwd_hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_RETRY); +- info = IEEE80211_SKB_CB(fwd_skb); +- memset(info, 0, sizeof(*info)); +- info->control.flags |= IEEE80211_TX_INTCFL_NEED_TXPROCESSING; +- info->control.vif = &rx->sdata->vif; +- info->control.jiffies = jiffies; +- if (is_multicast_ether_addr(fwd_hdr->addr1)) { +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_mcast); +- memcpy(fwd_hdr->addr2, sdata->vif.addr, ETH_ALEN); +- /* update power mode indication when forwarding */ +- ieee80211_mps_set_frame_flags(sdata, NULL, fwd_hdr); +- } else if (!mesh_nexthop_lookup(sdata, fwd_skb)) { +- /* mesh power mode flags updated in mesh_nexthop_lookup */ +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_unicast); +- } else { +- /* unable to resolve next hop */ +- mesh_path_error_tx(sdata, ifmsh->mshcfg.element_ttl, +- fwd_hdr->addr3, 0, +- WLAN_REASON_MESH_PATH_NOFORWARD, +- fwd_hdr->addr2); +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, dropped_frames_no_route); +- kfree_skb(fwd_skb); +- return RX_DROP_MONITOR; +- } +- +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_frames); +- ieee80211_add_pending_skb(local, fwd_skb); +- out: +- if (is_multicast_ether_addr(hdr->addr1)) +- return RX_CONTINUE; +- return RX_DROP_MONITOR; +-} +-#endif +- + static ieee80211_rx_result debug_noinline + ieee80211_rx_h_data(struct ieee80211_rx_data *rx) + { +@@ -2991,6 +3028,7 @@ ieee80211_rx_h_data(struct ieee80211_rx_ + struct net_device *dev = sdata->dev; + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)rx->skb->data; + __le16 fc = hdr->frame_control; ++ static ieee80211_rx_result res; + bool port_control; + int err; + +@@ -3017,6 +3055,10 @@ ieee80211_rx_h_data(struct ieee80211_rx_ + if (unlikely(err)) + return RX_DROP_UNUSABLE; + ++ res = ieee80211_rx_mesh_data(rx->sdata, rx->sta, rx->skb); ++ if (res != RX_CONTINUE) ++ return res; ++ + if (!ieee80211_frame_allowed(rx, fc)) + return RX_DROP_MONITOR; + +@@ -3987,10 +4029,6 @@ static void ieee80211_rx_handlers(struct + CALL_RXH(ieee80211_rx_h_defragment); + CALL_RXH(ieee80211_rx_h_michael_mic_verify); + /* must be after MMIC verify so header is counted in MPDU mic */ +-#ifdef CPTCFG_MAC80211_MESH +- if (ieee80211_vif_is_mesh(&rx->sdata->vif)) +- CALL_RXH(ieee80211_rx_h_mesh_fwding); +-#endif + CALL_RXH(ieee80211_rx_h_amsdu); + CALL_RXH(ieee80211_rx_h_data); + +--- a/net/wireless/util.c ++++ b/net/wireless/util.c +@@ -542,7 +542,7 @@ unsigned int ieee80211_get_mesh_hdrlen(s + } + EXPORT_SYMBOL(ieee80211_get_mesh_hdrlen); + +-static bool ieee80211_get_8023_tunnel_proto(const void *hdr, __be16 *proto) ++bool ieee80211_get_8023_tunnel_proto(const void *hdr, __be16 *proto) + { + const __be16 *hdr_proto = hdr + ETH_ALEN; + +@@ -556,6 +556,49 @@ static bool ieee80211_get_8023_tunnel_pr + + return true; + } ++EXPORT_SYMBOL(ieee80211_get_8023_tunnel_proto); ++ ++int ieee80211_strip_8023_mesh_hdr(struct sk_buff *skb) ++{ ++ const void *mesh_addr; ++ struct { ++ struct ethhdr eth; ++ u8 flags; ++ } payload; ++ int hdrlen; ++ int ret; ++ ++ ret = skb_copy_bits(skb, 0, &payload, sizeof(payload)); ++ if (ret) ++ return ret; ++ ++ hdrlen = sizeof(payload.eth) + __ieee80211_get_mesh_hdrlen(payload.flags); ++ ++ if (likely(pskb_may_pull(skb, hdrlen + 8) && ++ ieee80211_get_8023_tunnel_proto(skb->data + hdrlen, ++ &payload.eth.h_proto))) ++ hdrlen += ETH_ALEN + 2; ++ else if (!pskb_may_pull(skb, hdrlen)) ++ return -EINVAL; ++ ++ mesh_addr = skb->data + sizeof(payload.eth) + ETH_ALEN; ++ switch (payload.flags & MESH_FLAGS_AE) { ++ case MESH_FLAGS_AE_A4: ++ memcpy(&payload.eth.h_source, mesh_addr, ETH_ALEN); ++ break; ++ case MESH_FLAGS_AE_A5_A6: ++ memcpy(&payload.eth, mesh_addr, 2 * ETH_ALEN); ++ break; ++ default: ++ break; ++ } ++ ++ pskb_pull(skb, hdrlen - sizeof(payload.eth)); ++ memcpy(skb->data, &payload.eth, sizeof(payload.eth)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(ieee80211_strip_8023_mesh_hdr); + + int ieee80211_data_to_8023_exthdr(struct sk_buff *skb, struct ethhdr *ehdr, + const u8 *addr, enum nl80211_iftype iftype, +@@ -568,7 +611,6 @@ int ieee80211_data_to_8023_exthdr(struct + } payload; + struct ethhdr tmp; + u16 hdrlen; +- u8 mesh_flags = 0; + + if (unlikely(!ieee80211_is_data_present(hdr->frame_control))) + return -1; +@@ -589,12 +631,6 @@ int ieee80211_data_to_8023_exthdr(struct + memcpy(tmp.h_dest, ieee80211_get_DA(hdr), ETH_ALEN); + memcpy(tmp.h_source, ieee80211_get_SA(hdr), ETH_ALEN); + +- if (iftype == NL80211_IFTYPE_MESH_POINT && +- skb_copy_bits(skb, hdrlen, &mesh_flags, 1) < 0) +- return -1; +- +- mesh_flags &= MESH_FLAGS_AE; +- + switch (hdr->frame_control & + cpu_to_le16(IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) { + case cpu_to_le16(IEEE80211_FCTL_TODS): +@@ -608,17 +644,6 @@ int ieee80211_data_to_8023_exthdr(struct + iftype != NL80211_IFTYPE_AP_VLAN && + iftype != NL80211_IFTYPE_STATION)) + return -1; +- if (iftype == NL80211_IFTYPE_MESH_POINT) { +- if (mesh_flags == MESH_FLAGS_AE_A4) +- return -1; +- if (mesh_flags == MESH_FLAGS_AE_A5_A6 && +- skb_copy_bits(skb, hdrlen + +- offsetof(struct ieee80211s_hdr, eaddr1), +- tmp.h_dest, 2 * ETH_ALEN) < 0) +- return -1; +- +- hdrlen += __ieee80211_get_mesh_hdrlen(mesh_flags); +- } + break; + case cpu_to_le16(IEEE80211_FCTL_FROMDS): + if ((iftype != NL80211_IFTYPE_STATION && +@@ -627,16 +652,6 @@ int ieee80211_data_to_8023_exthdr(struct + (is_multicast_ether_addr(tmp.h_dest) && + ether_addr_equal(tmp.h_source, addr))) + return -1; +- if (iftype == NL80211_IFTYPE_MESH_POINT) { +- if (mesh_flags == MESH_FLAGS_AE_A5_A6) +- return -1; +- if (mesh_flags == MESH_FLAGS_AE_A4 && +- skb_copy_bits(skb, hdrlen + +- offsetof(struct ieee80211s_hdr, eaddr1), +- tmp.h_source, ETH_ALEN) < 0) +- return -1; +- hdrlen += __ieee80211_get_mesh_hdrlen(mesh_flags); +- } + break; + case cpu_to_le16(0): + if (iftype != NL80211_IFTYPE_ADHOC && +@@ -646,7 +661,7 @@ int ieee80211_data_to_8023_exthdr(struct + break; + } + +- if (likely(!is_amsdu && ++ if (likely(!is_amsdu && iftype != NL80211_IFTYPE_MESH_POINT && + skb_copy_bits(skb, hdrlen, &payload, sizeof(payload)) == 0 && + ieee80211_get_8023_tunnel_proto(&payload, &tmp.h_proto))) { + /* remove RFC1042 or Bridge-Tunnel encapsulation */ +@@ -722,7 +737,8 @@ __ieee80211_amsdu_copy_frag(struct sk_bu + + static struct sk_buff * + __ieee80211_amsdu_copy(struct sk_buff *skb, unsigned int hlen, +- int offset, int len, bool reuse_frag) ++ int offset, int len, bool reuse_frag, ++ int min_len) + { + struct sk_buff *frame; + int cur_len = len; +@@ -736,7 +752,7 @@ __ieee80211_amsdu_copy(struct sk_buff *s + * in the stack later. + */ + if (reuse_frag) +- cur_len = min_t(int, len, 32); ++ cur_len = min_t(int, len, min_len); + + /* + * Allocate and reserve two bytes more for payload +@@ -746,6 +762,7 @@ __ieee80211_amsdu_copy(struct sk_buff *s + if (!frame) + return NULL; + ++ frame->priority = skb->priority; + skb_reserve(frame, hlen + sizeof(struct ethhdr) + 2); + skb_copy_bits(skb, offset, skb_put(frame, cur_len), cur_len); + +@@ -762,23 +779,37 @@ __ieee80211_amsdu_copy(struct sk_buff *s + void ieee80211_amsdu_to_8023s(struct sk_buff *skb, struct sk_buff_head *list, + const u8 *addr, enum nl80211_iftype iftype, + const unsigned int extra_headroom, +- const u8 *check_da, const u8 *check_sa) ++ const u8 *check_da, const u8 *check_sa, ++ bool mesh_control) + { + unsigned int hlen = ALIGN(extra_headroom, 4); + struct sk_buff *frame = NULL; + int offset = 0, remaining; +- struct ethhdr eth; ++ struct { ++ struct ethhdr eth; ++ uint8_t flags; ++ } hdr; + bool reuse_frag = skb->head_frag && !skb_has_frag_list(skb); + bool reuse_skb = false; + bool last = false; ++ int copy_len = sizeof(hdr.eth); ++ ++ if (iftype == NL80211_IFTYPE_MESH_POINT) ++ copy_len = sizeof(hdr); + + while (!last) { + unsigned int subframe_len; +- int len; ++ int len, mesh_len = 0; + u8 padding; + +- skb_copy_bits(skb, offset, ð, sizeof(eth)); +- len = ntohs(eth.h_proto); ++ skb_copy_bits(skb, offset, &hdr, copy_len); ++ if (iftype == NL80211_IFTYPE_MESH_POINT) ++ mesh_len = __ieee80211_get_mesh_hdrlen(hdr.flags); ++ if (mesh_control) ++ len = le16_to_cpu(*(__le16 *)&hdr.eth.h_proto) + mesh_len; ++ else ++ len = ntohs(hdr.eth.h_proto); ++ + subframe_len = sizeof(struct ethhdr) + len; + padding = (4 - subframe_len) & 0x3; + +@@ -787,16 +818,16 @@ void ieee80211_amsdu_to_8023s(struct sk_ + if (subframe_len > remaining) + goto purge; + /* mitigate A-MSDU aggregation injection attacks */ +- if (ether_addr_equal(eth.h_dest, rfc1042_header)) ++ if (ether_addr_equal(hdr.eth.h_dest, rfc1042_header)) + goto purge; + + offset += sizeof(struct ethhdr); + last = remaining <= subframe_len + padding; + + /* FIXME: should we really accept multicast DA? */ +- if ((check_da && !is_multicast_ether_addr(eth.h_dest) && +- !ether_addr_equal(check_da, eth.h_dest)) || +- (check_sa && !ether_addr_equal(check_sa, eth.h_source))) { ++ if ((check_da && !is_multicast_ether_addr(hdr.eth.h_dest) && ++ !ether_addr_equal(check_da, hdr.eth.h_dest)) || ++ (check_sa && !ether_addr_equal(check_sa, hdr.eth.h_source))) { + offset += len + padding; + continue; + } +@@ -808,7 +839,7 @@ void ieee80211_amsdu_to_8023s(struct sk_ + reuse_skb = true; + } else { + frame = __ieee80211_amsdu_copy(skb, hlen, offset, len, +- reuse_frag); ++ reuse_frag, 32 + mesh_len); + if (!frame) + goto purge; + +@@ -819,10 +850,11 @@ void ieee80211_amsdu_to_8023s(struct sk_ + frame->dev = skb->dev; + frame->priority = skb->priority; + +- if (likely(ieee80211_get_8023_tunnel_proto(frame->data, ð.h_proto))) ++ if (likely(iftype != NL80211_IFTYPE_MESH_POINT && ++ ieee80211_get_8023_tunnel_proto(frame->data, &hdr.eth.h_proto))) + skb_pull(frame, ETH_ALEN + 2); + +- memcpy(skb_push(frame, sizeof(eth)), ð, sizeof(eth)); ++ memcpy(skb_push(frame, sizeof(hdr.eth)), &hdr.eth, sizeof(hdr.eth)); + __skb_queue_tail(list, frame); + } + diff --git a/package/kernel/mac80211/patches/subsys/316-v6.3-wifi-mac80211-add-a-workaround-for-receiving-non-sta.patch b/package/kernel/mac80211/patches/subsys/316-v6.3-wifi-mac80211-add-a-workaround-for-receiving-non-sta.patch new file mode 100644 index 000000000..6dc98ae16 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/316-v6.3-wifi-mac80211-add-a-workaround-for-receiving-non-sta.patch @@ -0,0 +1,145 @@ +From: Felix Fietkau +Date: Fri, 9 Dec 2022 21:15:04 +0100 +Subject: [PATCH] wifi: mac80211: add a workaround for receiving + non-standard mesh A-MSDU + +At least ath10k and ath11k supported hardware (maybe more) does not implement +mesh A-MSDU aggregation in a standard compliant way. +802.11-2020 9.3.2.2.2 declares that the Mesh Control field is part of the +A-MSDU header. As such, its length must not be included in the subframe +length field. +Hardware affected by this bug treats the mesh control field as part of the +MSDU data and sets the length accordingly. +In order to avoid packet loss, keep track of which stations are affected +by this and take it into account when converting A-MSDU to 802.3 + mesh control +packets. + +Signed-off-by: Felix Fietkau +--- + +--- a/include/net/cfg80211.h ++++ b/include/net/cfg80211.h +@@ -6194,6 +6194,19 @@ static inline int ieee80211_data_to_8023 + } + + /** ++ * ieee80211_is_valid_amsdu - check if subframe lengths of an A-MSDU are valid ++ * ++ * This is used to detect non-standard A-MSDU frames, e.g. the ones generated ++ * by ath10k and ath11k, where the subframe length includes the length of the ++ * mesh control field. ++ * ++ * @skb: The input A-MSDU frame without any headers. ++ * @mesh_hdr: use standard compliant mesh A-MSDU subframe header ++ * Returns: true if subframe header lengths are valid for the @mesh_hdr mode ++ */ ++bool ieee80211_is_valid_amsdu(struct sk_buff *skb, bool mesh_hdr); ++ ++/** + * ieee80211_amsdu_to_8023s - decode an IEEE 802.11n A-MSDU frame + * + * Decode an IEEE 802.11 A-MSDU and convert it to a list of 802.3 frames. +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2899,7 +2899,6 @@ __ieee80211_rx_h_amsdu(struct ieee80211_ + static ieee80211_rx_result res; + struct ethhdr ethhdr; + const u8 *check_da = ethhdr.h_dest, *check_sa = ethhdr.h_source; +- bool mesh = false; + + if (unlikely(ieee80211_has_a4(hdr->frame_control))) { + check_da = NULL; +@@ -2917,7 +2916,6 @@ __ieee80211_rx_h_amsdu(struct ieee80211_ + case NL80211_IFTYPE_MESH_POINT: + check_sa = NULL; + check_da = NULL; +- mesh = true; + break; + default: + break; +@@ -2932,10 +2930,21 @@ __ieee80211_rx_h_amsdu(struct ieee80211_ + data_offset, true)) + return RX_DROP_UNUSABLE; + ++ if (rx->sta && rx->sta->amsdu_mesh_control < 0) { ++ bool valid_std = ieee80211_is_valid_amsdu(skb, true); ++ bool valid_nonstd = ieee80211_is_valid_amsdu(skb, false); ++ ++ if (valid_std && !valid_nonstd) ++ rx->sta->amsdu_mesh_control = 1; ++ else if (valid_nonstd && !valid_std) ++ rx->sta->amsdu_mesh_control = 0; ++ } ++ + ieee80211_amsdu_to_8023s(skb, &frame_list, dev->dev_addr, + rx->sdata->vif.type, + rx->local->hw.extra_tx_headroom, +- check_da, check_sa, mesh); ++ check_da, check_sa, ++ rx->sta->amsdu_mesh_control); + + while (!skb_queue_empty(&frame_list)) { + rx->skb = __skb_dequeue(&frame_list); +--- a/net/mac80211/sta_info.c ++++ b/net/mac80211/sta_info.c +@@ -591,6 +591,9 @@ __sta_info_alloc(struct ieee80211_sub_if + + sta->sta_state = IEEE80211_STA_NONE; + ++ if (sdata->vif.type == NL80211_IFTYPE_MESH_POINT) ++ sta->amsdu_mesh_control = -1; ++ + /* Mark TID as unreserved */ + sta->reserved_tid = IEEE80211_TID_UNRESERVED; + +--- a/net/mac80211/sta_info.h ++++ b/net/mac80211/sta_info.h +@@ -702,6 +702,7 @@ struct sta_info { + struct codel_params cparams; + + u8 reserved_tid; ++ s8 amsdu_mesh_control; + + struct cfg80211_chan_def tdls_chandef; + +--- a/net/wireless/util.c ++++ b/net/wireless/util.c +@@ -776,6 +776,38 @@ __ieee80211_amsdu_copy(struct sk_buff *s + return frame; + } + ++bool ieee80211_is_valid_amsdu(struct sk_buff *skb, bool mesh_hdr) ++{ ++ int offset = 0, remaining, subframe_len, padding; ++ ++ for (offset = 0; offset < skb->len; offset += subframe_len + padding) { ++ struct { ++ __be16 len; ++ u8 mesh_flags; ++ } hdr; ++ u16 len; ++ ++ if (skb_copy_bits(skb, offset + 2 * ETH_ALEN, &hdr, sizeof(hdr)) < 0) ++ return false; ++ ++ if (mesh_hdr) ++ len = le16_to_cpu(*(__le16 *)&hdr.len) + ++ __ieee80211_get_mesh_hdrlen(hdr.mesh_flags); ++ else ++ len = ntohs(hdr.len); ++ ++ subframe_len = sizeof(struct ethhdr) + len; ++ padding = (4 - subframe_len) & 0x3; ++ remaining = skb->len - offset; ++ ++ if (subframe_len > remaining) ++ return false; ++ } ++ ++ return true; ++} ++EXPORT_SYMBOL(ieee80211_is_valid_amsdu); ++ + void ieee80211_amsdu_to_8023s(struct sk_buff *skb, struct sk_buff_head *list, + const u8 *addr, enum nl80211_iftype iftype, + const unsigned int extra_headroom, diff --git a/package/kernel/mac80211/patches/subsys/318-wifi-mac80211-fix-race-in-mesh-sequence-number-assig.patch b/package/kernel/mac80211/patches/subsys/318-wifi-mac80211-fix-race-in-mesh-sequence-number-assig.patch new file mode 100644 index 000000000..7d01ffdff --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/318-wifi-mac80211-fix-race-in-mesh-sequence-number-assig.patch @@ -0,0 +1,37 @@ +From: Felix Fietkau +Date: Wed, 15 Feb 2023 15:21:37 +0100 +Subject: [PATCH] wifi: mac80211: fix race in mesh sequence number + assignment + +Since the sequence number is shared across different tx queues, it needs +to be atomic in order to avoid accidental duplicate assignment + +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -696,7 +696,7 @@ struct ieee80211_if_mesh { + struct mesh_stats mshstats; + struct mesh_config mshcfg; + atomic_t estab_plinks; +- u32 mesh_seqnum; ++ atomic_t mesh_seqnum; + bool accepting_plinks; + int num_gates; + struct beacon_data __rcu *beacon; +--- a/net/mac80211/mesh.c ++++ b/net/mac80211/mesh.c +@@ -752,10 +752,8 @@ unsigned int ieee80211_new_mesh_header(s + + meshhdr->ttl = sdata->u.mesh.mshcfg.dot11MeshTTL; + +- /* FIXME: racy -- TX on multiple queues can be concurrent */ +- put_unaligned(cpu_to_le32(sdata->u.mesh.mesh_seqnum), &meshhdr->seqnum); +- sdata->u.mesh.mesh_seqnum++; +- ++ put_unaligned_le32(atomic_inc_return(&sdata->u.mesh.mesh_seqnum), ++ &meshhdr->seqnum); + if (addr4or5 && !addr6) { + meshhdr->flags |= MESH_FLAGS_AE_A4; + memcpy(meshhdr->eaddr1, addr4or5, ETH_ALEN); diff --git a/package/kernel/mac80211/patches/subsys/319-wifi-mac80211-mesh-fast-xmit-support.patch b/package/kernel/mac80211/patches/subsys/319-wifi-mac80211-mesh-fast-xmit-support.patch new file mode 100644 index 000000000..968d2885f --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/319-wifi-mac80211-mesh-fast-xmit-support.patch @@ -0,0 +1,850 @@ +From: Felix Fietkau +Date: Sun, 26 Feb 2023 13:53:08 +0100 +Subject: [PATCH] wifi: mac80211: mesh fast xmit support + +Previously, fast xmit only worked on interface types where initially a +sta lookup is performed, and a cached header can be attached to the sta, +requiring only some fields to be updated at runtime. + +This technique is not directly applicable for a mesh device type due +to the dynamic nature of the topology and protocol. There are more +addresses that need to be filled, and there is an extra header with a +dynamic length based on the addressing mode. + +Change the code to cache entries contain a copy of the mesh subframe header + +bridge tunnel header, as well as an embedded struct ieee80211_fast_tx, which +contains the information for building the 802.11 header. + +Add a mesh specific early fast xmit call, which looks up a cached entry and +adds only the mesh subframe header, before passing it over to the generic +fast xmit code. + +To ensure the changes in network are reflected in these cached headers, +flush affected cached entries on path changes, as well as other conditions +that currently trigger a fast xmit check in other modes (key changes etc.) + +This code is loosely based on a previous implementation by: +Sriram R + +Signed-off-by: Ryder Lee +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -37,6 +37,7 @@ + extern const struct cfg80211_ops mac80211_config_ops; + + struct ieee80211_local; ++struct ieee80211_mesh_fast_tx; + + /* Maximum number of broadcast/multicast frames to buffer when some of the + * associated stations are using power saving. */ +@@ -656,6 +657,19 @@ struct mesh_table { + atomic_t entries; /* Up to MAX_MESH_NEIGHBOURS */ + }; + ++/** ++ * struct mesh_tx_cache - mesh fast xmit header cache ++ * ++ * @rht: hash table containing struct ieee80211_mesh_fast_tx, using skb DA as key ++ * @walk_head: linked list containing all ieee80211_mesh_fast_tx objects ++ * @walk_lock: lock protecting walk_head and rht ++ */ ++struct mesh_tx_cache { ++ struct rhashtable rht; ++ struct hlist_head walk_head; ++ spinlock_t walk_lock; ++}; ++ + struct ieee80211_if_mesh { + struct timer_list housekeeping_timer; + struct timer_list mesh_path_timer; +@@ -734,6 +748,7 @@ struct ieee80211_if_mesh { + struct mesh_table mpp_paths; /* Store paths for MPP&MAP */ + int mesh_paths_generation; + int mpp_paths_generation; ++ struct mesh_tx_cache tx_cache; + }; + + #ifdef CPTCFG_MAC80211_MESH +@@ -2002,6 +2017,11 @@ int ieee80211_tx_control_port(struct wip + int link_id, u64 *cookie); + int ieee80211_probe_mesh_link(struct wiphy *wiphy, struct net_device *dev, + const u8 *buf, size_t len); ++void __ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, ++ struct ieee80211_fast_tx *fast_tx, ++ struct sk_buff *skb, bool ampdu, ++ const u8 *da, const u8 *sa); + + /* HT */ + void ieee80211_apply_htcap_overrides(struct ieee80211_sub_if_data *sdata, +--- a/net/mac80211/mesh.c ++++ b/net/mac80211/mesh.c +@@ -10,6 +10,7 @@ + #include + #include "ieee80211_i.h" + #include "mesh.h" ++#include "wme.h" + #include "driver-ops.h" + + static int mesh_allocated; +@@ -698,6 +699,95 @@ ieee80211_mesh_update_bss_params(struct + __le32_to_cpu(he_oper->he_oper_params); + } + ++bool ieee80211_mesh_xmit_fast(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, u32 ctrl_flags) ++{ ++ struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; ++ struct ieee80211_mesh_fast_tx *entry; ++ struct ieee80211s_hdr *meshhdr; ++ u8 sa[ETH_ALEN] __aligned(2); ++ struct tid_ampdu_tx *tid_tx; ++ struct sta_info *sta; ++ bool copy_sa = false; ++ u16 ethertype; ++ u8 tid; ++ ++ if (ctrl_flags & IEEE80211_TX_CTRL_SKIP_MPATH_LOOKUP) ++ return false; ++ ++ if (ifmsh->mshcfg.dot11MeshNolearn) ++ return false; ++ ++ /* Add support for these cases later */ ++ if (ifmsh->ps_peers_light_sleep || ifmsh->ps_peers_deep_sleep) ++ return false; ++ ++ if (is_multicast_ether_addr(skb->data)) ++ return false; ++ ++ ethertype = (skb->data[12] << 8) | skb->data[13]; ++ if (ethertype < ETH_P_802_3_MIN) ++ return false; ++ ++ if (skb->sk && skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) ++ return false; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ skb_set_transport_header(skb, skb_checksum_start_offset(skb)); ++ if (skb_checksum_help(skb)) ++ return false; ++ } ++ ++ entry = mesh_fast_tx_get(sdata, skb->data); ++ if (!entry) ++ return false; ++ ++ if (skb_headroom(skb) < entry->hdrlen + entry->fast_tx.hdr_len) ++ return false; ++ ++ sta = rcu_dereference(entry->mpath->next_hop); ++ if (!sta) ++ return false; ++ ++ tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); ++ if (tid_tx) { ++ if (!test_bit(HT_AGG_STATE_OPERATIONAL, &tid_tx->state)) ++ return false; ++ if (tid_tx->timeout) ++ tid_tx->last_tx = jiffies; ++ } ++ ++ skb = skb_share_check(skb, GFP_ATOMIC); ++ if (!skb) ++ return true; ++ ++ skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, sta, skb)); ++ ++ meshhdr = (struct ieee80211s_hdr *)entry->hdr; ++ if ((meshhdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6) { ++ /* preserve SA from eth header for 6-addr frames */ ++ ether_addr_copy(sa, skb->data + ETH_ALEN); ++ copy_sa = true; ++ } ++ ++ memcpy(skb_push(skb, entry->hdrlen - 2 * ETH_ALEN), entry->hdr, ++ entry->hdrlen); ++ ++ meshhdr = (struct ieee80211s_hdr *)skb->data; ++ put_unaligned_le32(atomic_inc_return(&sdata->u.mesh.mesh_seqnum), ++ &meshhdr->seqnum); ++ meshhdr->ttl = sdata->u.mesh.mshcfg.dot11MeshTTL; ++ if (copy_sa) ++ ether_addr_copy(meshhdr->eaddr2, sa); ++ ++ skb_push(skb, 2 * ETH_ALEN); ++ __ieee80211_xmit_fast(sdata, sta, &entry->fast_tx, skb, tid_tx, ++ entry->mpath->dst, sdata->vif.addr); ++ ++ return true; ++} ++ + /** + * ieee80211_fill_mesh_addresses - fill addresses of a locally originated mesh frame + * @hdr: 802.11 frame header +@@ -780,6 +870,8 @@ static void ieee80211_mesh_housekeeping( + changed = mesh_accept_plinks_update(sdata); + ieee80211_mbss_info_change_notify(sdata, changed); + ++ mesh_fast_tx_gc(sdata); ++ + mod_timer(&ifmsh->housekeeping_timer, + round_jiffies(jiffies + + IEEE80211_MESH_HOUSEKEEPING_INTERVAL)); +--- a/net/mac80211/mesh.h ++++ b/net/mac80211/mesh.h +@@ -122,11 +122,41 @@ struct mesh_path { + u8 rann_snd_addr[ETH_ALEN]; + u32 rann_metric; + unsigned long last_preq_to_root; ++ unsigned long fast_tx_check; + bool is_root; + bool is_gate; + u32 path_change_count; + }; + ++#define MESH_FAST_TX_CACHE_MAX_SIZE 512 ++#define MESH_FAST_TX_CACHE_THRESHOLD_SIZE 384 ++#define MESH_FAST_TX_CACHE_TIMEOUT 8000 /* msecs */ ++ ++/** ++ * struct ieee80211_mesh_fast_tx - cached mesh fast tx entry ++ * @rhash: rhashtable pointer ++ * @addr_key: The Ethernet DA which is the key for this entry ++ * @fast_tx: base fast_tx data ++ * @hdr: cached mesh and rfc1042 headers ++ * @hdrlen: length of mesh + rfc1042 ++ * @walk_list: list containing all the fast tx entries ++ * @mpath: mesh path corresponding to the Mesh DA ++ * @mppath: MPP entry corresponding to this DA ++ * @timestamp: Last used time of this entry ++ */ ++struct ieee80211_mesh_fast_tx { ++ struct rhash_head rhash; ++ u8 addr_key[ETH_ALEN] __aligned(2); ++ ++ struct ieee80211_fast_tx fast_tx; ++ u8 hdr[sizeof(struct ieee80211s_hdr) + sizeof(rfc1042_header)]; ++ u16 hdrlen; ++ ++ struct mesh_path *mpath, *mppath; ++ struct hlist_node walk_list; ++ unsigned long timestamp; ++}; ++ + /* Recent multicast cache */ + /* RMC_BUCKETS must be a power of 2, maximum 256 */ + #define RMC_BUCKETS 256 +@@ -298,6 +328,20 @@ void mesh_path_discard_frame(struct ieee + void mesh_path_tx_root_frame(struct ieee80211_sub_if_data *sdata); + + bool mesh_action_is_path_sel(struct ieee80211_mgmt *mgmt); ++struct ieee80211_mesh_fast_tx * ++mesh_fast_tx_get(struct ieee80211_sub_if_data *sdata, const u8 *addr); ++bool ieee80211_mesh_xmit_fast(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, u32 ctrl_flags); ++void mesh_fast_tx_cache(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, struct mesh_path *mpath); ++void mesh_fast_tx_gc(struct ieee80211_sub_if_data *sdata); ++void mesh_fast_tx_flush_addr(struct ieee80211_sub_if_data *sdata, ++ const u8 *addr); ++void mesh_fast_tx_flush_mpath(struct mesh_path *mpath); ++void mesh_fast_tx_flush_sta(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta); ++void mesh_path_refresh(struct ieee80211_sub_if_data *sdata, ++ struct mesh_path *mpath, const u8 *addr); + + #ifdef CPTCFG_MAC80211_MESH + static inline +--- a/net/mac80211/mesh_hwmp.c ++++ b/net/mac80211/mesh_hwmp.c +@@ -394,6 +394,7 @@ static u32 hwmp_route_info_get(struct ie + u32 orig_sn, orig_metric; + unsigned long orig_lifetime, exp_time; + u32 last_hop_metric, new_metric; ++ bool flush_mpath = false; + bool process = true; + u8 hopcount; + +@@ -491,8 +492,10 @@ static u32 hwmp_route_info_get(struct ie + } + + if (fresh_info) { +- if (rcu_access_pointer(mpath->next_hop) != sta) ++ if (rcu_access_pointer(mpath->next_hop) != sta) { + mpath->path_change_count++; ++ flush_mpath = true; ++ } + mesh_path_assign_nexthop(mpath, sta); + mpath->flags |= MESH_PATH_SN_VALID; + mpath->metric = new_metric; +@@ -502,6 +505,8 @@ static u32 hwmp_route_info_get(struct ie + mpath->hop_count = hopcount; + mesh_path_activate(mpath); + spin_unlock_bh(&mpath->state_lock); ++ if (flush_mpath) ++ mesh_fast_tx_flush_mpath(mpath); + ewma_mesh_fail_avg_init(&sta->mesh->fail_avg); + /* init it at a low value - 0 start is tricky */ + ewma_mesh_fail_avg_add(&sta->mesh->fail_avg, 1); +@@ -539,8 +544,10 @@ static u32 hwmp_route_info_get(struct ie + } + + if (fresh_info) { +- if (rcu_access_pointer(mpath->next_hop) != sta) ++ if (rcu_access_pointer(mpath->next_hop) != sta) { + mpath->path_change_count++; ++ flush_mpath = true; ++ } + mesh_path_assign_nexthop(mpath, sta); + mpath->metric = last_hop_metric; + mpath->exp_time = time_after(mpath->exp_time, exp_time) +@@ -548,6 +555,8 @@ static u32 hwmp_route_info_get(struct ie + mpath->hop_count = 1; + mesh_path_activate(mpath); + spin_unlock_bh(&mpath->state_lock); ++ if (flush_mpath) ++ mesh_fast_tx_flush_mpath(mpath); + ewma_mesh_fail_avg_init(&sta->mesh->fail_avg); + /* init it at a low value - 0 start is tricky */ + ewma_mesh_fail_avg_add(&sta->mesh->fail_avg, 1); +@@ -1215,6 +1224,20 @@ static int mesh_nexthop_lookup_nolearn(s + return 0; + } + ++void mesh_path_refresh(struct ieee80211_sub_if_data *sdata, ++ struct mesh_path *mpath, const u8 *addr) ++{ ++ if (mpath->flags & (MESH_PATH_REQ_QUEUED | MESH_PATH_FIXED | ++ MESH_PATH_RESOLVING)) ++ return; ++ ++ if (time_after(jiffies, ++ mpath->exp_time - ++ msecs_to_jiffies(sdata->u.mesh.mshcfg.path_refresh_time)) && ++ (!addr || ether_addr_equal(sdata->vif.addr, addr))) ++ mesh_queue_preq(mpath, PREQ_Q_F_START | PREQ_Q_F_REFRESH); ++} ++ + /** + * mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling + * this function is considered "using" the associated mpath, so preempt a path +@@ -1242,19 +1265,15 @@ int mesh_nexthop_lookup(struct ieee80211 + if (!mpath || !(mpath->flags & MESH_PATH_ACTIVE)) + return -ENOENT; + +- if (time_after(jiffies, +- mpath->exp_time - +- msecs_to_jiffies(sdata->u.mesh.mshcfg.path_refresh_time)) && +- ether_addr_equal(sdata->vif.addr, hdr->addr4) && +- !(mpath->flags & MESH_PATH_RESOLVING) && +- !(mpath->flags & MESH_PATH_FIXED)) +- mesh_queue_preq(mpath, PREQ_Q_F_START | PREQ_Q_F_REFRESH); ++ mesh_path_refresh(sdata, mpath, hdr->addr4); + + next_hop = rcu_dereference(mpath->next_hop); + if (next_hop) { + memcpy(hdr->addr1, next_hop->sta.addr, ETH_ALEN); + memcpy(hdr->addr2, sdata->vif.addr, ETH_ALEN); + ieee80211_mps_set_frame_flags(sdata, next_hop, hdr); ++ if (ieee80211_hw_check(&sdata->local->hw, SUPPORT_FAST_XMIT)) ++ mesh_fast_tx_cache(sdata, skb, mpath); + return 0; + } + +--- a/net/mac80211/mesh_pathtbl.c ++++ b/net/mac80211/mesh_pathtbl.c +@@ -14,6 +14,7 @@ + #include "wme.h" + #include "ieee80211_i.h" + #include "mesh.h" ++#include + + static void mesh_path_free_rcu(struct mesh_table *tbl, struct mesh_path *mpath); + +@@ -32,6 +33,41 @@ static const struct rhashtable_params me + .hashfn = mesh_table_hash, + }; + ++static const struct rhashtable_params fast_tx_rht_params = { ++ .nelem_hint = 10, ++ .automatic_shrinking = true, ++ .key_len = ETH_ALEN, ++ .key_offset = offsetof(struct ieee80211_mesh_fast_tx, addr_key), ++ .head_offset = offsetof(struct ieee80211_mesh_fast_tx, rhash), ++ .hashfn = mesh_table_hash, ++}; ++ ++static void __mesh_fast_tx_entry_free(void *ptr, void *tblptr) ++{ ++ struct ieee80211_mesh_fast_tx *entry = ptr; ++ ++ kfree_rcu(entry, fast_tx.rcu_head); ++} ++ ++static void mesh_fast_tx_deinit(struct ieee80211_sub_if_data *sdata) ++{ ++ struct mesh_tx_cache *cache; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ rhashtable_free_and_destroy(&cache->rht, ++ __mesh_fast_tx_entry_free, NULL); ++} ++ ++static void mesh_fast_tx_init(struct ieee80211_sub_if_data *sdata) ++{ ++ struct mesh_tx_cache *cache; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ rhashtable_init(&cache->rht, &fast_tx_rht_params); ++ INIT_HLIST_HEAD(&cache->walk_head); ++ spin_lock_init(&cache->walk_lock); ++} ++ + static inline bool mpath_expired(struct mesh_path *mpath) + { + return (mpath->flags & MESH_PATH_ACTIVE) && +@@ -381,6 +417,243 @@ struct mesh_path *mesh_path_new(struct i + return new_mpath; + } + ++static void mesh_fast_tx_entry_free(struct mesh_tx_cache *cache, ++ struct ieee80211_mesh_fast_tx *entry) ++{ ++ hlist_del_rcu(&entry->walk_list); ++ rhashtable_remove_fast(&cache->rht, &entry->rhash, fast_tx_rht_params); ++ kfree_rcu(entry, fast_tx.rcu_head); ++} ++ ++struct ieee80211_mesh_fast_tx * ++mesh_fast_tx_get(struct ieee80211_sub_if_data *sdata, const u8 *addr) ++{ ++ struct ieee80211_mesh_fast_tx *entry; ++ struct mesh_tx_cache *cache; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); ++ if (!entry) ++ return NULL; ++ ++ if (!(entry->mpath->flags & MESH_PATH_ACTIVE) || ++ mpath_expired(entry->mpath)) { ++ spin_lock_bh(&cache->walk_lock); ++ entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); ++ if (entry) ++ mesh_fast_tx_entry_free(cache, entry); ++ spin_unlock_bh(&cache->walk_lock); ++ return NULL; ++ } ++ ++ mesh_path_refresh(sdata, entry->mpath, NULL); ++ if (entry->mppath) ++ entry->mppath->exp_time = jiffies; ++ entry->timestamp = jiffies; ++ ++ return entry; ++} ++ ++void mesh_fast_tx_cache(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, struct mesh_path *mpath) ++{ ++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ struct ieee80211_mesh_fast_tx *entry, *prev; ++ struct ieee80211_mesh_fast_tx build = {}; ++ struct ieee80211s_hdr *meshhdr; ++ struct mesh_tx_cache *cache; ++ struct ieee80211_key *key; ++ struct mesh_path *mppath; ++ struct sta_info *sta; ++ u8 *qc; ++ ++ if (sdata->noack_map || ++ !ieee80211_is_data_qos(hdr->frame_control)) ++ return; ++ ++ build.fast_tx.hdr_len = ieee80211_hdrlen(hdr->frame_control); ++ meshhdr = (struct ieee80211s_hdr *)(skb->data + build.fast_tx.hdr_len); ++ build.hdrlen = ieee80211_get_mesh_hdrlen(meshhdr); ++ ++ cache = &sdata->u.mesh.tx_cache; ++ if (atomic_read(&cache->rht.nelems) >= MESH_FAST_TX_CACHE_MAX_SIZE) ++ return; ++ ++ sta = rcu_dereference(mpath->next_hop); ++ if (!sta) ++ return; ++ ++ if ((meshhdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6) { ++ /* This is required to keep the mppath alive */ ++ mppath = mpp_path_lookup(sdata, meshhdr->eaddr1); ++ if (!mppath) ++ return; ++ build.mppath = mppath; ++ } else if (ieee80211_has_a4(hdr->frame_control)) { ++ mppath = mpath; ++ } else { ++ return; ++ } ++ ++ /* rate limit, in case fast xmit can't be enabled */ ++ if (mppath->fast_tx_check == jiffies) ++ return; ++ ++ mppath->fast_tx_check = jiffies; ++ ++ /* ++ * Same use of the sta lock as in ieee80211_check_fast_xmit, in order ++ * to protect against concurrent sta key updates. ++ */ ++ spin_lock_bh(&sta->lock); ++ key = rcu_access_pointer(sta->ptk[sta->ptk_idx]); ++ if (!key) ++ key = rcu_access_pointer(sdata->default_unicast_key); ++ build.fast_tx.key = key; ++ ++ if (key) { ++ bool gen_iv, iv_spc; ++ ++ gen_iv = key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_IV; ++ iv_spc = key->conf.flags & IEEE80211_KEY_FLAG_PUT_IV_SPACE; ++ ++ if (!(key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE) || ++ (key->flags & KEY_FLAG_TAINTED)) ++ goto unlock_sta; ++ ++ switch (key->conf.cipher) { ++ case WLAN_CIPHER_SUITE_CCMP: ++ case WLAN_CIPHER_SUITE_CCMP_256: ++ if (gen_iv) ++ build.fast_tx.pn_offs = build.fast_tx.hdr_len; ++ if (gen_iv || iv_spc) ++ build.fast_tx.hdr_len += IEEE80211_CCMP_HDR_LEN; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP: ++ case WLAN_CIPHER_SUITE_GCMP_256: ++ if (gen_iv) ++ build.fast_tx.pn_offs = build.fast_tx.hdr_len; ++ if (gen_iv || iv_spc) ++ build.fast_tx.hdr_len += IEEE80211_GCMP_HDR_LEN; ++ break; ++ default: ++ goto unlock_sta; ++ } ++ } ++ ++ memcpy(build.addr_key, mppath->dst, ETH_ALEN); ++ build.timestamp = jiffies; ++ build.fast_tx.band = info->band; ++ build.fast_tx.da_offs = offsetof(struct ieee80211_hdr, addr3); ++ build.fast_tx.sa_offs = offsetof(struct ieee80211_hdr, addr4); ++ build.mpath = mpath; ++ memcpy(build.hdr, meshhdr, build.hdrlen); ++ memcpy(build.hdr + build.hdrlen, rfc1042_header, sizeof(rfc1042_header)); ++ build.hdrlen += sizeof(rfc1042_header); ++ memcpy(build.fast_tx.hdr, hdr, build.fast_tx.hdr_len); ++ ++ hdr = (struct ieee80211_hdr *)build.fast_tx.hdr; ++ if (build.fast_tx.key) ++ hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PROTECTED); ++ ++ qc = ieee80211_get_qos_ctl(hdr); ++ qc[1] |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT >> 8; ++ ++ entry = kmemdup(&build, sizeof(build), GFP_ATOMIC); ++ if (!entry) ++ goto unlock_sta; ++ ++ spin_lock(&cache->walk_lock); ++ prev = rhashtable_lookup_get_insert_fast(&cache->rht, ++ &entry->rhash, ++ fast_tx_rht_params); ++ if (unlikely(IS_ERR(prev))) { ++ kfree(entry); ++ goto unlock_cache; ++ } ++ ++ /* ++ * replace any previous entry in the hash table, in case we're ++ * replacing it with a different type (e.g. mpath -> mpp) ++ */ ++ if (unlikely(prev)) { ++ rhashtable_replace_fast(&cache->rht, &prev->rhash, ++ &entry->rhash, fast_tx_rht_params); ++ hlist_del_rcu(&prev->walk_list); ++ kfree_rcu(prev, fast_tx.rcu_head); ++ } ++ ++ hlist_add_head(&entry->walk_list, &cache->walk_head); ++ ++unlock_cache: ++ spin_unlock(&cache->walk_lock); ++unlock_sta: ++ spin_unlock_bh(&sta->lock); ++} ++ ++void mesh_fast_tx_gc(struct ieee80211_sub_if_data *sdata) ++{ ++ unsigned long timeout = msecs_to_jiffies(MESH_FAST_TX_CACHE_TIMEOUT); ++ struct mesh_tx_cache *cache; ++ struct ieee80211_mesh_fast_tx *entry; ++ struct hlist_node *n; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ if (atomic_read(&cache->rht.nelems) < MESH_FAST_TX_CACHE_THRESHOLD_SIZE) ++ return; ++ ++ spin_lock_bh(&cache->walk_lock); ++ hlist_for_each_entry_safe(entry, n, &cache->walk_head, walk_list) ++ if (!time_is_after_jiffies(entry->timestamp + timeout)) ++ mesh_fast_tx_entry_free(cache, entry); ++ spin_unlock_bh(&cache->walk_lock); ++} ++ ++void mesh_fast_tx_flush_mpath(struct mesh_path *mpath) ++{ ++ struct ieee80211_sub_if_data *sdata = mpath->sdata; ++ struct mesh_tx_cache *cache = &sdata->u.mesh.tx_cache; ++ struct ieee80211_mesh_fast_tx *entry; ++ struct hlist_node *n; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ spin_lock_bh(&cache->walk_lock); ++ hlist_for_each_entry_safe(entry, n, &cache->walk_head, walk_list) ++ if (entry->mpath == mpath) ++ mesh_fast_tx_entry_free(cache, entry); ++ spin_unlock_bh(&cache->walk_lock); ++} ++ ++void mesh_fast_tx_flush_sta(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta) ++{ ++ struct mesh_tx_cache *cache = &sdata->u.mesh.tx_cache; ++ struct ieee80211_mesh_fast_tx *entry; ++ struct hlist_node *n; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ spin_lock_bh(&cache->walk_lock); ++ hlist_for_each_entry_safe(entry, n, &cache->walk_head, walk_list) ++ if (rcu_access_pointer(entry->mpath->next_hop) == sta) ++ mesh_fast_tx_entry_free(cache, entry); ++ spin_unlock_bh(&cache->walk_lock); ++} ++ ++void mesh_fast_tx_flush_addr(struct ieee80211_sub_if_data *sdata, ++ const u8 *addr) ++{ ++ struct mesh_tx_cache *cache = &sdata->u.mesh.tx_cache; ++ struct ieee80211_mesh_fast_tx *entry; ++ ++ cache = &sdata->u.mesh.tx_cache; ++ spin_lock_bh(&cache->walk_lock); ++ entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); ++ if (entry) ++ mesh_fast_tx_entry_free(cache, entry); ++ spin_unlock_bh(&cache->walk_lock); ++} ++ + /** + * mesh_path_add - allocate and add a new path to the mesh path table + * @dst: destination address of the path (ETH_ALEN length) +@@ -464,6 +737,8 @@ int mpp_path_add(struct ieee80211_sub_if + + if (ret) + kfree(new_mpath); ++ else ++ mesh_fast_tx_flush_addr(sdata, dst); + + sdata->u.mesh.mpp_paths_generation++; + return ret; +@@ -523,6 +798,10 @@ static void __mesh_path_del(struct mesh_ + { + hlist_del_rcu(&mpath->walk_list); + rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, mesh_rht_params); ++ if (tbl == &mpath->sdata->u.mesh.mpp_paths) ++ mesh_fast_tx_flush_addr(mpath->sdata, mpath->dst); ++ else ++ mesh_fast_tx_flush_mpath(mpath); + mesh_path_free_rcu(tbl, mpath); + } + +@@ -747,6 +1026,7 @@ void mesh_path_fix_nexthop(struct mesh_p + mpath->exp_time = 0; + mpath->flags = MESH_PATH_FIXED | MESH_PATH_SN_VALID; + mesh_path_activate(mpath); ++ mesh_fast_tx_flush_mpath(mpath); + spin_unlock_bh(&mpath->state_lock); + ewma_mesh_fail_avg_init(&next_hop->mesh->fail_avg); + /* init it at a low value - 0 start is tricky */ +@@ -758,6 +1038,7 @@ void mesh_pathtbl_init(struct ieee80211_ + { + mesh_table_init(&sdata->u.mesh.mesh_paths); + mesh_table_init(&sdata->u.mesh.mpp_paths); ++ mesh_fast_tx_init(sdata); + } + + static +@@ -785,6 +1066,7 @@ void mesh_path_expire(struct ieee80211_s + + void mesh_pathtbl_unregister(struct ieee80211_sub_if_data *sdata) + { ++ mesh_fast_tx_deinit(sdata); + mesh_table_free(&sdata->u.mesh.mesh_paths); + mesh_table_free(&sdata->u.mesh.mpp_paths); + } +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2791,6 +2791,7 @@ ieee80211_rx_mesh_data(struct ieee80211_ + if (mesh_hdr->flags & MESH_FLAGS_AE) { + struct mesh_path *mppath; + char *proxied_addr; ++ bool update = false; + + if (multicast) + proxied_addr = mesh_hdr->eaddr1; +@@ -2806,11 +2807,18 @@ ieee80211_rx_mesh_data(struct ieee80211_ + mpp_path_add(sdata, proxied_addr, eth->h_source); + } else { + spin_lock_bh(&mppath->state_lock); +- if (!ether_addr_equal(mppath->mpp, eth->h_source)) ++ if (!ether_addr_equal(mppath->mpp, eth->h_source)) { + memcpy(mppath->mpp, eth->h_source, ETH_ALEN); ++ update = true; ++ } + mppath->exp_time = jiffies; + spin_unlock_bh(&mppath->state_lock); + } ++ ++ /* flush fast xmit cache if the address path changed */ ++ if (update) ++ mesh_fast_tx_flush_addr(sdata, proxied_addr); ++ + rcu_read_unlock(); + } + +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -3022,6 +3022,9 @@ void ieee80211_check_fast_xmit(struct st + if (!ieee80211_hw_check(&local->hw, SUPPORT_FAST_XMIT)) + return; + ++ if (ieee80211_vif_is_mesh(&sdata->vif)) ++ mesh_fast_tx_flush_sta(sdata, sta); ++ + /* Locking here protects both the pointer itself, and against concurrent + * invocations winning data access races to, e.g., the key pointer that + * is used. +@@ -3403,6 +3406,9 @@ static bool ieee80211_amsdu_aggregate(st + if (sdata->vif.offload_flags & IEEE80211_OFFLOAD_ENCAP_ENABLED) + return false; + ++ if (ieee80211_vif_is_mesh(&sdata->vif)) ++ return false; ++ + if (skb_is_gso(skb)) + return false; + +@@ -3635,10 +3641,11 @@ free: + return NULL; + } + +-static void __ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata, +- struct sta_info *sta, +- struct ieee80211_fast_tx *fast_tx, +- struct sk_buff *skb, u8 tid, bool ampdu) ++void __ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, ++ struct ieee80211_fast_tx *fast_tx, ++ struct sk_buff *skb, bool ampdu, ++ const u8 *da, const u8 *sa) + { + struct ieee80211_local *local = sdata->local; + struct ieee80211_hdr *hdr = (void *)fast_tx->hdr; +@@ -3647,7 +3654,6 @@ static void __ieee80211_xmit_fast(struct + ieee80211_tx_result r; + int hw_headroom = sdata->local->hw.extra_tx_headroom; + int extra_head = fast_tx->hdr_len - (ETH_HLEN - 2); +- struct ethhdr eth; + + skb = skb_share_check(skb, GFP_ATOMIC); + if (unlikely(!skb)) +@@ -3667,11 +3673,10 @@ static void __ieee80211_xmit_fast(struct + ENCRYPT_NO))) + goto free; + +- memcpy(ð, skb->data, ETH_HLEN - 2); + hdr = skb_push(skb, extra_head); + memcpy(skb->data, fast_tx->hdr, fast_tx->hdr_len); +- memcpy(skb->data + fast_tx->da_offs, eth.h_dest, ETH_ALEN); +- memcpy(skb->data + fast_tx->sa_offs, eth.h_source, ETH_ALEN); ++ memcpy(skb->data + fast_tx->da_offs, da, ETH_ALEN); ++ memcpy(skb->data + fast_tx->sa_offs, sa, ETH_ALEN); + + info = IEEE80211_SKB_CB(skb); + memset(info, 0, sizeof(*info)); +@@ -3690,7 +3695,8 @@ static void __ieee80211_xmit_fast(struct + #endif + + if (hdr->frame_control & cpu_to_le16(IEEE80211_STYPE_QOS_DATA)) { +- tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ u8 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ + *ieee80211_get_qos_ctl(hdr) = tid; + } + +@@ -3733,6 +3739,7 @@ static bool ieee80211_xmit_fast(struct i + struct ieee80211_hdr *hdr = (void *)fast_tx->hdr; + struct tid_ampdu_tx *tid_tx = NULL; + struct sk_buff *next; ++ struct ethhdr eth; + u8 tid = IEEE80211_NUM_TIDS; + + /* control port protocol needs a lot of special handling */ +@@ -3758,6 +3765,8 @@ static bool ieee80211_xmit_fast(struct i + } + } + ++ memcpy(ð, skb->data, ETH_HLEN - 2); ++ + /* after this point (skb is modified) we cannot return false */ + skb = ieee80211_tx_skb_fixup(skb, ieee80211_sdata_netdev_features(sdata)); + if (!skb) +@@ -3765,7 +3774,8 @@ static bool ieee80211_xmit_fast(struct i + + skb_list_walk_safe(skb, skb, next) { + skb_mark_not_on_list(skb); +- __ieee80211_xmit_fast(sdata, sta, fast_tx, skb, tid, tid_tx); ++ __ieee80211_xmit_fast(sdata, sta, fast_tx, skb, tid_tx, ++ eth.h_dest, eth.h_source); + } + + return true; +@@ -4252,8 +4262,15 @@ void __ieee80211_subif_start_xmit(struct + return; + } + ++ sk_pacing_shift_update(skb->sk, sdata->local->hw.tx_sk_pacing_shift); ++ + rcu_read_lock(); + ++ if (ieee80211_vif_is_mesh(&sdata->vif) && ++ ieee80211_hw_check(&local->hw, SUPPORT_FAST_XMIT) && ++ ieee80211_mesh_xmit_fast(sdata, skb, ctrl_flags)) ++ goto out; ++ + if (ieee80211_lookup_ra_sta(sdata, skb, &sta)) + goto out_free; + +@@ -4263,8 +4280,6 @@ void __ieee80211_subif_start_xmit(struct + skb_set_queue_mapping(skb, ieee80211_select_queue(sdata, sta, skb)); + ieee80211_aggr_check(sdata, sta, skb); + +- sk_pacing_shift_update(skb->sk, sdata->local->hw.tx_sk_pacing_shift); +- + if (sta) { + struct ieee80211_fast_tx *fast_tx; + diff --git a/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch b/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch deleted file mode 100644 index 39f23f783..000000000 --- a/package/kernel/mac80211/patches/subsys/320-cfg80211-allow-grace-period-for-DFS-available-after-.patch +++ /dev/null @@ -1,149 +0,0 @@ -From: Felix Fietkau -Date: Thu, 14 Sep 2023 13:17:16 +0200 -Subject: [PATCH] cfg80211: allow grace period for DFS available after beacon - shutdown - -Fixes reconfiguring an AP on a DFS channel in non-ETSI regdomain - -Fixes: b35a51c7dd25 ("cfg80211: Make pre-CAC results valid only for ETSI domain") -Signed-off-by: Felix Fietkau ---- - ---- a/include/net/cfg80211.h -+++ b/include/net/cfg80211.h -@@ -189,6 +189,8 @@ enum ieee80211_channel_flags { - * @dfs_state: current state of this channel. Only relevant if radar is required - * on this channel. - * @dfs_state_entered: timestamp (jiffies) when the dfs state was entered. -+ * @dfs_state_last_available: timestamp (jiffies) of the last time when the -+ * channel was available. - * @dfs_cac_ms: DFS CAC time in milliseconds, this is valid for DFS channels. - * @psd: power spectral density (in dBm) - */ -@@ -206,6 +208,7 @@ struct ieee80211_channel { - int orig_mag, orig_mpwr; - enum nl80211_dfs_state dfs_state; - unsigned long dfs_state_entered; -+ unsigned long dfs_state_last_available; - unsigned int dfs_cac_ms; - s8 psd; - }; ---- a/net/wireless/ap.c -+++ b/net/wireless/ap.c -@@ -30,6 +30,9 @@ static int ___cfg80211_stop_ap(struct cf - if (!wdev->links[link_id].ap.beacon_interval) - return -ENOENT; - -+ cfg80211_update_last_available(wdev->wiphy, -+ &wdev->links[link_id].ap.chandef); -+ - err = rdev_stop_ap(rdev, dev, link_id); - if (!err) { - wdev->conn_owner_nlportid = 0; -@@ -41,9 +44,6 @@ static int ___cfg80211_stop_ap(struct cf - if (notify) - nl80211_send_ap_stopped(wdev, link_id); - -- /* Should we apply the grace period during beaconing interface -- * shutdown also? -- */ - cfg80211_sched_dfs_chan_update(rdev); - } - ---- a/net/wireless/chan.c -+++ b/net/wireless/chan.c -@@ -560,6 +560,8 @@ static void cfg80211_set_chans_dfs_state - - c->dfs_state = dfs_state; - c->dfs_state_entered = jiffies; -+ if (dfs_state == NL80211_DFS_AVAILABLE) -+ c->dfs_state_last_available = jiffies; - } - } - -@@ -1049,6 +1051,49 @@ static bool cfg80211_get_chans_dfs_avail - return true; - } - -+static void -+__cfg80211_update_last_available(struct wiphy *wiphy, -+ u32 center_freq, -+ u32 bandwidth) -+{ -+ struct ieee80211_channel *c; -+ u32 freq, start_freq, end_freq; -+ -+ start_freq = cfg80211_get_start_freq(center_freq, bandwidth); -+ end_freq = cfg80211_get_end_freq(center_freq, bandwidth); -+ -+ /* -+ * Check entire range of channels for the bandwidth. -+ * If any channel in between is disabled or has not -+ * had gone through CAC return false -+ */ -+ for (freq = start_freq; freq <= end_freq; freq += MHZ_TO_KHZ(20)) { -+ c = ieee80211_get_channel_khz(wiphy, freq); -+ if (!c) -+ return; -+ -+ c->dfs_state_last_available = jiffies; -+ } -+} -+ -+void cfg80211_update_last_available(struct wiphy *wiphy, -+ const struct cfg80211_chan_def *chandef) -+{ -+ int width; -+ -+ width = cfg80211_chandef_get_width(chandef); -+ if (width < 0) -+ return; -+ -+ __cfg80211_update_last_available(wiphy, MHZ_TO_KHZ(chandef->center_freq1), -+ width); -+ if (chandef->width != NL80211_CHAN_WIDTH_80P80) -+ return; -+ -+ __cfg80211_update_last_available(wiphy, MHZ_TO_KHZ(chandef->center_freq2), -+ width); -+} -+ - static bool cfg80211_chandef_dfs_available(struct wiphy *wiphy, - const struct cfg80211_chan_def *chandef) - { ---- a/net/wireless/core.h -+++ b/net/wireless/core.h -@@ -467,6 +467,8 @@ void cfg80211_set_dfs_state(struct wiphy - enum nl80211_dfs_state dfs_state); - - void cfg80211_dfs_channels_update_work(struct work_struct *work); -+void cfg80211_update_last_available(struct wiphy *wiphy, -+ const struct cfg80211_chan_def *chandef); - - void cfg80211_sched_dfs_chan_update(struct cfg80211_registered_device *rdev); - ---- a/net/wireless/mlme.c -+++ b/net/wireless/mlme.c -@@ -1037,6 +1037,8 @@ void cfg80211_dfs_channels_update_work(s - if (c->dfs_state == NL80211_DFS_UNAVAILABLE) { - time_dfs_update = IEEE80211_DFS_MIN_NOP_TIME_MS; - radar_event = NL80211_RADAR_NOP_FINISHED; -+ timeout = c->dfs_state_entered + -+ msecs_to_jiffies(time_dfs_update); - } else { - if (regulatory_pre_cac_allowed(wiphy) || - cfg80211_any_wiphy_oper_chan(wiphy, c)) -@@ -1044,11 +1046,10 @@ void cfg80211_dfs_channels_update_work(s - - time_dfs_update = REG_PRE_CAC_EXPIRY_GRACE_MS; - radar_event = NL80211_RADAR_PRE_CAC_EXPIRED; -+ timeout = c->dfs_state_last_available + -+ msecs_to_jiffies(time_dfs_update); - } - -- timeout = c->dfs_state_entered + -- msecs_to_jiffies(time_dfs_update); -- - if (time_after_eq(jiffies, timeout)) { - c->dfs_state = NL80211_DFS_USABLE; - c->dfs_state_entered = jiffies; diff --git a/package/kernel/mac80211/patches/subsys/320-wifi-mac80211-use-mesh-header-cache-to-speed-up-mesh.patch b/package/kernel/mac80211/patches/subsys/320-wifi-mac80211-use-mesh-header-cache-to-speed-up-mesh.patch new file mode 100644 index 000000000..28b1ff110 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/320-wifi-mac80211-use-mesh-header-cache-to-speed-up-mesh.patch @@ -0,0 +1,132 @@ +From: Felix Fietkau +Date: Thu, 16 Feb 2023 11:07:30 +0100 +Subject: [PATCH] wifi: mac80211: use mesh header cache to speed up mesh + forwarding + +Significantly reduces mesh forwarding path CPU usage and enables the +direct use of iTXQ. + +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2720,6 +2720,65 @@ ieee80211_deliver_skb(struct ieee80211_r + } + } + ++#ifdef CPTCFG_MAC80211_MESH ++static bool ++ieee80211_rx_mesh_fast_forward(struct ieee80211_sub_if_data *sdata, ++ struct sk_buff *skb, int hdrlen) ++{ ++ struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; ++ struct ieee80211_mesh_fast_tx *entry = NULL; ++ struct ieee80211s_hdr *mesh_hdr; ++ struct tid_ampdu_tx *tid_tx; ++ struct sta_info *sta; ++ struct ethhdr eth; ++ u8 tid; ++ ++ mesh_hdr = (struct ieee80211s_hdr *)(skb->data + sizeof(eth)); ++ if ((mesh_hdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6) ++ entry = mesh_fast_tx_get(sdata, mesh_hdr->eaddr1); ++ else if (!(mesh_hdr->flags & MESH_FLAGS_AE)) ++ entry = mesh_fast_tx_get(sdata, skb->data); ++ if (!entry) ++ return false; ++ ++ sta = rcu_dereference(entry->mpath->next_hop); ++ if (!sta) ++ return false; ++ ++ if (skb_linearize(skb)) ++ return false; ++ ++ tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); ++ if (tid_tx) { ++ if (!test_bit(HT_AGG_STATE_OPERATIONAL, &tid_tx->state)) ++ return false; ++ ++ if (tid_tx->timeout) ++ tid_tx->last_tx = jiffies; ++ } ++ ++ ieee80211_aggr_check(sdata, sta, skb); ++ ++ if (ieee80211_get_8023_tunnel_proto(skb->data + hdrlen, ++ &skb->protocol)) ++ hdrlen += ETH_ALEN; ++ else ++ skb->protocol = htons(skb->len - hdrlen); ++ skb_set_network_header(skb, hdrlen + 2); ++ ++ skb->dev = sdata->dev; ++ memcpy(ð, skb->data, ETH_HLEN - 2); ++ skb_pull(skb, 2); ++ __ieee80211_xmit_fast(sdata, sta, &entry->fast_tx, skb, tid_tx, ++ eth.h_dest, eth.h_source); ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_unicast); ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_frames); ++ ++ return true; ++} ++#endif ++ + static ieee80211_rx_result + ieee80211_rx_mesh_data(struct ieee80211_sub_if_data *sdata, struct sta_info *sta, + struct sk_buff *skb) +@@ -2824,6 +2883,10 @@ ieee80211_rx_mesh_data(struct ieee80211_ + + skb_set_queue_mapping(skb, ieee802_1d_to_ac[skb->priority]); + ++ if (!multicast && ++ ieee80211_rx_mesh_fast_forward(sdata, skb, mesh_hdrlen)) ++ return RX_QUEUED; ++ + ieee80211_fill_mesh_addresses(&hdr, &hdr.frame_control, + eth->h_dest, eth->h_source); + hdrlen = ieee80211_hdrlen(hdr.frame_control); +@@ -2862,6 +2925,7 @@ ieee80211_rx_mesh_data(struct ieee80211_ + info->control.flags |= IEEE80211_TX_INTCFL_NEED_TXPROCESSING; + info->control.vif = &sdata->vif; + info->control.jiffies = jiffies; ++ fwd_skb->dev = sdata->dev; + if (multicast) { + IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_mcast); + memcpy(fwd_hdr->addr2, sdata->vif.addr, ETH_ALEN); +@@ -2883,7 +2947,6 @@ ieee80211_rx_mesh_data(struct ieee80211_ + } + + IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_frames); +- fwd_skb->dev = sdata->dev; + ieee80211_add_pending_skb(local, fwd_skb); + + rx_accept: +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -2022,6 +2022,8 @@ void __ieee80211_xmit_fast(struct ieee80 + struct ieee80211_fast_tx *fast_tx, + struct sk_buff *skb, bool ampdu, + const u8 *da, const u8 *sa); ++void ieee80211_aggr_check(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, struct sk_buff *skb); + + /* HT */ + void ieee80211_apply_htcap_overrides(struct ieee80211_sub_if_data *sdata, +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -1191,10 +1191,8 @@ static bool ieee80211_tx_prep_agg(struct + return queued; + } + +-static void +-ieee80211_aggr_check(struct ieee80211_sub_if_data *sdata, +- struct sta_info *sta, +- struct sk_buff *skb) ++void ieee80211_aggr_check(struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta, struct sk_buff *skb) + { + struct rate_control_ref *ref = sdata->local->rate_ctrl; + u16 tid; diff --git a/package/kernel/mac80211/patches/subsys/321-mac80211-fix-mesh-forwarding.patch b/package/kernel/mac80211/patches/subsys/321-mac80211-fix-mesh-forwarding.patch new file mode 100644 index 000000000..e2b268ae4 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/321-mac80211-fix-mesh-forwarding.patch @@ -0,0 +1,32 @@ +From: Felix Fietkau +Date: Mon, 20 Feb 2023 12:50:50 +0100 +Subject: [PATCH] mac80211: fix mesh forwarding + +Linearize packets (needed for forwarding A-MSDU subframes). +Fix network header offset to fix flow dissector (and fair queueing). + +Fixes: 986e43b19ae9 ("wifi: mac80211: fix receiving A-MSDU frames on mesh interfaces") +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2904,6 +2904,9 @@ ieee80211_rx_mesh_data(struct ieee80211_ + + if (skb_cow_head(fwd_skb, hdrlen - sizeof(struct ethhdr))) + return RX_DROP_UNUSABLE; ++ ++ if (skb_linearize(fwd_skb)) ++ return RX_DROP_UNUSABLE; + } + + fwd_hdr = skb_push(fwd_skb, hdrlen - sizeof(struct ethhdr)); +@@ -2918,7 +2921,7 @@ ieee80211_rx_mesh_data(struct ieee80211_ + hdrlen += ETH_ALEN; + else + fwd_skb->protocol = htons(fwd_skb->len - hdrlen); +- skb_set_network_header(fwd_skb, hdrlen); ++ skb_set_network_header(fwd_skb, hdrlen + 2); + + info = IEEE80211_SKB_CB(fwd_skb); + memset(info, 0, sizeof(*info)); diff --git a/package/kernel/mac80211/patches/subsys/322-wifi-mac80211-fix-mesh-path-discovery-based-on-unica.patch b/package/kernel/mac80211/patches/subsys/322-wifi-mac80211-fix-mesh-path-discovery-based-on-unica.patch new file mode 100644 index 000000000..292a89ef9 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/322-wifi-mac80211-fix-mesh-path-discovery-based-on-unica.patch @@ -0,0 +1,52 @@ +From: Felix Fietkau +Date: Sun, 26 Feb 2023 20:30:20 +0100 +Subject: [PATCH] wifi: mac80211: fix mesh path discovery based on unicast + packets + +If a packet has reached its intended destination, it was bumped to the code +that accepts it, without first checking if a mesh_path needs to be created +based on the discovered source. +Fix this by moving the destination address check further down + +Fixes: 986e43b19ae9 ("wifi: mac80211: fix receiving A-MSDU frames on mesh interfaces") +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2824,17 +2824,6 @@ ieee80211_rx_mesh_data(struct ieee80211_ + mesh_rmc_check(sdata, eth->h_source, mesh_hdr)) + return RX_DROP_MONITOR; + +- /* Frame has reached destination. Don't forward */ +- if (ether_addr_equal(sdata->vif.addr, eth->h_dest)) +- goto rx_accept; +- +- if (!ifmsh->mshcfg.dot11MeshForwarding) { +- if (is_multicast_ether_addr(eth->h_dest)) +- goto rx_accept; +- +- return RX_DROP_MONITOR; +- } +- + /* forward packet */ + if (sdata->crypto_tx_tailroom_needed_cnt) + tailroom = IEEE80211_ENCRYPT_TAILROOM; +@@ -2881,6 +2870,17 @@ ieee80211_rx_mesh_data(struct ieee80211_ + rcu_read_unlock(); + } + ++ /* Frame has reached destination. Don't forward */ ++ if (ether_addr_equal(sdata->vif.addr, eth->h_dest)) ++ goto rx_accept; ++ ++ if (!ifmsh->mshcfg.dot11MeshForwarding) { ++ if (is_multicast_ether_addr(eth->h_dest)) ++ goto rx_accept; ++ ++ return RX_DROP_MONITOR; ++ } ++ + skb_set_queue_mapping(skb, ieee802_1d_to_ac[skb->priority]); + + if (!multicast && diff --git a/package/kernel/mac80211/patches/subsys/323-v6.3-wifi-mac80211-Add-VHT-MU-MIMO-related-flags-in-ieee8.patch b/package/kernel/mac80211/patches/subsys/323-v6.3-wifi-mac80211-Add-VHT-MU-MIMO-related-flags-in-ieee8.patch new file mode 100644 index 000000000..e23dc4d22 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/323-v6.3-wifi-mac80211-Add-VHT-MU-MIMO-related-flags-in-ieee8.patch @@ -0,0 +1,68 @@ +From: Muna Sinada +Date: Wed, 5 Oct 2022 14:54:45 -0700 +Subject: [PATCH] wifi: mac80211: Add VHT MU-MIMO related flags in + ieee80211_bss_conf + +Adding flags for SU Beamformer, SU Beamformee, MU Beamformer and +MU Beamformee for VHT. This is utilized to pass MU-MIMO +configurations from user space to driver in AP mode. + +Signed-off-by: Muna Sinada +Link: https://lore.kernel.org/r/1665006886-23874-1-git-send-email-quic_msinada@quicinc.com +[fixed indentation, removed redundant !!] +Signed-off-by: Johannes Berg +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -653,6 +653,14 @@ struct ieee80211_fils_discovery { + * write-protected by sdata_lock and local->mtx so holding either is fine + * for read access. + * @color_change_color: the bss color that will be used after the change. ++ * @vht_su_beamformer: in AP mode, does this BSS support operation as an VHT SU ++ * beamformer ++ * @vht_su_beamformee: in AP mode, does this BSS support operation as an VHT SU ++ * beamformee ++ * @vht_mu_beamformer: in AP mode, does this BSS support operation as an VHT MU ++ * beamformer ++ * @vht_mu_beamformee: in AP mode, does this BSS support operation as an VHT MU ++ * beamformee + */ + struct ieee80211_bss_conf { + const u8 *bssid; +@@ -726,6 +734,11 @@ struct ieee80211_bss_conf { + + bool color_change_active; + u8 color_change_color; ++ ++ bool vht_su_beamformer; ++ bool vht_su_beamformee; ++ bool vht_mu_beamformer; ++ bool vht_mu_beamformee; + }; + + /** +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -1252,6 +1252,21 @@ static int ieee80211_start_ap(struct wip + prev_beacon_int = link_conf->beacon_int; + link_conf->beacon_int = params->beacon_interval; + ++ if (params->vht_cap) { ++ link_conf->vht_su_beamformer = ++ params->vht_cap->vht_cap_info & ++ cpu_to_le32(IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE); ++ link_conf->vht_su_beamformee = ++ params->vht_cap->vht_cap_info & ++ cpu_to_le32(IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE); ++ link_conf->vht_mu_beamformer = ++ params->vht_cap->vht_cap_info & ++ cpu_to_le32(IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); ++ link_conf->vht_mu_beamformee = ++ params->vht_cap->vht_cap_info & ++ cpu_to_le32(IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE); ++ } ++ + if (params->he_cap && params->he_oper) { + link_conf->he_support = true; + link_conf->htc_trig_based_pkt_ext = diff --git a/package/kernel/mac80211/patches/subsys/324-v6.3-wifi-mac80211-Add-HE-MU-MIMO-related-flags-in-ieee80.patch b/package/kernel/mac80211/patches/subsys/324-v6.3-wifi-mac80211-Add-HE-MU-MIMO-related-flags-in-ieee80.patch new file mode 100644 index 000000000..f843dba12 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/324-v6.3-wifi-mac80211-Add-HE-MU-MIMO-related-flags-in-ieee80.patch @@ -0,0 +1,68 @@ +From: Muna Sinada +Date: Wed, 5 Oct 2022 14:54:46 -0700 +Subject: [PATCH] wifi: mac80211: Add HE MU-MIMO related flags in + ieee80211_bss_conf + +Adding flags for SU Beamformer, SU Beamformee, MU Beamformer and Full +Bandwidth UL MU-MIMO for HE. This is utilized to pass MU-MIMO +configurations from user space to driver in AP mode. + +Signed-off-by: Muna Sinada +Link: https://lore.kernel.org/r/1665006886-23874-2-git-send-email-quic_msinada@quicinc.com +[fixed indentation, removed redundant !!] +Signed-off-by: Johannes Berg +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -661,6 +661,15 @@ struct ieee80211_fils_discovery { + * beamformer + * @vht_mu_beamformee: in AP mode, does this BSS support operation as an VHT MU + * beamformee ++ * @he_su_beamformer: in AP-mode, does this BSS support operation as an HE SU ++ * beamformer ++ * @he_su_beamformee: in AP-mode, does this BSS support operation as an HE SU ++ * beamformee ++ * @he_mu_beamformer: in AP-mode, does this BSS support operation as an HE MU ++ * beamformer ++ * @he_full_ul_mumimo: does this BSS support the reception (AP) or transmission ++ * (non-AP STA) of an HE TB PPDU on an RU that spans the entire PPDU ++ * bandwidth + */ + struct ieee80211_bss_conf { + const u8 *bssid; +@@ -739,6 +748,10 @@ struct ieee80211_bss_conf { + bool vht_su_beamformee; + bool vht_mu_beamformer; + bool vht_mu_beamformee; ++ bool he_su_beamformer; ++ bool he_su_beamformee; ++ bool he_mu_beamformer; ++ bool he_full_ul_mumimo; + }; + + /** +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -1281,6 +1281,21 @@ static int ieee80211_start_ap(struct wip + changed |= BSS_CHANGED_HE_BSS_COLOR; + } + ++ if (params->he_cap) { ++ link_conf->he_su_beamformer = ++ params->he_cap->phy_cap_info[3] & ++ IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; ++ link_conf->he_su_beamformee = ++ params->he_cap->phy_cap_info[4] & ++ IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; ++ link_conf->he_mu_beamformer = ++ params->he_cap->phy_cap_info[4] & ++ IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; ++ link_conf->he_full_ul_mumimo = ++ params->he_cap->phy_cap_info[2] & ++ IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; ++ } ++ + if (sdata->vif.type == NL80211_IFTYPE_AP && + params->mbssid_config.tx_wdev) { + err = ieee80211_set_ap_mbssid_options(sdata, diff --git a/package/kernel/mac80211/patches/subsys/325-wifi-mac80211-introduce-ieee80211_refresh_tx_agg_ses.patch b/package/kernel/mac80211/patches/subsys/325-wifi-mac80211-introduce-ieee80211_refresh_tx_agg_ses.patch new file mode 100644 index 000000000..1be5fcfbf --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/325-wifi-mac80211-introduce-ieee80211_refresh_tx_agg_ses.patch @@ -0,0 +1,60 @@ +From: Ryder Lee +Date: Sat, 18 Feb 2023 01:50:05 +0800 +Subject: [PATCH] wifi: mac80211: introduce + ieee80211_refresh_tx_agg_session_timer() + +This allows low level drivers to refresh the tx agg session timer, based on +querying stats from the firmware usually. Especially for some mt76 devices +support .net_fill_forward_path would bypass mac80211, which leads to tx BA +session timeout for certain clients. + +Signed-off-by: Ryder Lee +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -5964,6 +5964,18 @@ void ieee80211_queue_delayed_work(struct + unsigned long delay); + + /** ++ * ieee80211_refresh_tx_agg_session_timer - Refresh a tx agg session timer. ++ * @sta: the station for which to start a BA session ++ * @tid: the TID to BA on. ++ * ++ * This function allows low level driver to refresh tx agg session timer ++ * to maintain BA session, the session level will still be managed by the ++ * mac80211. ++ */ ++void ieee80211_refresh_tx_agg_session_timer(struct ieee80211_sta *sta, ++ u16 tid); ++ ++/** + * ieee80211_start_tx_ba_session - Start a tx Block Ack session. + * @sta: the station for which to start a BA session + * @tid: the TID to BA on. +--- a/net/mac80211/agg-tx.c ++++ b/net/mac80211/agg-tx.c +@@ -554,6 +554,23 @@ void ieee80211_tx_ba_session_handle_star + ieee80211_send_addba_with_timeout(sta, tid_tx); + } + ++void ieee80211_refresh_tx_agg_session_timer(struct ieee80211_sta *pubsta, ++ u16 tid) ++{ ++ struct sta_info *sta = container_of(pubsta, struct sta_info, sta); ++ struct tid_ampdu_tx *tid_tx; ++ ++ if (WARN_ON_ONCE(tid >= IEEE80211_NUM_TIDS)) ++ return; ++ ++ tid_tx = rcu_dereference(sta->ampdu_mlme.tid_tx[tid]); ++ if (!tid_tx) ++ return; ++ ++ tid_tx->last_tx = jiffies; ++} ++EXPORT_SYMBOL(ieee80211_refresh_tx_agg_session_timer); ++ + /* + * After accepting the AddBA Response we activated a timer, + * resetting it after each frame that we send. diff --git a/package/kernel/mac80211/patches/subsys/326-wifi-mac80211-add-mesh-fast-rx-support.patch b/package/kernel/mac80211/patches/subsys/326-wifi-mac80211-add-mesh-fast-rx-support.patch new file mode 100644 index 000000000..11f39c2d1 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/326-wifi-mac80211-add-mesh-fast-rx-support.patch @@ -0,0 +1,77 @@ +From: Felix Fietkau +Date: Thu, 2 Mar 2023 13:52:29 +0100 +Subject: [PATCH] wifi: mac80211: add mesh fast-rx support + +This helps bring down rx CPU usage by avoiding calls to the rx handlers in +the slow path. Supports forwarding and local rx, including A-MSDU. + +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -4564,6 +4564,12 @@ void ieee80211_check_fast_rx(struct sta_ + } + + break; ++ case NL80211_IFTYPE_MESH_POINT: ++ fastrx.expected_ds_bits = cpu_to_le16(IEEE80211_FCTL_FROMDS | ++ IEEE80211_FCTL_TODS); ++ fastrx.da_offs = offsetof(struct ieee80211_hdr, addr3); ++ fastrx.sa_offs = offsetof(struct ieee80211_hdr, addr4); ++ break; + default: + goto clear; + } +@@ -4772,6 +4778,7 @@ static bool ieee80211_invoke_fast_rx(str + struct sk_buff *skb = rx->skb; + struct ieee80211_hdr *hdr = (void *)skb->data; + struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); ++ static ieee80211_rx_result res; + int orig_len = skb->len; + int hdrlen = ieee80211_hdrlen(hdr->frame_control); + int snap_offs = hdrlen; +@@ -4833,7 +4840,8 @@ static bool ieee80211_invoke_fast_rx(str + snap_offs += IEEE80211_CCMP_HDR_LEN; + } + +- if (!(status->rx_flags & IEEE80211_RX_AMSDU)) { ++ if (!ieee80211_vif_is_mesh(&rx->sdata->vif) && ++ !(status->rx_flags & IEEE80211_RX_AMSDU)) { + if (!pskb_may_pull(skb, snap_offs + sizeof(*payload))) + return false; + +@@ -4872,13 +4880,29 @@ static bool ieee80211_invoke_fast_rx(str + /* do the header conversion - first grab the addresses */ + ether_addr_copy(addrs.da, skb->data + fast_rx->da_offs); + ether_addr_copy(addrs.sa, skb->data + fast_rx->sa_offs); +- skb_postpull_rcsum(skb, skb->data + snap_offs, +- sizeof(rfc1042_header) + 2); +- /* remove the SNAP but leave the ethertype */ +- skb_pull(skb, snap_offs + sizeof(rfc1042_header)); ++ if (ieee80211_vif_is_mesh(&rx->sdata->vif)) { ++ skb_pull(skb, snap_offs - 2); ++ put_unaligned_be16(skb->len - 2, skb->data); ++ } else { ++ skb_postpull_rcsum(skb, skb->data + snap_offs, ++ sizeof(rfc1042_header) + 2); ++ ++ /* remove the SNAP but leave the ethertype */ ++ skb_pull(skb, snap_offs + sizeof(rfc1042_header)); ++ } + /* push the addresses in front */ + memcpy(skb_push(skb, sizeof(addrs)), &addrs, sizeof(addrs)); + ++ res = ieee80211_rx_mesh_data(rx->sdata, rx->sta, rx->skb); ++ switch (res) { ++ case RX_QUEUED: ++ return true; ++ case RX_CONTINUE: ++ break; ++ default: ++ goto drop; ++ } ++ + ieee80211_rx_8023(rx, fast_rx, orig_len); + + return true; diff --git a/package/kernel/mac80211/patches/subsys/327-wifi-mac80211-add-support-for-letting-drivers-regist.patch b/package/kernel/mac80211/patches/subsys/327-wifi-mac80211-add-support-for-letting-drivers-regist.patch new file mode 100644 index 000000000..ac290b536 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/327-wifi-mac80211-add-support-for-letting-drivers-regist.patch @@ -0,0 +1,149 @@ +From: Felix Fietkau +Date: Mon, 20 Mar 2023 14:28:08 +0100 +Subject: [PATCH] wifi: mac80211: add support for letting drivers register tc + offload support + +On newer MediaTek SoCs (e.g. MT7986), WLAN->WLAN or WLAN->Ethernet flows can +be offloaded by the SoC. In order to support that, the .ndo_setup_tc op is +needed. + +Signed-off-by: Felix Fietkau +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -4192,6 +4192,10 @@ struct ieee80211_prep_tx_info { + * Note that a sta can also be inserted or removed with valid links, + * i.e. passed to @sta_add/@sta_state with sta->valid_links not zero. + * In fact, cannot change from having valid_links and not having them. ++ * @net_setup_tc: Called from .ndo_setup_tc in order to prepare hardware ++ * flow offloading for flows originating from the vif. ++ * Note that the driver must not assume that the vif driver_data is valid ++ * at this point, since the callback can be called during netdev teardown. + */ + struct ieee80211_ops { + void (*tx)(struct ieee80211_hw *hw, +@@ -4547,6 +4551,11 @@ struct ieee80211_ops { + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + u16 old_links, u16 new_links); ++ int (*net_setup_tc)(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct net_device *dev, ++ enum tc_setup_type type, ++ void *type_data); + }; + + /** +--- a/net/mac80211/driver-ops.h ++++ b/net/mac80211/driver-ops.h +@@ -1470,6 +1470,23 @@ static inline int drv_net_fill_forward_p + return ret; + } + ++static inline int drv_net_setup_tc(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ struct net_device *dev, ++ enum tc_setup_type type, void *type_data) ++{ ++ int ret = -EOPNOTSUPP; ++ ++ sdata = get_bss_sdata(sdata); ++ trace_drv_net_setup_tc(local, sdata, type); ++ if (local->ops->net_setup_tc) ++ ret = local->ops->net_setup_tc(&local->hw, &sdata->vif, dev, ++ type, type_data); ++ trace_drv_return_int(local, ret); ++ ++ return ret; ++} ++ + int drv_change_vif_links(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, + u16 old_links, u16 new_links, +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -1939,7 +1939,8 @@ void ieee80211_color_collision_detection + /* interface handling */ + #define MAC80211_SUPPORTED_FEATURES_TX (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | \ + NETIF_F_HW_CSUM | NETIF_F_SG | \ +- NETIF_F_HIGHDMA | NETIF_F_GSO_SOFTWARE) ++ NETIF_F_HIGHDMA | NETIF_F_GSO_SOFTWARE | \ ++ NETIF_F_HW_TC) + #define MAC80211_SUPPORTED_FEATURES_RX (NETIF_F_RXCSUM) + #define MAC80211_SUPPORTED_FEATURES (MAC80211_SUPPORTED_FEATURES_TX | \ + MAC80211_SUPPORTED_FEATURES_RX) +--- a/net/mac80211/iface.c ++++ b/net/mac80211/iface.c +@@ -813,6 +813,21 @@ ieee80211_get_stats64(struct net_device + dev_fetch_sw_netstats(stats, dev->tstats); + } + ++static int ieee80211_netdev_setup_tc(struct net_device *dev, ++ enum tc_setup_type type, void *type_data) ++{ ++ struct ieee80211_sub_if_data *sdata; ++ struct ieee80211_local *local; ++ ++ sdata = IEEE80211_DEV_TO_SUB_IF(dev); ++ local = sdata->local; ++ ++ if (!local->ops->net_setup_tc) ++ return -EOPNOTSUPP; ++ ++ return drv_net_setup_tc(local, sdata, dev, type, type_data); ++} ++ + static const struct net_device_ops ieee80211_dataif_ops = { + .ndo_open = ieee80211_open, + .ndo_stop = ieee80211_stop, +@@ -821,6 +836,7 @@ static const struct net_device_ops ieee8 + .ndo_set_rx_mode = ieee80211_set_multicast_list, + .ndo_set_mac_address = ieee80211_change_mac, + .ndo_get_stats64 = ieee80211_get_stats64, ++ .ndo_setup_tc = ieee80211_netdev_setup_tc, + }; + + static u16 ieee80211_monitor_select_queue(struct net_device *dev, +@@ -929,6 +945,7 @@ static const struct net_device_ops ieee8 + .ndo_set_mac_address = ieee80211_change_mac, + .ndo_get_stats64 = ieee80211_get_stats64, + .ndo_fill_forward_path = ieee80211_netdev_fill_forward_path, ++ .ndo_setup_tc = ieee80211_netdev_setup_tc, + }; + + static bool ieee80211_iftype_supports_hdr_offload(enum nl80211_iftype iftype) +--- a/net/mac80211/trace.h ++++ b/net/mac80211/trace.h +@@ -2478,6 +2478,31 @@ DEFINE_EVENT(sta_event, drv_net_fill_for + TP_ARGS(local, sdata, sta) + ); + ++TRACE_EVENT(drv_net_setup_tc, ++ TP_PROTO(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ u8 type), ++ ++ TP_ARGS(local, sdata, type), ++ ++ TP_STRUCT__entry( ++ LOCAL_ENTRY ++ VIF_ENTRY ++ __field(u8, type) ++ ), ++ ++ TP_fast_assign( ++ LOCAL_ASSIGN; ++ VIF_ASSIGN; ++ __entry->type = type; ++ ), ++ ++ TP_printk( ++ LOCAL_PR_FMT VIF_PR_FMT " type:%d\n", ++ LOCAL_PR_ARG, VIF_PR_ARG, __entry->type ++ ) ++); ++ + TRACE_EVENT(drv_change_vif_links, + TP_PROTO(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, diff --git a/package/kernel/mac80211/patches/subsys/329-wifi-mac80211-fix-receiving-mesh-packets-in-forwardi.patch b/package/kernel/mac80211/patches/subsys/329-wifi-mac80211-fix-receiving-mesh-packets-in-forwardi.patch new file mode 100644 index 000000000..6882694da --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/329-wifi-mac80211-fix-receiving-mesh-packets-in-forwardi.patch @@ -0,0 +1,50 @@ +From: Felix Fietkau +Date: Sun, 26 Mar 2023 17:11:34 +0200 +Subject: [PATCH] wifi: mac80211: fix receiving mesh packets in forwarding=0 + networks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +When forwarding is set to 0, frames are typically sent with ttl=1. +Move the ttl decrement check below the check for local receive in order to +fix packet drops. + +Reported-by: Thomas Hühn +Reported-by: Nick Hainke +Fixes: 986e43b19ae9 ("wifi: mac80211: fix receiving A-MSDU frames on mesh interfaces") +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2828,14 +2828,6 @@ ieee80211_rx_mesh_data(struct ieee80211_ + if (sdata->crypto_tx_tailroom_needed_cnt) + tailroom = IEEE80211_ENCRYPT_TAILROOM; + +- if (!--mesh_hdr->ttl) { +- if (multicast) +- goto rx_accept; +- +- IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, dropped_frames_ttl); +- return RX_DROP_MONITOR; +- } +- + if (mesh_hdr->flags & MESH_FLAGS_AE) { + struct mesh_path *mppath; + char *proxied_addr; +@@ -2874,6 +2866,14 @@ ieee80211_rx_mesh_data(struct ieee80211_ + if (ether_addr_equal(sdata->vif.addr, eth->h_dest)) + goto rx_accept; + ++ if (!--mesh_hdr->ttl) { ++ if (multicast) ++ goto rx_accept; ++ ++ IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, dropped_frames_ttl); ++ return RX_DROP_MONITOR; ++ } ++ + if (!ifmsh->mshcfg.dot11MeshForwarding) { + if (is_multicast_ether_addr(eth->h_dest)) + goto rx_accept; diff --git a/package/kernel/mac80211/patches/subsys/330-mac80211-add-AQL-support-for-broadcast-packets.patch b/package/kernel/mac80211/patches/subsys/330-mac80211-add-AQL-support-for-broadcast-packets.patch deleted file mode 100644 index d822e4535..000000000 --- a/package/kernel/mac80211/patches/subsys/330-mac80211-add-AQL-support-for-broadcast-packets.patch +++ /dev/null @@ -1,293 +0,0 @@ -From: Felix Fietkau -Date: Fri, 9 Feb 2024 19:43:40 +0100 -Subject: [PATCH] mac80211: add AQL support for broadcast packets - -Excessive broadcast traffic with little competing unicast traffic can easily -flood hardware queues, leading to throughput issues. Additionally, filling -the hardware queues with too many packets breaks FQ for broadcast data. -Fix this by enabling AQL for broadcast packets. - -Signed-off-by: Felix Fietkau ---- - ---- a/include/net/cfg80211.h -+++ b/include/net/cfg80211.h -@@ -3416,6 +3416,7 @@ enum wiphy_params_flags { - /* The per TXQ device queue limit in airtime */ - #define IEEE80211_DEFAULT_AQL_TXQ_LIMIT_L 5000 - #define IEEE80211_DEFAULT_AQL_TXQ_LIMIT_H 12000 -+#define IEEE80211_DEFAULT_AQL_TXQ_LIMIT_BC 50000 - - /* The per interface airtime threshold to switch to lower queue limit */ - #define IEEE80211_AQL_THRESHOLD 24000 ---- a/net/mac80211/debugfs.c -+++ b/net/mac80211/debugfs.c -@@ -215,11 +215,13 @@ static ssize_t aql_pending_read(struct f - "VI %u us\n" - "BE %u us\n" - "BK %u us\n" -+ "BC/MC %u us\n" - "total %u us\n", - atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_VO]), - atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_VI]), - atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_BE]), - atomic_read(&local->aql_ac_pending_airtime[IEEE80211_AC_BK]), -+ atomic_read(&local->aql_bc_pending_airtime), - atomic_read(&local->aql_total_pending_airtime)); - return simple_read_from_buffer(user_buf, count, ppos, - buf, len); -@@ -245,7 +247,8 @@ static ssize_t aql_txq_limit_read(struct - "VO %u %u\n" - "VI %u %u\n" - "BE %u %u\n" -- "BK %u %u\n", -+ "BK %u %u\n" -+ "BC/MC %u\n", - local->aql_txq_limit_low[IEEE80211_AC_VO], - local->aql_txq_limit_high[IEEE80211_AC_VO], - local->aql_txq_limit_low[IEEE80211_AC_VI], -@@ -253,7 +256,8 @@ static ssize_t aql_txq_limit_read(struct - local->aql_txq_limit_low[IEEE80211_AC_BE], - local->aql_txq_limit_high[IEEE80211_AC_BE], - local->aql_txq_limit_low[IEEE80211_AC_BK], -- local->aql_txq_limit_high[IEEE80211_AC_BK]); -+ local->aql_txq_limit_high[IEEE80211_AC_BK], -+ local->aql_txq_limit_bc); - return simple_read_from_buffer(user_buf, count, ppos, - buf, len); - } -@@ -279,6 +283,11 @@ static ssize_t aql_txq_limit_write(struc - else - buf[count] = '\0'; - -+ if (sscanf(buf, "mcast %u", &q_limit_low) == 1) { -+ local->aql_txq_limit_bc = q_limit_low; -+ return count; -+ } -+ - if (sscanf(buf, "%u %u %u", &ac, &q_limit_low, &q_limit_high) != 3) - return -EINVAL; - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -1338,10 +1338,12 @@ struct ieee80211_local { - spinlock_t handle_wake_tx_queue_lock; - - u16 airtime_flags; -+ u32 aql_txq_limit_bc; - u32 aql_txq_limit_low[IEEE80211_NUM_ACS]; - u32 aql_txq_limit_high[IEEE80211_NUM_ACS]; - u32 aql_threshold; - atomic_t aql_total_pending_airtime; -+ atomic_t aql_bc_pending_airtime; - atomic_t aql_ac_pending_airtime[IEEE80211_NUM_ACS]; - - const struct ieee80211_ops *ops; ---- a/net/mac80211/main.c -+++ b/net/mac80211/main.c -@@ -944,6 +944,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_ - spin_lock_init(&local->rx_path_lock); - spin_lock_init(&local->queue_stop_reason_lock); - -+ local->aql_txq_limit_bc = IEEE80211_DEFAULT_AQL_TXQ_LIMIT_BC; - for (i = 0; i < IEEE80211_NUM_ACS; i++) { - INIT_LIST_HEAD(&local->active_txqs[i]); - spin_lock_init(&local->active_txq_lock[i]); ---- a/net/mac80211/sta_info.c -+++ b/net/mac80211/sta_info.c -@@ -2357,13 +2357,28 @@ EXPORT_SYMBOL(ieee80211_sta_recalc_aggre - - void ieee80211_sta_update_pending_airtime(struct ieee80211_local *local, - struct sta_info *sta, u8 ac, -- u16 tx_airtime, bool tx_completed) -+ u16 tx_airtime, bool tx_completed, -+ bool mcast) - { - int tx_pending; - - if (!wiphy_ext_feature_isset(local->hw.wiphy, NL80211_EXT_FEATURE_AQL)) - return; - -+ if (mcast) { -+ if (!tx_completed) { -+ atomic_add(tx_airtime, &local->aql_bc_pending_airtime); -+ return; -+ } -+ -+ tx_pending = atomic_sub_return(tx_airtime, -+ &local->aql_bc_pending_airtime); -+ if (tx_pending < 0) -+ atomic_cmpxchg(&local->aql_bc_pending_airtime, -+ tx_pending, 0); -+ return; -+ } -+ - if (!tx_completed) { - if (sta) - atomic_add(tx_airtime, ---- a/net/mac80211/tx.c -+++ b/net/mac80211/tx.c -@@ -2554,7 +2554,7 @@ static u16 ieee80211_store_ack_skb(struc - - spin_lock_irqsave(&local->ack_status_lock, flags); - id = idr_alloc(&local->ack_status_frames, ack_skb, -- 1, 0x2000, GFP_ATOMIC); -+ 1, 0x1000, GFP_ATOMIC); - spin_unlock_irqrestore(&local->ack_status_lock, flags); - - if (id >= 0) { -@@ -3983,20 +3983,20 @@ begin: - encap_out: - info->control.vif = vif; - -- if (tx.sta && -- wiphy_ext_feature_isset(local->hw.wiphy, NL80211_EXT_FEATURE_AQL)) { -- bool ampdu = txq->ac != IEEE80211_AC_VO; -+ if (wiphy_ext_feature_isset(local->hw.wiphy, NL80211_EXT_FEATURE_AQL)) { -+ bool ampdu = txq->sta && txq->ac != IEEE80211_AC_VO; - u32 airtime; - - airtime = ieee80211_calc_expected_tx_airtime(hw, vif, txq->sta, - skb->len, ampdu); -- if (airtime) { -- airtime = ieee80211_info_set_tx_time_est(info, airtime); -- ieee80211_sta_update_pending_airtime(local, tx.sta, -- txq->ac, -- airtime, -- false); -- } -+ if (!airtime) -+ return skb; -+ -+ airtime = ieee80211_info_set_tx_time_est(info, airtime); -+ info->tx_time_mc = !tx.sta; -+ ieee80211_sta_update_pending_airtime(local, tx.sta, txq->ac, -+ airtime, false, -+ info->tx_time_mc); - } - - return skb; -@@ -4048,6 +4048,7 @@ struct ieee80211_txq *ieee80211_next_txq - struct ieee80211_txq *ret = NULL; - struct txq_info *txqi = NULL, *head = NULL; - bool found_eligible_txq = false; -+ bool aql_check; - - spin_lock_bh(&local->active_txq_lock[ac]); - -@@ -4071,26 +4072,26 @@ struct ieee80211_txq *ieee80211_next_txq - if (!head) - head = txqi; - -+ aql_check = ieee80211_txq_airtime_check(hw, &txqi->txq); -+ if (aql_check) -+ found_eligible_txq = true; -+ - if (txqi->txq.sta) { - struct sta_info *sta = container_of(txqi->txq.sta, - struct sta_info, sta); -- bool aql_check = ieee80211_txq_airtime_check(hw, &txqi->txq); -- s32 deficit = ieee80211_sta_deficit(sta, txqi->txq.ac); -- -- if (aql_check) -- found_eligible_txq = true; -- -- if (deficit < 0) -+ if (ieee80211_sta_deficit(sta, txqi->txq.ac) < 0) { - sta->airtime[txqi->txq.ac].deficit += - sta->airtime_weight << AIRTIME_QUANTUM_SHIFT; -- -- if (deficit < 0 || !aql_check) { -- list_move_tail(&txqi->schedule_order, -- &local->active_txqs[txqi->txq.ac]); -- goto begin; -+ aql_check = false; - } - } - -+ if (!aql_check) { -+ list_move_tail(&txqi->schedule_order, -+ &local->active_txqs[txqi->txq.ac]); -+ goto begin; -+ } -+ - if (txqi->schedule_round == local->schedule_round[ac]) - goto out; - -@@ -4155,7 +4156,8 @@ bool ieee80211_txq_airtime_check(struct - return true; - - if (!txq->sta) -- return true; -+ return atomic_read(&local->aql_bc_pending_airtime) < -+ local->aql_txq_limit_bc; - - if (unlikely(txq->tid == IEEE80211_NUM_TIDS)) - return true; -@@ -4204,15 +4206,15 @@ bool ieee80211_txq_may_transmit(struct i - - spin_lock_bh(&local->active_txq_lock[ac]); - -- if (!txqi->txq.sta) -- goto out; -- - if (list_empty(&txqi->schedule_order)) - goto out; - - if (!ieee80211_txq_schedule_airtime_check(local, ac)) - goto out; - -+ if (!txqi->txq.sta) -+ goto out; -+ - list_for_each_entry_safe(iter, tmp, &local->active_txqs[ac], - schedule_order) { - if (iter == txqi) ---- a/include/net/mac80211.h -+++ b/include/net/mac80211.h -@@ -1180,8 +1180,8 @@ struct ieee80211_tx_info { - status_data_idr:1, - status_data:13, - hw_queue:4, -+ tx_time_mc:1, - tx_time_est:10; -- /* 1 free bit */ - - union { - struct { ---- a/net/mac80211/sta_info.h -+++ b/net/mac80211/sta_info.h -@@ -147,7 +147,8 @@ struct airtime_info { - - void ieee80211_sta_update_pending_airtime(struct ieee80211_local *local, - struct sta_info *sta, u8 ac, -- u16 tx_airtime, bool tx_completed); -+ u16 tx_airtime, bool tx_completed, -+ bool mcast); - - struct sta_info; - ---- a/net/mac80211/status.c -+++ b/net/mac80211/status.c -@@ -717,7 +717,7 @@ static void ieee80211_report_used_skb(st - ieee80211_sta_update_pending_airtime(local, sta, - skb_get_queue_mapping(skb), - tx_time_est, -- true); -+ true, info->tx_time_mc); - rcu_read_unlock(); - } - -@@ -1138,10 +1138,11 @@ void ieee80211_tx_status_ext(struct ieee - /* Do this here to avoid the expensive lookup of the sta - * in ieee80211_report_used_skb(). - */ -+ bool mcast = IEEE80211_SKB_CB(skb)->tx_time_mc; - ieee80211_sta_update_pending_airtime(local, sta, - skb_get_queue_mapping(skb), - tx_time_est, -- true); -+ true, mcast); - ieee80211_info_set_tx_time_est(IEEE80211_SKB_CB(skb), 0); - } - diff --git a/package/kernel/mac80211/patches/subsys/330-wifi-ieee80211-correctly-mark-FTM-frames-non-buffera.patch b/package/kernel/mac80211/patches/subsys/330-wifi-ieee80211-correctly-mark-FTM-frames-non-buffera.patch new file mode 100644 index 000000000..079dd2a86 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/330-wifi-ieee80211-correctly-mark-FTM-frames-non-buffera.patch @@ -0,0 +1,134 @@ +From: Johannes Berg +Date: Wed, 29 Mar 2023 16:46:26 +0200 +Subject: [PATCH] wifi: ieee80211: correctly mark FTM frames non-bufferable + +The checks of whether or not a frame is bufferable were not +taking into account that some action frames aren't, such as +FTM. Check this, which requires some changes to the function +ieee80211_is_bufferable_mmpdu() since we need the whole skb +for the checks now. + +Signed-off-by: Johannes Berg +Reviewed-by: Greenman, Gregory +Reviewed-by: Peer, Ilan +--- + +--- a/drivers/net/wireless/intel/iwlwifi/mvm/tx.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/tx.c +@@ -601,8 +601,9 @@ static void iwl_mvm_skb_prepare_status(s + + static int iwl_mvm_get_ctrl_vif_queue(struct iwl_mvm *mvm, + struct ieee80211_tx_info *info, +- struct ieee80211_hdr *hdr) ++ struct sk_buff *skb) + { ++ struct ieee80211_hdr *hdr = (void *)skb->data; + struct iwl_mvm_vif *mvmvif = + iwl_mvm_vif_from_mac80211(info->control.vif); + __le16 fc = hdr->frame_control; +@@ -621,7 +622,7 @@ static int iwl_mvm_get_ctrl_vif_queue(st + * reason 7 ("Class 3 frame received from nonassociated STA"). + */ + if (ieee80211_is_mgmt(fc) && +- (!ieee80211_is_bufferable_mmpdu(fc) || ++ (!ieee80211_is_bufferable_mmpdu(skb) || + ieee80211_is_deauth(fc) || ieee80211_is_disassoc(fc))) + return mvm->probe_queue; + +@@ -740,7 +741,7 @@ int iwl_mvm_tx_skb_non_sta(struct iwl_mv + else + sta_id = mvmvif->mcast_sta.sta_id; + +- queue = iwl_mvm_get_ctrl_vif_queue(mvm, &info, hdr); ++ queue = iwl_mvm_get_ctrl_vif_queue(mvm, &info, skb); + } else if (info.control.vif->type == NL80211_IFTYPE_MONITOR) { + queue = mvm->snif_queue; + sta_id = mvm->snif_sta.sta_id; +--- a/include/linux/ieee80211.h ++++ b/include/linux/ieee80211.h +@@ -772,20 +772,6 @@ static inline bool ieee80211_is_any_null + } + + /** +- * ieee80211_is_bufferable_mmpdu - check if frame is bufferable MMPDU +- * @fc: frame control field in little-endian byteorder +- */ +-static inline bool ieee80211_is_bufferable_mmpdu(__le16 fc) +-{ +- /* IEEE 802.11-2012, definition of "bufferable management frame"; +- * note that this ignores the IBSS special case. */ +- return ieee80211_is_mgmt(fc) && +- (ieee80211_is_action(fc) || +- ieee80211_is_disassoc(fc) || +- ieee80211_is_deauth(fc)); +-} +- +-/** + * ieee80211_is_first_frag - check if IEEE80211_SCTL_FRAG is not set + * @seq_ctrl: frame sequence control bytes in little-endian byteorder + */ +@@ -4121,6 +4107,44 @@ static inline u8 *ieee80211_get_DA(struc + } + + /** ++ * ieee80211_is_bufferable_mmpdu - check if frame is bufferable MMPDU ++ * @skb: the skb to check, starting with the 802.11 header ++ */ ++static inline bool ieee80211_is_bufferable_mmpdu(struct sk_buff *skb) ++{ ++ struct ieee80211_mgmt *mgmt = (void *)skb->data; ++ __le16 fc = mgmt->frame_control; ++ ++ /* ++ * IEEE 802.11 REVme D2.0 definition of bufferable MMPDU; ++ * note that this ignores the IBSS special case. ++ */ ++ if (!ieee80211_is_mgmt(fc)) ++ return false; ++ ++ if (ieee80211_is_disassoc(fc) || ieee80211_is_deauth(fc)) ++ return true; ++ ++ if (!ieee80211_is_action(fc)) ++ return false; ++ ++ if (skb->len < offsetofend(typeof(*mgmt), u.action.u.ftm.action_code)) ++ return true; ++ ++ /* action frame - additionally check for non-bufferable FTM */ ++ ++ if (mgmt->u.action.category != WLAN_CATEGORY_PUBLIC && ++ mgmt->u.action.category != WLAN_CATEGORY_PROTECTED_DUAL_OF_ACTION) ++ return true; ++ ++ if (mgmt->u.action.u.ftm.action_code == WLAN_PUB_ACTION_FTM_REQUEST || ++ mgmt->u.action.u.ftm.action_code == WLAN_PUBLIC_ACTION_FTM_RESPONSE) ++ return false; ++ ++ return true; ++} ++ ++/** + * _ieee80211_is_robust_mgmt_frame - check if frame is a robust management frame + * @hdr: the frame (buffer must include at least the first octet of payload) + */ +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -488,7 +488,7 @@ ieee80211_tx_h_unicast_ps_buf(struct iee + int ac = skb_get_queue_mapping(tx->skb); + + if (ieee80211_is_mgmt(hdr->frame_control) && +- !ieee80211_is_bufferable_mmpdu(hdr->frame_control)) { ++ !ieee80211_is_bufferable_mmpdu(tx->skb)) { + info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER; + return TX_CONTINUE; + } +@@ -1326,7 +1326,7 @@ static struct txq_info *ieee80211_get_tx + if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && + unlikely(!ieee80211_is_data_present(hdr->frame_control))) { + if ((!ieee80211_is_mgmt(hdr->frame_control) || +- ieee80211_is_bufferable_mmpdu(hdr->frame_control) || ++ ieee80211_is_bufferable_mmpdu(skb) || + vif->type == NL80211_IFTYPE_STATION) && + sta && sta->uploaded) { + /* diff --git a/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-extend-IEEE80211_KEY_FLAG_GENERATE_MMI.patch b/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-extend-IEEE80211_KEY_FLAG_GENERATE_MMI.patch deleted file mode 100644 index 5c202c26c..000000000 --- a/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-extend-IEEE80211_KEY_FLAG_GENERATE_MMI.patch +++ /dev/null @@ -1,70 +0,0 @@ -From: Michael-CY Lee -Date: Tue, 26 Mar 2024 08:30:36 +0800 -Subject: [PATCH] wifi: mac80211: extend IEEE80211_KEY_FLAG_GENERATE_MMIE to - other ciphers - -Extend the flag IEEE80211_KEY_FLAG_GENERATE_MMIE to BIP-CMAC-256, -BIP-GMAC-128 and BIP-GMAC-256 for the same reason and in the same -way that the flag was added originally in commit a0b4496a4368 -("mac80211: add IEEE80211_KEY_FLAG_GENERATE_MMIE to ieee80211_key_flags"). - -Signed-off-by: Michael-CY Lee -Link: https://msgid.link/20240326003036.15215-1-michael-cy.lee@mediatek.com -Signed-off-by: Johannes Berg ---- - ---- a/include/net/mac80211.h -+++ b/include/net/mac80211.h -@@ -2123,8 +2123,8 @@ static inline bool lockdep_vif_wiphy_mut - * @IEEE80211_KEY_FLAG_GENERATE_MMIC on the same key. - * @IEEE80211_KEY_FLAG_NO_AUTO_TX: Key needs explicit Tx activation. - * @IEEE80211_KEY_FLAG_GENERATE_MMIE: This flag should be set by the driver -- * for a AES_CMAC key to indicate that it requires sequence number -- * generation only -+ * for a AES_CMAC or a AES_GMAC key to indicate that it requires sequence -+ * number generation only - * @IEEE80211_KEY_FLAG_SPP_AMSDU: SPP A-MSDUs can be used with this key - * (set by mac80211 from the sta->spp_amsdu flag) - */ ---- a/net/mac80211/wpa.c -+++ b/net/mac80211/wpa.c -@@ -895,7 +895,8 @@ ieee80211_crypto_aes_cmac_256_encrypt(st - - info = IEEE80211_SKB_CB(skb); - -- if (info->control.hw_key) -+ if (info->control.hw_key && -+ !(key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIE)) - return TX_CONTINUE; - - if (WARN_ON(skb_tailroom(skb) < sizeof(*mmie))) -@@ -911,6 +912,9 @@ ieee80211_crypto_aes_cmac_256_encrypt(st - - bip_ipn_set64(mmie->sequence_number, pn64); - -+ if (info->control.hw_key) -+ return TX_CONTINUE; -+ - bip_aad(skb, aad); - - /* MIC = AES-256-CMAC(IGTK, AAD || Management Frame Body || MMIE, 128) -@@ -1040,7 +1044,8 @@ ieee80211_crypto_aes_gmac_encrypt(struct - - info = IEEE80211_SKB_CB(skb); - -- if (info->control.hw_key) -+ if (info->control.hw_key && -+ !(key->conf.flags & IEEE80211_KEY_FLAG_GENERATE_MMIE)) - return TX_CONTINUE; - - if (WARN_ON(skb_tailroom(skb) < sizeof(*mmie))) -@@ -1056,6 +1061,9 @@ ieee80211_crypto_aes_gmac_encrypt(struct - - bip_ipn_set64(mmie->sequence_number, pn64); - -+ if (info->control.hw_key) -+ return TX_CONTINUE; -+ - bip_aad(skb, aad); - - hdr = (struct ieee80211_hdr *)skb->data; diff --git a/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-flush-queues-on-STA-removal.patch b/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-flush-queues-on-STA-removal.patch new file mode 100644 index 000000000..00232ec1b --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/331-wifi-mac80211-flush-queues-on-STA-removal.patch @@ -0,0 +1,36 @@ +From: Johannes Berg +Date: Mon, 13 Mar 2023 11:42:12 +0100 +Subject: [PATCH] wifi: mac80211: flush queues on STA removal + +When we remove a station, we first make it unreachable, +then we (must) remove its keys, and then remove the +station itself. Depending on the hardware design, if +we have hardware crypto at all, frames still sitting +on hardware queues may then be transmitted without a +valid key, possibly unencrypted or with a fixed key. + +Fix this by flushing the queues when removing stations +so this cannot happen. + +Cc: stable@vger.kernel.org +Signed-off-by: Johannes Berg +Reviewed-by: Greenman, Gregory +--- + +--- a/net/mac80211/sta_info.c ++++ b/net/mac80211/sta_info.c +@@ -1271,6 +1271,14 @@ static void __sta_info_destroy_part2(str + WARN_ON_ONCE(ret); + } + ++ /* Flush queues before removing keys, as that might remove them ++ * from hardware, and then depending on the offload method, any ++ * frames sitting on hardware queues might be sent out without ++ * any encryption at all. ++ */ ++ if (local->ops->set_key) ++ ieee80211_flush_queues(local, sta->sdata, false); ++ + /* now keys can no longer be reached */ + ieee80211_free_sta_keys(local, sta); + diff --git a/package/kernel/mac80211/patches/subsys/332-wifi-iwlwifi-mvm-support-flush-on-AP-interfaces.patch b/package/kernel/mac80211/patches/subsys/332-wifi-iwlwifi-mvm-support-flush-on-AP-interfaces.patch new file mode 100644 index 000000000..3c31dfedd --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/332-wifi-iwlwifi-mvm-support-flush-on-AP-interfaces.patch @@ -0,0 +1,34 @@ +From: Johannes Berg +Date: Mon, 13 Mar 2023 12:02:58 +0100 +Subject: [PATCH] wifi: iwlwifi: mvm: support flush on AP interfaces + +Support TX flush on AP interfaces so that we will do a +proper flush for frames on the queue before keys are +removed. + +Signed-off-by: Johannes Berg +Reviewed-by: Greenman, Gregory +--- + +--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +@@ -4854,9 +4854,6 @@ static void iwl_mvm_mac_flush(struct iee + return; + } + +- if (vif->type != NL80211_IFTYPE_STATION) +- return; +- + /* Make sure we're done with the deferred traffic before flushing */ + flush_work(&mvm->add_stream_wk); + +@@ -4874,9 +4871,6 @@ static void iwl_mvm_mac_flush(struct iee + if (mvmsta->vif != vif) + continue; + +- /* make sure only TDLS peers or the AP are flushed */ +- WARN_ON(i != mvmvif->ap_sta_id && !sta->tdls); +- + if (drop) { + if (iwl_mvm_flush_sta(mvm, mvmsta, false)) + IWL_ERR(mvm, "flush request fail\n"); diff --git a/package/kernel/mac80211/patches/subsys/333-wifi-mac80211-add-flush_sta-method.patch b/package/kernel/mac80211/patches/subsys/333-wifi-mac80211-add-flush_sta-method.patch new file mode 100644 index 000000000..3bba0b7e6 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/333-wifi-mac80211-add-flush_sta-method.patch @@ -0,0 +1,91 @@ +From: Johannes Berg +Date: Mon, 13 Mar 2023 11:53:51 +0100 +Subject: [PATCH] wifi: mac80211: add flush_sta method + +Some drivers like iwlwifi might have per-STA queues, so we +may want to flush/drop just those queues rather than all +when removing a station. Add a separate method for that. + +Signed-off-by: Johannes Berg +Reviewed-by: Greenman, Gregory +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -3918,6 +3918,10 @@ struct ieee80211_prep_tx_info { + * Note that vif can be NULL. + * The callback can sleep. + * ++ * @flush_sta: Flush or drop all pending frames from the hardware queue(s) for ++ * the given station, as it's about to be removed. ++ * The callback can sleep. ++ * + * @channel_switch: Drivers that need (or want) to offload the channel + * switch operation for CSAs received from the AP may implement this + * callback. They must then call ieee80211_chswitch_done() to indicate +@@ -4372,6 +4376,8 @@ struct ieee80211_ops { + #endif + void (*flush)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u32 queues, bool drop); ++ void (*flush_sta)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); + void (*channel_switch)(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_channel_switch *ch_switch); +--- a/net/mac80211/driver-ops.h ++++ b/net/mac80211/driver-ops.h +@@ -617,6 +617,21 @@ static inline void drv_flush(struct ieee + trace_drv_return_void(local); + } + ++static inline void drv_flush_sta(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ struct sta_info *sta) ++{ ++ might_sleep(); ++ ++ if (sdata && !check_sdata_in_driver(sdata)) ++ return; ++ ++ trace_drv_flush_sta(local, sdata, &sta->sta); ++ if (local->ops->flush_sta) ++ local->ops->flush_sta(&local->hw, &sdata->vif, &sta->sta); ++ trace_drv_return_void(local); ++} ++ + static inline void drv_channel_switch(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, + struct ieee80211_channel_switch *ch_switch) +--- a/net/mac80211/sta_info.c ++++ b/net/mac80211/sta_info.c +@@ -1276,8 +1276,12 @@ static void __sta_info_destroy_part2(str + * frames sitting on hardware queues might be sent out without + * any encryption at all. + */ +- if (local->ops->set_key) +- ieee80211_flush_queues(local, sta->sdata, false); ++ if (local->ops->set_key) { ++ if (local->ops->flush_sta) ++ drv_flush_sta(local, sta->sdata, sta); ++ else ++ ieee80211_flush_queues(local, sta->sdata, false); ++ } + + /* now keys can no longer be reached */ + ieee80211_free_sta_keys(local, sta); +--- a/net/mac80211/trace.h ++++ b/net/mac80211/trace.h +@@ -1177,6 +1177,13 @@ TRACE_EVENT(drv_flush, + ) + ); + ++DEFINE_EVENT(sta_event, drv_flush_sta, ++ TP_PROTO(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ struct ieee80211_sta *sta), ++ TP_ARGS(local, sdata, sta) ++); ++ + TRACE_EVENT(drv_channel_switch, + TP_PROTO(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, diff --git a/package/kernel/mac80211/patches/subsys/334-wifi-iwlwifi-mvm-support-new-flush_sta-method.patch b/package/kernel/mac80211/patches/subsys/334-wifi-iwlwifi-mvm-support-new-flush_sta-method.patch new file mode 100644 index 000000000..18f39d505 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/334-wifi-iwlwifi-mvm-support-new-flush_sta-method.patch @@ -0,0 +1,53 @@ +From: Johannes Berg +Date: Mon, 13 Mar 2023 12:05:35 +0100 +Subject: [PATCH] wifi: iwlwifi: mvm: support new flush_sta method + +For iwlwifi this is simple to implement, and on newer hardware +it's an improvement since we have per-station queues. + +Signed-off-by: Johannes Berg +Reviewed-by: Greenman, Gregory +--- + +--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +@@ -4890,6 +4890,31 @@ static void iwl_mvm_mac_flush(struct iee + iwl_trans_wait_tx_queues_empty(mvm->trans, msk); + } + ++static void iwl_mvm_mac_flush_sta(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw); ++ int i; ++ ++ mutex_lock(&mvm->mutex); ++ for (i = 0; i < mvm->fw->ucode_capa.num_stations; i++) { ++ struct iwl_mvm_sta *mvmsta; ++ struct ieee80211_sta *tmp; ++ ++ tmp = rcu_dereference_protected(mvm->fw_id_to_mac_id[i], ++ lockdep_is_held(&mvm->mutex)); ++ if (tmp != sta) ++ continue; ++ ++ mvmsta = iwl_mvm_sta_from_mac80211(sta); ++ ++ if (iwl_mvm_flush_sta(mvm, mvmsta, false)) ++ IWL_ERR(mvm, "flush request fail\n"); ++ } ++ mutex_unlock(&mvm->mutex); ++} ++ + static int iwl_mvm_mac_get_survey(struct ieee80211_hw *hw, int idx, + struct survey_info *survey) + { +@@ -5417,6 +5442,7 @@ const struct ieee80211_ops iwl_mvm_hw_op + .mgd_complete_tx = iwl_mvm_mac_mgd_complete_tx, + .mgd_protect_tdls_discover = iwl_mvm_mac_mgd_protect_tdls_discover, + .flush = iwl_mvm_mac_flush, ++ .flush_sta = iwl_mvm_mac_flush_sta, + .sched_scan_start = iwl_mvm_mac_sched_scan_start, + .sched_scan_stop = iwl_mvm_mac_sched_scan_stop, + .set_key = iwl_mvm_mac_set_key, diff --git a/package/kernel/mac80211/patches/subsys/335-wifi-mac80211-add-LDPC-related-flags-in-ieee80211_bs.patch b/package/kernel/mac80211/patches/subsys/335-wifi-mac80211-add-LDPC-related-flags-in-ieee80211_bs.patch new file mode 100644 index 000000000..1b379b76a --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/335-wifi-mac80211-add-LDPC-related-flags-in-ieee80211_bs.patch @@ -0,0 +1,62 @@ +From: Ryder Lee +Date: Sat, 18 Feb 2023 01:49:25 +0800 +Subject: [PATCH] wifi: mac80211: add LDPC related flags in ieee80211_bss_conf + +This is utilized to pass LDPC configurations from user space +(i.e. hostapd) to driver. + +Signed-off-by: Ryder Lee +Link: https://lore.kernel.org/r/1de696aaa34efd77a926eb657b8c0fda05aaa177.1676628065.git.ryder.lee@mediatek.com +Signed-off-by: Johannes Berg +--- + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -653,6 +653,9 @@ struct ieee80211_fils_discovery { + * write-protected by sdata_lock and local->mtx so holding either is fine + * for read access. + * @color_change_color: the bss color that will be used after the change. ++ * @ht_ldpc: in AP mode, indicates interface has HT LDPC capability. ++ * @vht_ldpc: in AP mode, indicates interface has VHT LDPC capability. ++ * @he_ldpc: in AP mode, indicates interface has HE LDPC capability. + * @vht_su_beamformer: in AP mode, does this BSS support operation as an VHT SU + * beamformer + * @vht_su_beamformee: in AP mode, does this BSS support operation as an VHT SU +@@ -744,6 +747,9 @@ struct ieee80211_bss_conf { + bool color_change_active; + u8 color_change_color; + ++ bool ht_ldpc; ++ bool vht_ldpc; ++ bool he_ldpc; + bool vht_su_beamformer; + bool vht_su_beamformee; + bool vht_mu_beamformer; +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -1252,7 +1252,15 @@ static int ieee80211_start_ap(struct wip + prev_beacon_int = link_conf->beacon_int; + link_conf->beacon_int = params->beacon_interval; + ++ if (params->ht_cap) ++ link_conf->ht_ldpc = ++ params->ht_cap->cap_info & ++ cpu_to_le16(IEEE80211_HT_CAP_LDPC_CODING); ++ + if (params->vht_cap) { ++ link_conf->vht_ldpc = ++ params->vht_cap->vht_cap_info & ++ cpu_to_le32(IEEE80211_VHT_CAP_RXLDPC); + link_conf->vht_su_beamformer = + params->vht_cap->vht_cap_info & + cpu_to_le32(IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE); +@@ -1282,6 +1290,9 @@ static int ieee80211_start_ap(struct wip + } + + if (params->he_cap) { ++ link_conf->he_ldpc = ++ params->he_cap->phy_cap_info[1] & ++ IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; + link_conf->he_su_beamformer = + params->he_cap->phy_cap_info[3] & + IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; diff --git a/package/kernel/mac80211/patches/subsys/336-v6.4-wifi-mac80211-generate-EMA-beacons-in-AP-mode.patch b/package/kernel/mac80211/patches/subsys/336-v6.4-wifi-mac80211-generate-EMA-beacons-in-AP-mode.patch new file mode 100644 index 000000000..088f468e3 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/336-v6.4-wifi-mac80211-generate-EMA-beacons-in-AP-mode.patch @@ -0,0 +1,372 @@ +From bd54f3c29077f23dad92ef82a78061b40be30c65 Mon Sep 17 00:00:00 2001 +From: Aloka Dixit +Date: Mon, 5 Dec 2022 16:50:37 -0800 +Subject: [PATCH] wifi: mac80211: generate EMA beacons in AP mode + +Add APIs to generate an array of beacons for an EMA AP (enhanced +multiple BSSID advertisements), each including a single MBSSID element. +EMA profile periodicity equals the count of elements. + +- ieee80211_beacon_get_template_ema_list() - Generate and return all +EMA beacon templates. Drivers must call ieee80211_beacon_free_ema_list() +to free the memory. No change in the prototype for the existing API, +ieee80211_beacon_get_template(), which should be used for non-EMA AP. + +- ieee80211_beacon_get_template_ema_index() - Generate a beacon which +includes the multiple BSSID element at the given index. Drivers can use +this function in a loop until NULL is returned which indicates end of +available MBSSID elements. + +- ieee80211_beacon_free_ema_list() - free the memory allocated for the +list of EMA beacon templates. + +Modify existing functions ieee80211_beacon_get_ap(), +ieee80211_get_mbssid_beacon_len() and ieee80211_beacon_add_mbssid() +to accept a new parameter for EMA index. + +Signed-off-by: Aloka Dixit +Co-developed-by: John Crispin +Signed-off-by: John Crispin +Link: https://lore.kernel.org/r/20221206005040.3177-2-quic_alokad@quicinc.com +Signed-off-by: Johannes Berg +--- + include/net/mac80211.h | 68 +++++++++++++++++++ + net/mac80211/cfg.c | 11 +-- + net/mac80211/ieee80211_i.h | 10 ++- + net/mac80211/tx.c | 134 ++++++++++++++++++++++++++++++++++--- + 4 files changed, 205 insertions(+), 18 deletions(-) + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -5252,6 +5252,74 @@ ieee80211_beacon_get_template(struct iee + unsigned int link_id); + + /** ++ * ieee80211_beacon_get_template_ema_index - EMA beacon template generation ++ * @hw: pointer obtained from ieee80211_alloc_hw(). ++ * @vif: &struct ieee80211_vif pointer from the add_interface callback. ++ * @offs: &struct ieee80211_mutable_offsets pointer to struct that will ++ * receive the offsets that may be updated by the driver. ++ * @link_id: the link id to which the beacon belongs (or 0 for a non-MLD AP). ++ * @ema_index: index of the beacon in the EMA set. ++ * ++ * This function follows the same rules as ieee80211_beacon_get_template() ++ * but returns a beacon template which includes multiple BSSID element at the ++ * requested index. ++ * ++ * Return: The beacon template. %NULL indicates the end of EMA templates. ++ */ ++struct sk_buff * ++ieee80211_beacon_get_template_ema_index(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_mutable_offsets *offs, ++ unsigned int link_id, u8 ema_index); ++ ++/** ++ * struct ieee80211_ema_beacons - List of EMA beacons ++ * @cnt: count of EMA beacons. ++ * ++ * @bcn: array of EMA beacons. ++ * @bcn.skb: the skb containing this specific beacon ++ * @bcn.offs: &struct ieee80211_mutable_offsets pointer to struct that will ++ * receive the offsets that may be updated by the driver. ++ */ ++struct ieee80211_ema_beacons { ++ u8 cnt; ++ struct { ++ struct sk_buff *skb; ++ struct ieee80211_mutable_offsets offs; ++ } bcn[]; ++}; ++ ++/** ++ * ieee80211_beacon_get_template_ema_list - EMA beacon template generation ++ * @hw: pointer obtained from ieee80211_alloc_hw(). ++ * @vif: &struct ieee80211_vif pointer from the add_interface callback. ++ * @link_id: the link id to which the beacon belongs (or 0 for a non-MLD AP) ++ * ++ * This function follows the same rules as ieee80211_beacon_get_template() ++ * but allocates and returns a pointer to list of all beacon templates required ++ * to cover all profiles in the multiple BSSID set. Each template includes only ++ * one multiple BSSID element. ++ * ++ * Driver must call ieee80211_beacon_free_ema_list() to free the memory. ++ * ++ * Return: EMA beacon templates of type struct ieee80211_ema_beacons *. ++ * %NULL on error. ++ */ ++struct ieee80211_ema_beacons * ++ieee80211_beacon_get_template_ema_list(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ unsigned int link_id); ++ ++/** ++ * ieee80211_beacon_free_ema_list - free an EMA beacon template list ++ * @ema_beacons: list of EMA beacons of type &struct ieee80211_ema_beacons pointers. ++ * ++ * This function will free a list previously acquired by calling ++ * ieee80211_beacon_get_template_ema_list() ++ */ ++void ieee80211_beacon_free_ema_list(struct ieee80211_ema_beacons *ema_beacons); ++ ++/** + * ieee80211_beacon_get_tim - beacon generation function + * @hw: pointer obtained from ieee80211_alloc_hw(). + * @vif: &struct ieee80211_vif pointer from the add_interface callback. +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -1122,11 +1122,11 @@ static int ieee80211_assign_beacon(struc + if (params->mbssid_ies) { + mbssid = params->mbssid_ies; + size += struct_size(new->mbssid_ies, elem, mbssid->cnt); +- size += ieee80211_get_mbssid_beacon_len(mbssid); ++ size += ieee80211_get_mbssid_beacon_len(mbssid, mbssid->cnt); + } else if (old && old->mbssid_ies) { + mbssid = old->mbssid_ies; + size += struct_size(new->mbssid_ies, elem, mbssid->cnt); +- size += ieee80211_get_mbssid_beacon_len(mbssid); ++ size += ieee80211_get_mbssid_beacon_len(mbssid, mbssid->cnt); + } + + new = kzalloc(size, GFP_KERNEL); +@@ -3384,8 +3384,11 @@ cfg80211_beacon_dup(struct cfg80211_beac + + len = beacon->head_len + beacon->tail_len + beacon->beacon_ies_len + + beacon->proberesp_ies_len + beacon->assocresp_ies_len + +- beacon->probe_resp_len + beacon->lci_len + beacon->civicloc_len + +- ieee80211_get_mbssid_beacon_len(beacon->mbssid_ies); ++ beacon->probe_resp_len + beacon->lci_len + beacon->civicloc_len; ++ ++ if (beacon->mbssid_ies) ++ len += ieee80211_get_mbssid_beacon_len(beacon->mbssid_ies, ++ beacon->mbssid_ies->cnt); + + new_beacon = kzalloc(sizeof(*new_beacon) + len, GFP_KERNEL); + if (!new_beacon) +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -1182,13 +1182,17 @@ ieee80211_vif_get_shift(struct ieee80211 + } + + static inline int +-ieee80211_get_mbssid_beacon_len(struct cfg80211_mbssid_elems *elems) ++ieee80211_get_mbssid_beacon_len(struct cfg80211_mbssid_elems *elems, u8 i) + { +- int i, len = 0; ++ int len = 0; + +- if (!elems) ++ if (!elems || !elems->cnt || i > elems->cnt) + return 0; + ++ if (i < elems->cnt) ++ return elems->elem[i].len; ++ ++ /* i == elems->cnt, calculate total length of all MBSSID elements */ + for (i = 0; i < elems->cnt; i++) + len += elems->elem[i].len; + +--- a/net/mac80211/tx.c ++++ b/net/mac80211/tx.c +@@ -5205,13 +5205,20 @@ ieee80211_beacon_get_finish(struct ieee8 + } + + static void +-ieee80211_beacon_add_mbssid(struct sk_buff *skb, struct beacon_data *beacon) ++ieee80211_beacon_add_mbssid(struct sk_buff *skb, struct beacon_data *beacon, ++ u8 i) + { +- int i; ++ if (!beacon->mbssid_ies || !beacon->mbssid_ies->cnt || ++ i > beacon->mbssid_ies->cnt) ++ return; + +- if (!beacon->mbssid_ies) ++ if (i < beacon->mbssid_ies->cnt) { ++ skb_put_data(skb, beacon->mbssid_ies->elem[i].data, ++ beacon->mbssid_ies->elem[i].len); + return; ++ } + ++ /* i == beacon->mbssid_ies->cnt, include all MBSSID elements */ + for (i = 0; i < beacon->mbssid_ies->cnt; i++) + skb_put_data(skb, beacon->mbssid_ies->elem[i].data, + beacon->mbssid_ies->elem[i].len); +@@ -5224,7 +5231,8 @@ ieee80211_beacon_get_ap(struct ieee80211 + struct ieee80211_mutable_offsets *offs, + bool is_template, + struct beacon_data *beacon, +- struct ieee80211_chanctx_conf *chanctx_conf) ++ struct ieee80211_chanctx_conf *chanctx_conf, ++ u8 ema_index) + { + struct ieee80211_local *local = hw_to_local(hw); + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); +@@ -5243,7 +5251,9 @@ ieee80211_beacon_get_ap(struct ieee80211 + /* headroom, head length, + * tail length, maximum TIM length and multiple BSSID length + */ +- mbssid_len = ieee80211_get_mbssid_beacon_len(beacon->mbssid_ies); ++ mbssid_len = ieee80211_get_mbssid_beacon_len(beacon->mbssid_ies, ++ ema_index); ++ + skb = dev_alloc_skb(local->tx_headroom + beacon->head_len + + beacon->tail_len + 256 + + local->hw.extra_beacon_tailroom + mbssid_len); +@@ -5261,7 +5271,7 @@ ieee80211_beacon_get_ap(struct ieee80211 + offs->cntdwn_counter_offs[0] = beacon->cntdwn_counter_offsets[0]; + + if (mbssid_len) { +- ieee80211_beacon_add_mbssid(skb, beacon); ++ ieee80211_beacon_add_mbssid(skb, beacon, ema_index); + offs->mbssid_off = skb->len - mbssid_len; + } + +@@ -5280,12 +5290,51 @@ ieee80211_beacon_get_ap(struct ieee80211 + return skb; + } + ++static struct ieee80211_ema_beacons * ++ieee80211_beacon_get_ap_ema_list(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_link_data *link, ++ struct ieee80211_mutable_offsets *offs, ++ bool is_template, struct beacon_data *beacon, ++ struct ieee80211_chanctx_conf *chanctx_conf) ++{ ++ struct ieee80211_ema_beacons *ema = NULL; ++ ++ if (!beacon->mbssid_ies || !beacon->mbssid_ies->cnt) ++ return NULL; ++ ++ ema = kzalloc(struct_size(ema, bcn, beacon->mbssid_ies->cnt), ++ GFP_ATOMIC); ++ if (!ema) ++ return NULL; ++ ++ for (ema->cnt = 0; ema->cnt < beacon->mbssid_ies->cnt; ema->cnt++) { ++ ema->bcn[ema->cnt].skb = ++ ieee80211_beacon_get_ap(hw, vif, link, ++ &ema->bcn[ema->cnt].offs, ++ is_template, beacon, ++ chanctx_conf, ema->cnt); ++ if (!ema->bcn[ema->cnt].skb) ++ break; ++ } ++ ++ if (ema->cnt == beacon->mbssid_ies->cnt) ++ return ema; ++ ++ ieee80211_beacon_free_ema_list(ema); ++ return NULL; ++} ++ ++#define IEEE80211_INCLUDE_ALL_MBSSID_ELEMS -1 ++ + static struct sk_buff * + __ieee80211_beacon_get(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_mutable_offsets *offs, + bool is_template, +- unsigned int link_id) ++ unsigned int link_id, ++ int ema_index, ++ struct ieee80211_ema_beacons **ema_beacons) + { + struct ieee80211_local *local = hw_to_local(hw); + struct beacon_data *beacon = NULL; +@@ -5314,8 +5363,29 @@ __ieee80211_beacon_get(struct ieee80211_ + if (!beacon) + goto out; + +- skb = ieee80211_beacon_get_ap(hw, vif, link, offs, is_template, +- beacon, chanctx_conf); ++ if (ema_beacons) { ++ *ema_beacons = ++ ieee80211_beacon_get_ap_ema_list(hw, vif, link, ++ offs, ++ is_template, ++ beacon, ++ chanctx_conf); ++ } else { ++ if (beacon->mbssid_ies && beacon->mbssid_ies->cnt) { ++ if (ema_index >= beacon->mbssid_ies->cnt) ++ goto out; /* End of MBSSID elements */ ++ ++ if (ema_index <= IEEE80211_INCLUDE_ALL_MBSSID_ELEMS) ++ ema_index = beacon->mbssid_ies->cnt; ++ } else { ++ ema_index = 0; ++ } ++ ++ skb = ieee80211_beacon_get_ap(hw, vif, link, offs, ++ is_template, beacon, ++ chanctx_conf, ++ ema_index); ++ } + } else if (sdata->vif.type == NL80211_IFTYPE_ADHOC) { + struct ieee80211_if_ibss *ifibss = &sdata->u.ibss; + struct ieee80211_hdr *hdr; +@@ -5403,10 +5473,50 @@ ieee80211_beacon_get_template(struct iee + struct ieee80211_mutable_offsets *offs, + unsigned int link_id) + { +- return __ieee80211_beacon_get(hw, vif, offs, true, link_id); ++ return __ieee80211_beacon_get(hw, vif, offs, true, link_id, ++ IEEE80211_INCLUDE_ALL_MBSSID_ELEMS, NULL); + } + EXPORT_SYMBOL(ieee80211_beacon_get_template); + ++struct sk_buff * ++ieee80211_beacon_get_template_ema_index(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_mutable_offsets *offs, ++ unsigned int link_id, u8 ema_index) ++{ ++ return __ieee80211_beacon_get(hw, vif, offs, true, link_id, ema_index, ++ NULL); ++} ++EXPORT_SYMBOL(ieee80211_beacon_get_template_ema_index); ++ ++void ieee80211_beacon_free_ema_list(struct ieee80211_ema_beacons *ema_beacons) ++{ ++ u8 i; ++ ++ if (!ema_beacons) ++ return; ++ ++ for (i = 0; i < ema_beacons->cnt; i++) ++ kfree_skb(ema_beacons->bcn[i].skb); ++ ++ kfree(ema_beacons); ++} ++EXPORT_SYMBOL(ieee80211_beacon_free_ema_list); ++ ++struct ieee80211_ema_beacons * ++ieee80211_beacon_get_template_ema_list(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ unsigned int link_id) ++{ ++ struct ieee80211_ema_beacons *ema_beacons = NULL; ++ ++ WARN_ON(__ieee80211_beacon_get(hw, vif, NULL, false, link_id, 0, ++ &ema_beacons)); ++ ++ return ema_beacons; ++} ++EXPORT_SYMBOL(ieee80211_beacon_get_template_ema_list); ++ + struct sk_buff *ieee80211_beacon_get_tim(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u16 *tim_offset, u16 *tim_length, +@@ -5414,7 +5524,9 @@ struct sk_buff *ieee80211_beacon_get_tim + { + struct ieee80211_mutable_offsets offs = {}; + struct sk_buff *bcn = __ieee80211_beacon_get(hw, vif, &offs, false, +- link_id); ++ link_id, ++ IEEE80211_INCLUDE_ALL_MBSSID_ELEMS, ++ NULL); + struct sk_buff *copy; + int shift; + diff --git a/package/kernel/mac80211/patches/subsys/337-mac80211-fix-sband-iftype-data-lookup-for-AP_VLAN.patch b/package/kernel/mac80211/patches/subsys/337-mac80211-fix-sband-iftype-data-lookup-for-AP_VLAN.patch new file mode 100644 index 000000000..67b428494 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/337-mac80211-fix-sband-iftype-data-lookup-for-AP_VLAN.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Date: Thu, 22 Jun 2023 18:02:25 +0200 +Subject: [PATCH] mac80211: fix sband iftype data lookup for AP_VLAN + +AP_VLAN interfaces are virtual, so doesn't really exist as a type for +capabilities. When passed in as a type, AP is the one that's really intended. + +Fixes: c4cbaf7973a7 ("cfg80211: Add support for HE") +Signed-off-by: Felix Fietkau +--- + +--- a/include/net/cfg80211.h ++++ b/include/net/cfg80211.h +@@ -567,6 +567,9 @@ ieee80211_get_sband_iftype_data(const st + if (WARN_ON(iftype >= NL80211_IFTYPE_MAX)) + return NULL; + ++ if (iftype == NL80211_IFTYPE_AP_VLAN) ++ iftype = NL80211_IFTYPE_AP; ++ + for (i = 0; i < sband->n_iftype_data; i++) { + const struct ieee80211_sband_iftype_data *data = + &sband->iftype_data[i]; diff --git a/package/kernel/mac80211/patches/subsys/338-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch b/package/kernel/mac80211/patches/subsys/338-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch new file mode 100644 index 000000000..f7391a580 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/338-mac80211-split-mesh-fast-tx-cache-into-local-proxied.patch @@ -0,0 +1,219 @@ +From: Felix Fietkau +Date: Fri, 30 Jun 2023 13:11:51 +0200 +Subject: [PATCH] mac80211: split mesh fast tx cache into + local/proxied/forwarded + +Depending on the origin of the packets (and their SA), 802.11 + mesh headers +could be filled in differently. In order to properly deal with that, add a +new field to the lookup key, indicating the type (local, proxied or +forwarded). This can fix spurious packet drop issues that depend on the order +in which nodes/hosts communicate with each other. + +Signed-off-by: Felix Fietkau +--- + +--- a/net/mac80211/mesh.c ++++ b/net/mac80211/mesh.c +@@ -703,6 +703,9 @@ bool ieee80211_mesh_xmit_fast(struct iee + struct sk_buff *skb, u32 ctrl_flags) + { + struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; ++ struct ieee80211_mesh_fast_tx_key key = { ++ .type = MESH_FAST_TX_TYPE_LOCAL ++ }; + struct ieee80211_mesh_fast_tx *entry; + struct ieee80211s_hdr *meshhdr; + u8 sa[ETH_ALEN] __aligned(2); +@@ -738,7 +741,10 @@ bool ieee80211_mesh_xmit_fast(struct iee + return false; + } + +- entry = mesh_fast_tx_get(sdata, skb->data); ++ ether_addr_copy(key.addr, skb->data); ++ if (!ether_addr_equal(skb->data + ETH_ALEN, sdata->vif.addr)) ++ key.type = MESH_FAST_TX_TYPE_PROXIED; ++ entry = mesh_fast_tx_get(sdata, &key); + if (!entry) + return false; + +--- a/net/mac80211/mesh.h ++++ b/net/mac80211/mesh.h +@@ -133,9 +133,33 @@ struct mesh_path { + #define MESH_FAST_TX_CACHE_TIMEOUT 8000 /* msecs */ + + /** ++ * enum ieee80211_mesh_fast_tx_type - cached mesh fast tx entry type ++ * ++ * @MESH_FAST_TX_TYPE_LOCAL: tx from the local vif address as SA ++ * @MESH_FAST_TX_TYPE_PROXIED: local tx with a different SA (e.g. bridged) ++ * @MESH_FAST_TX_TYPE_FORWARDED: forwarded from a different mesh point ++ */ ++enum ieee80211_mesh_fast_tx_type { ++ MESH_FAST_TX_TYPE_LOCAL, ++ MESH_FAST_TX_TYPE_PROXIED, ++ MESH_FAST_TX_TYPE_FORWARDED, ++}; ++ ++/** ++ * struct ieee80211_mesh_fast_tx_key - cached mesh fast tx entry key ++ * ++ * @addr: The Ethernet DA for this entry ++ * @type: cache entry type ++ */ ++struct ieee80211_mesh_fast_tx_key { ++ u8 addr[ETH_ALEN] __aligned(2); ++ enum ieee80211_mesh_fast_tx_type type; ++}; ++ ++/** + * struct ieee80211_mesh_fast_tx - cached mesh fast tx entry + * @rhash: rhashtable pointer +- * @addr_key: The Ethernet DA which is the key for this entry ++ * @key: the lookup key for this cache entry + * @fast_tx: base fast_tx data + * @hdr: cached mesh and rfc1042 headers + * @hdrlen: length of mesh + rfc1042 +@@ -146,7 +170,7 @@ struct mesh_path { + */ + struct ieee80211_mesh_fast_tx { + struct rhash_head rhash; +- u8 addr_key[ETH_ALEN] __aligned(2); ++ struct ieee80211_mesh_fast_tx_key key; + + struct ieee80211_fast_tx fast_tx; + u8 hdr[sizeof(struct ieee80211s_hdr) + sizeof(rfc1042_header)]; +@@ -329,7 +353,8 @@ void mesh_path_tx_root_frame(struct ieee + + bool mesh_action_is_path_sel(struct ieee80211_mgmt *mgmt); + struct ieee80211_mesh_fast_tx * +-mesh_fast_tx_get(struct ieee80211_sub_if_data *sdata, const u8 *addr); ++mesh_fast_tx_get(struct ieee80211_sub_if_data *sdata, ++ struct ieee80211_mesh_fast_tx_key *key); + bool ieee80211_mesh_xmit_fast(struct ieee80211_sub_if_data *sdata, + struct sk_buff *skb, u32 ctrl_flags); + void mesh_fast_tx_cache(struct ieee80211_sub_if_data *sdata, +--- a/net/mac80211/mesh_pathtbl.c ++++ b/net/mac80211/mesh_pathtbl.c +@@ -36,8 +36,8 @@ static const struct rhashtable_params me + static const struct rhashtable_params fast_tx_rht_params = { + .nelem_hint = 10, + .automatic_shrinking = true, +- .key_len = ETH_ALEN, +- .key_offset = offsetof(struct ieee80211_mesh_fast_tx, addr_key), ++ .key_len = sizeof(struct ieee80211_mesh_fast_tx_key), ++ .key_offset = offsetof(struct ieee80211_mesh_fast_tx, key), + .head_offset = offsetof(struct ieee80211_mesh_fast_tx, rhash), + .hashfn = mesh_table_hash, + }; +@@ -426,20 +426,21 @@ static void mesh_fast_tx_entry_free(stru + } + + struct ieee80211_mesh_fast_tx * +-mesh_fast_tx_get(struct ieee80211_sub_if_data *sdata, const u8 *addr) ++mesh_fast_tx_get(struct ieee80211_sub_if_data *sdata, ++ struct ieee80211_mesh_fast_tx_key *key) + { + struct ieee80211_mesh_fast_tx *entry; + struct mesh_tx_cache *cache; + + cache = &sdata->u.mesh.tx_cache; +- entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); ++ entry = rhashtable_lookup(&cache->rht, key, fast_tx_rht_params); + if (!entry) + return NULL; + + if (!(entry->mpath->flags & MESH_PATH_ACTIVE) || + mpath_expired(entry->mpath)) { + spin_lock_bh(&cache->walk_lock); +- entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); ++ entry = rhashtable_lookup(&cache->rht, key, fast_tx_rht_params); + if (entry) + mesh_fast_tx_entry_free(cache, entry); + spin_unlock_bh(&cache->walk_lock); +@@ -484,18 +485,24 @@ void mesh_fast_tx_cache(struct ieee80211 + if (!sta) + return; + ++ build.key.type = MESH_FAST_TX_TYPE_LOCAL; + if ((meshhdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6) { + /* This is required to keep the mppath alive */ + mppath = mpp_path_lookup(sdata, meshhdr->eaddr1); + if (!mppath) + return; + build.mppath = mppath; ++ if (!ether_addr_equal(meshhdr->eaddr2, sdata->vif.addr)) ++ build.key.type = MESH_FAST_TX_TYPE_PROXIED; + } else if (ieee80211_has_a4(hdr->frame_control)) { + mppath = mpath; + } else { + return; + } + ++ if (!ether_addr_equal(hdr->addr4, sdata->vif.addr)) ++ build.key.type = MESH_FAST_TX_TYPE_FORWARDED; ++ + /* rate limit, in case fast xmit can't be enabled */ + if (mppath->fast_tx_check == jiffies) + return; +@@ -542,7 +549,7 @@ void mesh_fast_tx_cache(struct ieee80211 + } + } + +- memcpy(build.addr_key, mppath->dst, ETH_ALEN); ++ memcpy(build.key.addr, mppath->dst, ETH_ALEN); + build.timestamp = jiffies; + build.fast_tx.band = info->band; + build.fast_tx.da_offs = offsetof(struct ieee80211_hdr, addr3); +@@ -644,13 +651,19 @@ void mesh_fast_tx_flush_addr(struct ieee + const u8 *addr) + { + struct mesh_tx_cache *cache = &sdata->u.mesh.tx_cache; ++ struct ieee80211_mesh_fast_tx_key key = {}; + struct ieee80211_mesh_fast_tx *entry; ++ int i; + ++ ether_addr_copy(key.addr, addr); + cache = &sdata->u.mesh.tx_cache; + spin_lock_bh(&cache->walk_lock); +- entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); +- if (entry) +- mesh_fast_tx_entry_free(cache, entry); ++ for (i = MESH_FAST_TX_TYPE_LOCAL; i < MESH_FAST_TX_TYPE_FORWARDED; i++) { ++ key.type = i; ++ entry = rhashtable_lookup(&cache->rht, &key, fast_tx_rht_params); ++ if (entry) ++ mesh_fast_tx_entry_free(cache, entry); ++ } + spin_unlock_bh(&cache->walk_lock); + } + +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -2726,7 +2726,10 @@ ieee80211_rx_mesh_fast_forward(struct ie + struct sk_buff *skb, int hdrlen) + { + struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; +- struct ieee80211_mesh_fast_tx *entry = NULL; ++ struct ieee80211_mesh_fast_tx_key key = { ++ .type = MESH_FAST_TX_TYPE_FORWARDED ++ }; ++ struct ieee80211_mesh_fast_tx *entry; + struct ieee80211s_hdr *mesh_hdr; + struct tid_ampdu_tx *tid_tx; + struct sta_info *sta; +@@ -2735,9 +2738,13 @@ ieee80211_rx_mesh_fast_forward(struct ie + + mesh_hdr = (struct ieee80211s_hdr *)(skb->data + sizeof(eth)); + if ((mesh_hdr->flags & MESH_FLAGS_AE) == MESH_FLAGS_AE_A5_A6) +- entry = mesh_fast_tx_get(sdata, mesh_hdr->eaddr1); ++ ether_addr_copy(key.addr, mesh_hdr->eaddr1); + else if (!(mesh_hdr->flags & MESH_FLAGS_AE)) +- entry = mesh_fast_tx_get(sdata, skb->data); ++ ether_addr_copy(key.addr, skb->data); ++ else ++ return false; ++ ++ entry = mesh_fast_tx_get(sdata, &key); + if (!entry) + return false; + diff --git a/package/kernel/mac80211/patches/subsys/340-wifi-nl80211-split-helper-function-from-nl80211_put_.patch b/package/kernel/mac80211/patches/subsys/340-wifi-nl80211-split-helper-function-from-nl80211_put_.patch deleted file mode 100644 index 40757e377..000000000 --- a/package/kernel/mac80211/patches/subsys/340-wifi-nl80211-split-helper-function-from-nl80211_put_.patch +++ /dev/null @@ -1,145 +0,0 @@ -From: Felix Fietkau -Date: Tue, 4 Jun 2024 14:31:09 +0200 -Subject: [PATCH] wifi: nl80211: split helper function from - nl80211_put_iface_combinations - -Create a helper function that puts the data from struct -ieee80211_iface_combination to a nl80211 message. -This will be used for adding per-radio interface combination data. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/wireless/nl80211.c -+++ b/net/wireless/nl80211.c -@@ -1620,71 +1620,78 @@ nla_put_failure: - return -ENOBUFS; - } - --static int nl80211_put_iface_combinations(struct wiphy *wiphy, -- struct sk_buff *msg, -- bool large) -+static int nl80211_put_ifcomb_data(struct sk_buff *msg, bool large, int idx, -+ const struct ieee80211_iface_combination *c) - { -- struct nlattr *nl_combis; -- int i, j; -+ struct nlattr *nl_combi, *nl_limits; -+ int i; - -- nl_combis = nla_nest_start_noflag(msg, -- NL80211_ATTR_INTERFACE_COMBINATIONS); -- if (!nl_combis) -+ nl_combi = nla_nest_start_noflag(msg, idx); -+ if (!nl_combi) - goto nla_put_failure; - -- for (i = 0; i < wiphy->n_iface_combinations; i++) { -- const struct ieee80211_iface_combination *c; -- struct nlattr *nl_combi, *nl_limits; -+ nl_limits = nla_nest_start_noflag(msg, NL80211_IFACE_COMB_LIMITS); -+ if (!nl_limits) -+ goto nla_put_failure; - -- c = &wiphy->iface_combinations[i]; -+ for (i = 0; i < c->n_limits; i++) { -+ struct nlattr *nl_limit; - -- nl_combi = nla_nest_start_noflag(msg, i + 1); -- if (!nl_combi) -+ nl_limit = nla_nest_start_noflag(msg, i + 1); -+ if (!nl_limit) - goto nla_put_failure; -- -- nl_limits = nla_nest_start_noflag(msg, -- NL80211_IFACE_COMB_LIMITS); -- if (!nl_limits) -+ if (nla_put_u32(msg, NL80211_IFACE_LIMIT_MAX, c->limits[i].max)) - goto nla_put_failure; -+ if (nl80211_put_iftypes(msg, NL80211_IFACE_LIMIT_TYPES, -+ c->limits[i].types)) -+ goto nla_put_failure; -+ nla_nest_end(msg, nl_limit); -+ } - -- for (j = 0; j < c->n_limits; j++) { -- struct nlattr *nl_limit; -+ nla_nest_end(msg, nl_limits); - -- nl_limit = nla_nest_start_noflag(msg, j + 1); -- if (!nl_limit) -- goto nla_put_failure; -- if (nla_put_u32(msg, NL80211_IFACE_LIMIT_MAX, -- c->limits[j].max)) -- goto nla_put_failure; -- if (nl80211_put_iftypes(msg, NL80211_IFACE_LIMIT_TYPES, -- c->limits[j].types)) -- goto nla_put_failure; -- nla_nest_end(msg, nl_limit); -- } -+ if (c->beacon_int_infra_match && -+ nla_put_flag(msg, NL80211_IFACE_COMB_STA_AP_BI_MATCH)) -+ goto nla_put_failure; -+ if (nla_put_u32(msg, NL80211_IFACE_COMB_NUM_CHANNELS, -+ c->num_different_channels) || -+ nla_put_u32(msg, NL80211_IFACE_COMB_MAXNUM, -+ c->max_interfaces)) -+ goto nla_put_failure; -+ if (large && -+ (nla_put_u32(msg, NL80211_IFACE_COMB_RADAR_DETECT_WIDTHS, -+ c->radar_detect_widths) || -+ nla_put_u32(msg, NL80211_IFACE_COMB_RADAR_DETECT_REGIONS, -+ c->radar_detect_regions))) -+ goto nla_put_failure; -+ if (c->beacon_int_min_gcd && -+ nla_put_u32(msg, NL80211_IFACE_COMB_BI_MIN_GCD, -+ c->beacon_int_min_gcd)) -+ goto nla_put_failure; - -- nla_nest_end(msg, nl_limits); -+ nla_nest_end(msg, nl_combi); - -- if (c->beacon_int_infra_match && -- nla_put_flag(msg, NL80211_IFACE_COMB_STA_AP_BI_MATCH)) -- goto nla_put_failure; -- if (nla_put_u32(msg, NL80211_IFACE_COMB_NUM_CHANNELS, -- c->num_different_channels) || -- nla_put_u32(msg, NL80211_IFACE_COMB_MAXNUM, -- c->max_interfaces)) -- goto nla_put_failure; -- if (large && -- (nla_put_u32(msg, NL80211_IFACE_COMB_RADAR_DETECT_WIDTHS, -- c->radar_detect_widths) || -- nla_put_u32(msg, NL80211_IFACE_COMB_RADAR_DETECT_REGIONS, -- c->radar_detect_regions))) -- goto nla_put_failure; -- if (c->beacon_int_min_gcd && -- nla_put_u32(msg, NL80211_IFACE_COMB_BI_MIN_GCD, -- c->beacon_int_min_gcd)) -- goto nla_put_failure; -+ return 0; -+nla_put_failure: -+ return -ENOBUFS; -+} - -- nla_nest_end(msg, nl_combi); -- } -+static int nl80211_put_iface_combinations(struct wiphy *wiphy, -+ struct sk_buff *msg, -+ bool large) -+{ -+ struct nlattr *nl_combis; -+ int i; -+ -+ nl_combis = nla_nest_start_noflag(msg, -+ NL80211_ATTR_INTERFACE_COMBINATIONS); -+ if (!nl_combis) -+ goto nla_put_failure; -+ -+ for (i = 0; i < wiphy->n_iface_combinations; i++) -+ if (nl80211_put_ifcomb_data(msg, large, i + 1, -+ &wiphy->iface_combinations[i])) -+ goto nla_put_failure; - - nla_nest_end(msg, nl_combis); - diff --git a/package/kernel/mac80211/patches/subsys/341-wifi-cfg80211-add-support-for-advertising-multiple-r.patch b/package/kernel/mac80211/patches/subsys/341-wifi-cfg80211-add-support-for-advertising-multiple-r.patch deleted file mode 100644 index 45349891b..000000000 --- a/package/kernel/mac80211/patches/subsys/341-wifi-cfg80211-add-support-for-advertising-multiple-r.patch +++ /dev/null @@ -1,348 +0,0 @@ -From: Felix Fietkau -Date: Wed, 22 May 2024 11:42:57 +0200 -Subject: [PATCH] wifi: cfg80211: add support for advertising multiple - radios belonging to a wiphy - -The prerequisite for MLO support in cfg80211/mac80211 is that all the links -participating in MLO must be from the same wiphy/ieee80211_hw. To meet this -expectation, some drivers may need to group multiple discrete hardware each -acting as a link in MLO under single wiphy. - -With this change, supported frequencies and interface combinations of each -individual radio are reported to user space. This allows user space to figure -out the limitations of what combination of channels can be used concurrently. - -Even for non-MLO devices, this improves support for devices capable of -running on multiple channels at the same time. - -Signed-off-by: Felix Fietkau ---- - ---- a/include/net/cfg80211.h -+++ b/include/net/cfg80211.h -@@ -5045,7 +5045,9 @@ struct ieee80211_iface_limit { - * struct ieee80211_iface_combination - possible interface combination - * - * With this structure the driver can describe which interface -- * combinations it supports concurrently. -+ * combinations it supports concurrently. When set in a struct wiphy_radio, -+ * the combinations refer to combinations of interfaces currently active on -+ * that radio. - * - * Examples: - * -@@ -5403,6 +5405,38 @@ struct wiphy_iftype_akm_suites { - int n_akm_suites; - }; - -+/** -+ * struct wiphy_radio_freq_range - wiphy frequency range -+ * @start_freq: start range edge frequency (kHz) -+ * @end_freq: end range edge frequency (kHz) -+ */ -+struct wiphy_radio_freq_range { -+ u32 start_freq; -+ u32 end_freq; -+}; -+ -+ -+/** -+ * struct wiphy_radio - physical radio of a wiphy -+ * This structure describes a physical radio belonging to a wiphy. -+ * It is used to describe concurrent-channel capabilities. Only one channel -+ * can be active on the radio described by struct wiphy_radio. -+ * -+ * @freq_range: frequency range that the radio can operate on. -+ * @n_freq_range: number of elements in @freq_range -+ * -+ * @iface_combinations: Valid interface combinations array, should not -+ * list single interface types. -+ * @n_iface_combinations: number of entries in @iface_combinations array. -+ */ -+struct wiphy_radio { -+ const struct wiphy_radio_freq_range *freq_range; -+ int n_freq_range; -+ -+ const struct ieee80211_iface_combination *iface_combinations; -+ int n_iface_combinations; -+}; -+ - #define CFG80211_HW_TIMESTAMP_ALL_PEERS 0xffff - - /** -@@ -5621,6 +5655,9 @@ struct wiphy_iftype_akm_suites { - * A value of %CFG80211_HW_TIMESTAMP_ALL_PEERS indicates the driver - * supports enabling HW timestamping for all peers (i.e. no need to - * specify a mac address). -+ * -+ * @radio: radios belonging to this wiphy -+ * @n_radio: number of radios - */ - struct wiphy { - struct mutex mtx; -@@ -5771,6 +5808,9 @@ struct wiphy { - - u16 hw_timestamp_max_peers; - -+ int n_radio; -+ const struct wiphy_radio *radio; -+ - char priv[] __aligned(NETDEV_ALIGN); - }; - ---- a/include/uapi/linux/nl80211.h -+++ b/include/uapi/linux/nl80211.h -@@ -2061,6 +2061,10 @@ enum nl80211_commands { - * @NL80211_ATTR_INTERFACE_COMBINATIONS: Nested attribute listing the supported - * interface combinations. In each nested item, it contains attributes - * defined in &enum nl80211_if_combination_attrs. -+ * If the wiphy uses multiple radios (@NL80211_ATTR_WIPHY_RADIOS is set), -+ * this attribute contains the interface combinations of the first radio. -+ * See @NL80211_ATTR_WIPHY_INTERFACE_COMBINATIONS for the global wiphy -+ * combinations for the sum of all radios. - * @NL80211_ATTR_SOFTWARE_IFTYPES: Nested attribute (just like - * %NL80211_ATTR_SUPPORTED_IFTYPES) containing the interface types that - * are managed in software: interfaces of these types aren't subject to -@@ -2856,6 +2860,14 @@ enum nl80211_commands { - * %NL80211_CMD_ASSOCIATE indicating the SPP A-MSDUs - * are used on this connection - * -+ * @NL80211_ATTR_WIPHY_RADIOS: Nested attribute describing physical radios -+ * belonging to this wiphy. See &enum nl80211_wiphy_radio_attrs. -+ * -+ * @NL80211_ATTR_WIPHY_INTERFACE_COMBINATIONS: Nested attribute listing the -+ * supported interface combinations for all radios combined. In each -+ * nested item, it contains attributes defined in -+ * &enum nl80211_if_combination_attrs. -+ * - * @NUM_NL80211_ATTR: total number of nl80211_attrs available - * @NL80211_ATTR_MAX: highest attribute number currently defined - * @__NL80211_ATTR_AFTER_LAST: internal use -@@ -3401,6 +3413,9 @@ enum nl80211_attrs { - - NL80211_ATTR_ASSOC_SPP_AMSDU, - -+ NL80211_ATTR_WIPHY_RADIOS, -+ NL80211_ATTR_WIPHY_INTERFACE_COMBINATIONS, -+ - /* add attributes here, update the policy in nl80211.c */ - - __NL80211_ATTR_AFTER_LAST, -@@ -7987,4 +8002,54 @@ enum nl80211_ap_settings_flags { - NL80211_AP_SETTINGS_SA_QUERY_OFFLOAD_SUPPORT = 1 << 1, - }; - -+/** -+ * enum nl80211_wiphy_radio_attrs - wiphy radio attributes -+ * -+ * @__NL80211_WIPHY_RADIO_ATTR_INVALID: Invalid -+ * -+ * @NL80211_WIPHY_RADIO_ATTR_INDEX: Index of this radio (u32) -+ * @NL80211_WIPHY_RADIO_ATTR_FREQ_RANGE: Frequency range supported by this -+ * radio. Attribute may be present multiple times. -+ * @NL80211_WIPHY_RADIO_ATTR_INTERFACE_COMBINATION: Supported interface -+ * combination for this radio. Attribute may be present multiple times -+ * and contains attributes defined in &enum nl80211_if_combination_attrs. -+ * -+ * @__NL80211_WIPHY_RADIO_ATTR_LAST: Internal -+ * @NL80211_WIPHY_RADIO_ATTR_MAX: Highest attribute -+ */ -+enum nl80211_wiphy_radio_attrs { -+ __NL80211_WIPHY_RADIO_ATTR_INVALID, -+ -+ NL80211_WIPHY_RADIO_ATTR_INDEX, -+ NL80211_WIPHY_RADIO_ATTR_FREQ_RANGE, -+ NL80211_WIPHY_RADIO_ATTR_INTERFACE_COMBINATION, -+ -+ /* keep last */ -+ __NL80211_WIPHY_RADIO_ATTR_LAST, -+ NL80211_WIPHY_RADIO_ATTR_MAX = __NL80211_WIPHY_RADIO_ATTR_LAST - 1, -+}; -+ -+/** -+ * enum nl80211_wiphy_radio_freq_range - wiphy radio frequency range -+ * -+ * @__NL80211_WIPHY_RADIO_FREQ_ATTR_INVALID: Invalid -+ * -+ * @NL80211_WIPHY_RADIO_FREQ_ATTR_START: Frequency range start (u32). -+ * The unit is kHz. -+ * @NL80211_WIPHY_RADIO_FREQ_ATTR_END: Frequency range end (u32). -+ * The unit is kHz. -+ * -+ * @__NL80211_WIPHY_RADIO_FREQ_ATTR_LAST: Internal -+ * @NL80211_WIPHY_RADIO_FREQ_ATTR_MAX: Highest attribute -+ */ -+enum nl80211_wiphy_radio_freq_range { -+ __NL80211_WIPHY_RADIO_FREQ_ATTR_INVALID, -+ -+ NL80211_WIPHY_RADIO_FREQ_ATTR_START, -+ NL80211_WIPHY_RADIO_FREQ_ATTR_END, -+ -+ __NL80211_WIPHY_RADIO_FREQ_ATTR_LAST, -+ NL80211_WIPHY_RADIO_FREQ_ATTR_MAX = __NL80211_WIPHY_RADIO_FREQ_ATTR_LAST - 1, -+}; -+ - #endif /* __LINUX_NL80211_H */ ---- a/net/wireless/nl80211.c -+++ b/net/wireless/nl80211.c -@@ -1621,16 +1621,18 @@ nla_put_failure: - } - - static int nl80211_put_ifcomb_data(struct sk_buff *msg, bool large, int idx, -- const struct ieee80211_iface_combination *c) -+ const struct ieee80211_iface_combination *c, -+ u16 nested) - { - struct nlattr *nl_combi, *nl_limits; - int i; - -- nl_combi = nla_nest_start_noflag(msg, idx); -+ nl_combi = nla_nest_start_noflag(msg, idx | nested); - if (!nl_combi) - goto nla_put_failure; - -- nl_limits = nla_nest_start_noflag(msg, NL80211_IFACE_COMB_LIMITS); -+ nl_limits = nla_nest_start_noflag(msg, NL80211_IFACE_COMB_LIMITS | -+ nested); - if (!nl_limits) - goto nla_put_failure; - -@@ -1678,19 +1680,26 @@ nla_put_failure: - - static int nl80211_put_iface_combinations(struct wiphy *wiphy, - struct sk_buff *msg, -- bool large) -+ int attr, int radio, -+ bool large, u16 nested) - { -+ const struct ieee80211_iface_combination *c; - struct nlattr *nl_combis; -- int i; -+ int i, n; - -- nl_combis = nla_nest_start_noflag(msg, -- NL80211_ATTR_INTERFACE_COMBINATIONS); -+ nl_combis = nla_nest_start_noflag(msg, attr | nested); - if (!nl_combis) - goto nla_put_failure; - -- for (i = 0; i < wiphy->n_iface_combinations; i++) -- if (nl80211_put_ifcomb_data(msg, large, i + 1, -- &wiphy->iface_combinations[i])) -+ if (radio >= 0) { -+ c = wiphy->radio[0].iface_combinations; -+ n = wiphy->radio[0].n_iface_combinations; -+ } else { -+ c = wiphy->iface_combinations; -+ n = wiphy->n_iface_combinations; -+ } -+ for (i = 0; i < n; i++) -+ if (nl80211_put_ifcomb_data(msg, large, i + 1, &c[i], nested)) - goto nla_put_failure; - - nla_nest_end(msg, nl_combis); -@@ -2397,6 +2406,80 @@ fail: - return -ENOBUFS; - } - -+static int nl80211_put_radio(struct wiphy *wiphy, struct sk_buff *msg, int idx) -+{ -+ const struct wiphy_radio *r = &wiphy->radio[idx]; -+ struct nlattr *radio, *freq; -+ int i; -+ -+ radio = nla_nest_start(msg, idx); -+ if (!radio) -+ return -ENOBUFS; -+ -+ if (nla_put_u32(msg, NL80211_WIPHY_RADIO_ATTR_INDEX, idx)) -+ goto nla_put_failure; -+ -+ for (i = 0; i < r->n_freq_range; i++) { -+ const struct wiphy_radio_freq_range *range = &r->freq_range[i]; -+ -+ freq = nla_nest_start(msg, NL80211_WIPHY_RADIO_ATTR_FREQ_RANGE); -+ if (!freq) -+ goto nla_put_failure; -+ -+ if (nla_put_u32(msg, NL80211_WIPHY_RADIO_FREQ_ATTR_START, -+ range->start_freq) || -+ nla_put_u32(msg, NL80211_WIPHY_RADIO_FREQ_ATTR_END, -+ range->end_freq)) -+ goto nla_put_failure; -+ -+ nla_nest_end(msg, freq); -+ } -+ -+ for (i = 0; i < r->n_iface_combinations; i++) -+ if (nl80211_put_ifcomb_data(msg, true, -+ NL80211_WIPHY_RADIO_ATTR_INTERFACE_COMBINATION, -+ &r->iface_combinations[i], -+ NLA_F_NESTED)) -+ goto nla_put_failure; -+ -+ nla_nest_end(msg, radio); -+ -+ return 0; -+ -+nla_put_failure: -+ return -ENOBUFS; -+} -+ -+static int nl80211_put_radios(struct wiphy *wiphy, struct sk_buff *msg) -+{ -+ struct nlattr *radios; -+ int i; -+ -+ if (!wiphy->n_radio) -+ return 0; -+ -+ radios = nla_nest_start(msg, NL80211_ATTR_WIPHY_RADIOS); -+ if (!radios) -+ return -ENOBUFS; -+ -+ for (i = 0; i < wiphy->n_radio; i++) -+ if (nl80211_put_radio(wiphy, msg, i)) -+ goto fail; -+ -+ nla_nest_end(msg, radios); -+ -+ if (nl80211_put_iface_combinations(wiphy, msg, -+ NL80211_ATTR_WIPHY_INTERFACE_COMBINATIONS, -+ -1, true, NLA_F_NESTED)) -+ return -ENOBUFS; -+ -+ return 0; -+ -+fail: -+ nla_nest_cancel(msg, radios); -+ return -ENOBUFS; -+} -+ - struct nl80211_dump_wiphy_state { - s64 filter_wiphy; - long start; -@@ -2692,7 +2775,9 @@ static int nl80211_send_wiphy(struct cfg - goto nla_put_failure; - - if (nl80211_put_iface_combinations(&rdev->wiphy, msg, -- state->split)) -+ NL80211_ATTR_INTERFACE_COMBINATIONS, -+ rdev->wiphy.n_radio ? 0 : -1, -+ state->split, 0)) - goto nla_put_failure; - - state->split_start++; -@@ -3006,6 +3091,12 @@ static int nl80211_send_wiphy(struct cfg - rdev->wiphy.hw_timestamp_max_peers)) - goto nla_put_failure; - -+ state->split_start++; -+ break; -+ case 17: -+ if (nl80211_put_radios(&rdev->wiphy, msg)) -+ goto nla_put_failure; -+ - /* done */ - state->split_start = 0; - break; diff --git a/package/kernel/mac80211/patches/subsys/342-wifi-cfg80211-extend-interface-combination-check-for.patch b/package/kernel/mac80211/patches/subsys/342-wifi-cfg80211-extend-interface-combination-check-for.patch deleted file mode 100644 index 0ba97a2c0..000000000 --- a/package/kernel/mac80211/patches/subsys/342-wifi-cfg80211-extend-interface-combination-check-for.patch +++ /dev/null @@ -1,172 +0,0 @@ -From: Felix Fietkau -Date: Tue, 4 Jun 2024 21:01:50 +0200 -Subject: [PATCH] wifi: cfg80211: extend interface combination check for - multi-radio - -Add a field in struct iface_combination_params to check per-radio -interface combinations instead of per-wiphy ones. - -Signed-off-by: Felix Fietkau ---- - ---- a/include/net/cfg80211.h -+++ b/include/net/cfg80211.h -@@ -1598,6 +1598,7 @@ struct cfg80211_color_change_settings { - * - * Used to pass interface combination parameters - * -+ * @radio_idx: wiphy radio index or -1 for global - * @num_different_channels: the number of different channels we want - * to use for verification - * @radar_detect: a bitmap where each bit corresponds to a channel -@@ -1611,6 +1612,7 @@ struct cfg80211_color_change_settings { - * the verification - */ - struct iface_combination_params { -+ int radio_idx; - int num_different_channels; - u8 radar_detect; - int iftype_num[NUM_NL80211_IFTYPES]; -@@ -4579,6 +4581,8 @@ struct mgmt_frame_regs { - * - * @set_hw_timestamp: Enable/disable HW timestamping of TM/FTM frames. - * @set_ttlm: set the TID to link mapping. -+ * @get_radio_mask: get bitmask of radios in use. -+ * (invoked with the wiphy mutex held) - */ - struct cfg80211_ops { - int (*suspend)(struct wiphy *wiphy, struct cfg80211_wowlan *wow); -@@ -4940,6 +4944,7 @@ struct cfg80211_ops { - struct cfg80211_set_hw_timestamp *hwts); - int (*set_ttlm)(struct wiphy *wiphy, struct net_device *dev, - struct cfg80211_ttlm_params *params); -+ u32 (*get_radio_mask)(struct wiphy *wiphy, struct net_device *dev); - }; - - /* ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -3930,6 +3930,7 @@ int ieee80211_check_combinations(struct - int total = 1; - struct iface_combination_params params = { - .radar_detect = radar_detect, -+ .radio_idx = -1, - }; - - lockdep_assert_wiphy(local->hw.wiphy); -@@ -4020,7 +4021,9 @@ int ieee80211_max_num_channels(struct ie - struct ieee80211_chanctx *ctx; - u32 max_num_different_channels = 1; - int err; -- struct iface_combination_params params = {0}; -+ struct iface_combination_params params = { -+ .radio_idx = -1, -+ }; - - lockdep_assert_wiphy(local->hw.wiphy); - ---- a/net/wireless/rdev-ops.h -+++ b/net/wireless/rdev-ops.h -@@ -1542,4 +1542,16 @@ rdev_set_ttlm(struct cfg80211_registered - - return ret; - } -+ -+static inline u32 -+rdev_get_radio_mask(struct cfg80211_registered_device *rdev, -+ struct net_device *dev) -+{ -+ struct wiphy *wiphy = &rdev->wiphy; -+ -+ if (!rdev->ops->get_radio_mask) -+ return 0; -+ -+ return rdev->ops->get_radio_mask(wiphy, dev); -+} - #endif /* __CFG80211_RDEV_OPS */ ---- a/net/wireless/util.c -+++ b/net/wireless/util.c -@@ -2305,13 +2305,16 @@ static int cfg80211_wdev_bi(struct wirel - - static void cfg80211_calculate_bi_data(struct wiphy *wiphy, u32 new_beacon_int, - u32 *beacon_int_gcd, -- bool *beacon_int_different) -+ bool *beacon_int_different, -+ int radio_idx) - { -+ struct cfg80211_registered_device *rdev; - struct wireless_dev *wdev; - - *beacon_int_gcd = 0; - *beacon_int_different = false; - -+ rdev = wiphy_to_rdev(wiphy); - list_for_each_entry(wdev, &wiphy->wdev_list, list) { - int wdev_bi; - -@@ -2319,6 +2322,11 @@ static void cfg80211_calculate_bi_data(s - if (wdev->valid_links) - continue; - -+ /* skip wdevs not active on the given wiphy radio */ -+ if (radio_idx >= 0 && -+ !(rdev_get_radio_mask(rdev, wdev->netdev) & BIT(radio_idx))) -+ continue; -+ - wdev_bi = cfg80211_wdev_bi(wdev); - - if (!wdev_bi) -@@ -2366,14 +2374,19 @@ int cfg80211_iter_combinations(struct wi - void *data), - void *data) - { -+ const struct wiphy_radio *radio = NULL; -+ const struct ieee80211_iface_combination *c, *cs; - const struct ieee80211_regdomain *regdom; - enum nl80211_dfs_regions region = 0; -- int i, j, iftype; -+ int i, j, n, iftype; - int num_interfaces = 0; - u32 used_iftypes = 0; - u32 beacon_int_gcd; - bool beacon_int_different; - -+ if (params->radio_idx >= 0) -+ radio = &wiphy->radio[params->radio_idx]; -+ - /* - * This is a bit strange, since the iteration used to rely only on - * the data given by the driver, but here it now relies on context, -@@ -2385,7 +2398,8 @@ int cfg80211_iter_combinations(struct wi - * interfaces (while being brought up) and channel/radar data. - */ - cfg80211_calculate_bi_data(wiphy, params->new_beacon_int, -- &beacon_int_gcd, &beacon_int_different); -+ &beacon_int_gcd, &beacon_int_different, -+ params->radio_idx); - - if (params->radar_detect) { - rcu_read_lock(); -@@ -2402,13 +2416,18 @@ int cfg80211_iter_combinations(struct wi - used_iftypes |= BIT(iftype); - } - -- for (i = 0; i < wiphy->n_iface_combinations; i++) { -- const struct ieee80211_iface_combination *c; -+ if (radio) { -+ cs = radio->iface_combinations; -+ n = radio->n_iface_combinations; -+ } else { -+ cs = wiphy->iface_combinations; -+ n = wiphy->n_iface_combinations; -+ } -+ for (i = 0; i < n; i++) { - struct ieee80211_iface_limit *limits; - u32 all_iftypes = 0; - -- c = &wiphy->iface_combinations[i]; -- -+ c = &cs[i]; - if (num_interfaces > c->max_interfaces) - continue; - if (params->num_different_channels > c->num_different_channels) diff --git a/package/kernel/mac80211/patches/subsys/343-wifi-cfg80211-add-helper-for-checking-if-a-chandef-i.patch b/package/kernel/mac80211/patches/subsys/343-wifi-cfg80211-add-helper-for-checking-if-a-chandef-i.patch deleted file mode 100644 index d115dd2e5..000000000 --- a/package/kernel/mac80211/patches/subsys/343-wifi-cfg80211-add-helper-for-checking-if-a-chandef-i.patch +++ /dev/null @@ -1,69 +0,0 @@ -From: Felix Fietkau -Date: Fri, 7 Jun 2024 17:58:54 +0200 -Subject: [PATCH] wifi: cfg80211: add helper for checking if a chandef is - valid on a radio - -Check if the full channel width is in the radio's frequency range. - -Signed-off-by: Felix Fietkau ---- - ---- a/include/net/cfg80211.h -+++ b/include/net/cfg80211.h -@@ -6485,6 +6485,15 @@ static inline bool cfg80211_channel_is_p - } - - /** -+ * cfg80211_radio_chandef_valid - Check if the radio supports the chandef -+ * -+ * @radio: wiphy radio -+ * @chandef: chandef for current channel -+ */ -+bool cfg80211_radio_chandef_valid(const struct wiphy_radio *radio, -+ const struct cfg80211_chan_def *chandef); -+ -+/** - * ieee80211_get_response_rate - get basic rate for a given rate - * - * @sband: the band to look for rates in ---- a/net/wireless/util.c -+++ b/net/wireless/util.c -@@ -2884,3 +2884,38 @@ cfg80211_get_iftype_ext_capa(struct wiph - return NULL; - } - EXPORT_SYMBOL(cfg80211_get_iftype_ext_capa); -+ -+static bool -+ieee80211_radio_freq_range_valid(const struct wiphy_radio *radio, -+ u32 freq, u32 width) -+{ -+ const struct wiphy_radio_freq_range *r; -+ int i; -+ -+ for (i = 0; i < radio->n_freq_range; i++) { -+ r = &radio->freq_range[i]; -+ if (freq - width / 2 >= r->start_freq && -+ freq + width / 2 <= r->end_freq) -+ return true; -+ } -+ -+ return false; -+} -+ -+bool cfg80211_radio_chandef_valid(const struct wiphy_radio *radio, -+ const struct cfg80211_chan_def *chandef) -+{ -+ u32 freq, width; -+ -+ freq = ieee80211_chandef_to_khz(chandef); -+ width = nl80211_chan_width_to_mhz(chandef->width); -+ if (!ieee80211_radio_freq_range_valid(radio, freq, width)) -+ return false; -+ -+ freq = MHZ_TO_KHZ(chandef->center_freq2); -+ if (freq && !ieee80211_radio_freq_range_valid(radio, freq, width)) -+ return false; -+ -+ return true; -+} -+EXPORT_SYMBOL(cfg80211_radio_chandef_valid); diff --git a/package/kernel/mac80211/patches/subsys/344-wifi-mac80211-add-support-for-DFS-with-multiple-radi.patch b/package/kernel/mac80211/patches/subsys/344-wifi-mac80211-add-support-for-DFS-with-multiple-radi.patch deleted file mode 100644 index 18634fe14..000000000 --- a/package/kernel/mac80211/patches/subsys/344-wifi-mac80211-add-support-for-DFS-with-multiple-radi.patch +++ /dev/null @@ -1,88 +0,0 @@ -From: Felix Fietkau -Date: Thu, 6 Jun 2024 12:19:08 +0200 -Subject: [PATCH] wifi: mac80211: add support for DFS with multiple - radios - -DFS can be supported with multi-channel combinations, as long as each DFS -capable radio only supports one channel. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/mac80211/main.c -+++ b/net/mac80211/main.c -@@ -1084,6 +1084,27 @@ static int ieee80211_init_cipher_suites( - return 0; - } - -+static bool -+ieee80211_ifcomb_check(const struct ieee80211_iface_combination *c, int n_comb) -+{ -+ int i, j; -+ -+ for (i = 0; i < n_comb; i++, c++) { -+ /* DFS is not supported with multi-channel combinations yet */ -+ if (c->radar_detect_widths && -+ c->num_different_channels > 1) -+ return false; -+ -+ /* mac80211 doesn't support more than one IBSS interface */ -+ for (j = 0; j < c->n_limits; j++) -+ if ((c->limits[j].types & BIT(NL80211_IFTYPE_ADHOC)) && -+ c->limits[j].max > 1) -+ return false; -+ } -+ -+ return true; -+} -+ - int ieee80211_register_hw(struct ieee80211_hw *hw) - { - struct ieee80211_local *local = hw_to_local(hw); -@@ -1173,17 +1194,20 @@ int ieee80211_register_hw(struct ieee802 - if (comb->num_different_channels > 1) - return -EINVAL; - } -- } else { -- /* DFS is not supported with multi-channel combinations yet */ -- for (i = 0; i < local->hw.wiphy->n_iface_combinations; i++) { -- const struct ieee80211_iface_combination *comb; -+ } - -- comb = &local->hw.wiphy->iface_combinations[i]; -+ if (hw->wiphy->n_radio) { -+ for (i = 0; i < hw->wiphy->n_radio; i++) { -+ const struct wiphy_radio *radio = &hw->wiphy->radio[i]; - -- if (comb->radar_detect_widths && -- comb->num_different_channels > 1) -+ if (!ieee80211_ifcomb_check(radio->iface_combinations, -+ radio->n_iface_combinations)) - return -EINVAL; - } -+ } else { -+ if (!ieee80211_ifcomb_check(hw->wiphy->iface_combinations, -+ hw->wiphy->n_iface_combinations)) -+ return -EINVAL; - } - - /* Only HW csum features are currently compatible with mac80211 */ -@@ -1313,18 +1337,6 @@ int ieee80211_register_hw(struct ieee802 - hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_MONITOR); - hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR); - -- /* mac80211 doesn't support more than one IBSS interface right now */ -- for (i = 0; i < hw->wiphy->n_iface_combinations; i++) { -- const struct ieee80211_iface_combination *c; -- int j; -- -- c = &hw->wiphy->iface_combinations[i]; -- -- for (j = 0; j < c->n_limits; j++) -- if ((c->limits[j].types & BIT(NL80211_IFTYPE_ADHOC)) && -- c->limits[j].max > 1) -- return -EINVAL; -- } - - local->int_scan_req = kzalloc(sizeof(*local->int_scan_req) + - sizeof(void *) * channels, GFP_KERNEL); diff --git a/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-add-radio-index-to-ieee80211_chanctx_c.patch b/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-add-radio-index-to-ieee80211_chanctx_c.patch deleted file mode 100644 index b832a2a12..000000000 --- a/package/kernel/mac80211/patches/subsys/345-wifi-mac80211-add-radio-index-to-ieee80211_chanctx_c.patch +++ /dev/null @@ -1,66 +0,0 @@ -From: Felix Fietkau -Date: Wed, 5 Jun 2024 10:41:34 +0200 -Subject: [PATCH] wifi: mac80211: add radio index to - ieee80211_chanctx_conf - -Will be used to explicitly assign a channel context to a wiphy radio. - -Signed-off-by: Felix Fietkau ---- - ---- a/include/net/mac80211.h -+++ b/include/net/mac80211.h -@@ -250,6 +250,7 @@ struct ieee80211_chan_req { - * @min_def: the minimum channel definition currently required. - * @ap: the channel definition the AP actually is operating as, - * for use with (wider bandwidth) OFDMA -+ * @radio_idx: index of the wiphy radio used used for this channel - * @rx_chains_static: The number of RX chains that must always be - * active on the channel to receive MIMO transmissions - * @rx_chains_dynamic: The number of RX chains that must be enabled -@@ -264,6 +265,7 @@ struct ieee80211_chanctx_conf { - struct cfg80211_chan_def min_def; - struct cfg80211_chan_def ap; - -+ int radio_idx; - u8 rx_chains_static, rx_chains_dynamic; - - bool radar_enabled; ---- a/net/mac80211/chan.c -+++ b/net/mac80211/chan.c -@@ -623,7 +623,8 @@ ieee80211_chanctx_radar_required(struct - static struct ieee80211_chanctx * - ieee80211_alloc_chanctx(struct ieee80211_local *local, - const struct ieee80211_chan_req *chanreq, -- enum ieee80211_chanctx_mode mode) -+ enum ieee80211_chanctx_mode mode, -+ int radio_idx) - { - struct ieee80211_chanctx *ctx; - -@@ -641,6 +642,7 @@ ieee80211_alloc_chanctx(struct ieee80211 - ctx->conf.rx_chains_dynamic = 1; - ctx->mode = mode; - ctx->conf.radar_enabled = false; -+ ctx->conf.radio_idx = radio_idx; - _ieee80211_recalc_chanctx_min_def(local, ctx, NULL); - - return ctx; -@@ -680,7 +682,7 @@ ieee80211_new_chanctx(struct ieee80211_l - - lockdep_assert_wiphy(local->hw.wiphy); - -- ctx = ieee80211_alloc_chanctx(local, chanreq, mode); -+ ctx = ieee80211_alloc_chanctx(local, chanreq, mode, -1); - if (!ctx) - return ERR_PTR(-ENOMEM); - -@@ -1098,7 +1100,7 @@ int ieee80211_link_reserve_chanctx(struc - !list_empty(&curr_ctx->reserved_links)) - return -EBUSY; - -- new_ctx = ieee80211_alloc_chanctx(local, chanreq, mode); -+ new_ctx = ieee80211_alloc_chanctx(local, chanreq, mode, -1); - if (!new_ctx) - return -ENOMEM; - diff --git a/package/kernel/mac80211/patches/subsys/346-wifi-mac80211-extend-ifcomb-check-functions-for-mult.patch b/package/kernel/mac80211/patches/subsys/346-wifi-mac80211-extend-ifcomb-check-functions-for-mult.patch deleted file mode 100644 index 168cf6fad..000000000 --- a/package/kernel/mac80211/patches/subsys/346-wifi-mac80211-extend-ifcomb-check-functions-for-mult.patch +++ /dev/null @@ -1,322 +0,0 @@ -From: Felix Fietkau -Date: Tue, 4 Jun 2024 21:48:48 +0200 -Subject: [PATCH] wifi: mac80211: extend ifcomb check functions for - multi-radio - -Add support for counting global and per-radio max/current number of -channels, as well as checking radio-specific interface combinations. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/mac80211/cfg.c -+++ b/net/mac80211/cfg.c -@@ -263,7 +263,7 @@ static int ieee80211_start_p2p_device(st - - lockdep_assert_wiphy(sdata->local->hw.wiphy); - -- ret = ieee80211_check_combinations(sdata, NULL, 0, 0); -+ ret = ieee80211_check_combinations(sdata, NULL, 0, 0, -1); - if (ret < 0) - return ret; - -@@ -285,7 +285,7 @@ static int ieee80211_start_nan(struct wi - - lockdep_assert_wiphy(sdata->local->hw.wiphy); - -- ret = ieee80211_check_combinations(sdata, NULL, 0, 0); -+ ret = ieee80211_check_combinations(sdata, NULL, 0, 0, -1); - if (ret < 0) - return ret; - -@@ -3992,7 +3992,7 @@ __ieee80211_channel_switch(struct wiphy - goto out; - - /* if reservation is invalid then this will fail */ -- err = ieee80211_check_combinations(sdata, NULL, chanctx->mode, 0); -+ err = ieee80211_check_combinations(sdata, NULL, chanctx->mode, 0, -1); - if (err) { - ieee80211_link_unreserve_chanctx(link_data); - goto out; -@@ -5161,4 +5161,5 @@ const struct cfg80211_ops mac80211_confi - .del_link_station = ieee80211_del_link_station, - .set_hw_timestamp = ieee80211_set_hw_timestamp, - .set_ttlm = ieee80211_set_ttlm, -+ .get_radio_mask = ieee80211_get_radio_mask, - }; ---- a/net/mac80211/chan.c -+++ b/net/mac80211/chan.c -@@ -47,24 +47,29 @@ int ieee80211_chanctx_refcount(struct ie - ieee80211_chanctx_num_reserved(local, ctx); - } - --static int ieee80211_num_chanctx(struct ieee80211_local *local) -+static int ieee80211_num_chanctx(struct ieee80211_local *local, int radio_idx) - { - struct ieee80211_chanctx *ctx; - int num = 0; - - lockdep_assert_wiphy(local->hw.wiphy); - -- list_for_each_entry(ctx, &local->chanctx_list, list) -+ list_for_each_entry(ctx, &local->chanctx_list, list) { -+ if (radio_idx >= 0 && ctx->conf.radio_idx != radio_idx) -+ continue; - num++; -+ } - - return num; - } - --static bool ieee80211_can_create_new_chanctx(struct ieee80211_local *local) -+static bool ieee80211_can_create_new_chanctx(struct ieee80211_local *local, -+ int radio_idx) - { - lockdep_assert_wiphy(local->hw.wiphy); - -- return ieee80211_num_chanctx(local) < ieee80211_max_num_channels(local); -+ return ieee80211_num_chanctx(local, radio_idx) < -+ ieee80211_max_num_channels(local, radio_idx); - } - - static struct ieee80211_chanctx * -@@ -1045,7 +1050,7 @@ int ieee80211_link_reserve_chanctx(struc - - new_ctx = ieee80211_find_reservation_chanctx(local, chanreq, mode); - if (!new_ctx) { -- if (ieee80211_can_create_new_chanctx(local)) { -+ if (ieee80211_can_create_new_chanctx(local, -1)) { - new_ctx = ieee80211_new_chanctx(local, chanreq, mode); - if (IS_ERR(new_ctx)) - return PTR_ERR(new_ctx); -@@ -1736,7 +1741,7 @@ int ieee80211_link_use_channel(struct ie - link->radar_required = ret; - - ret = ieee80211_check_combinations(sdata, &chanreq->oper, mode, -- radar_detect_width); -+ radar_detect_width, -1); - if (ret < 0) - goto out; - ---- a/net/mac80211/ibss.c -+++ b/net/mac80211/ibss.c -@@ -1745,7 +1745,7 @@ int ieee80211_ibss_join(struct ieee80211 - IEEE80211_CHANCTX_SHARED : IEEE80211_CHANCTX_EXCLUSIVE; - - ret = ieee80211_check_combinations(sdata, ¶ms->chandef, chanmode, -- radar_detect_width); -+ radar_detect_width, -1); - if (ret < 0) - return ret; - ---- a/net/mac80211/ieee80211_i.h -+++ b/net/mac80211/ieee80211_i.h -@@ -2596,8 +2596,9 @@ void ieee80211_recalc_dtim(struct ieee80 - int ieee80211_check_combinations(struct ieee80211_sub_if_data *sdata, - const struct cfg80211_chan_def *chandef, - enum ieee80211_chanctx_mode chanmode, -- u8 radar_detect); --int ieee80211_max_num_channels(struct ieee80211_local *local); -+ u8 radar_detect, int radio_idx); -+int ieee80211_max_num_channels(struct ieee80211_local *local, int radio_idx); -+u32 ieee80211_get_radio_mask(struct wiphy *wiphy, struct net_device *dev); - void ieee80211_recalc_chanctx_chantype(struct ieee80211_local *local, - struct ieee80211_chanctx *ctx); - ---- a/net/mac80211/iface.c -+++ b/net/mac80211/iface.c -@@ -397,7 +397,7 @@ static int ieee80211_check_concurrent_if - } - } - -- return ieee80211_check_combinations(sdata, NULL, 0, 0); -+ return ieee80211_check_combinations(sdata, NULL, 0, 0, -1); - } - - static int ieee80211_check_queues(struct ieee80211_sub_if_data *sdata, ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -3918,20 +3918,103 @@ static u8 ieee80211_chanctx_radar_detect - return radar_detect; - } - -+static u32 -+__ieee80211_get_radio_mask(struct ieee80211_sub_if_data *sdata) -+{ -+ struct ieee80211_bss_conf *link_conf; -+ struct ieee80211_chanctx_conf *conf; -+ unsigned int link_id; -+ u32 mask = 0; -+ -+ for_each_vif_active_link(&sdata->vif, link_conf, link_id) { -+ conf = sdata_dereference(link_conf->chanctx_conf, sdata); -+ if (!conf || conf->radio_idx < 0) -+ continue; -+ -+ mask |= BIT(conf->radio_idx); -+ } -+ -+ return mask; -+} -+ -+u32 ieee80211_get_radio_mask(struct wiphy *wiphy, struct net_device *dev) -+{ -+ struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); -+ -+ return __ieee80211_get_radio_mask(sdata); -+} -+ -+static bool -+ieee80211_sdata_uses_radio(struct ieee80211_sub_if_data *sdata, int radio_idx) -+{ -+ if (radio_idx < 0) -+ return true; -+ -+ return __ieee80211_get_radio_mask(sdata) & BIT(radio_idx); -+} -+ -+static int -+ieee80211_fill_ifcomb_params(struct ieee80211_local *local, -+ struct iface_combination_params *params, -+ const struct cfg80211_chan_def *chandef, -+ struct ieee80211_sub_if_data *sdata) -+{ -+ struct ieee80211_sub_if_data *sdata_iter; -+ struct ieee80211_chanctx *ctx; -+ int total = !!sdata; -+ -+ list_for_each_entry(ctx, &local->chanctx_list, list) { -+ if (ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED) -+ continue; -+ -+ if (params->radio_idx >= 0 && -+ ctx->conf.radio_idx != params->radio_idx) -+ continue; -+ -+ params->radar_detect |= -+ ieee80211_chanctx_radar_detect(local, ctx); -+ -+ if (chandef && ctx->mode != IEEE80211_CHANCTX_EXCLUSIVE && -+ cfg80211_chandef_compatible(chandef, &ctx->conf.def)) -+ continue; -+ -+ params->num_different_channels++; -+ } -+ -+ list_for_each_entry(sdata_iter, &local->interfaces, list) { -+ struct wireless_dev *wdev_iter; -+ -+ wdev_iter = &sdata_iter->wdev; -+ -+ if (sdata_iter == sdata || -+ !ieee80211_sdata_running(sdata_iter) || -+ cfg80211_iftype_allowed(local->hw.wiphy, -+ wdev_iter->iftype, 0, 1)) -+ continue; -+ -+ if (!ieee80211_sdata_uses_radio(sdata_iter, params->radio_idx)) -+ continue; -+ -+ params->iftype_num[wdev_iter->iftype]++; -+ total++; -+ } -+ -+ return total; -+} -+ - int ieee80211_check_combinations(struct ieee80211_sub_if_data *sdata, - const struct cfg80211_chan_def *chandef, - enum ieee80211_chanctx_mode chanmode, -- u8 radar_detect) -+ u8 radar_detect, int radio_idx) - { -+ bool shared = chanmode == IEEE80211_CHANCTX_SHARED; - struct ieee80211_local *local = sdata->local; -- struct ieee80211_sub_if_data *sdata_iter; - enum nl80211_iftype iftype = sdata->wdev.iftype; -- struct ieee80211_chanctx *ctx; -- int total = 1; - struct iface_combination_params params = { - .radar_detect = radar_detect, -- .radio_idx = -1, -+ .radio_idx = radio_idx, - }; -+ int total; - - lockdep_assert_wiphy(local->hw.wiphy); - -@@ -3968,37 +4051,9 @@ int ieee80211_check_combinations(struct - if (iftype != NL80211_IFTYPE_UNSPECIFIED) - params.iftype_num[iftype] = 1; - -- list_for_each_entry(ctx, &local->chanctx_list, list) { -- if (ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED) -- continue; -- params.radar_detect |= -- ieee80211_chanctx_radar_detect(local, ctx); -- if (ctx->mode == IEEE80211_CHANCTX_EXCLUSIVE) { -- params.num_different_channels++; -- continue; -- } -- if (chandef && chanmode == IEEE80211_CHANCTX_SHARED && -- cfg80211_chandef_compatible(chandef, -- &ctx->conf.def)) -- continue; -- params.num_different_channels++; -- } -- -- list_for_each_entry_rcu(sdata_iter, &local->interfaces, list) { -- struct wireless_dev *wdev_iter; -- -- wdev_iter = &sdata_iter->wdev; -- -- if (sdata_iter == sdata || -- !ieee80211_sdata_running(sdata_iter) || -- cfg80211_iftype_allowed(local->hw.wiphy, -- wdev_iter->iftype, 0, 1)) -- continue; -- -- params.iftype_num[wdev_iter->iftype]++; -- total++; -- } -- -+ total = ieee80211_fill_ifcomb_params(local, ¶ms, -+ shared ? chandef : NULL, -+ sdata); - if (total == 1 && !params.radar_detect) - return 0; - -@@ -4015,30 +4070,17 @@ ieee80211_iter_max_chans(const struct ie - c->num_different_channels); - } - --int ieee80211_max_num_channels(struct ieee80211_local *local) -+int ieee80211_max_num_channels(struct ieee80211_local *local, int radio_idx) - { -- struct ieee80211_sub_if_data *sdata; -- struct ieee80211_chanctx *ctx; - u32 max_num_different_channels = 1; - int err; - struct iface_combination_params params = { -- .radio_idx = -1, -+ .radio_idx = radio_idx, - }; - - lockdep_assert_wiphy(local->hw.wiphy); - -- list_for_each_entry(ctx, &local->chanctx_list, list) { -- if (ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED) -- continue; -- -- params.num_different_channels++; -- -- params.radar_detect |= -- ieee80211_chanctx_radar_detect(local, ctx); -- } -- -- list_for_each_entry_rcu(sdata, &local->interfaces, list) -- params.iftype_num[sdata->wdev.iftype]++; -+ ieee80211_fill_ifcomb_params(local, ¶ms, NULL, NULL); - - err = cfg80211_iter_combinations(local->hw.wiphy, ¶ms, - ieee80211_iter_max_chans, diff --git a/package/kernel/mac80211/patches/subsys/347-wifi-mac80211-move-code-in-ieee80211_link_reserve_ch.patch b/package/kernel/mac80211/patches/subsys/347-wifi-mac80211-move-code-in-ieee80211_link_reserve_ch.patch deleted file mode 100644 index 9a8506760..000000000 --- a/package/kernel/mac80211/patches/subsys/347-wifi-mac80211-move-code-in-ieee80211_link_reserve_ch.patch +++ /dev/null @@ -1,175 +0,0 @@ -From: Felix Fietkau -Date: Wed, 5 Jun 2024 10:49:22 +0200 -Subject: [PATCH] wifi: mac80211: move code in - ieee80211_link_reserve_chanctx to a helper - -Reduces indentation in preparation for further changes - -Signed-off-by: Felix Fietkau ---- - ---- a/net/mac80211/chan.c -+++ b/net/mac80211/chan.c -@@ -1033,6 +1033,71 @@ int ieee80211_link_unreserve_chanctx(str - return 0; - } - -+static struct ieee80211_chanctx * -+ieee80211_replace_chanctx(struct ieee80211_local *local, -+ const struct ieee80211_chan_req *chanreq, -+ enum ieee80211_chanctx_mode mode, -+ struct ieee80211_chanctx *curr_ctx) -+{ -+ struct ieee80211_chanctx *new_ctx, *ctx; -+ -+ if (!curr_ctx || (curr_ctx->replace_state == -+ IEEE80211_CHANCTX_WILL_BE_REPLACED) || -+ !list_empty(&curr_ctx->reserved_links)) { -+ /* -+ * Another link already requested this context for a -+ * reservation. Find another one hoping all links assigned -+ * to it will also switch soon enough. -+ * -+ * TODO: This needs a little more work as some cases -+ * (more than 2 chanctx capable devices) may fail which could -+ * otherwise succeed provided some channel context juggling was -+ * performed. -+ * -+ * Consider ctx1..3, link1..6, each ctx has 2 links. link1 and -+ * link2 from ctx1 request new different chandefs starting 2 -+ * in-place reserations with ctx4 and ctx5 replacing ctx1 and -+ * ctx2 respectively. Next link5 and link6 from ctx3 reserve -+ * ctx4. If link3 and link4 remain on ctx2 as they are then this -+ * fails unless `replace_ctx` from ctx5 is replaced with ctx3. -+ */ -+ list_for_each_entry(ctx, &local->chanctx_list, list) { -+ if (ctx->replace_state != -+ IEEE80211_CHANCTX_REPLACE_NONE) -+ continue; -+ -+ if (!list_empty(&ctx->reserved_links)) -+ continue; -+ -+ curr_ctx = ctx; -+ break; -+ } -+ } -+ -+ /* -+ * If that's true then all available contexts already have reservations -+ * and cannot be used. -+ */ -+ if (!curr_ctx || (curr_ctx->replace_state == -+ IEEE80211_CHANCTX_WILL_BE_REPLACED) || -+ !list_empty(&curr_ctx->reserved_links)) -+ return ERR_PTR(-EBUSY); -+ -+ new_ctx = ieee80211_alloc_chanctx(local, chanreq, mode, -1); -+ if (!new_ctx) -+ return ERR_PTR(-ENOMEM); -+ -+ new_ctx->replace_ctx = curr_ctx; -+ new_ctx->replace_state = IEEE80211_CHANCTX_REPLACES_OTHER; -+ -+ curr_ctx->replace_ctx = new_ctx; -+ curr_ctx->replace_state = IEEE80211_CHANCTX_WILL_BE_REPLACED; -+ -+ list_add_rcu(&new_ctx->list, &local->chanctx_list); -+ -+ return new_ctx; -+} -+ - int ieee80211_link_reserve_chanctx(struct ieee80211_link_data *link, - const struct ieee80211_chan_req *chanreq, - enum ieee80211_chanctx_mode mode, -@@ -1040,7 +1105,7 @@ int ieee80211_link_reserve_chanctx(struc - { - struct ieee80211_sub_if_data *sdata = link->sdata; - struct ieee80211_local *local = sdata->local; -- struct ieee80211_chanctx *new_ctx, *curr_ctx, *ctx; -+ struct ieee80211_chanctx *new_ctx, *curr_ctx; - - lockdep_assert_wiphy(local->hw.wiphy); - -@@ -1050,75 +1115,13 @@ int ieee80211_link_reserve_chanctx(struc - - new_ctx = ieee80211_find_reservation_chanctx(local, chanreq, mode); - if (!new_ctx) { -- if (ieee80211_can_create_new_chanctx(local, -1)) { -+ if (ieee80211_can_create_new_chanctx(local, -1)) - new_ctx = ieee80211_new_chanctx(local, chanreq, mode); -- if (IS_ERR(new_ctx)) -- return PTR_ERR(new_ctx); -- } else { -- if (!curr_ctx || -- (curr_ctx->replace_state == -- IEEE80211_CHANCTX_WILL_BE_REPLACED) || -- !list_empty(&curr_ctx->reserved_links)) { -- /* -- * Another link already requested this context -- * for a reservation. Find another one hoping -- * all links assigned to it will also switch -- * soon enough. -- * -- * TODO: This needs a little more work as some -- * cases (more than 2 chanctx capable devices) -- * may fail which could otherwise succeed -- * provided some channel context juggling was -- * performed. -- * -- * Consider ctx1..3, link1..6, each ctx has 2 -- * links. link1 and link2 from ctx1 request new -- * different chandefs starting 2 in-place -- * reserations with ctx4 and ctx5 replacing -- * ctx1 and ctx2 respectively. Next link5 and -- * link6 from ctx3 reserve ctx4. If link3 and -- * link4 remain on ctx2 as they are then this -- * fails unless `replace_ctx` from ctx5 is -- * replaced with ctx3. -- */ -- list_for_each_entry(ctx, &local->chanctx_list, -- list) { -- if (ctx->replace_state != -- IEEE80211_CHANCTX_REPLACE_NONE) -- continue; -- -- if (!list_empty(&ctx->reserved_links)) -- continue; -- -- curr_ctx = ctx; -- break; -- } -- } -- -- /* -- * If that's true then all available contexts already -- * have reservations and cannot be used. -- */ -- if (!curr_ctx || -- (curr_ctx->replace_state == -- IEEE80211_CHANCTX_WILL_BE_REPLACED) || -- !list_empty(&curr_ctx->reserved_links)) -- return -EBUSY; -- -- new_ctx = ieee80211_alloc_chanctx(local, chanreq, mode, -1); -- if (!new_ctx) -- return -ENOMEM; -- -- new_ctx->replace_ctx = curr_ctx; -- new_ctx->replace_state = -- IEEE80211_CHANCTX_REPLACES_OTHER; -- -- curr_ctx->replace_ctx = new_ctx; -- curr_ctx->replace_state = -- IEEE80211_CHANCTX_WILL_BE_REPLACED; -- -- list_add_rcu(&new_ctx->list, &local->chanctx_list); -- } -+ else -+ new_ctx = ieee80211_replace_chanctx(local, chanreq, -+ mode, curr_ctx); -+ if (IS_ERR(new_ctx)) -+ return PTR_ERR(new_ctx); - } - - list_add(&link->reserved_chanctx_list, &new_ctx->reserved_links); diff --git a/package/kernel/mac80211/patches/subsys/348-wifi-mac80211-add-wiphy-radio-assignment-and-validat.patch b/package/kernel/mac80211/patches/subsys/348-wifi-mac80211-add-wiphy-radio-assignment-and-validat.patch deleted file mode 100644 index c559f070e..000000000 --- a/package/kernel/mac80211/patches/subsys/348-wifi-mac80211-add-wiphy-radio-assignment-and-validat.patch +++ /dev/null @@ -1,132 +0,0 @@ -From: Felix Fietkau -Date: Wed, 5 Jun 2024 18:39:55 +0200 -Subject: [PATCH] wifi: mac80211: add wiphy radio assignment and - validation - -Validate number of channels and interface combinations per radio. -Assign each channel context to a radio. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/mac80211/chan.c -+++ b/net/mac80211/chan.c -@@ -680,14 +680,15 @@ static int ieee80211_add_chanctx(struct - static struct ieee80211_chanctx * - ieee80211_new_chanctx(struct ieee80211_local *local, - const struct ieee80211_chan_req *chanreq, -- enum ieee80211_chanctx_mode mode) -+ enum ieee80211_chanctx_mode mode, -+ int radio_idx) - { - struct ieee80211_chanctx *ctx; - int err; - - lockdep_assert_wiphy(local->hw.wiphy); - -- ctx = ieee80211_alloc_chanctx(local, chanreq, mode, -1); -+ ctx = ieee80211_alloc_chanctx(local, chanreq, mode, radio_idx); - if (!ctx) - return ERR_PTR(-ENOMEM); - -@@ -1040,6 +1041,8 @@ ieee80211_replace_chanctx(struct ieee802 - struct ieee80211_chanctx *curr_ctx) - { - struct ieee80211_chanctx *new_ctx, *ctx; -+ struct wiphy *wiphy = local->hw.wiphy; -+ const struct wiphy_radio *radio; - - if (!curr_ctx || (curr_ctx->replace_state == - IEEE80211_CHANCTX_WILL_BE_REPLACED) || -@@ -1069,6 +1072,12 @@ ieee80211_replace_chanctx(struct ieee802 - if (!list_empty(&ctx->reserved_links)) - continue; - -+ if (ctx->conf.radio_idx >= 0) { -+ radio = &wiphy->radio[ctx->conf.radio_idx]; -+ if (!cfg80211_radio_chandef_valid(radio, &chanreq->oper)) -+ continue; -+ } -+ - curr_ctx = ctx; - break; - } -@@ -1098,6 +1107,34 @@ ieee80211_replace_chanctx(struct ieee802 - return new_ctx; - } - -+static bool -+ieee80211_find_available_radio(struct ieee80211_local *local, -+ const struct ieee80211_chan_req *chanreq, -+ int *radio_idx) -+{ -+ struct wiphy *wiphy = local->hw.wiphy; -+ const struct wiphy_radio *radio; -+ int i; -+ -+ *radio_idx = -1; -+ if (!wiphy->n_radio) -+ return true; -+ -+ for (i = 0; i < wiphy->n_radio; i++) { -+ radio = &wiphy->radio[i]; -+ if (!cfg80211_radio_chandef_valid(radio, &chanreq->oper)) -+ continue; -+ -+ if (!ieee80211_can_create_new_chanctx(local, i)) -+ continue; -+ -+ *radio_idx = i; -+ return true; -+ } -+ -+ return false; -+} -+ - int ieee80211_link_reserve_chanctx(struct ieee80211_link_data *link, - const struct ieee80211_chan_req *chanreq, - enum ieee80211_chanctx_mode mode, -@@ -1106,6 +1143,7 @@ int ieee80211_link_reserve_chanctx(struc - struct ieee80211_sub_if_data *sdata = link->sdata; - struct ieee80211_local *local = sdata->local; - struct ieee80211_chanctx *new_ctx, *curr_ctx; -+ int radio_idx; - - lockdep_assert_wiphy(local->hw.wiphy); - -@@ -1115,8 +1153,10 @@ int ieee80211_link_reserve_chanctx(struc - - new_ctx = ieee80211_find_reservation_chanctx(local, chanreq, mode); - if (!new_ctx) { -- if (ieee80211_can_create_new_chanctx(local, -1)) -- new_ctx = ieee80211_new_chanctx(local, chanreq, mode); -+ if (ieee80211_can_create_new_chanctx(local, -1) && -+ ieee80211_find_available_radio(local, chanreq, &radio_idx)) -+ new_ctx = ieee80211_new_chanctx(local, chanreq, mode, -+ radio_idx); - else - new_ctx = ieee80211_replace_chanctx(local, chanreq, - mode, curr_ctx); -@@ -1724,6 +1764,7 @@ int ieee80211_link_use_channel(struct ie - struct ieee80211_local *local = sdata->local; - struct ieee80211_chanctx *ctx; - u8 radar_detect_width = 0; -+ int radio_idx; - int ret; - - lockdep_assert_wiphy(local->hw.wiphy); -@@ -1751,8 +1792,12 @@ int ieee80211_link_use_channel(struct ie - __ieee80211_link_release_channel(link); - - ctx = ieee80211_find_chanctx(local, chanreq, mode); -- if (!ctx) -- ctx = ieee80211_new_chanctx(local, chanreq, mode); -+ if (!ctx) { -+ if (!ieee80211_find_available_radio(local, chanreq, &radio_idx)) -+ ctx = ERR_PTR(-EBUSY); -+ else -+ ctx = ieee80211_new_chanctx(local, chanreq, mode, radio_idx); -+ } - if (IS_ERR(ctx)) { - ret = PTR_ERR(ctx); - goto out; diff --git a/package/kernel/mac80211/patches/subsys/349-wifi-mac80211_hwsim-add-support-for-multi-radio-wiph.patch b/package/kernel/mac80211/patches/subsys/349-wifi-mac80211_hwsim-add-support-for-multi-radio-wiph.patch deleted file mode 100644 index 91fe6d83d..000000000 --- a/package/kernel/mac80211/patches/subsys/349-wifi-mac80211_hwsim-add-support-for-multi-radio-wiph.patch +++ /dev/null @@ -1,199 +0,0 @@ -From: Felix Fietkau -Date: Tue, 11 Jun 2024 09:02:55 +0200 -Subject: [PATCH] wifi: mac80211_hwsim: add support for multi-radio wiphy - -This registers one wiphy radio per supported band. Number of different -channels is set per radio. - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/wireless/virtual/mac80211_hwsim.c -+++ b/drivers/net/wireless/virtual/mac80211_hwsim.c -@@ -69,6 +69,10 @@ static bool mlo; - module_param(mlo, bool, 0444); - MODULE_PARM_DESC(mlo, "Support MLO"); - -+static bool multi_radio; -+module_param(multi_radio, bool, 0444); -+MODULE_PARM_DESC(mlo, "Support Multiple Radios per wiphy"); -+ - /** - * enum hwsim_regtest - the type of regulatory tests we offer - * -@@ -669,6 +673,10 @@ struct mac80211_hwsim_data { - struct ieee80211_iface_limit if_limits[3]; - int n_if_limits; - -+ struct ieee80211_iface_combination if_combination_radio; -+ struct wiphy_radio_freq_range radio_range[NUM_NL80211_BANDS]; -+ struct wiphy_radio radio[NUM_NL80211_BANDS]; -+ - u32 ciphers[ARRAY_SIZE(hwsim_ciphers)]; - - struct mac_address addresses[2]; -@@ -917,6 +925,7 @@ static const struct nla_policy hwsim_gen - [HWSIM_ATTR_MLO_SUPPORT] = { .type = NLA_FLAG }, - [HWSIM_ATTR_PMSR_SUPPORT] = NLA_POLICY_NESTED(hwsim_pmsr_capa_policy), - [HWSIM_ATTR_PMSR_RESULT] = NLA_POLICY_NESTED(hwsim_pmsr_peers_result_policy), -+ [HWSIM_ATTR_MULTI_RADIO] = { .type = NLA_FLAG }, - }; - - #if IS_REACHABLE(CONFIG_VIRTIO) -@@ -4007,6 +4016,7 @@ struct hwsim_new_radio_params { - bool reg_strict; - bool p2p_device; - bool use_chanctx; -+ bool multi_radio; - bool destroy_on_close; - const char *hwname; - bool no_vif; -@@ -4083,6 +4093,12 @@ static int append_radio_msg(struct sk_bu - return ret; - } - -+ if (param->multi_radio) { -+ ret = nla_put_flag(skb, HWSIM_ATTR_MULTI_RADIO); -+ if (ret < 0) -+ return ret; -+ } -+ - if (param->hwname) { - ret = nla_put(skb, HWSIM_ATTR_RADIO_NAME, - strlen(param->hwname), param->hwname); -@@ -5099,6 +5115,7 @@ static int mac80211_hwsim_new_radio(stru - struct net *net; - int idx, i; - int n_limits = 0; -+ int n_bands = 0; - - if (WARN_ON(param->channels > 1 && !param->use_chanctx)) - return -EINVAL; -@@ -5202,22 +5219,22 @@ static int mac80211_hwsim_new_radio(stru - n_limits++; - } - -+ data->if_combination.radar_detect_widths = -+ BIT(NL80211_CHAN_WIDTH_5) | -+ BIT(NL80211_CHAN_WIDTH_10) | -+ BIT(NL80211_CHAN_WIDTH_20_NOHT) | -+ BIT(NL80211_CHAN_WIDTH_20) | -+ BIT(NL80211_CHAN_WIDTH_40) | -+ BIT(NL80211_CHAN_WIDTH_80) | -+ BIT(NL80211_CHAN_WIDTH_160); -+ - if (data->use_chanctx) { - hw->wiphy->max_scan_ssids = 255; - hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; - hw->wiphy->max_remain_on_channel_duration = 1000; -- data->if_combination.radar_detect_widths = 0; - data->if_combination.num_different_channels = data->channels; - } else { - data->if_combination.num_different_channels = 1; -- data->if_combination.radar_detect_widths = -- BIT(NL80211_CHAN_WIDTH_5) | -- BIT(NL80211_CHAN_WIDTH_10) | -- BIT(NL80211_CHAN_WIDTH_20_NOHT) | -- BIT(NL80211_CHAN_WIDTH_20) | -- BIT(NL80211_CHAN_WIDTH_40) | -- BIT(NL80211_CHAN_WIDTH_80) | -- BIT(NL80211_CHAN_WIDTH_160); - } - - if (!n_limits) { -@@ -5333,6 +5350,9 @@ static int mac80211_hwsim_new_radio(stru - - for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { - struct ieee80211_supported_band *sband = &data->bands[band]; -+ struct wiphy_radio_freq_range *radio_range; -+ const struct ieee80211_channel *c; -+ struct wiphy_radio *radio; - - sband->band = band; - -@@ -5406,8 +5426,36 @@ static int mac80211_hwsim_new_radio(stru - mac80211_hwsim_sband_capab(sband); - - hw->wiphy->bands[band] = sband; -+ -+ if (!param->multi_radio) -+ continue; -+ -+ c = sband->channels; -+ radio_range = &data->radio_range[n_bands]; -+ radio_range->start_freq = ieee80211_channel_to_khz(c) - 10000; -+ -+ c += sband->n_channels - 1; -+ radio_range->end_freq = ieee80211_channel_to_khz(c) + 10000; -+ -+ radio = &data->radio[n_bands++]; -+ radio->freq_range = radio_range; -+ radio->n_freq_range = 1; -+ radio->iface_combinations = &data->if_combination_radio; -+ radio->n_iface_combinations = 1; - } - -+ if (param->multi_radio) { -+ hw->wiphy->radio = data->radio; -+ hw->wiphy->n_radio = n_bands; -+ -+ memcpy(&data->if_combination_radio, &data->if_combination, -+ sizeof(data->if_combination)); -+ data->if_combination.num_different_channels *= n_bands; -+ } -+ -+ if (data->use_chanctx) -+ data->if_combination.radar_detect_widths = 0; -+ - /* By default all radios belong to the first group */ - data->group = 1; - mutex_init(&data->mutex); -@@ -6025,6 +6073,9 @@ static int hwsim_new_radio_nl(struct sk_ - else - param.use_chanctx = (param.channels > 1); - -+ if (info->attrs[HWSIM_ATTR_MULTI_RADIO]) -+ param.multi_radio = true; -+ - if (info->attrs[HWSIM_ATTR_REG_HINT_ALPHA2]) - param.reg_alpha2 = - nla_data(info->attrs[HWSIM_ATTR_REG_HINT_ALPHA2]); -@@ -6105,7 +6156,7 @@ static int hwsim_new_radio_nl(struct sk_ - - param.mlo = info->attrs[HWSIM_ATTR_MLO_SUPPORT]; - -- if (param.mlo) -+ if (param.mlo || param.multi_radio) - param.use_chanctx = true; - - if (info->attrs[HWSIM_ATTR_RADIO_NAME]) { -@@ -6802,7 +6853,8 @@ static int __init init_mac80211_hwsim(vo - - param.p2p_device = support_p2p_device; - param.mlo = mlo; -- param.use_chanctx = channels > 1 || mlo; -+ param.multi_radio = multi_radio; -+ param.use_chanctx = channels > 1 || mlo || multi_radio; - param.iftypes = HWSIM_IFTYPE_SUPPORT_MASK; - if (param.p2p_device) - param.iftypes |= BIT(NL80211_IFTYPE_P2P_DEVICE); ---- a/drivers/net/wireless/virtual/mac80211_hwsim.h -+++ b/drivers/net/wireless/virtual/mac80211_hwsim.h -@@ -157,6 +157,9 @@ enum hwsim_commands { - * to provide details about peer measurement request (nl80211_peer_measurement_attrs) - * @HWSIM_ATTR_PMSR_RESULT: nested attributed used with %HWSIM_CMD_REPORT_PMSR - * to provide peer measurement result (nl80211_peer_measurement_attrs) -+ * @HWSIM_ATTR_MULTI_RADIO: Register multiple wiphy radios (flag). -+ * Adds one radio for each band. Number of supported channels will be set for -+ * each radio instead of for the wiphy. - * @__HWSIM_ATTR_MAX: enum limit - */ - enum hwsim_attrs { -@@ -189,6 +192,7 @@ enum hwsim_attrs { - HWSIM_ATTR_PMSR_SUPPORT, - HWSIM_ATTR_PMSR_REQUEST, - HWSIM_ATTR_PMSR_RESULT, -+ HWSIM_ATTR_MULTI_RADIO, - __HWSIM_ATTR_MAX, - }; - #define HWSIM_ATTR_MAX (__HWSIM_ATTR_MAX - 1) diff --git a/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch b/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch index 7a96f9f2b..c38fa13f0 100644 --- a/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch +++ b/package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch @@ -16,7 +16,7 @@ and we should ignore this. --- a/net/wireless/core.c +++ b/net/wireless/core.c -@@ -651,21 +651,6 @@ static int wiphy_verify_combinations(str +@@ -614,21 +614,6 @@ static int wiphy_verify_combinations(str c->limits[j].max > 1)) return -EINVAL; diff --git a/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch b/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch new file mode 100644 index 000000000..5d8742ba9 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch @@ -0,0 +1,36 @@ +--- a/net/mac80211/vht.c ++++ b/net/mac80211/vht.c +@@ -135,7 +135,8 @@ ieee80211_vht_cap_ie_to_sta_vht_cap(stru + have_80mhz = false; + for (i = 0; i < sband->n_channels; i++) { + if (sband->channels[i].flags & (IEEE80211_CHAN_DISABLED | +- IEEE80211_CHAN_NO_80MHZ)) ++ IEEE80211_CHAN_NO_80MHZ) & ++ (sband->band != NL80211_BAND_2GHZ)) + continue; + + have_80mhz = true; +--- a/net/mac80211/util.c ++++ b/net/mac80211/util.c +@@ -1955,7 +1955,8 @@ static int ieee80211_build_preq_ies_band + /* Check if any channel in this sband supports at least 80 MHz */ + for (i = 0; i < sband->n_channels; i++) { + if (sband->channels[i].flags & (IEEE80211_CHAN_DISABLED | +- IEEE80211_CHAN_NO_80MHZ)) ++ IEEE80211_CHAN_NO_80MHZ) & ++ (sband->band != NL80211_BAND_2GHZ)) + continue; + + have_80mhz = true; +--- a/net/mac80211/mlme.c ++++ b/net/mac80211/mlme.c +@@ -4744,7 +4744,8 @@ static int ieee80211_prep_channel(struct + have_80mhz = false; + for (i = 0; i < sband->n_channels; i++) { + if (sband->channels[i].flags & (IEEE80211_CHAN_DISABLED | +- IEEE80211_CHAN_NO_80MHZ)) ++ IEEE80211_CHAN_NO_80MHZ) & ++ (sband->band != NL80211_BAND_2GHZ)) + continue; + + have_80mhz = true; diff --git a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch new file mode 100644 index 000000000..bc5e7e76c --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch @@ -0,0 +1,162 @@ +--- a/include/net/cfg80211.h ++++ b/include/net/cfg80211.h +@@ -4084,6 +4084,7 @@ struct mgmt_frame_regs { + * (as advertised by the nl80211 feature flag.) + * @get_tx_power: store the current TX power into the dbm variable; + * return 0 if successful ++ * @set_antenna_gain: set antenna gain to reduce maximum tx power if necessary + * + * @rfkill_poll: polls the hw rfkill line, use cfg80211 reporting + * functions to adjust rfkill hw state +@@ -4434,6 +4435,7 @@ struct cfg80211_ops { + enum nl80211_tx_power_setting type, int mbm); + int (*get_tx_power)(struct wiphy *wiphy, struct wireless_dev *wdev, + int *dbm); ++ int (*set_antenna_gain)(struct wiphy *wiphy, int dbi); + + void (*rfkill_poll)(struct wiphy *wiphy); + +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -1677,6 +1677,7 @@ enum ieee80211_smps_mode { + * + * @power_level: requested transmit power (in dBm), backward compatibility + * value only that is set to the minimum of all interfaces ++ * @max_antenna_gain: maximum antenna gain adjusted by user config (in dBi) + * + * @chandef: the channel definition to tune to + * @radar_enabled: whether radar detection is enabled +@@ -1697,6 +1698,7 @@ enum ieee80211_smps_mode { + struct ieee80211_conf { + u32 flags; + int power_level, dynamic_ps_timeout; ++ int max_antenna_gain; + + u16 listen_interval; + u8 ps_dtim_period; +--- a/include/uapi/linux/nl80211.h ++++ b/include/uapi/linux/nl80211.h +@@ -2749,6 +2749,9 @@ enum nl80211_commands { + * When used with %NL80211_CMD_FRAME_TX_STATUS, indicates the ack RX + * timestamp. When used with %NL80211_CMD_FRAME RX notification, indicates + * the incoming frame RX timestamp. ++ * @NL80211_ATTR_WIPHY_ANTENNA_GAIN: Configured antenna gain. Used to reduce ++ * transmit power to stay within regulatory limits. u32, dBi. ++ * + * @NUM_NL80211_ATTR: total number of nl80211_attrs available + * @NL80211_ATTR_MAX: highest attribute number currently defined + * @__NL80211_ATTR_AFTER_LAST: internal use +@@ -3277,6 +3280,8 @@ enum nl80211_attrs { + NL80211_ATTR_TX_HW_TIMESTAMP, + NL80211_ATTR_RX_HW_TIMESTAMP, + ++ NL80211_ATTR_WIPHY_ANTENNA_GAIN, ++ + /* add attributes here, update the policy in nl80211.c */ + + __NL80211_ATTR_AFTER_LAST, +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -3046,6 +3046,19 @@ static int ieee80211_get_tx_power(struct + return 0; + } + ++static int ieee80211_set_antenna_gain(struct wiphy *wiphy, int dbi) ++{ ++ struct ieee80211_local *local = wiphy_priv(wiphy); ++ ++ if (dbi < 0) ++ return -EINVAL; ++ ++ local->user_antenna_gain = dbi; ++ ieee80211_hw_config(local, 0); ++ ++ return 0; ++} ++ + static void ieee80211_rfkill_poll(struct wiphy *wiphy) + { + struct ieee80211_local *local = wiphy_priv(wiphy); +@@ -4956,6 +4969,7 @@ const struct cfg80211_ops mac80211_confi + .set_wiphy_params = ieee80211_set_wiphy_params, + .set_tx_power = ieee80211_set_tx_power, + .get_tx_power = ieee80211_get_tx_power, ++ .set_antenna_gain = ieee80211_set_antenna_gain, + .rfkill_poll = ieee80211_rfkill_poll, + CFG80211_TESTMODE_CMD(ieee80211_testmode_cmd) + CFG80211_TESTMODE_DUMP(ieee80211_testmode_dump) +--- a/net/mac80211/ieee80211_i.h ++++ b/net/mac80211/ieee80211_i.h +@@ -1542,6 +1542,7 @@ struct ieee80211_local { + int dynamic_ps_forced_timeout; + + int user_power_level; /* in dBm, for all interfaces */ ++ int user_antenna_gain; /* in dBi */ + + enum ieee80211_smps_mode smps_mode; + +--- a/net/mac80211/main.c ++++ b/net/mac80211/main.c +@@ -96,7 +96,7 @@ static u32 ieee80211_hw_conf_chan(struct + struct ieee80211_sub_if_data *sdata; + struct cfg80211_chan_def chandef = {}; + u32 changed = 0; +- int power; ++ int power, max_power; + u32 offchannel_flag; + + offchannel_flag = local->hw.conf.flags & IEEE80211_CONF_OFFCHANNEL; +@@ -157,6 +157,12 @@ static u32 ieee80211_hw_conf_chan(struct + } + rcu_read_unlock(); + ++ max_power = chandef.chan->max_reg_power; ++ if (local->user_antenna_gain > 0) { ++ max_power -= local->user_antenna_gain; ++ power = min(power, max_power); ++ } ++ + if (local->hw.conf.power_level != power) { + changed |= IEEE80211_CONF_CHANGE_POWER; + local->hw.conf.power_level = power; +@@ -762,6 +768,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_ + IEEE80211_RADIOTAP_MCS_HAVE_BW; + local->hw.radiotap_vht_details = IEEE80211_RADIOTAP_VHT_KNOWN_GI | + IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH; ++ local->user_antenna_gain = 0; + local->hw.uapsd_queues = IEEE80211_DEFAULT_UAPSD_QUEUES; + local->hw.uapsd_max_sp_len = IEEE80211_DEFAULT_MAX_SP_LEN; + local->hw.max_mtu = IEEE80211_MAX_DATA_LEN; +--- a/net/wireless/nl80211.c ++++ b/net/wireless/nl80211.c +@@ -823,6 +823,7 @@ static const struct nla_policy nl80211_p + [NL80211_ATTR_MLD_ADDR] = NLA_POLICY_EXACT_LEN(ETH_ALEN), + [NL80211_ATTR_MLO_SUPPORT] = { .type = NLA_FLAG }, + [NL80211_ATTR_MAX_NUM_AKM_SUITES] = { .type = NLA_REJECT }, ++ [NL80211_ATTR_WIPHY_ANTENNA_GAIN] = { .type = NLA_U32 }, + }; + + /* policy for the key attributes */ +@@ -3535,6 +3536,22 @@ static int nl80211_set_wiphy(struct sk_b + if (result) + goto out; + } ++ ++ if (info->attrs[NL80211_ATTR_WIPHY_ANTENNA_GAIN]) { ++ int idx, dbi = 0; ++ ++ if (!rdev->ops->set_antenna_gain) { ++ result = -EOPNOTSUPP; ++ goto out; ++ } ++ ++ idx = NL80211_ATTR_WIPHY_ANTENNA_GAIN; ++ dbi = nla_get_u32(info->attrs[idx]); ++ ++ result = rdev->ops->set_antenna_gain(&rdev->wiphy, dbi); ++ if (result) ++ goto out; ++ } + + if (info->attrs[NL80211_ATTR_WIPHY_TX_POWER_SETTING]) { + struct wireless_dev *txp_wdev = wdev; diff --git a/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch b/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch index e64ca1753..2bc11efd0 100644 --- a/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch +++ b/package/kernel/mac80211/patches/subsys/780-avoid-crashing-missing-band.patch @@ -18,7 +18,7 @@ Signed-off-by: David Bauer --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c -@@ -2459,6 +2459,13 @@ static void sta_stats_decode_rate(struct +@@ -2422,6 +2422,13 @@ static void sta_stats_decode_rate(struct sband = local->hw.wiphy->bands[band]; diff --git a/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch b/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch new file mode 100644 index 000000000..20f857f2d --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch @@ -0,0 +1,11 @@ +--- a/backport-include/linux/etherdevice.h ++++ b/backport-include/linux/etherdevice.h +@@ -39,7 +39,7 @@ static inline void u64_to_ether_addr(u64 + } + #endif /* LINUX_VERSION_IS_LESS(4,11,0) */ + +-#if LINUX_VERSION_IS_LESS(5,15,0) ++#if LINUX_VERSION_IS_LESS(5,4,0) + /** + * eth_hw_addr_set - Assign Ethernet address to a net_device + * @dev: pointer to net_device structure diff --git a/package/kernel/mac80211/patches/subsys/900-add-eth-ieee80211_bss_conf.patch b/package/kernel/mac80211/patches/subsys/900-add-eth-ieee80211_bss_conf.patch new file mode 100644 index 000000000..55e2e1b73 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/900-add-eth-ieee80211_bss_conf.patch @@ -0,0 +1,55 @@ +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -673,6 +673,12 @@ + * @he_full_ul_mumimo: does this BSS support the reception (AP) or transmission + * (non-AP STA) of an HE TB PPDU on an RU that spans the entire PPDU + * bandwidth ++ * @eht_su_beamformer: in AP-mode, does this BSS enable operation as an EHT SU ++ * beamformer ++ * @eht_su_beamformee: in AP-mode, does this BSS enable operation as an EHT SU ++ * beamformee ++ * @eht_mu_beamformer: in AP-mode, does this BSS enable operation as an EHT MU ++ * beamformer + */ + struct ieee80211_bss_conf { + const u8 *bssid; +@@ -758,6 +764,9 @@ + bool he_su_beamformee; + bool he_mu_beamformer; + bool he_full_ul_mumimo; ++ bool eht_su_beamformer; ++ bool eht_su_beamformee; ++ bool eht_mu_beamformer; + }; + + /** +--- a/net/mac80211/cfg.c ++++ b/net/mac80211/cfg.c +@@ -1307,6 +1307,27 @@ + IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; + } + ++ if (params->eht_cap) { ++ if (!link_conf->he_support) ++ return -EOPNOTSUPP; ++ link_conf->eht_support = true; ++ link_conf->eht_su_beamformer = ++ params->eht_cap->fixed.phy_cap_info[0] & ++ IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER; ++ link_conf->eht_su_beamformee = ++ params->eht_cap->fixed.phy_cap_info[0] & ++ IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; ++ link_conf->eht_mu_beamformer = ++ params->eht_cap->fixed.phy_cap_info[7] & ++ (IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | ++ IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | ++ IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ); ++ } else { ++ link_conf->eht_su_beamformer = false; ++ link_conf->eht_su_beamformee = false; ++ link_conf->eht_mu_beamformer = false; ++ } ++ + if (sdata->vif.type == NL80211_IFTYPE_AP && + params->mbssid_config.tx_wdev) { + err = ieee80211_set_ap_mbssid_options(sdata, diff --git a/package/kernel/mac80211/patches/subsys/910-fix-build-for-kernel-5.10.patch b/package/kernel/mac80211/patches/subsys/910-fix-build-for-kernel-5.10.patch deleted file mode 100644 index 78c77ff81..000000000 --- a/package/kernel/mac80211/patches/subsys/910-fix-build-for-kernel-5.10.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/backport-include/net/dropreason-core.h -+++ b/backport-include/net/dropreason-core.h -@@ -21,6 +21,17 @@ - #define SKB_CONSUMED SKB_DROP_REASON_NOT_SPECIFIED - #endif - -+#if LINUX_VERSION_IS_LESS(5,15,0) -+#define SKB_DROP_REASON_NOT_SPECIFIED 0 -+#define SKB_DROP_REASON_MAX 12 -+static inline void kfree_skb_reason(struct sk_buff *skb, int reason) -+{ -+ if (!skb_unref(skb)) -+ return; -+ __kfree_skb(skb); -+} -+#endif -+ - #if LINUX_VERSION_IS_LESS(6,4,0) - #define SKB_DROP_REASON_SUBSYS_MASK 0xffff0000 - #define SKB_DROP_REASON_SUBSYS_SHIFT 16 diff --git a/package/kernel/mac80211/patches/subsys/920-mac80211-mtk-ACS-channel-time-is-reset-by-ch_restore.patch b/package/kernel/mac80211/patches/subsys/920-mac80211-mtk-ACS-channel-time-is-reset-by-ch_restore.patch deleted file mode 100644 index 71095caf0..000000000 --- a/package/kernel/mac80211/patches/subsys/920-mac80211-mtk-ACS-channel-time-is-reset-by-ch_restore.patch +++ /dev/null @@ -1,58 +0,0 @@ -From e86b89d026fa963ff6c789747b9b373884956157 Mon Sep 17 00:00:00 2001 -From: Evelyn Tsai -Date: Fri, 1 Dec 2023 08:48:35 +0800 -Subject: [PATCH] mac80211: mtk: ACS channel time is reset by ch_restore - -Issue: -There's a chance that the channel time for duty channel is zero in ACS -scan. - -Root cause: -The chan_stat may be reset when restore to duty channel. -Mac80211 will notify to hostapd when scan done and then restore to duty -channel. -And mt76 will clear scan flag after restore done. -If hostapd get the chan_stat before channel_restore, will get the -correct channel time; -If hostapd get the chan_stat after channel_restore, will get zero -channel time; - -Solution: -When channel switch, will check the mac80211 scan state but not the mt76 scan flag. -Mac80211 scan state will be set in scanning, and will be reset after -scan done and before restore to duty channel. - -Signed-off-by: fancy.liu ---- - include/net/mac80211.h | 6 ++++++ - net/mac80211/util.c | 8 ++++++++ - 2 files changed, 14 insertions(+) - ---- a/include/net/mac80211.h -+++ b/include/net/mac80211.h -@@ -7444,4 +7444,10 @@ int ieee80211_set_active_links(struct ie - void ieee80211_set_active_links_async(struct ieee80211_vif *vif, - u16 active_links); - -+/** -+ * ieee80211_get_scanning - get scanning bitmask -+ * -+ * @hw: pointer as obtained from ieee80211_alloc_hw() -+ */ -+unsigned long ieee80211_get_scanning(struct ieee80211_hw *hw); - #endif /* MAC80211_H */ ---- a/net/mac80211/util.c -+++ b/net/mac80211/util.c -@@ -5147,3 +5147,11 @@ void ieee80211_fragment_element(struct s - - *len_pos = elem_len; - } -+ -+unsigned long ieee80211_get_scanning(struct ieee80211_hw *hw) -+{ -+ struct ieee80211_local *local = hw_to_local(hw); -+ -+ return local->scanning; -+} -+EXPORT_SYMBOL(ieee80211_get_scanning); -\ No newline at end of file diff --git a/package/kernel/mac80211/realtek.mk b/package/kernel/mac80211/realtek.mk index 28ea6a657..2f1fa8376 100644 --- a/package/kernel/mac80211/realtek.mk +++ b/package/kernel/mac80211/realtek.mk @@ -1,9 +1,7 @@ PKG_DRIVERS += \ rtlwifi rtlwifi-pci rtlwifi-btcoexist rtlwifi-usb rtl8192c-common \ - rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723-common rtl8723be rtl8723bs rtl8821ae \ - rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-8821c rtw88-8822b rtw88-8822c \ - rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \ - rtw88-8822ce rtw88-8822cu rtw88-8723de + rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723bs rtl8821ae \ + rtl8xxxu rtw88 config-$(call config_package,rtlwifi) += RTL_CARDS RTLWIFI config-$(call config_package,rtlwifi-pci) += RTLWIFI_PCI @@ -20,26 +18,11 @@ config-$(CONFIG_PACKAGE_RTLWIFI_DEBUG) += RTLWIFI_DEBUG config-$(call config_package,rtl8xxxu) += RTL8XXXU config-y += RTL8XXXU_UNTESTED -config-$(call config_package,rtl8723-common) += RTL8723_COMMON -config-$(call config_package,rtl8723be) += RTL8723BE - config-$(call config_package,rtl8723bs) += RTL8723BS config-y += STAGING -config-$(call config_package,rtw88) += RTW88 RTW88_CORE -config-$(call config_package,rtw88-pci) += RTW88_PCI -config-$(call config_package,rtw88-usb) += RTW88_USB -config-$(call config_package,rtw88-8821c) += RTW88_8821C -config-$(call config_package,rtw88-8821ce) += RTW88_8821CE -config-$(call config_package,rtw88-8821cu) += RTW88_8821CU -config-$(call config_package,rtw88-8822b) += RTW88_8822B -config-$(call config_package,rtw88-8822be) += RTW88_8822BE -config-$(call config_package,rtw88-8822bu) += RTW88_8822BU -config-$(call config_package,rtw88-8822c) += RTW88_8822C -config-$(call config_package,rtw88-8822ce) += RTW88_8822CE -config-$(call config_package,rtw88-8822cu) += RTW88_8822CU -config-$(call config_package,rtw88-8723d) += RTW88_8723D -config-$(call config_package,rtw88-8723de) += RTW88_8723DE +config-$(call config_package,rtw88) += RTW88 RTW88_CORE RTW88_PCI +config-y += RTW88_8821CE RTW88_8822BE RTW88_8822CE RTW88_8723DE config-$(CONFIG_PACKAGE_RTW88_DEBUG) += RTW88_DEBUG config-$(CONFIG_PACKAGE_RTW88_DEBUGFS) += RTW88_DEBUGFS @@ -55,7 +38,7 @@ endef define KernelPackage/rtlwifi $(call KernelPackage/mac80211/Default) TITLE:=Realtek common driver part - DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 + DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 +@DRIVER_11N_SUPPORT FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtlwifi.ko HIDDEN:=1 endef @@ -185,137 +168,20 @@ endef define KernelPackage/rtw88 $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTW88 common part - DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_core.ko - AUTOLOAD:=$(call AutoProbe,rtw88_core) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-pci - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTW88 PCI chips support - DEPENDS+= @PCI_SUPPORT +kmod-rtw88 - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_pci.ko - AUTOLOAD:=$(call AutoProbe,rtw88_pci) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-usb - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTW88 USB chips support - DEPENDS+= @USB_SUPPORT +kmod-rtw88 +kmod-usb-core - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_usb.ko - AUTOLOAD:=$(call AutoProbe,rtw88_usb) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-8821c - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8821C family support - DEPENDS+= +kmod-rtw88 +rtl8821ce-firmware +@DRIVER_11AC_SUPPORT - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8821c.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8821c) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-8822b - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8822B family support - DEPENDS+= +kmod-rtw88 +rtl8822be-firmware +@DRIVER_11AC_SUPPORT - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822b.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8822b) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-8822c - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8822C family support - DEPENDS+= +kmod-rtw88 +rtl8822ce-firmware +@DRIVER_11AC_SUPPORT - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822c.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8822c) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-8723d - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8723D family support - DEPENDS+= +kmod-rtw88 +rtl8723de-firmware - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723d.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8723d) - HIDDEN:=1 -endef - -define KernelPackage/rtw88-8821ce - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8821CE support - DEPENDS+= +kmod-rtw88-pci +kmod-rtw88-8821c - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8821ce.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8821ce) -endef - -define KernelPackage/rtw88-8821cu - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8821CU support - DEPENDS+= +kmod-rtw88-usb +kmod-rtw88-8821c - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8821cu.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8821cu) -endef - -define KernelPackage/rtw88-8822be - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8822BE support - DEPENDS+= +kmod-rtw88-pci +kmod-rtw88-8822b - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822be.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8822be) -endef - -define KernelPackage/rtw88-8822bu - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8822BU support - DEPENDS+= +kmod-rtw88-usb +kmod-rtw88-8822b - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822bu.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8822bu) -endef - -define KernelPackage/rtw88-8822ce - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8822CE support - DEPENDS+= +kmod-rtw88-pci +kmod-rtw88-8822c - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822ce.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8822ce) -endef - -define KernelPackage/rtw88-8822cu - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8822CU support - DEPENDS+= +kmod-rtw88-usb +kmod-rtw88-8822c - FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822cu.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8822cu) -endef - -define KernelPackage/rtw88-8723de - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8723DE support - DEPENDS+= +kmod-rtw88-pci +kmod-rtw88-8723d - FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723de.ko - AUTOLOAD:=$(call AutoProbe,rtw88_8723) -endef - -define KernelPackage/rtl8723-common - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8723AE/RTL8723BE common support module - DEPENDS+= +kmod-rtlwifi - FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723com/rtl8723-common.ko - HIDDEN:=1 -endef - -define KernelPackage/rtl8723be - $(call KernelPackage/mac80211/Default) - TITLE:=Realtek RTL8723AE/RTL8723BE support - DEPENDS+= +kmod-rtlwifi-btcoexist +kmod-rtlwifi-pci +kmod-rtl8723-common +rtl8723be-firmware - FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723be/rtl8723be.ko - AUTOLOAD:=$(call AutoProbe,rtl8723be) + TITLE:=Realtek RTL8821CE/RTL8822BE/RTL8822CE/RTL8723DE + DEPENDS+= @(PCI_SUPPORT) +kmod-mac80211 +@DRIVER_11AC_SUPPORT +@DRIVER_11N_SUPPORT + FILES:=\ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8821ce.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8821c.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822be.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822b.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822ce.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822c.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723de.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723d.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_core.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_pci.ko + AUTOLOAD:=$(call AutoProbe,rtw88_8821ce rtw88_8822be rtw88_8822ce rtw88_8723de) endef define KernelPackage/rtl8723bs diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index ffa01afec..a28afcb92 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -6,11 +6,24 @@ PKG_RELEASE=1 PKG_LICENSE:=GPLv2 PKG_LICENSE_FILES:= -PKG_SOURCE_VERSION:=20240714 -PKG_SOURCE_URL:=https://codeload.github.com/ptpt52/mt76/tar.gz/$(PKG_SOURCE_VERSION)? -PKG_HASH:=aa2e2c91d3f0d4b5151ac8ab3d1ea4dd2289ea825cdab80c7a9af166459be0df -PKG_SOURCE:=$(PKG_NAME)-$(PKG_SOURCE_VERSION).tar.gz -PKG_VERSION := $(PKG_SOURCE_VERSION) +PKG_SOURCE_URL:=https://github.com/openwrt/mt76 +PKG_SOURCE_PROTO:=git + +ifdef CONFIG_LINUX_5_4 +PKG_SOURCE_DATE:=2022-12-22 +PKG_SOURCE_VERSION:=5b509e80384ab019ac11aa90c81ec0dbb5b0d7f2 +PKG_MIRROR_HASH:=6fc25df4d28becd010ff4971b23731c08b53e69381a9e4c868091899712f78a9 +PATCH_DIR:=./patches-5.4 +else ifndef ($(filter on,$(CONFIG_LINUX_6_1) $(CONFIG_LINUX_6_6)),) +PKG_SOURCE_DATE:=2024-04-04 +PKG_SOURCE_VERSION:=8f301a5c5fe3d998b50666bde1d35d412833be89 +PKG_MIRROR_HASH:=49291145ccceeac2964c9a43a46bed88298e5c1da63c6f3c2c1f6b3c1902a61e +PATCH_DIR:=./patches-6.x +else +PKG_SOURCE_DATE:=2023-08-14 +PKG_SOURCE_VERSION:=b14c2351ddb8601c322576d84029e463d456caef +PKG_MIRROR_HASH:=62b5e157ad525424b6857e77ed373e8d39d03af71b057f8b309d8b293d6eac5f +endif PKG_MAINTAINER:=Felix Fietkau PKG_USE_NINJA:=0 @@ -632,11 +645,6 @@ define Package/mt76-test/install $(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/mt76-test $(1)/usr/sbin endef -define Build/InstallDev - mkdir -p $(STAGING_DIR_IMAGE) - $(CP) $(PKG_BUILD_DIR)/firmware/mt7981_eeprom_mt7976_dbdc.bin $(STAGING_DIR_IMAGE)/ -endef - $(eval $(call KernelPackage,mt76-core)) $(eval $(call KernelPackage,mt76-usb)) $(eval $(call KernelPackage,mt76x02-usb)) diff --git a/package/kernel/mt76/patches-5.4/001-allow-vht-on-2g.patch b/package/kernel/mt76/patches-5.4/001-allow-vht-on-2g.patch new file mode 100644 index 000000000..12ce67daf --- /dev/null +++ b/package/kernel/mt76/patches-5.4/001-allow-vht-on-2g.patch @@ -0,0 +1,59 @@ +From ed0b9c38becdbf9379787ca0b4db557f03a31dd7 Mon Sep 17 00:00:00 2001 +From: DENG Qingfang +Date: Mon, 23 Nov 2020 10:46:37 +0800 +Subject: [PATCH] mt76: allow VHT rate on 2.4GHz + +Allow chips that support 11ac to use 256QAM on 2.4GHz + +Signed-off-by: DENG Qingfang +--- + mac80211.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/mac80211.c b/mac80211.c +index 766681a4..06aa4228 100644 +--- a/mac80211.c ++++ b/mac80211.c +@@ -281,7 +281,7 @@ static void mt76_init_stream_cap(struct mt76_phy *phy, + void mt76_set_stream_caps(struct mt76_phy *phy, bool vht) + { + if (phy->cap.has_2ghz) +- mt76_init_stream_cap(phy, &phy->sband_2g.sband, false); ++ mt76_init_stream_cap(phy, &phy->sband_2g.sband, vht); + if (phy->cap.has_5ghz) + mt76_init_stream_cap(phy, &phy->sband_5g.sband, vht); + if (phy->cap.has_6ghz) +@@ -348,13 +348,13 @@ mt76_init_sband(struct mt76_phy *phy, struct mt76_sband *msband, + + static int + mt76_init_sband_2g(struct mt76_phy *phy, struct ieee80211_rate *rates, +- int n_rates) ++ int n_rates, bool vht) + { + phy->hw->wiphy->bands[NL80211_BAND_2GHZ] = &phy->sband_2g.sband; + + return mt76_init_sband(phy, &phy->sband_2g, mt76_channels_2ghz, + ARRAY_SIZE(mt76_channels_2ghz), rates, +- n_rates, true, false); ++ n_rates, true, vht); + } + + static int +@@ -506,7 +506,7 @@ int mt76_register_phy(struct mt76_phy *phy, bool vht, + return ret; + + if (phy->cap.has_2ghz) { +- ret = mt76_init_sband_2g(phy, rates, n_rates); ++ ret = mt76_init_sband_2g(phy, rates, n_rates, vht); + if (ret) + return ret; + } +@@ -644,7 +644,7 @@ int mt76_register_device(struct mt76_dev *dev, bool vht, + return ret; + + if (phy->cap.has_2ghz) { +- ret = mt76_init_sband_2g(phy, rates, n_rates); ++ ret = mt76_init_sband_2g(phy, rates, n_rates, vht); + if (ret) + return ret; + } diff --git a/package/kernel/mt76/patches-5.4/002-fix-build-error.patch b/package/kernel/mt76/patches-5.4/002-fix-build-error.patch new file mode 100644 index 000000000..0480a4eb3 --- /dev/null +++ b/package/kernel/mt76/patches-5.4/002-fix-build-error.patch @@ -0,0 +1,57 @@ +--- a/debugfs.c ++++ b/debugfs.c +@@ -25,6 +25,7 @@ mt76_reg_get(void *data, u64 *val) + DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mt76_reg_get, mt76_reg_set, + "0x%08llx\n"); + ++#if 0 + static int + mt76_napi_threaded_set(void *data, u64 val) + { +@@ -50,6 +51,7 @@ mt76_napi_threaded_get(void *data, u64 *val) + + DEFINE_DEBUGFS_ATTRIBUTE(fops_napi_threaded, mt76_napi_threaded_get, + mt76_napi_threaded_set, "%llu\n"); ++#endif + + int mt76_queues_read(struct seq_file *s, void *data) + { +@@ -116,8 +118,6 @@ mt76_register_debugfs_fops(struct mt76_phy *phy, + debugfs_create_bool("led_active_low", 0600, dir, &phy->leds.al); + debugfs_create_u32("regidx", 0600, dir, &dev->debugfs_reg); + debugfs_create_file_unsafe("regval", 0600, dir, dev, fops); +- debugfs_create_file_unsafe("napi_threaded", 0600, dir, dev, +- &fops_napi_threaded); + debugfs_create_blob("eeprom", 0400, dir, &dev->eeprom); + if (dev->otp.data) + debugfs_create_blob("otp", 0400, dir, &dev->otp); +--- a/mt7615/mcu.c ++++ b/mt7615/mcu.c +@@ -6,6 +6,7 @@ + */ + + #include ++#include + #include "mt7615.h" + #include "mcu.h" + #include "mac.h" +--- a/mt7915/mt7915.h ++++ b/mt7915/mt7915.h +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include "../mt76_connac.h" + #include "regs.h" + +--- a/mt76_connac_mcu.c ++++ b/mt76_connac_mcu.c +@@ -2,6 +2,7 @@ + /* Copyright (C) 2020 MediaTek Inc. */ + + #include ++#include + #include "mt76_connac2_mac.h" + #include "mt76_connac_mcu.h" + diff --git a/package/kernel/mt76/patches-5.4/100-api_update.patch b/package/kernel/mt76/patches-5.4/100-api_update.patch new file mode 100644 index 000000000..3a76f1175 --- /dev/null +++ b/package/kernel/mt76/patches-5.4/100-api_update.patch @@ -0,0 +1,11 @@ +--- a/tx.c ++++ b/tx.c +@@ -330,7 +330,7 @@ mt76_tx(struct mt76_phy *phy, struct iee + if ((dev->drv->drv_flags & MT_DRV_HW_MGMT_TXQ) && + !(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && + !ieee80211_is_data(hdr->frame_control) && +- !ieee80211_is_bufferable_mmpdu(hdr->frame_control)) { ++ !ieee80211_is_bufferable_mmpdu(skb)) { + qid = MT_TXQ_PSD; + } + diff --git a/package/kernel/mt76/patches-5.4/110-wifi-mt76-ignore-key-disable-commands.patch b/package/kernel/mt76/patches-5.4/110-wifi-mt76-ignore-key-disable-commands.patch new file mode 100644 index 000000000..3c132420e --- /dev/null +++ b/package/kernel/mt76/patches-5.4/110-wifi-mt76-ignore-key-disable-commands.patch @@ -0,0 +1,301 @@ +From: Felix Fietkau +Date: Wed, 22 Mar 2023 10:17:49 +0100 +Subject: [PATCH] wifi: mt76: ignore key disable commands + +This helps avoid cleartext leakage of already queued or powersave buffered +packets, when a reassoc triggers the key deletion. + +Cc: stable@vger.kernel.org +Signed-off-by: Felix Fietkau +--- + +--- a/mt7603/main.c ++++ b/mt7603/main.c +@@ -512,15 +512,15 @@ mt7603_set_key(struct ieee80211_hw *hw, + !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) + return -EOPNOTSUPP; + +- if (cmd == SET_KEY) { +- key->hw_key_idx = wcid->idx; +- wcid->hw_key_idx = idx; +- } else { ++ if (cmd != SET_KEY) { + if (idx == wcid->hw_key_idx) + wcid->hw_key_idx = -1; + +- key = NULL; ++ return 0; + } ++ ++ key->hw_key_idx = wcid->idx; ++ wcid->hw_key_idx = idx; + mt76_wcid_key_setup(&dev->mt76, wcid, key); + + return mt7603_wtbl_set_key(dev, wcid->idx, key); +--- a/mt7615/mac.c ++++ b/mt7615/mac.c +@@ -1193,8 +1193,7 @@ EXPORT_SYMBOL_GPL(mt7615_mac_enable_rtsc + static int + mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, + struct ieee80211_key_conf *key, +- enum mt76_cipher_type cipher, u16 cipher_mask, +- enum set_key_cmd cmd) ++ enum mt76_cipher_type cipher, u16 cipher_mask) + { + u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; + u8 data[32] = {}; +@@ -1203,27 +1202,18 @@ mt7615_mac_wtbl_update_key(struct mt7615 + return -EINVAL; + + mt76_rr_copy(dev, addr, data, sizeof(data)); +- if (cmd == SET_KEY) { +- if (cipher == MT_CIPHER_TKIP) { +- /* Rx/Tx MIC keys are swapped */ +- memcpy(data, key->key, 16); +- memcpy(data + 16, key->key + 24, 8); +- memcpy(data + 24, key->key + 16, 8); +- } else { +- if (cipher_mask == BIT(cipher)) +- memcpy(data, key->key, key->keylen); +- else if (cipher != MT_CIPHER_BIP_CMAC_128) +- memcpy(data, key->key, 16); +- if (cipher == MT_CIPHER_BIP_CMAC_128) +- memcpy(data + 16, key->key, 16); +- } ++ if (cipher == MT_CIPHER_TKIP) { ++ /* Rx/Tx MIC keys are swapped */ ++ memcpy(data, key->key, 16); ++ memcpy(data + 16, key->key + 24, 8); ++ memcpy(data + 24, key->key + 16, 8); + } else { ++ if (cipher_mask == BIT(cipher)) ++ memcpy(data, key->key, key->keylen); ++ else if (cipher != MT_CIPHER_BIP_CMAC_128) ++ memcpy(data, key->key, 16); + if (cipher == MT_CIPHER_BIP_CMAC_128) +- memset(data + 16, 0, 16); +- else if (cipher_mask) +- memset(data, 0, 16); +- if (!cipher_mask) +- memset(data, 0, sizeof(data)); ++ memcpy(data + 16, key->key, 16); + } + + mt76_wr_copy(dev, addr, data, sizeof(data)); +@@ -1234,7 +1224,7 @@ mt7615_mac_wtbl_update_key(struct mt7615 + static int + mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, + enum mt76_cipher_type cipher, u16 cipher_mask, +- int keyidx, enum set_key_cmd cmd) ++ int keyidx) + { + u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; + +@@ -1253,9 +1243,7 @@ mt7615_mac_wtbl_update_pk(struct mt7615_ + else + w0 &= ~MT_WTBL_W0_RX_IK_VALID; + +- if (cmd == SET_KEY && +- (cipher != MT_CIPHER_BIP_CMAC_128 || +- cipher_mask == BIT(cipher))) { ++ if (cipher != MT_CIPHER_BIP_CMAC_128 || cipher_mask == BIT(cipher)) { + w0 &= ~MT_WTBL_W0_KEY_IDX; + w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); + } +@@ -1272,19 +1260,10 @@ mt7615_mac_wtbl_update_pk(struct mt7615_ + + static void + mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, +- enum mt76_cipher_type cipher, u16 cipher_mask, +- enum set_key_cmd cmd) ++ enum mt76_cipher_type cipher, u16 cipher_mask) + { + u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); + +- if (!cipher_mask) { +- mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE); +- return; +- } +- +- if (cmd != SET_KEY) +- return; +- + if (cipher == MT_CIPHER_BIP_CMAC_128 && + cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) + return; +@@ -1295,8 +1274,7 @@ mt7615_mac_wtbl_update_cipher(struct mt7 + + int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, + struct mt76_wcid *wcid, +- struct ieee80211_key_conf *key, +- enum set_key_cmd cmd) ++ struct ieee80211_key_conf *key) + { + enum mt76_cipher_type cipher; + u16 cipher_mask = wcid->cipher; +@@ -1306,19 +1284,14 @@ int __mt7615_mac_wtbl_set_key(struct mt7 + if (cipher == MT_CIPHER_NONE) + return -EOPNOTSUPP; + +- if (cmd == SET_KEY) +- cipher_mask |= BIT(cipher); +- else +- cipher_mask &= ~BIT(cipher); +- +- mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd); +- err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask, +- cmd); ++ cipher_mask |= BIT(cipher); ++ mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask); ++ err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask); + if (err < 0) + return err; + + err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, +- key->keyidx, cmd); ++ key->keyidx); + if (err < 0) + return err; + +@@ -1329,13 +1302,12 @@ int __mt7615_mac_wtbl_set_key(struct mt7 + + int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, + struct mt76_wcid *wcid, +- struct ieee80211_key_conf *key, +- enum set_key_cmd cmd) ++ struct ieee80211_key_conf *key) + { + int err; + + spin_lock_bh(&dev->mt76.lock); +- err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); ++ err = __mt7615_mac_wtbl_set_key(dev, wcid, key); + spin_unlock_bh(&dev->mt76.lock); + + return err; +--- a/mt7615/main.c ++++ b/mt7615/main.c +@@ -391,18 +391,17 @@ static int mt7615_set_key(struct ieee802 + + if (cmd == SET_KEY) + *wcid_keyidx = idx; +- else if (idx == *wcid_keyidx) +- *wcid_keyidx = -1; +- else ++ else { ++ if (idx == *wcid_keyidx) ++ *wcid_keyidx = -1; + goto out; ++ } + +- mt76_wcid_key_setup(&dev->mt76, wcid, +- cmd == SET_KEY ? key : NULL); +- ++ mt76_wcid_key_setup(&dev->mt76, wcid, key); + if (mt76_is_mmio(&dev->mt76)) +- err = mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); ++ err = mt7615_mac_wtbl_set_key(dev, wcid, key); + else +- err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); ++ err = __mt7615_mac_wtbl_set_key(dev, wcid, key); + + out: + mt7615_mutex_release(dev); +--- a/mt7615/mt7615.h ++++ b/mt7615/mt7615.h +@@ -491,11 +491,9 @@ int mt7615_mac_write_txwi(struct mt7615_ + void mt7615_mac_set_timing(struct mt7615_phy *phy); + int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, + struct mt76_wcid *wcid, +- struct ieee80211_key_conf *key, +- enum set_key_cmd cmd); ++ struct ieee80211_key_conf *key); + int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, +- struct ieee80211_key_conf *key, +- enum set_key_cmd cmd); ++ struct ieee80211_key_conf *key); + void mt7615_mac_reset_work(struct work_struct *work); + u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid); + +--- a/mt76x02_util.c ++++ b/mt76x02_util.c +@@ -454,20 +454,20 @@ int mt76x02_set_key(struct ieee80211_hw + msta = sta ? (struct mt76x02_sta *)sta->drv_priv : NULL; + wcid = msta ? &msta->wcid : &mvif->group_wcid; + +- if (cmd == SET_KEY) { +- key->hw_key_idx = wcid->idx; +- wcid->hw_key_idx = idx; +- if (key->flags & IEEE80211_KEY_FLAG_RX_MGMT) { +- key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; +- wcid->sw_iv = true; +- } +- } else { ++ if (cmd != SET_KEY) { + if (idx == wcid->hw_key_idx) { + wcid->hw_key_idx = -1; + wcid->sw_iv = false; + } + +- key = NULL; ++ return 0; ++ } ++ ++ key->hw_key_idx = wcid->idx; ++ wcid->hw_key_idx = idx; ++ if (key->flags & IEEE80211_KEY_FLAG_RX_MGMT) { ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ wcid->sw_iv = true; + } + mt76_wcid_key_setup(&dev->mt76, wcid, key); + +--- a/mt7915/main.c ++++ b/mt7915/main.c +@@ -399,16 +399,15 @@ static int mt7915_set_key(struct ieee802 + mt7915_mcu_add_bss_info(phy, vif, true); + } + +- if (cmd == SET_KEY) ++ if (cmd == SET_KEY) { + *wcid_keyidx = idx; +- else if (idx == *wcid_keyidx) +- *wcid_keyidx = -1; +- else ++ } else { ++ if (idx == *wcid_keyidx) ++ *wcid_keyidx = -1; + goto out; ++ } + +- mt76_wcid_key_setup(&dev->mt76, wcid, +- cmd == SET_KEY ? key : NULL); +- ++ mt76_wcid_key_setup(&dev->mt76, wcid, key); + err = mt76_connac_mcu_add_key(&dev->mt76, vif, &msta->bip, + key, MCU_EXT_CMD(STA_REC_UPDATE), + &msta->wcid, cmd); +--- a/mt7921/main.c ++++ b/mt7921/main.c +@@ -569,16 +569,15 @@ static int mt7921_set_key(struct ieee802 + + mt7921_mutex_acquire(dev); + +- if (cmd == SET_KEY) ++ if (cmd == SET_KEY) { + *wcid_keyidx = idx; +- else if (idx == *wcid_keyidx) +- *wcid_keyidx = -1; +- else ++ } else { ++ if (idx == *wcid_keyidx) ++ *wcid_keyidx = -1; + goto out; ++ } + +- mt76_wcid_key_setup(&dev->mt76, wcid, +- cmd == SET_KEY ? key : NULL); +- ++ mt76_wcid_key_setup(&dev->mt76, wcid, key); + err = mt76_connac_mcu_add_key(&dev->mt76, vif, &msta->bip, + key, MCU_UNI_CMD(STA_REC_UPDATE), + &msta->wcid, cmd); diff --git a/package/kernel/mt76/patches-6.x/001-allow-vht-on-2g.patch b/package/kernel/mt76/patches-6.x/001-allow-vht-on-2g.patch new file mode 100644 index 000000000..aaa8dd5fa --- /dev/null +++ b/package/kernel/mt76/patches-6.x/001-allow-vht-on-2g.patch @@ -0,0 +1,59 @@ +From ed0b9c38becdbf9379787ca0b4db557f03a31dd7 Mon Sep 17 00:00:00 2001 +From: DENG Qingfang +Date: Mon, 23 Nov 2020 10:46:37 +0800 +Subject: [PATCH] mt76: allow VHT rate on 2.4GHz + +Allow chips that support 11ac to use 256QAM on 2.4GHz + +Signed-off-by: DENG Qingfang +--- + mac80211.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/mac80211.c b/mac80211.c +index 766681a4..06aa4228 100644 +--- a/mac80211.c ++++ b/mac80211.c +@@ -282,7 +282,7 @@ static void mt76_init_stream_cap(struct mt76_phy *phy, + void mt76_set_stream_caps(struct mt76_phy *phy, bool vht) + { + if (phy->cap.has_2ghz) +- mt76_init_stream_cap(phy, &phy->sband_2g.sband, false); ++ mt76_init_stream_cap(phy, &phy->sband_2g.sband, vht); + if (phy->cap.has_5ghz) + mt76_init_stream_cap(phy, &phy->sband_5g.sband, vht); + if (phy->cap.has_6ghz) +@@ -349,13 +349,13 @@ mt76_init_sband(struct mt76_phy *phy, struct mt76_sband *msband, + + static int + mt76_init_sband_2g(struct mt76_phy *phy, struct ieee80211_rate *rates, +- int n_rates) ++ int n_rates, bool vht) + { + phy->hw->wiphy->bands[NL80211_BAND_2GHZ] = &phy->sband_2g.sband; + + return mt76_init_sband(phy, &phy->sband_2g, mt76_channels_2ghz, + ARRAY_SIZE(mt76_channels_2ghz), rates, +- n_rates, true, false); ++ n_rates, true, vht); + } + + static int +@@ -508,7 +508,7 @@ int mt76_register_phy(struct mt76_phy *phy, bool vht, + return ret; + + if (phy->cap.has_2ghz) { +- ret = mt76_init_sband_2g(phy, rates, n_rates); ++ ret = mt76_init_sband_2g(phy, rates, n_rates, vht); + if (ret) + return ret; + } +@@ -691,7 +691,7 @@ int mt76_register_device(struct mt76_dev *dev, bool vht, + return ret; + + if (phy->cap.has_2ghz) { +- ret = mt76_init_sband_2g(phy, rates, n_rates); ++ ret = mt76_init_sband_2g(phy, rates, n_rates, vht); + if (ret) + return ret; + } diff --git a/package/kernel/mt76/patches-6.x/002-wifi-mt76-mt7915-fix-oops.patch b/package/kernel/mt76/patches-6.x/002-wifi-mt76-mt7915-fix-oops.patch new file mode 100644 index 000000000..d472dac92 --- /dev/null +++ b/package/kernel/mt76/patches-6.x/002-wifi-mt76-mt7915-fix-oops.patch @@ -0,0 +1,100 @@ +From 3b47d9df427c4833605a172f2a8f0e0012b04c80 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= +Date: Sat, 13 Jul 2024 15:00:10 +0200 +Subject: [PATCH] wifi: mt76: mt7915: fix oops on non-dbdc mt7986 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mt7915_band_config() sets band_idx = 1 on the main phy for mt7986 +with MT7975_ONE_ADIE or MT7976_ONE_ADIE. + +Commit 0335c034e726 ("wifi: mt76: fix race condition related to +checking tx queue fill status") introduced a dereference of the +phys array indirectly indexed by band_idx via wcid->phy_idx in +mt76_wcid_cleanup(). This caused the following Oops on affected +mt7986 devices: + + Unable to handle kernel read from unreadable memory at virtual address 0000000000000024 + Mem abort info: + ESR = 0x0000000096000005 + EC = 0x25: DABT (current EL), IL = 32 bits + SET = 0, FnV = 0 + EA = 0, S1PTW = 0 + FSC = 0x05: level 1 translation fault + Data abort info: + ISV = 0, ISS = 0x00000005 + CM = 0, WnR = 0 + user pgtable: 4k pages, 39-bit VAs, pgdp=0000000042545000 + [0000000000000024] pgd=0000000000000000, p4d=0000000000000000, pud=0000000000000000 + Internal error: Oops: 0000000096000005 [#1] SMP + Modules linked in: ... mt7915e mt76_connac_lib mt76 mac80211 cfg80211 ... + CPU: 2 PID: 1631 Comm: hostapd Not tainted 5.15.150 #0 + Hardware name: ZyXEL EX5700 (Telenor) (DT) + pstate: 80400005 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) + pc : mt76_wcid_cleanup+0x84/0x22c [mt76] + lr : mt76_wcid_cleanup+0x64/0x22c [mt76] + sp : ffffffc00a803700 + x29: ffffffc00a803700 x28: ffffff80008f7300 x27: ffffff80003f3c00 + x26: ffffff80000a7880 x25: ffffffc008c26e00 x24: 0000000000000001 + x23: ffffffc000a68114 x22: 0000000000000000 x21: ffffff8004172cc8 + x20: ffffffc00a803748 x19: ffffff8004152020 x18: 0000000000000000 + x17: 00000000000017c0 x16: ffffffc008ef5000 x15: 0000000000000be0 + x14: ffffff8004172e28 x13: ffffff8004172e28 x12: 0000000000000000 + x11: 0000000000000000 x10: ffffff8004172e30 x9 : ffffff8004172e28 + x8 : 0000000000000000 x7 : ffffff8004156020 x6 : 0000000000000000 + x5 : 0000000000000031 x4 : 0000000000000000 x3 : 0000000000000001 + x2 : 0000000000000000 x1 : ffffff80008f7300 x0 : 0000000000000024 + Call trace: + mt76_wcid_cleanup+0x84/0x22c [mt76] + __mt76_sta_remove+0x70/0xbc [mt76] + mt76_sta_state+0x8c/0x1a4 [mt76] + mt7915_eeprom_get_power_delta+0x11e4/0x23a0 [mt7915e] + drv_sta_state+0x144/0x274 [mac80211] + sta_info_move_state+0x1cc/0x2a4 [mac80211] + sta_set_sinfo+0xaf8/0xc24 [mac80211] + sta_info_destroy_addr_bss+0x4c/0x6c [mac80211] + + ieee80211_color_change_finish+0x1c08/0x1e70 [mac80211] + cfg80211_check_station_change+0x1360/0x4710 [cfg80211] + genl_family_rcv_msg_doit+0xb4/0x110 + genl_rcv_msg+0xd0/0x1bc + netlink_rcv_skb+0x58/0x120 + genl_rcv+0x34/0x50 + netlink_unicast+0x1f0/0x2ec + netlink_sendmsg+0x198/0x3d0 + ____sys_sendmsg+0x1b0/0x210 + ___sys_sendmsg+0x80/0xf0 + __sys_sendmsg+0x44/0xa0 + __arm64_sys_sendmsg+0x20/0x30 + invoke_syscall.constprop.0+0x4c/0xe0 + do_el0_svc+0x40/0xd0 + el0_svc+0x14/0x4c + el0t_64_sync_handler+0x100/0x110 + el0t_64_sync+0x15c/0x160 + Code: d2800002 910092c0 52800023 f9800011 (885f7c01) + ---[ end trace 7e42dd9a39ed2281 ]--- + +Fix by using mt76_dev_phy() which will map band_idx to the correct phy +for all hardware combinations. + +Fixes: 0335c034e726 ("wifi: mt76: fix race condition related to checking tx queue fill status") +Link: https://github.com/openwrt/openwrt/issues/14548 +Signed-off-by: Bjørn Mork +Link: https://patch.msgid.link/20240713130010.516037-1-bjorn@mork.no +Signed-off-by: Felix Fietkau +--- + mac80211.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/mac80211.c ++++ b/mac80211.c +@@ -1515,7 +1515,7 @@ EXPORT_SYMBOL_GPL(mt76_wcid_init); + + void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid) + { +- struct mt76_phy *phy = dev->phys[wcid->phy_idx]; ++ struct mt76_phy *phy = mt76_dev_phy(dev, wcid->phy_idx); + struct ieee80211_hw *hw; + struct sk_buff_head list; + struct sk_buff *skb; diff --git a/package/kernel/mt76/patches-6.x/101-fixes-mt7925-build-error.patch b/package/kernel/mt76/patches-6.x/101-fixes-mt7925-build-error.patch new file mode 100644 index 000000000..915f1c495 --- /dev/null +++ b/package/kernel/mt76/patches-6.x/101-fixes-mt7925-build-error.patch @@ -0,0 +1,23 @@ +--- a/mt7925/main.c ++++ b/mt7925/main.c +@@ -260,7 +260,8 @@ __mt7925_set_stream_he_eht_caps(struct m + n++; + } + +- _ieee80211_set_sband_iftype_data(sband, data, n); ++ sband->iftype_data = data; ++ sband->n_iftype_data = n; + } + + void mt7925_set_stream_he_eht_caps(struct mt792x_phy *phy) +--- a/mt7925/mcu.c ++++ b/mt7925/mcu.c +@@ -2209,7 +2209,7 @@ mt7925_mcu_bss_mld_tlv(struct sk_buff *s + struct ieee80211_sta *sta) + { + struct mt792x_vif *mvif = (struct mt792x_vif *)vif->drv_priv; +- bool is_mld = ieee80211_vif_is_mld(vif); ++ bool is_mld = (vif->valid_links != 0); + struct bss_mld_tlv *mld; + struct tlv *tlv; + diff --git a/package/kernel/mt76/patches/001-allow-vht-on-2g.patch b/package/kernel/mt76/patches/001-allow-vht-on-2g.patch new file mode 100644 index 000000000..aaa8dd5fa --- /dev/null +++ b/package/kernel/mt76/patches/001-allow-vht-on-2g.patch @@ -0,0 +1,59 @@ +From ed0b9c38becdbf9379787ca0b4db557f03a31dd7 Mon Sep 17 00:00:00 2001 +From: DENG Qingfang +Date: Mon, 23 Nov 2020 10:46:37 +0800 +Subject: [PATCH] mt76: allow VHT rate on 2.4GHz + +Allow chips that support 11ac to use 256QAM on 2.4GHz + +Signed-off-by: DENG Qingfang +--- + mac80211.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/mac80211.c b/mac80211.c +index 766681a4..06aa4228 100644 +--- a/mac80211.c ++++ b/mac80211.c +@@ -282,7 +282,7 @@ static void mt76_init_stream_cap(struct mt76_phy *phy, + void mt76_set_stream_caps(struct mt76_phy *phy, bool vht) + { + if (phy->cap.has_2ghz) +- mt76_init_stream_cap(phy, &phy->sband_2g.sband, false); ++ mt76_init_stream_cap(phy, &phy->sband_2g.sband, vht); + if (phy->cap.has_5ghz) + mt76_init_stream_cap(phy, &phy->sband_5g.sband, vht); + if (phy->cap.has_6ghz) +@@ -349,13 +349,13 @@ mt76_init_sband(struct mt76_phy *phy, struct mt76_sband *msband, + + static int + mt76_init_sband_2g(struct mt76_phy *phy, struct ieee80211_rate *rates, +- int n_rates) ++ int n_rates, bool vht) + { + phy->hw->wiphy->bands[NL80211_BAND_2GHZ] = &phy->sband_2g.sband; + + return mt76_init_sband(phy, &phy->sband_2g, mt76_channels_2ghz, + ARRAY_SIZE(mt76_channels_2ghz), rates, +- n_rates, true, false); ++ n_rates, true, vht); + } + + static int +@@ -508,7 +508,7 @@ int mt76_register_phy(struct mt76_phy *phy, bool vht, + return ret; + + if (phy->cap.has_2ghz) { +- ret = mt76_init_sband_2g(phy, rates, n_rates); ++ ret = mt76_init_sband_2g(phy, rates, n_rates, vht); + if (ret) + return ret; + } +@@ -691,7 +691,7 @@ int mt76_register_device(struct mt76_dev *dev, bool vht, + return ret; + + if (phy->cap.has_2ghz) { +- ret = mt76_init_sband_2g(phy, rates, n_rates); ++ ret = mt76_init_sband_2g(phy, rates, n_rates, vht); + if (ret) + return ret; + } diff --git a/package/kernel/mt76/patches/002-fix-page-pool.patch b/package/kernel/mt76/patches/002-fix-page-pool.patch new file mode 100644 index 000000000..b8d552ffd --- /dev/null +++ b/package/kernel/mt76/patches/002-fix-page-pool.patch @@ -0,0 +1,24 @@ +--- a/mac80211.c ++++ b/mac80211.c +@@ -4,7 +4,9 @@ + */ + #include + #include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0) + #include ++#endif + #include "mt76.h" + + #define CHAN2G(_idx, _freq) { \ +--- a/mt76.h ++++ b/mt76.h +@@ -15,6 +15,9 @@ + #include + #include + #include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,0) ++#include ++#endif + #include "util.h" + #include "testmode.h" + diff --git a/package/kernel/rtw88-usb/Makefile b/package/kernel/rtw88-usb/Makefile new file mode 100644 index 000000000..7afa41c7f --- /dev/null +++ b/package/kernel/rtw88-usb/Makefile @@ -0,0 +1,105 @@ +# +# Copyright (C) 2017 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=rtw88-usb +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-04-10 +PKG_SOURCE_URL:=https://github.com/lwfinger/rtw88.git +PKG_SOURCE_VERSION:=2e9f468009df592a51990d024928034e0af1c2b4 +PKG_MIRROR_HASH:=684b30e58d8b990bbe141baae00c48439f45c9f39faa6f552ffb18afb6594c74 + +PKG_BUILD_PARALLEL:=1 + +STAMP_CONFIGURED_DEPENDS := $(STAGING_DIR)/usr/include/mac80211-backport/backport/autoconf.h + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/rtw88-default + SUBMENU:=Wireless Drivers + TITLE:=Realtek rtw88 family usb driver + DEPENDS:=+kmod-mac80211 +kmod-usb-core \ + +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT +endef + +define KernelPackage/rtw88-usb + $(KernelPackage/rtw88-default) + HIDDEN:=1 + FILES:= \ + $(PKG_BUILD_DIR)/rtw_core.ko \ + $(PKG_BUILD_DIR)/rtw_usb.ko +endef + +define KernelPackage/rtl8723du + $(KernelPackage/rtw88-default) + TITLE:=Realtek RTL8723DU support + DEPENDS+=+kmod-rtw88-usb +rtl8723du-firmware + FILES:= \ + $(PKG_BUILD_DIR)/rtw_8723d.ko \ + $(PKG_BUILD_DIR)/rtw_8723du.ko + AUTOLOAD:=$(call AutoProbe,rtw_8723du) +endef + +define KernelPackage/rtl8821cu + $(KernelPackage/rtw88-default) + TITLE:=Realtek RTL8821CU support + DEPENDS+=+kmod-rtw88-usb +rtl8821ce-firmware + FILES:= \ + $(PKG_BUILD_DIR)/rtw_8821c.ko \ + $(PKG_BUILD_DIR)/rtw_8821cu.ko + AUTOLOAD:=$(call AutoProbe,rtw_8821cu) +endef + +define KernelPackage/rtl8822bu + $(KernelPackage/rtw88-default) + TITLE:=Realtek RTL8822BU support + DEPENDS+=+kmod-rtw88-usb +rtl8822be-firmware + FILES:= \ + $(PKG_BUILD_DIR)/rtw_8822b.ko \ + $(PKG_BUILD_DIR)/rtw_8822bu.ko + AUTOLOAD:=$(call AutoProbe,rtw_8822bu) +endef + +define KernelPackage/rtl8822cu + $(KernelPackage/rtw88-default) + TITLE:=Realtek RTL8822CU support + DEPENDS+=+kmod-rtw88-usb +rtl8822ce-firmware + FILES:= \ + $(PKG_BUILD_DIR)/rtw_8822c.ko \ + $(PKG_BUILD_DIR)/rtw_8822cu.ko + AUTOLOAD:=$(call AutoProbe,rtw_8822cu) +endef + +NOSTDINC_FLAGS := \ + $(KERNEL_NOSTDINC_FLAGS) \ + -I$(PKG_BUILD_DIR) \ + -I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \ + -I$(STAGING_DIR)/usr/include/mac80211-backport \ + -I$(STAGING_DIR)/usr/include/mac80211/uapi \ + -I$(STAGING_DIR)/usr/include/mac80211 \ + -include backport/autoconf.h \ + -include backport/backport.h + +NOSTDINC_FLAGS+=-DBUILD_OPENWRT + +define Build/Compile + +$(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + NOSTDINC_FLAGS="$(NOSTDINC_FLAGS)" \ + modules +endef + +$(eval $(call KernelPackage,rtw88-usb)) +$(eval $(call KernelPackage,rtl8723du)) +$(eval $(call KernelPackage,rtl8821cu)) +$(eval $(call KernelPackage,rtl8822bu)) +$(eval $(call KernelPackage,rtl8822cu)) diff --git a/package/kernel/rtw88-usb/patches/001-fix-merge-error.patch b/package/kernel/rtw88-usb/patches/001-fix-merge-error.patch new file mode 100644 index 000000000..4439c4f18 --- /dev/null +++ b/package/kernel/rtw88-usb/patches/001-fix-merge-error.patch @@ -0,0 +1,96 @@ +--- a/fw.c ++++ b/fw.c +@@ -1009,7 +1009,7 @@ static u8 rtw_get_rsvd_page_probe_req_location(struct rtw_dev *rtwdev, + if (rsvd_pkt->type != RSVD_PROBE_REQ) + continue; + if ((!ssid && !rsvd_pkt->ssid) || +- cfg80211_ssid_eq(rsvd_pkt->ssid, ssid)) ++ cfg80211_ssid_eq(rsvd_pkt->ssid, ssid)) + location = rsvd_pkt->page; + } + +--- a/mac.c ++++ b/mac.c +@@ -316,13 +316,6 @@ static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) + rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0)); + } + +- if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { +- if (chip->id == RTW_CHIP_TYPE_8822C || +- chip->id == RTW_CHIP_TYPE_8822B || +- chip->id == RTW_CHIP_TYPE_8821C) +- rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0)); +- } +- + if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) + rtw_write32(rtwdev, REG_SDIO_HIMR, imr); + +@@ -956,18 +949,6 @@ static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, + rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00); + } + +- /* reset firmware if still present */ +- if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B && +- rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) { +- rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00); +- } +- +- /* reset firmware if still present */ +- if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B && +- rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) { +- rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00); +- } +- + en_download_firmware_legacy(rtwdev, true); + ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); + en_download_firmware_legacy(rtwdev, false); +--- a/main.c ++++ b/main.c +@@ -110,9 +110,7 @@ static const struct ieee80211_iface_limit rtw_iface_limits[] = { + }, + { + .max = 1, +- .types = BIT(NL80211_IFTYPE_AP) | +- BIT(NL80211_IFTYPE_P2P_CLIENT) | +- BIT(NL80211_IFTYPE_P2P_GO) ++ .types = BIT(NL80211_IFTYPE_AP), + } + }; + +@@ -2124,11 +2122,6 @@ static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) + dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n"); + } + +- if (!is_valid_ether_addr(efuse->addr)) { +- eth_random_addr(efuse->addr); +- dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n"); +- } +- + out_disable: + rtw_chip_efuse_disable(rtwdev); + +@@ -2361,9 +2354,7 @@ int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) + hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_ADHOC) | +- BIT(NL80211_IFTYPE_MESH_POINT) | +- BIT(NL80211_IFTYPE_P2P_CLIENT) | +- BIT(NL80211_IFTYPE_P2P_GO); ++ BIT(NL80211_IFTYPE_MESH_POINT); + hw->wiphy->available_antennas_tx = hal->antenna_tx; + hw->wiphy->available_antennas_rx = hal->antenna_rx; + +--- a/usb.c ++++ b/usb.c +@@ -93,11 +93,6 @@ static u32 rtw_usb_read(struct rtw_dev *rtwdev, u32 addr, u16 len) + rtwdev->chip->id == RTW_CHIP_TYPE_8821C) + rtw_usb_reg_sec(rtwdev, addr, data); + +- if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C || +- rtwdev->chip->id == RTW_CHIP_TYPE_8822B || +- rtwdev->chip->id == RTW_CHIP_TYPE_8821C) +- rtw_usb_reg_sec(rtwdev, addr, data); +- + return le32_to_cpu(*data); + } + diff --git a/package/kernel/rtw88-usb/patches/101-wireless-6.1.patch b/package/kernel/rtw88-usb/patches/101-wireless-6.1.patch new file mode 100644 index 000000000..37a9bca9f --- /dev/null +++ b/package/kernel/rtw88-usb/patches/101-wireless-6.1.patch @@ -0,0 +1,432 @@ +--- a/bf.c ++++ b/bf.c +@@ -57,7 +57,7 @@ void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, + } + + ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap; +-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 19, 0) && !defined(BUILD_OPENWRT) + vht_cap = &sta->vht_cap; + #else + vht_cap = &sta->deflink.vht_cap; +@@ -75,7 +75,7 @@ void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, + ether_addr_copy(bfee->mac_addr, bssid); + bfee->role = RTW_BFEE_MU; + bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + bfee->aid = vif->cfg.aid; + #else + bfee->aid = bss_conf->aid; +--- a/fw.c ++++ b/fw.c +@@ -191,7 +191,7 @@ legacy: + si->ra_report.desc_rate = rate; + si->ra_report.bit_rate = bit_rate; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) || defined(BUILD_OPENWRT) + sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(bit_rate); + #else + sta->max_rc_amsdu_len = get_max_amsdu_len(bit_rate); +@@ -726,7 +726,7 @@ void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) + rtw_fw_send_h2c_command(rtwdev, h2c_pkt); + } + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) || defined(BUILD_OPENWRT) + void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + bool reset_ra_mask) + #else +@@ -735,7 +735,7 @@ void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) + { + u8 h2c_pkt[H2C_PKT_SIZE] = {0}; + bool disable_pt = true; +-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) && !defined(BUILD_OPENWRT) + bool reset_ra_mask = true; + #endif + +@@ -1228,7 +1228,7 @@ static struct sk_buff *rtw_get_rsvd_page_skb(struct ieee80211_hw *hw, + + switch (rsvd_pkt->type) { + case RSVD_BEACON: +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + skb_new = ieee80211_beacon_get_tim(hw, vif, &tim_offset, NULL, 0); + #else + skb_new = ieee80211_beacon_get_tim(hw, vif, &tim_offset, NULL); +@@ -1243,7 +1243,7 @@ static struct sk_buff *rtw_get_rsvd_page_skb(struct ieee80211_hw *hw, + break; + case RSVD_NULL: + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 17) +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) || defined(BUILD_OPENWRT) + skb_new = ieee80211_nullfunc_get(hw, vif, -1, false); + #else + skb_new = ieee80211_nullfunc_get(hw, vif, false); +@@ -1254,7 +1254,7 @@ static struct sk_buff *rtw_get_rsvd_page_skb(struct ieee80211_hw *hw, + break; + case RSVD_QOS_NULL: + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 17) +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) || defined(BUILD_OPENWRT) + skb_new = ieee80211_nullfunc_get(hw, vif, -1, true); + #else + skb_new = ieee80211_nullfunc_get(hw, vif, true); +--- a/fw.h ++++ b/fw.h +@@ -834,7 +834,7 @@ void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data); + + void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); + void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) || defined(BUILD_OPENWRT) + void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + bool reset_ra_mask); + #else +--- a/mac80211.c ++++ b/mac80211.c +@@ -365,7 +365,7 @@ static void rtw_conf_tx(struct rtw_dev *rtwdev, + static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *conf, +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + u64 changed) + #else + u32 changed) +@@ -383,7 +383,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw, + + if (changed & BSS_CHANGED_ASSOC) { + rtw_vif_assoc_changed(rtwvif, conf); +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + if (vif->cfg.assoc) { + #else + if (conf->assoc) { +@@ -393,7 +393,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw, + rtw_fw_download_rsvd_page(rtwdev); + rtw_send_rsvd_page_h2c(rtwdev); + rtw_fw_default_port(rtwdev, rtwvif); +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + rtw_coex_media_status_notify(rtwdev, vif->cfg.assoc); + #else + rtw_coex_media_status_notify(rtwdev, conf->assoc); +@@ -460,7 +460,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw, + mutex_unlock(&rtwdev->mutex); + } + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + static int rtw_ops_start_ap(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *link_conf) +@@ -481,7 +481,7 @@ static int rtw_ops_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif) + return 0; + } + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + static void rtw_ops_stop_ap(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *link_conf) +@@ -502,7 +502,7 @@ static void rtw_ops_stop_ap(struct ieee80211_hw *hw, + + static int rtw_ops_conf_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + unsigned int link_id, u16 ac, + #else + u16 ac, +@@ -731,7 +731,7 @@ static void rtw_ops_sw_scan_complete(struct ieee80211_hw *hw, + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0) + static void rtw_ops_mgd_prepare_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,14,0)) ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,14,0)) || defined(BUILD_OPENWRT) + struct ieee80211_prep_tx_info *info) + #else + u16 duration) +--- a/main.c ++++ b/main.c +@@ -191,7 +191,7 @@ static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif) + struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; + + if (vif->type == NL80211_IFTYPE_STATION) +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + if (vif->cfg.assoc) + #else + if (vif->bss_conf.assoc) +@@ -343,7 +343,7 @@ int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, + if (si->mac_id >= RTW_MAX_MAC_ID_NUM) + return -ENOSPC; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + if (vif->type == NL80211_IFTYPE_STATION && vif->cfg.assoc == 0) + #else + if (vif->type == NL80211_IFTYPE_STATION && vif->bss_conf.assoc == 0) +@@ -572,7 +572,7 @@ EXPORT_SYMBOL(rtw_dump_reg); + void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, + struct ieee80211_bss_conf *conf) + { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + struct ieee80211_vif *vif = NULL; + + if (conf) +@@ -1000,7 +1000,7 @@ static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) + static u64 get_vht_ra_mask(struct ieee80211_sta *sta) + { + u64 ra_mask = 0; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); + #else + u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); +@@ -1224,26 +1224,26 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + bool is_vht_enable = false; + bool is_support_sgi = false; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.vht_supported) { + #else + if (sta->vht_cap.vht_supported) { + #endif + is_vht_enable = true; + ra_mask |= get_vht_ra_mask(sta); +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) + #else + if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) + #endif + stbc_en = VHT_STBC_EN; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) + #else + if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) + #endif + ldpc_en = VHT_LDPC_EN; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + } else if (sta->deflink.ht_cap.ht_supported) { + ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | + (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); +@@ -1266,20 +1266,20 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; + + if (hal->current_band_type == RTW_BAND_5G) { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; + #else + ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; + #endif + ra_mask_bak = ra_mask; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.vht_supported) { + #else + if (sta->vht_cap.vht_supported) { + #endif + ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; + wireless_set = WIRELESS_OFDM | WIRELESS_VHT; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + } else if (sta->deflink.ht_cap.ht_supported) { + #else + } else if (sta->ht_cap.ht_supported) { +@@ -1291,13 +1291,13 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + } + dm_info->rrsr_val_init = RRSR_INIT_5G; + } else if (hal->current_band_type == RTW_BAND_2G) { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; + #else + ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; + #endif + ra_mask_bak = ra_mask; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.vht_supported) { + #else + if (sta->vht_cap.vht_supported) { +@@ -1306,7 +1306,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + RA_MASK_OFDM_IN_VHT; + wireless_set = WIRELESS_CCK | WIRELESS_OFDM | + WIRELESS_HT | WIRELESS_VHT; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + } else if (sta->deflink.ht_cap.ht_supported) { + #else + } else if (sta->ht_cap.ht_supported) { +@@ -1315,7 +1315,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + RA_MASK_OFDM_IN_HT_2G; + wireless_set = WIRELESS_CCK | WIRELESS_OFDM | + WIRELESS_HT; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + } else if (sta->deflink.supp_rates[0] <= 0xf) { + #else + } else if (sta->supp_rates[0] <= 0xf) { +@@ -1332,14 +1332,14 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + wireless_set = 0; + } + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + switch (sta->deflink.bandwidth) { + #else + switch (sta->bandwidth) { + #endif + case IEEE80211_STA_RX_BW_80: + bw_mode = RTW_CHANNEL_WIDTH_80; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + is_support_sgi = sta->deflink.vht_cap.vht_supported && + (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); + #else +@@ -1349,7 +1349,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + break; + case IEEE80211_STA_RX_BW_40: + bw_mode = RTW_CHANNEL_WIDTH_40; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + is_support_sgi = sta->deflink.ht_cap.ht_supported && + (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); + #else +@@ -1359,7 +1359,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + break; + default: + bw_mode = RTW_CHANNEL_WIDTH_20; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + is_support_sgi = sta->deflink.ht_cap.ht_supported && + (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); + #else +@@ -1369,14 +1369,14 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + break; + } + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { + #else + if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { + #endif + tx_num = 2; + rf_type = RF_2T2R; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { + #else + } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { +@@ -1400,7 +1400,7 @@ void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, + si->ra_mask = ra_mask; + si->rate_id = rate_id; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) || defined(BUILD_OPENWRT) + rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); + #else + rtw_fw_send_ra_info(rtwdev, si); +@@ -1780,7 +1780,7 @@ static void rtw_vif_smps_iter(void *data, u8 *mac, + { + struct rtw_dev *rtwdev = (struct rtw_dev *)data; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) + #else + if (vif->type != NL80211_IFTYPE_STATION || !vif->bss_conf.assoc) +@@ -1788,13 +1788,13 @@ static void rtw_vif_smps_iter(void *data, u8 *mac, + return; + + if (rtwdev->hal.txrx_1ss) +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); + #else + ieee80211_request_smps(vif, IEEE80211_SMPS_STATIC); + #endif + else +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); + #else + ieee80211_request_smps(vif, IEEE80211_SMPS_OFF); +@@ -2516,7 +2516,7 @@ static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif) + if (vif->type != NL80211_IFTYPE_STATION) + return; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) || defined(BUILD_OPENWRT) + if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) + #else + if (vif->bss_conf.assoc || !is_zero_ether_addr(rtwvif->bssid)) +--- a/ps.c ++++ b/ps.c +@@ -334,7 +334,7 @@ void rtw_recalc_lps(struct rtw_dev *rtwdev, struct ieee80211_vif *new_vif) + __rtw_vif_recalc_lps(&data, new_vif); + rtw_iterate_vifs(rtwdev, rtw_vif_recalc_lps_iter, &data); + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) || defined(BUILD_OPENWRT) + if (data.count == 1 && data.found_vif->cfg.ps) { + rtwdev->ps_enabled = true; + } else { +--- a/tx.c ++++ b/tx.c +@@ -90,7 +90,7 @@ EXPORT_SYMBOL(rtw_tx_fill_tx_desc); + + static u8 get_tx_ampdu_factor(struct ieee80211_sta *sta) + { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + u8 exp = sta->deflink.ht_cap.ampdu_factor; + #else + u8 exp = sta->ht_cap.ampdu_factor; +@@ -105,7 +105,7 @@ static u8 get_tx_ampdu_factor(struct ieee80211_sta *sta) + + static u8 get_tx_ampdu_density(struct ieee80211_sta *sta) + { +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + return sta->deflink.ht_cap.ampdu_density; + #else + return sta->ht_cap.ampdu_density; +@@ -117,7 +117,7 @@ static u8 get_highest_ht_tx_rate(struct rtw_dev *rtwdev, + { + u8 rate; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (rtwdev->hal.rf_type == RF_2T2R && sta->deflink.ht_cap.mcs.rx_mask[1] != 0) + #else + if (rtwdev->hal.rf_type == RF_2T2R && sta->ht_cap.mcs.rx_mask[1] != 0) +@@ -136,7 +136,7 @@ static u8 get_highest_vht_tx_rate(struct rtw_dev *rtwdev, + u8 rate; + u16 tx_mcs_map; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + tx_mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.tx_mcs_map); + #else + tx_mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.tx_mcs_map); +@@ -382,7 +382,7 @@ static void rtw_tx_data_pkt_info_update(struct rtw_dev *rtwdev, + if (info->control.use_rts || skb->len > hw->wiphy->rts_threshold) + pkt_info->rts = true; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) || defined(BUILD_OPENWRT) + if (sta->deflink.vht_cap.vht_supported) + rate = get_highest_vht_tx_rate(rtwdev, sta); + else if (sta->deflink.ht_cap.ht_supported) diff --git a/package/kernel/rtw88-usb/patches/102-disable-pcie.patch b/package/kernel/rtw88-usb/patches/102-disable-pcie.patch new file mode 100644 index 000000000..f57ad4c88 --- /dev/null +++ b/package/kernel/rtw88-usb/patches/102-disable-pcie.patch @@ -0,0 +1,69 @@ +--- a/Makefile ++++ b/Makefile +@@ -30,10 +30,6 @@ NO_SKIP_SIGN := y + endif + + EXTRA_CFLAGS += -O2 +-EXTRA_CFLAGS += -DCONFIG_RTW88_8822BE=1 +-EXTRA_CFLAGS += -DCONFIG_RTW88_8821CE=1 +-EXTRA_CFLAGS += -DCONFIG_RTW88_8822CE=1 +-EXTRA_CFLAGS += -DCONFIG_RTW88_8723DE=1 + EXTRA_CFLAGS += -DCONFIG_RTW88_DEBUG=1 + EXTRA_CFLAGS += -DCONFIG_RTW88_DEBUGFS=1 + #EXTRA_CFLAGS += -DCONFIG_RTW88_REGD_USER_REG_HINTS +@@ -60,9 +56,6 @@ rtw_core-objs += main.o \ + obj-m += rtw_8822b.o + rtw_8822b-objs := rtw8822b.o rtw8822b_table.o + +-obj-m += rtw_8822be.o +-rtw_8822be-objs := rtw8822be.o +- + obj-m += rtw_8822bu.o + rtw_8822bu-objs := rtw8822bu.o + +@@ -72,9 +65,6 @@ rtw_8822bs-objs := rtw8822bs.o + obj-m += rtw_8822c.o + rtw_8822c-objs := rtw8822c.o rtw8822c_table.o + +-obj-m += rtw_8822ce.o +-rtw_8822ce-objs := rtw8822ce.o +- + obj-m += rtw_8822cu.o + rtw_8822cu-objs := rtw8822cu.o + +@@ -102,9 +92,6 @@ rtw_8723cs-objs := rtw8723cs.o + obj-m += rtw_8723d.o + rtw_8723d-objs := rtw8723d.o rtw8723d_table.o + +-obj-m += rtw_8723de.o +-rtw_8723de-objs := rtw8723de.o +- + obj-m += rtw_8723du.o + rtw_8723du-objs := rtw8723du.o + +@@ -114,15 +101,9 @@ rtw_8723ds-objs := rtw8723ds.o + obj-m += rtw_8821c.o + rtw_8821c-objs := rtw8821c.o rtw8821c_table.o + +-obj-m += rtw_8821ce.o +-rtw_8821ce-objs := rtw8821ce.o +- + obj-m += rtw_8821a.o + rtw_8821a-objs := rtw8821a.o rtw8821a_table.o + +-obj-m += rtw_8821ae.o +-rtw_8821ae-objs := rtw8821ae.o +- + obj-m += rtw_8821au.o + rtw_8821au-objs := rtw8821au.o + +@@ -132,9 +113,6 @@ rtw_8821cs-objs := rtw8821cs.o + obj-m += rtw_8821cu.o + rtw_8821cu-objs := rtw8821cu.o + +-obj-m += rtw_pci.o +-rtw_pci-objs := pci.o +- + obj-m += rtw_sdio.o + rtw_sdio-objs := sdio.o + diff --git a/package/lean/autocore/files/x86/autocore b/package/lean/autocore/files/x86/autocore index ecae6d7d2..f5d8a0106 100755 --- a/package/lean/autocore/files/x86/autocore +++ b/package/lean/autocore/files/x86/autocore @@ -66,9 +66,7 @@ start() ethtool -K $c tx-checksum-ipv4 on >/dev/null 2>&1 ethtool -K $c tx-checksum-ipv6 on >/dev/null 2>&1) ethtool -K $c tx-scatter-gather on >/dev/null 2>&1 - ethtool -K $c gso on >/dev/null 2>&1 ethtool -K $c tso on >/dev/null 2>&1 - ethtool -K $c ufo on >/dev/null 2>&1 done [ -f /etc/index.htm ] && mv /etc/index.htm /usr/lib/lua/luci/view/admin_status/index.htm diff --git a/package/lean/default-settings/files/zzz-default-settings b/package/lean/default-settings/files/zzz-default-settings index fa949ecf0..804667ed5 100755 --- a/package/lean/default-settings/files/zzz-default-settings +++ b/package/lean/default-settings/files/zzz-default-settings @@ -3,8 +3,16 @@ uci set luci.main.lang=zh_cn uci commit luci -uci set system.@system[0].timezone=CST-8 -uci set system.@system[0].zonename=Asia/Shanghai +uci -q batch <<-EOF + set system.@system[0].timezone='CST-8' + set system.@system[0].zonename='Asia/Shanghai' + + delete system.ntp.server + add_list system.ntp.server='ntp1.aliyun.com' + add_list system.ntp.server='ntp.tencent.com' + add_list system.ntp.server='ntp.ntsc.ac.cn' + add_list system.ntp.server='time.ustc.edu.cn' +EOF uci commit system uci set fstab.@global[0].anon_mount=1 @@ -28,28 +36,30 @@ sed -i 's/\"services\"/\"nas\"/g' /usr/lib/lua/luci/controller/usb_printer.lua sed -i 's/\"services\"/\"nas\"/g' /usr/lib/lua/luci/controller/xunlei.lua sed -i 's/services/nas/g' /usr/lib/lua/luci/view/minidlna_status.htm -ln -sf /sbin/ip /usr/bin/ip - -sed -i 's#downloads.openwrt.org#mirrors.cloud.tencent.com/lede#g' /etc/opkg/distfeeds.conf +sed -i 's#downloads.openwrt.org#mirrors.tencent.com/lede#g' /etc/opkg/distfeeds.conf sed -i 's/root::0:0:99999:7:::/root:$1$V4UetPzk$CYXluq4wUazHjmCDBCqXF.:0:0:99999:7:::/g' /etc/shadow sed -i 's/root:::0:99999:7:::/root:$1$V4UetPzk$CYXluq4wUazHjmCDBCqXF.:0:0:99999:7:::/g' /etc/shadow sed -i "s/# //g" /etc/opkg/distfeeds.conf sed -i '/openwrt_luci/ { s/snapshots/releases\/18.06.9/g; }' /etc/opkg/distfeeds.conf +sed -i '/check_signature/d' /etc/opkg.conf + sed -i '/REDIRECT --to-ports 53/d' /etc/firewall.user -# echo 'iptables -A OUTPUT -m string --string "api.installer.xiaomi.cn" --algo bm --to 65535 -j DROP' >> /etc/firewall.user sed -i '/option disabled/d' /etc/config/wireless +sed -i '/set wireless.radio${devidx}.disabled/d' /lib/wifi/mac80211.sh sed -i '/DISTRIB_REVISION/d' /etc/openwrt_release -echo "DISTRIB_REVISION='R24.06.29-D'" >> /etc/openwrt_release +echo "DISTRIB_REVISION='R24.07.19-D'" >> /etc/openwrt_release sed -i '/DISTRIB_DESCRIPTION/d' /etc/openwrt_release echo "DISTRIB_DESCRIPTION='OpenWrt '" >> /etc/openwrt_release sed -i '/log-facility/d' /etc/dnsmasq.conf echo "log-facility=/dev/null" >> /etc/dnsmasq.conf +#ln -sf /sbin/ip /usr/bin/ip + rm -rf /tmp/luci-modulecache/ rm -f /tmp/luci-indexcache diff --git a/package/lean/r8101/Makefile b/package/lean/r8101/Makefile new file mode 100644 index 000000000..232ad16f0 --- /dev/null +++ b/package/lean/r8101/Makefile @@ -0,0 +1,39 @@ +# +# Download realtek r8101 linux driver from official site: +# [https://www.realtek.com/component/zoo/category/network-interface-controllers-10-100-1000m-gigabit-ethernet-pci-express-software] +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=r8101 +PKG_VERSION:=1.038.02 +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/sbwml/package_kernel_r8101 +PKG_SOURCE_VERSION:=5dea36329c0524490c093991801973fc48d92a8b +PKG_MIRROR_HASH:=f4182719b25cd177023dddd6f0f555597c8e340fa38127566681d10be885dd9a + +PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/r8101 + TITLE:=Driver for Realtek r8101 chipsets + SUBMENU:=Network Devices + VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(PKG_RELEASE) + DEPENDS:=@PCI_SUPPORT + FILES:= $(PKG_BUILD_DIR)/src/r8101.ko + AUTOLOAD:=$(call AutoProbe,r8101) +endef + +define Package/r8101/description + This package contains a driver for Realtek r8101 chipsets. +endef + +define Build/Compile + +$(KERNEL_MAKE) M=$(PKG_BUILD_DIR)/src modules +endef + +$(eval $(call KernelPackage,r8101)) diff --git a/package/lean/r8101/patches/010-6.1-support.patch b/package/lean/r8101/patches/010-6.1-support.patch new file mode 100644 index 000000000..489d2ebed --- /dev/null +++ b/package/lean/r8101/patches/010-6.1-support.patch @@ -0,0 +1,14 @@ +--- a/src/r8101.h +--- b/src/r8101.h +@@ -492,7 +492,11 @@ + typedef struct napi_struct *napi_ptr; + typedef int napi_budget; + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) ++#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add_weight(ndev, &priv->napi, function, weight) ++#else + #define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add(ndev, &priv->napi, function, weight) ++#endif + #define RTL_NAPI_QUOTA(budget, ndev) min(budget, budget) + #define RTL_GET_PRIV(stuct_ptr, priv_struct) container_of(stuct_ptr, priv_struct, stuct_ptr) + #define RTL_GET_NETDEV(priv_ptr) struct net_device *dev = priv_ptr->dev; diff --git a/package/utils/f2fs-tools/Makefile b/package/utils/f2fs-tools/Makefile index d5dc1a6d7..d11e89d8e 100644 --- a/package/utils/f2fs-tools/Makefile +++ b/package/utils/f2fs-tools/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=f2fs-tools PKG_VERSION:=1.16.0 -PKG_RELEASE:=2 +PKG_RELEASE:=3 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git/snapshot/ @@ -137,6 +137,7 @@ define Package/f2fsck/install $(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/dump.f2fs $(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/sload.f2fs $(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/resize.f2fs + $(LN) ../sbin/fsck.f2fs $(1)/usr/sbin/f2fslabel endef Package/f2fsck-selinux/install = $(Package/f2fsck/install) diff --git a/package/utils/lua/Makefile b/package/utils/lua/Makefile index e4d2fd1c5..247a2a7ca 100644 --- a/package/utils/lua/Makefile +++ b/package/utils/lua/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=lua PKG_VERSION:=5.1.5 -PKG_RELEASE:=10 +PKG_RELEASE:=11 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://www.lua.org/ftp/ \ diff --git a/package/utils/lua/patches-host/001-include-version-number.patch b/package/utils/lua/patches-host/001-include-version-number.patch index f769e6073..806d37003 100644 --- a/package/utils/lua/patches-host/001-include-version-number.patch +++ b/package/utils/lua/patches-host/001-include-version-number.patch @@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist. Signed-off-by: Rafał Miłecki --- -diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -41,10 +41,10 @@ RANLIB= ranlib @@ -42,7 +41,7 @@ rename to doc/luac5.1.1 diff --git a/src/Makefile b/src/Makefile --- a/src/Makefile +++ b/src/Makefile -@@ -29,10 +29,10 @@ CORE_O= lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \ +@@ -29,10 +29,10 @@ CORE_O= lapi.o lcode.o ldebug.o ldo.o ld LIB_O= lauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \ lstrlib.o loadlib.o linit.o diff --git a/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch b/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch index 7f00c8c3a..888722958 100644 --- a/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch +++ b/package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch @@ -1,8 +1,6 @@ -diff --git a/src/lnum.c b/src/lnum.c -index 1456b6a2ed23..b0632b04c2b7 100644 --- a/src/lnum.c +++ b/src/lnum.c -@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) { +@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lu #else return 0; /* Reject the number */ #endif @@ -11,7 +9,7 @@ index 1456b6a2ed23..b0632b04c2b7 100644 } } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) { return TK_NUMBER; /* not in signed range, or has '.', 'e' etc. trailing */ -@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) { +@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Inte return 0; } @@ -25,8 +23,6 @@ index 1456b6a2ed23..b0632b04c2b7 100644 + return (unsigned LUA_INTEGER)v; +} +#endif -diff --git a/src/lnum_config.h b/src/lnum_config.h -index 19d7a4231a49..1092eead6629 100644 --- a/src/lnum_config.h +++ b/src/lnum_config.h @@ -141,7 +141,12 @@ @@ -43,6 +39,3 @@ index 19d7a4231a49..1092eead6629 100644 #endif #ifndef LUA_INTEGER_MIN # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1) /* -2^16|32 */ --- -1.9.1 - diff --git a/package/utils/lua/patches-host/100-no_readline.patch b/package/utils/lua/patches-host/100-no_readline.patch index 209c302bb..700114e43 100644 --- a/package/utils/lua/patches-host/100-no_readline.patch +++ b/package/utils/lua/patches-host/100-no_readline.patch @@ -10,7 +10,7 @@ #if defined(LUA_USE_MACOSX) --- a/src/Makefile +++ b/src/Makefile -@@ -17,6 +17,7 @@ +@@ -17,6 +17,7 @@ LIBS= -lm $(MYLIBS) MYCFLAGS= MYLDFLAGS= MYLIBS= @@ -18,7 +18,7 @@ # == END OF USER SETTINGS. NO NEED TO CHANGE ANYTHING BELOW THIS LINE ========= -@@ -75,7 +76,7 @@ +@@ -75,7 +76,7 @@ echo: @echo "MYLIBS = $(MYLIBS)" # convenience targets for popular platforms @@ -27,7 +27,7 @@ none: @echo "Please choose a platform:" @echo " $(PLATS)" -@@ -90,16 +91,16 @@ +@@ -90,16 +91,16 @@ bsd: $(MAKE) all MYCFLAGS="-DLUA_USE_POSIX -DLUA_USE_DLOPEN" MYLIBS="-Wl,-E" freebsd: diff --git a/package/utils/lua/patches-host/400-CVE-2014-5461.patch b/package/utils/lua/patches-host/400-CVE-2014-5461.patch new file mode 100644 index 000000000..cce73ff96 --- /dev/null +++ b/package/utils/lua/patches-host/400-CVE-2014-5461.patch @@ -0,0 +1,19 @@ +From: Enrico Tassi +Date: Tue, 26 Aug 2014 16:20:55 +0200 +Subject: Fix stack overflow in vararg functions + +--- + src/ldo.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/src/ldo.c ++++ b/src/ldo.c +@@ -274,7 +274,7 @@ int luaD_precall (lua_State *L, StkId fu + CallInfo *ci; + StkId st, base; + Proto *p = cl->p; +- luaD_checkstack(L, p->maxstacksize); ++ luaD_checkstack(L, p->maxstacksize + p->numparams); + func = restorestack(L, funcr); + if (!p->is_vararg) { /* no varargs? */ + base = func + 1; diff --git a/package/utils/lua/patches/001-include-version-number.patch b/package/utils/lua/patches/001-include-version-number.patch index f769e6073..806d37003 100644 --- a/package/utils/lua/patches/001-include-version-number.patch +++ b/package/utils/lua/patches/001-include-version-number.patch @@ -8,7 +8,6 @@ Including it allows multiple lua versions to coexist. Signed-off-by: Rafał Miłecki --- -diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -41,10 +41,10 @@ RANLIB= ranlib @@ -42,7 +41,7 @@ rename to doc/luac5.1.1 diff --git a/src/Makefile b/src/Makefile --- a/src/Makefile +++ b/src/Makefile -@@ -29,10 +29,10 @@ CORE_O= lapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \ +@@ -29,10 +29,10 @@ CORE_O= lapi.o lcode.o ldebug.o ldo.o ld LIB_O= lauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \ lstrlib.o loadlib.o linit.o diff --git a/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch b/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch index 7f00c8c3a..888722958 100644 --- a/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch +++ b/package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch @@ -1,8 +1,6 @@ -diff --git a/src/lnum.c b/src/lnum.c -index 1456b6a2ed23..b0632b04c2b7 100644 --- a/src/lnum.c +++ b/src/lnum.c -@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) { +@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lu #else return 0; /* Reject the number */ #endif @@ -11,7 +9,7 @@ index 1456b6a2ed23..b0632b04c2b7 100644 } } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) { return TK_NUMBER; /* not in signed range, or has '.', 'e' etc. trailing */ -@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) { +@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Inte return 0; } @@ -25,8 +23,6 @@ index 1456b6a2ed23..b0632b04c2b7 100644 + return (unsigned LUA_INTEGER)v; +} +#endif -diff --git a/src/lnum_config.h b/src/lnum_config.h -index 19d7a4231a49..1092eead6629 100644 --- a/src/lnum_config.h +++ b/src/lnum_config.h @@ -141,7 +141,12 @@ @@ -43,6 +39,3 @@ index 19d7a4231a49..1092eead6629 100644 #endif #ifndef LUA_INTEGER_MIN # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1) /* -2^16|32 */ --- -1.9.1 - diff --git a/package/utils/lua/patches/400-CVE-2014-5461.patch b/package/utils/lua/patches/400-CVE-2014-5461.patch new file mode 100644 index 000000000..cce73ff96 --- /dev/null +++ b/package/utils/lua/patches/400-CVE-2014-5461.patch @@ -0,0 +1,19 @@ +From: Enrico Tassi +Date: Tue, 26 Aug 2014 16:20:55 +0200 +Subject: Fix stack overflow in vararg functions + +--- + src/ldo.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/src/ldo.c ++++ b/src/ldo.c +@@ -274,7 +274,7 @@ int luaD_precall (lua_State *L, StkId fu + CallInfo *ci; + StkId st, base; + Proto *p = cl->p; +- luaD_checkstack(L, p->maxstacksize); ++ luaD_checkstack(L, p->maxstacksize + p->numparams); + func = restorestack(L, funcr); + if (!p->is_vararg) { /* no varargs? */ + base = func + 1; diff --git a/package/wwan/luci-app-modem/Makefile b/package/wwan/luci-app-modem/Makefile index 16a8cc292..ba7cbe485 100644 --- a/package/wwan/luci-app-modem/Makefile +++ b/package/wwan/luci-app-modem/Makefile @@ -24,7 +24,6 @@ LUCI_DEPENDS:=+luci-compat \ +kmod-pcie_mhi \ +pciutils \ +quectel-CM-5G \ - +sms-tool \ +jq define Package/luci-app-modem/conffiles diff --git a/package/wwan/luci-app-sms-tool/LICENSE b/package/wwan/luci-app-sms-tool/LICENSE deleted file mode 100644 index f288702d2..000000000 --- a/package/wwan/luci-app-sms-tool/LICENSE +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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But first, please read -. diff --git a/package/wwan/luci-app-sms-tool/Makefile b/package/wwan/luci-app-sms-tool/Makefile deleted file mode 100644 index db9d2a20c..000000000 --- a/package/wwan/luci-app-sms-tool/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (C) 2023 Siriling -# This is free software, licensed under the GNU General Public License v3. - -include $(TOPDIR)/rules.mk - -PKG_NAME:=luci-app-sms-tool -LUCI_TITLE:=LuCI Support for sms_tool -LUCI_PKGARCH:=all -PKG_VERSION:=1.0.0 -PKG_LICENSE:=GPLv3 -PKG_LINCESE_FILES:=LICENSE -PKF_MAINTAINER:=siriling -LUCI_DEPENDS:=+sms-tool +luci-compat +kmod-usb-serial +kmod-usb-serial-option - -define Package/luci-app-sms-tool/postinst -#!/bin/sh -rm -rf /tmp/luci-indexcache -rm -rf /tmp/luci-modulecache/ -/sbin/set_sms_ports.sh -exit 0 -endef - -define Package/$(PKG_NAME)/config -# shown in make menuconfig -help - $(LUCI_TITLE) - Version: $(PKG_VERSION) -endef - -include $(TOPDIR)/feeds/luci/luci.mk - -# call BuildPackage - OpenWrt buildroot signature diff --git a/package/wwan/luci-app-sms-tool/htdocs/luci-static/resources/icons/delsms.png b/package/wwan/luci-app-sms-tool/htdocs/luci-static/resources/icons/delsms.png deleted file mode 100644 index b036e813f546c56ad0e934e1c7ec9ee359f469b4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9221 zcmV+gB>LNlP) zaB^>EX>4U6ba`-PAZ2)IW&i+q+O3;cc4WD7MgK7h4FTQ^2X-yZK*QHQK$69(?v|cR zu}LP=;9ejijtQX6{*Qk@=HK{NT(l;pQgh4M@-Md7eCI*6?_a+^osIYB`{V01_xtna z`vuQaf#2c%S@Y-l&GVl3`_J?9GfwCE^kbm5KQD~mU+ABKeEnSD^ZeI^f_oRR>oZXQ z3>5t5%JKa@K3C4ImY-Aje9oTF>vtLWHu@1m@i}EzB0rTN8n+e-I?zUgym zd=2#b-{$MBo_q2;xM1&3|L!vA+l8)Y?$5;gT&O(uq4AS@cz0_E8MnaW_F3D{qW;sr zf4Y0~^Y%Ys|1GTFkK8{z|B1HwibD3E7s4M=%HO~L_Ia1S2KpncH+Da+oa^_Me|x?p z*MCmge1%Wn=d60pezWT_Gv)l5)Ynw*Bi=W(TK7|#uVS+y2`dlu)%dEE#Uz)Oop$gw zU2~pL9v9tm-5s~@@98GD82$Ez-`-C{boFE<7|qY1;6{D9;|l>^gxZHmN(7$u-}mC~ zW!t^nq|BDF%kft47)-hHzy31+>Ko6k3FmD6UMud)E9j=Mo@irpj&Sz26UEr^; zKmRGNfe5C%%#{gtJIotmB=;-1!VPrbjfvl{h+SEq0azj~owyknh=9%1jmz9o@xD06 zLRJFQxpg0+A4I^VXUy@1BM}*kU|cH*ieE5E5=0rlvv53 zo5b((YCK!Y*APx{k`yx{=A$Fv zg{ToR5?e8|)y3!)ImOI2PgNw(O(q3rIYo>J#_fDM?mKp$$Qf4g|0Qmw)EhVde~p|` z=>EmX{WWfX7qun4n>S*w47I2>P<_07@l{|vf#@a;yDbQ_BwmtM=te5WJB(a>Tfyu8Jnv+_dJ&1U@n!uAfoJI;y)AXd^a3L&%Wh4lZaa{etxsiT)p#X%|%oacwQOr zz7pP_)}%hyis7unLJejVS8geS4ZX*`U8{pE%%OH+@0@NCk?jQBVJvcnWIDv?`n4A9IV=)DmzWZTfAA}L2sK>TCwY(!G-StUY;g#BD`Fp9Fhh{tbyRdgP zy+<_~M$ZJcCA$^_?K8L{*f*B08BXb$Bs-Iv;qR)9_6PFX-nC|jUrZhr4TiNy-)}nE z_61X&!?+|?ITSYqnwZeczOEJ0DURrd$!%}jPHk>(a?5N+sdM;pjvJkyWWzo#ltaem zcZqUxylWCl+I!iuR2qG_RLkiz)wQ=_(t$^z4ziGsFb+eC#`MuU(i=yk*f|cVFp0~s ziRmvt1vfJeqgxU2C1$ZQ*WwzKq3(l6trtMnO#yR1qbA?)yeyT&Qs&VzI7V#@Gq{=F zGI8_-t}$N?GTbIydUPZ>`Z!F+<#&NK-o*n|x3=e=n=NMEC)0|B97uCgL8yg5p#X(c zgaS@>lK)d#0DNWD5fGRT@YVgMsFqKJKTVtFa!sH`ImHI*QZ?k|%q~$z(ajSGl0YI6 zOHaOQF$ZAkS7}tyY$lL~i=^ZmfIkWJBK?_u%+wRvmQG8KD)}no1Ww*r^h$=6ary-! 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" delete " .. d .. "") -end -end - -function delete_all_sms() - local devv = tostring(uci:get("sms_tool", "general", "readport")) - os.execute("sms_tool -d " .. devv .. " delete all") -end - -function get_ussd() - local cursor = luci.model.uci.cursor() - if cursor:get("sms_tool", "general", "ussd") == "1" then - return " -R" - else - return "" - end -end - - -function get_pdu() - local cursor = luci.model.uci.cursor() - if cursor:get("sms_tool", "general", "pdu") == "1" then - return " -r" - else - return "" - end -end - - -function ussd() - local devv = tostring(uci:get("sms_tool", "general", "ussdport")) - - local ussd = get_ussd() - local pdu = get_pdu() - - local ussd_code = http.formvalue("code") - if ussd_code then - local odpall = io.popen("sms_tool -d " .. devv .. ussd .. pdu .. " ussd " .. ussd_code .." 2>&1") - local odp = odpall:read("*a") - odpall:close() - http.write(tostring(odp)) - else - http.write_json(http.formvalue()) - end -end - - -function at() - local devv = tostring(uci:get("sms_tool", "general", "atport")) - - local at_code = http.formvalue("code") - if at_code then - local odpall = io.popen("sms_tool -d " .. devv .. " at " ..at_code:gsub("[$]", "\\\$"):gsub("\"", "\\\"").." 2>&1") - local odp = odpall:read("*a") - odpall:close() - http.write(tostring(odp)) - else - http.write_json(http.formvalue()) - end -end - - -function sms() - local devv = tostring(uci:get("sms_tool", "general", "sendport")) - local sms_code = http.formvalue("scode") - - nr = (string.sub(sms_code, 1, 20)) - msgall = string.sub(sms_code, 21) - msg = string.gsub(msgall, "\n", " ") - - if sms_code then - local odpall = io.popen("sms_tool -d " .. devv .. " send " .. nr .." '".. msg .."'") - local odp = odpall:read("*a") - odpall:close() - http.write(tostring(odp)) - else - http.write_json(http.formvalue()) - end - -end - -function slots() - local sim = { } - local devv = tostring(uci:get("sms_tool", "general", "readport")) - local led = tostring(uci:get("sms_tool", "general", "smsled")) - local dsled = tostring(uci:get("sms_tool", "general", "ledtype")) - local ln = tostring(uci:get("sms_tool", "general", "lednotify")) - - local smsmem = tostring(uci:get("sms_tool", "general", "storage")) - - local statusb = luci.util.exec("sms_tool -s" .. smsmem .. " -d ".. devv .. " status") - local usex = string.sub (statusb, 23, 27) - local max = statusb:match('[^: ]+$') - sim["use"] = string.match(usex, '%d+') - local smscount = string.match(usex, '%d+') - if ln == "1" then - luci.sys.call("echo " .. smscount .. " > /etc/config/sms_count") - if dsled == "S" then - luci.util.exec("/etc/init.d/led restart") - end - if dsled == "D" then - luci.sys.call("echo 0 > '/sys/class/leds/" .. led .. "/brightness'") - end - end - sim["all"] = string.match(max, '%d+') - luci.http.prepare_content("application/json") - luci.http.write_json(sim) -end - - -function count_sms() - os.execute("sleep 3") - local cursor = luci.model.uci.cursor() - if cursor:get("sms_tool", "general", "lednotify") == "1" then - local devv = tostring(uci:get("sms_tool", "general", "readport")) - - local smsmem = tostring(uci:get("sms_tool", "general", "storage")) - - local statusb = luci.util.exec("sms_tool -s" .. smsmem .. " -d ".. devv .. " status") - local smsnum = string.sub (statusb, 23, 27) - local smscount = string.match(smsnum, '%d+') - os.execute("echo " .. smscount .. " > /etc/config/sms_count") - end -end - - -function uussd(rv) - local c = nixio.fs.access("/etc/config/ussd.user") and - io.popen("cat /etc/config/ussd.user") - - if c then - for l in c:lines() do - local i = l - if i then - rv[#rv + 1] = { - usd = i - } - end - end - c:close() - end -end - - - -function userussd() - local usd = { } - uussd(usd) - luci.http.prepare_content("application/json") - luci.http.write_json(usd) -end - - -function uat(rv) - local c = nixio.fs.access("/etc/config/atcmds.user") and - io.popen("cat /etc/config/atcmds.user") - - if c then - for l in c:lines() do - local i = l - if i then - rv[#rv + 1] = { - atu = i - } - end - end - c:close() - end -end - - - -function useratc() - local atu = { } - uat(atu) - luci.http.prepare_content("application/json") - luci.http.write_json(atu) -end - - - -function uphb(rv) - local c = nixio.fs.access("/etc/config/phonebook.user") and - io.popen("cat /etc/config/phonebook.user") - - if c then - for l in c:lines() do - local i = l - if i then - rv[#rv + 1] = { - phb = i - } - end - end - c:close() - end -end - - - -function userphb() - local phb = { } - uphb(phb) - luci.http.prepare_content("application/json") - luci.http.write_json(phb) -end diff --git a/package/wwan/luci-app-sms-tool/luasrc/model/cbi/modem/smsconfig.lua b/package/wwan/luci-app-sms-tool/luasrc/model/cbi/modem/smsconfig.lua deleted file mode 100644 index dc756e5c4..000000000 --- a/package/wwan/luci-app-sms-tool/luasrc/model/cbi/modem/smsconfig.lua +++ /dev/null @@ -1,226 +0,0 @@ -local util = require "luci.util" -local fs = require "nixio.fs" -local sys = require "luci.sys" -local http = require "luci.http" -local dispatcher = require "luci.dispatcher" -local http = require "luci.http" -local sys = require "luci.sys" -local uci = require "luci.model.uci".cursor() - -local USSD_FILE_PATH = "/etc/config/ussd.user" -local PHB_FILE_PATH = "/etc/config/phonebook.user" -local SMSC_FILE_PATH = "/etc/config/smscommands.user" -local AT_FILE_PATH = "/etc/config/atcmds.user" - -local led = tostring(uci:get("sms_tool", "general", "smsled")) -local dsled = tostring(uci:get("sms_tool", "general", "ledtype")) -local ledtime = tostring(uci:get("sms_tool", "general", "checktime")) - -local m -local s -local dev1, dev2, dev3, dev4, leds -local try_devices1 = nixio.fs.glob("/dev/tty[A-Z][A-Z]*") -local try_devices2 = nixio.fs.glob("/dev/tty[A-Z][A-Z]*") -local try_devices3 = nixio.fs.glob("/dev/tty[A-Z][A-Z]*") -local try_devices4 = nixio.fs.glob("/dev/tty[A-Z][A-Z]*") -local try_leds = nixio.fs.glob("/sys/class/leds/*") - - -local devv = tostring(uci:get("sms_tool", "general", "readport")) - -local smsmem = tostring(uci:get("sms_tool", "general", "storage")) - -local statusb = luci.util.exec("sms_tool -s".. smsmem .. " -d ".. devv .. " status") - -local smsnum = string.sub (statusb, 23, 27) - -local smscount = string.match(smsnum, '%d+') - -m = Map("sms_tool", translate("配置短信工具"), - translate("sms_tool和gui应用程序的配置面板。")) - -s = m:section(NamedSection, 'general' , "sms_tool" , "" .. translate("")) -s.anonymous = true -s:tab("sms", translate("SMS 设置")) -s:tab("ussd", translate("USSD 代码设置")) -s:tab("at", translate("AT 命令设置")) -s:tab("info", translate("通知设置")) - -this_tab = "sms" - -dev1 = s:taboption(this_tab, Value, "readport", translate("短信读取端口")) -if try_devices1 then -local node -for node in try_devices1 do -dev1:value(node, node) -end -end - -mem = s:taboption(this_tab, ListValue, "storage", translate("信息存储区"), translate("信息存储在一个特定的位置（例如，在SIM卡或调制解调器内存），但根据设备的类型，其他区域也可能是可用的。")) -mem.default = "SM" -mem:value("SM", translate("SIM 卡")) -mem:value("ME", translate("调制解调器内存")) -mem.rmempty = true - -local msm = s:taboption(this_tab, Flag, "mergesms", translate("合并分割的信息"), translate("勾选这个选项会使阅读信息更容易，但会导致显示和接收的信息数量不一致。")) -msm.rmempty = false - -dev2 = s:taboption(this_tab, Value, "sendport", translate("短信发送端口")) -if try_devices2 then -local node -for node in try_devices2 do -dev2:value(node, node) -end -end - -local t = s:taboption(this_tab, Value, "pnumber", translate("前缀号码"), translate("电话号码的前面应该有国家的前缀（波兰是48，没有'+'）。如果号码是5个、4个或3个字符，它将被视为 '短'，不应该在前面加上国家前缀。")) -t.rmempty = true -t.default = 48 - -local f = s:taboption(this_tab, Flag, "prefix", translate("为电话号码添加前缀"), translate("自动添加电话号码字段的前缀。")) -f.rmempty = false - - -local i = s:taboption(this_tab, Flag, "information", translate("号码和前缀的解释"), translate("在发送短信的标签中，显示前缀的解释和正确的电话号码。")) -i.rmempty = false - -local ta = s:taboption(this_tab, TextValue, "user_phonebook", translate("用户电话簿"), translate("每一行必须有以下格式。'联系人姓名;电话号码'。保存到文件'/etc/config/phonebook.user'。")) -ta.rows = 7 -ta.rmempty = false - -function ta.cfgvalue(self, section) - return fs.readfile(PHB_FILE_PATH) -end - -function ta.write(self, section, value) - value = value:gsub("\r\n", "\n") - fs.writefile(PHB_FILE_PATH, value) -end - -this_taba = "ussd" - -dev3 = s:taboption(this_taba, Value, "ussdport", translate("USSD发送端口")) -if try_devices3 then -local node -for node in try_devices3 do -dev3:value(node, node) -end -end - -local u = s:taboption(this_taba, Flag, "ussd", translate("以纯文本发送USSD代码"), translate("以纯文本发送USSD代码。命令没有被编码到PDU中。")) -u.rmempty = false - -local p = s:taboption(this_taba, Flag, "pdu", translate("接收没有PDU解码的信息"), translate("接收并显示消息，而不将其解码为PDU。")) -p.rmempty = false - -local tb = s:taboption(this_taba, TextValue, "user_ussd", translate("用户USSD代码"), translate("每一行必须有以下格式。'代码名称;代码'。保存到文件'/etc/config/ussd.user'。")) -tb.rows = 7 -tb.rmempty = true - -function tb.cfgvalue(self, section) - return fs.readfile(USSD_FILE_PATH) -end - -function tb.write(self, section, value) - value = value:gsub("\r\n", "\n") - fs.writefile(USSD_FILE_PATH, value) -end - -this_tabc = "at" - -dev4 = s:taboption(this_tabc, Value, "atport", translate("AT命令的发送端口")) -if try_devices4 then -local node -for node in try_devices4 do -dev4:value(node, node) -end -end - -local tat = s:taboption(this_tabc, TextValue, "user_at", translate("用户AT命令"), translate("每一行必须有以下格式。'AT命令名称;AT命令'。保存到文件'/etc/config/atcmds.user'。")) -tat.rows = 20 -tat.rmempty = true - -function tat.cfgvalue(self, section) - return fs.readfile(AT_FILE_PATH) -end - -function tat.write(self, section, value) - value = value:gsub("\r\n", "\n") - fs.writefile(AT_FILE_PATH, value) -end - -this_tabb = "info" - -local uw = s:taboption(this_tabb, Flag, "lednotify", translate("通知新消息"), translate("LED通知有新的信息。在激活这个功能之前，请配置并保存短信阅读端口，检查短信收件箱的时间，并选择通知LED。")) -uw.rmempty = false - -function uw.write(self, section, value) -if devv ~= nil or devv ~= '' then -if ( smscount ~= nil and led ~= nil ) then - if value == '1' then - - luci.sys.call("echo " .. smscount .. " > /etc/config/sms_count") - luci.sys.call("uci set sms_tool.general.lednotify=" .. 1 .. ";/etc/init.d/smsled enable;/etc/init.d/smsled start") - luci.sys.call("/sbin/cronsync.sh") - - elseif value == '0' then - luci.sys.call("uci set sms_tool.general.lednotify=" .. 0 .. ";/etc/init.d/smsled stop;/etc/init.d/smsled disable") - if dsled == 'D' then - luci.sys.call("echo 0 > '/sys/class/leds/" .. led .. "/brightness'") - end - luci.sys.call("/sbin/cronsync.sh") - - end -return Flag.write(self, section ,value) - end -end -end - -local time = s:taboption(this_tabb, Value, "checktime", translate("每(几)分钟检查一次收件箱"), translate("指定你想在多少分钟内检查你的收件箱。")) -time.rmempty = false -time.maxlength = 2 -time.default = 5 - -function time.validate(self, value) - if ( tonumber(value) < 60 and tonumber(value) > 0 ) then - return value - end -end - -sync = s:taboption(this_tabb, ListValue, "prestart", translate("每隔一段时间重新启动收件箱检查程序"), translate("该过程将在选定的时间间隔内重新启动。这将消除检查收件箱的延迟。")) -sync.default = "6" -sync:value("4", translate("4h")) -sync:value("6", translate("6h")) -sync:value("8", translate("8h")) -sync:value("12", translate("12h")) -sync.rmempty = true - - -leds = s:taboption(this_tabb, Value, "smsled", translate("通知LED"), translate("选择通知LED。")) -if try_leds then -local node -local status -for node in try_leds do -local status = node -local all = string.sub (status, 17) -leds:value(all, all) -end -end - -oled = s:taboption(this_tabb, ListValue, "ledtype", translate("该二极管只专门用于这些通知"), translate("如果路由器只有一个LED，或者LED是多任务的，就选'No'。")) -oled.default = "D" -oled:value("S", translate("No")) -oled:value("D", translate("Yes")) -oled.rmempty = true - -local timeon = s:taboption(this_tabb, Value, "ledtimeon", translate("每(几)秒打开LED灯"), translate("指定LED应该亮多长时间。")) -timeon.rmempty = false -timeon.maxlength = 3 -timeon.default = 1 - -local timeoff = s:taboption(this_tabb, Value, "ledtimeoff", translate("每(几)秒关闭LED灯"), translate("指定LED应该关闭多长时间。")) -timeoff.rmempty = false -timeoff.maxlength = 3 -timeoff.default = 5 - -return m diff --git a/package/wwan/luci-app-sms-tool/luasrc/view/modem/atcommands.htm b/package/wwan/luci-app-sms-tool/luasrc/view/modem/atcommands.htm deleted file mode 100644 index 3510d8b87..000000000 --- a/package/wwan/luci-app-sms-tool/luasrc/view/modem/atcommands.htm +++ /dev/null @@ -1,136 +0,0 @@ -<%+header%> - - - -

    <%:AT 命令%>

    -     -

    -

    <%:向调制解调器发送命令%>

    -
    - -
    -
    <%:用户AT命令%>:
    - -
    - -
    -
    -
    - -
    -
    <%:要发送的命令%>:
    -
    -
    - -
    - -
    -
    <%:回复%>: -

    -

    - -
    -
    -
    - -
    - - - -<%+footer%> - diff --git a/package/wwan/luci-app-sms-tool/luasrc/view/modem/readsms.htm b/package/wwan/luci-app-sms-tool/luasrc/view/modem/readsms.htm deleted file mode 100644 index dc8245e2d..000000000 --- a/package/wwan/luci-app-sms-tool/luasrc/view/modem/readsms.htm +++ /dev/null @@ -1,285 +0,0 @@ -<% - local util = require "luci.util" - local fs = require "nixio.fs" - local sys = require "luci.sys" - local http = require "luci.http" - local dispatcher = require "luci.dispatcher" - local uci = require "luci.model.uci".cursor() - - local devv = tostring(uci:get("sms_tool", "general", "readport")) - local smsmem = tostring(uci:get("sms_tool", "general", "storage")) - local sms = tostring(luci.sys.exec("sms_tool -s" .. smsmem .. " -d " .. devv .. " -f '%Y-%m-%d %H:%M' -j recv 2>/dev/null")) - local smsmer = tostring(uci:get("sms_tool", "general", "mergesms")) - local smscuta = string.sub (sms, 8) - local smscut = smscuta:sub(1, #smscuta - 2) - local statusb = luci.util.exec("sms_tool -s" .. smsmem .. " -d ".. devv .. " status") - local all = statusb:match('[^: ]+$') - local location = "" - local l = string.sub (statusb, 15, 16) - if l == "SM" then - location = translate("SIM card") - end - if l == "ME" then - location = translate("Modem memory") - end --%> - -<%+header%> - - - - - - - -

    <%:短信%>

    -
    <%:通过sms_tool接收信息的Web用户界面。关于短信工具的更多信息，请见%> <%:eko.one.pl 论坛%>。
    -

    -

    <%:接收的信息%>

    -
    -
    <%:信息存储在%>:
    <%=location%>
    -
    <%:信息 (收件箱 / 最大值)%>:
    -
    - - - - - - - - - - -
    <%:来自%><%:收到%><%:信息%>
    - -
    -
    - -
    -
    -     - -
    -
    - -<%+footer%> diff --git a/package/wwan/luci-app-sms-tool/luasrc/view/modem/sendsms.htm b/package/wwan/luci-app-sms-tool/luasrc/view/modem/sendsms.htm deleted file mode 100644 index f9747c6a5..000000000 --- a/package/wwan/luci-app-sms-tool/luasrc/view/modem/sendsms.htm +++ /dev/null @@ -1,237 +0,0 @@ -<% - local util = require "luci.util" - local sys = require "luci.sys" - local uci = require "luci.model.uci".cursor() - - local pon = tostring(uci:get("sms_tool", "general", "prefix")) - local pnumber = tostring(uci:get("sms_tool", "general", "pnumber")) - local info = tostring(uci:get("sms_tool", "general", "information")) - --%> - -<%+header%> - - - - - - - - -

    <%:短信%>

    -
    <%:通过sms_tool发送信息的Web用户界面。关于短信工具的更多信息，请见%> <%:eko.one.pl 论坛%>.
    -

    - -

    <%:发送短信%>

    - -
    - -
    -
    <%:用户电话簿%>:
    -
    - - -
    -
    -
    - -
    -
    <%:发送至%>:
    -
    -
    -
    -
    -
    <%:消息正文%>:
    -
    160
    -
    -
    - -
    -
    <%:状态%>:
    - -
    - -
    -
    - -
    -
    -
    - -
    - - - -<%+footer%> diff --git a/package/wwan/luci-app-sms-tool/luasrc/view/modem/ussd.htm b/package/wwan/luci-app-sms-tool/luasrc/view/modem/ussd.htm deleted file mode 100644 index 38be1c3c4..000000000 --- a/package/wwan/luci-app-sms-tool/luasrc/view/modem/ussd.htm +++ /dev/null @@ -1,265 +0,0 @@ -<% - local util = require "luci.util" - local fs = require "nixio.fs" - local sys = require "luci.sys" - local http = require "luci.http" - local dispatcher = require "luci.dispatcher" - local uci = require "luci.model.uci".cursor() - --%> - - -<%+header%> - - - -

    <%:USSD 代码%>

    -
    <%:通过sms_tool处理USSD代码的Web用户界面。关于短信工具的更多信息，请见%> <%:eko.one.pl forum%>.
    -

    -

    <%:发送 USSD 代码%>

    -
    - -
    -
    <%:用户 USSD 代码%>:
    - -
    - -
    -
    -
    - -
    -
    <%:要发送的代码%>:
    -
    - -
    -
    -
    <%:回复%>:
    - -
    -
    - -
    -
    -
    -
    - -
    - - - -<%+footer%> diff --git a/package/wwan/luci-app-sms-tool/po/pl/sms-tool.po b/package/wwan/luci-app-sms-tool/po/pl/sms-tool.po deleted file mode 100644 index 2ef0778b5..000000000 --- a/package/wwan/luci-app-sms-tool/po/pl/sms-tool.po +++ /dev/null @@ -1,288 +0,0 @@ -msgid "" -msgstr "Content-Type: text/plain; charset=UTF-8" - -"Language: pl\n" -"Last-Translator: Rafał Wabik (IceG) - From eko.one.pl forum\n" - -msgid "SMS Messages" -msgstr "Wiadomości SMS" - -msgid "Received Messages" -msgstr "Odebrane wiadomości" - -msgid "Send Messages" -msgstr "Wysyłanie wiadomości" - -msgid "USSD" -msgstr "USSD" - -msgid "From" -msgstr "Nadawca" - -msgid "Received" -msgstr "Odebrano" - -msgid "Message" -msgstr "Wiadomość" - -msgid "Configuration" -msgstr "Ustawienia" - -msgid "Sample codes" -msgstr "Przykładowe kody" - -msgid "Sending USSD codes" -msgstr "Wysyłanie kodów USSD" - -msgid "Please enter phone number" -msgstr "Proszę podać numer telefonu" - -msgid "Please correct phone number" -msgstr "Proszę poprawić numer telefonu" - -msgid "Please enter a message text" -msgstr "Proszę podać treść wiadomości" - -msgid "Please select the message(s) to be deleted" -msgstr "Proszę wybrać wiadomość(-ci) do usunięcia" - -msgid "Reply" -msgstr "Odpowiedź" - -msgid "SMS sent sucessfully" -msgstr "SMS został wysłany" - -msgid "Please enter a USSD code" -msgstr "Proszę podać kod do wysłania" - -msgid "Delete selected message(s)?" -msgstr "Usunąć wybraną(-e) wiadomość(-ci)?" - -msgid "Delete all the messages?" -msgstr "Usunąć wszystkie wiadomości?" - -msgid "Configuration sms-tool" -msgstr "Konfiguracja sms-tool" - -msgid "Configuration panel for sms_tool and gui application." -msgstr "Panel ustawień dla aplikacji sms_tool oraz dla interfejsu użytkownika." - -msgid "Device" -msgstr "Urządzenie" - -msgid "Web UI for handling messages via sms_tool." -msgstr "Interfejs użytkownika dla sms_tool do obsługi wiadomości SMS." - -msgid "Web UI for handling USSD codes via sms_tool." -msgstr "Interfejs użytkownika dla sms_tool do obsługi kodów USSD." - -msgid "SIM card" -msgstr "Karta SIM" - -msgid "Modem memory" -msgstr "Pamięć modemu" - -msgid "Messages store in" -msgstr "Miejsce przechowywania wiadomości" - -msgid "Messages (Inbox / Maximum)" -msgstr "Wiadomości (Odebrane / Maksymalnie)" - -msgid "Delete Selected" -msgstr "Usuń wybraną" - -msgid "Delete message(s)" -msgstr "Usuń wiadomość(-ci)" - -msgid "Delete All" -msgstr "Usuń wszystkie" - -msgid "USSD Codes" -msgstr "Kody USSD" - -msgid "Send to" -msgstr "Wyślij do" - -msgid "Message text" -msgstr "Treść wiadomości" - -msgid "Send Message" -msgstr "Wyślij SMS" - -msgid "Code to send" -msgstr "Kod do wysłania" - -msgid "Send Code" -msgstr "Wyślij kod" - -msgid "SMS Settings" -msgstr "Ustawienia dla wiadomości SMS" - -msgid "USSD Codes Settings" -msgstr "Ustawienia dla kodów USSD" - -msgid "SMS Reading Port" -msgstr "Port do odczytu SMS" - -msgid "SMS Sending Port" -msgstr "Port do wysyłania SMS" - -msgid "USSD Sending Port" -msgstr "Port do wysyłania kodów USSD" - -msgid "Add Prefix to Phone Number" -msgstr "Dodaj prefiks do numeru telefonu" - -msgid "Automatically add prefix to the phone number field." -msgstr "Automatycznie uzupełnij pole numeru telefonu o prefiks." - -msgid "Prefix Number" -msgstr "Numer prefiks" - -msgid "PHONE_NUMBER" -msgstr "48NumerTelefonu" - -msgid "Refresh SMS" -msgstr "Odśwież" - -msgid "Sending USSD Code in plain text" -msgstr "Wysyłaj kod USSD jawnym tekstem" - -msgid "Receive message without PDU decoding" -msgstr "Odbierz wiadomość bez dekodowania jej jako PDU" - -msgid "Send the USSD code in plain text. Command is not being coded to the PDU." -msgstr "Wysyła kod USSD jawnym tekstem. Polecenie nie jest dekodowane na PDU." - -msgid "Receive and display the message without decoding it as a PDU." -msgstr "Odebrana wiadomość wyświetlana jest bez dekodowania jej jako PDU." - -msgid "Explanation of number and prefix" -msgstr "Wyjaśnienie dot. numeru i prefiksu" - -msgid "In the tab for sending SMSes, show an explanation of the prefix and the correct phone number." -msgstr "W zakładce umożliwiającej wysyłanie SMS-ów pokaż wyjaśnienie dotyczące prefiksu i poprawnego numeru telefonu." - -msgid "The phone number should be preceded by the country prefix (for Poland it is 48, without '+'). If the number is 5, 4 or 3 characters, it is treated as 'short' and should not be preceded by a country prefix." -msgstr "Numer telefonu należy poprzedzić prefiksem kraju (dla Polski jest to 48, bez znaku '+'). Jeżeli numer jest 5, 4 lub 3 znakowy to jest on traktowany jako 'krótki' i nie należy go poprzedzać prefiksem kraju." - -msgid "The phone number should be preceded by the country prefix (for Poland it is 48, without +). If the number is 5, 4 or 3 characters, it is treated as.. short and should not be preceded by a country prefix." -msgstr "Numer telefonu należy poprzedzić prefiksem kraju (dla Polski jest to 48, bez znaku +). Jeżeli numer jest 5, 4 lub 3 znakowy to jest on traktowany jako krótki i nie należy go poprzedzać prefiksem kraju." - -msgid "Each line must have the following format: 'Contact name;Phone number'. Save to file '/etc/config/phonebook.user'." -msgstr "Każda linijka powinna mieć następujący format: 'Nazwa kontaktu;Numer telefonu'. Dla wygody kontakty użytkownika zapisywane są w pliku '/etc/config/phonebook.user'." - -msgid "User Phonebook" -msgstr "Kontakty użytkownika" - -msgid "User USSD Codes" -msgstr "Kody USSD użytkownika" - -msgid "Each line must have the following format: 'Code name;Code'. Save to file '/etc/config/ussd.user'." -msgstr "Każda linijka powinna mieć następujący format: 'Etykieta kodu;Kod'. Dla wygody kody użytkownika zapisywane są w pliku '/etc/config/ussd.user'." - -msgid "Notification Settings" -msgstr "Ustawienia powiadomień" - -msgid "The LED informs about a new message. Before activating this function, please config and save the SMS reading port, time to check SMS inbox and select the notification LED." -msgstr "Powiadomienie diodą o nowej wiadomości. Przed uruchomieniem tej funkcji proszę ustawić port odczytu wiadomości, czas sprawdzania skrzynki odbiorczej oraz wybrać diodę powiadomień." - -msgid "Check inbox every minute(s)" -msgstr "Sprawdzaj skrzynkę odbiorczą co minut(-y)" - -msgid "Specify how many minutes you want your inbox to be checked." -msgstr "Podaj co ile minut ma być sprawdzana skrzynka odbiorcza w poszukiwaniu nowych wiadomości." - -msgid "Notification LED" -msgstr "Dioda powiadomień" - -msgid "Select the notification LED." -msgstr "Wybierz diodę powiadomień." - -msgid "Notify new messages" -msgstr "Powiadomienie o nowych wiadomościach" - -msgid "Turn on the LED for seconds(s)" -msgstr "Włącz diodę na sekund(-y)" - -msgid "Turn off the LED for seconds(s)" -msgstr "Wyłącz diodę na sekund(-y)" - -msgid "Specify for how long the LED should be on." -msgstr "Podaj przez jaki czas dioda ma być włączona." - -msgid "Specify for how long the LED should be off." -msgstr "Podaj przez jaki czas dioda ma być wyłączona." - -msgid "Merge split messages" -msgstr "Połącz podzielone wiadomości" - -msgid "Checking this option will make it easier to read the messages, but it will cause a discrepancy in the number of messages shown and received." -msgstr "Podzielone wiadomości zostaną złączone. Zaznaczenie tej opcji ułatwi czytanie SMS-ów, ale spowoduje niezgodność w ilości pokazanych, odebranych wiadomości." - -msgid "Message storage area" -msgstr "Miejsce przechowywania wiadomości" - -msgid "Messages are stored in a specific location (for example, on the SIM card or modem memory), but other areas may also be available depending on the type of device." -msgstr "Wiadomości przechowywane są w określonym miejscu (np. na karcie SIM lub pamięci modemu), ale w zależności od typu urządzenia mogą być dostępne także inne obszary." - -msgid "AT Commands" -msgstr "Polecenia AT" - -msgid "Web UI for handling AT commands via sms_tool." -msgstr "Interfejs użytkownika dla sms_tool do obsługi poleceń AT." - -msgid "Sending commands to modem" -msgstr "Wysyłanie poleceń do modemu" - -msgid "User AT Commands" -msgstr "Polecenia AT użytkownika" - -msgid "Command to send" -msgstr "Polecenie do wysłania" - -msgid "Please enter a AT Command" -msgstr "Proszę podać polecenie AT do wysłania" - -msgid "AT Commands Sending Port" -msgstr "Port do wysyłania poleceń AT" - -msgid "Send Command" -msgstr "Wyślij polecenie" - -msgid "AT Commands Settings" -msgstr "Ustawienia dla poleceń AT" - -msgid "Each line must have the following format: 'AT Command name;AT Command'. Save to file '/etc/config/atcmds.user'." -msgstr "Każda linijka powinna mieć następujący format: 'Etykieta polecenia;polecenie AT'. Dla wygody polecenia użytkownika zapisywane są w pliku '/etc/config/atcmds.user'." - -msgid "Restart the inbox checking process every" -msgstr "Uruchom proces ponownie po" - -msgid "The process will restart at the selected time interval. This will eliminate the delay in checking your inbox." -msgstr "Proces zostanie uruchomiony ponownie po wybranym przez użytkownika czasie. Pozwoli to wyeliminować opóźnienie w sprawdzaniu skrzynki odbiorczej." - -msgid "4h" -msgstr "4 godz." - -msgid "6h" -msgstr "6 godz." - -msgid "8h" -msgstr "8 godz." - -msgid "12h" -msgstr "12 godz." - -msgid "The diode is dedicated only to these notifications" -msgstr "Dioda jest dedykowana tylko tym powiadomieniom" - -msgid "Select 'No' in case the router has only one LED or if the LED is multi-tasking." -msgstr "Wybierz 'Nie' w przypadku, kiedy router ma tylko jedną diodę lub gdy dioda obsługuje wiele zadań." - -msgid "No" -msgstr "Nie" - -msgid "Yes" -msgstr "Tak" - diff --git a/package/wwan/luci-app-sms-tool/po/zh-cn/sms-tool.po b/package/wwan/luci-app-sms-tool/po/zh-cn/sms-tool.po deleted file mode 100644 index 4417c9cbe..000000000 --- a/package/wwan/luci-app-sms-tool/po/zh-cn/sms-tool.po +++ /dev/null @@ -1,246 +0,0 @@ -msgid "Modem" -msgstr "调制解调器" - -msgid "SMS Messages" -msgstr "SMS 信息" - -msgid "Received Messages" -msgstr "接收信息" - -msgid "Send Messages" -msgstr "发送信息" - -msgid "From" -msgstr "发件人" - -msgid "Received" -msgstr "接收时间" - -msgid "Message" -msgstr "信息" - -msgid "Configuration" -msgstr "参数配置" - -msgid "Sample codes" -msgstr "代码样本" - -msgid "Please enter phone number" -msgstr "请输入手机号" - -msgid "Please correct phone number" -msgstr "请更正手机号" - -msgid "Please enter a message text" -msgstr "请输入信息内容" - -msgid "Please select the message(s) to be deleted" -msgstr "请选择要删除的信息" - -msgid "Reply" -msgstr "回复" - -msgid "SMS sent sucessfully" -msgstr "信息发送成功" - -msgid "Delete selected message(s)?" -msgstr "删除选择的信息?" - -msgid "Delete all the messages?" -msgstr "删除所有信息?" - -msgid "Configuration sms-tool" -msgstr "配置 sms-tool" - -msgid "Configuration panel for sms_tool and gui application." -msgstr "sms_tool 和 gui 应用程序的配置面板." - -msgid "Device" -msgstr "设备" - -msgid "Web UI for handling messages via sms_tool." -msgstr "用于通过 sms_tool 处理信息的 Web UI." - -msgid "Web UI for sending messages via sms_tool." -msgstr "用于通过 sms_tool 发送信息的 Web UI." - -msgid "Web UI for receiveling messages via sms_tool." -msgstr "用于通过 sms_tool 接收信息的 Web UI." - -msgid "SIM card" -msgstr "SIM卡" - -msgid "Modem memory" -msgstr "Modem内存" - -msgid "Messages store in" -msgstr "信息存储在" - -msgid "Messages (Inbox / Maximum)" -msgstr "信息（收件箱/最大）" - -msgid "Delete Selected" -msgstr "删除所选" - -msgid "Delete message(s)" -msgstr "删除信息" - -msgid "Delete All" -msgstr "删除所有" - -msgid "Send to" -msgstr "发送到" - -msgid "Message text" -msgstr "信息文本" - -msgid "Send Message" -msgstr "发送信息" - -msgid "Code to send" -msgstr "代码发送" - -msgid "Send Code" -msgstr "发送代码" - -msgid "SMS Settings" -msgstr "SMS 设置" - -msgid "SMS Reading Port" -msgstr "SMS 读取端口" - -msgid "SMS Sending Port" -msgstr "SMS 发送端口" - -msgid "Add Prefix to Phone Number" -msgstr "为手机号码添加前缀" - -msgid "Automatically add prefix to the phone number field." -msgstr "自动为手机号码字段添加前缀." - -msgid "Prefix Number" -msgstr "前缀编号" - -msgid "PHONE_NUMBER" -msgstr "手机号码" - -msgid "Refresh SMS" -msgstr "刷新信息" - -msgid "Explanation of number and prefix" -msgstr "数字和前缀的解释" - -msgid "In the tab for sending SMSes, show an explanation of the prefix and the correct phone number." -msgstr "在发送短信的选项卡中，显示前缀说明和正确的电话号码." - -msgid "The phone number should be preceded by the country prefix (for Poland it is 48, without '+'). If the number is 5, 4 or 3 characters, it is treated as 'short' and should not be preceded by a country prefix." -msgstr "电话号码前面应有国家/地区前缀（中国为 86，不带“+”）, 号码是 5、4 或 3 个字符的短号除外." - -msgid "The phone number should be preceded by the country prefix (for Poland it is 48, without +). If the number is 5, 4 or 3 characters, it is treated as.. short and should not be preceded by a country prefix." -msgstr "电话号码前面应有国家/地区前缀（中国为 86，不带“+”）, 号码是 5、4 或 3 个字符的短号除外." - -msgid "Each line must have the following format: 'Contact name;Phone number'. Save to file '/etc/config/phonebook.user'." -msgstr "每行必须具有以下格式：“联系人姓名；电话号码”。 保存到文件“/etc/config/phonebook.user”." - -msgid "User Phonebook" -msgstr "电话簿" - -msgid "Notification Settings" -msgstr "通知设置" - -msgid "The LED informs about a new message. Before activating this function, please config and save the SMS reading port, time to check SMS inbox and select the notification LED." -msgstr "LED 新消息通知。 激活此功能前，请配置并保存短信阅读端口，及时查看短信收件箱并选择通知LED." - -msgid "Check inbox every minute(s)" -msgstr "每分钟检查收件箱" - -msgid "Specify how many minutes you want your inbox to be checked." -msgstr "指定要检查收件箱的分钟数." - -msgid "Notification LED" -msgstr "通知LED" - -msgid "Select the notification LED." -msgstr "选择通知LED." - -msgid "Notify new messages" -msgstr "通知新消息" - -msgid "Turn on the LED for seconds(s)" -msgstr "打开LED秒数" - -msgid "Turn off the LED for seconds(s)" -msgstr "关闭LED秒数" - -msgid "Specify for how long the LED should be on." -msgstr "指定 LED 应亮多长时间." - -msgid "Specify for how long the LED should be off." -msgstr "指定 LED 应关闭多长时间." - -msgid "Merge split messages" -msgstr "合并分割的消息" - -msgid "Checking this option will make it easier to read the messages, but it will cause a discrepancy in the number of messages shown and received." -msgstr "选中此选项将使阅读消息更容易，但会导致显示和接收的消息数量出现差异." - -msgid "Message storage area" -msgstr "消息存储区" - -msgid "Messages are stored in a specific location (for example, on the SIM card or modem memory), but other areas may also be available depending on the type of device." -msgstr "消息存储在特定位置（例如，SIM 卡或调制解调器内存中），但其他区域也可能可用，具体取决于设备类型." - -msgid "AT Commands" -msgstr "AT 命令" - -msgid "Web UI for handling AT commands via sms_tool." -msgstr "用于通过 sms_tool 处理 AT 命令的 Web UI." - -msgid "Sending commands to modem" -msgstr "向调制解调器发送命令" - -msgid "User AT Commands" -msgstr "用户 AT 命令" - -msgid "Command to send" -msgstr "命令发送" - -msgid "Please enter a AT Command" -msgstr "请输入 AT 命令" - -msgid "AT Commands Sending Port" -msgstr "AT命令发送端口" - -msgid "Send Command" -msgstr "发送命令" - -msgid "AT Commands Settings" -msgstr "AT命令设置" - -msgid "Each line must have the following format: 'AT Command name;AT Command'. Save to file '/etc/config/atcmds.user'." -msgstr "每行必须具有以下格式：'AT Command name;AT Command'。 保存到文件“/etc/config/atcmds.user”." - -msgid "Restart the inbox checking process every" -msgstr "每次重新启动收件箱检查过程" - -msgid "The process will restart at the selected time interval. This will eliminate the delay in checking your inbox." -msgstr "该过程将在选定的时间间隔重新开始。 这将消除检查收件箱的延迟." - -msgid "4h" -msgstr "4小时." - -msgid "6h" -msgstr "6小时." - -msgid "8h" -msgstr "8小时." - -msgid "12h" -msgstr "12小时." - -msgid "The diode is dedicated only to these notifications" -msgstr "二极管仅用于这些通知" - -msgid "Select 'No' in case the router has only one LED or if the LED is multi-tasking." -msgstr "如果路由器只有一个 LED 或者 LED 是多任务处理，请选择“否”." - diff --git a/package/wwan/luci-app-sms-tool/root/etc/config/atcmds.user b/package/wwan/luci-app-sms-tool/root/etc/config/atcmds.user deleted file mode 100644 index 44bafb90e..000000000 --- a/package/wwan/luci-app-sms-tool/root/etc/config/atcmds.user +++ /dev/null @@ -1,28 +0,0 @@ -------查询------;AT -查看IMEI;AT+CGSN -固件版本信息;AT+GMR -信号强度;AT+CSQ -正在使用的网络信息;AT+QNWINFO -查询限速;AT+C5GQOSRDP=1 -模块温度;AT+QTEMP -查询运营商名称;AT+QSPN -查询小区信息;AT+QENG="servingcell" ------3/4/5G网络配置-----;AT -查询当前网络搜索模式;AT+QNWPREFCFG="mode_pref" -!切换仅3G;AT+QNWPREFCFG="mode_pref",WCDMA -切换仅4G;AT+QNWPREFCFG="mode_pref",LTE -切换仅5G;AT+QNWPREFCFG="mode_pref",NR5G -切换5,4G;AT+QNWPREFCFG="mode_pref",NR5G:LTE -切换AUTO;AT+QNWPREFCFG="mode_pref",AUTO ------锁频段-----;AT -查询支持的所有频段;AT+QNWPREFCFG=? -查询当前配置的5G频段;AT+QNWPREFCFG="nr5g_band" -查询当前配置的4G频段;AT+QNWPREFCFG="lte_band" -!5G锁频段(78);AT+QNWPREFCFG="nr5g_band",78 -5G默认频段;AT+QNWPREFCFG="nr5g_band",1:28:41:77:78:79 -!4G锁频段(1);AT+QNWPREFCFG="lte_band",1 -4G默认频段;AT+QNWPREFCFG="lte_band",1:2:3:5:7:8:20:28:34:38:39:40:41 ------MORE-----;AT -查看产品型号;ATI -挂断现有语音;ATH -!更改IMEI,需重启;AT+EGMR=1,7,"868227050701486" \ No newline at end of file diff --git a/package/wwan/luci-app-sms-tool/root/etc/config/phonebook.user b/package/wwan/luci-app-sms-tool/root/etc/config/phonebook.user deleted file mode 100644 index 74c98ab4d..000000000 --- a/package/wwan/luci-app-sms-tool/root/etc/config/phonebook.user +++ /dev/null @@ -1 +0,0 @@ -other user;8613188888888 diff --git a/package/wwan/luci-app-sms-tool/root/etc/config/sms_tool b/package/wwan/luci-app-sms-tool/root/etc/config/sms_tool deleted file mode 100644 index 7bff8f6d2..000000000 --- a/package/wwan/luci-app-sms-tool/root/etc/config/sms_tool +++ /dev/null @@ -1,14 +0,0 @@ - -config sms_tool 'general' - option pnumber '86' - option prefix '1' - option ledtimeon '1' - option ledtimeoff '5' - option lednotify '0' - option checktime '10' - option mergesms '0' - option information '0' - option pdu '0' - option storage 'SM' - option prestart '6' - option ledtype 'D' diff --git a/package/wwan/luci-app-sms-tool/root/etc/init.d/smsled b/package/wwan/luci-app-sms-tool/root/etc/init.d/smsled deleted file mode 100755 index 2442b145e..000000000 --- a/package/wwan/luci-app-sms-tool/root/etc/init.d/smsled +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh /etc/rc.common -# Copyright 2020 Rafał Wabik (IceG) - From eko.one.pl forum -# Licensed to the GNU General Public License v3.0. - -USE_PROCD=1 -START=99 -STOP=01 - -start_service() { - procd_open_instance - procd_set_param command /bin/sh "/sbin/smsled-init.sh" - procd_close_instance -} - -stop_service() { - for KILLPID in `ps | grep 'smsled' | awk ' { print $1;}'`; do - (kill -9 $KILLPID >/dev/null 2>&1 )& - done - sleep 1 - return 0 -} - -restart_service() { - stop_service - start_service -} diff --git a/package/wwan/luci-app-sms-tool/root/etc/uci-defaults/set_sms_ports.sh b/package/wwan/luci-app-sms-tool/root/etc/uci-defaults/set_sms_ports.sh deleted file mode 100755 index fbc77d705..000000000 --- a/package/wwan/luci-app-sms-tool/root/etc/uci-defaults/set_sms_ports.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -# Copyright 2020-2021 Rafał Wabik (IceG) - From eko.one.pl forum -# Licensed to the GNU General Public License v3.0. - -work=false -for port in /dev/ttyUSB* -do - [[ -e $port ]] || continue - gcom -d $port info &> /tmp/testusb - testUSB=`cat /tmp/testusb | grep "Error\|Can't"` - if [ -z "$testUSB" ]; then - work=$port - break - fi -done -rm -rf /tmp/testusb - -if [ $work != false ]; then -uci set sms_tool.@sms_tool[0].readport=$work -uci set sms_tool.@sms_tool[0].sendport=$work -uci set sms_tool.@sms_tool[0].atport=$work -uci commit sms_tool -fi diff --git a/package/wwan/luci-app-sms-tool/root/etc/uci-defaults/start-smsled b/package/wwan/luci-app-sms-tool/root/etc/uci-defaults/start-smsled deleted file mode 100755 index 95ca388b7..000000000 --- a/package/wwan/luci-app-sms-tool/root/etc/uci-defaults/start-smsled +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh -# Copyright 2020 Rafał Wabik (IceG) - From eko.one.pl forum -# Licensed to the GNU General Public License v3.0. - -/etc/init.d/smsled disable - -exit 0 diff --git a/package/wwan/luci-app-sms-tool/root/sbin/cronsync.sh b/package/wwan/luci-app-sms-tool/root/sbin/cronsync.sh deleted file mode 100755 index 39f7899c3..000000000 --- a/package/wwan/luci-app-sms-tool/root/sbin/cronsync.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh - -[ -e /etc/crontabs/root ] || touch /etc/crontabs/root - -SLED=$(uci -q get sms_tool.general.lednotify) -if [ "x$SLED" != "x1" ]; then - if grep -q "smsled" /etc/crontabs/root; then - grep -v "/init.d/smsled" /etc/crontabs/root > /tmp/new_cron - mv /tmp/new_cron /etc/crontabs/root - /etc/init.d/cron restart - fi - exit 0 -fi - -if ! grep -q "smsled" /etc/crontabs/root; then -PTR=$(uci -q get sms_tool.general.prestart) - echo "1 */$PTR * * * /etc/init.d/smsled enable" >> /etc/crontabs/root - /etc/init.d/cron restart -fi - -exit 0 diff --git a/package/wwan/luci-app-sms-tool/root/sbin/set_sms_ports.sh b/package/wwan/luci-app-sms-tool/root/sbin/set_sms_ports.sh deleted file mode 100755 index e89eb1737..000000000 --- a/package/wwan/luci-app-sms-tool/root/sbin/set_sms_ports.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/sh -# Copyright 2020-2021 Rafał Wabik (IceG) - From eko.one.pl forum -# Licensed to the GNU General Public License v3.0. - -work=false -for port in /dev/ttyUSB* -do - [[ -e $port ]] || continue - gcom -d $port info &> /tmp/testusb - testUSB=`cat /tmp/testusb | grep "Error\|Can't"` - if [ -z "$testUSB" ]; then - work=$port - break - fi -done -rm -rf /tmp/testusb - -if [ $work != false ]; then -uci set sms_tool.@sms_tool[0].readport=$work -uci set sms_tool.@sms_tool[0].sendport=$work -uci set sms_tool.@sms_tool[0].ussdport=$work -uci set sms_tool.@sms_tool[0].atport=$work -uci commit sms_tool -fi diff --git a/package/wwan/luci-app-sms-tool/root/sbin/smsled-init.sh b/package/wwan/luci-app-sms-tool/root/sbin/smsled-init.sh deleted file mode 100755 index fa7d86304..000000000 --- a/package/wwan/luci-app-sms-tool/root/sbin/smsled-init.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh -# Copyright 2020 Rafał Wabik (IceG) - From eko.one.pl forum -# Licensed to the GNU General Public License v3.0. - -sleep 10 -CT=$(uci -q get sms_tool.general.checktime) -TX=$(echo $CT | tr -dc '0-9') -TM=$(($TX * 60)) - -while [ 1 ]; do - LED=$(uci -q get sms_tool.general.lednotify) - if [ $LED == "1" ]; then - sleep $TM - (/sbin/smsled.sh >/dev/null 2>&1 )& - continue - fi - sleep 1 -done - -exit 0 - diff --git a/package/wwan/luci-app-sms-tool/root/sbin/smsled.sh b/package/wwan/luci-app-sms-tool/root/sbin/smsled.sh deleted file mode 100755 index fffd8566c..000000000 --- a/package/wwan/luci-app-sms-tool/root/sbin/smsled.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh -# Copyright 2020-2021 Rafał Wabik (IceG) - From eko.one.pl forum -# Licensed to the GNU General Public License v3.0. - - DEV=$(uci -q get sms_tool.general.readport) - LEDX=$(uci -q get sms_tool.general.smsled) - MEM=$(uci -q get sms_tool.general.storage) - STX=$(sms_tool -s $MEM -d $DEV status | cut -c23-27) - SMS=$(echo $STX | tr -dc '0-9') - SMSC=$(cat /etc/config/sms_count) - LEDT="/sys/class/leds/$LEDX/trigger" - LEDON="/sys/class/leds/$LEDX/delay_on" - LEDOFF="/sys/class/leds/$LEDX/delay_off" - LED="/sys/class/leds/$LEDX/brightness" - - LON=$(uci -q get sms_tool.general.ledtimeon) - TXON=$(echo $LON | tr -dc '0-9') - TMON=$(($TXON * 1000)) - - LOFF=$(uci -q get sms_tool.general.ledtimeoff) - TXOFF=$(echo $LOFF | tr -dc '0-9') - TMOFF=$(($TXOFF * 1000)) - -if [ $SMS == $SMSC ]; then - - exit 0 -fi - -if [ $SMS > $SMSC ]; then - -echo timer > $LEDT -echo $TMOFF > $LEDOFF -echo $TMON > $LEDON -exit 0 - -fi - - -exit 0 diff --git a/package/wwan/luci-app-sms-tool/root/usr/share/rpcd/acl.d/luci-app-sms-tool.json b/package/wwan/luci-app-sms-tool/root/usr/share/rpcd/acl.d/luci-app-sms-tool.json deleted file mode 100644 index 3f4e02f78..000000000 --- a/package/wwan/luci-app-sms-tool/root/usr/share/rpcd/acl.d/luci-app-sms-tool.json +++ /dev/null @@ -1,24 +0,0 @@ -{ - "luci-app-sms-tool": { - "description": "Grant UCI and file access for luci-app-sms-tool", - "read": { - "file": { - "/usr/bin/sms_tool *": [ "exec" ], - }, - "uci": [ "sms_tool" ] - }, - "write": { - "file": { - "/usr/bin/sms_tool *": [ "exec" ], - - }, - "uci": [ "sms_tool" ] - } - } -} - - - - - - diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index b60b94de6..f66708125 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -9,11 +9,9 @@ SUBTARGETS:=mt7622 mt7623 mt7629 filogic FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb KERNEL_PATCHVER:=6.6 -KERNEL_TESTING_PATCHVER:=6.1 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ - kmod-leds-gpio kmod-gpio-button-hotplug \ - autocore-arm htop wpad-openssl uboot-envtools + kmod-leds-gpio kmod-gpio-button-hotplug $(eval $(call BuildTarget)) diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface index 3ac856d1c..6dfa52c29 100644 --- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface +++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface @@ -1,11 +1,33 @@ set_preinit_iface() { - ip link set eth0 up - case $(board_name) in - ubnt,unifi-6-lr) + cudy,m3000-v1|\ + cudy,tr3000-v1|\ + glinet,gl-mt3000) + ip link set eth1 up + ifname=eth1 + ;; + cudy,re3000-v1|\ + ubnt,unifi-6-lr|\ + zyxel,nwa50ax-pro) + ip link set eth0 up ifname=eth0 ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632) + ip link set lan up + ifname=lan + ;; + xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-ax3000t-ubootmod|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,mi-router-wr30u-ubootmod|\ + xiaomi,redmi-router-ax6000-stock|\ + xiaomi,redmi-router-ax6000-ubootmod) + ip link set eth0 up + ifname=lan4 + ;; *) + ip link set eth0 up ifname=lan1 ;; esac diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts index 6d77be532..b8fac373a 100644 --- a/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts @@ -1,108 +1,20 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include -#include -#include "mt7622.dtsi" -#include "mt6380.dtsi" +#include "mt7622-buffalo-wsr.dtsi" / { model = "Buffalo WSR-2533DHP2"; compatible = "buffalo,wsr-2533dhp2", "mediatek,mt7622"; aliases { - serial0 = &uart0; - led-boot = &power_green; - led-failsafe = &power_amber; - led-running = &power_green; - led-upgrade = &power_green; - }; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + label-mac-device = &gmac0; }; memory { reg = <0 0x40000000 0 0x0F000000>; }; - leds { - compatible = "gpio-leds"; - - wireless_amber { - label = "amber:wireless"; - gpios = <&pio 2 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&pio 3 GPIO_ACTIVE_LOW>; - }; - - power_green: power_green { - label = "green:power"; - gpios = <&pio 4 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - wireless_green { - label = "green:wireless"; - gpios = <&pio 15 GPIO_ACTIVE_HIGH>; - }; - - internet { - label = "green:internet"; - gpios = <&pio 19 GPIO_ACTIVE_HIGH>; - }; - - router { - label = "green:router"; - gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - /* GPIO 1 and 16 are a tri-state switch button with - * ROUTER / AP / WB. - */ - router { - label = "router"; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - bridge { - label = "wb"; - gpios = <&pio 16 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - /* GPIO 18 is a switch button with AUTO / MANUAL. */ - manual { - label = "manual"; - gpios = <&pio 18 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - }; - - wps { - label = "wps"; - gpios = <&pio 102 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - rtkgsw: rtkgsw@0 { compatible = "mediatek,rtk-gsw"; mediatek,ethsys = <ðsys>; @@ -111,41 +23,7 @@ }; }; -&cpu0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; -}; - -&cpu1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -&slot0 { - status = "okay"; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x5000>; - ieee80211-freq-limit = <5000000 6000000>; - }; -}; - &pio { - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - /* Parallel nand is shared pin with eMMC */ parallel_nand_pins: parallel-nand-pins { mux { @@ -164,75 +42,11 @@ bias-pull-up; }; }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - pwm7_pins: pwm1-2-pins { - mux { - function = "pwm"; - groups = "pwm_ch7_2"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; }; -&bch { - status = "okay"; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - - phy-connection-type = "2500base-x"; - - nvmem-cells = <&macaddr_factory_4>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; +&gmac0 { + nvmem-cells = <&macaddr_factory_4 (-1)>; + nvmem-cell-names = "mac-address"; }; &nandc { @@ -276,6 +90,18 @@ label = "factory"; reg = <0x1c0000 0x40000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; partition@200000 { @@ -304,47 +130,3 @@ }; }; }; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; - status = "okay"; -}; - -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; - -&wmac { - status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; -}; - -&rtc { - status = "disabled"; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts b/target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts new file mode 100644 index 000000000..82cc970fd --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr-3200ax4s.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "mt7622-buffalo-wsr.dtsi" + +/ { + model = "Buffalo WSR-3200AX4S"; + compatible = "buffalo,wsr-3200ax4s", "mediatek,mt7622"; + + memory { + reg = <0 0x40000000 0 0x1f000000>; + }; +}; + +&pio { + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + + conf-cmd-dat { + pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI", + "SPI_MISO", "SPI_CS"; + input-enable; + drive-strength = <16>; + bias-pull-up; + }; + + conf-clk { + pins = "SPI_CLK"; + drive-strength = <16>; + bias-pull-down; + }; + }; +}; + +&mdio { + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-connection-type = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <104000000>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; + mediatek,bmt-table-size = <0x1000>; + /* + * - Preloader - (kernel (6MiB, in firmware)) + * - Kernel2 - WTB + */ + mediatek,bmt-remap-range = <0x0 0x8c0000>, + <0x1ac0000 0x5200000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; + + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; + + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x80000>; + read-only; + }; + + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x100000>; + read-only; + }; + + partition@2c0000 { + compatible = "brcm,trx"; + brcm,trx-magic = <0x33504844>; + label = "firmware"; + reg = <0x2c0000 0x1800000>; + }; + + partition@1ac0000 { + label = "Kernel2"; + reg = <0x1ac0000 0x1800000>; + }; + + partition@32c0000 { + label = "glbcfg"; + reg = <0x32c0000 0x200000>; + read-only; + }; + + partition@34c0000 { + label = "board_data"; + reg = <0x34c0000 0x200000>; + read-only; + }; + + partition@36c0000 { + label = "WTB"; + reg = <0x36c0000 0x3600000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi b/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi new file mode 100644 index 000000000..2f0540f41 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-buffalo-wsr.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include +#include + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + aliases { + serial0 = &uart0; + led-boot = &power_green; + led-failsafe = &power_amber; + led-running = &power_green; + led-upgrade = &power_green; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + }; + + power_amber: led-1 { + gpios = <&pio 3 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_POWER; + }; + + power_green: led-2 { + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_POWER; + }; + + led-3 { + gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + }; + + led-4 { + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WAN; + }; + + led-5 { + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + }; + + keys { + compatible = "gpio-keys"; + + key-reset { + label = "reset"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + /* GPIO 1 and 16 are a tri-state switch button with + * ROUTER / AP / WB. + */ + key-router { + label = "router"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + key-bridge { + label = "wb"; + gpios = <&pio 16 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + /* GPIO 18 is a switch button with AUTO / MANUAL. */ + key-manual { + label = "manual"; + gpios = <&pio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + key-wps { + label = "wps"; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&cpu0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&cpu1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&slot0 { + status = "okay"; + + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x5000>; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-connection-type = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&bch { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&rtc { + status = "disabled"; +}; diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi new file mode 100644 index 000000000..0560bbd33 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7622.dtsi" +#include "mt6380.dtsi" +#include +#include + +/ { + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + + button-wps { + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + label = "wps"; + linux,code = ; + }; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&bch { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + phy-mode = "2500base-x"; + reg = <0>; + nvmem-cells = <&macaddr_odm 1>; + nvmem-cell-names = "mac-address"; + fixed-link { + full-duplex; + pause; + speed = <2500>; + }; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 0>; + + ports { + wan: port@4 { + reg = <4>; + label = "wan"; + nvmem-cells = <&macaddr_odm 0>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pio { + epa_elna_pins: epa-elna-pins { + mux { + function = "antsel"; + groups = "antsel0", "antsel1", "antsel2", "antsel3", + "antsel4", "antsel5", "antsel6", "antsel7", + "antsel8", "antsel9", "antsel12", "antsel13", + "antsel14", "antsel15", "antsel16", "antsel17"; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst", + "pcie1_0_waken", + "pcie1_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx"; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +&slot0 { + wmac1: mt7915@0,0 { + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5000000 6000000>; + mediatek,mtd-eeprom = <&factory 0x05000>; + nvmem-cells = <&macaddr_odm 3>; + nvmem-cell-names = "mac-address"; + }; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + snand: flash@0 { + compatible = "spi-nand"; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-v2; + nand-ecc-engine = <&snfi>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x00080000 0x00040000>; + read-only; + }; + + partition@C0000 { + label = "Bootloader"; + reg = <0x000C0000 0x00080000>; + read-only; + }; + + partition@140000 { + label = "BootConfig"; + reg = <0x00140000 0x00040000>; + }; + + partition@180000 { + label = "Odm"; + reg = <0x00180000 0x00040000>; + read-only; + odm_partition: nvmem-layout { + compatible = "fixed-layout"; + }; + }; + + config1: partition@1C0000 { + compatible = "nvmem-cells"; + label = "Config1"; + reg = <0x001C0000 0x00080000>; + read-only; + }; + + partition@240000 { + label = "Config2"; + reg = <0x00240000 0x00080000>; + read-only; + }; + + partition@2C0000 { + label = "Kernel1"; + reg = <0x002C0000 0x02D00000>; + + compatible = "denx,fit"; + openwrt,cmdline-match = "boot_part=Kernel1"; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00800000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x00800000 0x02500000>; + }; + }; + + partition@2FC0000 { + label = "Kernel2"; + reg = <0x02FC0000 0x02D00000>; + + compatible = "denx,fit"; + openwrt,cmdline-match = "boot_part=Kernel2"; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00800000>; + }; + + partition@800000 { + label = "ubi"; + reg = <0x00800000 0x02500000>; + }; + }; + + factory: partition@5CC0000 { + label = "Factory"; + reg = <0x05CC0000 0x00100000>; + read-only; + }; + + partition@5DC0000 { + label = "Mydlink"; + reg = <0x05DC0000 0x00200000>; + read-only; + }; + + partition@5FC0000 { + label = "Storage"; + reg = <0x05FC0000 0x00300000>; + read-only; + }; + }; + }; +}; + +&ssusb { + status = "disabled"; +}; + +&u3phy { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + pinctrl-names = "default"; + pinctrl-0 = <&epa_elna_pins>; + mediatek,mtd-eeprom = <&factory 0x0000>; + nvmem-cells = <&macaddr_odm 2>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts new file mode 100644 index 000000000..2b40c5e7d --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-m32-a1.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi" +#include + +/ { + model = "D-Link EAGLE PRO AI M32 A1"; + compatible = "dlink,eagle-pro-ai-m32-a1", "mediatek,mt7622"; + + aliases { + led-boot = &led_status_orange; + led-failsafe = &led_status_red; + led-running = &led_status_white; + led-upgrade = &led_status_red; + }; + + leds { + compatible = "gpio-leds"; + + led_status_white: led-status-white { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 85 GPIO_ACTIVE_LOW>; + }; + + led_status_orange: led-status-orange { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 20 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_status_red: led-status-red { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&switch { + ports { + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + }; +}; + +&odm_partition { + macaddr_odm: macaddr@83 { + compatible = "mac-base"; + reg = <0x83 0x6>; + #nvmem-cell-cells = <1>; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts new file mode 100644 index 000000000..b21ba36cf --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-dlink-eagle-pro-ai-r32-a1.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi" +#include + +/ { + model = "D-Link EAGLE PRO AI R32 A1"; + compatible = "dlink,eagle-pro-ai-r32-a1", "mediatek,mt7622"; + + aliases { + led-boot = &led_power_orange; + led-failsafe = &led_power_orange; + led-running = &led_power_white; + led-upgrade = &led_power_orange; + }; + + leds { + compatible = "gpio-leds"; + + led_power_orange: led-power-orange { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + + led_power_white: led-power-white { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 85 GPIO_ACTIVE_LOW>; + }; + + led_internet_orange: led-internet-orange { + color = ; + function = "internet"; // LED_FUNCTION_INTERNET; + gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; + + led_internet_white: led-internet-white { + color = ; + function = "internet"; // LED_FUNCTION_INTERNET; + gpios = <&pio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&switch { + ports { + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + }; +}; + +&odm_partition { + macaddr_odm: macaddr@81 { + compatible = "mac-base"; + reg = <0x81 0x6>; + #nvmem-cell-cells = <1>; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts index 3e061ef94..7fe5d02e1 100644 --- a/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts +++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts @@ -130,7 +130,7 @@ regulator-name = "usb_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&pio 22 GPIO_ACTIVE_LOW>; + gpios = <&pio 22 GPIO_ACTIVE_LOW>; enable-active-high; }; diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts index fdbcbc18b..2bf4a33a5 100644 --- a/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts +++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts @@ -33,14 +33,12 @@ compatible = "gpio-leds"; led-0 { - label = "red:wps"; gpios = <&pio 47 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_WPS; }; led_power_red: led-1 { - label = "red:power"; gpios = <&pio 48 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_POWER; @@ -48,7 +46,6 @@ }; led_power_green: led-2 { - label = "green:power"; gpios = <&pio 49 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_POWER; @@ -56,7 +53,6 @@ }; led-3 { - label = "blue:power"; gpios = <&pio 50 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_POWER; @@ -64,7 +60,6 @@ }; led-4 { - label = "white:wlan2g"; gpios = <&pio 85 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_WLAN; @@ -73,7 +68,6 @@ }; led-5 { - label = "white:wlan5g"; gpios = <&pio 89 GPIO_ACTIVE_HIGH>; color = ; function = LED_FUNCTION_WLAN; @@ -215,9 +209,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <31>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; @@ -258,7 +252,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -327,20 +320,24 @@ reg = <0x1c0000 0x100000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; - }; + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; - macaddr_factory_7fff4: macaddr@7fff4 { - reg = <0x7fff4 0x6>; - }; + macaddr_factory_7fff4: macaddr@7fff4 { + reg = <0x7fff4 0x6>; + }; - macaddr_factory_7fffa: macaddr@7fffa { - reg = <0x7fffa 0x6>; + macaddr_factory_7fffa: macaddr@7fffa { + reg = <0x7fffa 0x6>; + }; }; }; @@ -395,9 +392,8 @@ reg = <0x0000 0 0 0 0>; mediatek,mtd-eeprom = <&factory 0x5000>; ieee80211-freq-limit = <5000000 6000000>; - nvmem-cells = <&macaddr_factory_4>; + nvmem-cells = <&macaddr_factory_4 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; }; diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts b/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts index 9df736eb0..88538c8b0 100644 --- a/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts +++ b/target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts @@ -10,6 +10,11 @@ aliases { label-mac-device = &wan; }; + + chosen { + rootdisk = <&ubi_rootfs>; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 ubi.block=0,fit root=/dev/fit0 rootwait"; + }; }; &snand { @@ -25,31 +30,70 @@ }; partition@80000 { - label = "fip"; - reg = <0x80000 0x140000>; - read-only; - }; - - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x100000>; - read-only; - }; - - partition@300000 { label = "ubi"; - reg = <0x300000 0x7d00000>; + reg = <0x80000 0x7f80000>; + compatible = "linux,ubi"; + + volumes { + ubi-volume-ubootenv { + volname = "ubootenv"; + nvmem-layout { + compatible = "u-boot,env-redundant-bool-layout"; + }; + }; + + ubi-volume-ubootenv2 { + volname = "ubootenv2"; + nvmem-layout { + compatible = "u-boot,env-redundant-bool-layout"; + }; + }; + + ubi_rootfs: ubi-volume-fit { + volname = "fit"; + }; + + ubi_factory: ubi-volume-factory { + volname = "factory"; + }; + }; + }; + }; +}; + +&ubi_factory { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x4da8>; /* actual length 0x400 */ + }; + + eeprom_factory_5000: eeprom@5000 { + reg = <0x5000 0xe00>; + }; + + macaddr_factory_7fff4: macaddr@7fff4 { + reg = <0x7fff4 0x6>; + }; + + macaddr_factory_7fffa: macaddr@7fffa { + reg = <0x7fffa 0x6>; }; }; }; &wmac { - mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; status = "okay"; }; &wmac1 { - mediatek,mtd-eeprom = <&factory 0x5000>; + nvmem-cells = <&eeprom_factory_5000>; + nvmem-cell-names = "eeprom"; }; &gmac0 { @@ -61,17 +105,3 @@ nvmem-cells = <&macaddr_factory_7fffa>; nvmem-cell-names = "mac-address"; }; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_7fff4: macaddr@7fff4 { - reg = <0x7fff4 0x6>; - }; - - macaddr_factory_7fffa: macaddr@7fffa { - reg = <0x7fffa 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450.dts b/target/linux/mediatek/dts/mt7622-linksys-e8450.dts index 8552dbf1a..dedcc057f 100644 --- a/target/linux/mediatek/dts/mt7622-linksys-e8450.dts +++ b/target/linux/mediatek/dts/mt7622-linksys-e8450.dts @@ -45,6 +45,20 @@ factory: partition@1c0000 { label = "factory"; reg = <0x1c0000 0x0100000>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_7fff4: macaddr@7fff4 { + reg = <0x7fff4 0x6>; + }; + + macaddr_factory_7fffa: macaddr@7fffa { + reg = <0x7fffa 0x6>; + }; + }; }; partition@300000 { @@ -106,17 +120,3 @@ nvmem-cells = <&macaddr_factory_7fffa>; nvmem-cell-names = "mac-address"; }; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_7fff4: macaddr@7fff4 { - reg = <0x7fff4 0x6>; - }; - - macaddr_factory_7fffa: macaddr@7fffa { - reg = <0x7fffa 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi b/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi index 1fe839575..48b25f7a4 100644 --- a/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi +++ b/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi @@ -1,8 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0-only OR MIT) /dts-v1/; -#include #include +#include +#include #include "mt7622.dtsi" #include "mt6380.dtsi" @@ -110,10 +111,6 @@ }; }; -&btif { - status = "okay"; -}; - &cir { pinctrl-names = "default"; pinctrl-0 = <&irrx_pins>; @@ -141,9 +138,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <31>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; @@ -181,7 +178,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -276,6 +272,11 @@ function = "flash"; groups = "snfi"; }; + + conf { + groups = "snfi"; + drive-strength = ; + }; }; spic0_pins: spic0-pins { diff --git a/target/linux/mediatek/dts/mt7622-netgear-wax206.dts b/target/linux/mediatek/dts/mt7622-netgear-wax206.dts index 5dd386bcd..524a49874 100644 --- a/target/linux/mediatek/dts/mt7622-netgear-wax206.dts +++ b/target/linux/mediatek/dts/mt7622-netgear-wax206.dts @@ -114,10 +114,6 @@ status = "okay"; }; -&btif { - status = "okay"; -}; - &cir { pinctrl-names = "default"; pinctrl-0 = <&irrx_pins>; @@ -147,13 +143,13 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; + reg = <31>; #interrupt-cells = <1>; interrupt-controller; interrupt-parent = <&pio>; interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reg = <0>; reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; ports { @@ -191,7 +187,6 @@ port@6 { ethernet = <&gmac0>; - label = "cpu"; phy-mode = "2500base-x"; reg = <6>; @@ -406,19 +401,22 @@ }; factory: partition@1c0000 { - compatible = "nvmem-cells"; label = "Factory"; reg = <0x1c0000 0x0100000>; - #address-cells = <1>; - #size-cells = <1>; read-only; - macaddr_factory_7fff4: macaddr@7fff4 { - reg = <0x7fff4 0x6>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_factory_7fffa: macaddr@7fffa { - reg = <0x7fffa 0x6>; + macaddr_factory_7fff4: macaddr@7fff4 { + reg = <0x7fff4 0x6>; + }; + + macaddr_factory_7fffa: macaddr@7fffa { + reg = <0x7fffa 0x6>; + }; }; }; diff --git a/target/linux/mediatek/dts/mt7622-reyee-ax3200-e5.dts b/target/linux/mediatek/dts/mt7622-reyee-ax3200-e5.dts new file mode 100644 index 000000000..d86ea52fc --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-reyee-ax3200-e5.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7622-ruijie-rg-ew3200.dtsi" + +/ { + model = "reyee AX3200 E5"; + compatible = "reyee,ax3200-e5", "mediatek,mt7622"; +}; + +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_nor_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "ATF"; + reg = <0x20000 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot"; + reg = <0x30000 0x80000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x80000 0x90000>; + }; + + factory: partition@90000 { + label = "Factory"; + reg = <0x90000 0xd0000>; + read-only; + }; + + partition@d0000 { + label = "product_info"; + reg = <0xd0000 0xe0000>; + read-only; + }; + + partition@e0000 { + label = "kdump"; + reg = <0xe0000 0xf0000>; + read-only; + }; + + partition@f0000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0xf0000 0x1000000>; + }; + }; + }; +}; + +&wmac { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&epa_elna_pins>; + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&slot0 { + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x5000>; + ieee80211-freq-limit = <5000000 6000000>; + mediatek,disable-radar-background; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts index 0f6d9bbc5..721695227 100644 --- a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts +++ b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts @@ -44,12 +44,12 @@ partition@200000 { label = "kernel"; - reg = <0x2c0000 0x400000>; + reg = <0x2c0000 0x600000>; }; partition@6c0000 { label = "ubi"; - reg = <0x6c0000 0x6f00000>; + reg = <0x8c0000 0x6f00000>; }; /delete-node/ partition@2200000; diff --git a/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200.dtsi b/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200.dtsi new file mode 100644 index 000000000..24ed92788 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200.dtsi @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + aliases { + ethernet0 = &gmac0; + label-mac-device = &gmac0; + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n1"; + bootargs = "console=ttyS0,115200n1 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + mesh_green { + label = "green:mesh"; + gpios = <&pio 79 GPIO_ACTIVE_LOW>; + }; + + mesh_red { + label = "red:mesh"; + gpios = <&pio 82 GPIO_ACTIVE_LOW>; + }; + + led_system: system_blue { + label = "blue:system"; + gpios = <&pio 81 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +ð { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-connection-type = "2500base-x"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + wan: port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; +}; + +&pio { + epa_elna_pins: epa-elna-pins { + mux { + function = "antsel"; + groups = "antsel0", "antsel1", "antsel2", "antsel3", + "antsel4", "antsel5", "antsel6", "antsel7", + "antsel8", "antsel9", "antsel12", "antsel13", + "antsel14", "antsel15", "antsel16", "antsel17"; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_0_waken", + "pcie0_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + spi_nor_pins: spi-nor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx"; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwrap { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; +}; + +&rtc { + status = "disabled"; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&watchdog { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; +}; diff --git a/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts b/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts index fba9a1b8f..857f94ae9 100644 --- a/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts +++ b/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts @@ -1,239 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include -#include - -#include "mt7622.dtsi" -#include "mt6380.dtsi" +#include "mt7622-ruijie-rg-ew3200.dtsi" / { model = "Ruijie RG-EW3200GX PRO"; compatible = "ruijie,rg-ew3200gx-pro", "mediatek,mt7622"; - - aliases { - ethernet0 = &gmac0; - label-mac-device = &gmac0; - led-boot = &led_system; - led-failsafe = &led_system; - led-running = &led_system; - led-upgrade = &led_system; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n1"; - bootargs = "console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - - cpu@1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - mesh_green { - label = "green:mesh"; - gpios = <&pio 79 GPIO_ACTIVE_LOW>; - }; - - mesh_red { - label = "red:mesh"; - gpios = <&pio 82 GPIO_ACTIVE_LOW>; - }; - - led_system: system_blue { - label = "blue:system"; - gpios = <&pio 81 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-connection-type = "2500base-x"; - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; - reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&pio>; - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - wan: port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; -}; - -&slot0 { - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x5000>; - ieee80211-freq-limit = <5000000 6000000>; - mediatek,disable-radar-background; - }; -}; - -&pio { - epa_elna_pins: epa-elna-pins { - mux { - function = "antsel"; - groups = "antsel0", "antsel1", "antsel2", "antsel3", - "antsel4", "antsel5", "antsel6", "antsel7", - "antsel8", "antsel9", "antsel12", "antsel13", - "antsel14", "antsel15", "antsel16", "antsel17"; - }; - }; - - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_0_waken", - "pcie0_0_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - spi_nor_pins: spi-nor-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx"; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&pwrap { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; }; &nor_flash { @@ -302,24 +74,6 @@ }; }; -&rtc { - status = "disabled"; -}; - -&uart0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&watchdog { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; -}; - &wmac { status = "okay"; @@ -327,3 +81,13 @@ pinctrl-0 = <&epa_elna_pins>; mediatek,mtd-eeprom = <&factory 0x0>; }; + +&slot0 { + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x5000>; + ieee80211-freq-limit = <5000000 6000000>; + mediatek,disable-radar-background; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts index b634e2878..5ec07128b 100644 --- a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts +++ b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include #include "mt7622.dtsi" @@ -57,7 +58,8 @@ compatible = "gpio-leds"; led_status: status_red { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 81 GPIO_ACTIVE_LOW>; default-state = "on"; }; @@ -284,6 +286,20 @@ label = "factory"; reg = <0x1c0000 0x40000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_24: macaddr@24 { + reg = <0x24 0x6>; + }; + + macaddr_factory_2a: macaddr@2a { + reg = <0x2a 0x6>; + }; + }; }; partition@200000 { @@ -305,20 +321,6 @@ }; }; -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_24: macaddr@24 { - reg = <0x24 0x6>; - }; - - macaddr_factory_2a: macaddr@2a { - reg = <0x2a 0x6>; - }; -}; - &ssusb { vusb33-supply = <®_3p3v>; vbus-supply = <®_5v>; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts index 5b1fd1d9b..6e310d40b 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts @@ -5,6 +5,11 @@ / { model = "Ubiquiti UniFi 6 LR v1 (U-Boot mod)"; compatible = "ubnt,unifi-6-lr-v1-ubootmod", "mediatek,mt7622"; + + chosen { + rootdisk = <&rootdisk>; + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0 rootwait"; + }; }; &nor_partitions { @@ -33,6 +38,20 @@ label = "eeprom"; reg = <0x110000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; partition@120000 { @@ -40,7 +59,7 @@ reg = <0x120000 0xee0000>; }; - partition@1000000 { + rootdisk: partition@1000000 { compatible = "denx,fit"; label = "firmware"; reg = <0x1000000 0x3000000>; @@ -68,17 +87,3 @@ nvmem-cells = <&macaddr_eeprom_0>; nvmem-cell-names = "mac-address"; }; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts index 95f19af4c..7e07e1ba6 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts @@ -38,6 +38,20 @@ label = "eeprom"; reg = <0x110000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; partition@120000 { @@ -84,17 +98,3 @@ nvmem-cells = <&macaddr_eeprom_0>; nvmem-cell-names = "mac-address"; }; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi index b3299a988..91719865d 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi @@ -1,5 +1,30 @@ #include "mt7622-ubnt-unifi-6-lr.dtsi" +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + phy-connection-type = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts index 6a7b6868c..501e09a69 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts @@ -5,6 +5,11 @@ / { model = "Ubiquiti UniFi 6 LR v2 (U-Boot mod)"; compatible = "ubnt,unifi-6-lr-v2-ubootmod", "mediatek,mt7622"; + + chosen { + rootdisk = <&rootdisk>; + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0 rootwait"; + }; }; &nor_partitions { @@ -33,6 +38,20 @@ label = "eeprom"; reg = <0x110000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; partition@120000 { @@ -40,7 +59,7 @@ reg = <0x120000 0xee0000>; }; - partition@1000000 { + rootdisk: partition@1000000 { compatible = "denx,fit"; label = "firmware"; reg = <0x1000000 0x3000000>; @@ -68,17 +87,3 @@ nvmem-cells = <&macaddr_eeprom_0>; nvmem-cell-names = "mac-address"; }; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts index f40e8e632..9fef3d672 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts @@ -38,6 +38,20 @@ label = "eeprom"; reg = <0x110000 0x10000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; }; partition@120000 { @@ -84,17 +98,3 @@ nvmem-cells = <&macaddr_eeprom_0>; nvmem-cell-names = "mac-address"; }; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi index 4d278805d..ab3c59292 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi @@ -22,3 +22,29 @@ }; }; }; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + phy-connection-type = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts new file mode 100644 index 000000000..8c90c734d --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3-ubootmod.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7622-ubnt-unifi-6-lr-v3.dtsi" + +/ { + model = "Ubiquiti UniFi 6 LR v3 (U-Boot mod)"; + compatible = "ubnt,unifi-6-lr-v3-ubootmod", "mediatek,mt7622"; + + chosen { + rootdisk = <&rootdisk>; + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8 root=/dev/fit0 rootwait"; + }; +}; + +&nor_partitions { + partition@0 { + label = "bl2"; + reg = <0x0 0x20000>; + }; + + partition@20000 { + label = "fip"; + reg = <0x20000 0xa0000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + factory: partition@d0000 { + label = "factory"; + reg = <0xd0000 0x40000>; + read-only; + }; + + eeprom: partition@110000 { + label = "eeprom"; + reg = <0x110000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; + }; + + partition@120000 { + label = "recovery"; + reg = <0x120000 0xee0000>; + }; + + rootdisk: partition@1000000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x1000000 0x3000000>; + }; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&slot0 { + wifi@0,0 { + reg = <0x0 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x20000>; + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts new file mode 100644 index 000000000..71ee9f0ce --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7622-ubnt-unifi-6-lr-v3.dtsi" + +/ { + model = "Ubiquiti UniFi 6 LR v3"; + compatible = "ubnt,unifi-6-lr-v3", "mediatek,mt7622"; +}; + +&nor_partitions { + partition@0 { + label = "preloader"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "atf"; + reg = <0x40000 0x20000>; + }; + + partition@60000 { + label = "u-boot"; + reg = <0x60000 0x60000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + factory: partition@d0000 { + label = "factory"; + reg = <0xd0000 0x40000>; + read-only; + }; + + eeprom: partition@110000 { + label = "eeprom"; + reg = <0x110000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; + }; + + partition@120000 { + label = "bs"; + reg = <0x120000 0x10000>; + }; + + partition@130000 { + label = "cfg"; + reg = <0x130000 0x100000>; + read-only; + }; + + partition@230000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x230000 0x1ee0000>; + }; + + partition@2110000 { + label = "kernel1"; + reg = <0x2110000 0x1ee0000>; + }; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&slot0 { + wifi@0,0 { + reg = <0x0 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x20000>; + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi new file mode 100644 index 000000000..c581bd7d9 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v3.dtsi @@ -0,0 +1,50 @@ +#include "mt7622-ubnt-unifi-6-lr.dtsi" + +/ { + aliases { + led-boot = &led_white; + led-failsafe = &led_white; + led-running = &led_blue; + led-upgrade = &led_blue; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_white: dome_white { + label = "white:dome"; + gpios = <&pio 0x43 GPIO_ACTIVE_LOW>; + }; + + led_blue: dome_blue { + label = "blue:dome"; + gpios = <&pio 0x44 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi index 4231cc1f7..783b0c388 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi @@ -151,31 +151,6 @@ status = "disabled"; }; -ð { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - - phy-mode = "2500base-x"; - phy-handle = <&phy0>; - phy-connection-type = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@8 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x8>; - }; - }; -}; - &pwrap { pinctrl-names = "default"; pinctrl-0 = <&pmic_bus_pins>; diff --git a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts index 9661d0c7f..ebc8731bc 100644 --- a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts +++ b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include #include "mt7622.dtsi" @@ -21,7 +22,8 @@ chosen { stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + rootdisk = <&ubi_rootfs>; + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 ubi.block=0,fit root=/dev/fit0"; }; memory { @@ -32,12 +34,14 @@ compatible = "gpio-leds"; led_power_blue: power_blue { - label = "blue:power"; + function = LED_FUNCTION_POWER; + color = ; gpios = <&pio 18 GPIO_ACTIVE_LOW>; }; led_power_amber: power_amber { - label = "amber:power"; + function = LED_FUNCTION_POWER; + color = ; gpios = <&pio 17 GPIO_ACTIVE_LOW>; }; @@ -146,9 +150,8 @@ phy-connection-type = "2500base-x"; - nvmem-cells = <&macaddr_factory_4>; + nvmem-cells = <&macaddr_factory_4 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; fixed-link { speed = <2500>; @@ -161,9 +164,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <31>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; @@ -196,7 +199,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -229,7 +231,7 @@ mediatek,bmt-v2; mediatek,bmt-table-size = <0x1000>; - mediatek,bmt-remap-range = <0x0 0x6c0000>; + mediatek,bmt-remap-range = <0x0 0x340000>; partitions { compatible = "fixed-partitions"; @@ -269,12 +271,16 @@ reg = <0x1c0000 0x80000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -290,12 +296,9 @@ read-only; }; - /* Shrunk and renamed from "firmware" - * as to not break luci size checks - */ partition@2c0000 { - label = "kernel"; - reg = <0x2c0000 0x400000>; + label = "ubi-loader"; + reg = <0x2c0000 0x80000>; }; /* ubi partition is the result of squashing @@ -305,9 +308,16 @@ * - overlay * - obr */ - partition@6c0000 { + partition@340000 { label = "ubi"; - reg = <0x6C0000 0x6f00000>; + reg = <0x340000 0x7280000>; + compatible = "linux,ubi"; + + volumes { + ubi_rootfs: ubi-volume-fit { + volname = "fit"; + }; + }; }; }; }; diff --git a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts index bcd81ba6d..2dbb98e23 100644 --- a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts +++ b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts @@ -9,4 +9,26 @@ / { model = "UniElec U7623-02 eMMC"; compatible = "unielec,u7623-02", "mediatek,mt7623"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11004000 root=/dev/fit0 rootwait"; + rootdisk = <&emmc_rootdisk>; + }; +}; + +&mmc0 { + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + emmc_rootdisk: block-partition-env { + partno = <3>; + }; + }; + }; + }; }; diff --git a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi index 50c7f3e88..fedf8b859 100644 --- a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi +++ b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi @@ -121,17 +121,16 @@ #address-cells = <1>; #size-cells = <0>; - mt7530: switch@0 { - compatible = "mediatek,mt7530"; + mt7530: switch@1f { }; }; }; &mt7530 { compatible = "mediatek,mt7530"; + reg = <31>; #address-cells = <1>; #size-cells = <0>; - reg = <0>; pinctrl-names = "default"; mediatek,mcm; resets = <ðsys 2>; @@ -178,7 +177,6 @@ cpu_port0: port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "trgmii"; diff --git a/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts b/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts new file mode 100644 index 000000000..7a3fa4def --- /dev/null +++ b/target/linux/mediatek/dts/mt7629-iptime-a6004mx.dts @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "mt7629.dtsi" + +/ { + model = "ipTIME A6004MX"; + compatible = "iptime,a6004mx", "mediatek,mt7629"; + + aliases { + led-boot = &led_cpu; + led-failsafe = &led_cpu; + led-running = &led_cpu; + led-upgrade = &led_cpu; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "console=ttyS0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_cpu: cpu { + function = LED_FUNCTION_CPU; + color = ; + gpios = <&pio 57 GPIO_ACTIVE_LOW>; + }; + + wlan5g { + label = "orange:wlan5g"; + gpios = <&pio 22 GPIO_ACTIVE_LOW>; + // linux,default-trigger = "phy0radio"; + }; + + wlan2g { + label = "orange:wlan2g"; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + // linux,default-trigger = "phy1radio"; + }; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "factory"; + linux,code = ; + gpios = <&pio 60 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 58 GPIO_ACTIVE_LOW>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + pinctrl-1 = <&ephy_leds_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + nvmem-cells = <&macaddr_factory_4 3>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + nvmem-cells = <&macaddr_factory_4 1>; + nvmem-cell-names = "mac-address"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 28 0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "Config"; + reg = <0x100000 0x40000>; + }; + + partition@140000 { + label = "factory"; + reg = <0x140000 0x80000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@1c0000 { + label = "firmware"; + reg = <0x1c0000 0x7400000>; + compatible = "denx,fit"; + openwrt,fit-offset = <0x800>; + }; + }; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + ephy_leds_pins: ephy-leds-pins { + mux { + function = "led"; + groups = "ephy_leds"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_txd_rxd" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = ; +}; diff --git a/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts b/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts new file mode 100644 index 000000000..99d3a7cef --- /dev/null +++ b/target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "mt7629.dtsi" + +/ { + model = "Netgear EX6250 v2"; + compatible = "netgear,ex6250-v2", "mediatek,mt7629"; + + aliases { + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "console=ttyS0,115200n8"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 60 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&pio 58 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ap_mode { + label = "ap_mode"; + gpios = <&pio 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + extender_mode { + label = "extender_mode"; + gpios = <&pio 53 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_power_green: power_green { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 61 GPIO_ACTIVE_LOW>; + }; + + client_green { + label = "green:client"; + gpios = <&pio 59 GPIO_ACTIVE_LOW>; + }; + + client_red { + label = "red:client"; + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + }; + + router_green { + label = "green:router"; + gpios = <&pio 55 GPIO_ACTIVE_LOW>; + }; + + router_red { + label = "red:router"; + gpios = <&pio 56 GPIO_ACTIVE_LOW>; + }; + + wps_green { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&pio 57 GPIO_ACTIVE_LOW>; + }; + + eth_green { + label = "green:eth"; + gpios = <&pio 16 GPIO_ACTIVE_LOW>; + }; + + eth_yellow { + label = "yellow:eth"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + pinctrl-1 = <&ephy_leds_pins>; + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&qspi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x60000>; + read-only; + }; + + partition@60000 { + label = "Config"; + reg = <0x60000 0x10000>; + read-only; + }; + + partition@70000 { + label = "Factory"; + reg = <0x70000 0x10000>; + read-only; + }; + + partition@80000 { + label = "firmware"; + reg = <0x80000 0xcd0000>; + compatible = "denx,fit"; + }; + + partition@d50000 { + label = "CFG"; + reg = <0xd50000 0x80000>; + read-only; + }; + + partition@dd0000 { + label = "RAE"; + reg = <0xdd0000 0x200000>; + read-only; + }; + + partition@fd0000 { + label = "POT"; + reg = <0xfd0000 0x10000>; + read-only; + }; + + partition@fe0000 { + label = "LOG"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + ephy_leds_pins: ephy-leds-pins { + mux { + function = "led"; + groups = "ephy_leds"; + }; + }; + + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_txd_rxd" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts b/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts new file mode 100644 index 000000000..bab3ad573 --- /dev/null +++ b/target/linux/mediatek/dts/mt7629-tplink_eap225-v5.dts @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include +#include "mt7629.dtsi" + +/ { + model = "TP-Link EAP225 v5"; + compatible = "tplink,eap225-v5", "mediatek,mt7629"; + + aliases { + led-boot = &led_status_green; + led-failsafe = &led_status_amber; + led-running = &led_status_green; + led-upgrade = &led_status_amber; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "console=ttyS0,115200n8"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: status_green { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 55 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_status_amber: status_amber { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 56 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + pinctrl-1 = <&ephy_leds_pins>; + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&phy0>; + nvmem-cells = <&macaddr_factory_8>; + nvmem-cell-names = "mac-address"; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&qspi { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x00080000>; + read-only; + }; + + partition@80000 { + label = "Partition"; + reg = <0x00080000 0x00010000>; + read-only; + }; + + partition@90000 { + label = "Factory"; + reg = <0x00090000 0x00010000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_8: macaddr@8 { + reg = <0x8 0x6>; + }; + }; + }; + + partition@A0000 { + label = "Radio"; + reg = <0x000A0000 0x00010000>; + read-only; + }; + + partition@B0000 { + label = "Extra"; + reg = <0x000B0000 0x00010000>; + read-only; + }; + + /* Vendor layout: kernel (0x000C0000 0x001A0000) - rootfs (0x00260000 0x00BE0000) */ + /* OpenWrt flash layout: combine kernel and rootfs from OEM layout */ + partition@C0000 { + label = "firmware"; + reg = <0x000C0000 0x00D80000>; + }; + + partition@E40000 { + label = "Config"; + reg = <0x00E40000 0x0001B0000>; + read-only; + }; + }; + }; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + ephy_leds_pins: ephy-leds-pins { + mux { + function = "led"; + groups = "ephy_leds"; + }; + }; + + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_txd_rxd" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-abt-asr3000.dts b/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts similarity index 56% rename from target/linux/mediatek/dts/mt7981b-abt-asr3000.dts rename to target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts index b089f3d27..6ff061b1e 100644 --- a/target/linux/mediatek/dts/mt7981b-abt-asr3000.dts +++ b/target/linux/mediatek/dts/mt7981a-comfast-cf-e393ax.dts @@ -1,28 +1,27 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include -#include - #include "mt7981.dtsi" / { - model = "ABT ASR3000"; - compatible = "abt,asr3000", "mediatek,mt7981"; + model = "COMFAST CF-E393AX"; + compatible = "comfast,cf-e393ax", "mediatek,mt7981"; aliases { serial0 = &uart0; - led-boot = &led_wps; - led-upgrade = &led_wps; - label-mac-device = &gmac0; + led-boot = &led_red; + led-failsafe = &led_red; + led-running = &led_blue; + led-upgrade = &led_green; }; chosen { + bootargs-override = "console=ttyS0,115200n8"; stdout-path = "serial0:115200n8"; }; memory { - reg = <0 0x40000000 0 0x10000000>; + reg = <0 0x40000000 0 0x10000000>; // 256mb }; gpio-keys { @@ -33,25 +32,27 @@ linux,code = ; gpios = <&pio 1 GPIO_ACTIVE_LOW>; }; - - mesh { - label = "mesh"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; }; leds { compatible = "gpio-leds"; - wan { - label = "green:wan"; + led_blue: blue { gpios = <&pio 8 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; }; - led_wps: wps { - label = "green:wps"; - gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + led_red: red { + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led_green: green { + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; }; }; }; @@ -60,11 +61,11 @@ status = "okay"; gmac0: mac@0 { + /* LAN */ compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "2500base-x"; - - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_factory_e000 0>; nvmem-cell-names = "mac-address"; fixed-link { @@ -75,44 +76,78 @@ }; gmac1: mac@1 { + /* WAN */ compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "gmii"; phy-handle = <&int_gbe_phy>; - - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_factory_e000 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <0x500000>; }; }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; - reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; }; }; +&crypto { + status = "okay"; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - spi_nand@0 { - compatible = "spi-nand"; + spi_nand: spi_nand@0 { #address-cells = <1>; #size-cells = <1>; - reg = <0>; - + compatible = "spi-nand"; + reg = <1>; spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; @@ -124,48 +159,48 @@ partition@0 { label = "BL2"; - reg = <0x0000000 0x0100000>; + reg = <0x00000 0x0100000>; read-only; }; partition@100000 { label = "u-boot-env"; reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "art"; - reg = <0x0180000 0x0100000>; read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; }; - factory: partition@280000 { + factory: partition@180000 { label = "Factory"; - reg = <0x0280000 0x0100000>; + reg = <0x180000 0x0200000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_e000: macaddr@e000 { + compatible = "mac-base"; + reg = <0xe000 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; partition@380000 { label = "FIP"; - reg = <0x0380000 0x0200000>; + reg = <0x380000 0x0200000>; read-only; }; partition@580000 { label = "ubi"; - reg = <0x0580000 0x7000000>; + reg = <0x580000 0x4000000>; + compatible = "linux,ubi"; }; }; }; @@ -178,16 +213,6 @@ port@0 { reg = <0>; - label = "lan3"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; label = "lan1"; }; @@ -206,34 +231,6 @@ }; }; -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - }; - - wf_led_pins: wf-led-pins { - mux { - function = "led"; - groups = "wf2g_led1", "wf5g_led1"; - }; - }; -}; - &uart0 { status = "okay"; }; @@ -244,12 +241,7 @@ &wifi { status = "okay"; - pinctrl-0 = <&wifi_dbdc_pins>, <&wf_led_pins>; - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - mediatek,mtd-eeprom = <&factory 0x0>; - - led { - led-active-low; - }; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; }; + diff --git a/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts b/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts new file mode 100644 index 000000000..c306a5eb7 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981a-edgecore-eap111.dts @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include +#include "mt7981.dtsi" + +/ { + model = "Edgecore EAP111"; + compatible = "edgecore,eap111", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + led-boot = &led_green; + led-failsafe = &led_green; + led-running = &led_green; + led-upgrade = &led_green; + }; + + chosen { + bootargs-override = "console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_green: led-green { + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led_orange: led-orange { + gpios = <&pio 34 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led_blue: led-blue { + gpios = <&pio 35 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_wan: macaddr@2a { + reg = <0x2a 0x6>; + }; + + macaddr_lan: macaddr@24 { + reg = <0x24 0x6>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + compatible = "linux,ubi"; + }; + }; + }; +}; + +&mdio_bus { + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <10000>; + + en8801sc: ethernet-phy@24 { + reg = <24>; + compatible = "ethernet-phy-id03a2.9471"; + phy-mode = "sgmii"; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "sgmii"; + phy-handle = <&en8801sc>; + managed = "in-band-status"; + nvmem-cells = <&macaddr_lan>; + nvmem-cell-names = "mac-address"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cells = <&macaddr_wan>; + nvmem-cell-names = "mac-address"; + }; +}; + +&wifi { + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi new file mode 100644 index 000000000..e9050e02e --- /dev/null +++ b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000-xe3000-common.dtsi @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200n8 root=PARTLABEL=rootfs rootwait"; + }; + + aliases { + label-mac-device = &gmac0; + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan_5v: regulator-fan-5v { + compatible = "regulator-fixed"; + regulator-name = "fan"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + hub_power { + gpio-export,name = "hub_power"; + gpio-export,output = <1>; + gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; + + 5G_power { + gpio-export,name = "5G_power"; + gpio-export,output = <1>; + gpios = <&pio 11 GPIO_ACTIVE_HIGH>; + }; + + 5G_control { + gpio-export,name = "5G_control"; + gpio-export,output = <1>; + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + }; + + 5G_reset { + gpio-export,name = "5G_reset"; + gpio-export,output = <0>; + gpios = <&pio 10 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + wifi2g { + label = "green:wifi2g"; + gpios = <&pio 30 GPIO_ACTIVE_LOW>; + }; + + wifi5g { + label = "green:wifi5g"; + gpios = <&pio 38 GPIO_ACTIVE_LOW>; + }; + + 5g_led1 { + label = "green:5g:led1"; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + 5g_led2 { + label = "green:5g:led2"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + 5g_led3 { + label = "green:5g:led3"; + gpios = <&pio 8 GPIO_ACTIVE_LOW>; + }; + + 5g_led4 { + label = "green:5g:led4"; + gpios = <&pio 4 GPIO_ACTIVE_HIGH>; + }; + + led_power: power { + label = "green:power"; + gpios = <&pio 39 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "green:wan"; + gpios = <&pio 31 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + block-partition-env { + partname = "u-boot-env"; + + nvmem-layout { + compatible = "u-boot,env-layout"; + }; + }; + + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_a: macaddr@a { + compatible = "mac-base"; + reg = <0xa 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; + }; +}; + +&mdio_bus { + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <600>; + reset-post-delay-us = <20000>; + + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + nvmem-cells = <&macaddr_factory_a 0>; + nvmem-cell-names = "mac-address"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cells = <&macaddr_factory_a 1>; + nvmem-cell-names = "mac-address"; + }; +}; + +&pio { + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; + groups = "emmc_8"; + }; + }; + mmc0_pins_uhs: mmc0-pins-uhs { + mux { + function = "flash"; + groups = "emmc_8"; + }; + }; + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset", "pcie_clk", "pcie_wake"; + }; + }; + pwm0_pin: pwm0-pin-g0 { + mux { + function = "pwm"; + groups = "pwm0_1"; + }; + }; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; + +&fan { + pwms = <&pwm 0 40000 0>; + fan-supply = <&fan_5v>; + interrupt-parent = <&pio>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000.dts b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000.dts new file mode 100644 index 000000000..bee1ecd89 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981a-glinet-gl-x3000.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7981a-glinet-gl-x3000-xe3000-common.dtsi" + +/ { + model = "GL.iNet GL-X3000"; + compatible = "glinet,gl-x3000", "mediatek,mt7981"; +}; diff --git a/target/linux/mediatek/dts/mt7981a-glinet-gl-xe3000.dts b/target/linux/mediatek/dts/mt7981a-glinet-gl-xe3000.dts new file mode 100644 index 000000000..e14b944bc --- /dev/null +++ b/target/linux/mediatek/dts/mt7981a-glinet-gl-xe3000.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7981a-glinet-gl-x3000-xe3000-common.dtsi" + +/ { + model = "GL.iNet GL-XE3000"; + compatible = "glinet,gl-xe3000", "mediatek,mt7981"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&pio { + uart1_pins: uart1-pins-g1 { + mux { + function = "uart"; + groups = "uart1_3"; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts b/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts new file mode 100644 index 000000000..48fe2f2fc --- /dev/null +++ b/target/linux/mediatek/dts/mt7981a-ubnt-unifi-6-plus.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981.dtsi" + +/ { + model = "Ubiquiti UniFi 6 Plus"; + compatible = "ubnt,unifi-6-plus", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + led-boot = &led_white; + led-failsafe = &led_white; + led-running = &led_blue; + led-upgrade = &led_blue; + label-mac-device = &gmac1; + }; + + chosen { + bootargs-override = "console=ttyS0,115200n8 rootwait root=/dev/mmcblk0p7"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + + leds { + compatible = "gpio-leds"; + + led_blue: dome-blue { + label = "blue:dome"; + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + }; + + led_white: dome-white { + label = "white:dome"; + gpios = <&pio 34 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&pio { + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; + + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_uhs: mmc0-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom: partition@00000 { + label = "EEPROM"; + reg = <0x00000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; + }; + }; + + partition@10000 { + label = "u-boot-env"; + reg = <0x10000 0x80000>; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_eeprom_0>; + }; +}; + +&wifi { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cetron-ct3003-mod.dts b/target/linux/mediatek/dts/mt7981b-cetron-ct3003-mod.dts deleted file mode 100644 index b59ee4d20..000000000 --- a/target/linux/mediatek/dts/mt7981b-cetron-ct3003-mod.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include "mt7981b-cetron-ct3003.dts" - -/ { - model = "Cetron CT3003 (U-Boot mod)"; - compatible = "cetron,ct3003-mod", "mediatek,mt7981"; -}; - -&spi0 { - spi_nand@0 { - partitions { - partition@580000 { - label = "ubi"; - reg = <0x0580000 0x7000000>; - }; - - /delete-node/ partition@2580000; - /delete-node/ partition@4580000; - }; - }; -}; diff --git a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts index ee77b3768..919c20891 100644 --- a/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts +++ b/target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts @@ -3,6 +3,7 @@ /dts-v1/; #include #include +#include #include "mt7981.dtsi" @@ -12,6 +13,7 @@ aliases { serial0 = &uart0; + label-mac-device = &gmac0; led-boot = &led_status_red; led-failsafe = &led_status_red; led-running = &led_status_green; @@ -46,12 +48,14 @@ compatible = "gpio-leds"; led_status_red: led_status_red { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 3 GPIO_ACTIVE_LOW>; }; led_status_green: led_status_green { - label = "green:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 7 GPIO_ACTIVE_LOW>; }; }; @@ -65,7 +69,7 @@ reg = <0>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 0>; nvmem-cell-names = "mac-address"; fixed-link { @@ -77,7 +81,7 @@ }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -128,12 +132,16 @@ reg = <0x0180000 0x0100000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; + macaddr_art_0: macaddr@0 { + compatible = "mac-base"; + reg = <0x0 0x6>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -190,9 +198,8 @@ port@3 { reg = <3>; label = "wan"; - nvmem-cells = <&macaddr_art_0>; + nvmem-cells = <&macaddr_art_0 3>; nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; }; port@6 { diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dts b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dts deleted file mode 100644 index c1ce4d130..000000000 --- a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include "mt7981b-cmcc-rax3000m.dts" - -/ { - model = "CMCC RAX3000M (eMMC version)"; - compatible = "cmcc,rax3000m-emmc", "mediatek,mt7981"; - - chosen { - bootargs = "root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; - }; -}; - -&mmc0 { - bus-width = <8>; - max-frequency = <26000000>; - no-sd; - no-sdio; - non-removable; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "flash"; - groups = "emmc_45"; - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "flash"; - groups = "emmc_45"; - }; - }; -}; diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dtso b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dtso new file mode 100644 index 000000000..c1c9c75c2 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +/plugin/; + +/ { + compatible = "cmcc,rax3000m", "mediatek,mt7981"; + + fragment@0 { + target = <&mmc0>; + __overlay__ { + bus-width = <8>; + max-frequency = <26000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + }; + + fragment@1 { + target = <&pio>; + __overlay__ { + mmc0_pins_default: mmc0-pins { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dts b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dts deleted file mode 100644 index 086a4223d..000000000 --- a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include "mt7981b-cmcc-rax3000m.dts" - -/ { - model = "CMCC RAX3000M (NAND version)"; - compatible = "cmcc,rax3000m-nand", "mediatek,mt7981"; - - aliases { - label-mac-device = &gmac1; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <0>; - - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x100000 0x80000>; - }; - - factory: partition@180000 { - label = "factory"; - reg = <0x180000 0x200000>; - read-only; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7200000>; - }; - }; - }; -}; - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0x0>; -}; diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dtso b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dtso new file mode 100644 index 000000000..4d2b01cb6 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dtso @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +/plugin/; + +/ { + compatible = "cmcc,rax3000m", "mediatek,mt7981"; + + fragment@0 { + target = <&gmac0>; + __overlay__ { + nvmem-cells = <&macaddr_factory_2a 0>; + nvmem-cell-names = "mac-address"; + }; + }; + + fragment@1 { + target = <&gmac1>; + __overlay__ { + nvmem-cells = <&macaddr_factory_24 0>; + nvmem-cell-names = "mac-address"; + }; + }; + + fragment@2 { + target = <&pio>; + __overlay__ { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + }; + }; + }; + + fragment@3 { + target = <&spi0>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + factory: partition@180000 { + label = "factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_24: macaddr@24 { + compatible = "mac-base"; + reg = <0x24 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_2a: macaddr@2a { + compatible = "mac-base"; + reg = <0x2a 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7200000>; + }; + }; + }; + }; + }; + + fragment@4 { + target = <&wifi>; + __overlay__ { + mediatek,mtd-eeprom = <&factory 0x0>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts index 3f330f40f..c8db5b58f 100644 --- a/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts +++ b/target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts @@ -6,6 +6,7 @@ /dts-v1/; #include #include +#include #include "mt7981.dtsi" @@ -50,17 +51,20 @@ compatible = "gpio-leds"; green_led: led-0 { - label = "green:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; led-1 { - label = "blue:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 12 GPIO_ACTIVE_LOW>; }; red_led: led-2 { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 35 GPIO_ACTIVE_LOW>; }; }; diff --git a/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts b/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts new file mode 100644 index 000000000..8b9c7a754 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/dts-v1/; + +#include "mt7981.dtsi" +#include +#include +#include + +/ { + model = "Confiabits MT7981"; + compatible = "confiabits,mt7981", "mediatek,mt7981"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-mesh { + label = "mesh"; + linux,input-type = ; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + debounce-interval = <60>; + }; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-wlan5g { + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <5>; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led-wan-red { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + led_power: led-power { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-lan1 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-lan2 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-lan3 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led-wan-blue { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-wlan2g { + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <2>; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led-mesh { + color = ; + function = "mesh"; // no LED_FUNCTION_MESH yet + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 0>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + + +&mdio_bus { + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "wan"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 1>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + read-only; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + compatible = "linux,ubi"; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + +}; + +&usb_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; + mediatek,u3p-dis-msk = <0x1>; +}; + +&wifi { + status = "okay"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts new file mode 100644 index 000000000..85bdabe47 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "Cudy M3000 v1"; + compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb"; + + aliases { + label-mac-device = &gmac0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: internet-white { + function = LED_FUNCTION_WAN_ONLINE; + color = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + internet-red { + function = LED_FUNCTION_WAN_ONLINE; + color = ; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&rtl8221b_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 1>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 0>; + }; +}; + +&mdio_bus { + rtl8221b_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <1>; + + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partition@0 { + label = "BL2"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x0180000 0x0200000>; + read-only; + }; + + bdinfo: partition@380000 { + label = "bdinfo"; + reg = <0x0380000 0x0040000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_de00: macaddr@de00 { + #nvmem-cell-cells = <1>; + compatible = "mac-base"; + reg = <0xde00 0x6>; + }; + }; + }; + + partition@3c0000 { + label = "FIP"; + reg = <0x03c0000 0x0200000>; + }; + + partition@5c0000 { + label = "ubi"; + reg = <0x05c0000 0x4000000>; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&wifi { + status = "okay"; + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts new file mode 100644 index 000000000..4025e5aaa --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-re3000-v1.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include +#include +#include + +#include "mt7981.dtsi" + +/ { + model = "Cudy RE3000 v1"; + compatible = "cudy,re3000-v1", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + label-mac-device = &gmac1; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: led@0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "red:wifi5"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led@2 { + label = "white:wifi2"; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led@3 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led@4 { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 0>; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + }; +}; + +&spi0 { + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + read-only; + }; + + factory: partition@50000 { + label = "Factory"; + reg = <0x50000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + }; + }; + + bdinfo: partition@60000 { + label = "bdinfo"; + reg = <0x60000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_de00: macaddr@de00 { + compatible = "mac-base"; + reg = <0xde00 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@70000 { + label = "FIP"; + reg = <0x70000 0x80000>; + read-only; + }; + + partition@f0000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0xf0000 0xf10000>; + }; + }; + }; +}; + +&pio { + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; +}; + +&wifi { + status = "okay"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dts new file mode 100644 index 000000000..1f03b42b1 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include + +#include "mt7981.dtsi" + +/ { + model = "Cudy TR3000 v1"; + compatible = "cudy,tr3000-v1", "mediatek,mt7981-spim-snand-rfb"; + + aliases { + label-mac-device = &gmac1; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + mode { + label = "mode"; + linux,input-type = ; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: led_0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led_1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + }; + + usb_vbus: regulator-usb { + compatible = "regulator-fixed"; + + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&phy1>; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 1>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 0>; + }; +}; + +&mdio_bus { + phy1: phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + realtek,aldps-enable; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + read-only; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + }; + }; + + partition@380000 { + label = "bdinfo"; + reg = <0x380000 0x0040000>; + read-only; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_de00: macaddr@de00 { + compatible = "mac-base"; + reg = <0xde00 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + + }; + + partition@3C0000 { + label = "FIP"; + reg = <0x3C0000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x5C0000 0x4000000>; + compatible = "linux,ubi"; + }; + }; + }; +}; + + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; + vbus-supply = <&usb_vbus>; +}; + +&wifi { + status = "okay"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts new file mode 100644 index 000000000..1ded8b5a6 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include + +#include "mt7981.dtsi" + +/ { + model = "Cudy WR3000 v1"; + compatible = "cudy,wr3000-v1", "mediatek,mt7981"; + + aliases { + ethernet0 = &gmac0; + label-mac-device = &gmac0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: led@0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "blue:internet"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led@2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led@3 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led@4 { + label = "blue:wifi2"; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led@5 { + label = "blue:wifi5"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 0>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + read-only; + }; + + factory: partition@50000 { + label = "Factory"; + reg = <0x50000 0x10000>; + read-only; + }; + + bdinfo: partition@60000 { + label = "bdinfo"; + reg = <0x60000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_bdinfo_de00: macaddr@de00 { + compatible = "mac-base"; + reg = <0xde00 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@70000 { + label = "FIP"; + reg = <0x70000 0x80000>; + read-only; + }; + + partition@f0000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0xf0000 0xf10000>; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_bdinfo_de00 1>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&wifi { + status = "okay"; + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts b/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts new file mode 100644 index 000000000..dc14fce2b --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-dlink-aquila-pro-ai-m30-a1.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "D-Link AQUILA PRO AI M30 A1"; + compatible = "dlink,aquila-pro-ai-m30-a1", "mediatek,mt7981"; + + aliases { + label-mac-device = &gmac0; + led-boot = &led_status_white; + led-failsafe = &led_status_red; + led-running = &led_status_white; + led-upgrade = &led_status_blue; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-leds-on-off { + label = "leds-on-off"; + linux,code = ; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cells = <&macaddr_odm 1>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + label = "internet"; + + nvmem-cells = <&macaddr_odm 0>; + nvmem-cell-names = "mac-address"; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x3200000>; + }; + + partition@3780000 { + label = "ubi1"; + reg = <0x3780000 0x3200000>; + read-only; + }; + + partition@6980000 { + label = "Odm"; + reg = <0x6980000 0x40000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_odm: macaddr@81 { + compatible = "mac-base"; + reg = <0x81 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + + }; + + partition@69c0000 { + label = "Config1"; + reg = <0x69c0000 0x80000>; + read-only; + }; + + partition@6a40000 { + label = "Config2"; + reg = <0x6a40000 0x80000>; + read-only; + }; + + partition@6ac0000 { + label = "Storage"; + reg = <0x6ac0000 0xA00000>; + read-only; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-down = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + i2c_pins_g0: i2c-pins-g0 { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; +}; + +&wifi { + status = "okay"; + + nvmem-cells = <&eeprom_factory_0>, <&macaddr_odm 2>; + nvmem-cell-names = "eeprom", "mac-address"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_g0>; + + gca230718@40 { + compatible = "unknown,gca230718"; + reg = <0x40>; + + led_status_red: led@0 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <0>; + }; + + led@1 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <1>; + }; + + led_status_blue: led@2 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <2>; + }; + + led_status_white: led@3 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <3>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-fzs-5gcpe-p3.dts b/target/linux/mediatek/dts/mt7981b-fzs-5gcpe-p3.dts deleted file mode 100644 index d1813a7fc..000000000 --- a/target/linux/mediatek/dts/mt7981b-fzs-5gcpe-p3.dts +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include -#include - -#include "mt7981.dtsi" - -/ { - model = "FZS 5GCPE P3"; - compatible = "fzs,5gcpe-p3", "mediatek,mt7981"; - - aliases { - serial0 = &uart0; - led-boot = &led_wifi; - led-upgrade = &led_wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x10000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - linux,code = ; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_wifi: wifi { - label = "green:wifi"; - gpios = <&pio 15 GPIO_ACTIVE_LOW>; - linux,default-trigger = "phy1tpt"; - }; - - 4g { - label = "green:4g"; - gpios = <&pio 34 GPIO_ACTIVE_LOW>; - }; - - 5g { - label = "green:5g"; - gpios = <&pio 35 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - nvmem-cells = <&macaddr_factory_2a>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; -}; - -&mdio_bus { - switch: switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand@0 { - compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x000000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - read-only; - }; - - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7000000>; - }; - }; - }; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "wan"; - nvmem-cells = <&macaddr_factory_24>; - nvmem-cell-names = "mac-address"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1_1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_1"; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&wifi { - status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_24: macaddr@24 { - reg = <0x24 0x6>; - }; - - macaddr_factory_2a: macaddr@2a { - reg = <0x2a 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts index 068dd0f23..15818a90f 100644 --- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts +++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dts @@ -57,7 +57,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + gpios = <&pio 12 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-boot-on; }; @@ -103,6 +103,8 @@ gmac0: mac@0 { compatible = "mediatek,eth-mac"; + nvmem-cells = <&macaddr_boot1_a 0>; + nvmem-cell-names = "mac-address"; reg = <0>; phy-mode = "2500base-x"; @@ -111,6 +113,8 @@ gmac1: mac@1 { compatible = "mediatek,eth-mac"; + nvmem-cells = <&macaddr_boot1_a 1>; + nvmem-cell-names = "mac-address"; reg = <1>; phy-mode = "gmii"; phy-handle = <&int_gbe_phy>; @@ -148,4 +152,54 @@ vmmc-supply = <®_3p3v>; cap-mmc-highspeed; non-removable; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + + partitions { + block-partition-u-boot-env { + partname = "u-boot-env"; + nvmem-layout { + compatible = "u-boot,env-layout"; + }; + }; + }; + }; + + boot1 { + compatible = "block-device"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_boot1_a: macaddr@a { + compatible = "mac-base"; + reg = <0xa 0x6>; + #nvmem-cell-cells = <1>; + }; + + ddns@10 { + reg = <0x10 0x10>; + }; + + sn-bak@20 { + reg = <0x20 0x10>; + }; + + sn@30 { + reg = <0x30 0x10>; + }; + + country-code@88 { + reg = <0x88 0x10>; + }; + }; + }; + }; }; diff --git a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts index bc0016684..727179892 100644 --- a/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts +++ b/target/linux/mediatek/dts/mt7981b-glinet-gl-mt3000.dts @@ -7,10 +7,11 @@ compatible = "glinet,gl-mt3000", "mediatek,mt7981"; aliases { - led-boot = &led_run; - led-failsafe = &led_run; + label-mac-device = &gmac0; + led-boot = &led_lightblue; + led-failsafe = &led_lightblue; led-running = &led_white; - led-upgrade = &led_run; + led-upgrade = &led_lightblue; serial0 = &uart0; }; @@ -39,12 +40,12 @@ leds { compatible = "gpio-leds"; - led_run: run { + led_lightblue: led@0 { label = "blue:run"; gpios = <&pio 31 GPIO_ACTIVE_LOW>; }; - led_white: system { + led_white: led@1 { label = "white:system"; gpios = <&pio 30 GPIO_ACTIVE_LOW>; }; @@ -55,7 +56,7 @@ regulator-name = "fan"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&pio 28 GPIO_ACTIVE_HIGH>; + gpios = <&pio 28 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-boot-on; }; @@ -65,7 +66,7 @@ regulator-name = "usb_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + gpios = <&pio 12 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-boot-on; }; @@ -90,7 +91,7 @@ reg = <0>; phy-mode = "2500base-x"; phy-handle = <&phy0>; - nvmem-cells = <&macaddr>; + nvmem-cells = <&macaddr 0>; nvmem-cell-names = "mac-address"; }; @@ -99,9 +100,8 @@ reg = <1>; phy-mode = "gmii"; phy-handle = <&int_gbe_phy>; - nvmem-cells = <&macaddr>; + nvmem-cells = <&macaddr 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; }; @@ -176,18 +176,25 @@ factory: partition@180000 { label = "Factory"; reg = <0x180000 0x0200000>; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + read-only; - macaddr: macaddr@a { - reg = <0xa 0x6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr: macaddr@a { + compatible = "mac-base"; + reg = <0xa 0x6>; + #nvmem-cell-cells = <1>; + }; }; }; partition@380000 { label = "FIP"; reg = <0x380000 0x0200000>; + read-only; }; partition@580000 { diff --git a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts index 4d405b539..030cc2504 100644 --- a/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts +++ b/target/linux/mediatek/dts/mt7981b-h3c-magic-nx30-pro.dts @@ -3,6 +3,7 @@ /dts-v1/; #include #include +#include #include "mt7981.dtsi" @@ -12,7 +13,6 @@ aliases { serial0 = &uart0; - led-boot = &led_status_green; led-failsafe = &led_status_red; led-running = &led_status_green; @@ -47,12 +47,14 @@ compatible = "gpio-leds"; led_status_green: green { - label = "green:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 4 GPIO_ACTIVE_LOW>; }; led_status_red: red { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 5 GPIO_ACTIVE_LOW>; }; }; @@ -82,7 +84,7 @@ }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -108,10 +110,6 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -196,7 +194,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; diff --git a/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts b/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts index d9fec68bc..c8b9aeba4 100644 --- a/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts +++ b/target/linux/mediatek/dts/mt7981b-jcg-q30-pro.dts @@ -3,6 +3,7 @@ /dts-v1/; #include #include +#include #include "mt7981.dtsi" @@ -41,12 +42,14 @@ compatible = "gpio-leds"; led_status_red: red { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 8 GPIO_ACTIVE_HIGH>; }; led_status_blue: blue { - label = "blue:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 13 GPIO_ACTIVE_LOW>; }; }; @@ -72,7 +75,7 @@ }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -98,10 +101,6 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -122,6 +121,20 @@ label = "Factory"; reg = <0x0180000 0x0200000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_wan: macaddr@a0024 { + reg = <0xa0024 0x6>; + }; + + macaddr_lan: macaddr@a002a { + reg = <0xa002a 0x6>; + }; + }; }; partition@380000 { @@ -167,7 +180,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -214,17 +226,3 @@ mediatek,mtd-eeprom = <&factory 0x0>; }; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_wan: macaddr@a0024 { - reg = <0xa0024 0x6>; - }; - - macaddr_lan: macaddr@a002a { - reg = <0xa002a 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts index bab81b1da..1ac815d8b 100644 --- a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts +++ b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts @@ -3,7 +3,7 @@ /dts-v1/; #include #include - +#include #include "mt7981.dtsi" / { @@ -11,76 +11,83 @@ compatible = "nokia,ea0326gmp", "mediatek,mt7981"; aliases { - serial0 = &uart0; - - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; + led-boot = &power_led; + led-running = &power_led; + led-failsafe = &power_led; + led-upgrade = &power_led; label-mac-device = &gmac1; + serial0 = &uart0; }; chosen { + rootdisk = <&ubi_rootdisk>; stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { reg = <0 0x40000000 0 0x10000000>; }; gpio-keys { compatible = "gpio-keys"; - reset { + button-reset { label = "reset"; linux,code = ; gpios = <&pio 1 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = ; gpios = <&pio 0 GPIO_ACTIVE_LOW>; }; }; - leds { + gpio-leds { compatible = "gpio-leds"; - led_power: power { - label = "green:power"; + power_led: led-0 { + color = ; + function = LED_FUNCTION_POWER; gpios = <&pio 4 GPIO_ACTIVE_LOW>; }; - wan_green { - label = "green:wan"; + led-1 { + color = ; + function = LED_FUNCTION_WAN; gpios = <&pio 5 GPIO_ACTIVE_LOW>; }; - wan_red { - label = "red:wan"; + led-2 { + color = ; + function = LED_FUNCTION_WAN; gpios = <&pio 6 GPIO_ACTIVE_LOW>; }; - lan { - label = "green:lan"; + led-3 { + color = ; + function = LED_FUNCTION_LAN; gpios = <&pio 7 GPIO_ACTIVE_LOW>; }; - wifi { - label = "green:wifi"; + led-4 { + color = ; + function = LED_FUNCTION_WLAN; gpios = <&pio 8 GPIO_ACTIVE_LOW>; - linux,default-trigger = "phy1tpt"; }; - wps { - label = "green:wps"; + led-5 { + color = ; + function = LED_FUNCTION_WPS; gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; }; }; ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; status = "okay"; gmac0: mac@0 { @@ -88,7 +95,7 @@ reg = <0>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_factory_28>; + nvmem-cells = <&macaddr_factory_28 0>; nvmem-cell-names = "mac-address"; fixed-link { @@ -104,14 +111,13 @@ phy-mode = "gmii"; phy-handle = <&int_gbe_phy>; - nvmem-cells = <&macaddr_factory_28>; + nvmem-cells = <&macaddr_factory_28 3>; nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; }; }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -122,33 +128,50 @@ }; }; +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + }; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_flash_pins>; status = "okay"; - spi_nand@0 { - compatible = "spi-nand"; + spi_nand: flash@0 { #address-cells = <1>; #size-cells = <1>; + compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { - label = "BL2"; - reg = <0x0000000 0x0100000>; + label = "bl2"; + reg = <0x00000 0x0100000>; read-only; }; @@ -157,45 +180,56 @@ reg = <0x0100000 0x0080000>; }; - factory: partition@180000 { - label = "Factory"; - reg = <0x0180000 0x0200000>; + partition@180000 { + label = "factory"; + reg = <0x180000 0x0200000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_28: macaddr@28 { + compatible = "mac-base"; + reg = <0x28 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; partition@380000 { - label = "FIP"; - reg = <0x0380000 0x0200000>; + label = "fip"; + reg = <0x380000 0x0200000>; read-only; }; partition@580000 { - label = "Config"; - reg = <0x0580000 0x0200000>; + label = "config"; + reg = <0x580000 0x200000>; read-only; }; partition@780000 { - label = "Config2"; - reg = <0x0780000 0x0200000>; + label = "config2"; + reg = <0x780000 0x200000>; read-only; }; partition@980000 { - label = "Aos-net"; - reg = <0x0980000 0x0c00000>; - read-only; - }; - - partition@1580000 { - label = "bvasPlugin"; - reg = <0x1580000 0x0c00000>; - read-only; - }; - - partition@2180000 { + compatible = "linux,ubi"; label = "ubi"; - reg = <0x2180000 0x5680000>; + reg = <0x980000 0x7680000>; + + volumes { + ubi_rootdisk: ubi-volume-fit { + volname = "fit"; + }; + }; }; }; }; @@ -223,7 +257,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -236,27 +269,6 @@ }; }; -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - }; -}; - &uart0 { status = "okay"; }; @@ -266,20 +278,7 @@ }; &wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; - nvmem-cells = <&macaddr_factory_28>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_28: macaddr@28 { - reg = <0x28 0x6>; - }; }; diff --git a/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts b/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts new file mode 100644 index 000000000..0e9dea1dd --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-openembed-som7981.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include +#include +#include +#include "mt7981.dtsi" + +/ { + model = "OpenEmbed SOM7981"; + compatible = "openembed,som7981", "mediatek,mt7981"; + + aliases { + led-boot = &wlan2g_led; + led-failsafe = &wlan2g_led; + led-upgrade = &wlan2g_led; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + reg = <0 0x40000000 0 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 8 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + wlan2g_led: led-2 { + function = LED_FUNCTION_WLAN_2GHZ; + color = ; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led-3 { + function = LED_FUNCTION_WLAN_5GHZ; + color = ; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + nvmem-cells = <&macaddr_factory_a 0>; + nvmem-cell-names = "mac-address"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cells = <&macaddr_factory_a 1>; + nvmem-cell-names = "mac-address"; + }; +}; + +&mdio_bus { + phy0: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + realtek,aldps-enable; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + compatible = "nvmem-cells"; + label = "factory"; + reg = <0x180000 0x100000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_a: macaddr@a { + compatible = "mac-base"; + reg = <0xa 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@280000 { + label = "config"; + reg = <0x280000 0x100000>; + read-only; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0xf880000>; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-openwrt-one.dts b/target/linux/mediatek/dts/mt7981b-openwrt-one.dts new file mode 100644 index 000000000..b2223f8d7 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-openwrt-one.dts @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7981.dtsi" + +/ { + model = "OpenWrt One"; + compatible = "openwrt,one", "mediatek,mt7981"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + led-boot = &led_status_white; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_green; + }; + + chosen { + stdout-path = "serial0:115200n8"; + rootdisk = <&ubi_fit_volume>; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user { + label = "user"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_status_white: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + pwms = <&pwm 0 10000>; + linux,default-trigger = "pattern"; + led-pattern = <0 500 25 500>; + }; + + led_status_green: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + pwms = <&pwm 1 10000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_status_red: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + gpio-0 { + gpio-export,name = "mikrobus-reset"; + gpio-export,output = <1>; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + }; + + gpio-1 { + gpio-export,name = "watchdog-enable"; + gpio-export,output = <1>; + gpios = <&pio 11 GPIO_ACTIVE_HIGH>; + }; + + gpio-2 { + gpio-export,name = "usb-enable"; + gpio-export,output = <1>; + gpios = <&pio 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-watchdog { + compatible = "linux,wdt-gpio"; + gpios = <&pio 8 GPIO_ACTIVE_LOW>; + hw_algo = "toggle"; + hw_margin_ms = <25000>; + always-running; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-handle = <&phy15>; + phy-mode = "2500base-x"; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_a>; + }; +}; + +&mdio_bus { + phy15: phy@f { + reg = <0xf>; + + airoha,pnswap-rx; + + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + + phy-mode = "2500base-x"; + full-duplex; + pause; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = ; + }; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + spi1_flash_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1_1"; + }; + + conf-pu { + pins = "SPI1_CS"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c0_0"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_0_tx_rx"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_0", "pwm1_1"; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x100000 0x7F00000>; + compatible = "linux,ubi"; + + volumes { + ubi_fit_volume: ubi-volume-fit { + volname = "fit"; + }; + }; + }; + }; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_flash_pins>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <52000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2-nor"; + reg = <0x00000 0x40000>; + }; + + partition@40000 { + label = "factory"; + reg = <0x40000 0xc0000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x24 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_a: macaddr@a { + compatible = "mac-base"; + reg = <0x2a 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@100000 { + label = "fip-nor"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xc80000>; + }; + }; + }; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&sgmiisys0 { + /delete-node/ mediatek,pnswap; +}; diff --git a/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts b/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts index b937c43b6..3925f80ba 100644 --- a/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts +++ b/target/linux/mediatek/dts/mt7981b-qihoo-360t7.dts @@ -3,6 +3,7 @@ /dts-v1/; #include #include +#include #include "mt7981.dtsi" @@ -12,7 +13,6 @@ aliases { serial0 = &uart0; - led-boot = &led_status_red; led-failsafe = &led_status_red; led-running = &led_status_green; @@ -47,12 +47,14 @@ compatible = "gpio-leds"; led_status_red: red { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 3 GPIO_ACTIVE_LOW>; }; led_status_green: green { - label = "green:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 7 GPIO_ACTIVE_LOW>; }; }; @@ -75,7 +77,7 @@ }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -101,10 +103,6 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -186,7 +184,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; diff --git a/target/linux/mediatek/dts/mt7981b-routerich-ax3000.dts b/target/linux/mediatek/dts/mt7981b-routerich-ax3000.dts new file mode 100644 index 000000000..dfe44843b --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-routerich-ax3000.dts @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7981.dtsi" + +/ { + model = "Routerich AX3000"; + compatible = "routerich,ax3000", "mediatek,mt7981"; + + aliases { + label-mac-device = &wan; + + led-boot = &led_power_blue; + led-failsafe = &led_power_blue; + led-running = &led_power_blue; + led-upgrade = &led_power_blue; + + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + label = "mesh"; + linux,input-type = ; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + button-1 { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <50>; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + }; + + led_power_blue: led-2 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led-6 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-7 { + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <24>; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led-8 { + color = ; + /* LED_FUNCTION_MESH isn't implemented yet */ + function = "mesh"; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + }; + }; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 (-1)>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <0x1f>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + /* ESMT F50L1G41LB (128M) */ + spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4e 0x41 0x4e 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0_all { + label = "spi0.0"; + reg = <0x0 0x8000000>; + read-only; + }; + + partition@0 { + label = "BL2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + + partition@4580000 { + label = "firmware_backup"; + reg = <0x4580000 0x2000000>; + read-only; + }; + + partition@6580000 { + label = "zrsave"; + reg = <0x6580000 0x100000>; + read-only; + }; + + partition@6680000 { + label = "config2"; + reg = <0x6680000 0x100000>; + read-only; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + wan: port@4 { + reg = <4>; + label = "wan"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 (-2)>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + nvmem-cell-names = "eeprom"; + nvmem-cells = <&eeprom_factory_0>; +}; + +&xhci { + status = "okay"; + mediatek,u3p-dis-msk = <0x1>; +}; diff --git a/target/linux/mediatek/dts/mt7981b-unielec-u7981-01-emmc.dts b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01-emmc.dts new file mode 100644 index 000000000..abd4d4e59 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01-emmc.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 Allen Zhao + */ + +/dts-v1/; +#include "mt7981b-unielec-u7981-01.dtsi" +/ { + model = "Unielec U7981-01 (EMMC)"; + compatible = "unielec,u7981-01-emmc", "mediatek,mt7981"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <52000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + block-partition-env { + partname = "u-boot-env"; + + nvmem-layout { + compatible = "u-boot,env-layout"; + }; + }; + + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_1000: macaddr@1000 { + compatible = "mac-base"; + reg = <0x1000 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; + }; +}; + +&pio { + mmc0_pins_default: mmc0-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_uhs: mmc0-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_1000 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_1000 1>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-unielec-u7981-01-nand.dts b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01-nand.dts new file mode 100644 index 000000000..230a612a3 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01-nand.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 Allen Zhao + */ + +/dts-v1/; +#include "mt7981b-unielec-u7981-01.dtsi" +/ { + model = "Unielec U7981-01 (NAND)"; + compatible = "unielec,u7981-01-nand", "mediatek,mt7981"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + spi_nand: spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "factory"; + reg = <0x180000 0x200000>; + read-only; + + compatible = "nvmem-cells"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_1000: macaddr@1000 { + compatible = "mac-base"; + reg = <0x1000 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x0200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_1000 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_1000 1>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi new file mode 100644 index 000000000..6e6150ba2 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-unielec-u7981-01.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 Allen Zhao + */ + +/dts-v1/; +#include "mt7981.dtsi" +/ { + model = "Unielec U7981-01 (EMMC)"; + compatible = "unielec,u7981-01-emmc", "mediatek,mt7981"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11002000 \ + "; + }; + + gpio-keys { + compatible = "gpio-keys"; + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins &gbe_led0_pins &gbe_led1_pins>; + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + /* WAN */ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&xhci { + mediatek,u3p-dis-msk = <0x0>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts b/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts new file mode 100644 index 000000000..62be0faa4 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-wavlink-wl-wn586x3.dts @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "WAVLINK WL-WN586X3"; + compatible = "wavlink,wl-wn586x3", "mediatek,mt7981"; + + aliases { + label-mac-device = &wifi; + led-boot = &led_status_blue; + led-failsafe = &led_status_blue; + led-running = &led_status_blue; + led-upgrade = &led_status_blue; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_status_blue: led-2 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + nvmem-cells = <&macaddr_hw_44e 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + nvmem-cells = <&macaddr_hw_44e 1>; + nvmem-cell-names = "mac-address"; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@00000 { + label = "bl2"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + read-only; + }; + + factory: partition@50000 { + label = "factory"; + reg = <0x50000 0xb0000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@f0000 { + label = "firmware"; + reg = <0x180000 0xe00000>; + }; + + partition@f80000 { + label = "hw"; + reg = <0xf80000 0x80000>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_hw_44e: macaddr@44e { + compatible = "mac-base"; + reg = <0x44e 0x11>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&wifi { + status = "okay"; + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_factory_4 0>; + nvmem-cell-names = "mac-address"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-ax3000t.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-ax3000t.dts deleted file mode 100644 index 96f7680ef..000000000 --- a/target/linux/mediatek/dts/mt7981b-xiaomi-ax3000t.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; - -#include "mt7981b-xiaomi_mi-router.dtsi" - -/ { - model = "Xiaomi Mi Router AX3000T"; - compatible = "xiaomi,mi-router-ax3000t", "mediatek,mt7981"; -}; - -&gmac0 { - nvmem-cells = <&macaddr_factory_4>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <(-2)>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; - - nfc@57 { - compatible = "nt082c"; - reg = <0x57>; - }; -}; - -&partitions { - partition@600000 { - label = "ubi"; - reg = <0x0600000 0x6400000>; - }; - - partition@6a00000 { - label = "data"; - reg = <0x6a00000 0x0c00000>; - read-only; - }; -}; - -&pio { - i2c_pins: i2c-pins { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; -}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t-ubootmod.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t-ubootmod.dts new file mode 100644 index 000000000..809e625ce --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t-ubootmod.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-ax3000t.dtsi" + +/ { + model = "Xiaomi Mi Router AX3000T (OpenWrt U-Boot layout)"; + compatible = "xiaomi,mi-router-ax3000t-ubootmod", "mediatek,mt7981"; +}; + +&partitions { + partition@600000 { + label = "ubi"; + reg = <0x600000 0x7000000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t.dts new file mode 100644 index 000000000..cc0d44fdf --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-ax3000t.dtsi" + +/ { + model = "Xiaomi Mi Router AX3000T"; + compatible = "xiaomi,mi-router-ax3000t", "mediatek,mt7981"; +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + +&partitions { + // ubi_kernel is the ubi partition in stock. + partition@600000 { + label = "ubi_kernel"; + reg = <0x600000 0x2200000>; + }; + + /* ubi is the result of squashing + * consecutive stock partitions: + * - ubi1 + * - overlay + * - data + */ + partition@2800000 { + label = "ubi"; + reg = <0x2800000 0x4e00000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t.dtsi new file mode 100644 index 000000000..7b6fde846 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-ax3000t.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-common.dtsi" + +&gmac0 { + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 (-2)>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + + nfc@57 { + compatible = "nt082c"; + reg = <0x57>; + }; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi_mi-router.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi similarity index 69% rename from target/linux/mediatek/dts/mt7981b-xiaomi_mi-router.dtsi rename to target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi index bb97b5588..d6872395a 100644 --- a/target/linux/mediatek/dts/mt7981b-xiaomi_mi-router.dtsi +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-common.dtsi @@ -1,17 +1,18 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include +/dts-v1/; #include +#include #include "mt7981.dtsi" / { aliases { serial0 = &uart0; - led-boot = &led_system_orange; - led-failsafe = &led_system_blue; - led-running = &led_system_blue; - led-upgrade = &led_system_orange; + led-boot = &led_status_yellow; + led-failsafe = &led_status_yellow; + led-running = &led_status_blue; + led-upgrade = &led_status_yellow; }; chosen { @@ -25,30 +26,32 @@ gpio-keys { compatible = "gpio-keys"; - reset { - label = "reset"; - linux,code = ; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - }; - - mesh { + button-mesh { label = "mesh"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; linux,code = ; linux,input-type = ; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "reset"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; }; }; leds: leds { compatible = "gpio-leds"; - led_system_blue: system_blue { - label = "blue:system"; + led_status_blue: led-status-blue { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; - led_system_orange: system_orange { - label = "orange:system"; + led_status_yellow: led-status-yellow { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 10 GPIO_ACTIVE_LOW>; }; }; @@ -71,7 +74,7 @@ }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -82,89 +85,6 @@ }; }; -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand@0 { - compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x0000000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "Nvram"; - reg = <0x0100000 0x0040000>; - read-only; - }; - - partition@140000 { - label = "Bdata"; - reg = <0x0140000 0x0040000>; - read-only; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x0180000 0x0200000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; - }; - }; - - partition@380000 { - label = "FIP"; - reg = <0x0380000 0x0200000>; - read-only; - }; - - partition@580000 { - label = "crash"; - reg = <0x0580000 0x0040000>; - read-only; - }; - - partition@5c0000 { - label = "crash_log"; - reg = <0x05c0000 0x0040000>; - read-only; - }; - - partition@7600000 { - label = "KF"; - reg = <0x7600000 0x0040000>; - read-only; - }; - }; - }; -}; - &switch { ports { #address-cells = <1>; @@ -192,7 +112,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -205,6 +124,91 @@ }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00 0x100000>; + read-only; + }; + + partition@100000 { + label = "Nvram"; + reg = <0x100000 0x40000>; + }; + + partition@140000 { + label = "Bdata"; + reg = <0x140000 0x40000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "crash"; + reg = <0x580000 0x40000>; + read-only; + }; + + partition@5c0000 { + label = "crash_log"; + reg = <0x5c0000 0x40000>; + read-only; + }; + + partition@7600000 { + label = "KF"; + reg = <0x7600000 0x40000>; + read-only; + }; + }; + }; +}; + &pio { spi0_flash_pins: spi0-pins { mux { @@ -214,18 +218,24 @@ conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ + drive-strength = ; + bias-pull-up = ; }; conf-pd { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ + drive-strength = ; + bias-pull-down = ; }; }; }; +&wifi { + status = "okay"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; +}; + &uart0 { status = "okay"; }; @@ -233,9 +243,3 @@ &watchdog { status = "okay"; }; - -&wifi { - status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; -}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts new file mode 100644 index 000000000..7faa6e84e --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-stock.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-wr30u.dtsi" + +/ { + model = "Xiaomi Mi Router WR30U (stock layout)"; + compatible = "xiaomi,mi-router-wr30u-stock", "mediatek,mt7981"; +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + +&partitions { + // ubi_kernel is the ubi partition in stock. + partition@600000 { + label = "ubi_kernel"; + reg = <0x600000 0x2200000>; + }; + + /* ubi is the result of squashing + * consecutive stock partitions: + * - ubi1 + * - overlay + * - data + */ + partition@2800000 { + label = "ubi"; + reg = <0x2800000 0x4e00000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts new file mode 100644 index 000000000..6d0f3feb4 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u-ubootmod.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-wr30u.dtsi" + +/ { + model = "Xiaomi Mi Router WR30U (OpenWrt U-Boot layout)"; + compatible = "xiaomi,mi-router-wr30u-ubootmod", "mediatek,mt7981"; +}; + +&partitions { + partition@600000 { + label = "ubi"; + reg = <0x600000 0x7000000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi new file mode 100644 index 000000000..87a2493a2 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-xiaomi-mi-router-wr30u.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7981b-xiaomi-mi-router-common.dtsi" + +&gmac0 { + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 (-1)>; +}; + +&leds { + led-wan-blue { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led-wan-yellow { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7981b-xiaomi-wr30u.dts b/target/linux/mediatek/dts/mt7981b-xiaomi-wr30u.dts deleted file mode 100644 index f1cfcf1a3..000000000 --- a/target/linux/mediatek/dts/mt7981b-xiaomi-wr30u.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; - -#include "mt7981b-xiaomi_mi-router.dtsi" - -/ { - model = "Xiaomi Mi Router WR30U"; - compatible = "xiaomi,mi-router-wr30u", "mediatek,mt7981"; -}; - -&gmac0 { - nvmem-cells = <&macaddr_factory_4>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; -}; - -&leds { - internet_blue { - label = "blue:internet"; - gpios = <&pio 11 GPIO_ACTIVE_LOW>; - }; - - internet_orange { - label = "orange:internet"; - gpios = <&pio 12 GPIO_ACTIVE_LOW>; - }; -}; - -&partitions { - partition@600000 { - label = "ubi"; - reg = <0x600000 0x7000000>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts new file mode 100644 index 000000000..5f98e6178 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + compatible = "yuncore,ax835", "mediatek,mt7981"; + model = "YunCore AX835"; + + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + reg_led_vbus { + compatible = "regulator-fixed"; + regulator-name = "led_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + + led_system: led_system { + label = "red:system"; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + led_wifi24 { + label = "green:wifi2"; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led_wifi5 { + label = "blue:wifi5"; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_hwwatchdog { + // a gpio-wdt watchdog couldn't be made to work. + // the device rebooted after 5 minutes. + label = "hwwatchdog"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + led-pattern = <1000>, <1000>; + }; + + // there's another "syswatchdog" on gpio2 + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_2a>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@00000 { + label = "BL2"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + read-only; + }; + + factory: partition@50000 { + label = "Factory"; + reg = <0x50000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + + macaddr_factory_24: macaddr@24 { + reg = <0x24 0x6>; + }; + + macaddr_factory_2a: macaddr@2a { + reg = <0x2a 0x6>; + }; + }; + }; + + partition@100000 { + label = "FIP"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x180000 0xe00000>; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + label = "lan"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + nvmem-cells = <&eeprom_factory 0>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts new file mode 100644 index 000000000..f4d5271f9 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8102ax.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "Zbtlink ZBT-Z8102AX"; + compatible = "zbtlink,zbt-z8102ax", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_green; + label-mac-device = &gmac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 loglevel=8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + button-mesh { + label = "mesh"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + + button-hub { + label = "hub"; + linux,code = ; + gpios = <&pio 12 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_red: red { + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + led_status_green: green { + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + blue { + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; + }; + + 4g { + gpios = <&pio 8 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_USB; + function-enumerator = <0>; + }; + + 4g2 { + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_USB; + function-enumerator = <1>; + }; + }; + + watchdog { + compatible = "linux,wdt-gpio"; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + hw_algo = "toggle"; + hw_margin_ms = <1000>; + }; + + gpio-export { + compatible = "gpio-export"; + #size-cells = <0>; + + pcie { + gpio-export,name = "pcie_power"; + gpio-export,output = <1>; + gpios = <&pio 3 GPIO_ACTIVE_HIGH>; + }; + + 5g1 { + gpio-export,name = "5g1"; + gpio-export,output = <1>; + gpios = <&pio 4 GPIO_ACTIVE_HIGH>; + }; + + 5g2 { + gpio-export,name = "5g2"; + gpio-export,output = <1>; + gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; + + sim1 { + gpio-export,name = "sim1"; + gpio-export,output = <1>; + gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + }; + + sim2 { + gpio-export,name = "sim2"; + gpio-export,output = <1>; + gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 2>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + /* WAN */ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 3>; + }; +}; + +&mdio_bus { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + bias-pull-up = <103>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + bias-pull-down = <103>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&wifi { + status = "okay"; + + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts similarity index 51% rename from target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts rename to target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts index 5371e2ae0..2b079f5bc 100644 --- a/target/linux/mediatek/dts/mt7981b-imou-lc-hx3001.dts +++ b/target/linux/mediatek/dts/mt7981b-zbtlink-zbt-z8103ax.dts @@ -1,26 +1,25 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /dts-v1/; -#include -#include #include "mt7981.dtsi" / { - model = "IMOU LC-HX3001"; - compatible = "imou,lc-hx3001", "mediatek,mt7981"; + model = "Zbtlink ZBT-Z8103AX"; + compatible = "zbtlink,zbt-z8103ax", "mediatek,mt7981"; aliases { serial0 = &uart0; - - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_green; + label-mac-device = &gmac0; }; chosen { stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 loglevel=8"; }; memory { @@ -30,47 +29,62 @@ gpio-keys { compatible = "gpio-keys"; - reset { + button-mesh { + label = "mesh"; + linux,code = ; + linux,input-type = ; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + + button-reset { label = "reset"; linux,code = ; gpios = <&pio 1 GPIO_ACTIVE_LOW>; }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; }; leds { compatible = "gpio-leds"; - led_power: power { - label = "green:power"; - gpios = <&pio 4 GPIO_ACTIVE_LOW>; - }; - - wifi { - label = "green:wifi"; - gpios = <&pio 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "phy1tpt"; - }; - - wan_red { - label = "red:wan"; - gpios = <&pio 6 GPIO_ACTIVE_LOW>; - }; - - wan_green { - label = "green:wan"; - gpios = <&pio 7 GPIO_ACTIVE_LOW>; - }; - - lan { - label = "green:lan"; + led-wan { + color = ; + function = LED_FUNCTION_WAN; gpios = <&pio 8 GPIO_ACTIVE_LOW>; }; + + led-status-blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 23 GPIO_ACTIVE_HIGH>; + }; + + led_status_green: led-status-green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + }; + + led_status_red: led-status-red { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 25 GPIO_ACTIVE_LOW>; + }; + + led-wlan2g { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + function-enumerator = <0>; + linux,default-trigger = "phy0tpt"; + }; + + led-wlan5g { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + function-enumerator = <1>; + linux,default-trigger = "phy1tpt"; + }; }; }; @@ -78,10 +92,14 @@ status = "okay"; gmac0: mac@0 { + /* LAN */ compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "2500base-x"; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 2>; + fixed-link { speed = <2500>; full-duplex; @@ -90,15 +108,19 @@ }; gmac1: mac@1 { + /* WAN */ compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "gmii"; phy-handle = <&int_gbe_phy>; + + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_factory_4 3>; }; }; &mdio_bus { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; @@ -124,41 +146,53 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { - label = "BL2"; + label = "bl2"; reg = <0x0000000 0x0100000>; read-only; }; partition@100000 { label = "u-boot-env"; - reg = <0x0100000 0x0080000>; + reg = <0x100000 0x80000>; }; - factory: partition@180000 { + partition@180000 { label = "Factory"; - reg = <0x0180000 0x0200000>; + reg = <0x180000 0x200000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; partition@380000 { label = "FIP"; - reg = <0x0380000 0x0200000>; + reg = <0x380000 0x200000>; read-only; }; partition@580000 { label = "ubi"; - reg = <0x0580000 0x7280000>; + reg = <0x580000 0x4000000>; }; }; }; @@ -208,14 +242,14 @@ conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ + drive-strength = ; + bias-pull-up = ; }; conf-pd { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ + drive-strength = ; + bias-pull-down = ; }; }; }; @@ -230,6 +264,6 @@ &wifi { status = "okay"; - - mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; }; diff --git a/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts b/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts new file mode 100644 index 000000000..54df8c054 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/dts-v1/; + +#include "mt7981.dtsi" + +/ { + model = "ZyXEL NWA50AX Pro"; + compatible = "zyxel,nwa50ax-pro", "mediatek,mt7981"; + + aliases { + led-boot = &led_green; + led-failsafe = &led_red; + led-running = &led_green; + led-upgrade = &led_red; + serial0 = &uart0; + label-mac-device = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_green: led@0 { + label = "green:system"; + gpios = <&pio 4 GPIO_ACTIVE_HIGH>; + }; + + led@1 { + label = "blue:system"; + gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + }; + + led_red: led@2 { + label = "red:system"; + gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + status = "okay"; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_mrd_1fff8>; + nvmem-cell-names = "mac-address"; + }; +}; + +&mdio_bus { + reset-gpios = <&pio 12 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + phy0: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + + /* LED0: Amber ; LED1: nc ; LED2: nc ; LED3: Green */ + mxl,led-config = <0x3b0 0x0 0x0 0x3c0>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + + spi-cal-enable; + spi-cal-mode = "read-data"; + spi-cal-datalen = <7>; + spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; + spi-cal-addrlen = <5>; + spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; + + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr: macaddr@a { + reg = <0xa 0x6>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x3200000>; + }; + + partition@3780000 { + label = "ubi_1"; + reg = <0x3780000 0x3200000>; + read-only; + }; + + partition@6980000 { + label = "rootfs-data"; + reg = <0x6980000 0x3c00000>; + read-only; + }; + + partition@a580000 { + label = "logs"; + reg = <0xa580000 0x3a80000>; + read-only; + }; + + partition@e000000 { + label = "myzyxel"; + reg = <0xe000000 0xf00000>; + read-only; + }; + + partition@ef00000 { + label = "bootconfig"; + reg = <0xef00000 0x80000>; + }; + + partition@ef80000 { + label = "mrd"; + reg = <0xef80000 0x80000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_mrd_1fff8: macaddr@1fff8 { + reg = <0x1fff8 0x6>; + }; + }; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + pwm_pins: pwm0-pins { + mux { + function = "pwm"; + groups = "pwm0_1"; + }; + }; +}; + +&wifi { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-acelink-ew-7886cax.dts b/target/linux/mediatek/dts/mt7986a-acelink-ew-7886cax.dts new file mode 100644 index 000000000..1bf5d7317 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-acelink-ew-7886cax.dts @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + compatible = "acelink,ew-7886cax", "mediatek,mt7986a"; + model = "Acelink EW-7886CAX"; + + aliases { + serial0 = &uart0; + led-boot = &led_status_blue; + led-running = &led_status_green; + led-upgrade = &led_status_red; + led-failsafe = &led_status_red; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + reg = <0 0x40000000 0 0x20000000>; + device_type = "memory"; + }; + + keys { + compatible = "gpio-keys"; + + key-restart { + label = "Reset"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_red: led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + }; + + led_status_green: led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: led-2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + nvmem-cells = <&macaddr>; + nvmem-cell-names = "mac-address"; + }; + + mdio-bus { + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <50000>; + reset-post-delay-us = <20000>; + #address-cells = <1>; + #size-cells = <0>; + + /* Maxlinear GPY211C */ + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + label = "bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + label = "u-boot-env"; + }; + + partition@180000 { + compatible = "nvmem-cells"; + reg = <0x180000 0x200000>; + label = "factory"; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr: macaddr@4 { + reg = <0x4 0x6>; + }; + }; + }; + + partition@380000 { + reg = <0x380000 0x200000>; + label = "fip"; + }; + + partition@580000 { + reg = <0x580000 0x4000000>; + label = "ubi"; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; + nvmem-cells = <&eeprom>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts b/target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts new file mode 100644 index 000000000..612f3c733 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Acer Predator W6"; + compatible = "acer,predator-w6", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "dm-mod.create=\"dm-verity,,,ro,0 31544 verity 1 PARTLABEL=rootfs PARTLABEL=rootfs 4096 4096 3943 3944 sha256 2f969fa9e9e4e20b37746f22633e85b178f5db7c143e11f92733a704299cc933 2dd56e34b15c6c84573cf26c4392028421061d2c808975217b45e9a5b49d2087\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + factory { + label = "factory"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + + leds { + compatible = "gpio-leds"; + + led_status: led@0 { + label = "ant0:red"; + gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@1 { + label = "ant0:green"; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "ant0:blue"; + gpios = <&pio 36 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "ant1:red"; + gpios = <&pio 35 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@4 { + label = "ant1:green"; + gpios = <&pio 34 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "ant1:blue"; + gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@6 { + label = "ant2:red"; + gpios = <&pio 38 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@7 { + label = "ant2:green"; + gpios = <&pio 37 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@8 { + label = "ant2:blue"; + gpios = <&pio 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@9 { + label = "ant3:red"; + gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@10 { + label = "ant3:green"; + gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@11 { + label = "ant3:blue"; + gpios = <&pio 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@12 { + label = "ant4:red"; + gpios = <&pio 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@13 { + label = "ant4:green"; + gpios = <&pio 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@14 { + label = "ant4:blue"; + gpios = <&pio 32 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@15 { + label = "ant5:red"; + gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@16 { + label = "ant5:green"; + gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@17 { + label = "ant5:blue"; + gpios = <&pio 43 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + /* WAN */ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + + /* LED0: nc ; LED1: nc ; LED2: Amber ; LED3: Green */ + mxl,led-config = <0x0 0x0 0x370 0x80>; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "game"; + phy-handle = <&swphy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&swphy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&swphy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&swphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + swphy0: phy@0 { + reg = <0>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + swphy1: phy@1 { + reg = <1>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + swphy2: phy@2 { + reg = <2>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + swphy3: phy@3 { + reg = <3>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0xc001 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + }; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&trng { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <0x08>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts b/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts new file mode 100644 index 000000000..0034ad828 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-asus-rt-ax59u.dts @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + + model = "ASUS RT-AX59U"; + compatible = "asus,rt-ax59u", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_blue; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = ""; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + button-0 { + label = "wps"; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-1 { + label = "reset"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + + led_status_red: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led_status_blue: led-2 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + out { + gpio-export,name = "led-light"; + gpio-export,output = <0>; + gpios = <&pio 22 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "wan"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + spi_nand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + /* + * ASUS bootloader tries to replace the partitions defined in + * Device Tree and by that also deletes all additional properties + * needed for UBI and NVMEM-on-UBI. + * Prevent this from happening by tricking the loader to delete and + * replace a bait node instead. + */ + partitions: dummy { + compatible = "u-boot-dummy-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x0>; + label = "remove_me"; + }; + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x400000>; + label = "u-boot"; + read-only; + }; + + partition@400000 { + compatible = "linux,ubi"; + reg = <0x400000 0xfc00000>; + label = "UBI_DEV"; + + volumes { + ubi_factory: ubi-volume-factory { + volname = "Factory"; + }; + }; + }; + }; + }; +}; + +&ubi_factory { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; + pinctrl-names = "default", "dbdc"; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts index bcbe0d2a9..e40602fa2 100644 --- a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts +++ b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts @@ -13,6 +13,7 @@ aliases { serial0 = &uart0; + label-mac-device = &gmac0; led-boot = &led_system; led-failsafe = &led_system; led-running = &led_system; @@ -21,7 +22,7 @@ chosen { stdout-path = "serial0:115200n8"; - bootargs-override = "ubi.mtd=UBI_DEV"; + bootargs-override = ""; }; memory { @@ -65,7 +66,8 @@ }; wan-red { - label = "red:wan"; + function = LED_FUNCTION_WAN; + color = ; gpios = <&pio 12 GPIO_ACTIVE_LOW>; }; }; @@ -100,6 +102,8 @@ /* LAN */ compatible = "mediatek,eth-mac"; reg = <0>; + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; phy-mode = "2500base-x"; fixed-link { @@ -136,7 +140,7 @@ mxl,led-config = <0x03f0 0x0 0x0 0x0>; }; - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; @@ -214,25 +218,66 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - partitions: partitions { + /* + * ASUS bootloader tries to replace the partitions defined in + * Device Tree and by that also deletes all additional properties + * needed for UBI and NVMEM-on-UBI. + * Prevent this from happening by tricking the loader to delete and + * replace a bait node instead. + */ + partitions: dummy { + compatible = "u-boot-dummy-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x0>; + label = "remove_me"; + }; + }; + + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { - label = "bootloader"; reg = <0x0 0x400000>; + label = "bootloader"; read-only; }; partition@400000 { - label = "UBI_DEV"; + compatible = "linux,ubi"; reg = <0x400000 0xfc00000>; + label = "UBI_DEV"; + + volumes { + ubi_factory: ubi-volume-factory { + volname = "Factory"; + }; + }; }; }; }; }; +&ubi_factory { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + }; +}; + &switch { ports { #address-cells = <1>; @@ -241,21 +286,25 @@ port@1 { reg = <1>; label = "lan1"; + phy-handle = <&swphy1>; }; port@2 { reg = <2>; label = "lan2"; + phy-handle = <&swphy2>; }; port@3 { reg = <3>; label = "lan3"; + phy-handle = <&swphy3>; }; port@4 { reg = <4>; label = "lan4"; + phy-handle = <&swphy4>; }; port@6 { @@ -276,7 +325,7 @@ #address-cells = <1>; #size-cells = <0>; - phy@1 { + swphy1: phy@1 { reg = <1>; mediatek,led-config = < @@ -290,7 +339,7 @@ >; }; - phy@2 { + swphy2: phy@2 { reg = <2>; mediatek,led-config = < @@ -304,7 +353,7 @@ >; }; - phy@3 { + swphy3: phy@3 { reg = <3>; mediatek,led-config = < @@ -318,7 +367,7 @@ >; }; - phy@4 { + swphy4: phy@4 { reg = <4>; mediatek,led-config = < @@ -339,10 +388,12 @@ }; &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; pinctrl-0 = <&wf_2g_5g_pins>; pinctrl-1 = <&wf_dbdc_pins>; + pinctrl-names = "default", "dbdc"; + status = "okay"; }; &trng { diff --git a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts new file mode 100644 index 000000000..891d56853 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "ASUS TUF-AX6000"; + compatible = "asus,tuf-ax6000", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = ""; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + mesh { + label = "wps"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + + led_system: system { + label = "white:system"; + gpios = <&pio 11 GPIO_ACTIVE_HIGH>; + }; + + wan-red { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + cover-blue { + label = "blue:cover"; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + /* LAN */ + compatible = "mediatek,eth-mac"; + reg = <0>; + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + /* WAN */ + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <50000>; + reset-post-delay-us = <20000>; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <5>; + + mxl,led-drive-vdd; + mxl,led-config = <0x03f0 0x0 0x0 0x0>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + + /* LED0: CONN (WAN white) */ + mxl,led-config = <0x03f0 0x0 0x0 0x0>; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + spi_nand_flash: flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + /* + * ASUS bootloader tries to replace the partitions defined in + * Device Tree and by that also deletes all additional properties + * needed for UBI and NVMEM-on-UBI. + * Prevent this from happening by tricking the loader to delete and + * replace a bait node instead. + */ + partitions: dummy { + compatible = "u-boot-dummy-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x0>; + label = "remove_me"; + }; + }; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x400000>; + label = "bootloader"; + read-only; + }; + + partition@400000 { + compatible = "linux,ubi"; + reg = <0x400000 0xfc00000>; + label = "UBI_DEV"; + + volumes { + ubi_factory: ubi-volume-factory { + volname = "Factory"; + }; + }; + }; + }; + }; +}; + +&ubi_factory { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan4"; + phy-handle = <&swphy1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-handle = <&swphy2>; + }; + + port@3 { + reg = <3>; + label = "lan2"; + phy-handle = <&swphy3>; + }; + + port@4 { + reg = <4>; + label = "lan1"; + phy-handle = <&swphy4>; + }; + + port@5 { + reg = <5>; + label = "lan5"; + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + swphy1: phy@1 { + reg = <1>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0x8000 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + swphy2: phy@2 { + reg = <2>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0x8000 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + swphy3: phy@3 { + reg = <3>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0x8000 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + + swphy4: phy@4 { + reg = <4>; + + mediatek,led-config = < + 0x21 0x8009 /* BASIC_CTRL */ + 0x22 0x0c00 /* ON_DURATION */ + 0x23 0x1400 /* BLINK_DURATION */ + 0x24 0x8000 /* LED0_ON_CTRL */ + 0x25 0x0000 /* LED0_BLINK_CTRL */ + 0x26 0xc007 /* LED1_ON_CTRL */ + 0x27 0x003f /* LED1_BLINK_CTRL */ + >; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts new file mode 100644 index 000000000..09a557c0c --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-mini.dts @@ -0,0 +1,715 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 Tianling Shen + */ + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPi-R3 Mini"; + chassis-type = "embedded"; + compatible = "bananapi,bpi-r3-mini", "mediatek,mt7986a"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + + led-boot = &status_led; + led-failsafe = &status_led; + led-running = &status_led; + led-upgrade = &status_led; + }; + + chosen { + stdout-path = "serial0:115200n8"; + rootdisk-emmc = <&emmc_rootdisk>; + rootdisk-spim-nand = <&nand_rootdisk>; + }; + + memory { + reg = <0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_led: led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_WLAN; + color = ; + function-enumerator = <1>; + gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + function = LED_FUNCTION_WLAN; + color = ; + function-enumerator = <2>; + gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <255 128 80 0>; + pwms = <&pwm 0 10000 0>; + status = "okay"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 20 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; +}; + +&auxadc { + status = "okay"; +}; + +&cpu_thermal { + cooling-maps { + cpu-active-low { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-active-med { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-active-high { + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-handle = <&phy14>; + phy-mode = "2500base-x"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy15>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy14: phy@e { + compatible = "ethernet-phy-id03a2.a411"; + reg = <14>; + pinctrl-names = "default"; + pinctrl-0 = <&en8811_pwr_a>; + + airoha,pnswap-rx; + + interrupt-parent = <&pio>; + interrupts = <48 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + + phy-mode = "2500base-x"; + full-duplex; + pause; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + color = ; + }; + }; + }; + + phy15: phy@f { + compatible = "ethernet-phy-id03a2.a411"; + reg = <15>; + pinctrl-names = "default"; + pinctrl-0 = <&en8811_pwr_b>; + + airoha,pnswap-rx; + + interrupt-parent = <&pio>; + interrupts = <46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + + phy-mode = "2500base-x"; + full-duplex; + pause; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = ; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + size = <256>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + emmc_rootdisk: block-partition-production { + partname = "production"; + }; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + en8811_pwr_a: en8811-pwr-a { + pins = "GPIO_11"; + drive-strength = <8>; + mediatek,pull-down-adv = <1>; + output-low; + }; + + en8811_pwr_b: en8811-pwr-b { + pins = "GPIO_12"; + drive-strength = <8>; + mediatek,pull-down-adv = <1>; + output-low; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins-default { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + usb_ngff_pins: usb-ngff-pins { + ngff-gnss-off { + pins = "GPIO_6"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pe-rst { + pins = "GPIO_7"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-wwan-off { + pins = "GPIO_8"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pwr-off { + pins = "GPIO_9"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-rst { + pins = "GPIO_10"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-coex { + pins = "SPI1_CS"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "ubi"; + reg = <0x200000 0x7e00000>; + compatible = "linux,ubi"; + + volumes { + nand_rootdisk: ubi-volume-fit { + volname = "fit"; + }; + }; + }; + }; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + /* conflicts with M.2 pin */ + status = "disabled"; +}; + +&ssusb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_ngff_pins>; + vusb33-supply = <®_3p3v>; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; + status = "okay"; + + mediatek,eeprom-data = <0x86790200 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 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0x40c640c6 + 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 + 0x40c640c6 0x40c640c6 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts index a8c1235cb..fd0e1a691 100644 --- a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts +++ b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts @@ -12,11 +12,12 @@ compatible = "glinet,gl-mt6000", "mediatek,mt7986a"; aliases { - led-boot = &led_run; - led-failsafe = &led_run; - led-running = &led_white; - led-upgrade = &led_run; serial0 = &uart0; + label-mac-device = &gmac1; + led-boot = &led_blue; + led-failsafe = &led_blue; + led-running = &led_white; + led-upgrade = &led_white; }; chosen { @@ -55,13 +56,12 @@ leds { compatible = "gpio-leds"; - led_run: run { + led_blue: led@0 { label = "blue:run"; gpios = <&pio 38 GPIO_ACTIVE_LOW>; - default-state = "on"; }; - led_white: system { + led_white: led@1 { label = "white:system"; gpios = <&pio 37 GPIO_ACTIVE_LOW>; }; @@ -85,6 +85,8 @@ compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "2500base-x"; + nvmem-cells = <&macaddr_factory_a 2>; + nvmem-cell-names = "mac-address"; fixed-link { speed = <2500>; @@ -96,6 +98,8 @@ gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; + nvmem-cells = <&macaddr_factory_a 0>; + nvmem-cell-names = "mac-address"; phy-mode = "2500base-x"; phy-handle = <&phy1>; }; @@ -126,7 +130,7 @@ realtek,aldps-enable; }; - switch: switch@31 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>; @@ -286,6 +290,8 @@ }; &wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; pinctrl-names = "default"; pinctrl-0 = <&wf_2g_5g_pins>; status = "okay"; @@ -307,4 +313,42 @@ no-sd; no-sdio; status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + block-partition-env { + partname = "u-boot-env"; + + nvmem-layout { + compatible = "u-boot,env-layout"; + }; + }; + + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_a: macaddr@a { + compatible = "mac-base"; + reg = <0xa 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; + }; }; diff --git a/target/linux/mediatek/dts/mt7986a-hf-m7986r1-emmc.dts b/target/linux/mediatek/dts/mt7986a-hf-m7986r1-emmc.dts deleted file mode 100644 index eeeb63241..000000000 --- a/target/linux/mediatek/dts/mt7986a-hf-m7986r1-emmc.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include "mt7986a-hf-m7986r1.dtsi" - -/ { - model = "HF-M7986R1 eMMC version"; - compatible = "hf,m7986r1-emmc", "mediatek,mt7986a"; - - chosen { - bootargs = "root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&mmc0 { - bus-width = <8>; - cap-mmc-highspeed; - hs400-ds-delay = <0x14014>; - max-frequency = <200000000>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - no-sd; - no-sdio; - non-removable; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins-default { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; - }; - }; -}; diff --git a/target/linux/mediatek/dts/mt7986a-hf-m7986r1-nand.dts b/target/linux/mediatek/dts/mt7986a-hf-m7986r1-nand.dts deleted file mode 100644 index 7427ec2fa..000000000 --- a/target/linux/mediatek/dts/mt7986a-hf-m7986r1-nand.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include "mt7986a-hf-m7986r1.dtsi" - -/ { - model = "HF-M7986R1 NAND version"; - compatible = "hf,m7986r1-nand", "mediatek,mt7986a"; -}; - -&pio { - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = <8>; - mediatek,pull-down-adv = <0>; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - - spi-max-frequency = <20000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x00000 0x100000>; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "factory"; - reg = <0x180000 0x200000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7a80000>; - }; - }; - }; -}; diff --git a/target/linux/mediatek/dts/mt7986a-hf-m7986r1.dtsi b/target/linux/mediatek/dts/mt7986a-hf-m7986r1.dtsi deleted file mode 100644 index f4c58812c..000000000 --- a/target/linux/mediatek/dts/mt7986a-hf-m7986r1.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include -#include -#include - -#include "mt7986a.dtsi" - -/ { - aliases { - serial0 = &uart0; - led-boot = &sys_led; - led-failsafe = &sys_led; - led-running = &sys_led; - led-upgrade = &sys_led; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - reg = <0 0x40000000 0 0x40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - // seems to conflict with pcie_clk, needs investigate - button-reset { - label = "reset"; - linux,code = ; - gpios = <&pio 9 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - sys_led: led-0 { - label = "hf:sys"; - gpios = <&pio 15 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "led-1"; - gpios = <&pio 16 GPIO_ACTIVE_LOW>; - }; - - led-2 { - label = "led-2"; - gpios = <&pio 17 GPIO_ACTIVE_LOW>; - }; - - led-3 { - label = "led-3"; - gpios = <&pio 18 GPIO_ACTIVE_LOW>; - }; - - led-4 { - label = "led-4"; - gpios = <&pio 19 GPIO_ACTIVE_LOW>; - }; - - led-5 { - label = "led-5"; - gpios = <&pio 20 GPIO_ACTIVE_LOW>; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&mdio { - switch: switch@1f { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - }; - }; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - pcie_pins: pcie-pins { - power-pcie { - pins = "GPIO_7"; - drive-strength = <8>; - mediatek,pull-up-adv = <1>; - }; - - reset-pcie { - pins = "GPIO_9"; - drive-strength = <8>; - mediatek,pull-down-adv = <1>; - output-low; - }; - - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - usb_pins: usb-pins { - reset-sata { - pins = "GPIO_1"; - drive-strength = <8>; - mediatek,pull-up-adv = <1>; - }; - - power-m2 { - pins = "GPIO_6"; - drive-strength = <8>; - mediatek,pull-up-adv = <1>; - }; - - reset-m2 { - pins = "GPIO_8"; - drive-strength = <8>; - mediatek,pull-down-adv = <1>; - output-low; - }; - }; -}; - -&ssusb { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&trng { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cs-05.dts b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts similarity index 65% rename from target/linux/mediatek/dts/mt7986a-jdcloud-re-cs-05.dts rename to target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts index b9ac922d3..372d4ec22 100644 --- a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cs-05.dts +++ b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts @@ -1,59 +1,71 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 Tianling Shen + */ /dts-v1/; #include #include +#include #include "mt7986a.dtsi" / { - model = "JDCloud RE-CS-05"; - compatible = "jdcloud,re-cs-05", "mediatek,mt7986a"; + model = "JDCloud RE-CP-03"; + compatible = "jdcloud,re-cp-03", "mediatek,mt7986a"; aliases { + led-boot = &red_led; + led-failsafe = &red_led; + led-running = &green_led; + led-upgrade = &green_led; serial0 = &uart0; - led-boot = &led_status_green; - led-failsafe = &led_status_red; - led-running = &led_status_blue; - led-upgrade = &led_status_red; }; chosen { + bootargs-override = "root=/dev/fit0 rootwait"; stdout-path = "serial0:115200n8"; - bootargs = "console=ttyS0,115200n8 root=PARTLABEL=rootfs rootwait"; + rootdisk = <&emmc_rootdisk>; }; - keys { + memory@40000000 { + reg = <0 0x40000000 0 0x40000000>; + }; + + gpio-keys { compatible = "gpio-keys"; - reset { + button-joylink { + label = "joylink"; + linux,code = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + button-reset { label = "reset"; linux,code = ; gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 10 GPIO_ACTIVE_LOW>; - }; }; - leds { + gpio-leds { compatible = "gpio-leds"; - led_status_blue: blue { - label = "blue:status"; + led-0 { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 7 GPIO_ACTIVE_HIGH>; }; - led_status_red: red { - label = "red:status"; + red_led: led-1 { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 11 GPIO_ACTIVE_HIGH>; }; - led_status_green: green { - label = "green:status"; + green_led: led-2 { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 12 GPIO_ACTIVE_LOW>; }; }; @@ -89,6 +101,9 @@ reg = <0>; phy-mode = "2500base-x"; + nvmem-cells = <&macaddr_factory_2a 0>; + nvmem-cell-names = "mac-address"; + fixed-link { speed = <2500>; full-duplex; @@ -99,8 +114,11 @@ gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; - phy-handle = <&phy6>; phy-mode = "2500base-x"; + phy-handle = <&phy6>; + + nvmem-cells = <&macaddr_factory_24 0>; + nvmem-cell-names = "mac-address"; }; mdio: mdio-bus { @@ -110,16 +128,17 @@ }; &mdio { - phy6: ethernet-phy@6 { + phy6: phy@6 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <6>; - reset-assert-us = <100000>; - reset-deassert-us = <100000>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; realtek,aldps-enable; }; - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; @@ -130,6 +149,142 @@ }; }; +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + hs400-ds-delay = <0x14014>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + + partitions { + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_24: macaddr@24 { + compatible = "mac-base"; + reg = <0x24 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_2a: macaddr@2a { + compatible = "mac-base"; + reg = <0x2a 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + emmc_rootdisk: block-partition-production { + partname = "production"; + }; + }; + }; + }; +}; + +&pio { + mmc0_pins_default: mmc0-pins-default { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + &switch { ports { #address-cells = <1>; @@ -169,99 +324,6 @@ }; }; -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - cap-mmc-highspeed; - hs400-ds-delay = <0x14014>; - max-frequency = <200000000>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - non-removable; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - &trng { status = "okay"; }; @@ -275,7 +337,9 @@ }; &wifi { - status = "okay"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; pinctrl-names = "default"; pinctrl-0 = <&wf_2g_5g_pins>; + status = "okay"; }; diff --git a/target/linux/mediatek/dts/mt7986a-netcore-n60.dts b/target/linux/mediatek/dts/mt7986a-netcore-n60.dts index 6863aeba0..b96b1e2ec 100644 --- a/target/linux/mediatek/dts/mt7986a-netcore-n60.dts +++ b/target/linux/mediatek/dts/mt7986a-netcore-n60.dts @@ -3,6 +3,7 @@ /dts-v1/; #include #include +#include #include "mt7986a.dtsi" @@ -46,13 +47,15 @@ leds { compatible = "gpio-leds"; - led_status_red: status_red { - label = "red:status"; + led_status_red: status-red { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 29 GPIO_ACTIVE_LOW>; }; - led_status_blue: status_blue { - label = "blue:status"; + led_status_blue: status-blue { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&pio 32 GPIO_ACTIVE_LOW>; }; }; @@ -107,7 +110,7 @@ mxl,led-config = <0x0 0x0 0x0 0x3f0>; }; - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; @@ -145,7 +148,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; @@ -173,10 +175,6 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -270,15 +268,17 @@ }; &factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_lan: macaddr@1fef20 { - reg = <0x1fef20 0x6>; - }; + macaddr_lan: macaddr@1fef20 { + reg = <0x1fef20 0x6>; + }; - macaddr_wan: macaddr@1fef26 { - reg = <0x1fef26 0x6>; + macaddr_wan: macaddr@1fef26 { + reg = <0x1fef26 0x6>; + }; }; }; diff --git a/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts index 4bb983d7c..80b614ac2 100644 --- a/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts +++ b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts @@ -1,15 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; -#include #include +#include #include #include "mt7986a.dtsi" / { - model = "Ruijie RG-X60 Pro"; compatible = "ruijie,rg-x60-pro", "mediatek,mt7986a"; + model = "Ruijie RG-X60 Pro"; aliases { serial0 = &uart0; @@ -23,37 +23,39 @@ bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x11002000"; }; - memory { + memory@40000000 { reg = <0 0x40000000 0 0x20000000>; }; gpio-keys { compatible = "gpio-keys"; - reset { + button-0 { label = "reset"; gpios = <&pio 9 GPIO_ACTIVE_LOW>; linux,code = ; }; - mesh { + button-1 { label = "mesh"; gpios = <&pio 10 GPIO_ACTIVE_LOW>; linux,code = ; }; }; - leds { + leds-gpio { compatible = "gpio-leds"; - led_alarm: status_purple { - label = "purple:status"; - gpios = <&pio 11 GPIO_ACTIVE_LOW>; + led_system: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 22 GPIO_ACTIVE_LOW>; }; - led_system: status_white { - label = "white:status"; - gpios = <&pio 22 GPIO_ACTIVE_LOW>; + led_alarm: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; }; }; }; @@ -65,7 +67,6 @@ compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "2500base-x"; - fixed-link { speed = <2500>; full-duplex; @@ -179,10 +180,20 @@ read-only; }; - factory: partition@180000 { + partition@180000 { label = "Factory"; reg = <0x180000 0x200000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + }; }; partition@380000 { @@ -256,7 +267,8 @@ pinctrl-names = "default"; pinctrl-0 = <&wf_2g_5g_pins>; - mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; }; &uart0 { diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts new file mode 100644 index 000000000..1537fc2c1 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8612"; + compatible = "smartrg,sdg-8612", "mediatek,mt7986a"; +}; + +&gmac0 { + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&gmac1 { + phy-handle = <&phy6>; +}; + +&mdio { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts new file mode 100644 index 000000000..15cfb1f12 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8614"; + compatible = "smartrg,sdg-8614", "mediatek,mt7986a"; + + /* SFP1 cage (WAN) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 62 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 63 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 65 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&pio 28 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 64 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + leds { + compatible = "gpio-leds"; + + sfp_red { + color = ; + function = "sfp"; + function-enumerator = <1>; + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + sfp_green { + color = ; + function = "sfp"; + function-enumerator = <0>; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&mux_sel { + output-low; + /delete-node/ output-high; +}; + +&gmac0 { + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&gmac1 { + sfp = <&sfp1>; + managed = "in-band-status"; +}; + +&mdio { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts new file mode 100644 index 000000000..2c28c8f7b --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8622"; + compatible = "smartrg,sdg-8622", "mediatek,mt7986a"; +}; + +&gmac0 { + phy-handle = <&phy5>; + + label = "lan"; +}; + +&gmac1 { + phy-handle = <&phy6>; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&radio0 { + ieee80211-freq-limit = <5170000 5330000>; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5490000 5835000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts new file mode 100644 index 000000000..bc92f85aa --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8632"; + compatible = "smartrg,sdg-8632", "mediatek,mt7986a"; +}; + +&gmac0 { + phy-handle = <&phy5>; + + label = "lan"; +}; + +&gmac1 { + phy-handle = <&phy6>; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&radio0 { + ieee80211-freq-limit = <5170000 5835000>; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5945000 7125000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi new file mode 100644 index 000000000..038a76ad7 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_white; + led-upgrade = &led_status_blue; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "root=/dev/mmcblk0p5"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /delete-node/ramoops@42ff0000; + + bootdata_reserved: bootdata@45000000 { + no-map; + reg = <0x0 0x45000000 0x0 0x00001000>; + }; + + ramoops_reserved: ramoops@45001000 { + no-map; + compatible = "ramoops"; + reg = <0x0 0x45001000 0x0 0x00140000>; + ftrace-size = <0x20000>; + record-size = <0x20000>; + console-size = <0x20000>; + pmsg-size = <0x80000>; + }; + }; + + bootdata { + compatible = "bootdata"; + memory-region = <&bootdata_reserved>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm 1 40000 0>; + + /** + * set fan speed + * + * 0 = off + * 51 = 20% duty cycle (minimum supported) + * 61 = 24% duty cycle (2020 RPM) + * 77 = 30% duty cycle (3000 RPM) + * 102 = 40% duty cycle (3600 RPM) + * 255 = 100% duty cycle + */ + cooling-levels = <51 61 77 102>; + + interrupt-parent = <&pio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pulses-per-revolution = <2>; + + status = "okay"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&cpu_thermal { + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-medium { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_medium>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-active-silent { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_active_silent>; + }; + }; + + trips { + cpu_trip_active_high: active-high { + temperature = <110000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_medium: active-medium { + temperature = <80000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_silent: active-silent { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + }; + + gmac1: mac@1 { + label = "wan"; + + compatible = "mediatek,eth-mac"; + reg = <1>; + + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + phy5: ethernet-phy@5 { + /* GPY211 */ + compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45"; + reg = <5>; + + mxl,led-drive-vdd; + mxl,led-config = <0x30 0x40 0x80 0x0>; + }; + + phy6: ethernet-phy@6 { + /* GPY211 */ + compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45"; + reg = <6>; + + mxl,led-drive-vdd; + mxl,led-config = <0x30 0x40 0x80 0x0>; + }; +}; + +&crypto { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "disabled"; + + slot0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + radio0: mt7915@0,0 { + reg = <0x0000 0 0 0 0>; + }; + }; +}; + +&pcie_phy { + status = "disabled"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_pereset"; + }; + }; + + button_pins: button-pins { + pins = "GPIO_12"; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_2_rx_tx", "uart1_2_cts_rts"; + }; + }; + + i2c0_pins: i2c0-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + mux_sel: mux-sel-hog { + gpio-hog; + gpios = <23 GPIO_ACTIVE_LOW>; + line-name = "mux-sel"; + output-high; + }; + + mux_oe: mux-oe-hog { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + line-name = "mux-oe"; + output-high; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + + /* DA14531MOD Bluetooth */ + bluetooth { + compatible = "renesas,DA14531"; + reset-gpios = <&pio 27 GPIO_ACTIVE_LOW>; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + system-leds { + compatible = "srg,sysled"; + reg = <0x30>; + + led_status_red: led@1 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <1>; + }; + + led_status_green: led@2 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <2>; + }; + + led_status_blue: led@3 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <3>; + }; + + led_status_white: led@4 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <4>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&watchdog { + interrupts = ; + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi index 65d0eb51b..1649b0775 100644 --- a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include "mt7986a.dtsi" @@ -16,6 +17,8 @@ }; chosen { + bootargs = "root=/dev/fit0 rootwait"; + rootdisk = <&ubi_rootdisk>; stdout-path = "serial0:115200n8"; }; @@ -67,12 +70,14 @@ compatible = "gpio-leds"; led_status_red: status_red { - label = "red:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 7 GPIO_ACTIVE_HIGH>; }; led_status_green: status_green { - label = "green:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&pio 8 GPIO_ACTIVE_HIGH>; }; @@ -95,7 +100,7 @@ reg = <0>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_config_1c>; + nvmem-cells = <&macaddr_config_1c 0>; nvmem-cell-names = "mac-address"; fixed-link { @@ -111,9 +116,8 @@ phy-handle = <&phy7>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_config_1c>; + nvmem-cells = <&macaddr_config_1c 1>; nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; }; mdio: mdio-bus { @@ -130,7 +134,6 @@ reset-deassert-us = <100000>; reset-gpios = <&pio 13 GPIO_ACTIVE_LOW>; realtek,aldps-enable; - realtek,led-link-select = <0xa7 0x0 0x0>; }; phy7: ethernet-phy@7 { @@ -140,10 +143,9 @@ reset-deassert-us = <100000>; reset-gpios = <&pio 17 GPIO_ACTIVE_LOW>; realtek,aldps-enable; - realtek,led-link-select = <0xa7 0x0 0x0>; }; - switch: switch@31 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; @@ -157,7 +159,6 @@ &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; status = "okay"; flash@0 { @@ -185,6 +186,18 @@ label = "config"; reg = <0x100000 0x0060000>; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_1c: macaddr@1c { + compatible = "mac-base"; + reg = <0x1c 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; factory: partition@160000 { @@ -201,13 +214,20 @@ partition@380000 { label = "fip"; - reg = <0x380000 0x0180000>; + reg = <0x380000 0x0200000>; read-only; }; - partition@500000 { + partition@580000 { + compatible = "linux,ubi"; + reg = <0x580000 0x7800000>; label = "ubi"; - reg = <0x500000 0x7300000>; + + volumes { + ubi_rootdisk: ubi-volume-fit { + volname = "fit"; + }; + }; }; }; }; @@ -256,17 +276,7 @@ &wifi { mediatek,mtd-eeprom = <&factory 0x0>; - nvmem-cells = <&macaddr_config_1c>; + nvmem-cells = <&macaddr_config_1c 2>; nvmem-cell-names = "mac-address"; status = "okay"; }; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_1c: macaddr@1c { - reg = <0x1c 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts index 33eca8f17..591d16195 100644 --- a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts @@ -15,22 +15,22 @@ port@0 { reg = <0>; - label = "lan4"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan3"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; - label = "lan1"; + label = "lan4"; }; port@5 { @@ -42,7 +42,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts index 4b757045e..68a159a8e 100644 --- a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts @@ -27,7 +27,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts index 85b5a3db2..751909a6a 100644 --- a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts @@ -15,22 +15,22 @@ port@0 { reg = <0>; - label = "lan4"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan3"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; - label = "lan1"; + label = "lan4"; }; port@5 { @@ -42,7 +42,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xtr8488.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xtr8488.dts deleted file mode 100644 index 7bfcecdfd..000000000 --- a/target/linux/mediatek/dts/mt7986a-tplink-tl-xtr8488.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; -#include "mt7986a-tplink-tl-xdr-common.dtsi" - -/ { - model = "TP-Link TL-XTR8488"; - compatible = "tplink,tl-xtr8488"; - - keys { - reset { - label = "reset"; - linux,code = ; - gpios = <&pio 15 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 16 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - turbo { - label = "green:turbo"; - gpios = <&pio 12 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð { - /delete-node/ mdio-bus; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy5: phy@5 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <5>; - realtek,aldps-enable; - realtek,led-link-select = <0xa7 0x0 0x0>; - }; - - phy7: phy@7 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <7>; - realtek,aldps-enable; - realtek,led-link-select = <0xa7 0x0 0x0>; - }; - - switch: switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan4"; - }; - - port@1 { - reg = <1>; - label = "lan3"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan1"; - }; - - port@5 { - reg = <5>; - label = "lan5"; - phy-handle = <&phy5>; - phy-mode = "2500base-x"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&spi0 { - flash@0 { - /delete-node/ partitions; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x000000 0x0100000>; - read-only; - }; - - config: partition@100000 { - label = "config"; - reg = <0x100000 0x0040000>; - read-only; - }; - - factory: partition@140000 { - label = "factory"; - reg = <0x140000 0x0040000>; - read-only; - }; - - partition@180000 { - label = "reserved"; - reg = <0x180000 0x0180000>; - read-only; - }; - - partition@300000 { - label = "u-boot-env"; - reg = <0x300000 0x0080000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x0200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7800000>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - mediatek,mtd-eeprom = <&factory 0x1000>; - ieee80211-freq-limit = <5470000 5875000>; - - nvmem-cells = <&macaddr_config_1c>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; - }; - }; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - -&wifi { - pinctrl-names = "default"; - pinctrl-0 = <&wf_2g_5g_pins>; -}; - -&config { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_config_1c: macaddr@1c { - reg = <0x1c 0x6>; - }; -}; diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts new file mode 100644 index 000000000..114076dff --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-stock.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" + +/ { + model = "Xiaomi Redmi Router AX6000 (stock layout)"; + compatible = "xiaomi,redmi-router-ax6000-stock", "mediatek,mt7986a"; +}; + +&spi_nand_flash { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + +&partitions { + partition@580000 { + label = "crash"; + reg = <0x580000 0x40000>; + read-only; + }; + + partition@5c0000 { + label = "crash_log"; + reg = <0x5c0000 0x40000>; + read-only; + }; + + partition@600000 { + label = "ubi_kernel"; + reg = <0x600000 0x1e00000>; + }; + + partition@2400000 { + label = "ubi"; + reg = <0x2400000 0x5000000>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts new file mode 100644 index 000000000..f26ab1a88 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000-ubootmod.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7986a-xiaomi-redmi-router-ax6000.dtsi" + +/ { + model = "Xiaomi Redmi Router AX6000 (OpenWrt U-Boot layout)"; + compatible = "xiaomi,redmi-router-ax6000-ubootmod", "mediatek,mt7986a"; +}; + +&chosen { + rootdisk = <&ubi_rootdisk>; + bootargs-append = " root=/dev/fit0 rootwait"; +}; + +&partitions { + partition@580000 { + compatible = "linux,ubi"; + reg = <0x580000 0x7a80000>; + label = "ubi"; + + volumes { + ubi_rootdisk: ubi-volume-fit { + volname = "fit"; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi similarity index 80% rename from target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts rename to target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi index f3f05474e..c26246110 100644 --- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi @@ -8,9 +8,6 @@ #include "mt7986a.dtsi" / { - model = "Xiaomi Redmi Router AX6000"; - compatible = "xiaomi,redmi-router-ax6000", "mediatek,mt7986a"; - aliases { serial0 = &uart0; led-boot = &led_status_rgb; @@ -19,7 +16,7 @@ led-upgrade = &led_status_rgb; }; - chosen { + chosen: chosen { stdout-path = "serial0:115200n8"; }; @@ -57,9 +54,8 @@ reg = <0>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_factory_4>; + nvmem-cells = <&macaddr_factory_4 (-1)>; nvmem-cell-names = "mac-address"; - mac-address-increment = <(-1)>; fixed-link { speed = <2500>; @@ -75,7 +71,7 @@ }; &mdio { - switch: switch@0 { + switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; @@ -132,10 +128,9 @@ &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; status = "okay"; - flash@0 { + spi_nand_flash: flash@0 { compatible = "spi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -145,11 +140,7 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { + partitions: partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -163,13 +154,11 @@ partition@100000 { label = "Nvram"; reg = <0x100000 0x40000>; - read-only; }; partition@140000 { label = "Bdata"; reg = <0x140000 0x40000>; - read-only; }; factory: partition@180000 { @@ -177,12 +166,16 @@ reg = <0x180000 0x200000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; + macaddr_factory_4: macaddr@4 { + compatible = "mac-base"; + reg = <0x4 0x6>; + #nvmem-cell-cells = <1>; + }; }; }; @@ -191,31 +184,6 @@ reg = <0x380000 0x200000>; read-only; }; - - partition@580000 { - label = "crash"; - reg = <0x580000 0x40000>; - read-only; - }; - - partition@5c0000 { - label = "crash_log"; - reg = <0x5c0000 0x40000>; - read-only; - }; - - /* ubi partition is the result of squashing - * consecutive stock partitions: - * - ubi - * - ubi1 - * - overlay - */ - partition@600000 { - label = "ubi"; - reg = <0x600000 0x6e00000>; - }; - - /* last 12 MiB is reserved for NMBM bad block table */ }; }; }; @@ -234,13 +202,18 @@ led_status_rgb: led@0 { reg = <0>; - label = "rgb:status"; + function = LED_FUNCTION_STATUS; + color = ; color-index = ; }; led_network_rgb: led@1 { reg = <1>; - label = "rgb:network"; + + /* Hardcoding here for backward compatibility */ + function = "network"; + + color = ; color-index = ; }; }; @@ -273,7 +246,6 @@ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi new file mode 100644 index 000000000..335ee9398 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include "mt7986a.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_red; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + poll-interval = <20>; + + reset-button { + label = "reset"; + gpios = <&pio 21 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wlan-button { + label = "wlan"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + wps-button { + label = "wps"; + gpios = <&pio 56 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_green_wifi24g { + label = "green:wifi24g"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_green_wifi5g { + label = "green:wifi5g"; + gpios = <&pio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_green_inet { + label = "green:inet"; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_red_inet { + label = "red:inet"; + gpios = <&pio 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_status_green: led_green_pwr { + label = "green:pwr"; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; /* Default blinking */ + led-pattern = <125 125>; /* Fast blink is 4 HZ */ + }; + + led_status_red: led_red_pwr { + label = "red:pwr"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led_green_fxs { + label = "green:fxs"; + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_amber_fxs { + label = "amber:fxs"; + gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_amber_wps24g { + label = "amber:wps24g"; + gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_amber_wps5g { + label = "amber:wps5g"; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_green_lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_green_sfp { + label = "green:sfp"; + gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + spi_nand: spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <10000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + nand_partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy = <&phy6>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <5>; + mxl,led-config = <0x03f0 0x0 0x0 0x0>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + mxl,led-config = <0x00f0 0x0 0x0 0x0>; + }; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + phy-mode = "2500base-x"; + phy = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&crypto { + status = "okay"; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "switch_int", "mdc_mdio"; + }; + }; + + spic_pins_g2: spic-pins-29-to-32 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf_dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + usb-oc-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + input; + line-name = "usb-oc"; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins_g2>; + status = "okay"; + + proslic_spi: proslic_spi@0 { + compatible = "silabs,proslic_spi"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha = <1>; + spi-cpol = <1>; + channel_count = <1>; + debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ + reset_gpio = <&pio 25 GPIO_ACTIVE_HIGH>; + ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; + + /* EFR32MG21 Zigbee (BOOT)*/ +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; + + /* EFR32MG21 Zigbee */ +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts new file mode 100644 index 000000000..4dbbd1367 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" +#include "mt7986a-zyxel-ex5601-t0-common.dtsi" +#include +#include + +/ { + model = "Zyxel EX5601-T0"; + compatible = "zyxel,ex5601-t0", "mediatek,mt7986a-rfb-snand"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; +}; + +&nand_partitions { + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory: eeprom@0 { + #size-cells = <1>; + reg = <0x0 0x1000>; + }; + + macaddr_factory_0004: macaddr@0004 { + compatible = "mac-base"; + reg = <0x0004 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_0024: macaddr@0024 { + compatible = "mac-base"; + reg = <0x0024 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_002a: macaddr@002a { + compatible = "mac-base"; + reg = <0x002a 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x01C0000>; + read-only; + }; + + partition@540000 { + label = "zloader"; + reg = <0x540000 0x0040000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x4000000>; + }; + + partition@4580000 { + label = "ubi2"; + reg = <0x4580000 0x4000000>; + read-only; + }; + + partition@8580000 { + label = "zyubi"; + reg = <0x8580000 0x15A80000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_002a 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_0024 0>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts new file mode 100644 index 000000000..62ce50ed2 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7986a.dtsi" +#include "mt7986a-zyxel-ex5601-t0-common.dtsi" +#include +#include + +/ { + model = "Zyxel EX5601-T0 ubootmod"; + compatible = "zyxel,ex5601-t0-ubootmod", "mediatek,mt7986a"; + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; + +&nand_partitions { + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + read-only; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory: eeprom@0 { + #size-cells = <1>; + reg = <0x0 0x1000>; + }; + + macaddr_factory_0004: macaddr@0004 { + compatible = "mac-base"; + reg = <0x0004 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_0024: macaddr@0024 { + compatible = "mac-base"; + reg = <0x0024 0x6>; + #nvmem-cell-cells = <1>; + }; + + macaddr_factory_002a: macaddr@002a { + compatible = "mac-base"; + reg = <0x002a 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@540000 { + label = "zloader"; + reg = <0x540000 0x0040000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x1da80000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_002a 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&macaddr_factory_0024 0>; + nvmem-cell-names = "mac-address"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory>; + nvmem-cell-names = "eeprom"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts b/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts new file mode 100644 index 000000000..29961e528 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "ZyXEL EX5700 (Telenor)"; + compatible = "zyxel,ex5700-telenor", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + led-boot = &led_status_green; + led-failsafe = &led_status_green; + led-running = &led_status_green; + led-upgrade = &led_status_amber; + }; + + chosen { + stdout-path = "serial0:115200n8"; + + // Stock U-Boot crashes unless /chosen/bootargs exists + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + + keys { + compatible = "gpio-keys"; + poll-interval = <20>; + + reset-button { + label = "reset"; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps-button { + label = "wps"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + red1 { + label = "red:net"; + gpios = <&pio 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green1 { + label = "green:net"; + gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + amber1 { + label = "amber:net"; + gpios = <&pio 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + white2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_status_green: green2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_status_amber: amber2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + label = "wan"; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <50000>; + reset-post-delay-us = <20000>; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <5>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0xa0000>; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_5g_pins>; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "switch_int", "mdc_mdio"; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; // "pcie_clk" and "pcie_wake" is unused? + }; + }; + + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_5g_pins: wf_5g-pins { + mux { + function = "wifi"; + groups = "wf_5g"; + }; + conf { + pins = "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4", + "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7", + "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + + flash@1 { + compatible = "spi-nand"; + reg = <1>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x000000 0x100000>; + read-only; + }; + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + }; + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + partition@580000 { + label = "ubi"; + reg = <0x580000 0x1da80000>; + }; + }; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986b-mercusys-mr90x-v1.dts b/target/linux/mediatek/dts/mt7986b-mercusys-mr90x-v1.dts new file mode 100644 index 000000000..f0a995820 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986b-mercusys-mr90x-v1.dts @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: (GL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986b.dtsi" + +/ { + compatible = "mercusys,mr90x-v1", "mediatek,mt7986b"; + model = "MERCUSYS MR90X v1"; + + aliases { + serial0 = &uart0; + + led-boot = &led_status_green; + led-failsafe = &led_status_green; + led-running = &led_status_green; + led-upgrade = &led_status_green; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + + led_status_green: led-5 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy6>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + /* WAN/LAN 2.5Gbps phy + MaxLinear GPY211C0VC (SLNW8) */ + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* WAN/LAN 1Gbps port */ + port@0 { + reg = <0>; + label = "lan0"; + }; + + /* LAN1 port */ + port@1 { + reg = <1>; + label = "lan1"; + }; + + /* LAN2 port */ + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + spi_nand_flash: flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x200000 0x100000>; + }; + + partition@300000 { + label = "ubi0"; + reg = <0x300000 0x3200000>; + }; + + partition@3500000 { + label = "ubi1"; + reg = <0x3500000 0x3200000>; + read-only; + }; + + partition@6700000 { + label = "userconfig"; + reg = <0x6700000 0x800000>; + read-only; + }; + + partition@6f00000 { + label = "tp_data"; + reg = <0x6f00000 0x400000>; + read-only; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; diff --git a/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts b/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts new file mode 100644 index 000000000..6e51d8847 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986b-netgear-wax220.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986b.dtsi" + +/ { + model = "Netgear WAX220"; + compatible = "netgear,wax220", "mediatek,mt7986b"; + + aliases { + serial0 = &uart0; + led-boot = &led_power_blue; + led-failsafe = &led_power_amber; + led-running = &led_power_green; + led-upgrade = &led_power_amber; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "reset"; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + wlan5g_green { + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + label = "green:wlan5g"; + }; + + led_power_amber: power_amber { + gpios = <&pio 15 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_POWER; + color = ; + }; + + wlan2g_green { + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + label = "green:wlan2g"; + }; + + led_power_blue: power_blue { + gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_POWER; + color = ; + }; + + led_power_green: power_green { + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_POWER; + color = ; + }; + + wlan2g_blue { + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + label = "blue:wlan2g"; + }; + + lan_green { + gpios = <&pio 22 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_LAN; + color = ; + }; + + lan_amber { + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_LAN; + color = ; + }; + + wlan5g_blue { + gpios = <&pio 2 GPIO_ACTIVE_LOW>; + label = "blue:wlan5g"; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy6>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + phy6: ethernet-phy@6 { + reg = <6>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + spi_nand_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <256>; + mediatek,bmt-remap-range = <0x0 0x580000>; + + partitions: partitions { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "fixed-partitions"; + + partition@0 { + label = "BL2"; + read-only; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x5140000>; + }; + + partition@56c0000 { + label = "RAE"; + reg = <0x56c0000 0x400000>; + }; + + partition@5ac0000 { + label = "POT"; + reg = <0x5ac0000 0x100000>; + }; + + partition@5bc0000 { + label = "Language"; + reg = <0x5bc0000 0x400000>; + }; + + partition@5fc0000 { + label = "Traffic"; + reg = <0x5fc0000 0x200000>; + }; + + partition@61c0000 { + label = "Cert"; + reg = <0x61c0000 0x100000>; + }; + + partition@62c0000 { + label = "NTGRcryptK"; + reg = <0x62c0000 0x100000>; + }; + + partition@63c0000 { + label = "NTGRcryptD"; + reg = <0x63c0000 0x500000>; + }; + + partition@68c0000 { + label = "LOG"; + reg = <0x68c0000 0x100000>; + }; + + partition@69c0000 { + label = "User_data"; + reg = <0x69c0000 0x640000>; + }; + }; + }; + +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/dts/mt7986b-tplink-re6000xd.dts b/target/linux/mediatek/dts/mt7986b-tplink-re6000xd.dts new file mode 100644 index 000000000..44a5e21e7 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986b-tplink-re6000xd.dts @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986b.dtsi" + +/ { + compatible = "tplink,re6000xd", "mediatek,mt7986b"; + model = "TP-Link RE6000XD"; + + aliases { + serial0 = &uart0; + + led-boot = &led_status_blue; + led-failsafe = &led_status_blue; + led-running = &led_status_blue; + led-upgrade = &led_status_blue; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_blue: power { + gpios = <&pio 15 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; + panic-indicator; + function-enumerator = <0>; + }; + wlan_2g { + gpios = <&pio 11 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + linux,default-trigger = "phy0tpt"; + }; + wlan_5g { + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + linux,default-trigger = "phy1tpt"; + }; + signal_blue { + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + }; + signal_red { + gpios = <&pio 19 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + }; + lan1 { + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + }; + lan2 { + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + lan3 { + gpios = <&pio 18 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy6>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + /* LAN3 2.5Gbps phy + MaxLinear GPY211C0VC (SLNW8) */ + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + /* reorder LAN1 and LAN2 port to match the port order of the case + LAN1 - LAN2 - LAN3 (top to bottom of the case, no silkscreen) + */ + /* LAN2 port */ + port@1 { + reg = <1>; + label = "lan2"; + }; + + /* LAN1 port */ + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + spi_nand_flash: flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x200000 0x100000>; + }; + + partition@300000 { + label = "ubi0"; + reg = <0x300000 0x3200000>; + }; + + partition@3500000 { + label = "ubi1"; + reg = <0x3500000 0x3200000>; + read-only; + }; + + partition@6700000 { + label = "userconfig"; + reg = <0x6700000 0x800000>; + read-only; + }; + + partition@6f00000 { + label = "tp_data"; + reg = <0x6f00000 0x400000>; + read-only; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8733.dts b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8733.dts new file mode 100644 index 000000000..c8c58271a --- /dev/null +++ b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8733.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7988a-smartrg-mt-stuart.dtsi" + +/ { + model = "SmartRG SDG-8733"; + compatible = "smartrg,sdg-8733", "mediatek,mt7988a"; +}; + +&gmac1 { + phy-connection-type = "usxgmii"; + phy = <&phy0>; +}; diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8734.dts b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8734.dts new file mode 100644 index 000000000..6eeb4993f --- /dev/null +++ b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8734.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7988a-smartrg-mt-stuart.dtsi" + +/ { + model = "SmartRG SDG-8734"; + compatible = "smartrg,sdg-8734", "mediatek,mt7988a"; + + gpio-leds { + compatible = "gpio-leds"; + + sfp_green { + color = ; + function = "sfp"; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + }; + + sfp_red { + color = ; + function = "sfp"; + gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c_sfp1: i2c-gpio-0 { + pinctrl-names = "default"; + pinctrl-0 = <&sfp_i2c_pins>; + + compatible = "i2c-gpio"; + sda-gpios = <&pio 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 32 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 34 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 37 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <4000>; + }; +}; + +&gmac1 { + sfp = <&sfp1>; + managed = "in-band-status"; +}; diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi new file mode 100644 index 000000000..fac267abf --- /dev/null +++ b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi @@ -0,0 +1,682 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 SmartRG Inc. + * Author: Chad Monroe + */ + +/dts-v1/; +#include "mt7988a.dtsi" +#include +#include +#include +#include +#include + +/ { + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + led-boot = &led_sys_green; + led-failsafe = &led_sys_blue; + led-running = &led_sys_white; + led-upgrade = &led_sys_red; + }; + + chosen { + stdout-path = &uart0; + bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf root=PARTLABEL=rootfs"; + }; + + memory { + reg = <0x0 0x40000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /delete-node/ramoops@42ff0000; + + bootdata@45000000 { + no-map; + reg = <0x0 0x45000000 0x0 0x00001000>; + }; + + ramoops_reserved: ramoops@45001000 { + no-map; + compatible = "ramoops"; + reg = <0x0 0x45001000 0x0 0x00140000>; + ftrace-size = <0x20000>; + record-size = <0x20000>; + console-size = <0x20000>; + pmsg-size = <0x80000>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + factory { + label = "reset"; + linux,code = ; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "sync"; + linux,code = ; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + bluetooth_reset { + gpio-export,name = "bt_reset"; + gpio-export,direction_may_change; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + + bluetooth_txrx_ctl { + gpio-export,name = "bt_txrx_ctl"; + gpio-export,direction_may_change; + gpios = <&pio 74 GPIO_ACTIVE_HIGH>; + }; + + gps_enable { + gpio-export,name = "gps_enable"; + gpio-export,output = <1>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + slic_interrupt { + gpio-export,name = "slic_interrupt"; + gpio-export,direction_may_change; + gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + }; + + slic_reset { + gpio-export,name = "slic_reset"; + gpio-export,output = <0>; + gpios = <&pio 72 GPIO_ACTIVE_HIGH>; + }; + + usb_enable { + gpio-export,name = "usb_enable"; + gpio-export,output = <1>; + gpios = <&pio 63 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&cpu0 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply = <&rt5190_buck3>; +}; + +&cci { + proc-supply = <&rt5190_buck3>; +}; + +&cpu_thermal { + /delete-node/cooling-maps; + /delete-node/trips; + + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <110000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <80000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_silent: active-silent { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-med { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-active-silent { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_active_silent>; + }; + }; +}; + +ð { + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fan { + pwms = <&pwm 0 40000 0>; + + /** + * set fan speed + * + * 0 = off + * 61 = 24% duty cycle + * 77 = 30% duty cycle + * 102 = 40% duty cycle + * 128 - 50% duty cycle + * 255 = 100% duty cycle + */ + cooling-levels = <61 77 102 128>; + + interrupt-parent = <&pio>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + pulses-per-revolution = <2>; + + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&gmac1 { + label = "wan"; + status = "okay"; + phy-mode = "usxgmii"; +}; + +&gmac2 { + label = "lan1"; + status = "okay"; + phy-mode = "usxgmii"; + phy-connection-type = "usxgmii"; + phy = <&phy8>; +}; + +&gsw_phy0 { + status = "disabled"; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>, <&gbe1_led1_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1_led1 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>, <&gbe2_led1_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2_led1 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>, <&gbe3_led1_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3_led1 { + status = "okay"; + color = ; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + rt5190a_64: rt5190a@64 { + compatible = "richtek,rt5190a"; + reg = <0x64>; + /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ + vin2-supply = <&rt5190_buck1>; + vin3-supply = <&rt5190_buck1>; + vin4-supply = <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name = "rt5190a-buck1"; + regulator-min-microvolt = <5090000>; + regulator-max-microvolt = <5090000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + buck2 { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + rt5190_buck3: buck3 { + regulator-name = "vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + }; + buck4 { + regulator-name = "rt5190a-buck4"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + ldo { + regulator-name = "rt5190a-ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + + system-leds { + compatible = "srg,sysled"; + reg = <0x30>; + + led_sys_red: system_red { + label = "red"; + reg = <1>; + }; + + led_sys_green: system_green { + label = "green"; + reg = <2>; + }; + + led_sys_blue: system_blue { + label = "blue"; + reg = <3>; + }; + + led_sys_white: system_white { + label = "white"; + reg = <4>; + }; + }; +}; + +&mdio_bus { + phy0: ethernet-phy@0 { + /* AQR113C */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + + reset-gpios = <&pio 62 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <1000000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_WAN; + color = ; + active-low; + }; + }; + }; + + phy8: ethernet-phy@8 { + /* AQR113C */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + + reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <1000000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_LAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_LAN; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_LAN; + color = ; + active-low; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_emmc_51>; + pinctrl-1 = <&mmc0_pins_emmc_51>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + card@0 { + #address-cells = <0>; + #size-cells = <0>; + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + + partitions { + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1e00>; + }; + }; + }; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_1_pins>; + reset-gpios = <&pio 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + mt7996@0,0 { + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>, <5945000 7125000>; + }; + }; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pcie2 { + status = "disabled"; +}; + +&pcie3 { + status = "disabled"; +}; + +&pio { + button_pins: button-pins { + pins = "GPIO_RESET", "GPIO_WPS"; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + + pcie0_1_pins: pcie0-pins-g1 { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1"; + }; + }; + + sfp_i2c_pins: sfp-i2c-pins { + conf-scl { + pins = "LED_A"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + conf-sda { + pins = "LED_E"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "disabled"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; + +}; + +&ssusb0 { + status = "okay"; +}; + +&ssusb1 { + status = "okay"; +}; + +&switch { + status = "okay"; + + ports { + port@0 { + status = "disabled"; + }; + + port@1 { + label = "lan2"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan4"; + }; + }; +}; + +&tphy { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + + /* Airoha AG3352 GPS */ +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; + + /* DA14531MOD Bluetooth */ +}; + +&watchdog { + status = "okay"; +}; + +&xphy { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi deleted file mode 100644 index 2b7131dd1..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ /dev/null @@ -1,801 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Sam.Shih - * Author: Jianhui Zhao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7981"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - }; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ - cooling-levels = <0 128 192 255>; - #cooling-cells = <2>; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* passive: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", - "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; - #io-channel-cells = <1>; - }; - - wdma: wdma@15104800 { - compatible = "mediatek,wed-wdma"; - reg = <0 0x15104800 0 0x400>, - <0 0x15104c00 0 0x400>; - }; - - ap2woccif: ap2woccif@151a5000 { - compatible = "mediatek,ap2woccif"; - reg = <0 0x151a5000 0 0x1000>, - <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = , - ; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@47c80000 { - reg = <0 0x47c80000 0 0x100000>; - no-map; - }; - - wo_emi0: wo-emi@47d80000 { - reg = <0 0x47d80000 0 0x40000>; - no-map; - }; - - wo_data: wo-data@47dc0000 { - reg = <0 0x47dc0000 0 0x240000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - trng { - compatible = "mediatek,mt7981-rng"; - }; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7981-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@1001B000 { - compatible = "mediatek,mt7981-topckgen", "syscon"; - reg = <0 0x1001B000 0 0x1000>; - #clock-cells = <1>; - }; - - apmixedsys: apmixedsys@1001E000 { - compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - clock-frequency = <13000000>; - interrupts = , - , - , - ; - - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>; /* GICR */ - - interrupts = ; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, - <&infracfg CLK_INFRA_I2C_PCK_CK>; - clock-names = "main", "dma", "arb", "pmic"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7981-pcie", - "mediatek,mt7986-pcie"; - device_type = "pci"; - reg = <0 0x11280000 0 0x4000>; - reg-names = "pcie-mac"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 - 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - clocks = <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&topckgen CLK_TOP_EIP97B>; - clock-names = "top_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; - }; - - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, - <0 0x11c00000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rm", - "iocfg_rb", "iocfg_lb", "iocfg_bl", - "iocfg_tm", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 56>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio_pins: mdc-mdio-pins { - mux { - function = "eth"; - groups = "smi_mdc_mdio"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - wifi_dbdc_pins: wifi-dbdc-pins { - mux { - function = "eth"; - groups = "wf0_mode1"; - }; - conf { - pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", - "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", - "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", - "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", - "WF_CBA_RESETB", "WF_DIG_RESETB"; - drive-strength = <4>; - }; - }; - - gbe_led0_pins: gbe-led0-pins { - mux { - function = "led"; - groups = "gbe_led0"; - }; - }; - - gbe_led1_pins: gbe-led1-pins { - mux { - function = "led"; - groups = "gbe_led1"; - }; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7981-ethsys", - "mediatek,mt7986-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - wed: wed@15010000 { - compatible = "mediatek,mt7981-wed", - "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7981-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys0 CLK_SGM0_CK0_EN>, - <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <&sgmiisys1 CLK_SGM1_CK1_EN>, - <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, - <&topckgen CLK_TOP_SGM_REG>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, - <&topckgen CLK_TOP_CB_SGM_325M>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - phy-mode = "gmii"; - phy-is-integrated; - nvmem-cells = <&phy_calibration>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy_led0: int-gbe-phy-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - int_gbe_phy_led1: int-gbe-phy-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - wo_dlm0: syscon@151e8000 { - compatible = "mediatek,mt7986-wo-dlm", "syscon"; - reg = <0 0x151e8000 0 0x2000>; - }; - - wo_ilm0: syscon@151e0000 { - compatible = "mediatek,mt7986-wo-ilm", "syscon"; - reg = <0 0x151e0000 0 0x8000>; - }; - - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; - reg = <0 0x10060000 0 0x1000>; - mediatek,pnswap; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7981-topmisc", "syscon"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - }; - - snand: snfi@11005000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; - reg-names = "nfi", "ecc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, - <&infracfg CLK_INFRA_NFI1_CK>, - <&infracfg CLK_INFRA_NFI_HCK_CK>; - clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, - <&topckgen CLK_TOP_CB_M_D8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - status = "disabled"; - }; - - wed_pcie: wed_pcie@10003000 { - compatible = "mediatek,wed_pcie"; - reg = <0 0x10003000 0 0x10>; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - consys: consys@10000000 { - compatible = "mediatek,mt7981-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - xhci: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - vusb33-supply = <®_3p3v>; - status = "disabled"; - }; - - usb_phy: usb-phy@11e10000 { - compatible = "mediatek,mt7981", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - status = "okay"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - efuse: efuse@11f20000 { - compatible = "mediatek,mt7981-efuse", - "mediatek,efuse"; - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; - - phy_calibration: phy-calib@8dc { - reg = <0x8dc 0x10>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8c8 { - reg = <0x8c8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8c8 { - reg = <0x8c8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8c9 { - reg = <0x8c9 1>; - bits = <2 6>; - }; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, - <&infracfg CLK_INFRA_AUD_26M_CK>, - <&infracfg CLK_INFRA_AUD_L_CK>, - <&infracfg CLK_INFRA_AUD_AUD_CK>, - <&infracfg CLK_INFRA_AUD_EG2_CK>, - <&topckgen CLK_TOP_AUD_SEL>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>, - <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - ice: ice_debug { - compatible = "mediatek,mt7981-ice_debug", - "mediatek,mt2701-ice_debug"; - clocks = <&infracfg CLK_INFRA_DBG_CK>; - clock-names = "ice_dbg"; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - pinctrl-0 = <&wifi_dbdc_pins>; - pinctrl-names = "dbdc"; - clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - status = "disabled"; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso deleted file mode 100644 index 779dc6782..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; -}; - diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso deleted file mode 100644 index 0846d88f6..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Authors: Daniel Golle - * Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "reserved"; - reg = <0x80000 0x300000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7a80000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso deleted file mode 100644 index e48881be4..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Authors: Daniel Golle - * Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@80000 { - label = "reserved2"; - reg = <0x80000 0x80000>; - }; - - partition@100000 { - label = "fip"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "recovery"; - reg = <0x180000 0xa80000>; - }; - - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso deleted file mode 100644 index f623bce07..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - status = "okay"; - }; - }; -}; - diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts deleted file mode 100644 index 1d3c575b7..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Authors: Sam.Shih - * Frank Wunderlich - * Daniel Golle - */ - -/dts-v1/; -#include -#include -#include -#include - -#include "mt7986a.dtsi" - -/ { - model = "Bananapi BPI-R3"; - chassis-type = "embedded"; - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - dcin: regulator-12vd { - compatible = "regulator-fixed"; - regulator-name = "12vd"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - /* cooling level (0, 1, 2) - pwm inverted */ - cooling-levels = <255 96 0>; - pwms = <&pwm 0 10000 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset-key { - label = "reset"; - linux,code = ; - gpios = <&pio 9 GPIO_ACTIVE_LOW>; - }; - - wps-key { - label = "wps"; - linux,code = ; - gpios = <&pio 10 GPIO_ACTIVE_LOW>; - }; - }; - - /* i2c of the left SFP cage (wan) */ - i2c_sfp1: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* i2c of the right SFP cage (lan) */ - i2c_sfp2: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - green_led: led-0 { - color = ; - function = LED_FUNCTION_POWER; - gpios = <&pio 69 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - blue_led: led-1 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&pio 86 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1.8vd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&dcin>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3.3vd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <&dcin>; - }; - - /* left SFP cage (wan) */ - sfp1: sfp-1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - - /* right SFP cage (lan) */ - sfp2: sfp-2 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; -}; - -&cpu_thermal { - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* active: set fan to cooling level 0 */ - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_active_low>; - }; - }; -}; - -&crypto { - status = "okay"; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - sfp = <&sfp1>; - managed = "in-band-status"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&mdio { - switch: switch@31 { - compatible = "mediatek,mt7531"; - reg = <31>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - i2c_pins: i2c-pins { - mux { - function = "i2c"; - groups = "i2c"; - }; - }; - - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_pereset"; - }; - }; - - pwm_pins: pwm-pins { - mux { - function = "pwm"; - groups = "pwm0", "pwm1_0"; - }; - }; - - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spic_pins: spic-pins { - mux { - function = "spi"; - groups = "spi1_0"; - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1_rx_tx"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_0_rx_tx"; - }; - }; - - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf-dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_led_pins: wf-led-pins { - mux { - function = "led"; - groups = "wifi_led"; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins>; - status = "okay"; -}; - -&ssusb { - status = "okay"; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - }; - - port@1 { - reg = <1>; - label = "lan0"; - }; - - port@2 { - reg = <2>; - label = "lan1"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - port5: port@5 { - reg = <5>; - label = "lan4"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&trng { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; - pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; - - led { - led-active-low; - }; -}; - diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts deleted file mode 100644 index ce007099d..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snand"; -}; - -&spi0 { - status = "okay"; - - spi_nand: spi_nand@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts deleted file mode 100644 index ea148315f..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snor"; -}; - -&spi0 { - status = "okay"; - - spi_nor: spi_nor@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - factory: partition@50000 { - label = "Factory"; - reg = <0x50000 0x00B0000>; - }; - partition@100000 { - label = "FIP"; - reg = <0x100000 0x0080000>; - }; - partition@180000 { - label = "firmware"; - reg = <0x180000 0xE00000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi deleted file mode 100644 index b3482f72c..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7986a.dtsi" - -/ { - model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -&mdio { - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - - reset-gpios = <&pio 6 1>; - reset-deassert-us = <20000>; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - - switch: switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 0>; - }; -}; - -&crypto { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - spic_pins_g2: spic-pins-29-to-32 { - mux { - function = "spi"; - groups = "spi1_2"; - }; - }; - - spi_flash_pins: spi-flash-pins-33-to-38 { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = <8>; - mediatek,pull-down-adv = <0>; /* bias-disable */ - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins_g2>; - status = "okay"; - - proslic_spi: proslic_spi@0 { - compatible = "silabs,proslic_spi"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-cpha = <1>; - spi-cpol = <1>; - channel_count = <1>; - debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ - reset_gpio = <&pio 7 0>; - ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ - }; -}; - -&gmac1 { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy-handle = <&phy6>; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "lan6"; - - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi deleted file mode 100644 index 64f2cf375..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ /dev/null @@ -1,645 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7986a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - clk40m: oscillator-40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - enable-method = "psci"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - #cooling-cells = <2>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@4fc00000 { - no-map; - reg = <0 0x4fc00000 0 0x00100000>; - }; - - wo_emi0: wo-emi@4fd00000 { - reg = <0 0x4fd00000 0 0x40000>; - no-map; - }; - - wo_emi1: wo-emi@4fd40000 { - reg = <0 0x4fd40000 0 0x40000>; - no-map; - }; - - wo_ilm0: wo-ilm@151e0000 { - reg = <0 0x151e0000 0 0x8000>; - no-map; - }; - - wo_ilm1: wo-ilm@151f0000 { - reg = <0 0x151f0000 0 0x8000>; - no-map; - }; - - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; - - wo_dlm0: wo-dlm@151e8000 { - reg = <0 0x151e8000 0 0x2000>; - no-map; - }; - - wo_dlm1: wo-dlm@151f8000 { - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; - - wo_boot: wo-boot@15194000 { - reg = <0 0x15194000 0 0x1000>; - no-map; - }; - - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x10000>, /* GICD */ - <0 0x0c080000 0 0x80000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - interrupts = ; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7986-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - wed_pcie: wed-pcie@10003000 { - compatible = "mediatek,mt7986-wed-pcie", - "syscon"; - reg = <0 0x10003000 0 0x10>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7986-topckgen", "syscon"; - reg = <0 0x1001B000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7986-apmixedsys"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7986a-pinctrl"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c30000 0 0x1000>, - <0 0x11c40000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11e30000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", - "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 100>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7986-sgmiisys_0", - "syscon"; - reg = <0 0x10060000 0 0x1000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7986-sgmiisys_1", - "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - trng: rng@1020f000 { - compatible = "mediatek,mt7986-rng", - "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x100>; - clocks = <&infracfg CLK_INFRA_TRNG_CK>; - clock-names = "rng"; - status = "disabled"; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&infracfg CLK_INFRA_EIP97_CK>; - clock-names = "infra_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; - status = "disabled"; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7986-pwm"; - reg = <0 0x10048000 0 0x1000>; - #clock-cells = <1>; - #pwm-cells = <2>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>; - clock-names = "top", "main", "pwm1", "pwm2"; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11008000 { - compatible = "mediatek,mt7986-i2c"; - reg = <0 0x11008000 0 0x90>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <5>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7986-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - ssusb: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>, - <&u2port1 PHY_TYPE_USB2>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>; - clock-names = "source", "hclk", "source_cg", "bus_clk", - "sys_cg"; - status = "disabled"; - }; - - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "therm", "auxadc", "adc_32k"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x00 0x11280000 0x00 0x4000>; - reg-names = "pcie-mac"; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x10000000>; - clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; - status = "disabled"; - - phys = <&pcie_port PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie_phy: t-phy@11c00000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - pcie_port: pcie-phy@11c00000 { - reg = <0 0x11c00000 0 0x20000>; - clocks = <&clk40m>; - clock-names = "ref"; - #phy-cells = <1>; - }; - }; - - efuse: efuse@11d00000 { - compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; - reg = <0 0x11d00000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - thermal_calibration: calib@274 { - reg = <0x274 0xc>; - }; - }; - - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, - <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; - clock-names = "ref", "da_ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u2port1: usb-phy@1000 { - reg = <0x1000 0x700>; - clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, - <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; - clock-names = "ref", "da_ref"; - #phy-cells = <1>; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7986-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - wed0: wed@15010000 { - compatible = "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; - mediatek,wo-ccif = <&wo_ccif0>; - }; - - wed1: wed@15011000 { - compatible = "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; - mediatek,wo-ccif = <&wo_ccif1>; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ccif1: syscon@151ad000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGMII0_TX250M_EN>, - <&sgmiisys0 CLK_SGMII0_RX250M_EN>, - <&sgmiisys0 CLK_SGMII0_CDR_REF>, - <&sgmiisys0 CLK_SGMII0_CDR_FB>, - <&sgmiisys1 CLK_SGMII1_TX250M_EN>, - <&sgmiisys1 CLK_SGMII1_RX250M_EN>, - <&sgmiisys1 CLK_SGMII1_CDR_REF>, - <&sgmiisys1 CLK_SGMII1_CDR_FB>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,wed-pcie = <&wed_pcie>; - mediatek,wed = <&wed0>, <&wed1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7986-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts deleted file mode 100644 index a845c796d..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7986b.dtsi" - -/ { - model = "MediaTek MT7986b RFB"; - compatible = "mediatek,mt7986b-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - reset-gpios = <&pio 6 1>; - reset-deassert-us = <20000>; - phy-mode = "2500base-x"; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - phy-mode = "2500base-x"; - }; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; - }; - }; -}; - -&crypto { - status = "okay"; -}; - -&pio { - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi deleted file mode 100644 index db5189664..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -#include "mt7986a.dtsi" -/ { - compatible = "mediatek,mt7986b"; -}; - -&pio { - compatible = "mediatek,mt7986b-pinctrl"; - gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso deleted file mode 100644 index 3f8ac2ae3..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_emmc_51>; - pinctrl-1 = <&mmc0_pins_emmc_51>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x12814>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_3p3v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso deleted file mode 100644 index d21a61ad1..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso deleted file mode 100644 index 86ab7566d..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&gmac1>; - __overlay__ { - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; - status = "okay"; - }; - }; - - fragment@1 { - target = <&int_2p5g_phy>; - __overlay__ { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso deleted file mode 100644 index 34a23bbd7..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy13>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso deleted file mode 100644 index ba40a119c..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_0_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp1: sfp@1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac1>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp1>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso deleted file mode 100644 index 140391fc4..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy8>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso deleted file mode 100644 index 19e0b2799..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy5>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso deleted file mode 100644 index b9aabd272..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c1>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_sfp_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp0: sfp@0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac2>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso deleted file mode 100644 index 04472cc12..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@1 { - target-path = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_sdcard>; - pinctrl-1 = <&mmc0_pins_sdcard>; - cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-mmc; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso deleted file mode 100644 index 618016517..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&snand>; - __overlay__ { - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; - - fragment@1 { - target = <&bch>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso deleted file mode 100644 index e63436fa5..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi0>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso deleted file mode 100644 index 33bd57b3f..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_flash_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cal-enable; - spi-cal-mode = "read-data"; - spi-cal-datalen = <7>; - spi-cal-data = /bits/ 8 < - 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ - spi-cal-addrlen = <1>; - spi-cal-addr = /bits/ 32 <0x0>; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - partition@50000 { - label = "Factory"; - reg = <0x50000 0x0200000>; - }; - partition@250000 { - label = "FIP"; - reg = <0x250000 0x0080000>; - }; - partition@2D0000 { - label = "firmware"; - reg = <0x2D0000 0x1D30000>; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts deleted file mode 100644 index 11dbf9830..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include - -/ { - model = "MediaTek MT7988A Reference Board"; - compatible = "mediatek,mt7988a-rfb", - "mediatek,mt7988"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; -}; - -&gmac0 { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -ð { - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "disabled"; -}; - -&pcie3 { - status = "okay"; -}; - -&ssusb0 { - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&xphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi deleted file mode 100644 index 7fed1e138..000000000 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ /dev/null @@ -1,1441 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7988"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x0>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x1>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x2>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x3>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - }; - }; - - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - - cci_opp: opp_table_cci { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <660000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <900000>; - }; - }; - - pmu { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupt = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - - interrupts = ; - }; - - phyfw: phy-firmware@f000000 { - compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f000000 0 0x8000>, - <0 0x0f100000 0 0x20000>, - <0 0x0f0f0000 0 0x200>; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7988-wdt", - "mediatek,mt6589-wdt", - "syscon"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl", "syscon"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", - "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 84>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c1_pins: i2c1-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c1_sfp_pins: i2c1-sfp-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_sfp"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2"; - }; - }; - - i2c2_0_pins: i2c2-pins-g0 { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2c2_1_pins: i2c2-pins-g1 { - mux { - function = "i2c"; - groups = "i2c2_1"; - }; - }; - - gbe0_led0_pins: gbe0-led0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-led0-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-led0-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-led0-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - gbe0_led1_pins: gbe0-led1-pins { - mux { - function = "led"; - groups = "gbe0_led1"; - }; - }; - - gbe1_led1_pins: gbe1-led1-pins { - mux { - function = "led"; - groups = "gbe1_led1"; - }; - }; - - gbe2_led1_pins: gbe2-led1-pins { - mux { - function = "led"; - groups = "gbe2_led1"; - }; - }; - - gbe3_led1_pins: gbe3-led1-pins { - mux { - function = "led"; - groups = "gbe3_led1"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - - i2p5gbe_led1_pins: 2p5gbe-led1-pins { - mux { - function = "led"; - groups = "2p5gbe_led1"; - }; - }; - - mmc0_pins_emmc_45: mmc0-pins-emmc-45 { - mux { - function = "flash"; - groups = "emmc_45"; - }; - }; - - mmc0_pins_emmc_51: mmc0-pins-emmc-51 { - mux { - function = "flash"; - groups = "emmc_51"; - }; - }; - - mmc0_pins_sdcard: mmc0-pins-sdcard { - mux { - function = "flash"; - groups = "sdcard"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - snfi_pins: snfi-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spi0_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0"; - }; - }; - - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spi1_pins: spi1-pins { - mux { - function = "spi"; - groups = "spi1"; - }; - }; - - spi2_pins: spi2-pins { - mux { - function = "spi"; - groups = "spi2"; - }; - }; - - spi2_flash_pins: spi2-flash-pins { - mux { - function = "spi"; - groups = "spi2", "spi2_wp_hold"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_0", - "syscon"; - reg = <0 0x10060000 0 0x1000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_1", - "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - usxgmiisys0: usxgmiisys@10080000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_0", - "syscon"; - reg = <0 0x10080000 0 0x1000>; - #clock-cells = <1>; - }; - - usxgmiisys1: usxgmiisys@10081000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_1", - "syscon"; - reg = <0 0x10081000 0 0x1000>; - #clock-cells = <1>; - }; - - xfi_pextp0: xfi-pextp@11f20000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_0", - "syscon"; - reg = <0 0x11f20000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pextp1: xfi-pextp@11f30000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_1", - "syscon"; - reg = <0 0x11f30000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pll: xfi-pll@11f40000 { - compatible = "mediatek,mt7988-xfi-pll", "syscon"; - reg = <0 0x11f40000 0 0x1000>; - #clock-cells = <1>; - }; - - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@11000000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - - snand: spi@11001000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11001000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI>, - <&infracfg CLK_INFRA_NFI>; - clock-names = "pad_clk", "nfi_clk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, - <&topckgen CLK_TOP_MPLL_D8>; - nand-ecc-engine = <&bch>; - mediatek,quad-spi; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&snfi_pins>; - status = "disabled"; - }; - - bch: ecc@11002000 { - compatible = "mediatek,mt7686-ecc"; - reg = <0 0x11002000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI1X_SEL>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - i2c0: i2c@11003000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11004000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11005000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@11007000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11007000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI0>, - <&infracfg CLK_INFRA_66M_SPI0_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11008000 { - compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm"; - reg = <0 0x11008000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI1>, - <&infracfg CLK_INFRA_66M_SPI1_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI2_BCK>, - <&infracfg CLK_INFRA_66M_SPI2_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ - cooling-levels = <0 128 255>; - #cooling-cells = <2>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts"; - #thermal-sensor-cells = <1>; - reg = <0 0x1100a000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; - clock-names = "lvts_clk"; - nvmem-cells = <&lvts_calibration>; - nvmem-cell-names = "e_data1"; - }; - - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, - <&infracfg CLK_INFRA_AUD_26M>, - <&infracfg CLK_INFRA_AUD_L>, - <&infracfg CLK_INFRA_AUD_AUD>, - <&infracfg CLK_INFRA_AUD_EG2>, - <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_AUD_I2S_M>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel", - "aud_i2s_m"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>, - <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - pcie2: pcie@11280000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11280000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <3>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x00200000>, - <0x82000000 0x00 0x20200000 0x00 - 0x20200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "disabled"; - - phys = <&xphyu3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, - <0 0 0 2 &pcie_intc2 1>, - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - pcie_intc2: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie3: pcie@11290000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11290000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x28000000 0x00 - 0x28000000 0x00 0x00200000>, - <0x82000000 0x00 0x28200000 0x00 - 0x28200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc3 0>, - <0 0 0 2 &pcie_intc3 1>, - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - pcie_intc3: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie0: pcie@11300000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11300000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <0>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x30000000 0x00 - 0x30000000 0x00 0x00200000>, - <0x82000000 0x00 0x30200000 0x00 - 0x30200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie1: pcie@11310000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11310000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <1>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x38000000 0x00 - 0x38000000 0x00 0x00200000>, - <0x82000000 0x00 0x38200000 0x00 - 0x38200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11D60000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC400>, - <&infracfg CLK_INFRA_MSDC2_HCK>, - <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, - <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, - <&apmixedsys CLK_APMIXED_MSDCPLL>; - clock-names = "source", - "hclk", - "axi_cg", - "ahb_cg"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tphy: tphy@11c50000 { - compatible = "mediatek,mt7988", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; - clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - }; - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; - clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,usb3-pll-ssc-delta; - mediatek,usb3-pll-ssc-delta1; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7988-topmisc", "syscon", - "mediatek,mt7988-power-controller"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - xphy: xphy@11e10000 { - compatible = "mediatek,mt7988", - "mediatek,xsphy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; - clocks = <&infracfg CLK_INFRA_USB_UTMI>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; - clocks = <&infracfg CLK_INFRA_USB_PIPE>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - }; - }; - - efuse: efuse@11f50000 { - compatible = "mediatek,efuse"; - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; - phy_calibration_p0: calib@940 { - reg = <0x940 0x10>; - }; - phy_calibration_p1: calib@954 { - reg = <0x954 0x10>; - }; - phy_calibration_p2: calib@968 { - reg = <0x968 0x10>; - }; - phy_calibration_p3: calib@97c { - reg = <0x97c 0x10>; - }; - cpufreq_calibration: calib@278 { - reg = <0x278 0x1>; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - switch: switch@15020000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7988-switch"; - reg = <0 0x15020000 0 0x8000>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - resets = <ðrst 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy0_led0: gsw-phy0-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy0_led1: gsw-phy0-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy1_led0: gsw-phy1-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy1_led1: gsw-phy1-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy2_led0: gsw-phy2-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy2_led1: gsw-phy2-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy3_led0: gsw-phy3-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy3_led1: gsw-phy3-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - ethwarp: syscon@15031000 { - compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - - ethrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) - >; - }; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7988-eth"; - reg = <0 0x15100000 0 0x80000>, - <0 0x15400000 0 0x380000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETHDMA_XGP1_EN>, - <ðsys CLK_ETHDMA_XGP2_EN>, - <ðsys CLK_ETHDMA_XGP3_EN>, - <ðsys CLK_ETHDMA_FE_EN>, - <ðsys CLK_ETHDMA_GP2_EN>, - <ðsys CLK_ETHDMA_GP1_EN>, - <ðsys CLK_ETHDMA_GP3_EN>, - <ðsys CLK_ETHDMA_ESW_EN>, - <ðsys CLK_ETHDMA_CRYPT0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <ðwarp CLK_ETHWARP_WOCPU2_EN>, - <ðwarp CLK_ETHWARP_WOCPU1_EN>, - <ðwarp CLK_ETHWARP_WOCPU0_EN>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>, - <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>, - <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>, - <&topckgen CLK_TOP_ETH_GMII_SEL>, - <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_SEL>, - <&topckgen CLK_TOP_ETH_XGMII_SEL>, - <&topckgen CLK_TOP_ETH_MII_SEL>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>, - <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_WARP_SEL>; - clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", - "gp3", "esw", "crypto", "sgmii_tx250m", - "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", - "ethwarp_wocpu2", "ethwarp_wocpu1", - "ethwarp_wocpu0", "top_usxgmii0_sel", - "top_usxgmii1_sel", "top_sgm0_sel", - "top_sgm1_sel", "top_xfi_phy0_xtal_sel", - "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", - "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", - "top_eth_sys_sel", "top_eth_xgmii_sel", - "top_eth_mii_sel", "top_netsys_sel", - "top_netsys_500m_sel", "top_netsys_pao_2x_sel", - "top_netsys_sync_250m_sel", - "top_netsys_ppefb_250m_sel", - "top_netsys_warp_sel"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_GSW_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&topckgen CLK_TOP_NET1PLL_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&apmixedsys CLK_APMIXED_SGMPLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; - mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>; - mediatek,xfi-pll = <&xfi_pll>; - mediatek,infracfg = <&topmisc>; - mediatek,toprgu = <&watchdog>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - status = "disabled"; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - status = "disabled"; - }; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* internal 2.5G PHY */ - int_2p5g_phy: ethernet-phy@15 { - reg = <15>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c deleted file mode 100644 index 1647021de..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -#define MT7981_PLL_FMAX (2500UL * MHZ) -#define CON0_MT7981_RST_BAR BIT(27) - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - _div_table, _parent_name) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, .div_table = _div_table, \ - .parent_name = _parent_name, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ - _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ - "clkxtal") - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, - 32, 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, - 0x0210, 4, 0, 0x0214, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, - 0x0220, 4, 0, 0x0224, 0), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, - 0x0230, 4, 0, 0x0234, 0), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, - 0x0240, 4, 0, 0x0244, 0), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, - 0x0250, 4, 0, 0x0254, 0), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, - 0x0260, 4, 0, 0x0264, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, - 0x0278, 4, 0, 0x027C, 0), -}; - -static const struct of_device_id of_match_clk_mt7981_apmixed[] = { - { .compatible = "mediatek,mt7981-apmixedsys", }, - {} -}; - -static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7981_apmixed_drv = { - .probe = clk_mt7981_apmixed_probe, - .driver = { - .name = "clk-mt7981-apmixed", - .of_match_table = of_match_clk_mt7981_apmixed, - }, -}; -builtin_platform_driver(clk_mt7981_apmixed_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c deleted file mode 100644 index 4aba657aa..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-eth.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#include -#include -#include -#include -#include - -#include "clk-mtk.h" -#include "clk-gate.h" - -#include - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xE4, - .clr_ofs = 0xE4, - .sta_ofs = 0xE4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] __initconst = { - GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), - GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), - GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), - GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xE4, - .clr_ofs = 0xE4, - .sta_ofs = 0xE4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] __initconst = { - GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), - GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), - GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), - GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), -}; - -static const struct mtk_gate_regs eth_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = ð_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate eth_clks[] __initconst = { - GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), - GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), - GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), - GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), -}; - -static void __init mtk_sgmiisys_0_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0", - mtk_sgmiisys_0_init); - -static void __init mtk_sgmiisys_1_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1", - mtk_sgmiisys_1_init); - -static void __init mtk_ethsys_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c deleted file mode 100644 index 8416829e3..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7981_clk_lock); - -static const struct mtk_fixed_factor infra_divs[] = { - FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), -}; - -static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", - "uart_sel" }; - -static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", - "spim_mst_sel" }; - -static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; - -static const char *const infra_pwm_bsel_parents[] __initconst = { - "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" -}; - -static const char *const infra_pcie_parents[] __initconst = { - "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", - infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", - infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", - infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", - infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", - infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", - infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", - infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, - -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), - GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), - GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), - GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), - GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), - GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), - - GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), - GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), - GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), - GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), - GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", - 14), - GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), - GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), - GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), - GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), - GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), - GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), - GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), - GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), - GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), - GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), - GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), - GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), - GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), - GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), - GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), - GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), - GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", - 13), - GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", - 14), - GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), - GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), - GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), - GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), - GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), - GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), - GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), - GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), - GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), - GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), - GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), - GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), - GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), - GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), - GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", - 13), - GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), - GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), -}; - -static int clk_mt7981_infracfg_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + - ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7981_clk_lock, clk_data); - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7981_infracfg[] = { - { .compatible = "mediatek,mt7981-infracfg", }, - {} -}; - -static struct platform_driver clk_mt7981_infracfg_drv = { - .probe = clk_mt7981_infracfg_probe, - .driver = { - .name = "clk-mt7981-infracfg", - .of_match_table = of_match_clk_mt7981_infracfg, - }, -}; -builtin_platform_driver(clk_mt7981_infracfg_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c deleted file mode 100644 index ce6dc1867..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ /dev/null @@ -1,450 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - * Author: Jianhui Zhao - */ - - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7981_clk_lock); - -static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), - FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), - FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), - FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), - FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), - FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), - FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), - FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), - FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), - FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), - FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), - FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), - FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), - FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), - FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), - FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), - FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), - FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), - FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), - FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), - FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), - FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), - FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), - FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), - FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), - FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), - FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), - FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), - FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), - FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), - FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), - FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), - FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), - FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), - FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), - FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), - FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), - FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), - FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), - FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), - FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), - FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), - FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), - FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), - FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), - FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), - FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), - FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), - FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), - FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), - FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), - FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), - FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), - FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), - FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), -}; - -static const char * const nfi1x_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_d4", - "net1_d8_d2", - "cb_net2_d6", - "cb_m_d4", - "cb_mm_d8", - "net1_d8_d4", - "cb_m_d8" -}; - -static const char * const spinfi_parents[] __initconst = { - "cksq_40m_d2", - "cb_cksq_40m", - "net1_d5_d4", - "cb_m_d4", - "cb_mm_d8", - "net1_d8_d4", - "mm_d6_d2", - "cb_m_d8" -}; - -static const char * const spi_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d2", - "cb_mm_d4", - "net1_d8_d2", - "cb_net2_d6", - "net1_d5_d4", - "cb_m_d4", - "net1_d8_d4" -}; - -static const char * const uart_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d8", - "m_d8_d2" -}; - -static const char * const pwm_parents[] __initconst = { - "cb_cksq_40m", - "net1_d8_d2", - "net1_d5_d4", - "cb_m_d4", - "m_d8_d2", - "cb_rtc_32k" -}; - -static const char * const i2c_parents[] __initconst = { - "cb_cksq_40m", - "net1_d5_d4", - "cb_m_d4", - "net1_d8_d4" -}; - -static const char * const pextp_tl_ck_parents[] __initconst = { - "cb_cksq_40m", - "net1_d5_d4", - "cb_m_d4", - "cb_rtc_32k" -}; - -static const char * const emmc_208m_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d2", - "cb_net2_d4", - "cb_apll2_196m", - "cb_mm_d4", - "net1_d8_d2", - "cb_mm_d6" -}; - -static const char * const emmc_400m_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_d2", - "cb_mm_d2", - "cb_net2_d2" -}; - -static const char * const csw_f26m_parents[] __initconst = { - "cksq_40m_d2", - "m_d8_d2" -}; - -static const char * const dramc_md32_parents[] __initconst = { - "cb_cksq_40m", - "cb_m_d2", - "cb_wedmcu_208m" -}; - -static const char * const sysaxi_parents[] __initconst = { - "cb_cksq_40m", - "net1_d8_d2" -}; - -static const char * const sysapb_parents[] __initconst = { - "cb_cksq_40m", - "m_d3_d2" -}; - -static const char * const arm_db_main_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_d6" -}; - -static const char * const ap2cnn_host_parents[] __initconst = { - "cb_cksq_40m", - "net1_d8_d4" -}; - -static const char * const netsys_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_d2" -}; - -static const char * const netsys_500m_parents[] __initconst = { - "cb_cksq_40m", - "cb_net1_d5" -}; - -static const char * const netsys_mcu_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_720m", - "cb_net1_d4", - "cb_net1_d5", - "cb_m_416m" -}; - -static const char * const netsys_2x_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_800m", - "cb_mm_720m" -}; - -static const char * const sgm_325m_parents[] __initconst = { - "cb_cksq_40m", - "cb_sgm_325m" -}; - -static const char * const sgm_reg_parents[] __initconst = { - "cb_cksq_40m", - "cb_net2_d4" -}; - -static const char * const eip97b_parents[] __initconst = { - "cb_cksq_40m", - "cb_net1_d5", - "cb_m_416m", - "cb_mm_d2", - "net1_d5_d2" -}; - -static const char * const aud_parents[] __initconst = { - "cb_cksq_40m", - "cb_apll2_196m" -}; - -static const char * const a1sys_parents[] __initconst = { - "cb_cksq_40m", - "apll2_d4" -}; - -static const char * const aud_l_parents[] __initconst = { - "cb_cksq_40m", - "cb_apll2_196m", - "m_d8_d2" -}; - -static const char * const a_tuner_parents[] __initconst = { - "cb_cksq_40m", - "apll2_d4", - "m_d8_d2" -}; - -static const char * const u2u3_parents[] __initconst = { - "cb_cksq_40m", - "m_d8_d2" -}; - -static const char * const u2u3_sys_parents[] __initconst = { - "cb_cksq_40m", - "net1_d5_d4" -}; - -static const char * const usb_frmcnt_parents[] __initconst = { - "cb_cksq_40m", - "cb_mm_d3_d5" -}; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, - 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, - 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, - 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, - 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", - pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, - 0x1C0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", - emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, - 0x1C0, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", - emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, - 0x1C0, 9), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", - csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", - csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, - 31, 0x1C0, 11, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, - 7, 0x1C0, 12, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", - sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, - 0x1C0, 13, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", - sysapb_parents, 0x030, 0x034, 0x038, 16, 1, - 23, 0x1C0, 14, - CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, - 0x1C0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", - ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, - 0x1C0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, - 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, - 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, - 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, - 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", - csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, - 7, 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, - 0x064, 0x068, 8, 1, 15, 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", - a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, - 0x074, 0x078, 8, 1, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", - u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, - 0x1C0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", - u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, - 0x1C4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", - usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, - 0x1C4, 1), -}; - -static struct mtk_composite top_aud_divs[] = { - DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", - 0x0420, 0, 0x0420, 8, 8), -}; - -static int clk_mt7981_topckgen_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) + - ARRAY_SIZE(top_aud_divs); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7981_clk_lock, clk_data); - mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base, - &mt7981_clk_lock, clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7981_topckgen[] = { - { .compatible = "mediatek,mt7981-topckgen", }, - {} -}; - -static struct platform_driver clk_mt7981_topckgen_drv = { - .probe = clk_mt7981_topckgen_probe, - .driver = { - .name = "clk-mt7981-topckgen", - .of_match_table = of_match_clk_mt7981_topckgen, - }, -}; -builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c deleted file mode 100644 index 76c8ebdea..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -#define MT7986_PLL_FMAX (2500UL * MHZ) -#define CON0_MT7986_RST_BAR BIT(27) - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - _div_table, _parent_name) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, .div_table = _div_table, \ - .parent_name = _parent_name, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ - _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ - "clkxtal") - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32, - 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, - 0x0210, 4, 0, 0x0214, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, - 0x0220, 4, 0, 0x0224, 0), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32, - 0x0230, 4, 0, 0x0234, 0), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0, - 32, 0x0240, 4, 0, 0x0244, 0), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32, - 0x0250, 4, 0, 0x0254, 0), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260, - 4, 0, 0x0264, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, - 0x0278, 4, 0, 0x027c, 0), -}; - -static const struct of_device_id of_match_clk_mt7986_apmixed[] = { - { .compatible = "mediatek,mt7986-apmixedsys", }, - {} -}; - -static int clk_mt7986_apmixed_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7986_apmixed_drv = { - .probe = clk_mt7986_apmixed_probe, - .driver = { - .name = "clk-mt7986-apmixed", - .of_match_table = of_match_clk_mt7986_apmixed, - }, -}; -builtin_platform_driver(clk_mt7986_apmixed_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c deleted file mode 100644 index ed2e7b200..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-eth.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include - -#include "clk-mtk.h" -#include "clk-gate.h" - -#include - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] __initconst = { - GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), - GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), - GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), - GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] __initconst = { - GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), - GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), - GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), - GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5), -}; - -static const struct mtk_gate_regs eth_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETH(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ð_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate eth_clks[] __initconst = { - GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), - GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), - GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), - GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14), - GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), -}; - -static void __init mtk_sgmiisys_0_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0", - mtk_sgmiisys_0_init); - -static void __init mtk_sgmiisys_1_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1", - mtk_sgmiisys_1_init); - -static void __init mtk_ethsys_init(struct device_node *node) -{ - struct clk_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c deleted file mode 100644 index 82279dfcf..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7986_clk_lock); - -static const struct mtk_fixed_factor infra_divs[] = { - FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2), -}; - -static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", - "uart_sel" }; - -static const char *const infra_spi_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_pwm_bsel_parents[] __initconst = { - "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel" -}; - -static const char *const infra_pcie_parents[] __initconst = { - "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", - infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", - infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", - infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1, - -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", - infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", - infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, - -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0), - GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1), - GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), - GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), - GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), - GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6), - GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7), - GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8), - GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10), - GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11), - GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13), - GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", - 14), - GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15), - GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16), - GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24), - GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), - GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), - GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1), - GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), - GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), - GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), - GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8), - GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9), - GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2", - 10), - GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), - GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), - GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2", - 13), - GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2", - 14), - GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15), - GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16), - GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel", - 17), - GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel", - 18), - GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2", - 19), - GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), - GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21), - GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0), - GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2", - 1), - GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2), - GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3), - GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12), - GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal", - 13), - GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14), - GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15), -}; - -static int clk_mt7986_infracfg_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + - ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; - -} - -static const struct of_device_id of_match_clk_mt7986_infracfg[] = { - { .compatible = "mediatek,mt7986-infracfg", }, - {} -}; - -static struct platform_driver clk_mt7986_infracfg_drv = { - .probe = clk_mt7986_infracfg_probe, - .driver = { - .name = "clk-mt7986-infracfg", - .of_match_table = of_match_clk_mt7986_infracfg, - }, -}; -builtin_platform_driver(clk_mt7986_infracfg_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c deleted file mode 100644 index 8550e2be7..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ /dev/null @@ -1,342 +0,0 @@ -// SPDX-License-Identifier: GPL-1.0 -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - * Author: Wenzhen Yu - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" - -#include -#include - -static DEFINE_SPINLOCK(mt7986_clk_lock); - -static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), - FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), -}; - -static const struct mtk_fixed_factor top_divs[] = { - /* XTAL */ - FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), - FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), - FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), - /* MPLL */ - FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), - /* MMPLL */ - FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), - FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), - FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), - /* APLL2 */ - FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), - /* NET1PLL */ - FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), - /* NET2PLL */ - FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), - FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), - /* WEDMCUPLL */ - FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, - 10), -}; - -static const char *const nfi1x_parents[] __initconst = { "top_xtal", - "top_mmpll_d8", - "top_net1pll_d8_d2", - "top_net2pll_d3_d2", - "top_mpll_d4", - "top_mmpll_d8_d2", - "top_wedmcupll_d5_d2", - "top_mpll_d8" }; - -static const char *const spinfi_parents[] __initconst = { - "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", - "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", - "top_mmpll_d3_d8", "top_mpll_d8" -}; - -static const char *const spi_parents[] __initconst = { - "top_xtal", "top_mpll_d2", "top_mmpll_d8", - "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", - "top_mpll_d4", "top_wedmcupll_d5_d2" -}; - -static const char *const uart_parents[] __initconst = { "top_xtal", - "top_mpll_d8", - "top_mpll_d8_d2" }; - -static const char *const pwm_parents[] __initconst = { - "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" -}; - -static const char *const i2c_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" -}; - -static const char *const pextp_tl_ck_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" -}; - -static const char *const emmc_250m_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d2" -}; - -static const char *const emmc_416m_parents[] __initconst = { "top_xtal", - "mpll" }; - -static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", - "top_mpll_d8_d2" }; - -static const char *const dramc_md32_parents[] __initconst = { "top_xtal", - "top_mpll_d2" }; - -static const char *const sysaxi_parents[] __initconst = { "top_xtal", - "top_net1pll_d8_d2", - "top_net2pll_d4" }; - -static const char *const sysapb_parents[] __initconst = { "top_xtal", - "top_mpll_d3_d2", - "top_net2pll_d4_d2" }; - -static const char *const arm_db_main_parents[] __initconst = { - "top_xtal", "top_net2pll_d3_d2" -}; - -static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", - "top_xtal" }; - -static const char *const netsys_parents[] __initconst = { "top_xtal", - "top_mmpll_d4" }; - -static const char *const netsys_500m_parents[] __initconst = { - "top_xtal", "top_net1pll_d5" -}; - -static const char *const netsys_mcu_parents[] __initconst = { - "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", - "top_net1pll_d5" -}; - -static const char *const netsys_2x_parents[] __initconst = { - "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" -}; - -static const char *const sgm_325m_parents[] __initconst = { "top_xtal", - "sgmpll" }; - -static const char *const sgm_reg_parents[] __initconst = { - "top_xtal", "top_net1pll_d8_d4" -}; - -static const char *const a1sys_parents[] __initconst = { "top_xtal", - "top_apll2_d4" }; - -static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", - "top_mmpll_d2" }; - -static const char *const eip_b_parents[] __initconst = { "top_xtal", - "net2pll" }; - -static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", - "top_mpll_d8_d2" }; - -static const char *const a_tuner_parents[] __initconst = { "top_xtal", - "top_apll2_d4", - "top_mpll_d8_d2" }; - -static const char *const u2u3_sys_parents[] __initconst = { - "top_xtal", "top_net1pll_d5_d4" -}; - -static const char *const da_u2_refsel_parents[] __initconst = { - "top_xtal", "top_mmpll_u2phy" -}; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, - 0x004, 0x008, 16, 3, 23, 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, - 0x014, 0x018, 0, 2, 7, 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, - 0x014, 0x018, 8, 2, 15, 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, - 0x014, 0x018, 16, 2, 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", - pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, - 31, 0x1C0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", - emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, - 0x1C0, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", - emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, - 0x1C0, 9), - MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", - f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, - 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, - 0x1C0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, - 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, - 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, - 31, 0x1C0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", - arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, - 0x1C0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, - 23, 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, - 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", - sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, - 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", - conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, - 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, - 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", - f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, - 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", - f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, - 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", - f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", - a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, - 0x1C0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, - 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", - u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, - 0x1C4, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", - u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, - 0x1C4, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", - da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, - 23, 0x1C4, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", - da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, - 31, 0x1C4, 4), - /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", - sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, - 0x1C4, 5), -}; - -static int clk_mt7986_topckgen_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + - ARRAY_SIZE(top_muxes); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - - clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]); - clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7986_topckgen[] = { - { .compatible = "mediatek,mt7986-topckgen", }, - {} -}; - -static struct platform_driver clk_mt7986_topckgen_drv = { - .probe = clk_mt7986_topckgen_probe, - .driver = { - .name = "clk-mt7986-topckgen", - .of_match_table = of_match_clk_mt7986_topckgen, - }, -}; -builtin_platform_driver(clk_mt7986_topckgen_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c deleted file mode 100644 index 587b70767..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -#define MT7988_PLL_FMAX (2500UL * MHZ) -#define MT7988_PCW_CHG_SHIFT 2 - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \ - _div_table) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \ - .div_table = _div_table, .parent_name = "clkxtal", \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL) - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, - 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, - 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, - 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, - 0x0154), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, - 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, - 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174), - PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, - 0x0204), - PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), - PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, - 32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314), -}; - -static const struct of_device_id of_match_clk_mt7988_apmixed[] = { - { - .compatible = "mediatek,mt7988-apmixedsys", - }, - {} -}; - -static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7988_apmixed_drv = { - .probe = clk_mt7988_apmixed_probe, - .driver = { - .name = "clk-mt7988-apmixed", - .of_match_table = of_match_clk_mt7988_apmixed, - }, -}; -builtin_platform_driver(clk_mt7988_apmixed_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c deleted file mode 100644 index 341d0f73f..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include - -static const struct mtk_gate_regs ethdma_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETHDMA(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðdma_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethdma_clks[] = { - GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), - GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), - GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), - GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), - GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), - GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), - GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), - GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), - GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", - 29), -}; - -static int clk_mt7988_ethsys_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] = { - GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), - GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), -}; - -static int clk_mt7988_sgmii0_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] = { - GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), - GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), -}; - -static int clk_mt7988_sgmii1_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct mtk_gate_regs ethwarp_cg_regs = { - .set_ofs = 0x14, - .clr_ofs = 0x14, - .sta_ofs = 0x14, -}; - -#define GATE_ETHWARP(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðwarp_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethwarp_clks[] = { - GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", - "netsys_mcu_sel", 13), - GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", - "netsys_mcu_sel", 14), - GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", - "netsys_mcu_sel", 15), -}; - -static int clk_mt7988_ethwarp_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks)); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_data; - } - return r; - -free_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7988_ethsys[] = { - { - .compatible = "mediatek,mt7988-ethsys", - }, - {} -}; - -static struct platform_driver clk_mt7988_ethsys_drv = { - .probe = clk_mt7988_ethsys_probe, - .driver = { - .name = "clk-mt7988-ethsys", - .of_match_table = of_match_clk_mt7988_ethsys, - }, -}; -builtin_platform_driver(clk_mt7988_ethsys_drv); - -static const struct of_device_id of_match_clk_mt7988_sgmii0[] = { - { - .compatible = "mediatek,mt7988-sgmiisys_0", - }, - {} -}; - -static struct platform_driver clk_mt7988_sgmii0_drv = { - .probe = clk_mt7988_sgmii0_probe, - .driver = { - .name = "clk-mt7988-sgmiisys_0", - .of_match_table = of_match_clk_mt7988_sgmii0, - }, -}; -builtin_platform_driver(clk_mt7988_sgmii0_drv); - -static const struct of_device_id of_match_clk_mt7988_sgmii1[] = { - { - .compatible = "mediatek,mt7988-sgmiisys_1", - }, - {} -}; - -static struct platform_driver clk_mt7988_sgmii1_drv = { - .probe = clk_mt7988_sgmii1_probe, - .driver = { - .name = "clk-mt7988-sgmiisys_1", - .of_match_table = of_match_clk_mt7988_sgmii1, - }, -}; -builtin_platform_driver(clk_mt7988_sgmii1_drv); - -static const struct of_device_id of_match_clk_mt7988_ethwarp[] = { - { - .compatible = "mediatek,mt7988-ethwarp", - }, - {} -}; - -static struct platform_driver clk_mt7988_ethwarp_drv = { - .probe = clk_mt7988_ethwarp_probe, - .driver = { - .name = "clk-mt7988-ethwarp", - .of_match_table = of_match_clk_mt7988_ethwarp, - }, -}; -builtin_platform_driver(clk_mt7988_ethwarp_drv); \ No newline at end of file diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c deleted file mode 100644 index bce8d5637..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const char *const infra_mux_uart0_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart1_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart2_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_mux_spi1_parents[] __initconst = { - "i2c_sel", "spim_mst_sel" -}; - -static const char *const infra_pwm_bck_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p1_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p2_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p3_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", - infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, - 0, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", - infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, - 1, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", - infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, - 2, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", - infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, - "infra_pcie_gfmux_tl_o_p0_sel", - infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, - 0x0020, 0x0024, 0, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, - "infra_pcie_gfmux_tl_o_p1_sel", - infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, - 0x0020, 0x0024, 2, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, - "infra_pcie_gfmux_tl_o_p2_sel", - infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, - 0x0020, 0x0024, 4, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, - "infra_pcie_gfmux_tl_o_p3_sel", - infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, - 0x0020, 0x0024, 6, 2, -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x10, - .clr_ofs = 0x14, - .sta_ofs = 0x18, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra3_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra3_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA3(_id, _name, _parent, _shift) \ - GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = _regs, .shift = _shift, \ - .flags = CLK_IS_CRITICAL, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, - "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, - "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, - "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, - "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", - "sysaxi_sel", 0), - GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", - "sysaxi_sel", 1), - GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", - "infra_pwm_sel", 2), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", - "infra_pwm_ck1_sel", 3), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", - "infra_pwm_ck2_sel", 4), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", - "infra_pwm_ck3_sel", 5), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", - "infra_pwm_ck4_sel", 6), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", - "infra_pwm_ck5_sel", 7), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", - "infra_pwm_ck6_sel", 8), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", - "infra_pwm_ck7_sel", 9), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", - "infra_pwm_ck8_sel", 10), - GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", - "sysaxi_sel", 12), - GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", - "sysaxi_sel", 13), - GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", - "csw_infra_f26m_sel", 14), - GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), - GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), - GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), - GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", - "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL), - // JTAG - GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", - "sysaxi_sel", 20, CLK_IS_CRITICAL), - GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", - "sysaxi_sel", 21), - GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", - "sysaxi_sel", 29), - GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", - "csw_infra_f26m_sel", 30), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", - "csw_infra_f26m_sel", 0), - GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), - GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", - "infra_mux_uart0_sel", 3), - GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", - "infra_mux_uart1_sel", 4), - GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", - "infra_mux_uart2_sel", 5), - GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), - GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", - "sysaxi_sel", 11, CLK_IS_CRITICAL), - GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", - "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", - "infra_mux_spi1_sel", 13), - GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", - "infra_mux_spi2_sel", 14), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", - "sysaxi_sel", 15, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", - "sysaxi_sel", 16), - GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", - "sysaxi_sel", 17), - GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", - "sysaxi_sel", 18), - GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19), - GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", - "csw_infra_f26m_sel", 20), - GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", - 21), - GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", - 22), - GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", - 23), - GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", - "sysaxi_sel", 24), - GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", - "sysaxi_sel", 25), - GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", - "sysaxi_sel", 26), - GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), - GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, - "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), - GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, - "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), - /* INFRA3 */ - GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", - 0), - GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", - "sysaxi_sel", 1), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", - 2), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", - "sysaxi_sel", 3), - GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), - GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", - "usb_sys_p1_sel", 5), - GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), - GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", - "usb_frmcnt_sel", 8, CLK_IS_CRITICAL), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", - "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL), - GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), - GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - "usb_phy_sel", 11), - GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), - GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - "top_xtal", 13), - GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), - GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", - "usb_xhci_p1_sel", 15), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", - "infra_pcie_gfmux_tl_o_p0_sel", 20), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", - "infra_pcie_gfmux_tl_o_p1_sel", 21), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", - "infra_pcie_gfmux_tl_o_p2_sel", 22), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", - "infra_pcie_gfmux_tl_o_p3_sel", 23), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - "top_xtal", 24), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - "top_xtal", 25), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - "top_xtal", 26), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - "top_xtal", 27), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", - "sysaxi_sel", 28), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", - "sysaxi_sel", 29), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", - "sysaxi_sel", 30), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", - "sysaxi_sel", 31), -}; - -static int clk_mt7988_infracfg_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7988_clk_lock, clk_data); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7988_infracfg[] = { - { - .compatible = "mediatek,mt7988-infracfg", - }, - {} -}; - -static struct platform_driver clk_mt7988_infracfg_drv = { - .probe = clk_mt7988_infracfg_probe, - .driver = { - .name = "clk-mt7988-infracfg", - .of_match_table = of_match_clk_mt7988_infracfg, - }, -}; -builtin_platform_driver(clk_mt7988_infracfg_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c deleted file mode 100644 index 917302b6d..000000000 --- a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c +++ /dev/null @@ -1,522 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), -}; - -static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), - FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), - FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), - FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), - FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), - FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), - FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), - FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), - FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), - FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), - FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), - FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), - FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), - FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), -}; - -static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", - "mmpll_d2" }; - -static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", - "net1pll_d5_d2" }; - -static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", - "mmpll" }; - -static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", - "net1pll_d5" }; - -static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; - -static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", - "mmpll", "net1pll_d4", - "net1pll_d5", "mpll" }; - -static const char *const eip197_parents[] = { "top_xtal", "netsyspll", - "net2pll", "mmpll", - "net1pll_d4", "net1pll_d5" }; - -static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; - -static const char *const uart_parents[] = { "top_xtal", "mpll_d8", - "mpll_d8_d2" }; - -static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", - "mmpll_d4" }; - -static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", - "mmpll_d2", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2" }; - -static const char *const spi_parents[] = { "top_xtal", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2", - "net2pll_d6", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", - "net1pll_d8_d2", "net2pll_d6", - "mpll_d4", "mmpll_d8", - "net1pll_d8_d4", "mpll_d8" }; - -static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", - "net1pll_d5_d4", "mpll_d4", - "mmpll_d8", "net1pll_d8_d4", - "mmpll_d6_d2", "mpll_d8" }; - -static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", - "net1pll_d5_d4", "mpll_d4", - "mpll_d8_d2", "top_rtc_32k" }; - -static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const pcie_mbist_250m_parents[] = { "top_xtal", - "net1pll_d5_d2" }; - -static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", - "mmpll_d8", "mpll_d8_d2", - "top_rtc_32k" }; - -static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; - -static const char *const aud_parents[] = { "top_xtal", "apll2" }; - -static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; - -static const char *const aud_l_parents[] = { "top_xtal", "apll2", - "mpll_d8_d2" }; - -static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; - -static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", - "net1pll_d8_d4" }; - -static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; - -static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; - -static const char *const eth_refck_50m_parents[] = { "top_xtal", - "net2pll_d4_d4" }; - -static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; - -static const char *const eth_xgmii_parents[] = { "top_xtal_d2", - "net1pll_d8_d8", - "net1pll_d8_d16" }; - -static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", - "net2pll_d2" }; - -static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; - -static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", - "wedmcupll" }; - -static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", - "net2pll_d8" }; - -static const char *const mcusys_backup_625m_parents[] = { "top_xtal", - "net1pll_d4" }; - -static const char *const macsec_parents[] = { "top_xtal", "sgmpll", - "net1pll_d8" }; - -static const char *const netsys_tops_400m_parents[] = { "top_xtal", - "net2pll_d2" }; - -static const char *const eth_mii_parents[] = { "top_xtal_d2", - "net2pll_d4_d8" }; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, - 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23, - 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", - netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, - 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", - eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7, - 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15, - 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, - 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, - 0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", - axi_infra_parents, 0x020, 0x024, 0x028, 0, - 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, - 0x024, 0x028, 8, 2, 15, 0x1c0, 9), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", - emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23, - 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", - emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31, - 0x1C0, 11), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, - 0x034, 0x038, 0, 3, 7, 0x1c0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, - 0x044, 0x048, 0, 3, 7, 0x1c0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, - 0x044, 0x048, 8, 2, 15, 0x1c0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, - "pcie_mbist_250m_sel", pcie_mbist_250m_parents, - 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", - pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3, - 31, 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, - 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3, - 23, 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", - eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31, - 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7, - 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15, - 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23, - 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", - usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, - 31, 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", - usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, - 0x074, 0x078, 8, 1, 15, 0x1c0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, - 0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, - 0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", - sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23, - 0x1c4, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", - usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, - 1, 31, 0x1C4, 4), - /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, - 7, 0x1C4, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, - 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8), - /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", - usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8, - 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, - 0x1C4, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, - 0x1C4, 11), - /* CLK_CFG_11 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", - axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24, - 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", - sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1, - 7, 0x1c4, 13, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", - eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1, - 15, 0x1C4, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", - eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1, - 23, 0x1C4, 15), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", - pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24, - 1, 31, 0x1C4, 16), - /* CLK_CFG_12 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", - eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, - 0x1C4, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", - bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15, - 0x1C4, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", - npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23, - 0x1C4, 19), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", - sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1, - 31, 0x1C4, 20, CLK_IS_CRITICAL), - /* CLK_CFG_13 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0, - 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS( - CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, - 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23, - 0x1C4, 23), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, - 0x1C4, 24), - /* CLK_CFG_14 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, - 0x1C4, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, - 0x1C4, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, - 23, 0x1C4, 27), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, - 31, 0x1C4, 28), - /* CLK_CFG_15 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1, - 7, 0x1C4, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1, - 15, 0x1C4, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, - 0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, - 0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1), - /* CLK_CFG_16 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, - 0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", - sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15, - 0x1C8, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, - "mcusys_backup_625m_sel", - mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, - 16, 1, 23, 0x1C8, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, - "netsys_sync_250m_sel", pcie_mbist_250m_parents, - 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), - /* CLK_CFG_17 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, - 0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, - "netsys_tops_400m_sel", netsys_tops_400m_parents, - 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, - "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, - 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", - netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31, - 0x1C8, 9), - /* CLK_CFG_18 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", - eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7, - 0x1c8, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, - 0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), -}; - -static const struct mtk_composite top_aud_divs[] = { - DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, - 8, 8), -}; - -static int clk_mt7988_topckgen_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + - ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7988_clk_lock, clk_data); - - mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), - base, &mt7988_clk_lock, clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", - "net1pll_d4" }; - -static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", - "net1pll_d4" }; - -static struct mtk_composite mcu_muxes[] = { - /* bus_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", - mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL), - /* mp2_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", - mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), -}; - -static int clk_mt7988_mcusys_probe(struct platform_device *pdev) -{ - struct clk_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(mcu_muxes); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - &mt7988_clk_lock, clk_data); - - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_mcusys_data; - } - return r; - -free_mcusys_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt7988_topckgen[] = { - { - .compatible = "mediatek,mt7988-topckgen", - }, - {} -}; - -static struct platform_driver clk_mt7988_topckgen_drv = { - .probe = clk_mt7988_topckgen_probe, - .driver = { - .name = "clk-mt7988-topckgen", - .of_match_table = of_match_clk_mt7988_topckgen, - }, -}; -builtin_platform_driver(clk_mt7988_topckgen_drv); - -static const struct of_device_id of_match_clk_mt7988_mcusys[] = { - { - .compatible = "mediatek,mt7988-mcusys", - }, - {} -}; - -static struct platform_driver clk_mt7988_mcusys_drv = { - .probe = clk_mt7988_mcusys_probe, - .driver = { - .name = "clk-mt7988-mcusys", - .of_match_table = of_match_clk_mt7988_mcusys, - }, -}; -builtin_platform_driver(clk_mt7988_mcusys_drv); \ No newline at end of file diff --git a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c deleted file mode 100644 index c12e6b8eb..000000000 --- a/target/linux/mediatek/files-5.15/drivers/net/phy/mediatek-2p5ge.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include -#include - -#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin" -#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin" - -#define MD32_EN_CFG 0x18 -#define MD32_EN BIT(0) - -#define BASE100T_STATUS_EXTEND 0x10 -#define BASE1000T_STATUS_EXTEND 0x11 -#define EXTEND_CTRL_AND_STATUS 0x16 - -#define PHY_AUX_CTRL_STATUS 0x1d -#define PHY_AUX_DPX_MASK GENMASK(5, 5) -#define PHY_AUX_SPEED_MASK GENMASK(4, 2) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_LINK_STATUS_MISC 0xa2 -#define MTK_PHY_FDX_ENABLE BIT(5) - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINK2500 BIT(7) -#define MTK_PHY_LED0_POLARITY BIT(14) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_FDX BIT(4) -#define MTK_PHY_LED1_ON_HDX BIT(5) -#define MTK_PHY_LED1_POLARITY BIT(14) - -enum { - PHY_AUX_SPD_10 = 0, - PHY_AUX_SPD_100, - PHY_AUX_SPD_1000, - PHY_AUX_SPD_2500, -}; - -static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) -{ - int ret; - int i; - const struct firmware *fw; - struct device *dev = &phydev->mdio.dev; - struct device_node *np; - void __iomem *dmb_addr; - void __iomem *pmb_addr; - void __iomem *mcucsr_base; - u16 reg; - struct pinctrl *pinctrl; - - np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); - if (!np) - return -ENOENT; - - dmb_addr = of_iomap(np, 0); - if (!dmb_addr) - return -ENOMEM; - pmb_addr = of_iomap(np, 1); - if (!pmb_addr) - return -ENOMEM; - mcucsr_base = of_iomap(np, 2); - if (!mcucsr_base) - return -ENOMEM; - - ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDAITEK_2P5GE_PHY_DMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); - release_firmware(fw); - - ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDIATEK_2P5GE_PHY_PMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); - release_firmware(fw); - - reg = readw(mcucsr_base + MD32_EN_CFG); - writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); - dev_dbg(dev, "Firmware loading/trigger ok.\n"); - - /* Setup LED */ - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000 | - MTK_PHY_LED0_ON_LINK2500); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); - return PTR_ERR(pinctrl); - } - - return 0; -} - -static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) -{ - bool changed = false; - u32 adv; - int ret; - - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. - */ - return phydev->duplex != DUPLEX_FULL - ? genphy_setup_forced(phydev) - : genphy_c45_pma_setup_forced(phydev); - } - - ret = genphy_c45_an_config_aneg(phydev); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); - ret = phy_modify_changed(phydev, MII_CTRL1000, - ADVERTISE_1000FULL | ADVERTISE_1000HALF, - adv); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - return genphy_c45_check_and_restart_aneg(phydev, changed); -} - -static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) -{ - int ret; - - ret = genphy_read_abilities(phydev); - if (ret) - return ret; - - /* We don't support HDX at MAC layer on mt798x. - * So mask phy's HDX capabilities, too. - */ - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); - - return 0; -} - -static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) -{ - int ret; - - ret = genphy_update_link(phydev); - if (ret) - return ret; - - phydev->speed = SPEED_UNKNOWN; - phydev->duplex = DUPLEX_UNKNOWN; - phydev->pause = 0; - phydev->asym_pause = 0; - - if (!phydev->link) - return 0; - - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { - ret = genphy_c45_read_lpa(phydev); - if (ret < 0) - return ret; - - /* Read the link partner's 1G advertisement */ - ret = phy_read(phydev, MII_STAT1000); - if (ret < 0) - return ret; - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); - } else if (phydev->autoneg == AUTONEG_DISABLE) { - linkmode_zero(phydev->lp_advertising); - } - - ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); - if (ret < 0) - return ret; - - switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { - case PHY_AUX_SPD_10: - phydev->speed = SPEED_10; - break; - case PHY_AUX_SPD_100: - phydev->speed = SPEED_100; - break; - case PHY_AUX_SPD_1000: - phydev->speed = SPEED_1000; - break; - case PHY_AUX_SPD_2500: - phydev->speed = SPEED_2500; - phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */ - break; - } - - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); - if (ret < 0) - return ret; - - phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; - - return 0; -} - -static struct phy_driver mtk_gephy_driver[] = { - { - PHY_ID_MATCH_EXACT(0x00339c11), - .name = "MediaTek MT798x 2.5GbE PHY", - .config_init = mt798x_2p5ge_phy_config_init, - .config_aneg = mt798x_2p5ge_phy_config_aneg, - .get_features = mt798x_2p5ge_phy_get_features, - .read_status = mt798x_2p5ge_phy_read_status, - }, -}; - -module_phy_driver(mtk_gephy_driver); - -static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { - { PHY_ID_MATCH_VENDOR(0x00339c00) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW); -MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW); diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c deleted file mode 100644 index 7c082dd20..000000000 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ /dev/null @@ -1,1041 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7981 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -#define MT7981_PIN(_number, _name) \ - MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { - PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { - PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { - PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { - PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), - - PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), - - PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { - PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { - PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), - PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), - - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), - - PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), - PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), - PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), - - PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), - - PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), - - PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), - - PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), - - PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), - - PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), -}; - -static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), -}; - -static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), - - PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), - - PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), - - PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), - - PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), - - PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), - - PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), - - PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), -}; - -static const unsigned int mt7981_pull_type[] = { - MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ - MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ - MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ - MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ - MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ - MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ - MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ - MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ - MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ - MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ - MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ - MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ - MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ - MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ - MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ - MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ - MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ - MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ - MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ - MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ - MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ - MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ - MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ - MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ - MTK_PULL_PU_PD_TYPE,/*56*/ -}; - -static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7981_pins[] = { - MT7981_PIN(0, "GPIO_WPS"), - MT7981_PIN(1, "GPIO_RESET"), - MT7981_PIN(2, "SYS_WATCHDOG"), - MT7981_PIN(3, "PCIE_PERESET_N"), - MT7981_PIN(4, "JTAG_JTDO"), - MT7981_PIN(5, "JTAG_JTDI"), - MT7981_PIN(6, "JTAG_JTMS"), - MT7981_PIN(7, "JTAG_JTCLK"), - MT7981_PIN(8, "JTAG_JTRST_N"), - MT7981_PIN(9, "WO_JTAG_JTDO"), - MT7981_PIN(10, "WO_JTAG_JTDI"), - MT7981_PIN(11, "WO_JTAG_JTMS"), - MT7981_PIN(12, "WO_JTAG_JTCLK"), - MT7981_PIN(13, "WO_JTAG_JTRST_N"), - MT7981_PIN(14, "USB_VBUS"), - MT7981_PIN(15, "PWM0"), - MT7981_PIN(16, "SPI0_CLK"), - MT7981_PIN(17, "SPI0_MOSI"), - MT7981_PIN(18, "SPI0_MISO"), - MT7981_PIN(19, "SPI0_CS"), - MT7981_PIN(20, "SPI0_HOLD"), - MT7981_PIN(21, "SPI0_WP"), - MT7981_PIN(22, "SPI1_CLK"), - MT7981_PIN(23, "SPI1_MOSI"), - MT7981_PIN(24, "SPI1_MISO"), - MT7981_PIN(25, "SPI1_CS"), - MT7981_PIN(26, "SPI2_CLK"), - MT7981_PIN(27, "SPI2_MOSI"), - MT7981_PIN(28, "SPI2_MISO"), - MT7981_PIN(29, "SPI2_CS"), - MT7981_PIN(30, "SPI2_HOLD"), - MT7981_PIN(31, "SPI2_WP"), - MT7981_PIN(32, "UART0_RXD"), - MT7981_PIN(33, "UART0_TXD"), - MT7981_PIN(34, "PCIE_CLK_REQ"), - MT7981_PIN(35, "PCIE_WAKE_N"), - MT7981_PIN(36, "SMI_MDC"), - MT7981_PIN(37, "SMI_MDIO"), - MT7981_PIN(38, "GBE_INT"), - MT7981_PIN(39, "GBE_RESET"), - MT7981_PIN(40, "WF_DIG_RESETB"), - MT7981_PIN(41, "WF_CBA_RESETB"), - MT7981_PIN(42, "WF_XO_REQ"), - MT7981_PIN(43, "WF_TOP_CLK"), - MT7981_PIN(44, "WF_TOP_DATA"), - MT7981_PIN(45, "WF_HB1"), - MT7981_PIN(46, "WF_HB2"), - MT7981_PIN(47, "WF_HB3"), - MT7981_PIN(48, "WF_HB4"), - MT7981_PIN(49, "WF_HB0"), - MT7981_PIN(50, "WF_HB0_B"), - MT7981_PIN(51, "WF_HB5"), - MT7981_PIN(52, "WF_HB6"), - MT7981_PIN(53, "WF_HB7"), - MT7981_PIN(54, "WF_HB8"), - MT7981_PIN(55, "WF_HB9"), - MT7981_PIN(56, "WF_HB10"), -}; - -/* List all groups consisting of these pins dedicated to the enablement of - * certain hardware block and the corresponding mode for all of the pins. - * The hardware probably has multiple combinations of these pinouts. - */ - -/* WA_AICE */ -static int mt7981_wa_aice1_pins[] = { 0, 1, }; -static int mt7981_wa_aice1_funcs[] = { 2, 2, }; - -static int mt7981_wa_aice2_pins[] = { 0, 1, }; -static int mt7981_wa_aice2_funcs[] = { 3, 3, }; - -static int mt7981_wa_aice3_pins[] = { 28, 29, }; -static int mt7981_wa_aice3_funcs[] = { 3, 3, }; - -static int mt7981_wm_aice1_pins[] = { 9, 10, }; -static int mt7981_wm_aice1_funcs[] = { 2, 2, }; - -static int mt7981_wm_aice2_pins[] = { 30, 31, }; -static int mt7981_wm_aice2_funcs[] = { 5, 5, }; - -/* WM_UART */ -static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; - -static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; - -static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; - -/* DFD */ -static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; - -/* SYS_WATCHDOG */ -static int mt7981_watchdog_pins[] = { 2, }; -static int mt7981_watchdog_funcs[] = { 1, }; - -static int mt7981_watchdog1_pins[] = { 13, }; -static int mt7981_watchdog1_funcs[] = { 5, }; - -/* PCIE_PERESET_N */ -static int mt7981_pcie_pereset_pins[] = { 3, }; -static int mt7981_pcie_pereset_funcs[] = { 1, }; - -/* JTAG */ -static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; - -/* WM_JTAG */ -static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; - -static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; - -/* WO0_JTAG */ -static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; - -static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; - -/* UART2 */ -static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - -static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; -static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; - -/* GBE_LED0 */ -static int mt7981_gbe_led0_pins[] = { 8, }; -static int mt7981_gbe_led0_funcs[] = { 3, }; - -/* PTA_EXT */ -static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; - -static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; - -/* PWM2 */ -static int mt7981_pwm2_pins[] = { 7, }; -static int mt7981_pwm2_funcs[] = { 4, }; - -/* NET_WO0_UART_TXD */ -static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; - -static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; - -static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; - -/* SPI1 */ -static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; - -/* I2C */ -static int mt7981_i2c0_0_pins[] = { 6, 7, }; -static int mt7981_i2c0_0_funcs[] = { 6, 6, }; - -static int mt7981_i2c0_1_pins[] = { 30, 31, }; -static int mt7981_i2c0_1_funcs[] = { 4, 4, }; - -static int mt7981_i2c0_2_pins[] = { 36, 37, }; -static int mt7981_i2c0_2_funcs[] = { 2, 2, }; - -static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; - -static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; - -static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; - -static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; - -/* DFD_NTRST */ -static int mt7981_dfd_ntrst_pins[] = { 8, }; -static int mt7981_dfd_ntrst_funcs[] = { 6, }; - -/* PWM0 */ -static int mt7981_pwm0_0_pins[] = { 13, }; -static int mt7981_pwm0_0_funcs[] = { 2, }; - -static int mt7981_pwm0_1_pins[] = { 15, }; -static int mt7981_pwm0_1_funcs[] = { 1, }; - -/* PWM1 */ -static int mt7981_pwm1_0_pins[] = { 14, }; -static int mt7981_pwm1_0_funcs[] = { 2, }; - -static int mt7981_pwm1_1_pins[] = { 15, }; -static int mt7981_pwm1_1_funcs[] = { 3, }; - -/* GBE_LED1 */ -static int mt7981_gbe_led1_pins[] = { 13, }; -static int mt7981_gbe_led1_funcs[] = { 3, }; - -/* PCM */ -static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; - -/* UDI */ -static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; - -/* DRV_VBUS */ -static int mt7981_drv_vbus_pins[] = { 14, }; -static int mt7981_drv_vbus_funcs[] = { 1, }; - -/* EMMC */ -static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -/* SNFI */ -static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; - -/* SPI0 */ -static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; - -/* SPI0 */ -static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; - -/* SPI1 */ -static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; - -/* SPI2 */ -static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; - -/* SPI2 */ -static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; - -/* UART1 */ -static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; - -static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - -static int mt7981_uart1_2_pins[] = { 9, 10, }; -static int mt7981_uart1_2_funcs[] = { 2, 2, }; - -/* UART2 */ -static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; - -/* UART0 */ -static int mt7981_uart0_pins[] = { 32, 33, }; -static int mt7981_uart0_funcs[] = { 1, 1, }; - -/* PCIE_CLK_REQ */ -static int mt7981_pcie_clk_pins[] = { 34, }; -static int mt7981_pcie_clk_funcs[] = { 2, }; - -/* PCIE_WAKE_N */ -static int mt7981_pcie_wake_pins[] = { 35, }; -static int mt7981_pcie_wake_funcs[] = { 2, }; - -/* MDC_MDIO */ -static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; - -static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; - -/* WF0_MODE1 */ -static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; -static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* WF0_MODE3 */ -static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -/* WF2G_LED */ -static int mt7981_wf2g_led0_pins[] = { 30, }; -static int mt7981_wf2g_led0_funcs[] = { 2, }; - -static int mt7981_wf2g_led1_pins[] = { 34, }; -static int mt7981_wf2g_led1_funcs[] = { 1, }; - -/* WF5G_LED */ -static int mt7981_wf5g_led0_pins[] = { 31, }; -static int mt7981_wf5g_led0_funcs[] = { 2, }; - -static int mt7981_wf5g_led1_pins[] = { 35, }; -static int mt7981_wf5g_led1_funcs[] = { 1, }; - -/* MT7531_INT */ -static int mt7981_mt7531_int_pins[] = { 38, }; -static int mt7981_mt7531_int_funcs[] = { 1, }; - -/* ANT_SEL */ -static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; - -static const struct group_desc mt7981_groups[] = { - /* @GPIO(0,1): WA_AICE(2) */ - PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), - /* @GPIO(0,1): WA_AICE(3) */ - PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), - /* @GPIO(0,1): WM_UART(5) */ - PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), - /* @GPIO(0,1,4,5): DFD(6) */ - PINCTRL_PIN_GROUP("dfd", mt7981_dfd), - /* @GPIO(2): SYS_WATCHDOG(1) */ - PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), - /* @GPIO(3): PCIE_PERESET_N(1) */ - PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), - /* @GPIO(4,8) JTAG(1) */ - PINCTRL_PIN_GROUP("jtag", mt7981_jtag), - /* @GPIO(4,8) WM_JTAG(2) */ - PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), - /* @GPIO(9,13) WO0_JTAG(1) */ - PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), - /* @GPIO(4,7) WM_JTAG(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), - /* @GPIO(4,5) WM_JTAG(4) */ - PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), - /* @GPIO(8) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), - /* @GPIO(4,6) PTA_EXT(4) */ - PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), - /* @GPIO(7) PWM2(4) */ - PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), - /* @GPIO(8) NET_WO0_UART_TXD(4) */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), - /* @GPIO(4,7) SPI1(5) */ - PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), - /* @GPIO(6,7) I2C(5) */ - PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), - /* @GPIO(0,1,4,5): DFD_NTRST(6) */ - PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), - /* @GPIO(9,10): WM_AICE(2) */ - PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), - /* @GPIO(13): PWM0(2) */ - PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), - /* @GPIO(15): PWM0(1) */ - PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), - /* @GPIO(14): PWM1(2) */ - PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), - /* @GPIO(15): PWM1(3) */ - PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), - /* @GPIO(14) NET_WO0_UART_TXD(3) */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), - /* @GPIO(15) NET_WO0_UART_TXD(4) */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), - /* @GPIO(13) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), - /* @GPIO(9,13) PCM(4) */ - PINCTRL_PIN_GROUP("pcm", mt7981_pcm), - /* @GPIO(13): SYS_WATCHDOG1(5) */ - PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), - /* @GPIO(9,13) UDI(4) */ - PINCTRL_PIN_GROUP("udi", mt7981_udi), - /* @GPIO(14) DRV_VBUS(1) */ - PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), - /* @GPIO(15,25): EMMC(2) */ - PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), - /* @GPIO(16,21): SNFI(3) */ - PINCTRL_PIN_GROUP("snfi", mt7981_snfi), - /* @GPIO(16,19): SPI0(1) */ - PINCTRL_PIN_GROUP("spi0", mt7981_spi0), - /* @GPIO(20,21): SPI0(1) */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), - /* @GPIO(22,25) SPI1(1) */ - PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), - /* @GPIO(26,29): SPI2(1) */ - PINCTRL_PIN_GROUP("spi2", mt7981_spi2), - /* @GPIO(30,31): SPI0(1) */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), - /* @GPIO(16,19): UART1(4) */ - PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), - /* @GPIO(26,29): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), - /* @GPIO(9,10): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ - PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), - /* @GPIO(20,21): WM_UART(4) */ - PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), - /* @GPIO(30,31): WM_UART(3) */ - PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), - /* @GPIO(20,24) WM_JTAG(5) */ - PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), - /* @GPIO(25,29) WO0_JTAG(5) */ - PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), - /* @GPIO(28,29): WA_AICE(3) */ - PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), - /* @GPIO(30,31): WM_AICE(5) */ - PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), - /* @GPIO(30,31): I2C(4) */ - PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), - /* @GPIO(30,31): I2C(6) */ - PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), - /* @GPIO(32,33): I2C(1) */ - PINCTRL_PIN_GROUP("uart0", mt7981_uart0), - /* @GPIO(32,33): I2C(2) */ - PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), - /* @GPIO(32,33): I2C(3) */ - PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), - /* @GPIO(32,33): I2C(5) */ - PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), - /* @GPIO(34): PCIE_CLK_REQ(2) */ - PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), - /* @GPIO(35): PCIE_WAKE_N(2) */ - PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), - /* @GPIO(36,37): I2C(2) */ - PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), - /* @GPIO(36,37): MDC_MDIO(1) */ - PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), - /* @GPIO(36,37): MDC_MDIO(3) */ - PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), - /* @GPIO(69,85): WF0_MODE1(1) */ - PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), - /* @GPIO(74,80): WF0_MODE3(3) */ - PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), - /* @GPIO(30): WF2G_LED(2) */ - PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), - /* @GPIO(34): WF2G_LED(1) */ - PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), - /* @GPIO(31): WF5G_LED(2) */ - PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), - /* @GPIO(35): WF5G_LED(1) */ - PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), - /* @GPIO(38): MT7531_INT(1) */ - PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), - /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ - PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; -static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", - "uart1_2", "uart2_0_tx_rx", - "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", - "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; -static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; -static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; -static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", - "wo0_jtag_1", "wm_jtag_1", }; -static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", - "wf2g_led1", "wf5g_led0", "wf5g_led1", }; -static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; -static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", - "pwm1_0", "pwm1_1", }; -static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", - "spi2_wp_hold", }; -static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", - "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; -static const char *mt7981_pcm_groups[] = { "pcm", }; -static const char *mt7981_udi_groups[] = { "udi", }; -static const char *mt7981_usb_groups[] = { "drv_vbus", }; -static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", - "wf0_mode1", "wf0_mode3", "mt7531_int", }; -static const char *mt7981_ant_groups[] = { "ant_sel", }; - -static const struct function_desc mt7981_functions[] = { - {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, - {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, - {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, - {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, - {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, - {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, - {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, - {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, - {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, - {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, - {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, - {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, - {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, - {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, - {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, - {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, - {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, -}; - -static const struct mtk_eint_hw mt7981_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7981_pins), - .db_cnt = 16, -}; - -static const char * const mt7981_pinctrl_register_base_names[] = { - "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", - "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", -}; - -static struct mtk_pin_soc mt7981_data = { - .reg_cal = mt7981_reg_cals, - .pins = mt7981_pins, - .npins = ARRAY_SIZE(mt7981_pins), - .grps = mt7981_groups, - .ngrps = ARRAY_SIZE(mt7981_groups), - .funcs = mt7981_functions, - .nfuncs = ARRAY_SIZE(mt7981_functions), - .eint_hw = &mt7981_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7981_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7981_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7981_pinctrl_of_match[] = { - { .compatible = "mediatek,mt7981-pinctrl", }, - {} -}; - -static int mt7981_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7981_data); -} - -static struct platform_driver mt7981_pinctrl_driver = { - .driver = { - .name = "mt7981-pinctrl", - .of_match_table = mt7981_pinctrl_of_match, - }, - .probe = mt7981_pinctrl_probe, -}; - -static int __init mt7981_pinctrl_init(void) -{ - return platform_driver_register(&mt7981_pinctrl_driver); -} -arch_initcall(mt7981_pinctrl_init); diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c deleted file mode 100644 index acaac9b38..000000000 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ /dev/null @@ -1,1011 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7986 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL } - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -/** - * enum - Locking variants of the iocfg bases - * - * MT7986 have multiple bases to program pin configuration listed as the below: - * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, - * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, - * _i_based could be used to indicate what base the pin should be mapped into. - * - * Each iocfg register base control different group of pads on the SoC - * - * - * chip carrier - * - * A B C D E F G H - * +------------------------+ - * 8 | o o o o o o o o | - * 7 | o o o o o o o o | - * 6 | o o o o o o o o | - * 5 | o o o o o o o o | - * 4 | o o o o o o o o | - * 3 | o o o o o o o o | - * 2 | o o o o o o o o | - * 1 | o o o o o o o o | - * +------------------------+ - * - * inside Chip carrier - * - * A B C D E F G H - * +------------------------+ - * 8 | | - * 7 | TL TR | - * 6 | +---------+ | - * 5 | LT | | RT | - * 4 | | | | - * 3 | LB | | RB | - * 2 | +---------+ | - * 1 | | - * +------------------------+ - * - */ - -enum { - GPIO_BASE, - IOCFG_RT_BASE, - IOCFG_RB_BASE, - IOCFG_LT_BASE, - IOCFG_LB_BASE, - IOCFG_TR_BASE, - IOCFG_TL_BASE, -}; - -static const char *const mt7986_pinctrl_register_base_names[] = { - "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr", - "iocfg_tl", -}; - -static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = { - PIN_FIELD(0, 100, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = { - PIN_FIELD(0, 100, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_di_range[] = { - PIN_FIELD(0, 100, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_do_range[] = { - PIN_FIELD(0, 100, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = { - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = { - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3), - PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3), -}; - -static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), -}; - -static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1), - PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1), - PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1), - PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1), - PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1), - PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1), - PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1), - PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1), - PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), - PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), - PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1), - PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1), - PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1), - PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), -}; - -static const unsigned int mt7986_pull_type[] = { - MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ - MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ - MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ - MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ - MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ - MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ - MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ - MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ - MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ - MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ - MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ - MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ - MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ - MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ - MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ - MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ - MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ - MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ - MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ - MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ - MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ - MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ - MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ - MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ - MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ - MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ - MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ - MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ - MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ - MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ - MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ - MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ - MTK_PULL_PU_PD_TYPE,/*100*/ -}; - -static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7986a_pins[] = { - MT7986_PIN(0, "SYS_WATCHDOG"), - MT7986_PIN(1, "WF2G_LED"), - MT7986_PIN(2, "WF5G_LED"), - MT7986_PIN(3, "I2C_SCL"), - MT7986_PIN(4, "I2C_SDA"), - MT7986_PIN(5, "GPIO_0"), - MT7986_PIN(6, "GPIO_1"), - MT7986_PIN(7, "GPIO_2"), - MT7986_PIN(8, "GPIO_3"), - MT7986_PIN(9, "GPIO_4"), - MT7986_PIN(10, "GPIO_5"), - MT7986_PIN(11, "GPIO_6"), - MT7986_PIN(12, "GPIO_7"), - MT7986_PIN(13, "GPIO_8"), - MT7986_PIN(14, "GPIO_9"), - MT7986_PIN(15, "GPIO_10"), - MT7986_PIN(16, "GPIO_11"), - MT7986_PIN(17, "GPIO_12"), - MT7986_PIN(18, "GPIO_13"), - MT7986_PIN(19, "GPIO_14"), - MT7986_PIN(20, "GPIO_15"), - MT7986_PIN(21, "PWM0"), - MT7986_PIN(22, "PWM1"), - MT7986_PIN(23, "SPI0_CLK"), - MT7986_PIN(24, "SPI0_MOSI"), - MT7986_PIN(25, "SPI0_MISO"), - MT7986_PIN(26, "SPI0_CS"), - MT7986_PIN(27, "SPI0_HOLD"), - MT7986_PIN(28, "SPI0_WP"), - MT7986_PIN(29, "SPI1_CLK"), - MT7986_PIN(30, "SPI1_MOSI"), - MT7986_PIN(31, "SPI1_MISO"), - MT7986_PIN(32, "SPI1_CS"), - MT7986_PIN(33, "SPI2_CLK"), - MT7986_PIN(34, "SPI2_MOSI"), - MT7986_PIN(35, "SPI2_MISO"), - MT7986_PIN(36, "SPI2_CS"), - MT7986_PIN(37, "SPI2_HOLD"), - MT7986_PIN(38, "SPI2_WP"), - MT7986_PIN(39, "UART0_RXD"), - MT7986_PIN(40, "UART0_TXD"), - MT7986_PIN(41, "PCIE_PERESET_N"), - MT7986_PIN(42, "UART1_RXD"), - MT7986_PIN(43, "UART1_TXD"), - MT7986_PIN(44, "UART1_CTS"), - MT7986_PIN(45, "UART1_RTS"), - MT7986_PIN(46, "UART2_RXD"), - MT7986_PIN(47, "UART2_TXD"), - MT7986_PIN(48, "UART2_CTS"), - MT7986_PIN(49, "UART2_RTS"), - MT7986_PIN(50, "EMMC_DATA_0"), - MT7986_PIN(51, "EMMC_DATA_1"), - MT7986_PIN(52, "EMMC_DATA_2"), - MT7986_PIN(53, "EMMC_DATA_3"), - MT7986_PIN(54, "EMMC_DATA_4"), - MT7986_PIN(55, "EMMC_DATA_5"), - MT7986_PIN(56, "EMMC_DATA_6"), - MT7986_PIN(57, "EMMC_DATA_7"), - MT7986_PIN(58, "EMMC_CMD"), - MT7986_PIN(59, "EMMC_CK"), - MT7986_PIN(60, "EMMC_DSL"), - MT7986_PIN(61, "EMMC_RSTB"), - MT7986_PIN(62, "PCM_DTX"), - MT7986_PIN(63, "PCM_DRX"), - MT7986_PIN(64, "PCM_CLK"), - MT7986_PIN(65, "PCM_FS"), - MT7986_PIN(66, "MT7531_INT"), - MT7986_PIN(67, "SMI_MDC"), - MT7986_PIN(68, "SMI_MDIO"), - MT7986_PIN(69, "WF0_DIG_RESETB"), - MT7986_PIN(70, "WF0_CBA_RESETB"), - MT7986_PIN(71, "WF0_XO_REQ"), - MT7986_PIN(72, "WF0_TOP_CLK"), - MT7986_PIN(73, "WF0_TOP_DATA"), - MT7986_PIN(74, "WF0_HB1"), - MT7986_PIN(75, "WF0_HB2"), - MT7986_PIN(76, "WF0_HB3"), - MT7986_PIN(77, "WF0_HB4"), - MT7986_PIN(78, "WF0_HB0"), - MT7986_PIN(79, "WF0_HB0_B"), - MT7986_PIN(80, "WF0_HB5"), - MT7986_PIN(81, "WF0_HB6"), - MT7986_PIN(82, "WF0_HB7"), - MT7986_PIN(83, "WF0_HB8"), - MT7986_PIN(84, "WF0_HB9"), - MT7986_PIN(85, "WF0_HB10"), - MT7986_PIN(86, "WF1_DIG_RESETB"), - MT7986_PIN(87, "WF1_CBA_RESETB"), - MT7986_PIN(88, "WF1_XO_REQ"), - MT7986_PIN(89, "WF1_TOP_CLK"), - MT7986_PIN(90, "WF1_TOP_DATA"), - MT7986_PIN(91, "WF1_HB1"), - MT7986_PIN(92, "WF1_HB2"), - MT7986_PIN(93, "WF1_HB3"), - MT7986_PIN(94, "WF1_HB4"), - MT7986_PIN(95, "WF1_HB0"), - MT7986_PIN(96, "WF1_HB0_B"), - MT7986_PIN(97, "WF1_HB5"), - MT7986_PIN(98, "WF1_HB6"), - MT7986_PIN(99, "WF1_HB7"), - MT7986_PIN(100, "WF1_HB8"), -}; - -static const struct mtk_pin_desc mt7986b_pins[] = { - MT7986_PIN(0, "SYS_WATCHDOG"), - MT7986_PIN(1, "WF2G_LED"), - MT7986_PIN(2, "WF5G_LED"), - MT7986_PIN(3, "I2C_SCL"), - MT7986_PIN(4, "I2C_SDA"), - MT7986_PIN(5, "GPIO_0"), - MT7986_PIN(6, "GPIO_1"), - MT7986_PIN(7, "GPIO_2"), - MT7986_PIN(8, "GPIO_3"), - MT7986_PIN(9, "GPIO_4"), - MT7986_PIN(10, "GPIO_5"), - MT7986_PIN(11, "GPIO_6"), - MT7986_PIN(12, "GPIO_7"), - MT7986_PIN(13, "GPIO_8"), - MT7986_PIN(14, "GPIO_9"), - MT7986_PIN(15, "GPIO_10"), - MT7986_PIN(16, "GPIO_11"), - MT7986_PIN(17, "GPIO_12"), - MT7986_PIN(18, "GPIO_13"), - MT7986_PIN(19, "GPIO_14"), - MT7986_PIN(20, "GPIO_15"), - MT7986_PIN(21, "PWM0"), - MT7986_PIN(22, "PWM1"), - MT7986_PIN(23, "SPI0_CLK"), - MT7986_PIN(24, "SPI0_MOSI"), - MT7986_PIN(25, "SPI0_MISO"), - MT7986_PIN(26, "SPI0_CS"), - MT7986_PIN(27, "SPI0_HOLD"), - MT7986_PIN(28, "SPI0_WP"), - MT7986_PIN(29, "SPI1_CLK"), - MT7986_PIN(30, "SPI1_MOSI"), - MT7986_PIN(31, "SPI1_MISO"), - MT7986_PIN(32, "SPI1_CS"), - MT7986_PIN(33, "SPI2_CLK"), - MT7986_PIN(34, "SPI2_MOSI"), - MT7986_PIN(35, "SPI2_MISO"), - MT7986_PIN(36, "SPI2_CS"), - MT7986_PIN(37, "SPI2_HOLD"), - MT7986_PIN(38, "SPI2_WP"), - MT7986_PIN(39, "UART0_RXD"), - MT7986_PIN(40, "UART0_TXD"), - MT7986_NOT_BALLOUT_PIN(41), - MT7986_NOT_BALLOUT_PIN(42), - MT7986_NOT_BALLOUT_PIN(43), - MT7986_NOT_BALLOUT_PIN(44), - MT7986_NOT_BALLOUT_PIN(45), - MT7986_NOT_BALLOUT_PIN(46), - MT7986_NOT_BALLOUT_PIN(47), - MT7986_NOT_BALLOUT_PIN(48), - MT7986_NOT_BALLOUT_PIN(49), - MT7986_NOT_BALLOUT_PIN(50), - MT7986_NOT_BALLOUT_PIN(51), - MT7986_NOT_BALLOUT_PIN(52), - MT7986_NOT_BALLOUT_PIN(53), - MT7986_NOT_BALLOUT_PIN(54), - MT7986_NOT_BALLOUT_PIN(55), - MT7986_NOT_BALLOUT_PIN(56), - MT7986_NOT_BALLOUT_PIN(57), - MT7986_NOT_BALLOUT_PIN(58), - MT7986_NOT_BALLOUT_PIN(59), - MT7986_NOT_BALLOUT_PIN(60), - MT7986_NOT_BALLOUT_PIN(61), - MT7986_NOT_BALLOUT_PIN(62), - MT7986_NOT_BALLOUT_PIN(63), - MT7986_NOT_BALLOUT_PIN(64), - MT7986_NOT_BALLOUT_PIN(65), - MT7986_PIN(66, "MT7531_INT"), - MT7986_PIN(67, "SMI_MDC"), - MT7986_PIN(68, "SMI_MDIO"), - MT7986_PIN(69, "WF0_DIG_RESETB"), - MT7986_PIN(70, "WF0_CBA_RESETB"), - MT7986_PIN(71, "WF0_XO_REQ"), - MT7986_PIN(72, "WF0_TOP_CLK"), - MT7986_PIN(73, "WF0_TOP_DATA"), - MT7986_PIN(74, "WF0_HB1"), - MT7986_PIN(75, "WF0_HB2"), - MT7986_PIN(76, "WF0_HB3"), - MT7986_PIN(77, "WF0_HB4"), - MT7986_PIN(78, "WF0_HB0"), - MT7986_PIN(79, "WF0_HB0_B"), - MT7986_PIN(80, "WF0_HB5"), - MT7986_PIN(81, "WF0_HB6"), - MT7986_PIN(82, "WF0_HB7"), - MT7986_PIN(83, "WF0_HB8"), - MT7986_PIN(84, "WF0_HB9"), - MT7986_PIN(85, "WF0_HB10"), - MT7986_PIN(86, "WF1_DIG_RESETB"), - MT7986_PIN(87, "WF1_CBA_RESETB"), - MT7986_PIN(88, "WF1_XO_REQ"), - MT7986_PIN(89, "WF1_TOP_CLK"), - MT7986_PIN(90, "WF1_TOP_DATA"), - MT7986_PIN(91, "WF1_HB1"), - MT7986_PIN(92, "WF1_HB2"), - MT7986_PIN(93, "WF1_HB3"), - MT7986_PIN(94, "WF1_HB4"), - MT7986_PIN(95, "WF1_HB0"), - MT7986_PIN(96, "WF1_HB0_B"), - MT7986_PIN(97, "WF1_HB5"), - MT7986_PIN(98, "WF1_HB6"), - MT7986_PIN(99, "WF1_HB7"), - MT7986_PIN(100, "WF1_HB8"), -}; - -/* List all groups consisting of these pins dedicated to the enablement of - * certain hardware block and the corresponding mode for all of the pins. - * The hardware probably has multiple combinations of these pinouts. - */ - -static int mt7986_watchdog_pins[] = { 0, }; -static int mt7986_watchdog_funcs[] = { 1, }; - -static int mt7986_wifi_led_pins[] = { 1, 2, }; -static int mt7986_wifi_led_funcs[] = { 1, 1, }; - -static int mt7986_i2c_pins[] = { 3, 4, }; -static int mt7986_i2c_funcs[] = { 1, 1, }; - -static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; -static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; -static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_pwm1_1_pins[] = { 20, }; -static int mt7986_pwm1_1_funcs[] = { 2, }; - -static int mt7986_pwm0_pins[] = { 21, }; -static int mt7986_pwm0_funcs[] = { 1, }; - -static int mt7986_pwm1_0_pins[] = { 22, }; -static int mt7986_pwm1_0_funcs[] = { 1, }; - -static int mt7986_emmc_45_pins[] = { - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; -static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; -static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; - -static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; -static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; -static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; - -static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; -static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; -static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; - -static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; -static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; - -static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; -static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; - -static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; -static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; - -static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; -static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; -static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; - -static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; -static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; - -static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; -static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; - -static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; -static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; - -static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; -static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; - -static int mt7986_uart0_pins[] = { 39, 40, }; -static int mt7986_uart0_funcs[] = { 1, 1, }; - -static int mt7986_pcie_reset_pins[] = { 41, }; -static int mt7986_pcie_reset_funcs[] = { 1, }; - -static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; -static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; -static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; - -static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; -static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; - -static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; -static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_emmc_51_pins[] = { - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; -static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - -static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; -static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; -static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; - -static int mt7986_switch_int_pins[] = { 66, }; -static int mt7986_switch_int_funcs[] = { 1, }; - -static int mt7986_mdc_mdio_pins[] = { 67, 68, }; -static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; - -static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; -static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - -static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; -static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - -static int mt7986_wf_dbdc_pins[] = { - 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; -static int mt7986_wf_dbdc_funcs[] = { - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -static int mt7986_pcie_clk_pins[] = { 9, }; -static int mt7986_pcie_clk_funcs[] = { 1, }; - -static int mt7986_pcie_wake_pins[] = { 10, }; -static int mt7986_pcie_wake_funcs[] = { 1, }; - -static const struct group_desc mt7986_groups[] = { - PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), - PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), - PINCTRL_PIN_GROUP("i2c", mt7986_i2c), - PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), - PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), - PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), - PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), - PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), - PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), - PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1), - PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0), - PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0), - PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45), - PINCTRL_PIN_GROUP("snfi", mt7986_snfi), - PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), - PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), - PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), - PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), - PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), - PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), - PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), - PINCTRL_PIN_GROUP("spi0", mt7986_spi0), - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), - PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), - PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx), - PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts), - PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3), - PINCTRL_PIN_GROUP("uart0", mt7986_uart0), - PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int), - PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio), - PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset), - PINCTRL_PIN_GROUP("uart1", mt7986_uart1), - PINCTRL_PIN_GROUP("uart2", mt7986_uart2), - PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51), - PINCTRL_PIN_GROUP("pcm", mt7986_pcm), - PINCTRL_PIN_GROUP("i2s", mt7986_i2s), - PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g), - PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g), - PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ - -static const char *mt7986_audio_groups[] = { "pcm", "i2s" }; -static const char *mt7986_emmc_groups[] = { - "emmc_45", "emmc_51", }; -static const char *mt7986_ethernet_groups[] = { - "switch_int", "mdc_mdio", }; -static const char *mt7986_i2c_groups[] = { "i2c", }; -static const char *mt7986_led_groups[] = { "wifi_led", }; -static const char *mt7986_flash_groups[] = { "snfi", }; -static const char *mt7986_pcie_groups[] = { - "pcie_clk", "pcie_wake", "pcie_pereset" }; -static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; -static const char *mt7986_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; -static const char *mt7986_uart_groups[] = { - "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", - "uart1_2_rx_tx", "uart1_2_cts_rts", - "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", - "uart2_0", "uart2_1", "uart0", "uart1", "uart2", -}; -static const char *mt7986_wdt_groups[] = { "watchdog", }; -static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", }; - -static const struct function_desc mt7986_functions[] = { - {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)}, - {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)}, - {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)}, - {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)}, - {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)}, - {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)}, - {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)}, - {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)}, - {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)}, - {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)}, - {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)}, - {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, -}; - -static const struct mtk_eint_hw mt7986a_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7986a_pins), - .db_cnt = 16, - .db_time = debounce_time_mt6765, -}; - -static const struct mtk_eint_hw mt7986b_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7986b_pins), - .db_cnt = 16, - .db_time = debounce_time_mt6765, -}; - -static struct mtk_pin_soc mt7986a_data = { - .reg_cal = mt7986_reg_cals, - .pins = mt7986a_pins, - .npins = ARRAY_SIZE(mt7986a_pins), - .grps = mt7986_groups, - .ngrps = ARRAY_SIZE(mt7986_groups), - .funcs = mt7986_functions, - .nfuncs = ARRAY_SIZE(mt7986_functions), - .eint_hw = &mt7986a_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static struct mtk_pin_soc mt7986b_data = { - .reg_cal = mt7986_reg_cals, - .pins = mt7986b_pins, - .npins = ARRAY_SIZE(mt7986b_pins), - .grps = mt7986_groups, - .ngrps = ARRAY_SIZE(mt7986_groups), - .funcs = mt7986_functions, - .nfuncs = ARRAY_SIZE(mt7986_functions), - .eint_hw = &mt7986b_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7986a_pinctrl_of_match[] = { - {.compatible = "mediatek,mt7986a-pinctrl",}, - {} -}; - -static const struct of_device_id mt7986b_pinctrl_of_match[] = { - {.compatible = "mediatek,mt7986b-pinctrl",}, - {} -}; - -static int mt7986a_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7986a_data); -} - -static int mt7986b_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7986b_data); -} - -static struct platform_driver mt7986a_pinctrl_driver = { - .driver = { - .name = "mt7986a-pinctrl", - .of_match_table = mt7986a_pinctrl_of_match, - }, - .probe = mt7986a_pinctrl_probe, -}; - -static struct platform_driver mt7986b_pinctrl_driver = { - .driver = { - .name = "mt7986b-pinctrl", - .of_match_table = mt7986b_pinctrl_of_match, - }, - .probe = mt7986b_pinctrl_probe, -}; - -static int __init mt7986a_pinctrl_init(void) -{ - return platform_driver_register(&mt7986a_pinctrl_driver); -} - -static int __init mt7986b_pinctrl_init(void) -{ - return platform_driver_register(&mt7986b_pinctrl_driver); -} - -arch_initcall(mt7986a_pinctrl_init); -arch_initcall(mt7986b_pinctrl_init); diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c deleted file mode 100644 index 659c83e99..000000000 --- a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ /dev/null @@ -1,1466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7988 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -enum MT7988_PINCTRL_REG_PAGE { - GPIO_BASE, - IOCFG_TR_BASE, - IOCFG_BR_BASE, - IOCFG_RB_BASE, - IOCFG_LB_BASE, - IOCFG_TL_BASE, -}; - -#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { - PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { - PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { - PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { - PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), - - PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), - PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), - - PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), - PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), - PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), - PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), - PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), - PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), - PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), - PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - - PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), -}; - -static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7988_pins[] = { - MT7988_PIN(0, "UART2_RXD"), - MT7988_PIN(1, "UART2_TXD"), - MT7988_PIN(2, "UART2_CTS"), - MT7988_PIN(3, "UART2_RTS"), - MT7988_PIN(4, "GPIO_A"), - MT7988_PIN(5, "SMI_0_MDC"), - MT7988_PIN(6, "SMI_0_MDIO"), - MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), - MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), - MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), - MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), - MT7988_PIN(11, "GPIO_P"), - MT7988_PIN(12, "WATCHDOG"), - MT7988_PIN(13, "GPIO_RESET"), - MT7988_PIN(14, "GPIO_WPS"), - MT7988_PIN(15, "PMIC_I2C_SCL"), - MT7988_PIN(16, "PMIC_I2C_SDA"), - MT7988_PIN(17, "I2C_1_SCL"), - MT7988_PIN(18, "I2C_1_SDA"), - MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), - MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), - MT7988_PIN(21, "PWMD1"), - MT7988_PIN(22, "SPI0_WP"), - MT7988_PIN(23, "SPI0_HOLD"), - MT7988_PIN(24, "SPI0_CSB"), - MT7988_PIN(25, "SPI0_MISO"), - MT7988_PIN(26, "SPI0_MOSI"), - MT7988_PIN(27, "SPI0_CLK"), - MT7988_PIN(28, "SPI1_CSB"), - MT7988_PIN(29, "SPI1_MISO"), - MT7988_PIN(30, "SPI1_MOSI"), - MT7988_PIN(31, "SPI1_CLK"), - MT7988_PIN(32, "SPI2_CLK"), - MT7988_PIN(33, "SPI2_MOSI"), - MT7988_PIN(34, "SPI2_MISO"), - MT7988_PIN(35, "SPI2_CSB"), - MT7988_PIN(36, "SPI2_HOLD"), - MT7988_PIN(37, "SPI2_WP"), - MT7988_PIN(38, "EMMC_RSTB"), - MT7988_PIN(39, "EMMC_DSL"), - MT7988_PIN(40, "EMMC_CK"), - MT7988_PIN(41, "EMMC_CMD"), - MT7988_PIN(42, "EMMC_DATA_7"), - MT7988_PIN(43, "EMMC_DATA_6"), - MT7988_PIN(44, "EMMC_DATA_5"), - MT7988_PIN(45, "EMMC_DATA_4"), - MT7988_PIN(46, "EMMC_DATA_3"), - MT7988_PIN(47, "EMMC_DATA_2"), - MT7988_PIN(48, "EMMC_DATA_1"), - MT7988_PIN(49, "EMMC_DATA_0"), - MT7988_PIN(50, "PCM_FS_I2S_LRCK"), - MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), - MT7988_PIN(52, "PCM_DRX_I2S_DIN"), - MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), - MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), - MT7988_PIN(55, "UART0_RXD"), - MT7988_PIN(56, "UART0_TXD"), - MT7988_PIN(57, "PWMD0"), - MT7988_PIN(58, "JTAG_JTDI"), - MT7988_PIN(59, "JTAG_JTDO"), - MT7988_PIN(60, "JTAG_JTMS"), - MT7988_PIN(61, "JTAG_JTCLK"), - MT7988_PIN(62, "JTAG_JTRST_N"), - MT7988_PIN(63, "USB_DRV_VBUS_P1"), - MT7988_PIN(64, "LED_A"), - MT7988_PIN(65, "LED_B"), - MT7988_PIN(66, "LED_C"), - MT7988_PIN(67, "LED_D"), - MT7988_PIN(68, "LED_E"), - MT7988_PIN(69, "GPIO_B"), - MT7988_PIN(70, "GPIO_C"), - MT7988_PIN(71, "I2C_2_SCL"), - MT7988_PIN(72, "I2C_2_SDA"), - MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), - MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), - MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), - MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), - MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), - MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), - MT7988_PIN(79, "USB_DRV_VBUS_P0"), - MT7988_PIN(80, "UART1_RXD"), - MT7988_PIN(81, "UART1_TXD"), - MT7988_PIN(82, "UART1_CTS"), - MT7988_PIN(83, "UART1_RTS"), -}; - -/* jtag */ -static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; - -static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; - -static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; - -static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; - -static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; - -static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; - -/* int_usxgmii */ -static int mt7988_int_usxgmii_pins[] = { 2, 3 }; -static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; - -/* pwm */ -static int mt7988_pwm0_pins[] = { 57 }; -static int mt7988_pwm0_funcs[] = { 1 }; - -static int mt7988_pwm1_pins[] = { 21 }; -static int mt7988_pwm1_funcs[] = { 1 }; - -static int mt7988_pwm2_pins[] = { 80 }; -static int mt7988_pwm2_funcs[] = { 2 }; - -static int mt7988_pwm3_pins[] = { 81 }; -static int mt7988_pwm3_funcs[] = { 2 }; - -static int mt7988_pwm4_pins[] = { 82 }; -static int mt7988_pwm4_funcs[] = { 2 }; - -static int mt7988_pwm5_pins[] = { 83 }; -static int mt7988_pwm5_funcs[] = { 2 }; - -static int mt7988_pwm6_pins[] = { 69 }; -static int mt7988_pwm6_funcs[] = { 3 }; - -static int mt7988_pwm7_pins[] = { 70 }; -static int mt7988_pwm7_funcs[] = { 3 }; - -/* dfd */ -static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2c */ -static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_0_pins[] = { 5, 6 }; -static int mt7988_i2c0_0_funcs[] = { 2, 2 }; - -static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; - -static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_1_pins[] = { 15, 16 }; -static int mt7988_i2c0_1_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; - -static int mt7988_i2c1_0_pins[] = { 17, 18 }; -static int mt7988_i2c1_0_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; - -static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c1_2_pins[] = { 69, 70 }; -static int mt7988_i2c1_2_funcs[] = { 2, 2 }; - -static int mt7988_i2c2_0_pins[] = { 69, 70 }; -static int mt7988_i2c2_0_funcs[] = { 4, 4 }; - -static int mt7988_i2c2_1_pins[] = { 71, 72 }; -static int mt7988_i2c2_1_funcs[] = { 1, 1 }; - -/* eth */ -static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; - -static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; - -/* pcie */ -static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; - -static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; - -/* pmic */ -static int mt7988_pmic_pins[] = { 11 }; -static int mt7988_pmic_funcs[] = { 1 }; - -/* watchdog */ -static int mt7988_watchdog_pins[] = { 12 }; -static int mt7988_watchdog_funcs[] = { 1 }; - -/* spi */ -static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; - -static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; - -/* flash */ -static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -static int mt7988_emmc_45_pins[] = { - 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -}; -static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; - -static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; - -static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49 }; -static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* uart */ -static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; - -static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; - -static int mt7988_uart0_pins[] = { 55, 56 }; -static int mt7988_uart0_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; - -static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -static int mt7988_tops_uart1_2_funcs[] = { - 4, - 4, -}; - -static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; - -/* udi */ -static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2s */ -static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; - -/* pcm */ -static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; - -/* led */ -static int mt7988_gbe0_led1_pins[] = { 58 }; -static int mt7988_gbe0_led1_funcs[] = { 6 }; -static int mt7988_gbe1_led1_pins[] = { 59 }; -static int mt7988_gbe1_led1_funcs[] = { 6 }; -static int mt7988_gbe2_led1_pins[] = { 60 }; -static int mt7988_gbe2_led1_funcs[] = { 6 }; -static int mt7988_gbe3_led1_pins[] = { 61 }; -static int mt7988_gbe3_led1_funcs[] = { 6 }; - -static int mt7988_2p5gbe_led1_pins[] = { 62 }; -static int mt7988_2p5gbe_led1_funcs[] = { 6 }; - -static int mt7988_gbe0_led0_pins[] = { 64 }; -static int mt7988_gbe0_led0_funcs[] = { 1 }; -static int mt7988_gbe1_led0_pins[] = { 65 }; -static int mt7988_gbe1_led0_funcs[] = { 1 }; -static int mt7988_gbe2_led0_pins[] = { 66 }; -static int mt7988_gbe2_led0_funcs[] = { 1 }; -static int mt7988_gbe3_led0_pins[] = { 67 }; -static int mt7988_gbe3_led0_funcs[] = { 1 }; - -static int mt7988_2p5gbe_led0_pins[] = { 68 }; -static int mt7988_2p5gbe_led0_funcs[] = { 1 }; - -/* usb */ -static int mt7988_drv_vbus_p1_pins[] = { 63 }; -static int mt7988_drv_vbus_p1_funcs[] = { 1 }; - -static int mt7988_drv_vbus_pins[] = { 79 }; -static int mt7988_drv_vbus_funcs[] = { 1 }; - -static const struct group_desc mt7988_groups[] = { - /* @GPIO(0,1,2,3): uart2 */ - PINCTRL_PIN_GROUP("uart2", mt7988_uart2), - /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ - PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), - /* @GPIO(2,3): int_usxgmii */ - PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), - /* @GPIO(0,1,2,3,4): dfd */ - PINCTRL_PIN_GROUP("dfd", mt7988_dfd), - /* @GPIO(0,1): xfi_phy0_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), - /* @GPIO(0,1): xfi_phy1_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), - /* @GPIO(5,6) i2c0_0 */ - PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), - /* @GPIO(5,6) i2c1_sfp */ - PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), - /* @GPIO(5,6) xfi_pextp_phy0_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), - /* @GPIO(5,6) xfi_pextp_phy1_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), - /* @GPIO(5,6) mdc_mdio0 */ - PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), - /* @GPIO(7): pcie_wake_n0_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), - /* @GPIO(8): pcie_clk_req_n0_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), - /* @GPIO(9): pcie_wake_n3_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), - /* @GPIO(10): pcie_clk_req_n3 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), - /* @GPIO(10): pcie_clk_req_n0_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), - /* @GPIO(7,8) pcie_p0_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), - /* @GPIO(7,8) pcie_p1_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), - /* @GPIO(7,8) pcie_p2_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), - /* @GPIO(9,10) pcie_p3_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), - /* @GPIO(9,10) ckm_phy_i2c */ - PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), - /* @GPIO(11): pmic */ - PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), - /* @GPIO(12): watchdog */ - PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), - /* @GPIO(13): pcie_wake_n0_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), - /* @GPIO(14): pcie_wake_n3_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), - /* @GPIO(15,16) i2c0_1 */ - PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), - /* @GPIO(15,16) u30_phy_i2c0 */ - PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), - /* @GPIO(15,16) u32_phy_i2c0 */ - PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), - /* @GPIO(15,16) xfi_phy0_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), - /* @GPIO(15,16) xfi_phy1_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), - /* @GPIO(15,16) xfi_phy_pll_i2c2 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), - /* @GPIO(17,18) i2c1_0 */ - PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), - /* @GPIO(17,18) u30_phy_i2c1 */ - PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), - /* @GPIO(17,18) u32_phy_i2c1 */ - PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), - /* @GPIO(17,18) xfi_phy_pll_i2c3 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), - /* @GPIO(17,18) sgmii0_i2c */ - PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), - /* @GPIO(17,18) sgmii1_i2c */ - PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), - /* @GPIO(19): pcie_2l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), - /* @GPIO(20): pcie_1l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), - /* @GPIO(21): pwm1 */ - PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), - /* @GPIO(22,23) spi0_wp_hold */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), - /* @GPIO(24,25,26,27) spi0 */ - PINCTRL_PIN_GROUP("spi0", mt7988_spi0), - /* @GPIO(28,29,30,31) spi1 */ - PINCTRL_PIN_GROUP("spi1", mt7988_spi1), - /* @GPIO(32,33,34,35) spi2 */ - PINCTRL_PIN_GROUP("spi2", mt7988_spi2), - /* @GPIO(36,37) spi2_wp_hold */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), - /* @GPIO(22,23,24,25,26,27) snfi */ - PINCTRL_PIN_GROUP("snfi", mt7988_snfi), - /* @GPIO(22,23) tops_uart0_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), - /* @GPIO(28,29,30,31) uart2_0 */ - PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), - /* @GPIO(32,33,34,35) uart1_0 */ - PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), - /* @GPIO(32,33,34,35) uart2_1 */ - PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), - /* @GPIO(28) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(29) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(30) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(28,29) tops_uart1_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), - /* @GPIO(30,31) tops_uart0_1 */ - PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), - /* @GPIO(36,37) tops_uart1_1 */ - PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), - /* @GPIO(32,33,34,35,36) udi */ - PINCTRL_PIN_GROUP("udi", mt7988_udi), - /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ - PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), - /* @GPIO(32,33,34,35,36,37) sdcard */ - PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), - /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ - PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), - /* @GPIO(28,29) 2p5g_ext_mdio */ - PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), - /* @GPIO(30,31) gbe_ext_mdio */ - PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), - /* @GPIO(50,51,52,53,54) i2s */ - PINCTRL_PIN_GROUP("i2s", mt7988_i2s), - /* @GPIO(50,51,52,53) pcm */ - PINCTRL_PIN_GROUP("pcm", mt7988_pcm), - /* @GPIO(55,56) uart0 */ - PINCTRL_PIN_GROUP("uart0", mt7988_uart0), - /* @GPIO(55,56) tops_uart0_2 */ - PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), - /* @GPIO(50,51,52,53) uart2_2 */ - PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), - /* @GPIO(50,51,52,53,54) wo0_jtag */ - PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), - /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ - PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), - /* @GPIO(50,51,52,53,54) wo2_jtag */ - PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), - /* @GPIO(57) pwm0 */ - PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), - /* @GPIO(58,59,60,61,62) jtag */ - PINCTRL_PIN_GROUP("jtag", mt7988_jtag), - /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ - PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), - /* @GPIO(58,59,60,61) uart2_3 */ - PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), - /* @GPIO(58,59,60,61) uart1_1 */ - PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), - /* @GPIO(58,59,60,61) gbe_led1 */ - PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), - PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), - PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), - PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), - /* @GPIO(62) 2p5gbe_led1 */ - PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), - /* @GPIO(64,65,66,67) gbe_led0 */ - PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), - PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), - PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), - PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), - /* @GPIO(68) 2p5gbe_led0 */ - PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), - /* @GPIO(63) drv_vbus_p1 */ - PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), - /* @GPIO(63) pcie_clk_req_n2_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), - /* @GPIO(69, 70) mdc_mdio1 */ - PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), - /* @GPIO(69, 70) i2c1_2 */ - PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), - /* @GPIO(69) pwm6 */ - PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), - /* @GPIO(70) pwm7 */ - PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), - /* @GPIO(69,70) i2c2_0 */ - PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), - /* @GPIO(71,72) i2c2_1 */ - PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), - /* @GPIO(73) pcie_2l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), - /* @GPIO(74) pcie_1l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), - /* @GPIO(75) pcie_wake_n1_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), - /* @GPIO(76) pcie_clk_req_n1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), - /* @GPIO(77) pcie_wake_n2_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), - /* @GPIO(78) pcie_clk_req_n2_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), - /* @GPIO(79) drv_vbus */ - PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), - /* @GPIO(79) pcie_wake_n2_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), - /* @GPIO(80,81,82,83) uart1_2 */ - PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), - /* @GPIO(80) pwm2 */ - PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), - /* @GPIO(81) pwm3 */ - PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), - /* @GPIO(82) pwm4 */ - PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), - /* @GPIO(83) pwm5 */ - PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), - /* @GPIO(80) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(81) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(82) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(80,81) tops_uart1_2 */ - PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), - /* @GPIO(80) net_wo0_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), - /* @GPIO(81) net_wo1_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), - /* @GPIO(82) net_wo2_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char *mt7988_jtag_groups[] = { - "tops_jtag0_0", "wo0_jtag", "wo1_jtag", - "wo2_jtag", "jtag", "tops_jtag0_1", -}; -static const char *mt7988_int_usxgmii_groups[] = { - "int_usxgmii", -}; -static const char *mt7988_pwm_groups[] = { - "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" -}; -static const char *mt7988_dfd_groups[] = { - "dfd", -}; -static const char *mt7988_i2c_groups[] = { - "xfi_phy0_i2c0", - "xfi_phy1_i2c0", - "xfi_phy_pll_i2c0", - "xfi_phy_pll_i2c1", - "i2c0_0", - "i2c1_sfp", - "xfi_pextp_phy0_i2c", - "xfi_pextp_phy1_i2c", - "i2c0_1", - "u30_phy_i2c0", - "u32_phy_i2c0", - "xfi_phy0_i2c1", - "xfi_phy1_i2c1", - "xfi_phy_pll_i2c2", - "i2c1_0", - "u30_phy_i2c1", - "u32_phy_i2c1", - "xfi_phy_pll_i2c3", - "sgmii0_i2c", - "sgmii1_i2c", - "i2c1_2", - "i2c2_0", - "i2c2_1", -}; -static const char *mt7988_ethernet_groups[] = { - "mdc_mdio0", - "2p5g_ext_mdio", - "gbe_ext_mdio", - "mdc_mdio1", -}; -static const char *mt7988_pcie_groups[] = { - "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", - "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", - "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", - "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", - "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", - "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", - "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", - "pcie_clk_req_n0_1" -}; -static const char *mt7988_pmic_groups[] = { - "pmic", -}; -static const char *mt7988_wdt_groups[] = { - "watchdog", -}; -static const char *mt7988_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -}; -static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", - "emmc_51" }; -static const char *mt7988_uart_groups[] = { - "uart2", - "tops_uart0_0", - "uart2_0", - "uart1_0", - "uart2_1", - "net_wo0_uart_txd_0", - "net_wo1_uart_txd_0", - "net_wo2_uart_txd_0", - "tops_uart1_0", - "ops_uart0_1", - "ops_uart1_1", - "uart0", - "tops_uart0_2", - "uart1_1", - "uart2_3", - "uart1_2", - "tops_uart1_2", - "net_wo0_uart_txd_1", - "net_wo1_uart_txd_1", - "net_wo2_uart_txd_1", -}; -static const char *mt7988_udi_groups[] = { - "udi", -}; -static const char *mt7988_audio_groups[] = { - "i2s", "pcm", -}; -static const char *mt7988_led_groups[] = { - "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", - "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", - "wf5g_led0", "wf5g_led1", -}; -static const char *mt7988_usb_groups[] = { - "drv_vbus", - "drv_vbus_p1", -}; - -static const struct function_desc mt7988_functions[] = { - { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, - { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, - { "int_usxgmii", mt7988_int_usxgmii_groups, - ARRAY_SIZE(mt7988_int_usxgmii_groups) }, - { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, - { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, - { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, - { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, - { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, - { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, - { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, - { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, - { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, - { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, - { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, - { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, - { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, -}; - -static const struct mtk_eint_hw mt7988_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7988_pins), - .db_cnt = 16, -}; - -static const char *mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -}; - -static struct mtk_pin_soc mt7988_data = { - .reg_cal = mt7988_reg_cals, - .pins = mt7988_pins, - .npins = ARRAY_SIZE(mt7988_pins), - .grps = mt7988_groups, - .ngrps = ARRAY_SIZE(mt7988_groups), - .funcs = mt7988_functions, - .nfuncs = ARRAY_SIZE(mt7988_functions), - .eint_hw = &mt7988_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7988_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7988_pinctrl_of_match[] = { - { - .compatible = "mediatek,mt7988-pinctrl", - }, - {} -}; - -static int mt7988_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -} - -static struct platform_driver mt7988_pinctrl_driver = { - .driver = { - .name = "mt7988-pinctrl", - .of_match_table = mt7988_pinctrl_of_match, - }, - .probe = mt7988_pinctrl_probe, -}; - -static int __init mt7988_pinctrl_init(void) -{ - return platform_driver_register(&mt7988_pinctrl_driver); -} -arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h deleted file mode 100644 index 192f8cefb..000000000 --- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7981-clk.h +++ /dev/null @@ -1,215 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Wenzhen.Yu - * Author: Jianhui Zhao - * Author: Daniel Golle - */ - -#ifndef _DT_BINDINGS_CLK_MT7981_H -#define _DT_BINDINGS_CLK_MT7981_H - -/* TOPCKGEN */ -#define CLK_TOP_CB_CKSQ_40M 0 -#define CLK_TOP_CB_M_416M 1 -#define CLK_TOP_CB_M_D2 2 -#define CLK_TOP_CB_M_D3 3 -#define CLK_TOP_M_D3_D2 4 -#define CLK_TOP_CB_M_D4 5 -#define CLK_TOP_CB_M_D8 6 -#define CLK_TOP_M_D8_D2 7 -#define CLK_TOP_CB_MM_720M 8 -#define CLK_TOP_CB_MM_D2 9 -#define CLK_TOP_CB_MM_D3 10 -#define CLK_TOP_CB_MM_D3_D5 11 -#define CLK_TOP_CB_MM_D4 12 -#define CLK_TOP_CB_MM_D6 13 -#define CLK_TOP_MM_D6_D2 14 -#define CLK_TOP_CB_MM_D8 15 -#define CLK_TOP_CB_APLL2_196M 16 -#define CLK_TOP_APLL2_D2 17 -#define CLK_TOP_APLL2_D4 18 -#define CLK_TOP_NET1_2500M 19 -#define CLK_TOP_CB_NET1_D4 20 -#define CLK_TOP_CB_NET1_D5 21 -#define CLK_TOP_NET1_D5_D2 22 -#define CLK_TOP_NET1_D5_D4 23 -#define CLK_TOP_CB_NET1_D8 24 -#define CLK_TOP_NET1_D8_D2 25 -#define CLK_TOP_NET1_D8_D4 26 -#define CLK_TOP_CB_NET2_800M 27 -#define CLK_TOP_CB_NET2_D2 28 -#define CLK_TOP_CB_NET2_D4 29 -#define CLK_TOP_NET2_D4_D2 30 -#define CLK_TOP_NET2_D4_D4 31 -#define CLK_TOP_CB_NET2_D6 32 -#define CLK_TOP_CB_WEDMCU_208M 33 -#define CLK_TOP_CB_SGM_325M 34 -#define CLK_TOP_CKSQ_40M_D2 35 -#define CLK_TOP_CB_RTC_32K 36 -#define CLK_TOP_CB_RTC_32P7K 37 -#define CLK_TOP_USB_TX250M 38 -#define CLK_TOP_FAUD 39 -#define CLK_TOP_NFI1X 40 -#define CLK_TOP_USB_EQ_RX250M 41 -#define CLK_TOP_USB_CDR_CK 42 -#define CLK_TOP_USB_LN0_CK 43 -#define CLK_TOP_SPINFI_BCK 44 -#define CLK_TOP_SPI 45 -#define CLK_TOP_SPIM_MST 46 -#define CLK_TOP_UART_BCK 47 -#define CLK_TOP_PWM_BCK 48 -#define CLK_TOP_I2C_BCK 49 -#define CLK_TOP_PEXTP_TL 50 -#define CLK_TOP_EMMC_208M 51 -#define CLK_TOP_EMMC_400M 52 -#define CLK_TOP_DRAMC_REF 53 -#define CLK_TOP_DRAMC_MD32 54 -#define CLK_TOP_SYSAXI 55 -#define CLK_TOP_SYSAPB 56 -#define CLK_TOP_ARM_DB_MAIN 57 -#define CLK_TOP_AP2CNN_HOST 58 -#define CLK_TOP_NETSYS 59 -#define CLK_TOP_NETSYS_500M 60 -#define CLK_TOP_NETSYS_WED_MCU 61 -#define CLK_TOP_NETSYS_2X 62 -#define CLK_TOP_SGM_325M 63 -#define CLK_TOP_SGM_REG 64 -#define CLK_TOP_F26M 65 -#define CLK_TOP_EIP97B 66 -#define CLK_TOP_USB3_PHY 67 -#define CLK_TOP_AUD 68 -#define CLK_TOP_A1SYS 69 -#define CLK_TOP_AUD_L 70 -#define CLK_TOP_A_TUNER 71 -#define CLK_TOP_U2U3_REF 72 -#define CLK_TOP_U2U3_SYS 73 -#define CLK_TOP_U2U3_XHCI 74 -#define CLK_TOP_USB_FRMCNT 75 -#define CLK_TOP_NFI1X_SEL 76 -#define CLK_TOP_SPINFI_SEL 77 -#define CLK_TOP_SPI_SEL 78 -#define CLK_TOP_SPIM_MST_SEL 79 -#define CLK_TOP_UART_SEL 80 -#define CLK_TOP_PWM_SEL 81 -#define CLK_TOP_I2C_SEL 82 -#define CLK_TOP_PEXTP_TL_SEL 83 -#define CLK_TOP_EMMC_208M_SEL 84 -#define CLK_TOP_EMMC_400M_SEL 85 -#define CLK_TOP_F26M_SEL 86 -#define CLK_TOP_DRAMC_SEL 87 -#define CLK_TOP_DRAMC_MD32_SEL 88 -#define CLK_TOP_SYSAXI_SEL 89 -#define CLK_TOP_SYSAPB_SEL 90 -#define CLK_TOP_ARM_DB_MAIN_SEL 91 -#define CLK_TOP_AP2CNN_HOST_SEL 92 -#define CLK_TOP_NETSYS_SEL 93 -#define CLK_TOP_NETSYS_500M_SEL 94 -#define CLK_TOP_NETSYS_MCU_SEL 95 -#define CLK_TOP_NETSYS_2X_SEL 96 -#define CLK_TOP_SGM_325M_SEL 97 -#define CLK_TOP_SGM_REG_SEL 98 -#define CLK_TOP_EIP97B_SEL 99 -#define CLK_TOP_USB3_PHY_SEL 100 -#define CLK_TOP_AUD_SEL 101 -#define CLK_TOP_A1SYS_SEL 102 -#define CLK_TOP_AUD_L_SEL 103 -#define CLK_TOP_A_TUNER_SEL 104 -#define CLK_TOP_U2U3_SEL 105 -#define CLK_TOP_U2U3_SYS_SEL 106 -#define CLK_TOP_U2U3_XHCI_SEL 107 -#define CLK_TOP_USB_FRMCNT_SEL 108 -#define CLK_TOP_AUD_I2S_M 109 - -/* INFRACFG */ -#define CLK_INFRA_66M_MCK 0 -#define CLK_INFRA_UART0_SEL 1 -#define CLK_INFRA_UART1_SEL 2 -#define CLK_INFRA_UART2_SEL 3 -#define CLK_INFRA_SPI0_SEL 4 -#define CLK_INFRA_SPI1_SEL 5 -#define CLK_INFRA_SPI2_SEL 6 -#define CLK_INFRA_PWM1_SEL 7 -#define CLK_INFRA_PWM2_SEL 8 -#define CLK_INFRA_PWM3_SEL 9 -#define CLK_INFRA_PWM_BSEL 10 -#define CLK_INFRA_PCIE_SEL 11 -#define CLK_INFRA_GPT_STA 12 -#define CLK_INFRA_PWM_HCK 13 -#define CLK_INFRA_PWM_STA 14 -#define CLK_INFRA_PWM1_CK 15 -#define CLK_INFRA_PWM2_CK 16 -#define CLK_INFRA_PWM3_CK 17 -#define CLK_INFRA_CQ_DMA_CK 18 -#define CLK_INFRA_AUD_BUS_CK 19 -#define CLK_INFRA_AUD_26M_CK 20 -#define CLK_INFRA_AUD_L_CK 21 -#define CLK_INFRA_AUD_AUD_CK 22 -#define CLK_INFRA_AUD_EG2_CK 23 -#define CLK_INFRA_DRAMC_26M_CK 24 -#define CLK_INFRA_DBG_CK 25 -#define CLK_INFRA_AP_DMA_CK 26 -#define CLK_INFRA_SEJ_CK 27 -#define CLK_INFRA_SEJ_13M_CK 28 -#define CLK_INFRA_THERM_CK 29 -#define CLK_INFRA_I2C0_CK 30 -#define CLK_INFRA_UART0_CK 31 -#define CLK_INFRA_UART1_CK 32 -#define CLK_INFRA_UART2_CK 33 -#define CLK_INFRA_SPI2_CK 34 -#define CLK_INFRA_SPI2_HCK_CK 35 -#define CLK_INFRA_NFI1_CK 36 -#define CLK_INFRA_SPINFI1_CK 37 -#define CLK_INFRA_NFI_HCK_CK 38 -#define CLK_INFRA_SPI0_CK 39 -#define CLK_INFRA_SPI1_CK 40 -#define CLK_INFRA_SPI0_HCK_CK 41 -#define CLK_INFRA_SPI1_HCK_CK 42 -#define CLK_INFRA_FRTC_CK 43 -#define CLK_INFRA_MSDC_CK 44 -#define CLK_INFRA_MSDC_HCK_CK 45 -#define CLK_INFRA_MSDC_133M_CK 46 -#define CLK_INFRA_MSDC_66M_CK 47 -#define CLK_INFRA_ADC_26M_CK 48 -#define CLK_INFRA_ADC_FRC_CK 49 -#define CLK_INFRA_FBIST2FPC_CK 50 -#define CLK_INFRA_I2C_MCK_CK 51 -#define CLK_INFRA_I2C_PCK_CK 52 -#define CLK_INFRA_IUSB_133_CK 53 -#define CLK_INFRA_IUSB_66M_CK 54 -#define CLK_INFRA_IUSB_SYS_CK 55 -#define CLK_INFRA_IUSB_CK 56 -#define CLK_INFRA_IPCIE_CK 57 -#define CLK_INFRA_IPCIE_PIPE_CK 58 -#define CLK_INFRA_IPCIER_CK 59 -#define CLK_INFRA_IPCIEB_CK 60 - -/* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - -/* SGMIISYS_0 */ -#define CLK_SGM0_TX_EN 0 -#define CLK_SGM0_RX_EN 1 -#define CLK_SGM0_CK0_EN 2 -#define CLK_SGM0_CDR_CK0_EN 3 - -/* SGMIISYS_1 */ -#define CLK_SGM1_TX_EN 0 -#define CLK_SGM1_RX_EN 1 -#define CLK_SGM1_CK1_EN 2 -#define CLK_SGM1_CDR_CK1_EN 3 - -/* ETHSYS */ -#define CLK_ETH_FE_EN 0 -#define CLK_ETH_GP2_EN 1 -#define CLK_ETH_GP1_EN 2 -#define CLK_ETH_WOCPU0_EN 3 - -#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h deleted file mode 100644 index 77cfea4a8..000000000 --- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#ifndef _DT_BINDINGS_CLK_MT7988_H -#define _DT_BINDINGS_CLK_MT7988_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_NETSYSPLL 0 -#define CLK_APMIXED_MPLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_APLL2 3 -#define CLK_APMIXED_NET1PLL 4 -#define CLK_APMIXED_NET2PLL 5 -#define CLK_APMIXED_WEDMCUPLL 6 -#define CLK_APMIXED_SGMPLL 7 -#define CLK_APMIXED_ARM_B 8 -#define CLK_APMIXED_CCIPLL2_B 9 -#define CLK_APMIXED_USXGMIIPLL 10 -#define CLK_APMIXED_MSDCPLL 11 - -/* TOPCKGEN */ - -#define CLK_TOP_XTAL 0 -#define CLK_TOP_XTAL_D2 1 -#define CLK_TOP_RTC_32K 2 -#define CLK_TOP_RTC_32P7K 3 -#define CLK_TOP_MPLL_D2 4 -#define CLK_TOP_MPLL_D3_D2 5 -#define CLK_TOP_MPLL_D4 6 -#define CLK_TOP_MPLL_D8 7 -#define CLK_TOP_MPLL_D8_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D3_D5 10 -#define CLK_TOP_MMPLL_D4 11 -#define CLK_TOP_MMPLL_D6_D2 12 -#define CLK_TOP_MMPLL_D8 13 -#define CLK_TOP_APLL2_D4 14 -#define CLK_TOP_NET1PLL_D4 15 -#define CLK_TOP_NET1PLL_D5 16 -#define CLK_TOP_NET1PLL_D5_D2 17 -#define CLK_TOP_NET1PLL_D5_D4 18 -#define CLK_TOP_NET1PLL_D8 19 -#define CLK_TOP_NET1PLL_D8_D2 20 -#define CLK_TOP_NET1PLL_D8_D4 21 -#define CLK_TOP_NET1PLL_D8_D8 22 -#define CLK_TOP_NET1PLL_D8_D16 23 -#define CLK_TOP_NET2PLL_D2 24 -#define CLK_TOP_NET2PLL_D4 25 -#define CLK_TOP_NET2PLL_D4_D4 26 -#define CLK_TOP_NET2PLL_D4_D8 27 -#define CLK_TOP_NET2PLL_D6 28 -#define CLK_TOP_NET2PLL_D8 29 -#define CLK_TOP_NETSYS_SEL 30 -#define CLK_TOP_NETSYS_500M_SEL 31 -#define CLK_TOP_NETSYS_2X_SEL 32 -#define CLK_TOP_NETSYS_GSW_SEL 33 -#define CLK_TOP_ETH_GMII_SEL 34 -#define CLK_TOP_NETSYS_MCU_SEL 35 -#define CLK_TOP_NETSYS_PAO_2X_SEL 36 -#define CLK_TOP_EIP197_SEL 37 -#define CLK_TOP_AXI_INFRA_SEL 38 -#define CLK_TOP_UART_SEL 39 -#define CLK_TOP_EMMC_250M_SEL 40 -#define CLK_TOP_EMMC_400M_SEL 41 -#define CLK_TOP_SPI_SEL 42 -#define CLK_TOP_SPIM_MST_SEL 43 -#define CLK_TOP_NFI1X_SEL 44 -#define CLK_TOP_SPINFI_SEL 45 -#define CLK_TOP_PWM_SEL 46 -#define CLK_TOP_I2C_SEL 47 -#define CLK_TOP_PCIE_MBIST_250M_SEL 48 -#define CLK_TOP_PEXTP_TL_SEL 49 -#define CLK_TOP_PEXTP_TL_P1_SEL 50 -#define CLK_TOP_PEXTP_TL_P2_SEL 51 -#define CLK_TOP_PEXTP_TL_P3_SEL 52 -#define CLK_TOP_USB_SYS_SEL 53 -#define CLK_TOP_USB_SYS_P1_SEL 54 -#define CLK_TOP_USB_XHCI_SEL 55 -#define CLK_TOP_USB_XHCI_P1_SEL 56 -#define CLK_TOP_USB_FRMCNT_SEL 57 -#define CLK_TOP_USB_FRMCNT_P1_SEL 58 -#define CLK_TOP_AUD_SEL 59 -#define CLK_TOP_A1SYS_SEL 60 -#define CLK_TOP_AUD_L_SEL 61 -#define CLK_TOP_A_TUNER_SEL 62 -#define CLK_TOP_SSPXTP_SEL 63 -#define CLK_TOP_USB_PHY_SEL 64 -#define CLK_TOP_USXGMII_SBUS_0_SEL 65 -#define CLK_TOP_USXGMII_SBUS_1_SEL 66 -#define CLK_TOP_SGM_0_SEL 67 -#define CLK_TOP_SGM_SBUS_0_SEL 68 -#define CLK_TOP_SGM_1_SEL 69 -#define CLK_TOP_SGM_SBUS_1_SEL 70 -#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 -#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 -#define CLK_TOP_SYSAXI_SEL 73 -#define CLK_TOP_SYSAPB_SEL 74 -#define CLK_TOP_ETH_REFCK_50M_SEL 75 -#define CLK_TOP_ETH_SYS_200M_SEL 76 -#define CLK_TOP_ETH_SYS_SEL 77 -#define CLK_TOP_ETH_XGMII_SEL 78 -#define CLK_TOP_BUS_TOPS_SEL 79 -#define CLK_TOP_NPU_TOPS_SEL 80 -#define CLK_TOP_DRAMC_SEL 81 -#define CLK_TOP_DRAMC_MD32_SEL 82 -#define CLK_TOP_INFRA_F26M_SEL 83 -#define CLK_TOP_PEXTP_P0_SEL 84 -#define CLK_TOP_PEXTP_P1_SEL 85 -#define CLK_TOP_PEXTP_P2_SEL 86 -#define CLK_TOP_PEXTP_P3_SEL 87 -#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 -#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 -#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 -#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 -#define CLK_TOP_CKM_SEL 92 -#define CLK_TOP_DA_SEL 93 -#define CLK_TOP_PEXTP_SEL 94 -#define CLK_TOP_TOPS_P2_26M_SEL 95 -#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 -#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 -#define CLK_TOP_MACSEC_SEL 98 -#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 -#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 -#define CLK_TOP_NETSYS_WARP_SEL 101 -#define CLK_TOP_ETH_MII_SEL 102 -#define CLK_TOP_NPU_SEL 103 -#define CLK_TOP_AUD_I2S_M 104 - -/* MCUSYS */ - -#define CLK_MCU_BUS_DIV_SEL 0 -#define CLK_MCU_ARM_DIV_SEL 1 - -/* INFRACFG_AO */ - -#define CLK_INFRA_MUX_UART0_SEL 0 -#define CLK_INFRA_MUX_UART1_SEL 1 -#define CLK_INFRA_MUX_UART2_SEL 2 -#define CLK_INFRA_MUX_SPI0_SEL 3 -#define CLK_INFRA_MUX_SPI1_SEL 4 -#define CLK_INFRA_MUX_SPI2_SEL 5 -#define CLK_INFRA_PWM_SEL 6 -#define CLK_INFRA_PWM_CK1_SEL 7 -#define CLK_INFRA_PWM_CK2_SEL 8 -#define CLK_INFRA_PWM_CK3_SEL 9 -#define CLK_INFRA_PWM_CK4_SEL 10 -#define CLK_INFRA_PWM_CK5_SEL 11 -#define CLK_INFRA_PWM_CK6_SEL 12 -#define CLK_INFRA_PWM_CK7_SEL 13 -#define CLK_INFRA_PWM_CK8_SEL 14 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 - -/* INFRACFG */ - -#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 -#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 -#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 -#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 -#define CLK_INFRA_66M_GPT_BCK 23 -#define CLK_INFRA_66M_PWM_HCK 24 -#define CLK_INFRA_66M_PWM_BCK 25 -#define CLK_INFRA_66M_PWM_CK1 26 -#define CLK_INFRA_66M_PWM_CK2 27 -#define CLK_INFRA_66M_PWM_CK3 28 -#define CLK_INFRA_66M_PWM_CK4 29 -#define CLK_INFRA_66M_PWM_CK5 30 -#define CLK_INFRA_66M_PWM_CK6 31 -#define CLK_INFRA_66M_PWM_CK7 32 -#define CLK_INFRA_66M_PWM_CK8 33 -#define CLK_INFRA_133M_CQDMA_BCK 34 -#define CLK_INFRA_66M_AUD_SLV_BCK 35 -#define CLK_INFRA_AUD_26M 36 -#define CLK_INFRA_AUD_L 37 -#define CLK_INFRA_AUD_AUD 38 -#define CLK_INFRA_AUD_EG2 39 -#define CLK_INFRA_DRAMC_F26M 40 -#define CLK_INFRA_133M_DBG_ACKM 41 -#define CLK_INFRA_66M_AP_DMA_BCK 42 -#define CLK_INFRA_66M_SEJ_BCK 43 -#define CLK_INFRA_PRE_CK_SEJ_F13M 44 -#define CLK_INFRA_26M_THERM_SYSTEM 45 -#define CLK_INFRA_I2C_BCK 46 -#define CLK_INFRA_52M_UART0_CK 47 -#define CLK_INFRA_52M_UART1_CK 48 -#define CLK_INFRA_52M_UART2_CK 49 -#define CLK_INFRA_NFI 50 -#define CLK_INFRA_SPINFI 51 -#define CLK_INFRA_66M_NFI_HCK 52 -#define CLK_INFRA_104M_SPI0 53 -#define CLK_INFRA_104M_SPI1 54 -#define CLK_INFRA_104M_SPI2_BCK 55 -#define CLK_INFRA_66M_SPI0_HCK 56 -#define CLK_INFRA_66M_SPI1_HCK 57 -#define CLK_INFRA_66M_SPI2_HCK 58 -#define CLK_INFRA_66M_FLASHIF_AXI 59 -#define CLK_INFRA_RTC 60 -#define CLK_INFRA_26M_ADC_BCK 61 -#define CLK_INFRA_RC_ADC 62 -#define CLK_INFRA_MSDC400 63 -#define CLK_INFRA_MSDC2_HCK 64 -#define CLK_INFRA_133M_MSDC_0_HCK 65 -#define CLK_INFRA_66M_MSDC_0_HCK 66 -#define CLK_INFRA_133M_CPUM_BCK 67 -#define CLK_INFRA_BIST2FPC 68 -#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 -#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 -#define CLK_INFRA_133M_USB_HCK 71 -#define CLK_INFRA_133M_USB_HCK_CK_P1 72 -#define CLK_INFRA_66M_USB_HCK 73 -#define CLK_INFRA_66M_USB_HCK_CK_P1 74 -#define CLK_INFRA_USB_SYS 75 -#define CLK_INFRA_USB_SYS_CK_P1 76 -#define CLK_INFRA_USB_REF 77 -#define CLK_INFRA_USB_CK_P1 78 -#define CLK_INFRA_USB_FRMCNT 79 -#define CLK_INFRA_USB_FRMCNT_CK_P1 80 -#define CLK_INFRA_USB_PIPE 81 -#define CLK_INFRA_USB_PIPE_CK_P1 82 -#define CLK_INFRA_USB_UTMI 83 -#define CLK_INFRA_USB_UTMI_CK_P1 84 -#define CLK_INFRA_USB_XHCI 85 -#define CLK_INFRA_USB_XHCI_CK_P1 86 -#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 -#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 -#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 -#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 -#define CLK_INFRA_PCIE_PIPE_P0 91 -#define CLK_INFRA_PCIE_PIPE_P1 92 -#define CLK_INFRA_PCIE_PIPE_P2 93 -#define CLK_INFRA_PCIE_PIPE_P3 94 -#define CLK_INFRA_133M_PCIE_CK_P0 95 -#define CLK_INFRA_133M_PCIE_CK_P1 96 -#define CLK_INFRA_133M_PCIE_CK_P2 97 -#define CLK_INFRA_133M_PCIE_CK_P3 98 - -/* ETHDMA */ - -#define CLK_ETHDMA_XGP1_EN 0 -#define CLK_ETHDMA_XGP2_EN 1 -#define CLK_ETHDMA_XGP3_EN 2 -#define CLK_ETHDMA_FE_EN 3 -#define CLK_ETHDMA_GP2_EN 4 -#define CLK_ETHDMA_GP1_EN 5 -#define CLK_ETHDMA_GP3_EN 6 -#define CLK_ETHDMA_ESW_EN 7 -#define CLK_ETHDMA_CRYPT0_EN 8 -#define CLK_ETHDMA_NR_CLK 9 - -/* SGMIISYS_0 */ - -#define CLK_SGM0_TX_EN 0 -#define CLK_SGM0_RX_EN 1 -#define CLK_SGMII0_NR_CLK 2 - -/* SGMIISYS_1 */ - -#define CLK_SGM1_TX_EN 0 -#define CLK_SGM1_RX_EN 1 -#define CLK_SGMII1_NR_CLK 2 - -/* ETHWARP */ - -#define CLK_ETHWARP_WOCPU2_EN 0 -#define CLK_ETHWARP_WOCPU1_EN 1 -#define CLK_ETHWARP_WOCPU0_EN 2 -#define CLK_ETHWARP_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h deleted file mode 100644 index 5a9b16932..000000000 --- a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mt7986-clk.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Sam Shih - */ - -#ifndef _DT_BINDINGS_CLK_MT7986_H -#define _DT_BINDINGS_CLK_MT7986_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - -/* TOPCKGEN */ - -#define CLK_TOP_XTAL 0 -#define CLK_TOP_XTAL_D2 1 -#define CLK_TOP_RTC_32K 2 -#define CLK_TOP_RTC_32P7K 3 -#define CLK_TOP_MPLL_D2 4 -#define CLK_TOP_MPLL_D4 5 -#define CLK_TOP_MPLL_D8 6 -#define CLK_TOP_MPLL_D8_D2 7 -#define CLK_TOP_MPLL_D3_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D4 10 -#define CLK_TOP_MMPLL_D8 11 -#define CLK_TOP_MMPLL_D8_D2 12 -#define CLK_TOP_MMPLL_D3_D8 13 -#define CLK_TOP_MMPLL_U2PHY 14 -#define CLK_TOP_APLL2_D4 15 -#define CLK_TOP_NET1PLL_D4 16 -#define CLK_TOP_NET1PLL_D5 17 -#define CLK_TOP_NET1PLL_D5_D2 18 -#define CLK_TOP_NET1PLL_D5_D4 19 -#define CLK_TOP_NET1PLL_D8_D2 20 -#define CLK_TOP_NET1PLL_D8_D4 21 -#define CLK_TOP_NET2PLL_D4 22 -#define CLK_TOP_NET2PLL_D4_D2 23 -#define CLK_TOP_NET2PLL_D3_D2 24 -#define CLK_TOP_WEDMCUPLL_D5_D2 25 -#define CLK_TOP_NFI1X_SEL 26 -#define CLK_TOP_SPINFI_SEL 27 -#define CLK_TOP_SPI_SEL 28 -#define CLK_TOP_SPIM_MST_SEL 29 -#define CLK_TOP_UART_SEL 30 -#define CLK_TOP_PWM_SEL 31 -#define CLK_TOP_I2C_SEL 32 -#define CLK_TOP_PEXTP_TL_SEL 33 -#define CLK_TOP_EMMC_250M_SEL 34 -#define CLK_TOP_EMMC_416M_SEL 35 -#define CLK_TOP_F_26M_ADC_SEL 36 -#define CLK_TOP_DRAMC_SEL 37 -#define CLK_TOP_DRAMC_MD32_SEL 38 -#define CLK_TOP_SYSAXI_SEL 39 -#define CLK_TOP_SYSAPB_SEL 40 -#define CLK_TOP_ARM_DB_MAIN_SEL 41 -#define CLK_TOP_ARM_DB_JTSEL 42 -#define CLK_TOP_NETSYS_SEL 43 -#define CLK_TOP_NETSYS_500M_SEL 44 -#define CLK_TOP_NETSYS_MCU_SEL 45 -#define CLK_TOP_NETSYS_2X_SEL 46 -#define CLK_TOP_SGM_325M_SEL 47 -#define CLK_TOP_SGM_REG_SEL 48 -#define CLK_TOP_A1SYS_SEL 49 -#define CLK_TOP_CONN_MCUSYS_SEL 50 -#define CLK_TOP_EIP_B_SEL 51 -#define CLK_TOP_PCIE_PHY_SEL 52 -#define CLK_TOP_USB3_PHY_SEL 53 -#define CLK_TOP_F26M_SEL 54 -#define CLK_TOP_AUD_L_SEL 55 -#define CLK_TOP_A_TUNER_SEL 56 -#define CLK_TOP_U2U3_SEL 57 -#define CLK_TOP_U2U3_SYS_SEL 58 -#define CLK_TOP_U2U3_XHCI_SEL 59 -#define CLK_TOP_DA_U2_REFSEL 60 -#define CLK_TOP_DA_U2_CK_1P_SEL 61 -#define CLK_TOP_AP2CNN_HOST_SEL 62 -#define CLK_TOP_JTAG 63 - -/* INFRACFG */ - -#define CLK_INFRA_SYSAXI_D2 0 -#define CLK_INFRA_UART0_SEL 1 -#define CLK_INFRA_UART1_SEL 2 -#define CLK_INFRA_UART2_SEL 3 -#define CLK_INFRA_SPI0_SEL 4 -#define CLK_INFRA_SPI1_SEL 5 -#define CLK_INFRA_PWM1_SEL 6 -#define CLK_INFRA_PWM2_SEL 7 -#define CLK_INFRA_PWM_BSEL 8 -#define CLK_INFRA_PCIE_SEL 9 -#define CLK_INFRA_GPT_STA 10 -#define CLK_INFRA_PWM_HCK 11 -#define CLK_INFRA_PWM_STA 12 -#define CLK_INFRA_PWM1_CK 13 -#define CLK_INFRA_PWM2_CK 14 -#define CLK_INFRA_CQ_DMA_CK 15 -#define CLK_INFRA_EIP97_CK 16 -#define CLK_INFRA_AUD_BUS_CK 17 -#define CLK_INFRA_AUD_26M_CK 18 -#define CLK_INFRA_AUD_L_CK 19 -#define CLK_INFRA_AUD_AUD_CK 20 -#define CLK_INFRA_AUD_EG2_CK 21 -#define CLK_INFRA_DRAMC_26M_CK 22 -#define CLK_INFRA_DBG_CK 23 -#define CLK_INFRA_AP_DMA_CK 24 -#define CLK_INFRA_SEJ_CK 25 -#define CLK_INFRA_SEJ_13M_CK 26 -#define CLK_INFRA_THERM_CK 27 -#define CLK_INFRA_I2C0_CK 28 -#define CLK_INFRA_UART0_CK 29 -#define CLK_INFRA_UART1_CK 30 -#define CLK_INFRA_UART2_CK 31 -#define CLK_INFRA_NFI1_CK 32 -#define CLK_INFRA_SPINFI1_CK 33 -#define CLK_INFRA_NFI_HCK_CK 34 -#define CLK_INFRA_SPI0_CK 35 -#define CLK_INFRA_SPI1_CK 36 -#define CLK_INFRA_SPI0_HCK_CK 37 -#define CLK_INFRA_SPI1_HCK_CK 38 -#define CLK_INFRA_FRTC_CK 39 -#define CLK_INFRA_MSDC_CK 40 -#define CLK_INFRA_MSDC_HCK_CK 41 -#define CLK_INFRA_MSDC_133M_CK 42 -#define CLK_INFRA_MSDC_66M_CK 43 -#define CLK_INFRA_ADC_26M_CK 44 -#define CLK_INFRA_ADC_FRC_CK 45 -#define CLK_INFRA_FBIST2FPC_CK 46 -#define CLK_INFRA_IUSB_133_CK 47 -#define CLK_INFRA_IUSB_66M_CK 48 -#define CLK_INFRA_IUSB_SYS_CK 49 -#define CLK_INFRA_IUSB_CK 50 -#define CLK_INFRA_IPCIE_CK 51 -#define CLK_INFRA_IPCIE_PIPE_CK 52 -#define CLK_INFRA_IPCIER_CK 53 -#define CLK_INFRA_IPCIEB_CK 54 -#define CLK_INFRA_TRNG_CK 55 - -/* SGMIISYS_0 */ - -#define CLK_SGMII0_TX250M_EN 0 -#define CLK_SGMII0_RX250M_EN 1 -#define CLK_SGMII0_CDR_REF 2 -#define CLK_SGMII0_CDR_FB 3 - -/* SGMIISYS_1 */ - -#define CLK_SGMII1_TX250M_EN 0 -#define CLK_SGMII1_RX250M_EN 1 -#define CLK_SGMII1_CDR_REF 2 -#define CLK_SGMII1_CDR_FB 3 - -/* ETHSYS */ - -#define CLK_ETH_FE_EN 0 -#define CLK_ETH_GP2_EN 1 -#define CLK_ETH_GP1_EN 2 -#define CLK_ETH_WOCPU1_EN 3 -#define CLK_ETH_WOCPU0_EN 4 - -#endif /* _DT_BINDINGS_CLK_MT7986_H */ diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h b/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h deleted file mode 100644 index af3d16c81..000000000 --- a/target/linux/mediatek/files-5.15/include/dt-bindings/reset/mt7986-resets.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Sam Shih - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 - -/* INFRACFG resets */ -#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 -#define MT7986_INFRACFG_SSUSB_SW_RST 7 -#define MT7986_INFRACFG_EIP97_SW_RST 8 -#define MT7986_INFRACFG_AUDIO_SW_RST 13 -#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 - -#define MT7986_INFRACFG_TRNG_SW_RST 17 -#define MT7986_INFRACFG_AP_DMA_SW_RST 32 -#define MT7986_INFRACFG_I2C_SW_RST 33 -#define MT7986_INFRACFG_NFI_SW_RST 34 -#define MT7986_INFRACFG_SPI0_SW_RST 35 -#define MT7986_INFRACFG_SPI1_SW_RST 36 -#define MT7986_INFRACFG_UART0_SW_RST 37 -#define MT7986_INFRACFG_UART1_SW_RST 38 -#define MT7986_INFRACFG_UART2_SW_RST 39 -#define MT7986_INFRACFG_AUXADC_SW_RST 43 - -#define MT7986_INFRACFG_APXGPT_SW_RST 66 -#define MT7986_INFRACFG_PWM_SW_RST 68 - -#define MT7986_INFRACFG_SW_RST_NUM 69 - -/* TOPRGU resets */ -#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 -#define MT7986_TOPRGU_SGMII0_SW_RST 1 -#define MT7986_TOPRGU_SGMII1_SW_RST 2 -#define MT7986_TOPRGU_INFRA_SW_RST 3 -#define MT7986_TOPRGU_U2PHY_SW_RST 5 -#define MT7986_TOPRGU_PCIE_SW_RST 6 -#define MT7986_TOPRGU_SSUSB_SW_RST 7 -#define MT7986_TOPRGU_ETHDMA_SW_RST 20 -#define MT7986_TOPRGU_CONSYS_SW_RST 23 - -#define MT7986_TOPRGU_SW_RST_NUM 24 - -/* ETHSYS Subsystem resets */ -#define MT7986_ETHSYS_FE_SW_RST 6 -#define MT7986_ETHSYS_PMTR_SW_RST 8 -#define MT7986_ETHSYS_GMAC_SW_RST 23 -#define MT7986_ETHSYS_PPE0_SW_RST 30 -#define MT7986_ETHSYS_PPE1_SW_RST 31 - -#define MT7986_ETHSYS_SW_RST_NUM 32 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi deleted file mode 100644 index 05d4b7d91..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ /dev/null @@ -1,808 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Sam.Shih - * Author: Jianhui Zhao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7981"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - }; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ - cooling-levels = <0 128 192 255>; - #cooling-cells = <2>; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* passive: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", - "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; - #io-channel-cells = <1>; - }; - - wdma: wdma@15104800 { - compatible = "mediatek,wed-wdma"; - reg = <0 0x15104800 0 0x400>, - <0 0x15104c00 0 0x400>; - }; - - ap2woccif: ap2woccif@151a5000 { - compatible = "mediatek,ap2woccif"; - reg = <0 0x151a5000 0 0x1000>, - <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = , - ; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 64 KiB reserved for ramoops/pstore */ - ramoops@42ff0000 { - compatible = "ramoops"; - reg = <0 0x42ff0000 0 0x10000>; - record-size = <0x1000>; - }; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@47c80000 { - reg = <0 0x47c80000 0 0x100000>; - no-map; - }; - - wo_emi0: wo-emi@47d80000 { - reg = <0 0x47d80000 0 0x40000>; - no-map; - }; - - wo_data: wo-data@47dc0000 { - reg = <0 0x47dc0000 0 0x240000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - trng { - compatible = "mediatek,mt7981-rng"; - }; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7981-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@1001B000 { - compatible = "mediatek,mt7981-topckgen", "syscon"; - reg = <0 0x1001B000 0 0x1000>; - #clock-cells = <1>; - }; - - apmixedsys: apmixedsys@1001E000 { - compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - clock-frequency = <13000000>; - interrupts = , - , - , - ; - - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>; /* GICR */ - - interrupts = ; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, - <&infracfg CLK_INFRA_I2C_PCK_CK>; - clock-names = "main", "dma", "arb", "pmic"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7981-pcie", - "mediatek,mt7986-pcie"; - device_type = "pci"; - reg = <0 0x11280000 0 0x4000>; - reg-names = "pcie-mac"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 - 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - clocks = <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&topckgen CLK_TOP_EIP97B>; - clock-names = "top_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; - }; - - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, - <0 0x11c00000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rm", - "iocfg_rb", "iocfg_lb", "iocfg_bl", - "iocfg_tm", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 56>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio_pins: mdc-mdio-pins { - mux { - function = "eth"; - groups = "smi_mdc_mdio"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - wifi_dbdc_pins: wifi-dbdc-pins { - mux { - function = "eth"; - groups = "wf0_mode1"; - }; - conf { - pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", - "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", - "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", - "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", - "WF_CBA_RESETB", "WF_DIG_RESETB"; - drive-strength = <4>; - }; - }; - - gbe_led0_pins: gbe-led0-pins { - mux { - function = "led"; - groups = "gbe_led0"; - }; - }; - - gbe_led1_pins: gbe-led1-pins { - mux { - function = "led"; - groups = "gbe_led1"; - }; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7981-ethsys", - "mediatek,mt7986-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - wed: wed@15010000 { - compatible = "mediatek,mt7981-wed", - "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7981-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys0 CLK_SGM0_CK0_EN>, - <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <&sgmiisys1 CLK_SGM1_CK1_EN>, - <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, - <&topckgen CLK_TOP_SGM_REG>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, - <&topckgen CLK_TOP_CB_SGM_325M>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - phy-mode = "gmii"; - phy-is-integrated; - nvmem-cells = <&phy_calibration>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy_led0: int-gbe-phy-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - int_gbe_phy_led1: int-gbe-phy-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - wo_dlm0: syscon@151e8000 { - compatible = "mediatek,mt7986-wo-dlm", "syscon"; - reg = <0 0x151e8000 0 0x2000>; - }; - - wo_ilm0: syscon@151e0000 { - compatible = "mediatek,mt7986-wo-ilm", "syscon"; - reg = <0 0x151e0000 0 0x8000>; - }; - - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; - reg = <0 0x10060000 0 0x1000>; - mediatek,pnswap; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7981-topmisc", "syscon"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - }; - - snand: snfi@11005000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; - reg-names = "nfi", "ecc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, - <&infracfg CLK_INFRA_NFI1_CK>, - <&infracfg CLK_INFRA_NFI_HCK_CK>; - clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, - <&topckgen CLK_TOP_CB_M_D8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - status = "disabled"; - }; - - wed_pcie: wed_pcie@10003000 { - compatible = "mediatek,wed_pcie"; - reg = <0 0x10003000 0 0x10>; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - consys: consys@10000000 { - compatible = "mediatek,mt7981-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - xhci: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - vusb33-supply = <®_3p3v>; - status = "disabled"; - }; - - usb_phy: usb-phy@11e10000 { - compatible = "mediatek,mt7981", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - status = "okay"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - efuse: efuse@11f20000 { - compatible = "mediatek,mt7981-efuse", - "mediatek,efuse"; - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; - - phy_calibration: phy-calib@8dc { - reg = <0x8dc 0x10>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8c8 { - reg = <0x8c8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8c8 { - reg = <0x8c8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8c9 { - reg = <0x8c9 1>; - bits = <2 6>; - }; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, - <&infracfg CLK_INFRA_AUD_26M_CK>, - <&infracfg CLK_INFRA_AUD_L_CK>, - <&infracfg CLK_INFRA_AUD_AUD_CK>, - <&infracfg CLK_INFRA_AUD_EG2_CK>, - <&topckgen CLK_TOP_AUD_SEL>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>, - <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - ice: ice_debug { - compatible = "mediatek,mt7981-ice_debug", - "mediatek,mt2701-ice_debug"; - clocks = <&infracfg CLK_INFRA_DBG_CK>; - clock-names = "ice_dbg"; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - pinctrl-0 = <&wifi_dbdc_pins>; - pinctrl-names = "dbdc"; - clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - status = "disabled"; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts deleted file mode 100644 index 83a37150c..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snand"; -}; - -&spi0 { - status = "okay"; - - spi_nand: spi_nand@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts deleted file mode 100644 index 868365a99..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snor"; -}; - -&spi0 { - status = "okay"; - - spi_nor: spi_nor@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - factory: partition@50000 { - label = "Factory"; - reg = <0x50000 0x00B0000>; - }; - partition@100000 { - label = "FIP"; - reg = <0x100000 0x0080000>; - }; - partition@180000 { - label = "firmware"; - reg = <0x180000 0xE00000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi deleted file mode 100644 index 1ab56e37f..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7986a.dtsi" - -/ { - model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -&mdio { - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - - reset-gpios = <&pio 6 1>; - reset-deassert-us = <20000>; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - - switch: switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 0>; - }; -}; - -&crypto { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - spic_pins_g2: spic-pins-29-to-32 { - mux { - function = "spi"; - groups = "spi1_2"; - }; - }; - - spi_flash_pins: spi-flash-pins-33-to-38 { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = <8>; - mediatek,pull-down-adv = <0>; /* bias-disable */ - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins_g2>; - status = "okay"; - - proslic_spi: proslic_spi@0 { - compatible = "silabs,proslic_spi"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-cpha = <1>; - spi-cpol = <1>; - channel_count = <1>; - debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ - reset_gpio = <&pio 7 0>; - ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ - }; -}; - -&gmac1 { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy-handle = <&phy6>; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "lan6"; - - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso deleted file mode 100644 index 3f8ac2ae3..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_emmc_51>; - pinctrl-1 = <&mmc0_pins_emmc_51>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x12814>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_3p3v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso deleted file mode 100644 index d21a61ad1..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso deleted file mode 100644 index 86ab7566d..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&gmac1>; - __overlay__ { - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; - status = "okay"; - }; - }; - - fragment@1 { - target = <&int_2p5g_phy>; - __overlay__ { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso deleted file mode 100644 index 34a23bbd7..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy13>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso deleted file mode 100644 index ba40a119c..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_0_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp1: sfp@1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac1>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp1>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso deleted file mode 100644 index 140391fc4..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy8>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso deleted file mode 100644 index 19e0b2799..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy5>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso deleted file mode 100644 index b9aabd272..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c1>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_sfp_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp0: sfp@0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac2>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso deleted file mode 100644 index 04472cc12..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@1 { - target-path = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_sdcard>; - pinctrl-1 = <&mmc0_pins_sdcard>; - cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-mmc; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso deleted file mode 100644 index 618016517..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&snand>; - __overlay__ { - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; - - fragment@1 { - target = <&bch>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso deleted file mode 100644 index e63436fa5..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi0>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso deleted file mode 100644 index 33bd57b3f..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_flash_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cal-enable; - spi-cal-mode = "read-data"; - spi-cal-datalen = <7>; - spi-cal-data = /bits/ 8 < - 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ - spi-cal-addrlen = <1>; - spi-cal-addr = /bits/ 32 <0x0>; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - partition@50000 { - label = "Factory"; - reg = <0x50000 0x0200000>; - }; - partition@250000 { - label = "FIP"; - reg = <0x250000 0x0080000>; - }; - partition@2D0000 { - label = "firmware"; - reg = <0x2D0000 0x1D30000>; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts deleted file mode 100644 index 11dbf9830..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include - -/ { - model = "MediaTek MT7988A Reference Board"; - compatible = "mediatek,mt7988a-rfb", - "mediatek,mt7988"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; -}; - -&gmac0 { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -ð { - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "disabled"; -}; - -&pcie3 { - status = "okay"; -}; - -&ssusb0 { - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&xphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi deleted file mode 100644 index 7fed1e138..000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ /dev/null @@ -1,1441 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7988"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x0>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x1>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x2>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x3>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - }; - }; - - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - - cci_opp: opp_table_cci { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <660000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <900000>; - }; - }; - - pmu { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupt = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - - interrupts = ; - }; - - phyfw: phy-firmware@f000000 { - compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f000000 0 0x8000>, - <0 0x0f100000 0 0x20000>, - <0 0x0f0f0000 0 0x200>; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7988-wdt", - "mediatek,mt6589-wdt", - "syscon"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl", "syscon"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", - "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 84>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c1_pins: i2c1-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c1_sfp_pins: i2c1-sfp-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_sfp"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2"; - }; - }; - - i2c2_0_pins: i2c2-pins-g0 { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2c2_1_pins: i2c2-pins-g1 { - mux { - function = "i2c"; - groups = "i2c2_1"; - }; - }; - - gbe0_led0_pins: gbe0-led0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-led0-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-led0-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-led0-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - gbe0_led1_pins: gbe0-led1-pins { - mux { - function = "led"; - groups = "gbe0_led1"; - }; - }; - - gbe1_led1_pins: gbe1-led1-pins { - mux { - function = "led"; - groups = "gbe1_led1"; - }; - }; - - gbe2_led1_pins: gbe2-led1-pins { - mux { - function = "led"; - groups = "gbe2_led1"; - }; - }; - - gbe3_led1_pins: gbe3-led1-pins { - mux { - function = "led"; - groups = "gbe3_led1"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - - i2p5gbe_led1_pins: 2p5gbe-led1-pins { - mux { - function = "led"; - groups = "2p5gbe_led1"; - }; - }; - - mmc0_pins_emmc_45: mmc0-pins-emmc-45 { - mux { - function = "flash"; - groups = "emmc_45"; - }; - }; - - mmc0_pins_emmc_51: mmc0-pins-emmc-51 { - mux { - function = "flash"; - groups = "emmc_51"; - }; - }; - - mmc0_pins_sdcard: mmc0-pins-sdcard { - mux { - function = "flash"; - groups = "sdcard"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - snfi_pins: snfi-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spi0_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0"; - }; - }; - - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spi1_pins: spi1-pins { - mux { - function = "spi"; - groups = "spi1"; - }; - }; - - spi2_pins: spi2-pins { - mux { - function = "spi"; - groups = "spi2"; - }; - }; - - spi2_flash_pins: spi2-flash-pins { - mux { - function = "spi"; - groups = "spi2", "spi2_wp_hold"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_0", - "syscon"; - reg = <0 0x10060000 0 0x1000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_1", - "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - usxgmiisys0: usxgmiisys@10080000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_0", - "syscon"; - reg = <0 0x10080000 0 0x1000>; - #clock-cells = <1>; - }; - - usxgmiisys1: usxgmiisys@10081000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_1", - "syscon"; - reg = <0 0x10081000 0 0x1000>; - #clock-cells = <1>; - }; - - xfi_pextp0: xfi-pextp@11f20000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_0", - "syscon"; - reg = <0 0x11f20000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pextp1: xfi-pextp@11f30000 { - compatible = "mediatek,mt7988-xfi-pextp", - "mediatek,mt7988-xfi-pextp_1", - "syscon"; - reg = <0 0x11f30000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pll: xfi-pll@11f40000 { - compatible = "mediatek,mt7988-xfi-pll", "syscon"; - reg = <0 0x11f40000 0 0x1000>; - #clock-cells = <1>; - }; - - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@11000000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - - snand: spi@11001000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11001000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI>, - <&infracfg CLK_INFRA_NFI>; - clock-names = "pad_clk", "nfi_clk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, - <&topckgen CLK_TOP_MPLL_D8>; - nand-ecc-engine = <&bch>; - mediatek,quad-spi; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&snfi_pins>; - status = "disabled"; - }; - - bch: ecc@11002000 { - compatible = "mediatek,mt7686-ecc"; - reg = <0 0x11002000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI1X_SEL>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - i2c0: i2c@11003000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11004000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11005000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@11007000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11007000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI0>, - <&infracfg CLK_INFRA_66M_SPI0_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11008000 { - compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm"; - reg = <0 0x11008000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI1>, - <&infracfg CLK_INFRA_66M_SPI1_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI2_BCK>, - <&infracfg CLK_INFRA_66M_SPI2_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ - cooling-levels = <0 128 255>; - #cooling-cells = <2>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts"; - #thermal-sensor-cells = <1>; - reg = <0 0x1100a000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; - clock-names = "lvts_clk"; - nvmem-cells = <&lvts_calibration>; - nvmem-cell-names = "e_data1"; - }; - - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, - <&infracfg CLK_INFRA_AUD_26M>, - <&infracfg CLK_INFRA_AUD_L>, - <&infracfg CLK_INFRA_AUD_AUD>, - <&infracfg CLK_INFRA_AUD_EG2>, - <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_AUD_I2S_M>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel", - "aud_i2s_m"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>, - <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - pcie2: pcie@11280000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11280000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <3>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x00200000>, - <0x82000000 0x00 0x20200000 0x00 - 0x20200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "disabled"; - - phys = <&xphyu3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, - <0 0 0 2 &pcie_intc2 1>, - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - pcie_intc2: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie3: pcie@11290000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11290000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x28000000 0x00 - 0x28000000 0x00 0x00200000>, - <0x82000000 0x00 0x28200000 0x00 - 0x28200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc3 0>, - <0 0 0 2 &pcie_intc3 1>, - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - pcie_intc3: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie0: pcie@11300000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11300000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <0>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x30000000 0x00 - 0x30000000 0x00 0x00200000>, - <0x82000000 0x00 0x30200000 0x00 - 0x30200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie1: pcie@11310000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11310000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <1>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x38000000 0x00 - 0x38000000 0x00 0x00200000>, - <0x82000000 0x00 0x38200000 0x00 - 0x38200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11D60000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC400>, - <&infracfg CLK_INFRA_MSDC2_HCK>, - <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, - <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, - <&apmixedsys CLK_APMIXED_MSDCPLL>; - clock-names = "source", - "hclk", - "axi_cg", - "ahb_cg"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tphy: tphy@11c50000 { - compatible = "mediatek,mt7988", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; - clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - }; - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; - clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,usb3-pll-ssc-delta; - mediatek,usb3-pll-ssc-delta1; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7988-topmisc", "syscon", - "mediatek,mt7988-power-controller"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - xphy: xphy@11e10000 { - compatible = "mediatek,mt7988", - "mediatek,xsphy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; - clocks = <&infracfg CLK_INFRA_USB_UTMI>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; - clocks = <&infracfg CLK_INFRA_USB_PIPE>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - }; - }; - - efuse: efuse@11f50000 { - compatible = "mediatek,efuse"; - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; - phy_calibration_p0: calib@940 { - reg = <0x940 0x10>; - }; - phy_calibration_p1: calib@954 { - reg = <0x954 0x10>; - }; - phy_calibration_p2: calib@968 { - reg = <0x968 0x10>; - }; - phy_calibration_p3: calib@97c { - reg = <0x97c 0x10>; - }; - cpufreq_calibration: calib@278 { - reg = <0x278 0x1>; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - switch: switch@15020000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7988-switch"; - reg = <0 0x15020000 0 0x8000>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - resets = <ðrst 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy0_led0: gsw-phy0-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy0_led1: gsw-phy0-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy1_led0: gsw-phy1-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy1_led1: gsw-phy1-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy2_led0: gsw-phy2-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy2_led1: gsw-phy2-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy3_led0: gsw-phy3-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy3_led1: gsw-phy3-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - ethwarp: syscon@15031000 { - compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - - ethrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) - >; - }; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7988-eth"; - reg = <0 0x15100000 0 0x80000>, - <0 0x15400000 0 0x380000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETHDMA_XGP1_EN>, - <ðsys CLK_ETHDMA_XGP2_EN>, - <ðsys CLK_ETHDMA_XGP3_EN>, - <ðsys CLK_ETHDMA_FE_EN>, - <ðsys CLK_ETHDMA_GP2_EN>, - <ðsys CLK_ETHDMA_GP1_EN>, - <ðsys CLK_ETHDMA_GP3_EN>, - <ðsys CLK_ETHDMA_ESW_EN>, - <ðsys CLK_ETHDMA_CRYPT0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <ðwarp CLK_ETHWARP_WOCPU2_EN>, - <ðwarp CLK_ETHWARP_WOCPU1_EN>, - <ðwarp CLK_ETHWARP_WOCPU0_EN>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>, - <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>, - <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>, - <&topckgen CLK_TOP_ETH_GMII_SEL>, - <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_SEL>, - <&topckgen CLK_TOP_ETH_XGMII_SEL>, - <&topckgen CLK_TOP_ETH_MII_SEL>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>, - <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_WARP_SEL>; - clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", - "gp3", "esw", "crypto", "sgmii_tx250m", - "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", - "ethwarp_wocpu2", "ethwarp_wocpu1", - "ethwarp_wocpu0", "top_usxgmii0_sel", - "top_usxgmii1_sel", "top_sgm0_sel", - "top_sgm1_sel", "top_xfi_phy0_xtal_sel", - "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", - "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", - "top_eth_sys_sel", "top_eth_xgmii_sel", - "top_eth_mii_sel", "top_netsys_sel", - "top_netsys_500m_sel", "top_netsys_pao_2x_sel", - "top_netsys_sync_250m_sel", - "top_netsys_ppefb_250m_sel", - "top_netsys_warp_sel"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_GSW_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&topckgen CLK_TOP_NET1PLL_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&apmixedsys CLK_APMIXED_SGMPLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; - mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>; - mediatek,xfi-pll = <&xfi_pll>; - mediatek,infracfg = <&topmisc>; - mediatek,toprgu = <&watchdog>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - status = "disabled"; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - status = "disabled"; - }; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* internal 2.5G PHY */ - int_2p5g_phy: ethernet-phy@15 { - reg = <15>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c deleted file mode 100644 index 3f1edc231..000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include "clk-pll.h" -#include - -#define MT7988_PLL_FMAX (2500UL * MHZ) -#define MT7988_PCW_CHG_SHIFT 2 - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \ - _div_table) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \ - .div_table = _div_table, .parent_name = "clkxtal", \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL) - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, - 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, - 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, - 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, - 0x0154), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, - 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, - 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174), - PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, - 0x0204), - PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), - PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, - 32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314), -}; - -static const struct of_device_id of_match_clk_mt7988_apmixed[] = { - { .compatible = "mediatek,mt7988-apmixedsys", }, - { /* sentinel */ } -}; - -static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7988_apmixed_drv = { - .probe = clk_mt7988_apmixed_probe, - .driver = { - .name = "clk-mt7988-apmixed", - .of_match_table = of_match_clk_mt7988_apmixed, - }, -}; -builtin_platform_driver(clk_mt7988_apmixed_drv); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c deleted file mode 100644 index 14b877f8c..000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include - -static const struct mtk_gate_regs ethdma_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETHDMA(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðdma_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethdma_clks[] = { - GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), - GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), - GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), - GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), - GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), - GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), - GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), - GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), - GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", - 29), -}; - -static const struct mtk_clk_desc ethdma_desc = { - .clks = ethdma_clks, - .num_clks = ARRAY_SIZE(ethdma_clks), -}; - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] = { - GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), - GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), -}; - -static const struct mtk_clk_desc sgmii0_desc = { - .clks = sgmii0_clks, - .num_clks = ARRAY_SIZE(sgmii0_clks), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] = { - GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), - GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), -}; - -static const struct mtk_clk_desc sgmii1_desc = { - .clks = sgmii1_clks, - .num_clks = ARRAY_SIZE(sgmii1_clks), -}; - -static const struct mtk_gate_regs ethwarp_cg_regs = { - .set_ofs = 0x14, - .clr_ofs = 0x14, - .sta_ofs = 0x14, -}; - -#define GATE_ETHWARP(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðwarp_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethwarp_clks[] = { - GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", - "netsys_mcu_sel", 13), - GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", - "netsys_mcu_sel", 14), - GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", - "netsys_mcu_sel", 15), -}; - -static const struct mtk_clk_desc ethwarp_desc = { - .clks = ethwarp_clks, - .num_clks = ARRAY_SIZE(ethwarp_clks), -}; - -static const struct of_device_id of_match_clk_mt7986_eth[] = { - { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, - { .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc }, - { .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc }, - { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); - -static struct platform_driver clk_mt7988_eth_drv = { - .driver = { - .name = "clk-mt7988-eth", - .of_match_table = of_match_clk_mt7986_eth, - }, - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, -}; -module_platform_driver(clk_mt7988_eth_drv); - -MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c deleted file mode 100644 index a5d21d756..000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const char *const infra_mux_uart0_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart1_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart2_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_mux_spi1_parents[] __initconst = { - "i2c_sel", "spim_mst_sel" -}; - -static const char *const infra_pwm_bck_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p1_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p2_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p3_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", - infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, - 0, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", - infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, - 1, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", - infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, - 2, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", - infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, - "infra_pcie_gfmux_tl_o_p0_sel", - infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, - 0x0020, 0x0024, 0, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, - "infra_pcie_gfmux_tl_o_p1_sel", - infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, - 0x0020, 0x0024, 2, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, - "infra_pcie_gfmux_tl_o_p2_sel", - infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, - 0x0020, 0x0024, 4, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, - "infra_pcie_gfmux_tl_o_p3_sel", - infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, - 0x0020, 0x0024, 6, 2, -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x10, - .clr_ofs = 0x14, - .sta_ofs = 0x18, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra3_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra3_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA3(_id, _name, _parent, _shift) \ - GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = _regs, .shift = _shift, \ - .flags = CLK_IS_CRITICAL, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, - "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, - "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, - "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, - "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", - "sysaxi_sel", 0), - GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", - "sysaxi_sel", 1), - GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", - "infra_pwm_sel", 2), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", - "infra_pwm_ck1_sel", 3), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", - "infra_pwm_ck2_sel", 4), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", - "infra_pwm_ck3_sel", 5), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", - "infra_pwm_ck4_sel", 6), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", - "infra_pwm_ck5_sel", 7), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", - "infra_pwm_ck6_sel", 8), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", - "infra_pwm_ck7_sel", 9), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", - "infra_pwm_ck8_sel", 10), - GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", - "sysaxi_sel", 12), - GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", - "sysaxi_sel", 13), - GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", - "csw_infra_f26m_sel", 14), - GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), - GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), - GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), - GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", - "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL), - // JTAG - GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", - "sysaxi_sel", 20, CLK_IS_CRITICAL), - GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", - "sysaxi_sel", 21), - GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", - "sysaxi_sel", 29), - GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", - "csw_infra_f26m_sel", 30), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", - "csw_infra_f26m_sel", 0), - GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), - GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", - "infra_mux_uart0_sel", 3), - GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", - "infra_mux_uart1_sel", 4), - GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", - "infra_mux_uart2_sel", 5), - GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), - GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", - "sysaxi_sel", 11, CLK_IS_CRITICAL), - GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", - "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", - "infra_mux_spi1_sel", 13), - GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", - "infra_mux_spi2_sel", 14), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", - "sysaxi_sel", 15, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", - "sysaxi_sel", 16), - GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", - "sysaxi_sel", 17), - GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", - "sysaxi_sel", 18), - GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19), - GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", - "csw_infra_f26m_sel", 20), - GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", - 21), - GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", - 22), - GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", - 23), - GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", - "sysaxi_sel", 24), - GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", - "sysaxi_sel", 25), - GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", - "sysaxi_sel", 26), - GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), - GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, - "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), - GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, - "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), - /* INFRA3 */ - GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", - 0), - GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", - "sysaxi_sel", 1), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", - 2), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", - "sysaxi_sel", 3), - GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), - GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", - "usb_sys_p1_sel", 5), - GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), - GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", - "usb_frmcnt_sel", 8, CLK_IS_CRITICAL), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", - "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL), - GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), - GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - "usb_phy_sel", 11), - GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), - GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - "top_xtal", 13), - GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), - GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", - "usb_xhci_p1_sel", 15), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", - "infra_pcie_gfmux_tl_o_p0_sel", 20), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", - "infra_pcie_gfmux_tl_o_p1_sel", 21), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", - "infra_pcie_gfmux_tl_o_p2_sel", 22), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", - "infra_pcie_gfmux_tl_o_p3_sel", 23), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - "top_xtal", 24), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - "top_xtal", 25), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - "top_xtal", 26), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - "top_xtal", 27), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", - "sysaxi_sel", 28), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", - "sysaxi_sel", 29), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", - "sysaxi_sel", 30), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", - "sysaxi_sel", 31), -}; - -static const struct mtk_clk_desc infra_desc = { - .clks = infra_clks, - .num_clks = ARRAY_SIZE(infra_clks), - .mux_clks = infra_muxes, - .num_mux_clks = ARRAY_SIZE(infra_muxes), - .clk_lock = &mt7988_clk_lock, -}; - -static const struct of_device_id of_match_clk_mt7988_infracfg[] = { - { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); - -static struct platform_driver clk_mt7988_infracfg_drv = { - .driver = { - .name = "clk-mt7988-infracfg", - .of_match_table = of_match_clk_mt7988_infracfg, - }, - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, -}; -module_platform_driver(clk_mt7988_infracfg_drv); diff --git a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c deleted file mode 100644 index b0745d650..000000000 --- a/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), -}; - -static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), - FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), - FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), - FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), - FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), - FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), - FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), - FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), - FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), - FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), - FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), - FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), - FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), - FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), -}; - -static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", - "mmpll_d2" }; - -static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", - "net1pll_d5_d2" }; - -static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", - "mmpll" }; - -static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", - "net1pll_d5" }; - -static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; - -static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", - "mmpll", "net1pll_d4", - "net1pll_d5", "mpll" }; - -static const char *const eip197_parents[] = { "top_xtal", "netsyspll", - "net2pll", "mmpll", - "net1pll_d4", "net1pll_d5" }; - -static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; - -static const char *const uart_parents[] = { "top_xtal", "mpll_d8", - "mpll_d8_d2" }; - -static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", - "mmpll_d4" }; - -static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", - "mmpll_d2", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2" }; - -static const char *const spi_parents[] = { "top_xtal", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2", - "net2pll_d6", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", - "net1pll_d8_d2", "net2pll_d6", - "mpll_d4", "mmpll_d8", - "net1pll_d8_d4", "mpll_d8" }; - -static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", - "net1pll_d5_d4", "mpll_d4", - "mmpll_d8", "net1pll_d8_d4", - "mmpll_d6_d2", "mpll_d8" }; - -static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", - "net1pll_d5_d4", "mpll_d4", - "mpll_d8_d2", "top_rtc_32k" }; - -static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const pcie_mbist_250m_parents[] = { "top_xtal", - "net1pll_d5_d2" }; - -static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", - "mmpll_d8", "mpll_d8_d2", - "top_rtc_32k" }; - -static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; - -static const char *const aud_parents[] = { "top_xtal", "apll2" }; - -static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; - -static const char *const aud_l_parents[] = { "top_xtal", "apll2", - "mpll_d8_d2" }; - -static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; - -static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", - "net1pll_d8_d4" }; - -static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; - -static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; - -static const char *const eth_refck_50m_parents[] = { "top_xtal", - "net2pll_d4_d4" }; - -static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; - -static const char *const eth_xgmii_parents[] = { "top_xtal_d2", - "net1pll_d8_d8", - "net1pll_d8_d16" }; - -static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", - "net2pll_d2" }; - -static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; - -static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", - "wedmcupll" }; - -static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", - "net2pll_d8" }; - -static const char *const mcusys_backup_625m_parents[] = { "top_xtal", - "net1pll_d4" }; - -static const char *const macsec_parents[] = { "top_xtal", "sgmpll", - "net1pll_d8" }; - -static const char *const netsys_tops_400m_parents[] = { "top_xtal", - "net2pll_d2" }; - -static const char *const eth_mii_parents[] = { "top_xtal_d2", - "net2pll_d4_d8" }; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, - 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23, - 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", - netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, - 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", - eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7, - 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15, - 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, - 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, - 0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", - axi_infra_parents, 0x020, 0x024, 0x028, 0, - 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, - 0x024, 0x028, 8, 2, 15, 0x1c0, 9), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", - emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23, - 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", - emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31, - 0x1C0, 11), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, - 0x034, 0x038, 0, 3, 7, 0x1c0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, - 0x044, 0x048, 0, 3, 7, 0x1c0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, - 0x044, 0x048, 8, 2, 15, 0x1c0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, - "pcie_mbist_250m_sel", pcie_mbist_250m_parents, - 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", - pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3, - 31, 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, - 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3, - 23, 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", - eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31, - 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7, - 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15, - 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23, - 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", - usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, - 31, 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", - usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, - 0x074, 0x078, 8, 1, 15, 0x1c0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, - 0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, - 0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", - sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23, - 0x1c4, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", - usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, - 1, 31, 0x1C4, 4), - /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, - 7, 0x1C4, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, - 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8), - /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", - usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8, - 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, - 0x1C4, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, - 0x1C4, 11), - /* CLK_CFG_11 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", - axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24, - 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", - sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1, - 7, 0x1c4, 13, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", - eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1, - 15, 0x1C4, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", - eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1, - 23, 0x1C4, 15), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", - pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24, - 1, 31, 0x1C4, 16), - /* CLK_CFG_12 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", - eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, - 0x1C4, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", - bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15, - 0x1C4, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", - npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23, - 0x1C4, 19), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", - sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1, - 31, 0x1C4, 20, CLK_IS_CRITICAL), - /* CLK_CFG_13 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0, - 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS( - CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, - 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23, - 0x1C4, 23), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, - 0x1C4, 24), - /* CLK_CFG_14 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, - 0x1C4, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, - 0x1C4, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, - 23, 0x1C4, 27), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, - 31, 0x1C4, 28), - /* CLK_CFG_15 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1, - 7, 0x1C4, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1, - 15, 0x1C4, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, - 0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, - 0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1), - /* CLK_CFG_16 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, - 0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", - sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15, - 0x1C8, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, - "mcusys_backup_625m_sel", - mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, - 16, 1, 23, 0x1C8, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, - "netsys_sync_250m_sel", pcie_mbist_250m_parents, - 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), - /* CLK_CFG_17 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, - 0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, - "netsys_tops_400m_sel", netsys_tops_400m_parents, - 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, - "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, - 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", - netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31, - 0x1C8, 9), - /* CLK_CFG_18 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", - eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7, - 0x1c8, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, - 0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), -}; - -static const struct mtk_composite top_aud_divs[] = { - DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, - 8, 8), -}; - -static const struct mtk_clk_desc topck_desc = { - .fixed_clks = top_fixed_clks, - .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), - .factor_clks = top_divs, - .num_factor_clks = ARRAY_SIZE(top_divs), - .mux_clks = top_muxes, - .num_mux_clks = ARRAY_SIZE(top_muxes), - .composite_clks = top_aud_divs, - .num_composite_clks = ARRAY_SIZE(top_aud_divs), - .clk_lock = &mt7988_clk_lock, -}; - -static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", - "net1pll_d4" }; - -static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", - "net1pll_d4" }; - -static struct mtk_composite mcu_muxes[] = { - /* bus_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", - mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL), - /* mp2_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", - mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), -}; - -static const struct mtk_clk_desc mcusys_desc = { - .composite_clks = mcu_muxes, - .num_composite_clks = ARRAY_SIZE(mcu_muxes), -}; - -static const struct of_device_id of_match_clk_mt7988_topckgen[] = { - { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, - { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); - -static struct platform_driver clk_mt7988_topckgen_drv = { - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7988-topckgen", - .of_match_table = of_match_clk_mt7988_topckgen, - }, -}; -module_platform_driver(clk_mt7988_topckgen_drv); -MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c deleted file mode 100644 index c12e6b8eb..000000000 --- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include -#include - -#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin" -#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin" - -#define MD32_EN_CFG 0x18 -#define MD32_EN BIT(0) - -#define BASE100T_STATUS_EXTEND 0x10 -#define BASE1000T_STATUS_EXTEND 0x11 -#define EXTEND_CTRL_AND_STATUS 0x16 - -#define PHY_AUX_CTRL_STATUS 0x1d -#define PHY_AUX_DPX_MASK GENMASK(5, 5) -#define PHY_AUX_SPEED_MASK GENMASK(4, 2) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_LINK_STATUS_MISC 0xa2 -#define MTK_PHY_FDX_ENABLE BIT(5) - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINK2500 BIT(7) -#define MTK_PHY_LED0_POLARITY BIT(14) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_FDX BIT(4) -#define MTK_PHY_LED1_ON_HDX BIT(5) -#define MTK_PHY_LED1_POLARITY BIT(14) - -enum { - PHY_AUX_SPD_10 = 0, - PHY_AUX_SPD_100, - PHY_AUX_SPD_1000, - PHY_AUX_SPD_2500, -}; - -static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) -{ - int ret; - int i; - const struct firmware *fw; - struct device *dev = &phydev->mdio.dev; - struct device_node *np; - void __iomem *dmb_addr; - void __iomem *pmb_addr; - void __iomem *mcucsr_base; - u16 reg; - struct pinctrl *pinctrl; - - np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); - if (!np) - return -ENOENT; - - dmb_addr = of_iomap(np, 0); - if (!dmb_addr) - return -ENOMEM; - pmb_addr = of_iomap(np, 1); - if (!pmb_addr) - return -ENOMEM; - mcucsr_base = of_iomap(np, 2); - if (!mcucsr_base) - return -ENOMEM; - - ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDAITEK_2P5GE_PHY_DMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); - release_firmware(fw); - - ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDIATEK_2P5GE_PHY_PMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); - release_firmware(fw); - - reg = readw(mcucsr_base + MD32_EN_CFG); - writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); - dev_dbg(dev, "Firmware loading/trigger ok.\n"); - - /* Setup LED */ - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000 | - MTK_PHY_LED0_ON_LINK2500); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); - return PTR_ERR(pinctrl); - } - - return 0; -} - -static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) -{ - bool changed = false; - u32 adv; - int ret; - - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. - */ - return phydev->duplex != DUPLEX_FULL - ? genphy_setup_forced(phydev) - : genphy_c45_pma_setup_forced(phydev); - } - - ret = genphy_c45_an_config_aneg(phydev); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); - ret = phy_modify_changed(phydev, MII_CTRL1000, - ADVERTISE_1000FULL | ADVERTISE_1000HALF, - adv); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - return genphy_c45_check_and_restart_aneg(phydev, changed); -} - -static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) -{ - int ret; - - ret = genphy_read_abilities(phydev); - if (ret) - return ret; - - /* We don't support HDX at MAC layer on mt798x. - * So mask phy's HDX capabilities, too. - */ - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); - - return 0; -} - -static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) -{ - int ret; - - ret = genphy_update_link(phydev); - if (ret) - return ret; - - phydev->speed = SPEED_UNKNOWN; - phydev->duplex = DUPLEX_UNKNOWN; - phydev->pause = 0; - phydev->asym_pause = 0; - - if (!phydev->link) - return 0; - - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { - ret = genphy_c45_read_lpa(phydev); - if (ret < 0) - return ret; - - /* Read the link partner's 1G advertisement */ - ret = phy_read(phydev, MII_STAT1000); - if (ret < 0) - return ret; - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); - } else if (phydev->autoneg == AUTONEG_DISABLE) { - linkmode_zero(phydev->lp_advertising); - } - - ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); - if (ret < 0) - return ret; - - switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { - case PHY_AUX_SPD_10: - phydev->speed = SPEED_10; - break; - case PHY_AUX_SPD_100: - phydev->speed = SPEED_100; - break; - case PHY_AUX_SPD_1000: - phydev->speed = SPEED_1000; - break; - case PHY_AUX_SPD_2500: - phydev->speed = SPEED_2500; - phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */ - break; - } - - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); - if (ret < 0) - return ret; - - phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; - - return 0; -} - -static struct phy_driver mtk_gephy_driver[] = { - { - PHY_ID_MATCH_EXACT(0x00339c11), - .name = "MediaTek MT798x 2.5GbE PHY", - .config_init = mt798x_2p5ge_phy_config_init, - .config_aneg = mt798x_2p5ge_phy_config_aneg, - .get_features = mt798x_2p5ge_phy_get_features, - .read_status = mt798x_2p5ge_phy_read_status, - }, -}; - -module_phy_driver(mtk_gephy_driver); - -static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { - { PHY_ID_MATCH_VENDOR(0x00339c00) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW); -MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c deleted file mode 100644 index 49c0be1bb..000000000 --- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ /dev/null @@ -1,1466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7988 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -enum MT7988_PINCTRL_REG_PAGE { - GPIO_BASE, - IOCFG_TR_BASE, - IOCFG_BR_BASE, - IOCFG_RB_BASE, - IOCFG_LB_BASE, - IOCFG_TL_BASE, -}; - -#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { - PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { - PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { - PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { - PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), - - PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), - PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), - - PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), - PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), - PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), - PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), - PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), - PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), - PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), - PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - - PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), -}; - -static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7988_pins[] = { - MT7988_PIN(0, "UART2_RXD"), - MT7988_PIN(1, "UART2_TXD"), - MT7988_PIN(2, "UART2_CTS"), - MT7988_PIN(3, "UART2_RTS"), - MT7988_PIN(4, "GPIO_A"), - MT7988_PIN(5, "SMI_0_MDC"), - MT7988_PIN(6, "SMI_0_MDIO"), - MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), - MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), - MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), - MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), - MT7988_PIN(11, "GPIO_P"), - MT7988_PIN(12, "WATCHDOG"), - MT7988_PIN(13, "GPIO_RESET"), - MT7988_PIN(14, "GPIO_WPS"), - MT7988_PIN(15, "PMIC_I2C_SCL"), - MT7988_PIN(16, "PMIC_I2C_SDA"), - MT7988_PIN(17, "I2C_1_SCL"), - MT7988_PIN(18, "I2C_1_SDA"), - MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), - MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), - MT7988_PIN(21, "PWMD1"), - MT7988_PIN(22, "SPI0_WP"), - MT7988_PIN(23, "SPI0_HOLD"), - MT7988_PIN(24, "SPI0_CSB"), - MT7988_PIN(25, "SPI0_MISO"), - MT7988_PIN(26, "SPI0_MOSI"), - MT7988_PIN(27, "SPI0_CLK"), - MT7988_PIN(28, "SPI1_CSB"), - MT7988_PIN(29, "SPI1_MISO"), - MT7988_PIN(30, "SPI1_MOSI"), - MT7988_PIN(31, "SPI1_CLK"), - MT7988_PIN(32, "SPI2_CLK"), - MT7988_PIN(33, "SPI2_MOSI"), - MT7988_PIN(34, "SPI2_MISO"), - MT7988_PIN(35, "SPI2_CSB"), - MT7988_PIN(36, "SPI2_HOLD"), - MT7988_PIN(37, "SPI2_WP"), - MT7988_PIN(38, "EMMC_RSTB"), - MT7988_PIN(39, "EMMC_DSL"), - MT7988_PIN(40, "EMMC_CK"), - MT7988_PIN(41, "EMMC_CMD"), - MT7988_PIN(42, "EMMC_DATA_7"), - MT7988_PIN(43, "EMMC_DATA_6"), - MT7988_PIN(44, "EMMC_DATA_5"), - MT7988_PIN(45, "EMMC_DATA_4"), - MT7988_PIN(46, "EMMC_DATA_3"), - MT7988_PIN(47, "EMMC_DATA_2"), - MT7988_PIN(48, "EMMC_DATA_1"), - MT7988_PIN(49, "EMMC_DATA_0"), - MT7988_PIN(50, "PCM_FS_I2S_LRCK"), - MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), - MT7988_PIN(52, "PCM_DRX_I2S_DIN"), - MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), - MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), - MT7988_PIN(55, "UART0_RXD"), - MT7988_PIN(56, "UART0_TXD"), - MT7988_PIN(57, "PWMD0"), - MT7988_PIN(58, "JTAG_JTDI"), - MT7988_PIN(59, "JTAG_JTDO"), - MT7988_PIN(60, "JTAG_JTMS"), - MT7988_PIN(61, "JTAG_JTCLK"), - MT7988_PIN(62, "JTAG_JTRST_N"), - MT7988_PIN(63, "USB_DRV_VBUS_P1"), - MT7988_PIN(64, "LED_A"), - MT7988_PIN(65, "LED_B"), - MT7988_PIN(66, "LED_C"), - MT7988_PIN(67, "LED_D"), - MT7988_PIN(68, "LED_E"), - MT7988_PIN(69, "GPIO_B"), - MT7988_PIN(70, "GPIO_C"), - MT7988_PIN(71, "I2C_2_SCL"), - MT7988_PIN(72, "I2C_2_SDA"), - MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), - MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), - MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), - MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), - MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), - MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), - MT7988_PIN(79, "USB_DRV_VBUS_P0"), - MT7988_PIN(80, "UART1_RXD"), - MT7988_PIN(81, "UART1_TXD"), - MT7988_PIN(82, "UART1_CTS"), - MT7988_PIN(83, "UART1_RTS"), -}; - -/* jtag */ -static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; - -static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; - -static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; - -static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; - -static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; - -static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; - -/* int_usxgmii */ -static int mt7988_int_usxgmii_pins[] = { 2, 3 }; -static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; - -/* pwm */ -static int mt7988_pwm0_pins[] = { 57 }; -static int mt7988_pwm0_funcs[] = { 1 }; - -static int mt7988_pwm1_pins[] = { 21 }; -static int mt7988_pwm1_funcs[] = { 1 }; - -static int mt7988_pwm2_pins[] = { 80 }; -static int mt7988_pwm2_funcs[] = { 2 }; - -static int mt7988_pwm3_pins[] = { 81 }; -static int mt7988_pwm3_funcs[] = { 2 }; - -static int mt7988_pwm4_pins[] = { 82 }; -static int mt7988_pwm4_funcs[] = { 2 }; - -static int mt7988_pwm5_pins[] = { 83 }; -static int mt7988_pwm5_funcs[] = { 2 }; - -static int mt7988_pwm6_pins[] = { 69 }; -static int mt7988_pwm6_funcs[] = { 3 }; - -static int mt7988_pwm7_pins[] = { 70 }; -static int mt7988_pwm7_funcs[] = { 3 }; - -/* dfd */ -static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2c */ -static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_0_pins[] = { 5, 6 }; -static int mt7988_i2c0_0_funcs[] = { 2, 2 }; - -static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; - -static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_1_pins[] = { 15, 16 }; -static int mt7988_i2c0_1_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; - -static int mt7988_i2c1_0_pins[] = { 17, 18 }; -static int mt7988_i2c1_0_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; - -static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c1_2_pins[] = { 69, 70 }; -static int mt7988_i2c1_2_funcs[] = { 2, 2 }; - -static int mt7988_i2c2_0_pins[] = { 69, 70 }; -static int mt7988_i2c2_0_funcs[] = { 4, 4 }; - -static int mt7988_i2c2_1_pins[] = { 71, 72 }; -static int mt7988_i2c2_1_funcs[] = { 1, 1 }; - -/* eth */ -static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; - -static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; - -/* pcie */ -static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; - -static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; - -/* pmic */ -static int mt7988_pmic_pins[] = { 11 }; -static int mt7988_pmic_funcs[] = { 1 }; - -/* watchdog */ -static int mt7988_watchdog_pins[] = { 12 }; -static int mt7988_watchdog_funcs[] = { 1 }; - -/* spi */ -static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; - -static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; - -/* flash */ -static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -static int mt7988_emmc_45_pins[] = { - 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -}; -static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; - -static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; - -static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49 }; -static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* uart */ -static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; - -static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; - -static int mt7988_uart0_pins[] = { 55, 56 }; -static int mt7988_uart0_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; - -static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -static int mt7988_tops_uart1_2_funcs[] = { - 4, - 4, -}; - -static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; - -/* udi */ -static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2s */ -static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; - -/* pcm */ -static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; - -/* led */ -static int mt7988_gbe0_led1_pins[] = { 58 }; -static int mt7988_gbe0_led1_funcs[] = { 6 }; -static int mt7988_gbe1_led1_pins[] = { 59 }; -static int mt7988_gbe1_led1_funcs[] = { 6 }; -static int mt7988_gbe2_led1_pins[] = { 60 }; -static int mt7988_gbe2_led1_funcs[] = { 6 }; -static int mt7988_gbe3_led1_pins[] = { 61 }; -static int mt7988_gbe3_led1_funcs[] = { 6 }; - -static int mt7988_2p5gbe_led1_pins[] = { 62 }; -static int mt7988_2p5gbe_led1_funcs[] = { 6 }; - -static int mt7988_gbe0_led0_pins[] = { 64 }; -static int mt7988_gbe0_led0_funcs[] = { 1 }; -static int mt7988_gbe1_led0_pins[] = { 65 }; -static int mt7988_gbe1_led0_funcs[] = { 1 }; -static int mt7988_gbe2_led0_pins[] = { 66 }; -static int mt7988_gbe2_led0_funcs[] = { 1 }; -static int mt7988_gbe3_led0_pins[] = { 67 }; -static int mt7988_gbe3_led0_funcs[] = { 1 }; - -static int mt7988_2p5gbe_led0_pins[] = { 68 }; -static int mt7988_2p5gbe_led0_funcs[] = { 1 }; - -/* usb */ -static int mt7988_drv_vbus_p1_pins[] = { 63 }; -static int mt7988_drv_vbus_p1_funcs[] = { 1 }; - -static int mt7988_drv_vbus_pins[] = { 79 }; -static int mt7988_drv_vbus_funcs[] = { 1 }; - -static const struct group_desc mt7988_groups[] = { - /* @GPIO(0,1,2,3): uart2 */ - PINCTRL_PIN_GROUP("uart2", mt7988_uart2), - /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ - PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), - /* @GPIO(2,3): int_usxgmii */ - PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), - /* @GPIO(0,1,2,3,4): dfd */ - PINCTRL_PIN_GROUP("dfd", mt7988_dfd), - /* @GPIO(0,1): xfi_phy0_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), - /* @GPIO(0,1): xfi_phy1_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), - /* @GPIO(5,6) i2c0_0 */ - PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), - /* @GPIO(5,6) i2c1_sfp */ - PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), - /* @GPIO(5,6) xfi_pextp_phy0_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), - /* @GPIO(5,6) xfi_pextp_phy1_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), - /* @GPIO(5,6) mdc_mdio0 */ - PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), - /* @GPIO(7): pcie_wake_n0_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), - /* @GPIO(8): pcie_clk_req_n0_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), - /* @GPIO(9): pcie_wake_n3_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), - /* @GPIO(10): pcie_clk_req_n3 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), - /* @GPIO(10): pcie_clk_req_n0_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), - /* @GPIO(7,8) pcie_p0_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), - /* @GPIO(7,8) pcie_p1_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), - /* @GPIO(7,8) pcie_p2_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), - /* @GPIO(9,10) pcie_p3_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), - /* @GPIO(9,10) ckm_phy_i2c */ - PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), - /* @GPIO(11): pmic */ - PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), - /* @GPIO(12): watchdog */ - PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), - /* @GPIO(13): pcie_wake_n0_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), - /* @GPIO(14): pcie_wake_n3_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), - /* @GPIO(15,16) i2c0_1 */ - PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), - /* @GPIO(15,16) u30_phy_i2c0 */ - PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), - /* @GPIO(15,16) u32_phy_i2c0 */ - PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), - /* @GPIO(15,16) xfi_phy0_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), - /* @GPIO(15,16) xfi_phy1_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), - /* @GPIO(15,16) xfi_phy_pll_i2c2 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), - /* @GPIO(17,18) i2c1_0 */ - PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), - /* @GPIO(17,18) u30_phy_i2c1 */ - PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), - /* @GPIO(17,18) u32_phy_i2c1 */ - PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), - /* @GPIO(17,18) xfi_phy_pll_i2c3 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), - /* @GPIO(17,18) sgmii0_i2c */ - PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), - /* @GPIO(17,18) sgmii1_i2c */ - PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), - /* @GPIO(19): pcie_2l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), - /* @GPIO(20): pcie_1l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), - /* @GPIO(21): pwm1 */ - PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), - /* @GPIO(22,23) spi0_wp_hold */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), - /* @GPIO(24,25,26,27) spi0 */ - PINCTRL_PIN_GROUP("spi0", mt7988_spi0), - /* @GPIO(28,29,30,31) spi1 */ - PINCTRL_PIN_GROUP("spi1", mt7988_spi1), - /* @GPIO(32,33,34,35) spi2 */ - PINCTRL_PIN_GROUP("spi2", mt7988_spi2), - /* @GPIO(36,37) spi2_wp_hold */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), - /* @GPIO(22,23,24,25,26,27) snfi */ - PINCTRL_PIN_GROUP("snfi", mt7988_snfi), - /* @GPIO(22,23) tops_uart0_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), - /* @GPIO(28,29,30,31) uart2_0 */ - PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), - /* @GPIO(32,33,34,35) uart1_0 */ - PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), - /* @GPIO(32,33,34,35) uart2_1 */ - PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), - /* @GPIO(28) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(29) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(30) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(28,29) tops_uart1_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), - /* @GPIO(30,31) tops_uart0_1 */ - PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), - /* @GPIO(36,37) tops_uart1_1 */ - PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), - /* @GPIO(32,33,34,35,36) udi */ - PINCTRL_PIN_GROUP("udi", mt7988_udi), - /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ - PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), - /* @GPIO(32,33,34,35,36,37) sdcard */ - PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), - /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ - PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), - /* @GPIO(28,29) 2p5g_ext_mdio */ - PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), - /* @GPIO(30,31) gbe_ext_mdio */ - PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), - /* @GPIO(50,51,52,53,54) i2s */ - PINCTRL_PIN_GROUP("i2s", mt7988_i2s), - /* @GPIO(50,51,52,53) pcm */ - PINCTRL_PIN_GROUP("pcm", mt7988_pcm), - /* @GPIO(55,56) uart0 */ - PINCTRL_PIN_GROUP("uart0", mt7988_uart0), - /* @GPIO(55,56) tops_uart0_2 */ - PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), - /* @GPIO(50,51,52,53) uart2_2 */ - PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), - /* @GPIO(50,51,52,53,54) wo0_jtag */ - PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), - /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ - PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), - /* @GPIO(50,51,52,53,54) wo2_jtag */ - PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), - /* @GPIO(57) pwm0 */ - PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), - /* @GPIO(58,59,60,61,62) jtag */ - PINCTRL_PIN_GROUP("jtag", mt7988_jtag), - /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ - PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), - /* @GPIO(58,59,60,61) uart2_3 */ - PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), - /* @GPIO(58,59,60,61) uart1_1 */ - PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), - /* @GPIO(58,59,60,61) gbe_led1 */ - PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), - PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), - PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), - PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), - /* @GPIO(62) 2p5gbe_led1 */ - PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), - /* @GPIO(64,65,66,67) gbe_led0 */ - PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), - PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), - PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), - PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), - /* @GPIO(68) 2p5gbe_led0 */ - PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), - /* @GPIO(63) drv_vbus_p1 */ - PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), - /* @GPIO(63) pcie_clk_req_n2_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), - /* @GPIO(69, 70) mdc_mdio1 */ - PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), - /* @GPIO(69, 70) i2c1_2 */ - PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), - /* @GPIO(69) pwm6 */ - PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), - /* @GPIO(70) pwm7 */ - PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), - /* @GPIO(69,70) i2c2_0 */ - PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), - /* @GPIO(71,72) i2c2_1 */ - PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), - /* @GPIO(73) pcie_2l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), - /* @GPIO(74) pcie_1l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), - /* @GPIO(75) pcie_wake_n1_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), - /* @GPIO(76) pcie_clk_req_n1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), - /* @GPIO(77) pcie_wake_n2_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), - /* @GPIO(78) pcie_clk_req_n2_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), - /* @GPIO(79) drv_vbus */ - PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), - /* @GPIO(79) pcie_wake_n2_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), - /* @GPIO(80,81,82,83) uart1_2 */ - PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), - /* @GPIO(80) pwm2 */ - PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), - /* @GPIO(81) pwm3 */ - PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), - /* @GPIO(82) pwm4 */ - PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), - /* @GPIO(83) pwm5 */ - PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), - /* @GPIO(80) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(81) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(82) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(80,81) tops_uart1_2 */ - PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), - /* @GPIO(80) net_wo0_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), - /* @GPIO(81) net_wo1_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), - /* @GPIO(82) net_wo2_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char * const mt7988_jtag_groups[] = { - "tops_jtag0_0", "wo0_jtag", "wo1_jtag", - "wo2_jtag", "jtag", "tops_jtag0_1", -}; -static const char * const mt7988_int_usxgmii_groups[] = { - "int_usxgmii", -}; -static const char * const mt7988_pwm_groups[] = { - "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" -}; -static const char * const mt7988_dfd_groups[] = { - "dfd", -}; -static const char * const mt7988_i2c_groups[] = { - "xfi_phy0_i2c0", - "xfi_phy1_i2c0", - "xfi_phy_pll_i2c0", - "xfi_phy_pll_i2c1", - "i2c0_0", - "i2c1_sfp", - "xfi_pextp_phy0_i2c", - "xfi_pextp_phy1_i2c", - "i2c0_1", - "u30_phy_i2c0", - "u32_phy_i2c0", - "xfi_phy0_i2c1", - "xfi_phy1_i2c1", - "xfi_phy_pll_i2c2", - "i2c1_0", - "u30_phy_i2c1", - "u32_phy_i2c1", - "xfi_phy_pll_i2c3", - "sgmii0_i2c", - "sgmii1_i2c", - "i2c1_2", - "i2c2_0", - "i2c2_1", -}; -static const char * const mt7988_ethernet_groups[] = { - "mdc_mdio0", - "2p5g_ext_mdio", - "gbe_ext_mdio", - "mdc_mdio1", -}; -static const char * const mt7988_pcie_groups[] = { - "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", - "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", - "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", - "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", - "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", - "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", - "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", - "pcie_clk_req_n0_1" -}; -static const char * const mt7988_pmic_groups[] = { - "pmic", -}; -static const char * const mt7988_wdt_groups[] = { - "watchdog", -}; -static const char * const mt7988_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -}; -static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", - "emmc_51" }; -static const char * const mt7988_uart_groups[] = { - "uart2", - "tops_uart0_0", - "uart2_0", - "uart1_0", - "uart2_1", - "net_wo0_uart_txd_0", - "net_wo1_uart_txd_0", - "net_wo2_uart_txd_0", - "tops_uart1_0", - "ops_uart0_1", - "ops_uart1_1", - "uart0", - "tops_uart0_2", - "uart1_1", - "uart2_3", - "uart1_2", - "tops_uart1_2", - "net_wo0_uart_txd_1", - "net_wo1_uart_txd_1", - "net_wo2_uart_txd_1", -}; -static const char * const mt7988_udi_groups[] = { - "udi", -}; -static const char * const mt7988_audio_groups[] = { - "i2s", "pcm", -}; -static const char * const mt7988_led_groups[] = { - "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", - "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", - "wf5g_led0", "wf5g_led1", -}; -static const char * const mt7988_usb_groups[] = { - "drv_vbus", - "drv_vbus_p1", -}; - -static const struct function_desc mt7988_functions[] = { - { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, - { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, - { "int_usxgmii", mt7988_int_usxgmii_groups, - ARRAY_SIZE(mt7988_int_usxgmii_groups) }, - { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, - { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, - { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, - { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, - { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, - { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, - { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, - { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, - { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, - { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, - { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, - { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, - { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, -}; - -static const struct mtk_eint_hw mt7988_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7988_pins), - .db_cnt = 16, -}; - -static const char * const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -}; - -static struct mtk_pin_soc mt7988_data = { - .reg_cal = mt7988_reg_cals, - .pins = mt7988_pins, - .npins = ARRAY_SIZE(mt7988_pins), - .grps = mt7988_groups, - .ngrps = ARRAY_SIZE(mt7988_groups), - .funcs = mt7988_functions, - .nfuncs = ARRAY_SIZE(mt7988_functions), - .eint_hw = &mt7988_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7988_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7988_pinctrl_of_match[] = { - { - .compatible = "mediatek,mt7988-pinctrl", - }, - {} -}; - -static int mt7988_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -} - -static struct platform_driver mt7988_pinctrl_driver = { - .driver = { - .name = "mt7988-pinctrl", - .of_match_table = mt7988_pinctrl_of_match, - }, - .probe = mt7988_pinctrl_probe, -}; - -static int __init mt7988_pinctrl_init(void) -{ - return platform_driver_register(&mt7988_pinctrl_driver); -} -arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h deleted file mode 100644 index 77cfea4a8..000000000 --- a/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#ifndef _DT_BINDINGS_CLK_MT7988_H -#define _DT_BINDINGS_CLK_MT7988_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_NETSYSPLL 0 -#define CLK_APMIXED_MPLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_APLL2 3 -#define CLK_APMIXED_NET1PLL 4 -#define CLK_APMIXED_NET2PLL 5 -#define CLK_APMIXED_WEDMCUPLL 6 -#define CLK_APMIXED_SGMPLL 7 -#define CLK_APMIXED_ARM_B 8 -#define CLK_APMIXED_CCIPLL2_B 9 -#define CLK_APMIXED_USXGMIIPLL 10 -#define CLK_APMIXED_MSDCPLL 11 - -/* TOPCKGEN */ - -#define CLK_TOP_XTAL 0 -#define CLK_TOP_XTAL_D2 1 -#define CLK_TOP_RTC_32K 2 -#define CLK_TOP_RTC_32P7K 3 -#define CLK_TOP_MPLL_D2 4 -#define CLK_TOP_MPLL_D3_D2 5 -#define CLK_TOP_MPLL_D4 6 -#define CLK_TOP_MPLL_D8 7 -#define CLK_TOP_MPLL_D8_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D3_D5 10 -#define CLK_TOP_MMPLL_D4 11 -#define CLK_TOP_MMPLL_D6_D2 12 -#define CLK_TOP_MMPLL_D8 13 -#define CLK_TOP_APLL2_D4 14 -#define CLK_TOP_NET1PLL_D4 15 -#define CLK_TOP_NET1PLL_D5 16 -#define CLK_TOP_NET1PLL_D5_D2 17 -#define CLK_TOP_NET1PLL_D5_D4 18 -#define CLK_TOP_NET1PLL_D8 19 -#define CLK_TOP_NET1PLL_D8_D2 20 -#define CLK_TOP_NET1PLL_D8_D4 21 -#define CLK_TOP_NET1PLL_D8_D8 22 -#define CLK_TOP_NET1PLL_D8_D16 23 -#define CLK_TOP_NET2PLL_D2 24 -#define CLK_TOP_NET2PLL_D4 25 -#define CLK_TOP_NET2PLL_D4_D4 26 -#define CLK_TOP_NET2PLL_D4_D8 27 -#define CLK_TOP_NET2PLL_D6 28 -#define CLK_TOP_NET2PLL_D8 29 -#define CLK_TOP_NETSYS_SEL 30 -#define CLK_TOP_NETSYS_500M_SEL 31 -#define CLK_TOP_NETSYS_2X_SEL 32 -#define CLK_TOP_NETSYS_GSW_SEL 33 -#define CLK_TOP_ETH_GMII_SEL 34 -#define CLK_TOP_NETSYS_MCU_SEL 35 -#define CLK_TOP_NETSYS_PAO_2X_SEL 36 -#define CLK_TOP_EIP197_SEL 37 -#define CLK_TOP_AXI_INFRA_SEL 38 -#define CLK_TOP_UART_SEL 39 -#define CLK_TOP_EMMC_250M_SEL 40 -#define CLK_TOP_EMMC_400M_SEL 41 -#define CLK_TOP_SPI_SEL 42 -#define CLK_TOP_SPIM_MST_SEL 43 -#define CLK_TOP_NFI1X_SEL 44 -#define CLK_TOP_SPINFI_SEL 45 -#define CLK_TOP_PWM_SEL 46 -#define CLK_TOP_I2C_SEL 47 -#define CLK_TOP_PCIE_MBIST_250M_SEL 48 -#define CLK_TOP_PEXTP_TL_SEL 49 -#define CLK_TOP_PEXTP_TL_P1_SEL 50 -#define CLK_TOP_PEXTP_TL_P2_SEL 51 -#define CLK_TOP_PEXTP_TL_P3_SEL 52 -#define CLK_TOP_USB_SYS_SEL 53 -#define CLK_TOP_USB_SYS_P1_SEL 54 -#define CLK_TOP_USB_XHCI_SEL 55 -#define CLK_TOP_USB_XHCI_P1_SEL 56 -#define CLK_TOP_USB_FRMCNT_SEL 57 -#define CLK_TOP_USB_FRMCNT_P1_SEL 58 -#define CLK_TOP_AUD_SEL 59 -#define CLK_TOP_A1SYS_SEL 60 -#define CLK_TOP_AUD_L_SEL 61 -#define CLK_TOP_A_TUNER_SEL 62 -#define CLK_TOP_SSPXTP_SEL 63 -#define CLK_TOP_USB_PHY_SEL 64 -#define CLK_TOP_USXGMII_SBUS_0_SEL 65 -#define CLK_TOP_USXGMII_SBUS_1_SEL 66 -#define CLK_TOP_SGM_0_SEL 67 -#define CLK_TOP_SGM_SBUS_0_SEL 68 -#define CLK_TOP_SGM_1_SEL 69 -#define CLK_TOP_SGM_SBUS_1_SEL 70 -#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 -#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 -#define CLK_TOP_SYSAXI_SEL 73 -#define CLK_TOP_SYSAPB_SEL 74 -#define CLK_TOP_ETH_REFCK_50M_SEL 75 -#define CLK_TOP_ETH_SYS_200M_SEL 76 -#define CLK_TOP_ETH_SYS_SEL 77 -#define CLK_TOP_ETH_XGMII_SEL 78 -#define CLK_TOP_BUS_TOPS_SEL 79 -#define CLK_TOP_NPU_TOPS_SEL 80 -#define CLK_TOP_DRAMC_SEL 81 -#define CLK_TOP_DRAMC_MD32_SEL 82 -#define CLK_TOP_INFRA_F26M_SEL 83 -#define CLK_TOP_PEXTP_P0_SEL 84 -#define CLK_TOP_PEXTP_P1_SEL 85 -#define CLK_TOP_PEXTP_P2_SEL 86 -#define CLK_TOP_PEXTP_P3_SEL 87 -#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 -#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 -#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 -#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 -#define CLK_TOP_CKM_SEL 92 -#define CLK_TOP_DA_SEL 93 -#define CLK_TOP_PEXTP_SEL 94 -#define CLK_TOP_TOPS_P2_26M_SEL 95 -#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 -#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 -#define CLK_TOP_MACSEC_SEL 98 -#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 -#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 -#define CLK_TOP_NETSYS_WARP_SEL 101 -#define CLK_TOP_ETH_MII_SEL 102 -#define CLK_TOP_NPU_SEL 103 -#define CLK_TOP_AUD_I2S_M 104 - -/* MCUSYS */ - -#define CLK_MCU_BUS_DIV_SEL 0 -#define CLK_MCU_ARM_DIV_SEL 1 - -/* INFRACFG_AO */ - -#define CLK_INFRA_MUX_UART0_SEL 0 -#define CLK_INFRA_MUX_UART1_SEL 1 -#define CLK_INFRA_MUX_UART2_SEL 2 -#define CLK_INFRA_MUX_SPI0_SEL 3 -#define CLK_INFRA_MUX_SPI1_SEL 4 -#define CLK_INFRA_MUX_SPI2_SEL 5 -#define CLK_INFRA_PWM_SEL 6 -#define CLK_INFRA_PWM_CK1_SEL 7 -#define CLK_INFRA_PWM_CK2_SEL 8 -#define CLK_INFRA_PWM_CK3_SEL 9 -#define CLK_INFRA_PWM_CK4_SEL 10 -#define CLK_INFRA_PWM_CK5_SEL 11 -#define CLK_INFRA_PWM_CK6_SEL 12 -#define CLK_INFRA_PWM_CK7_SEL 13 -#define CLK_INFRA_PWM_CK8_SEL 14 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 - -/* INFRACFG */ - -#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 -#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 -#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 -#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 -#define CLK_INFRA_66M_GPT_BCK 23 -#define CLK_INFRA_66M_PWM_HCK 24 -#define CLK_INFRA_66M_PWM_BCK 25 -#define CLK_INFRA_66M_PWM_CK1 26 -#define CLK_INFRA_66M_PWM_CK2 27 -#define CLK_INFRA_66M_PWM_CK3 28 -#define CLK_INFRA_66M_PWM_CK4 29 -#define CLK_INFRA_66M_PWM_CK5 30 -#define CLK_INFRA_66M_PWM_CK6 31 -#define CLK_INFRA_66M_PWM_CK7 32 -#define CLK_INFRA_66M_PWM_CK8 33 -#define CLK_INFRA_133M_CQDMA_BCK 34 -#define CLK_INFRA_66M_AUD_SLV_BCK 35 -#define CLK_INFRA_AUD_26M 36 -#define CLK_INFRA_AUD_L 37 -#define CLK_INFRA_AUD_AUD 38 -#define CLK_INFRA_AUD_EG2 39 -#define CLK_INFRA_DRAMC_F26M 40 -#define CLK_INFRA_133M_DBG_ACKM 41 -#define CLK_INFRA_66M_AP_DMA_BCK 42 -#define CLK_INFRA_66M_SEJ_BCK 43 -#define CLK_INFRA_PRE_CK_SEJ_F13M 44 -#define CLK_INFRA_26M_THERM_SYSTEM 45 -#define CLK_INFRA_I2C_BCK 46 -#define CLK_INFRA_52M_UART0_CK 47 -#define CLK_INFRA_52M_UART1_CK 48 -#define CLK_INFRA_52M_UART2_CK 49 -#define CLK_INFRA_NFI 50 -#define CLK_INFRA_SPINFI 51 -#define CLK_INFRA_66M_NFI_HCK 52 -#define CLK_INFRA_104M_SPI0 53 -#define CLK_INFRA_104M_SPI1 54 -#define CLK_INFRA_104M_SPI2_BCK 55 -#define CLK_INFRA_66M_SPI0_HCK 56 -#define CLK_INFRA_66M_SPI1_HCK 57 -#define CLK_INFRA_66M_SPI2_HCK 58 -#define CLK_INFRA_66M_FLASHIF_AXI 59 -#define CLK_INFRA_RTC 60 -#define CLK_INFRA_26M_ADC_BCK 61 -#define CLK_INFRA_RC_ADC 62 -#define CLK_INFRA_MSDC400 63 -#define CLK_INFRA_MSDC2_HCK 64 -#define CLK_INFRA_133M_MSDC_0_HCK 65 -#define CLK_INFRA_66M_MSDC_0_HCK 66 -#define CLK_INFRA_133M_CPUM_BCK 67 -#define CLK_INFRA_BIST2FPC 68 -#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 -#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 -#define CLK_INFRA_133M_USB_HCK 71 -#define CLK_INFRA_133M_USB_HCK_CK_P1 72 -#define CLK_INFRA_66M_USB_HCK 73 -#define CLK_INFRA_66M_USB_HCK_CK_P1 74 -#define CLK_INFRA_USB_SYS 75 -#define CLK_INFRA_USB_SYS_CK_P1 76 -#define CLK_INFRA_USB_REF 77 -#define CLK_INFRA_USB_CK_P1 78 -#define CLK_INFRA_USB_FRMCNT 79 -#define CLK_INFRA_USB_FRMCNT_CK_P1 80 -#define CLK_INFRA_USB_PIPE 81 -#define CLK_INFRA_USB_PIPE_CK_P1 82 -#define CLK_INFRA_USB_UTMI 83 -#define CLK_INFRA_USB_UTMI_CK_P1 84 -#define CLK_INFRA_USB_XHCI 85 -#define CLK_INFRA_USB_XHCI_CK_P1 86 -#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 -#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 -#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 -#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 -#define CLK_INFRA_PCIE_PIPE_P0 91 -#define CLK_INFRA_PCIE_PIPE_P1 92 -#define CLK_INFRA_PCIE_PIPE_P2 93 -#define CLK_INFRA_PCIE_PIPE_P3 94 -#define CLK_INFRA_133M_PCIE_CK_P0 95 -#define CLK_INFRA_133M_PCIE_CK_P1 96 -#define CLK_INFRA_133M_PCIE_CK_P2 97 -#define CLK_INFRA_133M_PCIE_CK_P3 98 - -/* ETHDMA */ - -#define CLK_ETHDMA_XGP1_EN 0 -#define CLK_ETHDMA_XGP2_EN 1 -#define CLK_ETHDMA_XGP3_EN 2 -#define CLK_ETHDMA_FE_EN 3 -#define CLK_ETHDMA_GP2_EN 4 -#define CLK_ETHDMA_GP1_EN 5 -#define CLK_ETHDMA_GP3_EN 6 -#define CLK_ETHDMA_ESW_EN 7 -#define CLK_ETHDMA_CRYPT0_EN 8 -#define CLK_ETHDMA_NR_CLK 9 - -/* SGMIISYS_0 */ - -#define CLK_SGM0_TX_EN 0 -#define CLK_SGM0_RX_EN 1 -#define CLK_SGMII0_NR_CLK 2 - -/* SGMIISYS_1 */ - -#define CLK_SGM1_TX_EN 0 -#define CLK_SGM1_RX_EN 1 -#define CLK_SGMII1_NR_CLK 2 - -/* ETHWARP */ - -#define CLK_ETHWARP_WOCPU2_EN 0 -#define CLK_ETHWARP_WOCPU1_EN 1 -#define CLK_ETHWARP_WOCPU0_EN 2 -#define CLK_ETHWARP_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 9ad068fe0..3d85936c1 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -92,26 +92,32 @@ cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; - opp00 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <850000>; }; - opp01 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <850000>; }; - opp02 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <850000>; }; - opp03 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <900000>; }; + + opp04 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1000000>; + }; + + opp05 { + opp-hz = /bits/ 64 <2300000000>; + opp-microvolt = <1150000>; + }; }; }; diff --git a/target/linux/mediatek/files/block/partitions/fit.c b/target/linux/mediatek/files/block/partitions/fit.c index 463cd4e9a..01b0f42c7 100644 --- a/target/linux/mediatek/files/block/partitions/fit.c +++ b/target/linux/mediatek/files/block/partitions/fit.c @@ -161,7 +161,7 @@ int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, config = fdt_path_offset(fit, FIT_CONFS_PATH); if (config < 0) { - printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_CONFS_PATH, images); + printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_CONFS_PATH, config); ret = -ENOENT; goto ret_out; } diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Kconfig b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Kconfig deleted file mode 100644 index d9e0230cf..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ - -config MT753X_GSW - tristate "Driver for the MediaTek MT753x switch" diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Makefile b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Makefile deleted file mode 100644 index 7aae451cd..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for MediaTek MT753x gigabit switch -# - -obj-$(CONFIG_MT753X_GSW) += mt753x.o - -mt753x-$(CONFIG_SWCONFIG) += mt753x_swconfig.o - -mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \ - mt753x_common.o mt753x_vlan.o \ - mt753x_nl.o diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.c deleted file mode 100644 index 6a94d0d2f..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.c +++ /dev/null @@ -1,631 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#include -#include - -#include "mt753x.h" -#include "mt753x_regs.h" - -/* MT7530 registers */ - -/* Unique fields of PMCR for MT7530 */ -#define FORCE_MODE BIT(15) - -/* Unique fields of GMACCR for MT7530 */ -#define VLAN_SUPT_NO_S 14 -#define VLAN_SUPT_NO_M 0x1c000 -#define LATE_COL_DROP BIT(13) - -/* Unique fields of (M)HWSTRAP for MT7530 */ -#define BOND_OPTION BIT(24) -#define P5_PHY0_SEL BIT(20) -#define CHG_TRAP BIT(16) -#define LOOPDET_DIS BIT(14) -#define P5_INTF_SEL_GMAC5 BIT(13) -#define SMI_ADDR_S 11 -#define SMI_ADDR_M 0x1800 -#define XTAL_FSEL_S 9 -#define XTAL_FSEL_M 0x600 -#define P6_INTF_DIS BIT(8) -#define P5_INTF_MODE_RGMII BIT(7) -#define P5_INTF_DIS_S BIT(6) -#define C_MDIO_BPS_S BIT(5) -#define EEPROM_EN_S BIT(4) - -/* PHY EEE Register bitmap of define */ -#define PHY_DEV07 0x07 -#define PHY_DEV07_REG_03C 0x3c - -/* PHY Extend Register 0x14 bitmap of define */ -#define PHY_EXT_REG_14 0x14 - -/* Fields of PHY_EXT_REG_14 */ -#define PHY_EN_DOWN_SHFIT BIT(4) - -/* PHY Token Ring Register 0x10 bitmap of define */ -#define PHY_TR_REG_10 0x10 - -/* PHY Token Ring Register 0x12 bitmap of define */ -#define PHY_TR_REG_12 0x12 - -/* PHY LPI PCS/DSP Control Register bitmap of define */ -#define PHY_LPI_REG_11 0x11 - -/* PHY DEV 0x1e Register bitmap of define */ -#define PHY_DEV1E 0x1e -#define PHY_DEV1E_REG_123 0x123 -#define PHY_DEV1E_REG_A6 0xa6 - -/* Values of XTAL_FSEL */ -#define XTAL_20MHZ 1 -#define XTAL_40MHZ 2 -#define XTAL_25MHZ 3 - -#define P6ECR 0x7830 -#define P6_INTF_MODE_TRGMII BIT(0) - -#define TRGMII_TXCTRL 0x7a40 -#define TRAIN_TXEN BIT(31) -#define TXC_INV BIT(30) -#define TX_DOEO BIT(29) -#define TX_RST BIT(28) - -#define TRGMII_TD0_CTRL 0x7a50 -#define TRGMII_TD1_CTRL 0x7a58 -#define TRGMII_TD2_CTRL 0x7a60 -#define TRGMII_TD3_CTRL 0x7a68 -#define TRGMII_TXCTL_CTRL 0x7a70 -#define TRGMII_TCK_CTRL 0x7a78 -#define TRGMII_TD_CTRL(n) (0x7a50 + (n) * 8) -#define NUM_TRGMII_CTRL 6 -#define TX_DMPEDRV BIT(31) -#define TX_DM_SR BIT(15) -#define TX_DMERODT BIT(14) -#define TX_DMOECTL BIT(13) -#define TX_TAP_S 8 -#define TX_TAP_M 0xf00 -#define TX_TRAIN_WD_S 0 -#define TX_TRAIN_WD_M 0xff - -#define TRGMII_TD0_ODT 0x7a54 -#define TRGMII_TD1_ODT 0x7a5c -#define TRGMII_TD2_ODT 0x7a64 -#define TRGMII_TD3_ODT 0x7a6c -#define TRGMII_TXCTL_ODT 0x7574 -#define TRGMII_TCK_ODT 0x757c -#define TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) -#define NUM_TRGMII_ODT 6 -#define TX_DM_DRVN_PRE_S 30 -#define TX_DM_DRVN_PRE_M 0xc0000000 -#define TX_DM_DRVP_PRE_S 28 -#define TX_DM_DRVP_PRE_M 0x30000000 -#define TX_DM_TDSEL_S 24 -#define TX_DM_TDSEL_M 0xf000000 -#define TX_ODTEN BIT(23) -#define TX_DME_PRE BIT(20) -#define TX_DM_DRVNT0 BIT(19) -#define TX_DM_DRVPT0 BIT(18) -#define TX_DM_DRVNTE BIT(17) -#define TX_DM_DRVPTE BIT(16) -#define TX_DM_ODTN_S 12 -#define TX_DM_ODTN_M 0x7000 -#define TX_DM_ODTP_S 8 -#define TX_DM_ODTP_M 0x700 -#define TX_DM_DRVN_S 4 -#define TX_DM_DRVN_M 0xf0 -#define TX_DM_DRVP_S 0 -#define TX_DM_DRVP_M 0x0f - -#define P5RGMIIRXCR 0x7b00 -#define CSR_RGMII_RCTL_CFG_S 24 -#define CSR_RGMII_RCTL_CFG_M 0x7000000 -#define CSR_RGMII_RXD_CFG_S 16 -#define CSR_RGMII_RXD_CFG_M 0x70000 -#define CSR_RGMII_EDGE_ALIGN BIT(8) -#define CSR_RGMII_RXC_90DEG_CFG_S 4 -#define CSR_RGMII_RXC_90DEG_CFG_M 0xf0 -#define CSR_RGMII_RXC_0DEG_CFG_S 0 -#define CSR_RGMII_RXC_0DEG_CFG_M 0x0f - -#define P5RGMIITXCR 0x7b04 -#define CSR_RGMII_TXEN_CFG_S 16 -#define CSR_RGMII_TXEN_CFG_M 0x70000 -#define CSR_RGMII_TXD_CFG_S 8 -#define CSR_RGMII_TXD_CFG_M 0x700 -#define CSR_RGMII_TXC_CFG_S 0 -#define CSR_RGMII_TXC_CFG_M 0x1f - -#define CHIP_REV 0x7ffc -#define CHIP_NAME_S 16 -#define CHIP_NAME_M 0xffff0000 -#define CHIP_REV_S 0 -#define CHIP_REV_M 0x0f - -/* MMD registers */ -#define CORE_PLL_GROUP2 0x401 -#define RG_SYSPLL_EN_NORMAL BIT(15) -#define RG_SYSPLL_VODEN BIT(14) -#define RG_SYSPLL_POSDIV_S 5 -#define RG_SYSPLL_POSDIV_M 0x60 - -#define CORE_PLL_GROUP4 0x403 -#define RG_SYSPLL_DDSFBK_EN BIT(12) -#define RG_SYSPLL_BIAS_EN BIT(11) -#define RG_SYSPLL_BIAS_LPF_EN BIT(10) - -#define CORE_PLL_GROUP5 0x404 -#define RG_LCDDS_PCW_NCPO1_S 0 -#define RG_LCDDS_PCW_NCPO1_M 0xffff - -#define CORE_PLL_GROUP6 0x405 -#define RG_LCDDS_PCW_NCPO0_S 0 -#define RG_LCDDS_PCW_NCPO0_M 0xffff - -#define CORE_PLL_GROUP7 0x406 -#define RG_LCDDS_PWDB BIT(15) -#define RG_LCDDS_ISO_EN BIT(13) -#define RG_LCCDS_C_S 4 -#define RG_LCCDS_C_M 0x70 -#define RG_LCDDS_PCW_NCPO_CHG BIT(3) - -#define CORE_PLL_GROUP10 0x409 -#define RG_LCDDS_SSC_DELTA_S 0 -#define RG_LCDDS_SSC_DELTA_M 0xfff - -#define CORE_PLL_GROUP11 0x40a -#define RG_LCDDS_SSC_DELTA1_S 0 -#define RG_LCDDS_SSC_DELTA1_M 0xfff - -#define CORE_GSWPLL_GCR_1 0x040d -#define GSWPLL_PREDIV_S 14 -#define GSWPLL_PREDIV_M 0xc000 -#define GSWPLL_POSTDIV_200M_S 12 -#define GSWPLL_POSTDIV_200M_M 0x3000 -#define GSWPLL_EN_PRE BIT(11) -#define GSWPLL_FBKSEL BIT(10) -#define GSWPLL_BP BIT(9) -#define GSWPLL_BR BIT(8) -#define GSWPLL_FBKDIV_200M_S 0 -#define GSWPLL_FBKDIV_200M_M 0xff - -#define CORE_GSWPLL_GCR_2 0x040e -#define GSWPLL_POSTDIV_500M_S 8 -#define GSWPLL_POSTDIV_500M_M 0x300 -#define GSWPLL_FBKDIV_500M_S 0 -#define GSWPLL_FBKDIV_500M_M 0xff - -#define TRGMII_GSW_CLK_CG 0x0410 -#define TRGMIICK_EN BIT(1) -#define GSWCK_EN BIT(0) - -static int mt7530_mii_read(struct gsw_mt753x *gsw, int phy, int reg) -{ - if (phy < MT753X_NUM_PHYS) - phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK; - - return mdiobus_read(gsw->host_bus, phy, reg); -} - -static void mt7530_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val) -{ - if (phy < MT753X_NUM_PHYS) - phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK; - - mdiobus_write(gsw->host_bus, phy, reg, val); -} - -static int mt7530_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg) -{ - u16 val; - - if (addr < MT753X_NUM_PHYS) - addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->host_bus->mdio_lock); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); - - val = gsw->host_bus->read(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG); - - mutex_unlock(&gsw->host_bus->mdio_lock); - - return val; -} - -static void mt7530_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, - u16 reg, u16 val) -{ - if (addr < MT753X_NUM_PHYS) - addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->host_bus->mdio_lock); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); - - gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, val); - - mutex_unlock(&gsw->host_bus->mdio_lock); -} - -static void mt7530_core_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val) -{ - gsw->mmd_write(gsw, 0, 0x1f, reg, val); -} - -static void mt7530_trgmii_setting(struct gsw_mt753x *gsw) -{ - u16 i; - - mt7530_core_reg_write(gsw, CORE_PLL_GROUP5, 0x0780); - mdelay(1); - mt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0); - mt7530_core_reg_write(gsw, CORE_PLL_GROUP10, 0x87); - mdelay(1); - mt7530_core_reg_write(gsw, CORE_PLL_GROUP11, 0x87); - - /* PLL BIAS enable */ - mt7530_core_reg_write(gsw, CORE_PLL_GROUP4, - RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN); - mdelay(1); - - /* PLL LPF enable */ - mt7530_core_reg_write(gsw, CORE_PLL_GROUP4, - RG_SYSPLL_DDSFBK_EN | - RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); - - /* sys PLL enable */ - mt7530_core_reg_write(gsw, CORE_PLL_GROUP2, - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | - (1 << RG_SYSPLL_POSDIV_S)); - - /* LCDDDS PWDS */ - mt7530_core_reg_write(gsw, CORE_PLL_GROUP7, - (3 << RG_LCCDS_C_S) | - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); - mdelay(1); - - /* Enable MT7530 TRGMII clock */ - mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN | TRGMIICK_EN); - - /* lower Tx Driving */ - for (i = 0 ; i < NUM_TRGMII_ODT; i++) - mt753x_reg_write(gsw, TRGMII_TD_ODT(i), - (4 << TX_DM_DRVP_S) | (4 << TX_DM_DRVN_S)); -} - -static void mt7530_rgmii_setting(struct gsw_mt753x *gsw) -{ - u32 val; - - mt7530_core_reg_write(gsw, CORE_PLL_GROUP5, 0x0c80); - mdelay(1); - mt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0); - mt7530_core_reg_write(gsw, CORE_PLL_GROUP10, 0x87); - mdelay(1); - mt7530_core_reg_write(gsw, CORE_PLL_GROUP11, 0x87); - - val = mt753x_reg_read(gsw, TRGMII_TXCTRL); - val &= ~TXC_INV; - mt753x_reg_write(gsw, TRGMII_TXCTRL, val); - - mt753x_reg_write(gsw, TRGMII_TCK_CTRL, - (8 << TX_TAP_S) | (0x55 << TX_TRAIN_WD_S)); -} - -static int mt7530_mac_port_setup(struct gsw_mt753x *gsw) -{ - u32 hwstrap, p6ecr = 0, p5mcr, p6mcr, phyad; - - hwstrap = mt753x_reg_read(gsw, MHWSTRAP); - hwstrap &= ~(P6_INTF_DIS | P5_INTF_MODE_RGMII | P5_INTF_DIS_S); - hwstrap |= P5_INTF_SEL_GMAC5; - if (!gsw->port5_cfg.enabled) { - p5mcr = FORCE_MODE; - hwstrap |= P5_INTF_DIS_S; - } else { - p5mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN; - - if (gsw->port5_cfg.force_link) { - p5mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC | - FORCE_TX_FC; - p5mcr |= gsw->port5_cfg.speed << FORCE_SPD_S; - - if (gsw->port5_cfg.duplex) - p5mcr |= FORCE_DPX; - } - - switch (gsw->port5_cfg.phy_mode) { - case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_GMII: - break; - case PHY_INTERFACE_MODE_RGMII: - hwstrap |= P5_INTF_MODE_RGMII; - break; - default: - dev_info(gsw->dev, "%s is not supported by port5\n", - phy_modes(gsw->port5_cfg.phy_mode)); - p5mcr = FORCE_MODE; - hwstrap |= P5_INTF_DIS_S; - } - - /* Port5 to PHY direct mode */ - if (of_property_read_u32(gsw->port5_cfg.np, "phy-address", - &phyad)) - goto parse_p6; - - if (phyad != 0 && phyad != 4) { - dev_info(gsw->dev, - "Only PHY 0/4 can be connected to Port 5\n"); - goto parse_p6; - } - - hwstrap &= ~P5_INTF_SEL_GMAC5; - if (phyad == 0) - hwstrap |= P5_PHY0_SEL; - else - hwstrap &= ~P5_PHY0_SEL; - } - -parse_p6: - if (!gsw->port6_cfg.enabled) { - p6mcr = FORCE_MODE; - hwstrap |= P6_INTF_DIS; - } else { - p6mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN; - - if (gsw->port6_cfg.force_link) { - p6mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC | - FORCE_TX_FC; - p6mcr |= gsw->port6_cfg.speed << FORCE_SPD_S; - - if (gsw->port6_cfg.duplex) - p6mcr |= FORCE_DPX; - } - - switch (gsw->port6_cfg.phy_mode) { - case PHY_INTERFACE_MODE_RGMII: - p6ecr = BIT(1); - break; - case PHY_INTERFACE_MODE_TRGMII: - /* set MT7530 central align */ - p6ecr = BIT(0); - break; - default: - dev_info(gsw->dev, "%s is not supported by port6\n", - phy_modes(gsw->port6_cfg.phy_mode)); - p6mcr = FORCE_MODE; - hwstrap |= P6_INTF_DIS; - } - } - - mt753x_reg_write(gsw, MHWSTRAP, hwstrap); - mt753x_reg_write(gsw, P6ECR, p6ecr); - - mt753x_reg_write(gsw, PMCR(5), p5mcr); - mt753x_reg_write(gsw, PMCR(6), p6mcr); - - return 0; -} - -static void mt7530_core_pll_setup(struct gsw_mt753x *gsw) -{ - u32 hwstrap; - - hwstrap = mt753x_reg_read(gsw, HWSTRAP); - - switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) { - case XTAL_40MHZ: - /* Disable MT7530 core clock */ - mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, 0); - - /* disable MT7530 PLL */ - mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1, - (2 << GSWPLL_POSTDIV_200M_S) | - (32 << GSWPLL_FBKDIV_200M_S)); - - /* For MT7530 core clock = 500Mhz */ - mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_2, - (1 << GSWPLL_POSTDIV_500M_S) | - (25 << GSWPLL_FBKDIV_500M_S)); - - /* Enable MT7530 PLL */ - mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1, - (2 << GSWPLL_POSTDIV_200M_S) | - (32 << GSWPLL_FBKDIV_200M_S) | - GSWPLL_EN_PRE); - - usleep_range(20, 40); - - /* Enable MT7530 core clock */ - mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN); - break; - default: - /* TODO: PLL settings for 20/25MHz */ - break; - } - - hwstrap = mt753x_reg_read(gsw, HWSTRAP); - hwstrap |= CHG_TRAP; - if (gsw->direct_phy_access) - hwstrap &= ~C_MDIO_BPS_S; - else - hwstrap |= C_MDIO_BPS_S; - - mt753x_reg_write(gsw, MHWSTRAP, hwstrap); - - if (gsw->port6_cfg.enabled && - gsw->port6_cfg.phy_mode == PHY_INTERFACE_MODE_TRGMII) { - mt7530_trgmii_setting(gsw); - } else { - /* RGMII */ - mt7530_rgmii_setting(gsw); - } - - /* delay setting for 10/1000M */ - mt753x_reg_write(gsw, P5RGMIIRXCR, - CSR_RGMII_EDGE_ALIGN | - (2 << CSR_RGMII_RXC_0DEG_CFG_S)); - mt753x_reg_write(gsw, P5RGMIITXCR, 0x14 << CSR_RGMII_TXC_CFG_S); -} - -static int mt7530_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev) -{ - u32 rev; - - rev = mt753x_reg_read(gsw, CHIP_REV); - - if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7530) { - if (crev) { - crev->rev = rev & CHIP_REV_M; - crev->name = "MT7530"; - } - - return 0; - } - - return -ENODEV; -} - -static void mt7530_phy_setting(struct gsw_mt753x *gsw) -{ - int i; - u32 val; - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - /* Disable EEE */ - gsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0); - - /* Enable HW auto downshift */ - gsw->mii_write(gsw, i, 0x1f, 0x1); - val = gsw->mii_read(gsw, i, PHY_EXT_REG_14); - val |= PHY_EN_DOWN_SHFIT; - gsw->mii_write(gsw, i, PHY_EXT_REG_14, val); - - /* Increase SlvDPSready time */ - gsw->mii_write(gsw, i, 0x1f, 0x52b5); - gsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae); - gsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f); - gsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae); - - /* Increase post_update_timer */ - gsw->mii_write(gsw, i, 0x1f, 0x3); - gsw->mii_write(gsw, i, PHY_LPI_REG_11, 0x4b); - gsw->mii_write(gsw, i, 0x1f, 0); - - /* Adjust 100_mse_threshold */ - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff); - - /* Disable mcc */ - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300); - } -} - -static inline bool get_phy_access_mode(const struct device_node *np) -{ - return of_property_read_bool(np, "mt7530,direct-phy-access"); -} - -static int mt7530_sw_init(struct gsw_mt753x *gsw) -{ - int i; - u32 val; - - gsw->direct_phy_access = get_phy_access_mode(gsw->dev->of_node); - - /* Force MT7530 to use (in)direct PHY access */ - val = mt753x_reg_read(gsw, HWSTRAP); - val |= CHG_TRAP; - if (gsw->direct_phy_access) - val &= ~C_MDIO_BPS_S; - else - val |= C_MDIO_BPS_S; - mt753x_reg_write(gsw, MHWSTRAP, val); - - /* Read PHY address base from HWSTRAP */ - gsw->phy_base = (((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3) + 8; - gsw->phy_base &= MT753X_SMI_ADDR_MASK; - - if (gsw->direct_phy_access) { - gsw->mii_read = mt7530_mii_read; - gsw->mii_write = mt7530_mii_write; - gsw->mmd_read = mt7530_mmd_read; - gsw->mmd_write = mt7530_mmd_write; - } else { - gsw->mii_read = mt753x_mii_read; - gsw->mii_write = mt753x_mii_write; - gsw->mmd_read = mt753x_mmd_ind_read; - gsw->mmd_write = mt753x_mmd_ind_write; - } - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - val = gsw->mii_read(gsw, i, MII_BMCR); - val |= BMCR_PDOWN; - gsw->mii_write(gsw, i, MII_BMCR, val); - } - - /* Force MAC link down before reset */ - mt753x_reg_write(gsw, PMCR(5), FORCE_MODE); - mt753x_reg_write(gsw, PMCR(6), FORCE_MODE); - - /* Switch soft reset */ - /* BUG: sw reset causes gsw int flooding */ - mt753x_reg_write(gsw, SYS_CTRL, SW_PHY_RST | SW_SYS_RST | SW_REG_RST); - usleep_range(10, 20); - - /* global mac control settings configuration */ - mt753x_reg_write(gsw, GMACCR, - LATE_COL_DROP | (15 << MTCC_LMT_S) | - (2 << MAX_RX_JUMBO_S) | RX_PKT_LEN_MAX_JUMBO); - - mt7530_core_pll_setup(gsw); - mt7530_mac_port_setup(gsw); - - return 0; -} - -static int mt7530_sw_post_init(struct gsw_mt753x *gsw) -{ - int i; - u32 val; - - mt7530_phy_setting(gsw); - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - val = gsw->mii_read(gsw, i, MII_BMCR); - val &= ~BMCR_PDOWN; - gsw->mii_write(gsw, i, MII_BMCR, val); - } - - return 0; -} - -struct mt753x_sw_id mt7530_id = { - .model = MT7530, - .detect = mt7530_sw_detect, - .init = mt7530_sw_init, - .post_init = mt7530_sw_post_init -}; diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.h deleted file mode 100644 index 40243d4e5..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - */ - -#ifndef _MT7530_H_ -#define _MT7530_H_ - -#include "mt753x.h" - -extern struct mt753x_sw_id mt7530_id; - -#endif /* _MT7530_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.c deleted file mode 100644 index 7ebf09c10..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.c +++ /dev/null @@ -1,918 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Zhanguo Ju - */ - -#include -#include -#include - -#include "mt753x.h" -#include "mt753x_regs.h" - -/* MT7531 registers */ -#define SGMII_REG_BASE 0x5000 -#define SGMII_REG_PORT_BASE 0x1000 -#define SGMII_REG(p, r) (SGMII_REG_BASE + \ - (p) * SGMII_REG_PORT_BASE + (r)) -#define PCS_CONTROL_1(p) SGMII_REG(p, 0x00) -#define SGMII_MODE(p) SGMII_REG(p, 0x20) -#define QPHY_PWR_STATE_CTRL(p) SGMII_REG(p, 0xe8) -#define PHYA_CTRL_SIGNAL3(p) SGMII_REG(p, 0x128) - -/* Fields of PCS_CONTROL_1 */ -#define SGMII_LINK_STATUS BIT(18) -#define SGMII_AN_ENABLE BIT(12) -#define SGMII_AN_RESTART BIT(9) - -/* Fields of SGMII_MODE */ -#define SGMII_REMOTE_FAULT_DIS BIT(8) -#define SGMII_IF_MODE_FORCE_DUPLEX BIT(4) -#define SGMII_IF_MODE_FORCE_SPEED_S 0x2 -#define SGMII_IF_MODE_FORCE_SPEED_M 0x0c -#define SGMII_IF_MODE_ADVERT_AN BIT(1) - -/* Values of SGMII_IF_MODE_FORCE_SPEED */ -#define SGMII_IF_MODE_FORCE_SPEED_10 0 -#define SGMII_IF_MODE_FORCE_SPEED_100 1 -#define SGMII_IF_MODE_FORCE_SPEED_1000 2 - -/* Fields of QPHY_PWR_STATE_CTRL */ -#define PHYA_PWD BIT(4) - -/* Fields of PHYA_CTRL_SIGNAL3 */ -#define RG_TPHY_SPEED_S 2 -#define RG_TPHY_SPEED_M 0x0c - -/* Values of RG_TPHY_SPEED */ -#define RG_TPHY_SPEED_1000 0 -#define RG_TPHY_SPEED_2500 1 - -/* Unique fields of (M)HWSTRAP for MT7531 */ -#define XTAL_FSEL_S 7 -#define XTAL_FSEL_M BIT(7) -#define PHY_EN BIT(6) -#define CHG_STRAP BIT(8) - -/* Efuse Register Define */ -#define GBE_EFUSE 0x7bc8 -#define GBE_SEL_EFUSE_EN BIT(0) - -/* PHY ENABLE Register bitmap define */ -#define PHY_DEV1F 0x1f -#define PHY_DEV1F_REG_44 0x44 -#define PHY_DEV1F_REG_104 0x104 -#define PHY_DEV1F_REG_10A 0x10a -#define PHY_DEV1F_REG_10B 0x10b -#define PHY_DEV1F_REG_10C 0x10c -#define PHY_DEV1F_REG_10D 0x10d -#define PHY_DEV1F_REG_268 0x268 -#define PHY_DEV1F_REG_269 0x269 -#define PHY_DEV1F_REG_403 0x403 - -/* Fields of PHY_DEV1F_REG_403 */ -#define GBE_EFUSE_SETTING BIT(3) -#define PHY_EN_BYPASS_MODE BIT(4) -#define POWER_ON_OFF BIT(5) -#define PHY_PLL_M GENMASK(9, 8) -#define PHY_PLL_SEL(x) (((x) << 8) & GENMASK(9, 8)) - -/* PHY EEE Register bitmap of define */ -#define PHY_DEV07 0x07 -#define PHY_DEV07_REG_03C 0x3c - -/* PHY Extend Register 0x14 bitmap of define */ -#define PHY_EXT_REG_14 0x14 - -/* Fields of PHY_EXT_REG_14 */ -#define PHY_EN_DOWN_SHFIT BIT(4) - -/* PHY Extend Register 0x17 bitmap of define */ -#define PHY_EXT_REG_17 0x17 - -/* Fields of PHY_EXT_REG_17 */ -#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) - -/* PHY Token Ring Register 0x10 bitmap of define */ -#define PHY_TR_REG_10 0x10 - -/* PHY Token Ring Register 0x12 bitmap of define */ -#define PHY_TR_REG_12 0x12 - -/* PHY DEV 0x1e Register bitmap of define */ -#define PHY_DEV1E 0x1e -#define PHY_DEV1E_REG_13 0x13 -#define PHY_DEV1E_REG_14 0x14 -#define PHY_DEV1E_REG_41 0x41 -#define PHY_DEV1E_REG_A6 0xa6 -#define PHY_DEV1E_REG_0C6 0x0c6 -#define PHY_DEV1E_REG_0FE 0x0fe -#define PHY_DEV1E_REG_123 0x123 -#define PHY_DEV1E_REG_189 0x189 - -/* Fields of PHY_DEV1E_REG_0C6 */ -#define PHY_POWER_SAVING_S 8 -#define PHY_POWER_SAVING_M 0x300 -#define PHY_POWER_SAVING_TX 0x0 - -/* Fields of PHY_DEV1E_REG_189 */ -#define DESCRAMBLER_CLEAR_EN 0x1 - -/* Values of XTAL_FSEL_S */ -#define XTAL_40MHZ 0 -#define XTAL_25MHZ 1 - -#define PLLGP_EN 0x7820 -#define EN_COREPLL BIT(2) -#define SW_CLKSW BIT(1) -#define SW_PLLGP BIT(0) - -#define PLLGP_CR0 0x78a8 -#define RG_COREPLL_EN BIT(22) -#define RG_COREPLL_POSDIV_S 23 -#define RG_COREPLL_POSDIV_M 0x3800000 -#define RG_COREPLL_SDM_PCW_S 1 -#define RG_COREPLL_SDM_PCW_M 0x3ffffe -#define RG_COREPLL_SDM_PCW_CHG BIT(0) - -/* TOP Signals Status Register */ -#define TOP_SIG_SR 0x780c -#define PAD_DUAL_SGMII_EN BIT(1) - -/* RGMII and SGMII PLL clock */ -#define ANA_PLLGP_CR2 0x78b0 -#define ANA_PLLGP_CR5 0x78bc - -/* GPIO mode define */ -#define GPIO_MODE_REGS(x) (0x7c0c + (((x) / 8) * 4)) -#define GPIO_MODE_S 4 - -/* GPIO GROUP IOLB SMT0 Control */ -#define SMT0_IOLB 0x7f04 -#define SMT_IOLB_5_SMI_MDC_EN BIT(5) - -/* Unique fields of PMCR for MT7531 */ -#define FORCE_MODE_EEE1G BIT(25) -#define FORCE_MODE_EEE100 BIT(26) -#define FORCE_MODE_TX_FC BIT(27) -#define FORCE_MODE_RX_FC BIT(28) -#define FORCE_MODE_DPX BIT(29) -#define FORCE_MODE_SPD BIT(30) -#define FORCE_MODE_LNK BIT(31) -#define FORCE_MODE BIT(15) - -#define CHIP_REV 0x781C -#define CHIP_NAME_S 16 -#define CHIP_NAME_M 0xffff0000 -#define CHIP_REV_S 0 -#define CHIP_REV_M 0x0f -#define CHIP_REV_E1 0x0 - -#define CLKGEN_CTRL 0x7500 -#define CLK_SKEW_OUT_S 8 -#define CLK_SKEW_OUT_M 0x300 -#define CLK_SKEW_IN_S 6 -#define CLK_SKEW_IN_M 0xc0 -#define RXCLK_NO_DELAY BIT(5) -#define TXCLK_NO_REVERSE BIT(4) -#define GP_MODE_S 1 -#define GP_MODE_M 0x06 -#define GP_CLK_EN BIT(0) - -/* Values of GP_MODE */ -#define GP_MODE_RGMII 0 -#define GP_MODE_MII 1 -#define GP_MODE_REV_MII 2 - -/* Values of CLK_SKEW_IN */ -#define CLK_SKEW_IN_NO_CHANGE 0 -#define CLK_SKEW_IN_DELAY_100PPS 1 -#define CLK_SKEW_IN_DELAY_200PPS 2 -#define CLK_SKEW_IN_REVERSE 3 - -/* Values of CLK_SKEW_OUT */ -#define CLK_SKEW_OUT_NO_CHANGE 0 -#define CLK_SKEW_OUT_DELAY_100PPS 1 -#define CLK_SKEW_OUT_DELAY_200PPS 2 -#define CLK_SKEW_OUT_REVERSE 3 - -/* Proprietory Control Register of Internal Phy device 0x1e */ -#define RXADC_CONTROL_3 0xc2 -#define RXADC_LDO_CONTROL_2 0xd3 - -/* Proprietory Control Register of Internal Phy device 0x1f */ -#define TXVLD_DA_271 0x271 -#define TXVLD_DA_272 0x272 -#define TXVLD_DA_273 0x273 - -/* DSP Channel and NOD_ADDR*/ -#define DSP_CH 0x2 -#define DSP_NOD_ADDR 0xD - -/* gpio pinmux pins and functions define */ -static int gpio_int_pins[] = {0}; -static int gpio_int_funcs[] = {1}; -static int gpio_mdc_pins[] = {11, 20}; -static int gpio_mdc_funcs[] = {2, 2}; -static int gpio_mdio_pins[] = {12, 21}; -static int gpio_mdio_funcs[] = {2, 2}; - -static int mt7531_set_port_sgmii_force_mode(struct gsw_mt753x *gsw, u32 port, - struct mt753x_port_cfg *port_cfg) -{ - u32 speed, port_base, val; - ktime_t timeout; - u32 timeout_us; - - if (port < 5 || port >= MT753X_NUM_PORTS) { - dev_info(gsw->dev, "port %d is not a SGMII port\n", port); - return -EINVAL; - } - - port_base = port - 5; - - switch (port_cfg->speed) { - case MAC_SPD_1000: - speed = RG_TPHY_SPEED_1000; - break; - case MAC_SPD_2500: - speed = RG_TPHY_SPEED_2500; - break; - default: - dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n", - port_cfg->speed, port); - - speed = RG_TPHY_SPEED_1000; - } - - /* Step 1: Speed select register setting */ - val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base)); - val &= ~RG_TPHY_SPEED_M; - val |= speed << RG_TPHY_SPEED_S; - mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val); - - /* Step 2 : Disable AN */ - val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); - val &= ~SGMII_AN_ENABLE; - mt753x_reg_write(gsw, PCS_CONTROL_1(port_base), val); - - /* Step 3: SGMII force mode setting */ - val = mt753x_reg_read(gsw, SGMII_MODE(port_base)); - val &= ~SGMII_IF_MODE_ADVERT_AN; - val &= ~SGMII_IF_MODE_FORCE_SPEED_M; - val |= SGMII_IF_MODE_FORCE_SPEED_1000 << SGMII_IF_MODE_FORCE_SPEED_S; - val |= SGMII_IF_MODE_FORCE_DUPLEX; - /* For sgmii force mode, 0 is full duplex and 1 is half duplex */ - if (port_cfg->duplex) - val &= ~SGMII_IF_MODE_FORCE_DUPLEX; - - mt753x_reg_write(gsw, SGMII_MODE(port_base), val); - - /* Step 4: XXX: Disable Link partner's AN and set force mode */ - - /* Step 5: XXX: Special setting for PHYA ==> reserved for flexible */ - - /* Step 6 : Release PHYA power down state */ - val = mt753x_reg_read(gsw, QPHY_PWR_STATE_CTRL(port_base)); - val &= ~PHYA_PWD; - mt753x_reg_write(gsw, QPHY_PWR_STATE_CTRL(port_base), val); - - /* Step 7 : Polling SGMII_LINK_STATUS */ - timeout_us = 2000000; - timeout = ktime_add_us(ktime_get(), timeout_us); - while (1) { - val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); - val &= SGMII_LINK_STATUS; - - if (val) - break; - - if (ktime_compare(ktime_get(), timeout) > 0) - return -ETIMEDOUT; - } - - return 0; -} - -static int mt7531_set_port_sgmii_an_mode(struct gsw_mt753x *gsw, u32 port, - struct mt753x_port_cfg *port_cfg) -{ - u32 speed, port_base, val; - ktime_t timeout; - u32 timeout_us; - - if (port < 5 || port >= MT753X_NUM_PORTS) { - dev_info(gsw->dev, "port %d is not a SGMII port\n", port); - return -EINVAL; - } - - port_base = port - 5; - - switch (port_cfg->speed) { - case MAC_SPD_1000: - speed = RG_TPHY_SPEED_1000; - break; - case MAC_SPD_2500: - speed = RG_TPHY_SPEED_2500; - break; - default: - dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n", - port_cfg->speed, port); - - speed = RG_TPHY_SPEED_1000; - } - - /* Step 1: Speed select register setting */ - val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base)); - val &= ~RG_TPHY_SPEED_M; - val |= speed << RG_TPHY_SPEED_S; - mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val); - - /* Step 2: Remote fault disable */ - val = mt753x_reg_read(gsw, SGMII_MODE(port)); - val |= SGMII_REMOTE_FAULT_DIS; - mt753x_reg_write(gsw, SGMII_MODE(port), val); - - /* Step 3: Setting Link partner's AN enable = 1 */ - - /* Step 4: Setting Link partner's device ability for speed/duplex */ - - /* Step 5: AN re-start */ - val = mt753x_reg_read(gsw, PCS_CONTROL_1(port)); - val |= SGMII_AN_RESTART; - mt753x_reg_write(gsw, PCS_CONTROL_1(port), val); - - /* Step 6: Special setting for PHYA ==> reserved for flexible */ - - /* Step 7 : Polling SGMII_LINK_STATUS */ - timeout_us = 2000000; - timeout = ktime_add_us(ktime_get(), timeout_us); - while (1) { - val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); - val &= SGMII_LINK_STATUS; - - if (val) - break; - - if (ktime_compare(ktime_get(), timeout) > 0) - return -ETIMEDOUT; - } - - return 0; -} - -static int mt7531_set_port_rgmii(struct gsw_mt753x *gsw, u32 port) -{ - u32 val; - - if (port != 5) { - dev_info(gsw->dev, "RGMII mode is not available for port %d\n", - port); - return -EINVAL; - } - - val = mt753x_reg_read(gsw, CLKGEN_CTRL); - val |= GP_CLK_EN; - val &= ~GP_MODE_M; - val |= GP_MODE_RGMII << GP_MODE_S; - val |= TXCLK_NO_REVERSE; - val |= RXCLK_NO_DELAY; - val &= ~CLK_SKEW_IN_M; - val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; - val &= ~CLK_SKEW_OUT_M; - val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; - mt753x_reg_write(gsw, CLKGEN_CTRL, val); - - return 0; -} - -static int mt7531_mac_port_setup(struct gsw_mt753x *gsw, u32 port, - struct mt753x_port_cfg *port_cfg) -{ - u32 pmcr; - u32 speed; - - if (port < 5 || port >= MT753X_NUM_PORTS) { - dev_info(gsw->dev, "port %d is not a MAC port\n", port); - return -EINVAL; - } - - if (port_cfg->enabled) { - pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN; - - if (port_cfg->force_link) { - /* PMCR's speed field 0x11 is reserved, - * sw should set 0x10 - */ - speed = port_cfg->speed; - if (port_cfg->speed == MAC_SPD_2500) - speed = MAC_SPD_1000; - - pmcr |= FORCE_MODE_LNK | FORCE_LINK | - FORCE_MODE_SPD | FORCE_MODE_DPX | - FORCE_MODE_RX_FC | FORCE_MODE_TX_FC | - FORCE_RX_FC | FORCE_TX_FC | - (speed << FORCE_SPD_S); - - if (port_cfg->duplex) - pmcr |= FORCE_DPX; - } - } else { - pmcr = FORCE_MODE_LNK; - } - - switch (port_cfg->phy_mode) { - case PHY_INTERFACE_MODE_RGMII: - mt7531_set_port_rgmii(gsw, port); - break; - case PHY_INTERFACE_MODE_SGMII: - if (port_cfg->force_link) - mt7531_set_port_sgmii_force_mode(gsw, port, port_cfg); - else - mt7531_set_port_sgmii_an_mode(gsw, port, port_cfg); - break; - default: - if (port_cfg->enabled) - dev_info(gsw->dev, "%s is not supported by port %d\n", - phy_modes(port_cfg->phy_mode), port); - - pmcr = FORCE_MODE_LNK; - } - - mt753x_reg_write(gsw, PMCR(port), pmcr); - - return 0; -} - -static void mt7531_core_pll_setup(struct gsw_mt753x *gsw) -{ - u32 hwstrap; - u32 val; - - val = mt753x_reg_read(gsw, TOP_SIG_SR); - if (val & PAD_DUAL_SGMII_EN) - return; - - hwstrap = mt753x_reg_read(gsw, HWSTRAP); - - switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) { - case XTAL_25MHZ: - /* Step 1 : Disable MT7531 COREPLL */ - val = mt753x_reg_read(gsw, PLLGP_EN); - val &= ~EN_COREPLL; - mt753x_reg_write(gsw, PLLGP_EN, val); - - /* Step 2: switch to XTAL output */ - val = mt753x_reg_read(gsw, PLLGP_EN); - val |= SW_CLKSW; - mt753x_reg_write(gsw, PLLGP_EN, val); - - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_EN; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - /* Step 3: disable PLLGP and enable program PLLGP */ - val = mt753x_reg_read(gsw, PLLGP_EN); - val |= SW_PLLGP; - mt753x_reg_write(gsw, PLLGP_EN, val); - - /* Step 4: program COREPLL output frequency to 500MHz */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_POSDIV_M; - val |= 2 << RG_COREPLL_POSDIV_S; - mt753x_reg_write(gsw, PLLGP_CR0, val); - usleep_range(25, 35); - - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_M; - val |= 0x140000 << RG_COREPLL_SDM_PCW_S; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - /* Set feedback divide ratio update signal to high */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val |= RG_COREPLL_SDM_PCW_CHG; - mt753x_reg_write(gsw, PLLGP_CR0, val); - /* Wait for at least 16 XTAL clocks */ - usleep_range(10, 20); - - /* Step 5: set feedback divide ratio update signal to low */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_CHG; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - /* Enable 325M clock for SGMII */ - mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000); - - /* Enable 250SSC clock for RGMII */ - mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000); - - /* Step 6: Enable MT7531 PLL */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val |= RG_COREPLL_EN; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - val = mt753x_reg_read(gsw, PLLGP_EN); - val |= EN_COREPLL; - mt753x_reg_write(gsw, PLLGP_EN, val); - usleep_range(25, 35); - - break; - case XTAL_40MHZ: - /* Step 1 : Disable MT7531 COREPLL */ - val = mt753x_reg_read(gsw, PLLGP_EN); - val &= ~EN_COREPLL; - mt753x_reg_write(gsw, PLLGP_EN, val); - - /* Step 2: switch to XTAL output */ - val = mt753x_reg_read(gsw, PLLGP_EN); - val |= SW_CLKSW; - mt753x_reg_write(gsw, PLLGP_EN, val); - - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_EN; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - /* Step 3: disable PLLGP and enable program PLLGP */ - val = mt753x_reg_read(gsw, PLLGP_EN); - val |= SW_PLLGP; - mt753x_reg_write(gsw, PLLGP_EN, val); - - /* Step 4: program COREPLL output frequency to 500MHz */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_POSDIV_M; - val |= 2 << RG_COREPLL_POSDIV_S; - mt753x_reg_write(gsw, PLLGP_CR0, val); - usleep_range(25, 35); - - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_M; - val |= 0x190000 << RG_COREPLL_SDM_PCW_S; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - /* Set feedback divide ratio update signal to high */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val |= RG_COREPLL_SDM_PCW_CHG; - mt753x_reg_write(gsw, PLLGP_CR0, val); - /* Wait for at least 16 XTAL clocks */ - usleep_range(10, 20); - - /* Step 5: set feedback divide ratio update signal to low */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val &= ~RG_COREPLL_SDM_PCW_CHG; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - /* Enable 325M clock for SGMII */ - mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000); - - /* Enable 250SSC clock for RGMII */ - mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000); - - /* Step 6: Enable MT7531 PLL */ - val = mt753x_reg_read(gsw, PLLGP_CR0); - val |= RG_COREPLL_EN; - mt753x_reg_write(gsw, PLLGP_CR0, val); - - val = mt753x_reg_read(gsw, PLLGP_EN); - val |= EN_COREPLL; - mt753x_reg_write(gsw, PLLGP_EN, val); - usleep_range(25, 35); - break; - } -} - -static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw) -{ - return 0; -} - -static int mt7531_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev) -{ - u32 rev, topsig; - - rev = mt753x_reg_read(gsw, CHIP_REV); - - if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7531) { - if (crev) { - topsig = mt753x_reg_read(gsw, TOP_SIG_SR); - - crev->rev = rev & CHIP_REV_M; - crev->name = topsig & PAD_DUAL_SGMII_EN ? - "MT7531AE" : "MT7531BE"; - } - - return 0; - } - - return -ENODEV; -} - -static void pinmux_set_mux_7531(struct gsw_mt753x *gsw, u32 pin, u32 mode) -{ - u32 val; - - val = mt753x_reg_read(gsw, GPIO_MODE_REGS(pin)); - val &= ~(0xf << (pin & 7) * GPIO_MODE_S); - val |= mode << (pin & 7) * GPIO_MODE_S; - mt753x_reg_write(gsw, GPIO_MODE_REGS(pin), val); -} - -static int mt7531_set_gpio_pinmux(struct gsw_mt753x *gsw) -{ - u32 group = 0; - struct device_node *np = gsw->dev->of_node; - - /* Set GPIO 0 interrupt mode */ - pinmux_set_mux_7531(gsw, gpio_int_pins[0], gpio_int_funcs[0]); - - of_property_read_u32(np, "mediatek,mdio_master_pinmux", &group); - - /* group = 0: do nothing, 1: 1st group (AE), 2: 2nd group (BE) */ - if (group > 0 && group <= 2) { - group--; - pinmux_set_mux_7531(gsw, gpio_mdc_pins[group], - gpio_mdc_funcs[group]); - pinmux_set_mux_7531(gsw, gpio_mdio_pins[group], - gpio_mdio_funcs[group]); - } - - return 0; -} - -static void mt7531_phy_pll_setup(struct gsw_mt753x *gsw) -{ - u32 hwstrap; - u32 val; - - hwstrap = mt753x_reg_read(gsw, HWSTRAP); - - switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) { - case XTAL_25MHZ: - /* disable pll auto calibration */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608); - - /* change pll sel */ - val = gsw->mmd_read(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_403); - val &= ~(PHY_PLL_M); - val |= PHY_PLL_SEL(3); - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); - - /* set divider ratio */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_10A, 0x1009); - - /* set divider ratio */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0x7c6); - - /* capacitance and resistance adjustment */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_10C, 0xa8be); - - break; - case XTAL_40MHZ: - /* disable pll auto calibration */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608); - - /* change pll sel */ - val = gsw->mmd_read(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_403); - val &= ~(PHY_PLL_M); - val |= PHY_PLL_SEL(3); - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); - - /* set divider ratio */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_10A, 0x1018); - - /* set divider ratio */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0xc676); - - /* capacitance and resistance adjustment */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_10C, 0xd8be); - break; - } - - /* power down pll. additional delay is not required via mdio access */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x10); - - /* power up pll */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x14); -} - -static void mt7531_phy_setting(struct gsw_mt753x *gsw) -{ - int i; - u32 val; - - /* Adjust DAC TX Delay */ - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_44, 0xc0); - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - /* Disable EEE */ - gsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0); - - /* Enable HW auto downshift */ - gsw->mii_write(gsw, i, 0x1f, 0x1); - val = gsw->mii_read(gsw, i, PHY_EXT_REG_14); - val |= PHY_EN_DOWN_SHFIT; - gsw->mii_write(gsw, i, PHY_EXT_REG_14, val); - - /* Increase SlvDPSready time */ - gsw->mii_write(gsw, i, 0x1f, 0x52b5); - gsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae); - gsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f); - gsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae); - gsw->mii_write(gsw, i, 0x1f, 0); - - /* Adjust 100_mse_threshold */ - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff); - - /* Disable mcc */ - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300); - - /* PHY link down power saving enable */ - val = gsw->mii_read(gsw, i, PHY_EXT_REG_17); - val |= PHY_LINKDOWN_POWER_SAVING_EN; - gsw->mii_write(gsw, i, PHY_EXT_REG_17, val); - - val = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6); - val &= ~PHY_POWER_SAVING_M; - val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6, val); - - /* Set TX Pair delay selection */ - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_13, 0x404); - gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_14, 0x404); - } -} - -static void mt7531_adjust_line_driving(struct gsw_mt753x *gsw, u32 port) -{ - /* For ADC timing margin window for LDO calibration */ - gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_LDO_CONTROL_2, 0x2222); - - /* Adjust AD sample timing */ - gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_CONTROL_3, 0x4444); - - /* Adjust Line driver current for different mode */ - gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_271, 0x2ca5); - - /* Adjust Line driver current for different mode */ - gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_272, 0xc6b); - - /* Adjust Line driver amplitude for 10BT */ - gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000); - - /* Adjust RX Echo path filter */ - gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2); - - /* Adjust RX HVGA bias current */ - gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333); - - /* Adjust TX class AB driver 1 */ - gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_268, 0x388); - - /* Adjust TX class AB driver 2 */ - gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_269, 0x4448); -} - -static void mt7531_eee_setting(struct gsw_mt753x *gsw, u32 port) -{ - u32 tr_reg_control; - u32 val; - - /* Disable generate signal to clear the scramble_lock when lpi mode */ - val = gsw->mmd_read(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189); - val &= ~DESCRAMBLER_CLEAR_EN; - gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189, val); - - /* roll back CR*/ - gsw->mii_write(gsw, port, 0x1f, 0x52b5); - gsw->mmd_write(gsw, port, 0x1e, 0x2d1, 0); - tr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) | - (DSP_NOD_ADDR << 7) | (0x8 << 1); - gsw->mii_write(gsw, port, 17, 0x1b); - gsw->mii_write(gsw, port, 18, 0); - gsw->mii_write(gsw, port, 16, tr_reg_control); - tr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) | - (DSP_NOD_ADDR << 7) | (0xf << 1); - gsw->mii_write(gsw, port, 17, 0); - gsw->mii_write(gsw, port, 18, 0); - gsw->mii_write(gsw, port, 16, tr_reg_control); - - tr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) | - (DSP_NOD_ADDR << 7) | (0x10 << 1); - gsw->mii_write(gsw, port, 17, 0x500); - gsw->mii_write(gsw, port, 18, 0); - gsw->mii_write(gsw, port, 16, tr_reg_control); - gsw->mii_write(gsw, port, 0x1f, 0); -} - -static int mt7531_sw_init(struct gsw_mt753x *gsw) -{ - int i; - u32 val; - - gsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK; - - gsw->mii_read = mt753x_mii_read; - gsw->mii_write = mt753x_mii_write; - gsw->mmd_read = mt753x_mmd_read; - gsw->mmd_write = mt753x_mmd_write; - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - val = gsw->mii_read(gsw, i, MII_BMCR); - val |= BMCR_ISOLATE; - gsw->mii_write(gsw, i, MII_BMCR, val); - } - - /* Force MAC link down before reset */ - mt753x_reg_write(gsw, PMCR(5), FORCE_MODE_LNK); - mt753x_reg_write(gsw, PMCR(6), FORCE_MODE_LNK); - - /* Switch soft reset */ - mt753x_reg_write(gsw, SYS_CTRL, SW_SYS_RST | SW_REG_RST); - usleep_range(10, 20); - - /* Enable MDC input Schmitt Trigger */ - val = mt753x_reg_read(gsw, SMT0_IOLB); - mt753x_reg_write(gsw, SMT0_IOLB, val | SMT_IOLB_5_SMI_MDC_EN); - - /* Set 7531 gpio pinmux */ - mt7531_set_gpio_pinmux(gsw); - - /* Global mac control settings */ - mt753x_reg_write(gsw, GMACCR, - (15 << MTCC_LMT_S) | (11 << MAX_RX_JUMBO_S) | - RX_PKT_LEN_MAX_JUMBO); - - mt7531_core_pll_setup(gsw); - mt7531_mac_port_setup(gsw, 5, &gsw->port5_cfg); - mt7531_mac_port_setup(gsw, 6, &gsw->port6_cfg); - - return 0; -} - -static int mt7531_sw_post_init(struct gsw_mt753x *gsw) -{ - int i; - u32 val; - - mt7531_phy_pll_setup(gsw); - - /* Internal PHYs are disabled by default. SW should enable them. - * Note that this may already be enabled in bootloader stage. - */ - val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); - val |= PHY_EN_BYPASS_MODE; - val &= ~POWER_ON_OFF; - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); - - mt7531_phy_setting(gsw); - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - val = gsw->mii_read(gsw, i, MII_BMCR); - val &= ~BMCR_ISOLATE; - gsw->mii_write(gsw, i, MII_BMCR, val); - } - - for (i = 0; i < MT753X_NUM_PHYS; i++) - mt7531_adjust_line_driving(gsw, i); - - for (i = 0; i < MT753X_NUM_PHYS; i++) - mt7531_eee_setting(gsw, i); - - val = mt753x_reg_read(gsw, CHIP_REV); - val &= CHIP_REV_M; - if (val == CHIP_REV_E1) { - mt7531_internal_phy_calibration(gsw); - } else { - val = mt753x_reg_read(gsw, GBE_EFUSE); - if (val & GBE_SEL_EFUSE_EN) { - val = gsw->mmd_read(gsw, 0, PHY_DEV1F, - PHY_DEV1F_REG_403); - val &= ~GBE_EFUSE_SETTING; - gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, - val); - } else { - mt7531_internal_phy_calibration(gsw); - } - } - - return 0; -} - -struct mt753x_sw_id mt7531_id = { - .model = MT7531, - .detect = mt7531_sw_detect, - .init = mt7531_sw_init, - .post_init = mt7531_sw_post_init -}; - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Zhanguo Ju "); -MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch"); diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.h deleted file mode 100644 index 52c8a49fd..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - */ - -#ifndef _MT7531_H_ -#define _MT7531_H_ - -#include "mt753x.h" - -extern struct mt753x_sw_id mt7531_id; - -#endif /* _MT7531_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x.h deleted file mode 100644 index 27cd6f4f1..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#ifndef _MT753X_H_ -#define _MT753X_H_ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SWCONFIG -#include -#endif - -#include "mt753x_vlan.h" - -#define MT753X_DFL_CPU_PORT 6 -#define MT753X_NUM_PHYS 5 - -#define MT753X_DFL_SMI_ADDR 0x1f -#define MT753X_SMI_ADDR_MASK 0x1f - -struct gsw_mt753x; - -enum mt753x_model { - MT7530 = 0x7530, - MT7531 = 0x7531 -}; - -struct mt753x_port_cfg { - struct device_node *np; - phy_interface_t phy_mode; - u32 enabled: 1; - u32 force_link: 1; - u32 speed: 2; - u32 duplex: 1; -}; - -struct mt753x_phy { - struct gsw_mt753x *gsw; - struct net_device netdev; - struct phy_device *phydev; -}; - -struct gsw_mt753x { - u32 id; - - struct device *dev; - struct mii_bus *host_bus; - struct mii_bus *gphy_bus; - struct mutex mii_lock; /* MII access lock */ - u32 smi_addr; - u32 phy_base; - int direct_phy_access; - - enum mt753x_model model; - const char *name; - - struct mt753x_port_cfg port5_cfg; - struct mt753x_port_cfg port6_cfg; - - int phy_status_poll; - struct mt753x_phy phys[MT753X_NUM_PHYS]; - - int phy_link_sts; - - int irq; - int reset_pin; - struct work_struct irq_worker; - -#ifdef CONFIG_SWCONFIG - struct switch_dev swdev; - u32 cpu_port; -#endif - - int global_vlan_enable; - struct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS]; - struct mt753x_port_entry port_entries[MT753X_NUM_PORTS]; - - int (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg); - void (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val); - - int (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg); - void (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, - u16 val); - - struct list_head list; -}; - -struct chip_rev { - const char *name; - u32 rev; -}; - -struct mt753x_sw_id { - enum mt753x_model model; - int (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev); - int (*init)(struct gsw_mt753x *gsw); - int (*post_init)(struct gsw_mt753x *gsw); -}; - -extern struct list_head mt753x_devs; - -struct gsw_mt753x *mt753x_get_gsw(u32 id); -struct gsw_mt753x *mt753x_get_first_gsw(void); -void mt753x_put_gsw(void); -void mt753x_lock_gsw(void); - -u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg); -void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val); - -int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg); -void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val); - -int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg); -void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, - u16 val); - -int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg); -void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, - u16 val); - -void mt753x_irq_worker(struct work_struct *work); -void mt753x_irq_enable(struct gsw_mt753x *gsw); - -/* MDIO Indirect Access Registers */ -#define MII_MMD_ACC_CTL_REG 0x0d -#define MMD_CMD_S 14 -#define MMD_CMD_M 0xc000 -#define MMD_DEVAD_S 0 -#define MMD_DEVAD_M 0x1f - -/* MMD_CMD: MMD commands */ -#define MMD_ADDR 0 -#define MMD_DATA 1 - -#define MII_MMD_ADDR_DATA_REG 0x0e - -/* Procedure of MT753x Internal Register Access - * - * 1. Internal Register Address - * - * The MT753x has a 16-bit register address and each register is 32-bit. - * This means the lowest two bits are not used as the register address is - * 4-byte aligned. - * - * Rest of the valid bits are divided into two parts: - * Bit 15..6 is the Page address - * Bit 5..2 is the low address - * - * ------------------------------------------------------------------- - * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | - * |----------------------------------------|---------------|--------| - * | Page Address | Address | Unused | - * ------------------------------------------------------------------- - * - * 2. MDIO access timing - * - * The MT753x uses the following MDIO timing for a single register read - * - * Phase 1: Write Page Address - * ------------------------------------------------------------------- - * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | RSVD | PAGE_ADDR | - * ------------------------------------------------------------------- - * | 01 | 01 | 11111 | 1 | 1111 | xx | 00000 | REG_ADDR[15..6] | - * ------------------------------------------------------------------- - * - * Phase 2: Write low Address & Read low word - * ------------------------------------------------------------------- - * | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA | - * ------------------------------------------------------------------- - * | 01 | 10 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] | - * ------------------------------------------------------------------- - * - * Phase 3: Read high word - * ------------------------------------------------------------------- - * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA | - * ------------------------------------------------------------------- - * | 01 | 10 | 11111 | 1 | 0000 | xx | DATA[31..16] | - * ------------------------------------------------------------------- - * - * The MT753x uses the following MDIO timing for a single register write - * - * Phase 1: Write Page Address (The same as read) - * - * Phase 2: Write low Address and low word - * ------------------------------------------------------------------- - * | ST | OP | PHY_ADDR | TYPE | LOW_ADDR | TA | DATA | - * ------------------------------------------------------------------- - * | 01 | 01 | 11111 | 0 | REG_ADDR[5..2] | xx | DATA[15..0] | - * ------------------------------------------------------------------- - * - * Phase 3: write high word - * ------------------------------------------------------------------- - * | ST | OP | PHY_ADDR | TYPE | RSVD | TA | DATA | - * ------------------------------------------------------------------- - * | 01 | 01 | 11111 | 1 | 0000 | xx | DATA[31..16] | - * ------------------------------------------------------------------- - * - */ - -/* Internal Register Address fields */ -#define MT753X_REG_PAGE_ADDR_S 6 -#define MT753X_REG_PAGE_ADDR_M 0xffc0 -#define MT753X_REG_ADDR_S 2 -#define MT753X_REG_ADDR_M 0x3c -#endif /* _MT753X_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_common.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_common.c deleted file mode 100644 index 4015ddf12..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_common.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#include -#include - -#include "mt753x.h" -#include "mt753x_regs.h" - -void mt753x_irq_enable(struct gsw_mt753x *gsw) -{ - u32 val; - int i; - - /* Record initial PHY link status */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - val = gsw->mii_read(gsw, i, MII_BMSR); - if (val & BMSR_LSTATUS) - gsw->phy_link_sts |= BIT(i); - } - - val = BIT(MT753X_NUM_PHYS) - 1; - - mt753x_reg_write(gsw, SYS_INT_EN, val); -} - -static void display_port_link_status(struct gsw_mt753x *gsw, u32 port) -{ - u32 pmsr, speed_bits; - const char *speed; - - pmsr = mt753x_reg_read(gsw, PMSR(port)); - - speed_bits = (pmsr & MAC_SPD_STS_M) >> MAC_SPD_STS_S; - - switch (speed_bits) { - case MAC_SPD_10: - speed = "10Mbps"; - break; - case MAC_SPD_100: - speed = "100Mbps"; - break; - case MAC_SPD_1000: - speed = "1Gbps"; - break; - case MAC_SPD_2500: - speed = "2.5Gbps"; - break; - } - - if (pmsr & MAC_LNK_STS) { - dev_info(gsw->dev, "Port %d Link is Up - %s/%s\n", - port, speed, (pmsr & MAC_DPX_STS) ? "Full" : "Half"); - } else { - dev_info(gsw->dev, "Port %d Link is Down\n", port); - } -} - -void mt753x_irq_worker(struct work_struct *work) -{ - struct gsw_mt753x *gsw; - u32 sts, physts, laststs; - int i; - - gsw = container_of(work, struct gsw_mt753x, irq_worker); - - sts = mt753x_reg_read(gsw, SYS_INT_STS); - - /* Check for changed PHY link status */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - if (!(sts & PHY_LC_INT(i))) - continue; - - laststs = gsw->phy_link_sts & BIT(i); - physts = !!(gsw->mii_read(gsw, i, MII_BMSR) & BMSR_LSTATUS); - physts <<= i; - - if (physts ^ laststs) { - gsw->phy_link_sts ^= BIT(i); - display_port_link_status(gsw, i); - } - } - - mt753x_reg_write(gsw, SYS_INT_STS, sts); - - enable_irq(gsw->irq); -} diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_mdio.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_mdio.c deleted file mode 100644 index 3e2e6d68a..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_mdio.c +++ /dev/null @@ -1,597 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mt753x.h" -#include "mt753x_swconfig.h" -#include "mt753x_regs.h" -#include "mt753x_nl.h" -#include "mt7530.h" -#include "mt7531.h" - -static u32 mt753x_id; -struct list_head mt753x_devs; -static DEFINE_MUTEX(mt753x_devs_lock); - -static struct mt753x_sw_id *mt753x_sw_ids[] = { - &mt7530_id, - &mt7531_id, -}; - -u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg) -{ - u32 high, low; - - mutex_lock(&gsw->host_bus->mdio_lock); - - gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f, - (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S); - - low = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, - (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S); - - high = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10); - - mutex_unlock(&gsw->host_bus->mdio_lock); - - return (high << 16) | (low & 0xffff); -} - -void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val) -{ - mutex_lock(&gsw->host_bus->mdio_lock); - - gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f, - (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S); - - gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, - (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff); - - gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16); - - mutex_unlock(&gsw->host_bus->mdio_lock); -} - -/* Indirect MDIO clause 22/45 access */ -static int mt753x_mii_rw(struct gsw_mt753x *gsw, int phy, int reg, u16 data, - u32 cmd, u32 st) -{ - ktime_t timeout; - u32 val, timeout_us; - int ret = 0; - - timeout_us = 100000; - timeout = ktime_add_us(ktime_get(), timeout_us); - while (1) { - val = mt753x_reg_read(gsw, PHY_IAC); - - if ((val & PHY_ACS_ST) == 0) - break; - - if (ktime_compare(ktime_get(), timeout) > 0) - return -ETIMEDOUT; - } - - val = (st << MDIO_ST_S) | - ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | - ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | - ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); - - if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) - val |= data & MDIO_RW_DATA_M; - - mt753x_reg_write(gsw, PHY_IAC, val | PHY_ACS_ST); - - timeout_us = 100000; - timeout = ktime_add_us(ktime_get(), timeout_us); - while (1) { - val = mt753x_reg_read(gsw, PHY_IAC); - - if ((val & PHY_ACS_ST) == 0) - break; - - if (ktime_compare(ktime_get(), timeout) > 0) - return -ETIMEDOUT; - } - - if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { - val = mt753x_reg_read(gsw, PHY_IAC); - ret = val & MDIO_RW_DATA_M; - } - - return ret; -} - -int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg) -{ - int val; - - if (phy < MT753X_NUM_PHYS) - phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->mii_lock); - val = mt753x_mii_rw(gsw, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); - mutex_unlock(&gsw->mii_lock); - - return val; -} - -void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val) -{ - if (phy < MT753X_NUM_PHYS) - phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->mii_lock); - mt753x_mii_rw(gsw, phy, reg, val, MDIO_CMD_WRITE, MDIO_ST_C22); - mutex_unlock(&gsw->mii_lock); -} - -int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg) -{ - int val; - - if (addr < MT753X_NUM_PHYS) - addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->mii_lock); - mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); - val = mt753x_mii_rw(gsw, addr, devad, 0, MDIO_CMD_READ_C45, - MDIO_ST_C45); - mutex_unlock(&gsw->mii_lock); - - return val; -} - -void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, - u16 val) -{ - if (addr < MT753X_NUM_PHYS) - addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->mii_lock); - mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); - mt753x_mii_rw(gsw, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45); - mutex_unlock(&gsw->mii_lock); -} - -int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg) -{ - u16 val; - - if (addr < MT753X_NUM_PHYS) - addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->mii_lock); - - mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), - MDIO_CMD_WRITE, MDIO_ST_C22); - - mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg, - MDIO_CMD_WRITE, MDIO_ST_C22); - - mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), - MDIO_CMD_WRITE, MDIO_ST_C22); - - val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0, - MDIO_CMD_READ, MDIO_ST_C22); - - mutex_unlock(&gsw->mii_lock); - - return val; -} - -void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, - u16 val) -{ - if (addr < MT753X_NUM_PHYS) - addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; - - mutex_lock(&gsw->mii_lock); - - mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), - MDIO_CMD_WRITE, MDIO_ST_C22); - - mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg, - MDIO_CMD_WRITE, MDIO_ST_C22); - - mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), - MDIO_CMD_WRITE, MDIO_ST_C22); - - mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val, - MDIO_CMD_WRITE, MDIO_ST_C22); - - mutex_unlock(&gsw->mii_lock); -} - -static inline int mt753x_get_duplex(const struct device_node *np) -{ - return of_property_read_bool(np, "full-duplex"); -} - -static void mt753x_load_port_cfg(struct gsw_mt753x *gsw) -{ - struct device_node *port_np; - struct device_node *fixed_link_node; - struct mt753x_port_cfg *port_cfg; - u32 port; - - for_each_child_of_node(gsw->dev->of_node, port_np) { - if (!of_device_is_compatible(port_np, "mediatek,mt753x-port")) - continue; - - if (!of_device_is_available(port_np)) - continue; - - if (of_property_read_u32(port_np, "reg", &port)) - continue; - - switch (port) { - case 5: - port_cfg = &gsw->port5_cfg; - break; - case 6: - port_cfg = &gsw->port6_cfg; - break; - default: - continue; - } - - if (port_cfg->enabled) { - dev_info(gsw->dev, "duplicated node for port%d\n", - port_cfg->phy_mode); - continue; - } - - port_cfg->np = port_np; - - if (of_get_phy_mode(port_np, &port_cfg->phy_mode) < 0) { - dev_info(gsw->dev, "incorrect phy-mode %d\n", port); - continue; - } - - fixed_link_node = of_get_child_by_name(port_np, "fixed-link"); - if (fixed_link_node) { - u32 speed; - - port_cfg->force_link = 1; - port_cfg->duplex = mt753x_get_duplex(fixed_link_node); - - if (of_property_read_u32(fixed_link_node, "speed", - &speed)) { - speed = 0; - continue; - } - - of_node_put(fixed_link_node); - - switch (speed) { - case 10: - port_cfg->speed = MAC_SPD_10; - break; - case 100: - port_cfg->speed = MAC_SPD_100; - break; - case 1000: - port_cfg->speed = MAC_SPD_1000; - break; - case 2500: - port_cfg->speed = MAC_SPD_2500; - break; - default: - dev_info(gsw->dev, "incorrect speed %d\n", - speed); - continue; - } - } - - port_cfg->enabled = 1; - } -} - -static void mt753x_add_gsw(struct gsw_mt753x *gsw) -{ - mutex_lock(&mt753x_devs_lock); - gsw->id = mt753x_id++; - INIT_LIST_HEAD(&gsw->list); - list_add_tail(&gsw->list, &mt753x_devs); - mutex_unlock(&mt753x_devs_lock); -} - -static void mt753x_remove_gsw(struct gsw_mt753x *gsw) -{ - mutex_lock(&mt753x_devs_lock); - list_del(&gsw->list); - mutex_unlock(&mt753x_devs_lock); -} - - -struct gsw_mt753x *mt753x_get_gsw(u32 id) -{ - struct gsw_mt753x *dev; - - mutex_lock(&mt753x_devs_lock); - - list_for_each_entry(dev, &mt753x_devs, list) { - if (dev->id == id) - return dev; - } - - mutex_unlock(&mt753x_devs_lock); - - return NULL; -} - -struct gsw_mt753x *mt753x_get_first_gsw(void) -{ - struct gsw_mt753x *dev; - - mutex_lock(&mt753x_devs_lock); - - list_for_each_entry(dev, &mt753x_devs, list) - return dev; - - mutex_unlock(&mt753x_devs_lock); - - return NULL; -} - -void mt753x_put_gsw(void) -{ - mutex_unlock(&mt753x_devs_lock); -} - -void mt753x_lock_gsw(void) -{ - mutex_lock(&mt753x_devs_lock); -} - -static int mt753x_hw_reset(struct gsw_mt753x *gsw) -{ - struct device_node *np = gsw->dev->of_node; - struct reset_control *rstc; - int mcm; - int ret = -EINVAL; - - mcm = of_property_read_bool(np, "mediatek,mcm"); - if (mcm) { - rstc = devm_reset_control_get(gsw->dev, "mcm"); - ret = IS_ERR(rstc); - if (IS_ERR(rstc)) { - dev_err(gsw->dev, "Missing reset ctrl of switch\n"); - return ret; - } - - reset_control_assert(rstc); - msleep(30); - reset_control_deassert(rstc); - - gsw->reset_pin = -1; - return 0; - } - - gsw->reset_pin = of_get_named_gpio(np, "reset-gpios", 0); - if (gsw->reset_pin < 0) { - dev_err(gsw->dev, "Missing reset pin of switch\n"); - return ret; - } - - ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mt753x-reset"); - if (ret) { - dev_info(gsw->dev, "Failed to request gpio %d\n", - gsw->reset_pin); - return ret; - } - - gpio_direction_output(gsw->reset_pin, 0); - msleep(30); - gpio_set_value(gsw->reset_pin, 1); - msleep(500); - - return 0; -} - -static irqreturn_t mt753x_irq_handler(int irq, void *dev) -{ - struct gsw_mt753x *gsw = dev; - - disable_irq_nosync(gsw->irq); - - schedule_work(&gsw->irq_worker); - - return IRQ_HANDLED; -} - -static int mt753x_probe(struct platform_device *pdev) -{ - struct gsw_mt753x *gsw; - struct mt753x_sw_id *sw; - struct device_node *np = pdev->dev.of_node; - struct device_node *mdio; - struct mii_bus *mdio_bus; - int ret = -EINVAL; - struct chip_rev rev; - struct mt753x_mapping *map; - int i; - - mdio = of_parse_phandle(np, "mediatek,mdio", 0); - if (!mdio) - return -EINVAL; - - mdio_bus = of_mdio_find_bus(mdio); - if (!mdio_bus) - return -EPROBE_DEFER; - - gsw = devm_kzalloc(&pdev->dev, sizeof(struct gsw_mt753x), GFP_KERNEL); - if (!gsw) - return -ENOMEM; - - gsw->host_bus = mdio_bus; - gsw->dev = &pdev->dev; - mutex_init(&gsw->mii_lock); - - /* Switch hard reset */ - if (mt753x_hw_reset(gsw)) - goto fail; - - /* Fetch the SMI address dirst */ - if (of_property_read_u32(np, "mediatek,smi-addr", &gsw->smi_addr)) - gsw->smi_addr = MT753X_DFL_SMI_ADDR; - - /* Get LAN/WAN port mapping */ - map = mt753x_find_mapping(np); - if (map) { - mt753x_apply_mapping(gsw, map); - gsw->global_vlan_enable = 1; - dev_info(gsw->dev, "LAN/WAN VLAN setting=%s\n", map->name); - } - - /* Load MAC port configurations */ - mt753x_load_port_cfg(gsw); - - /* Check for valid switch and then initialize */ - for (i = 0; i < ARRAY_SIZE(mt753x_sw_ids); i++) { - if (!mt753x_sw_ids[i]->detect(gsw, &rev)) { - sw = mt753x_sw_ids[i]; - - gsw->name = rev.name; - gsw->model = sw->model; - - dev_info(gsw->dev, "Switch is MediaTek %s rev %d", - gsw->name, rev.rev); - - /* Initialize the switch */ - ret = sw->init(gsw); - if (ret) - goto fail; - - break; - } - } - - if (i >= ARRAY_SIZE(mt753x_sw_ids)) { - dev_err(gsw->dev, "No mt753x switch found\n"); - goto fail; - } - - gsw->irq = platform_get_irq(pdev, 0); - if (gsw->irq >= 0) { - ret = devm_request_irq(gsw->dev, gsw->irq, mt753x_irq_handler, - 0, dev_name(gsw->dev), gsw); - if (ret) { - dev_err(gsw->dev, "Failed to request irq %d\n", - gsw->irq); - goto fail; - } - - INIT_WORK(&gsw->irq_worker, mt753x_irq_worker); - } - - platform_set_drvdata(pdev, gsw); - - gsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node, - "mediatek,phy-poll"); - - mt753x_add_gsw(gsw); - - mt753x_swconfig_init(gsw); - - if (sw->post_init) - sw->post_init(gsw); - - if (gsw->irq >= 0) - mt753x_irq_enable(gsw); - - return 0; - -fail: - devm_kfree(&pdev->dev, gsw); - - return ret; -} - -static int mt753x_remove(struct platform_device *pdev) -{ - struct gsw_mt753x *gsw = platform_get_drvdata(pdev); - - if (gsw->irq >= 0) - cancel_work_sync(&gsw->irq_worker); - - if (gsw->reset_pin >= 0) - devm_gpio_free(&pdev->dev, gsw->reset_pin); - -#ifdef CONFIG_SWCONFIG - mt753x_swconfig_destroy(gsw); -#endif - - mt753x_remove_gsw(gsw); - - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static const struct of_device_id mt753x_ids[] = { - { .compatible = "mediatek,mt753x" }, - { }, -}; - -MODULE_DEVICE_TABLE(of, mt753x_ids); - -static struct platform_driver mt753x_driver = { - .probe = mt753x_probe, - .remove = mt753x_remove, - .driver = { - .name = "mt753x", - .of_match_table = mt753x_ids, - }, -}; - -static int __init mt753x_init(void) -{ - int ret; - - INIT_LIST_HEAD(&mt753x_devs); - ret = platform_driver_register(&mt753x_driver); - - mt753x_nl_init(); - - return ret; -} -module_init(mt753x_init); - -static void __exit mt753x_exit(void) -{ - mt753x_nl_exit(); - - platform_driver_unregister(&mt753x_driver); -} -module_exit(mt753x_exit); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Weijie Gao "); -MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch"); diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.c deleted file mode 100644 index ccde2c920..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.c +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Sirui Zhao - */ - -#include -#include -#include -#include -#include - -#include "mt753x.h" -#include "mt753x_nl.h" - -struct mt753x_nl_cmd_item { - enum mt753x_cmd cmd; - bool require_dev; - int (*process)(struct genl_info *info, struct gsw_mt753x *gsw); - u32 nr_required_attrs; - const enum mt753x_attr *required_attrs; -}; - -static int mt753x_nl_response(struct sk_buff *skb, struct genl_info *info); - -/* -static const struct nla_policy mt753x_nl_cmd_policy[] = { - [MT753X_ATTR_TYPE_MESG] = { .type = NLA_STRING }, - [MT753X_ATTR_TYPE_PHY] = { .type = NLA_S32 }, - [MT753X_ATTR_TYPE_REG] = { .type = NLA_S32 }, - [MT753X_ATTR_TYPE_VAL] = { .type = NLA_S32 }, - [MT753X_ATTR_TYPE_DEV_NAME] = { .type = NLA_S32 }, - [MT753X_ATTR_TYPE_DEV_ID] = { .type = NLA_S32 }, - [MT753X_ATTR_TYPE_DEVAD] = { .type = NLA_S32 }, -}; -*/ - -static const struct genl_ops mt753x_nl_ops[] = { - { - .cmd = MT753X_CMD_REQUEST, - .doit = mt753x_nl_response, -// .policy = mt753x_nl_cmd_policy, - .flags = GENL_ADMIN_PERM, - }, { - .cmd = MT753X_CMD_READ, - .doit = mt753x_nl_response, -// .policy = mt753x_nl_cmd_policy, - .flags = GENL_ADMIN_PERM, - }, { - .cmd = MT753X_CMD_WRITE, - .doit = mt753x_nl_response, -// .policy = mt753x_nl_cmd_policy, - .flags = GENL_ADMIN_PERM, - }, -}; - -static struct genl_family mt753x_nl_family = { - .name = MT753X_GENL_NAME, - .version = MT753X_GENL_VERSION, - .maxattr = MT753X_NR_ATTR_TYPE, - .ops = mt753x_nl_ops, - .n_ops = ARRAY_SIZE(mt753x_nl_ops), -}; - -static int mt753x_nl_list_devs(char *buff, int size) -{ - struct gsw_mt753x *gsw; - int len, total = 0; - char buf[80]; - - memset(buff, 0, size); - - mt753x_lock_gsw(); - - list_for_each_entry(gsw, &mt753x_devs, list) { - len = snprintf(buf, sizeof(buf), - "id: %d, model: %s, node: %s\n", - gsw->id, gsw->name, gsw->dev->of_node->name); - strncat(buff, buf, size - total); - total += len; - } - - mt753x_put_gsw(); - - return total; -} - -static int mt753x_nl_prepare_reply(struct genl_info *info, u8 cmd, - struct sk_buff **skbp) -{ - struct sk_buff *msg; - void *reply; - - if (!info) - return -EINVAL; - - msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); - if (!msg) - return -ENOMEM; - - /* Construct send-back message header */ - reply = genlmsg_put(msg, info->snd_portid, info->snd_seq, - &mt753x_nl_family, 0, cmd); - if (!reply) { - nlmsg_free(msg); - return -EINVAL; - } - - *skbp = msg; - return 0; -} - -static int mt753x_nl_send_reply(struct sk_buff *skb, struct genl_info *info) -{ - struct genlmsghdr *genlhdr = nlmsg_data(nlmsg_hdr(skb)); - void *reply = genlmsg_data(genlhdr); - - /* Finalize a generic netlink message (update message header) */ - genlmsg_end(skb, reply); - - /* reply to a request */ - return genlmsg_reply(skb, info); -} - -static s32 mt753x_nl_get_s32(struct genl_info *info, enum mt753x_attr attr, - s32 defval) -{ - struct nlattr *na; - - na = info->attrs[attr]; - if (na) - return nla_get_s32(na); - - return defval; -} - -static int mt753x_nl_get_u32(struct genl_info *info, enum mt753x_attr attr, - u32 *val) -{ - struct nlattr *na; - - na = info->attrs[attr]; - if (na) { - *val = nla_get_u32(na); - return 0; - } - - return -1; -} - -static struct gsw_mt753x *mt753x_nl_parse_find_gsw(struct genl_info *info) -{ - struct gsw_mt753x *gsw; - struct nlattr *na; - int gsw_id; - - na = info->attrs[MT753X_ATTR_TYPE_DEV_ID]; - if (na) { - gsw_id = nla_get_s32(na); - if (gsw_id >= 0) - gsw = mt753x_get_gsw(gsw_id); - else - gsw = mt753x_get_first_gsw(); - } else { - gsw = mt753x_get_first_gsw(); - } - - return gsw; -} - -static int mt753x_nl_get_swdevs(struct genl_info *info, struct gsw_mt753x *gsw) -{ - struct sk_buff *rep_skb = NULL; - char dev_info[512]; - int ret; - - ret = mt753x_nl_list_devs(dev_info, sizeof(dev_info)); - if (!ret) { - pr_info("No switch registered\n"); - return -EINVAL; - } - - ret = mt753x_nl_prepare_reply(info, MT753X_CMD_REPLY, &rep_skb); - if (ret < 0) - goto err; - - ret = nla_put_string(rep_skb, MT753X_ATTR_TYPE_MESG, dev_info); - if (ret < 0) - goto err; - - return mt753x_nl_send_reply(rep_skb, info); - -err: - if (rep_skb) - nlmsg_free(rep_skb); - - return ret; -} - -static int mt753x_nl_reply_read(struct genl_info *info, struct gsw_mt753x *gsw) -{ - struct sk_buff *rep_skb = NULL; - s32 phy, devad, reg; - int value; - int ret = 0; - - phy = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_PHY, -1); - devad = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_DEVAD, -1); - reg = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_REG, -1); - - if (reg < 0) - goto err; - - ret = mt753x_nl_prepare_reply(info, MT753X_CMD_READ, &rep_skb); - if (ret < 0) - goto err; - - if (phy >= 0) { - if (devad < 0) - value = gsw->mii_read(gsw, phy, reg); - else - value = gsw->mmd_read(gsw, phy, devad, reg); - } else { - value = mt753x_reg_read(gsw, reg); - } - - ret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_REG, reg); - if (ret < 0) - goto err; - - ret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_VAL, value); - if (ret < 0) - goto err; - - return mt753x_nl_send_reply(rep_skb, info); - -err: - if (rep_skb) - nlmsg_free(rep_skb); - - return ret; -} - -static int mt753x_nl_reply_write(struct genl_info *info, struct gsw_mt753x *gsw) -{ - struct sk_buff *rep_skb = NULL; - s32 phy, devad, reg; - u32 value; - int ret = 0; - - phy = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_PHY, -1); - devad = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_DEVAD, -1); - reg = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_REG, -1); - - if (mt753x_nl_get_u32(info, MT753X_ATTR_TYPE_VAL, &value)) - goto err; - - if (reg < 0) - goto err; - - ret = mt753x_nl_prepare_reply(info, MT753X_CMD_WRITE, &rep_skb); - if (ret < 0) - goto err; - - if (phy >= 0) { - if (devad < 0) - gsw->mii_write(gsw, phy, reg, value); - else - gsw->mmd_write(gsw, phy, devad, reg, value); - } else { - mt753x_reg_write(gsw, reg, value); - } - - ret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_REG, reg); - if (ret < 0) - goto err; - - ret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_VAL, value); - if (ret < 0) - goto err; - - return mt753x_nl_send_reply(rep_skb, info); - -err: - if (rep_skb) - nlmsg_free(rep_skb); - - return ret; -} - -static const enum mt753x_attr mt753x_nl_cmd_read_attrs[] = { - MT753X_ATTR_TYPE_REG -}; - -static const enum mt753x_attr mt753x_nl_cmd_write_attrs[] = { - MT753X_ATTR_TYPE_REG, - MT753X_ATTR_TYPE_VAL -}; - -static const struct mt753x_nl_cmd_item mt753x_nl_cmds[] = { - { - .cmd = MT753X_CMD_REQUEST, - .require_dev = false, - .process = mt753x_nl_get_swdevs - }, { - .cmd = MT753X_CMD_READ, - .require_dev = true, - .process = mt753x_nl_reply_read, - .required_attrs = mt753x_nl_cmd_read_attrs, - .nr_required_attrs = ARRAY_SIZE(mt753x_nl_cmd_read_attrs), - }, { - .cmd = MT753X_CMD_WRITE, - .require_dev = true, - .process = mt753x_nl_reply_write, - .required_attrs = mt753x_nl_cmd_write_attrs, - .nr_required_attrs = ARRAY_SIZE(mt753x_nl_cmd_write_attrs), - } -}; - -static int mt753x_nl_response(struct sk_buff *skb, struct genl_info *info) -{ - struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); - const struct mt753x_nl_cmd_item *cmditem = NULL; - struct gsw_mt753x *gsw = NULL; - u32 sat_req_attrs = 0; - int i, ret; - - for (i = 0; i < ARRAY_SIZE(mt753x_nl_cmds); i++) { - if (hdr->cmd == mt753x_nl_cmds[i].cmd) { - cmditem = &mt753x_nl_cmds[i]; - break; - } - } - - if (!cmditem) { - pr_info("mt753x-nl: unknown cmd %u\n", hdr->cmd); - return -EINVAL; - } - - for (i = 0; i < cmditem->nr_required_attrs; i++) { - if (info->attrs[cmditem->required_attrs[i]]) - sat_req_attrs++; - } - - if (sat_req_attrs != cmditem->nr_required_attrs) { - pr_info("mt753x-nl: missing required attr(s) for cmd %u\n", - hdr->cmd); - return -EINVAL; - } - - if (cmditem->require_dev) { - gsw = mt753x_nl_parse_find_gsw(info); - if (!gsw) { - pr_info("mt753x-nl: failed to find switch dev\n"); - return -EINVAL; - } - } - - ret = cmditem->process(info, gsw); - - mt753x_put_gsw(); - - return ret; -} - -int __init mt753x_nl_init(void) -{ - int ret; - - ret = genl_register_family(&mt753x_nl_family); - if (ret) { - pr_info("mt753x-nl: genl_register_family_with_ops failed\n"); - return ret; - } - - return 0; -} - -void __exit mt753x_nl_exit(void) -{ - genl_unregister_family(&mt753x_nl_family); -} diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.h deleted file mode 100644 index 85dc9e791..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Sirui Zhao - */ - -#ifndef _MT753X_NL_H_ -#define _MT753X_NL_H_ - -#define MT753X_GENL_NAME "mt753x" -#define MT753X_GENL_VERSION 0x1 - -enum mt753x_cmd { - MT753X_CMD_UNSPEC = 0, - MT753X_CMD_REQUEST, - MT753X_CMD_REPLY, - MT753X_CMD_READ, - MT753X_CMD_WRITE, - - __MT753X_CMD_MAX, -}; - -enum mt753x_attr { - MT753X_ATTR_TYPE_UNSPEC = 0, - MT753X_ATTR_TYPE_MESG, - MT753X_ATTR_TYPE_PHY, - MT753X_ATTR_TYPE_DEVAD, - MT753X_ATTR_TYPE_REG, - MT753X_ATTR_TYPE_VAL, - MT753X_ATTR_TYPE_DEV_NAME, - MT753X_ATTR_TYPE_DEV_ID, - - __MT753X_ATTR_TYPE_MAX, -}; - -#define MT753X_NR_ATTR_TYPE (__MT753X_ATTR_TYPE_MAX - 1) - -#ifdef __KERNEL__ -int __init mt753x_nl_init(void); -void __exit mt753x_nl_exit(void); -#endif /* __KERNEL__ */ - -#endif /* _MT753X_NL_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_regs.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_regs.h deleted file mode 100644 index 3f23ae200..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_regs.h +++ /dev/null @@ -1,294 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#ifndef _MT753X_REGS_H_ -#define _MT753X_REGS_H_ - -#include - -/* Values of Egress TAG Control */ -#define ETAG_CTRL_UNTAG 0 -#define ETAG_CTRL_TAG 2 -#define ETAG_CTRL_SWAP 1 -#define ETAG_CTRL_STACK 3 - -#define VTCR 0x90 -#define VAWD1 0x94 -#define VAWD2 0x98 - -/* Fields of VTCR */ -#define VTCR_BUSY BIT(31) -#define IDX_INVLD BIT(16) -#define VTCR_FUNC_S 12 -#define VTCR_FUNC_M 0xf000 -#define VTCR_VID_S 0 -#define VTCR_VID_M 0xfff - -/* Values of VTCR_FUNC */ -#define VTCR_READ_VLAN_ENTRY 0 -#define VTCR_WRITE_VLAN_ENTRY 1 -#define VTCR_INVD_VLAN_ENTRY 2 -#define VTCR_ENABLE_VLAN_ENTRY 3 -#define VTCR_READ_ACL_ENTRY 4 -#define VTCR_WRITE_ACL_ENTRY 5 -#define VTCR_READ_TRTCM_TABLE 6 -#define VTCR_WRITE_TRTCM_TABLE 7 -#define VTCR_READ_ACL_MASK_ENTRY 8 -#define VTCR_WRITE_ACL_MASK_ENTRY 9 -#define VTCR_READ_ACL_RULE_ENTRY 10 -#define VTCR_WRITE_ACL_RULE_ENTRY 11 -#define VTCR_READ_ACL_RATE_ENTRY 12 -#define VTCR_WRITE_ACL_RATE_ENTRY 13 - -/* VLAN entry fields */ -/* VAWD1 */ -#define PORT_STAG BIT(31) -#define IVL_MAC BIT(30) -#define EG_CON BIT(29) -#define VTAG_EN BIT(28) -#define COPY_PRI BIT(27) -#define USER_PRI_S 24 -#define USER_PRI_M 0x7000000 -#define PORT_MEM_S 16 -#define PORT_MEM_M 0xff0000 -#define S_TAG1_S 4 -#define S_TAG1_M 0xfff0 -#define FID_S 1 -#define FID_M 0x0e -#define VENTRY_VALID BIT(0) - -/* VAWD2 */ -#define S_TAG2_S 16 -#define S_TAG2_M 0xffff0000 -#define PORT_ETAG_S(p) ((p) * 2) -#define PORT_ETAG_M 0x03 - -#define PORT_CTRL_BASE 0x2000 -#define PORT_CTRL_PORT_OFFSET 0x100 -#define PORT_CTRL_REG(p, r) (PORT_CTRL_BASE + \ - (p) * PORT_CTRL_PORT_OFFSET + (r)) -#define CKGCR(p) PORT_CTRL_REG(p, 0x00) -#define PCR(p) PORT_CTRL_REG(p, 0x04) -#define PIC(p) PORT_CTRL_REG(p, 0x08) -#define PSC(p) PORT_CTRL_REG(p, 0x0c) -#define PVC(p) PORT_CTRL_REG(p, 0x10) -#define PPBV1(p) PORT_CTRL_REG(p, 0x14) -#define PPBV2(p) PORT_CTRL_REG(p, 0x18) -#define BSR(p) PORT_CTRL_REG(p, 0x1c) -#define STAG01 PORT_CTRL_REG(p, 0x20) -#define STAG23 PORT_CTRL_REG(p, 0x24) -#define STAG45 PORT_CTRL_REG(p, 0x28) -#define STAG67 PORT_CTRL_REG(p, 0x2c) - -#define PPBV(p, g) (PPBV1(p) + ((g) / 2) * 4) - -/* Fields of PCR */ -#define MLDV2_EN BIT(30) -#define EG_TAG_S 28 -#define EG_TAG_M 0x30000000 -#define PORT_PRI_S 24 -#define PORT_PRI_M 0x7000000 -#define PORT_MATRIX_S 16 -#define PORT_MATRIX_M 0xff0000 -#define UP2DSCP_EN BIT(12) -#define UP2TAG_EN BIT(11) -#define ACL_EN BIT(10) -#define PORT_TX_MIR BIT(9) -#define PORT_RX_MIR BIT(8) -#define ACL_MIR BIT(7) -#define MIS_PORT_FW_S 4 -#define MIS_PORT_FW_M 0x70 -#define VLAN_MIS BIT(2) -#define PORT_VLAN_S 0 -#define PORT_VLAN_M 0x03 - -/* Values of PORT_VLAN */ -#define PORT_MATRIX_MODE 0 -#define FALLBACK_MODE 1 -#define CHECK_MODE 2 -#define SECURITY_MODE 3 - -/* Fields of PVC */ -#define STAG_VPID_S 16 -#define STAG_VPID_M 0xffff0000 -#define DIS_PVID BIT(15) -#define FORCE_PVID BIT(14) -#define PT_VPM BIT(12) -#define PT_OPTION BIT(11) -#define PVC_EG_TAG_S 8 -#define PVC_EG_TAG_M 0x700 -#define VLAN_ATTR_S 6 -#define VLAN_ATTR_M 0xc0 -#define PVC_PORT_STAG BIT(5) -#define BC_LKYV_EN BIT(4) -#define MC_LKYV_EN BIT(3) -#define UC_LKYV_EN BIT(2) -#define ACC_FRM_S 0 -#define ACC_FRM_M 0x03 - -/* Values of VLAN_ATTR */ -#define VA_USER_PORT 0 -#define VA_STACK_PORT 1 -#define VA_TRANSLATION_PORT 2 -#define VA_TRANSPARENT_PORT 3 - -/* Fields of PPBV */ -#define GRP_PORT_PRI_S(g) (((g) % 2) * 16 + 13) -#define GRP_PORT_PRI_M 0x07 -#define GRP_PORT_VID_S(g) (((g) % 2) * 16) -#define GRP_PORT_VID_M 0xfff - -#define PORT_MAC_CTRL_BASE 0x3000 -#define PORT_MAC_CTRL_PORT_OFFSET 0x100 -#define PORT_MAC_CTRL_REG(p, r) (PORT_MAC_CTRL_BASE + \ - (p) * PORT_MAC_CTRL_PORT_OFFSET + (r)) -#define PMCR(p) PORT_MAC_CTRL_REG(p, 0x00) -#define PMEEECR(p) PORT_MAC_CTRL_REG(p, 0x04) -#define PMSR(p) PORT_MAC_CTRL_REG(p, 0x08) -#define PINT_EN(p) PORT_MAC_CTRL_REG(p, 0x10) -#define PINT_STS(p) PORT_MAC_CTRL_REG(p, 0x14) - -#define GMACCR (PORT_MAC_CTRL_BASE + 0xe0) -#define TXCRC_EN BIT(19) -#define RXCRC_EN BIT(18) -#define PRMBL_LMT_EN BIT(17) -#define MTCC_LMT_S 9 -#define MTCC_LMT_M 0x1e00 -#define MAX_RX_JUMBO_S 2 -#define MAX_RX_JUMBO_M 0x3c -#define MAX_RX_PKT_LEN_S 0 -#define MAX_RX_PKT_LEN_M 0x3 - -/* Values of MAX_RX_PKT_LEN */ -#define RX_PKT_LEN_1518 0 -#define RX_PKT_LEN_1536 1 -#define RX_PKT_LEN_1522 2 -#define RX_PKT_LEN_MAX_JUMBO 3 - -/* Fields of PMCR */ -#define IPG_CFG_S 18 -#define IPG_CFG_M 0xc0000 -#define EXT_PHY BIT(17) -#define MAC_MODE BIT(16) -#define MAC_TX_EN BIT(14) -#define MAC_RX_EN BIT(13) -#define MAC_PRE BIT(11) -#define BKOFF_EN BIT(9) -#define BACKPR_EN BIT(8) -#define FORCE_EEE1G BIT(7) -#define FORCE_EEE1000 BIT(6) -#define FORCE_RX_FC BIT(5) -#define FORCE_TX_FC BIT(4) -#define FORCE_SPD_S 2 -#define FORCE_SPD_M 0x0c -#define FORCE_DPX BIT(1) -#define FORCE_LINK BIT(0) - -/* Fields of PMSR */ -#define EEE1G_STS BIT(7) -#define EEE100_STS BIT(6) -#define RX_FC_STS BIT(5) -#define TX_FC_STS BIT(4) -#define MAC_SPD_STS_S 2 -#define MAC_SPD_STS_M 0x0c -#define MAC_DPX_STS BIT(1) -#define MAC_LNK_STS BIT(0) - -/* Values of MAC_SPD_STS */ -#define MAC_SPD_10 0 -#define MAC_SPD_100 1 -#define MAC_SPD_1000 2 -#define MAC_SPD_2500 3 - -/* Values of IPG_CFG */ -#define IPG_96BIT 0 -#define IPG_96BIT_WITH_SHORT_IPG 1 -#define IPG_64BIT 2 - -#define MIB_COUNTER_BASE 0x4000 -#define MIB_COUNTER_PORT_OFFSET 0x100 -#define MIB_COUNTER_REG(p, r) (MIB_COUNTER_BASE + \ - (p) * MIB_COUNTER_PORT_OFFSET + (r)) -#define STATS_TDPC 0x00 -#define STATS_TCRC 0x04 -#define STATS_TUPC 0x08 -#define STATS_TMPC 0x0C -#define STATS_TBPC 0x10 -#define STATS_TCEC 0x14 -#define STATS_TSCEC 0x18 -#define STATS_TMCEC 0x1C -#define STATS_TDEC 0x20 -#define STATS_TLCEC 0x24 -#define STATS_TXCEC 0x28 -#define STATS_TPPC 0x2C -#define STATS_TL64PC 0x30 -#define STATS_TL65PC 0x34 -#define STATS_TL128PC 0x38 -#define STATS_TL256PC 0x3C -#define STATS_TL512PC 0x40 -#define STATS_TL1024PC 0x44 -#define STATS_TOC 0x48 -#define STATS_RDPC 0x60 -#define STATS_RFPC 0x64 -#define STATS_RUPC 0x68 -#define STATS_RMPC 0x6C -#define STATS_RBPC 0x70 -#define STATS_RAEPC 0x74 -#define STATS_RCEPC 0x78 -#define STATS_RUSPC 0x7C -#define STATS_RFEPC 0x80 -#define STATS_ROSPC 0x84 -#define STATS_RJEPC 0x88 -#define STATS_RPPC 0x8C -#define STATS_RL64PC 0x90 -#define STATS_RL65PC 0x94 -#define STATS_RL128PC 0x98 -#define STATS_RL256PC 0x9C -#define STATS_RL512PC 0xA0 -#define STATS_RL1024PC 0xA4 -#define STATS_ROC 0xA8 -#define STATS_RDPC_CTRL 0xB0 -#define STATS_RDPC_ING 0xB4 -#define STATS_RDPC_ARL 0xB8 - -#define SYS_CTRL 0x7000 -#define SW_PHY_RST BIT(2) -#define SW_SYS_RST BIT(1) -#define SW_REG_RST BIT(0) - -#define SYS_INT_EN 0x7008 -#define SYS_INT_STS 0x700c -#define MAC_PC_INT BIT(16) -#define PHY_INT(p) BIT((p) + 8) -#define PHY_LC_INT(p) BIT(p) - -#define PHY_IAC 0x701c -#define PHY_ACS_ST BIT(31) -#define MDIO_REG_ADDR_S 25 -#define MDIO_REG_ADDR_M 0x3e000000 -#define MDIO_PHY_ADDR_S 20 -#define MDIO_PHY_ADDR_M 0x1f00000 -#define MDIO_CMD_S 18 -#define MDIO_CMD_M 0xc0000 -#define MDIO_ST_S 16 -#define MDIO_ST_M 0x30000 -#define MDIO_RW_DATA_S 0 -#define MDIO_RW_DATA_M 0xffff - -/* MDIO_CMD: MDIO commands */ -#define MDIO_CMD_ADDR 0 -#define MDIO_CMD_WRITE 1 -#define MDIO_CMD_READ 2 -#define MDIO_CMD_READ_C45 3 - -/* MDIO_ST: MDIO start field */ -#define MDIO_ST_C45 0 -#define MDIO_ST_C22 1 - -#define HWSTRAP 0x7800 -#define MHWSTRAP 0x7804 - -#endif /* _MT753X_REGS_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.c deleted file mode 100644 index 342ad576b..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.c +++ /dev/null @@ -1,510 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mt753x.h" -#include "mt753x_swconfig.h" -#include "mt753x_regs.h" - -#define MT753X_PORT_MIB_TXB_ID 18 /* TxByte */ -#define MT753X_PORT_MIB_RXB_ID 37 /* RxByte */ - -#define MIB_DESC(_s, _o, _n) \ - { \ - .size = (_s), \ - .offset = (_o), \ - .name = (_n), \ - } - -struct mt753x_mib_desc { - unsigned int size; - unsigned int offset; - const char *name; -}; - -static const struct mt753x_mib_desc mt753x_mibs[] = { - MIB_DESC(1, STATS_TDPC, "TxDrop"), - MIB_DESC(1, STATS_TCRC, "TxCRC"), - MIB_DESC(1, STATS_TUPC, "TxUni"), - MIB_DESC(1, STATS_TMPC, "TxMulti"), - MIB_DESC(1, STATS_TBPC, "TxBroad"), - MIB_DESC(1, STATS_TCEC, "TxCollision"), - MIB_DESC(1, STATS_TSCEC, "TxSingleCol"), - MIB_DESC(1, STATS_TMCEC, "TxMultiCol"), - MIB_DESC(1, STATS_TDEC, "TxDefer"), - MIB_DESC(1, STATS_TLCEC, "TxLateCol"), - MIB_DESC(1, STATS_TXCEC, "TxExcCol"), - MIB_DESC(1, STATS_TPPC, "TxPause"), - MIB_DESC(1, STATS_TL64PC, "Tx64Byte"), - MIB_DESC(1, STATS_TL65PC, "Tx65Byte"), - MIB_DESC(1, STATS_TL128PC, "Tx128Byte"), - MIB_DESC(1, STATS_TL256PC, "Tx256Byte"), - MIB_DESC(1, STATS_TL512PC, "Tx512Byte"), - MIB_DESC(1, STATS_TL1024PC, "Tx1024Byte"), - MIB_DESC(2, STATS_TOC, "TxByte"), - MIB_DESC(1, STATS_RDPC, "RxDrop"), - MIB_DESC(1, STATS_RFPC, "RxFiltered"), - MIB_DESC(1, STATS_RUPC, "RxUni"), - MIB_DESC(1, STATS_RMPC, "RxMulti"), - MIB_DESC(1, STATS_RBPC, "RxBroad"), - MIB_DESC(1, STATS_RAEPC, "RxAlignErr"), - MIB_DESC(1, STATS_RCEPC, "RxCRC"), - MIB_DESC(1, STATS_RUSPC, "RxUnderSize"), - MIB_DESC(1, STATS_RFEPC, "RxFragment"), - MIB_DESC(1, STATS_ROSPC, "RxOverSize"), - MIB_DESC(1, STATS_RJEPC, "RxJabber"), - MIB_DESC(1, STATS_RPPC, "RxPause"), - MIB_DESC(1, STATS_RL64PC, "Rx64Byte"), - MIB_DESC(1, STATS_RL65PC, "Rx65Byte"), - MIB_DESC(1, STATS_RL128PC, "Rx128Byte"), - MIB_DESC(1, STATS_RL256PC, "Rx256Byte"), - MIB_DESC(1, STATS_RL512PC, "Rx512Byte"), - MIB_DESC(1, STATS_RL1024PC, "Rx1024Byte"), - MIB_DESC(2, STATS_ROC, "RxByte"), - MIB_DESC(1, STATS_RDPC_CTRL, "RxCtrlDrop"), - MIB_DESC(1, STATS_RDPC_ING, "RxIngDrop"), - MIB_DESC(1, STATS_RDPC_ARL, "RxARLDrop") -}; - -enum { - /* Global attributes. */ - MT753X_ATTR_ENABLE_VLAN, -}; - -static int mt753x_get_vlan_enable(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - val->value.i = gsw->global_vlan_enable; - - return 0; -} - -static int mt753x_set_vlan_enable(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - gsw->global_vlan_enable = val->value.i != 0; - - return 0; -} - -static int mt753x_get_port_pvid(struct switch_dev *dev, int port, int *val) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - if (port >= MT753X_NUM_PORTS) - return -EINVAL; - - *val = mt753x_reg_read(gsw, PPBV1(port)); - *val &= GRP_PORT_VID_M; - - return 0; -} - -static int mt753x_set_port_pvid(struct switch_dev *dev, int port, int pvid) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - if (port >= MT753X_NUM_PORTS) - return -EINVAL; - - if (pvid < MT753X_MIN_VID || pvid > MT753X_MAX_VID) - return -EINVAL; - - gsw->port_entries[port].pvid = pvid; - - return 0; -} - -static int mt753x_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - u32 member; - u32 etags; - int i; - - val->len = 0; - - if (val->port_vlan < 0 || val->port_vlan >= MT753X_NUM_VLANS) - return -EINVAL; - - mt753x_vlan_ctrl(gsw, VTCR_READ_VLAN_ENTRY, val->port_vlan); - - member = mt753x_reg_read(gsw, VAWD1); - member &= PORT_MEM_M; - member >>= PORT_MEM_S; - - etags = mt753x_reg_read(gsw, VAWD2); - - for (i = 0; i < MT753X_NUM_PORTS; i++) { - struct switch_port *p; - int etag; - - if (!(member & BIT(i))) - continue; - - p = &val->value.ports[val->len++]; - p->id = i; - - etag = (etags >> PORT_ETAG_S(i)) & PORT_ETAG_M; - - if (etag == ETAG_CTRL_TAG) - p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED); - else if (etag != ETAG_CTRL_UNTAG) - dev_info(gsw->dev, - "vlan egress tag control neither untag nor tag.\n"); - } - - return 0; -} - -static int mt753x_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - u8 member = 0; - u8 etags = 0; - int i; - - if (val->port_vlan < 0 || val->port_vlan >= MT753X_NUM_VLANS || - val->len > MT753X_NUM_PORTS) - return -EINVAL; - - for (i = 0; i < val->len; i++) { - struct switch_port *p = &val->value.ports[i]; - - if (p->id >= MT753X_NUM_PORTS) - return -EINVAL; - - member |= BIT(p->id); - - if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) - etags |= BIT(p->id); - } - - gsw->vlan_entries[val->port_vlan].member = member; - gsw->vlan_entries[val->port_vlan].etags = etags; - - return 0; -} - -static int mt753x_set_vid(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - int vlan; - u16 vid; - - vlan = val->port_vlan; - vid = (u16)val->value.i; - - if (vlan < 0 || vlan >= MT753X_NUM_VLANS) - return -EINVAL; - - if (vid < MT753X_MIN_VID || vid > MT753X_MAX_VID) - return -EINVAL; - - gsw->vlan_entries[vlan].vid = vid; - return 0; -} - -static int mt753x_get_vid(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - val->value.i = val->port_vlan; - return 0; -} - -static int mt753x_get_port_link(struct switch_dev *dev, int port, - struct switch_port_link *link) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - u32 speed, pmsr; - - if (port < 0 || port >= MT753X_NUM_PORTS) - return -EINVAL; - - pmsr = mt753x_reg_read(gsw, PMSR(port)); - - link->link = pmsr & MAC_LNK_STS; - link->duplex = pmsr & MAC_DPX_STS; - speed = (pmsr & MAC_SPD_STS_M) >> MAC_SPD_STS_S; - - switch (speed) { - case MAC_SPD_10: - link->speed = SWITCH_PORT_SPEED_10; - break; - case MAC_SPD_100: - link->speed = SWITCH_PORT_SPEED_100; - break; - case MAC_SPD_1000: - link->speed = SWITCH_PORT_SPEED_1000; - break; - case MAC_SPD_2500: - /* TODO: swconfig has no support for 2500 now */ - link->speed = SWITCH_PORT_SPEED_UNKNOWN; - break; - } - - return 0; -} - -static int mt753x_set_port_link(struct switch_dev *dev, int port, - struct switch_port_link *link) -{ -#ifndef MODULE - if (port >= MT753X_NUM_PHYS) - return -EINVAL; - - return switch_generic_set_link(dev, port, link); -#else - return -ENOTSUPP; -#endif -} - -static u64 get_mib_counter(struct gsw_mt753x *gsw, int i, int port) -{ - unsigned int offset; - u64 lo, hi, hi2; - - offset = mt753x_mibs[i].offset; - - if (mt753x_mibs[i].size == 1) - return mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset)); - - do { - hi = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset + 4)); - lo = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset)); - hi2 = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset + 4)); - } while (hi2 != hi); - - return (hi << 32) | lo; -} - -static int mt753x_get_port_mib(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - static char buf[4096]; - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - int i, len = 0; - - if (val->port_vlan >= MT753X_NUM_PORTS) - return -EINVAL; - - len += snprintf(buf + len, sizeof(buf) - len, - "Port %d MIB counters\n", val->port_vlan); - - for (i = 0; i < ARRAY_SIZE(mt753x_mibs); ++i) { - u64 counter; - - len += snprintf(buf + len, sizeof(buf) - len, - "%-11s: ", mt753x_mibs[i].name); - counter = get_mib_counter(gsw, i, val->port_vlan); - len += snprintf(buf + len, sizeof(buf) - len, "%llu\n", - counter); - } - - val->value.s = buf; - val->len = len; - return 0; -} - -static int mt753x_get_port_stats(struct switch_dev *dev, int port, - struct switch_port_stats *stats) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - if (port < 0 || port >= MT753X_NUM_PORTS) - return -EINVAL; - - stats->tx_bytes = get_mib_counter(gsw, MT753X_PORT_MIB_TXB_ID, port); - stats->rx_bytes = get_mib_counter(gsw, MT753X_PORT_MIB_RXB_ID, port); - - return 0; -} - -static void mt753x_port_isolation(struct gsw_mt753x *gsw) -{ - int i; - - for (i = 0; i < MT753X_NUM_PORTS; i++) - mt753x_reg_write(gsw, PCR(i), - BIT(gsw->cpu_port) << PORT_MATRIX_S); - - mt753x_reg_write(gsw, PCR(gsw->cpu_port), PORT_MATRIX_M); - - for (i = 0; i < MT753X_NUM_PORTS; i++) - mt753x_reg_write(gsw, PVC(i), - (0x8100 << STAG_VPID_S) | - (VA_TRANSPARENT_PORT << VLAN_ATTR_S)); -} - -static int mt753x_apply_config(struct switch_dev *dev) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - if (!gsw->global_vlan_enable) { - mt753x_port_isolation(gsw); - return 0; - } - - mt753x_apply_vlan_config(gsw); - - return 0; -} - -static int mt753x_reset_switch(struct switch_dev *dev) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - int i; - - memset(gsw->port_entries, 0, sizeof(gsw->port_entries)); - memset(gsw->vlan_entries, 0, sizeof(gsw->vlan_entries)); - - /* set default vid of each vlan to the same number of vlan, so the vid - * won't need be set explicitly. - */ - for (i = 0; i < MT753X_NUM_VLANS; i++) - gsw->vlan_entries[i].vid = i; - - return 0; -} - -static int mt753x_phy_read16(struct switch_dev *dev, int addr, u8 reg, - u16 *value) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - *value = gsw->mii_read(gsw, addr, reg); - - return 0; -} - -static int mt753x_phy_write16(struct switch_dev *dev, int addr, u8 reg, - u16 value) -{ - struct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev); - - gsw->mii_write(gsw, addr, reg, value); - - return 0; -} - -static const struct switch_attr mt753x_global[] = { - { - .type = SWITCH_TYPE_INT, - .name = "enable_vlan", - .description = "VLAN mode (1:enabled)", - .max = 1, - .id = MT753X_ATTR_ENABLE_VLAN, - .get = mt753x_get_vlan_enable, - .set = mt753x_set_vlan_enable, - } -}; - -static const struct switch_attr mt753x_port[] = { - { - .type = SWITCH_TYPE_STRING, - .name = "mib", - .description = "Get MIB counters for port", - .get = mt753x_get_port_mib, - .set = NULL, - }, -}; - -static const struct switch_attr mt753x_vlan[] = { - { - .type = SWITCH_TYPE_INT, - .name = "vid", - .description = "VLAN ID (0-4094)", - .set = mt753x_set_vid, - .get = mt753x_get_vid, - .max = 4094, - }, -}; - -static const struct switch_dev_ops mt753x_swdev_ops = { - .attr_global = { - .attr = mt753x_global, - .n_attr = ARRAY_SIZE(mt753x_global), - }, - .attr_port = { - .attr = mt753x_port, - .n_attr = ARRAY_SIZE(mt753x_port), - }, - .attr_vlan = { - .attr = mt753x_vlan, - .n_attr = ARRAY_SIZE(mt753x_vlan), - }, - .get_vlan_ports = mt753x_get_vlan_ports, - .set_vlan_ports = mt753x_set_vlan_ports, - .get_port_pvid = mt753x_get_port_pvid, - .set_port_pvid = mt753x_set_port_pvid, - .get_port_link = mt753x_get_port_link, - .set_port_link = mt753x_set_port_link, - .get_port_stats = mt753x_get_port_stats, - .apply_config = mt753x_apply_config, - .reset_switch = mt753x_reset_switch, - .phy_read16 = mt753x_phy_read16, - .phy_write16 = mt753x_phy_write16, -}; - -int mt753x_swconfig_init(struct gsw_mt753x *gsw) -{ - struct device_node *np = gsw->dev->of_node; - struct switch_dev *swdev; - int ret; - - if (of_property_read_u32(np, "mediatek,cpuport", &gsw->cpu_port)) - gsw->cpu_port = MT753X_DFL_CPU_PORT; - - swdev = &gsw->swdev; - - swdev->name = gsw->name; - swdev->alias = gsw->name; - swdev->cpu_port = gsw->cpu_port; - swdev->ports = MT753X_NUM_PORTS; - swdev->vlans = MT753X_NUM_VLANS; - swdev->ops = &mt753x_swdev_ops; - - ret = register_switch(swdev, NULL); - if (ret) { - dev_notice(gsw->dev, "Failed to register switch %s\n", - swdev->name); - return ret; - } - - mt753x_apply_config(swdev); - - return 0; -} - -void mt753x_swconfig_destroy(struct gsw_mt753x *gsw) -{ - unregister_switch(&gsw->swdev); -} diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.h deleted file mode 100644 index f000364ee..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#ifndef _MT753X_SWCONFIG_H_ -#define _MT753X_SWCONFIG_H_ - -#ifdef CONFIG_SWCONFIG -#include -#include "mt753x.h" - -int mt753x_swconfig_init(struct gsw_mt753x *gsw); -void mt753x_swconfig_destroy(struct gsw_mt753x *gsw); -#else -static inline int mt753x_swconfig_init(struct gsw_mt753x *gsw) -{ - mt753x_apply_vlan_config(gsw); - - return 0; -} - -static inline void mt753x_swconfig_destroy(struct gsw_mt753x *gsw) -{ -} -#endif - -#endif /* _MT753X_SWCONFIG_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.c b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.c deleted file mode 100644 index 4d88eee8d..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018 MediaTek Inc. - */ - -#include "mt753x.h" -#include "mt753x_regs.h" - -struct mt753x_mapping mt753x_def_mapping[] = { - { - .name = "llllw", - .pvids = { 1, 1, 1, 1, 2, 2, 1 }, - .members = { 0, 0x4f, 0x30 }, - .etags = { 0, 0, 0 }, - .vids = { 0, 1, 2 }, - }, { - .name = "wllll", - .pvids = { 2, 1, 1, 1, 1, 2, 1 }, - .members = { 0, 0x5e, 0x21 }, - .etags = { 0, 0, 0 }, - .vids = { 0, 1, 2 }, - }, { - .name = "lwlll", - .pvids = { 1, 2, 1, 1, 1, 2, 1 }, - .members = { 0, 0x5d, 0x22 }, - .etags = { 0, 0, 0 }, - .vids = { 0, 1, 2 }, - }, -}; - -void mt753x_vlan_ctrl(struct gsw_mt753x *gsw, u32 cmd, u32 val) -{ - int i; - - mt753x_reg_write(gsw, VTCR, - VTCR_BUSY | ((cmd << VTCR_FUNC_S) & VTCR_FUNC_M) | - (val & VTCR_VID_M)); - - for (i = 0; i < 300; i++) { - u32 val = mt753x_reg_read(gsw, VTCR); - - if ((val & VTCR_BUSY) == 0) - break; - - usleep_range(1000, 1100); - } - - if (i == 300) - dev_info(gsw->dev, "vtcr timeout\n"); -} - -static void mt753x_write_vlan_entry(struct gsw_mt753x *gsw, int vlan, u16 vid, - u8 ports, u8 etags) -{ - int port; - u32 val; - - /* vlan port membership */ - if (ports) - mt753x_reg_write(gsw, VAWD1, - IVL_MAC | VTAG_EN | VENTRY_VALID | - ((ports << PORT_MEM_S) & PORT_MEM_M)); - else - mt753x_reg_write(gsw, VAWD1, 0); - - /* egress mode */ - val = 0; - for (port = 0; port < MT753X_NUM_PORTS; port++) { - if (etags & BIT(port)) - val |= ETAG_CTRL_TAG << PORT_ETAG_S(port); - else - val |= ETAG_CTRL_UNTAG << PORT_ETAG_S(port); - } - mt753x_reg_write(gsw, VAWD2, val); - - /* write to vlan table */ - mt753x_vlan_ctrl(gsw, VTCR_WRITE_VLAN_ENTRY, vid); -} - -void mt753x_apply_vlan_config(struct gsw_mt753x *gsw) -{ - int i, j; - u8 tag_ports; - u8 untag_ports; - - /* set all ports as security mode */ - for (i = 0; i < MT753X_NUM_PORTS; i++) - mt753x_reg_write(gsw, PCR(i), - PORT_MATRIX_M | SECURITY_MODE); - - /* check if a port is used in tag/untag vlan egress mode */ - tag_ports = 0; - untag_ports = 0; - - for (i = 0; i < MT753X_NUM_VLANS; i++) { - u8 member = gsw->vlan_entries[i].member; - u8 etags = gsw->vlan_entries[i].etags; - - if (!member) - continue; - - for (j = 0; j < MT753X_NUM_PORTS; j++) { - if (!(member & BIT(j))) - continue; - - if (etags & BIT(j)) - tag_ports |= 1u << j; - else - untag_ports |= 1u << j; - } - } - - /* set all untag-only ports as transparent and the rest as user port */ - for (i = 0; i < MT753X_NUM_PORTS; i++) { - u32 pvc_mode = 0x8100 << STAG_VPID_S; - - if (untag_ports & BIT(i) && !(tag_ports & BIT(i))) - pvc_mode = (0x8100 << STAG_VPID_S) | - (VA_TRANSPARENT_PORT << VLAN_ATTR_S); - - mt753x_reg_write(gsw, PVC(i), pvc_mode); - } - - /* first clear the switch vlan table */ - for (i = 0; i < MT753X_NUM_VLANS; i++) - mt753x_write_vlan_entry(gsw, i, i, 0, 0); - - /* now program only vlans with members to avoid - * clobbering remapped entries in later iterations - */ - for (i = 0; i < MT753X_NUM_VLANS; i++) { - u16 vid = gsw->vlan_entries[i].vid; - u8 member = gsw->vlan_entries[i].member; - u8 etags = gsw->vlan_entries[i].etags; - - if (member) - mt753x_write_vlan_entry(gsw, i, vid, member, etags); - } - - /* Port Default PVID */ - for (i = 0; i < MT753X_NUM_PORTS; i++) { - int vlan = gsw->port_entries[i].pvid; - u16 pvid = 0; - u32 val; - - if (vlan < MT753X_NUM_VLANS && gsw->vlan_entries[vlan].member) - pvid = gsw->vlan_entries[vlan].vid; - - val = mt753x_reg_read(gsw, PPBV1(i)); - val &= ~GRP_PORT_VID_M; - val |= pvid; - mt753x_reg_write(gsw, PPBV1(i), val); - } -} - -struct mt753x_mapping *mt753x_find_mapping(struct device_node *np) -{ - const char *map; - int i; - - if (of_property_read_string(np, "mediatek,portmap", &map)) - return NULL; - - for (i = 0; i < ARRAY_SIZE(mt753x_def_mapping); i++) - if (!strcmp(map, mt753x_def_mapping[i].name)) - return &mt753x_def_mapping[i]; - - return NULL; -} - -void mt753x_apply_mapping(struct gsw_mt753x *gsw, struct mt753x_mapping *map) -{ - int i = 0; - - for (i = 0; i < MT753X_NUM_PORTS; i++) - gsw->port_entries[i].pvid = map->pvids[i]; - - for (i = 0; i < MT753X_NUM_VLANS; i++) { - gsw->vlan_entries[i].member = map->members[i]; - gsw->vlan_entries[i].etags = map->etags[i]; - gsw->vlan_entries[i].vid = map->vids[i]; - } -} diff --git a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.h b/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.h deleted file mode 100644 index c726b8eac..000000000 --- a/target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2018 MediaTek Inc. - */ - -#ifndef _MT753X_VLAN_H_ -#define _MT753X_VLAN_H_ - -#define MT753X_NUM_PORTS 7 -#define MT753X_NUM_VLANS 4095 -#define MT753X_MAX_VID 4095 -#define MT753X_MIN_VID 0 - -struct gsw_mt753x; - -struct mt753x_port_entry { - u16 pvid; -}; - -struct mt753x_vlan_entry { - u16 vid; - u8 member; - u8 etags; -}; - -struct mt753x_mapping { - char *name; - u16 pvids[MT753X_NUM_PORTS]; - u8 members[MT753X_NUM_VLANS]; - u8 etags[MT753X_NUM_VLANS]; - u16 vids[MT753X_NUM_VLANS]; -}; - -extern struct mt753x_mapping mt753x_defaults[]; - -void mt753x_vlan_ctrl(struct gsw_mt753x *gsw, u32 cmd, u32 val); -void mt753x_apply_vlan_config(struct gsw_mt753x *gsw); -struct mt753x_mapping *mt753x_find_mapping(struct device_node *np); -void mt753x_apply_mapping(struct gsw_mt753x *gsw, struct mt753x_mapping *map); -#endif /* _MT753X_VLAN_H_ */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c index 75e5a5e74..85c12b000 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c @@ -144,7 +144,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule * RT_ERR_SMI - SMI access error * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. * Note: - * This function enable and intialize ACL function + * This function enable and initialize ACL function */ rtk_api_ret_t rtk_filter_igrAcl_init(void) { @@ -204,7 +204,7 @@ rtk_api_ret_t rtk_filter_igrAcl_init(void) * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL * comparison rules by means of linked list. Pointer pFilter_field will be added to linked - * list keeped by structure that pFilter_cfg points to. + * list kept by structure that pFilter_cfg points to. */ rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field) { @@ -348,7 +348,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule } else { - /*default acl template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/ + /*default ACL template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/ aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16)); aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16)); } @@ -557,7 +557,7 @@ static rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule * pFilter_cfg - The ACL configuration that this function will add comparison rule * pFilter_action - Action(s) of ACL configuration. * Output: - * ruleNum - number of rules written in acl table + * ruleNum - number of rules written in ACL table * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -1140,12 +1140,12 @@ rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void) /* Function Name: * rtk_filter_igrAcl_cfg_get * Description: - * Get one ingress acl configuration from ASIC. + * Get one ingress ACL configuration from ASIC. * Input: * filter_id - Start index of ACL configuration. * Output: - * pFilter_cfg - buffer pointer of ingress acl data - * pFilter_action - buffer pointer of ingress acl action + * pFilter_cfg - buffer pointer of ingress ACL data + * pFilter_action - buffer pointer of ingress ACL action * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -1462,7 +1462,7 @@ rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cf * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function sets action of packets when no ACL configruation matches. + * This function sets action of packets when no ACL configuration matches. */ rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action) { @@ -1535,7 +1535,7 @@ rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_un * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state) { @@ -1571,7 +1571,7 @@ rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t st * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState) { @@ -1699,7 +1699,7 @@ rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate) * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * Note: - * System support 16 user defined field selctors. + * System support 16 user defined field selectors. * Each selector can be enabled or disable. * User can defined retrieving 16-bits in many predefiend * standard l2/l3/l4 payload. @@ -1928,7 +1928,7 @@ rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *p * Set Port Range check * Input: * index - index of Port Range 0-15 - * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * upperPort - The upper bound of Port range * lowerPort - The lower Bound of Port range * Output: @@ -1977,7 +1977,7 @@ rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t * Input: * index - index of Port Range 0-15 * Output: - * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * pUpperPort - The upper bound of Port range * pLowerPort - The lower Bound of Port range * Return: @@ -2011,7 +2011,7 @@ rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t /* Function Name: * rtk_filter_igrAclPolarity_set * Description: - * Set ACL Goip control palarity + * Set ACL Goip control polarity * Input: * polarity - 1: High, 0: Low * Output: @@ -2034,7 +2034,7 @@ rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity) /* Function Name: * rtk_filter_igrAclPolarity_get * Description: - * Get ACL Goip control palarity + * Get ACL Goip control polarity * Input: * pPolarity - 1: High, 0: Low * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c index d1cd95b37..b031cbe92 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c @@ -113,7 +113,7 @@ rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable) * Note: * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) * to the frame that transmitting to CPU port. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE @@ -160,7 +160,7 @@ rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist * Note: * The API can get configured CPU port and its setting. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c index 170cbdaaf..18e145a21 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c @@ -233,7 +233,7 @@ rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask) * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -321,7 +321,7 @@ rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protoco * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -1217,7 +1217,7 @@ rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable * Description: * Get IGMP/MLD Group database * Input: - * indes - Index (0~255) + * index - Index (0~255) * Output: * pGroup - Group database information. * Return: @@ -1418,7 +1418,7 @@ rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pA /* Function Name: * rtk_igmp_dropLeaveZeroEnable_set * Description: - * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Set the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * enabled - Action 1: drop, 0:pass * Output: @@ -1451,7 +1451,7 @@ rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled) /* Function Name: * rtk_igmp_dropLeaveZeroEnable_get * Description: - * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Get the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * None * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h index 6308da8d4..634e7325d 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes ACL module high-layer API defination + * Feature : The file includes ACL module high-layer API definition * */ @@ -566,7 +566,7 @@ typedef enum rtk_filter_portrange_e * RT_ERR_SMI - SMI access error * RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL. * Note: - * This function enable and intialize ACL function + * This function enable and initialize ACL function */ extern rtk_api_ret_t rtk_filter_igrAcl_init(void); @@ -589,7 +589,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_init(void); * This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg). * Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL * comparison rules by means of linked list. Pointer pFilter_field will be added to linked - * list keeped by structure that pFilter_cfg points to. + * list kept by structure that pFilter_cfg points to. */ extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field); @@ -602,7 +602,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, * pFilter_cfg - The ACL configuration that this function will add comparison rule * pFilter_action - Action(s) of ACL configuration. * Output: - * ruleNum - number of rules written in acl table + * ruleNum - number of rules written in ACL table * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -657,12 +657,12 @@ extern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void); /* Function Name: * rtk_filter_igrAcl_cfg_get * Description: - * Get one ingress acl configuration from ASIC. + * Get one ingress ACL configuration from ASIC. * Input: * filter_id - Start index of ACL configuration. * Output: - * pFilter_cfg - buffer pointer of ingress acl data - * pFilter_action - buffer pointer of ingress acl action + * pFilter_cfg - buffer pointer of ingress ACL data + * pFilter_action - buffer pointer of ingress ACL action * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -690,7 +690,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_fi * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function sets action of packets when no ACL configruation matches. + * This function sets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action); @@ -709,7 +709,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_fi * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action); @@ -729,7 +729,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_fi * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state); @@ -748,7 +748,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_sta * RT_ERR_PORT_ID - Invalid port id. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This function gets action of packets when no ACL configruation matches. + * This function gets action of packets when no ACL configuration matches. */ extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state); @@ -802,7 +802,7 @@ extern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTe * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * Note: - * System support 16 user defined field selctors. + * System support 16 user defined field selectors. * Each selector can be enabled or disable. * User can defined retrieving 16-bits in many predefiend * standard l2/l3/l4 payload. @@ -917,7 +917,7 @@ extern rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidran * Set Port Range check * Input: * index - index of Port Range 0-15 - * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * upperPort - The upper bound of Port range * lowerPort - The lower Bound of Port range * Output: @@ -940,7 +940,7 @@ extern rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portr * Input: * index - index of Port Range 0-15 * Output: - * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port + * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port * pUpperPort - The upper bound of Port range * pLowerPort - The lower Bound of Port range * Return: @@ -957,7 +957,7 @@ extern rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portr /* Function Name: * rtk_filter_igrAclPolarity_set * Description: - * Set ACL Goip control palarity + * Set ACL Goip control polarity * Input: * polarity - 1: High, 0: Low * Output: @@ -973,7 +973,7 @@ extern rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity); /* Function Name: * rtk_filter_igrAclPolarity_get * Description: - * Get ACL Goip control palarity + * Get ACL Goip control polarity * Input: * pPolarity - 1: High, 0: Low * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h index 5544aca7b..67aa1e3d8 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes CPU module high-layer API defination + * Feature : The file includes CPU module high-layer API definition * */ @@ -107,7 +107,7 @@ extern rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable); * Note: * The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899) * to the frame that transmitting to CPU port. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE @@ -131,7 +131,7 @@ extern rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode) * RT_ERR_L2_NO_CPU_PORT - CPU port is not exist * Note: * The API can get configured CPU port and its setting. - * The inset cpu tag mode is as following: + * The insert CPU tag mode is as following: * - CPU_INSERT_TO_ALL * - CPU_INSERT_TO_TRAPPING * - CPU_INSERT_TO_NONE diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h index ef0a05a04..082ee2569 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes 1X module high-layer API defination + * Feature : The file includes 1X module high-layer API definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h index b670998c8..e3920363d 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes EEE module high-layer API defination + * Feature : The file includes EEE module high-layer API definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h index 2c7f0756a..110f41e81 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes I2C module high-layer API defination + * Feature : The file includes I2C module high-layer API definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h index f088b0ccd..b36db43d8 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes IGMP module high-layer API defination + * Feature : The file includes IGMP module high-layer API definition * */ @@ -205,7 +205,7 @@ extern rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask); * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -225,7 +225,7 @@ extern rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t * Input: * port - Port ID * protocol - IGMP/MLD protocol - * action - Per-port and per-protocol IGMP action seeting + * action - Per-port and per-protocol IGMP action setting * Output: * None. * Return: @@ -640,7 +640,7 @@ extern rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPk * Description: * Get IGMP/MLD Group database * Input: - * indes - Index (0~255) + * index - Index (0~255) * Output: * pGroup - Group database information. * Return: @@ -694,7 +694,7 @@ extern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAc /* Function Name: * rtk_igmp_dropLeaveZeroEnable_set * Description: - * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Set the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * enabled - Action 1: drop, 0:pass * Output: @@ -712,7 +712,7 @@ extern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled); /* Function Name: * rtk_igmp_dropLeaveZeroEnable_get * Description: - * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Get the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * None * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h index f2689ebc7..20625fff5 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes Interrupt module high-layer API defination + * Feature : The file includes Interrupt module high-layer API definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h index e0ccdbe3d..ec5aad2e3 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes L2 module high-layer API defination + * Feature : The file includes L2 module high-layer API definition * */ @@ -209,7 +209,7 @@ extern rtk_api_ret_t rtk_l2_init(void); * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * If the unicast mac address already existed in LUT, it will update the status of the entry. * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. */ @@ -307,7 +307,7 @@ extern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_da * RT_ERR_PORT_MASK - Invalid portmask. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the multicast mac address already existed in the LUT, it will udpate the + * If the multicast mac address already existed in the LUT, it will update the * port mask of the entry. Otherwise, it will find an empty or asic auto learned * entry to write. If all the entries with the same hash value can't be replaced, * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. @@ -383,7 +383,7 @@ extern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr); /* Function Name: * rtk_l2_ipMcastAddr_add * Description: - * Add Lut IP multicast entry + * Add LUT IP multicast entry * Input: * pIpMcastAddr - IP Multicast entry * Output: @@ -418,7 +418,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr); * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get Lut table of IP multicast entry. + * The API can get LUT table of IP multicast entry. */ extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr); @@ -465,7 +465,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr); /* Function Name: * rtk_l2_ipVidMcastAddr_add * Description: - * Add Lut IP multicast+VID entry + * Add LUT IP multicast+VID entry * Input: * pIpVidMcastAddr - IP & VID multicast Entry * Output: @@ -913,7 +913,7 @@ extern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac * Set flooding portmask * Input: * type - flooding type. - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Output: * None * Return: @@ -938,7 +938,7 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, r * Input: * type - flooding type. * Output: - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -956,10 +956,10 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, r /* Function Name: * rtk_l2_localPktPermit_set * Description: - * Set permittion of frames if source port and destination port are the same. + * Set permission of frames if source port and destination port are the same. * Input: * port - Port id. - * permit - permittion status + * permit - permission status * Output: * None * Return: @@ -969,34 +969,34 @@ extern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, r * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid permit value. * Note: - * This API is setted to permit frame if its source port is equal to destination port. + * This API is set to permit frame if its source port is equal to destination port. */ extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit); /* Function Name: * rtk_l2_localPktPermit_get * Description: - * Get permittion of frames if source port and destination port are the same. + * Get permission of frames if source port and destination port are the same. * Input: * port - Port id. * Output: - * pPermit - permittion status + * pPermit - permission status * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API is to get permittion status for frames if its source port is equal to destination port. + * This API is to get permission status for frames if its source port is equal to destination port. */ extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit); /* Function Name: * rtk_l2_aging_set * Description: - * Set LUT agging out speed + * Set LUT ageing out speed * Input: - * aging_time - Agging out time. + * aging_time - Ageing out time. * Output: * None * Return: @@ -1005,14 +1005,14 @@ extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pP * RT_ERR_SMI - SMI access error * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can set LUT agging out period for each entry and the range is from 14s to 800s. + * The API can set LUT ageing out period for each entry and the range is from 14s to 800s. */ extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time); /* Function Name: * rtk_l2_aging_get * Description: - * Get LUT agging out time + * Get LUT ageing out time * Input: * None * Output: @@ -1023,14 +1023,14 @@ extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time); * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * The API can get LUT agging out period for each entry. + * The API can get LUT ageing out period for each entry. */ extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time); /* Function Name: * rtk_l2_ipMcastAddrLookup_set * Description: - * Set Lut IP multicast lookup function + * Set LUT IP multicast lookup function * Input: * type - Lookup type for IPMC packet. * Output: @@ -1051,7 +1051,7 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type /* Function Name: * rtk_l2_ipMcastAddrLookup_get * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * None. * Output: @@ -1068,9 +1068,9 @@ extern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pTy /* Function Name: * rtk_l2_ipMcastForwardRouterPort_set * Description: - * Set IPMC packet forward to rounter port also or not + * Set IPMC packet forward to router port also or not * Input: - * enabled - 1: Inlcude router port, 0, exclude router port + * enabled - 1: Include router port, 0, exclude router port * Output: * None. * Return: @@ -1085,11 +1085,11 @@ extern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled); /* Function Name: * rtk_l2_ipMcastForwardRouterPort_get * Description: - * Get IPMC packet forward to rounter port also or not + * Get IPMC packet forward to router port also or not * Input: * None. * Output: - * pEnabled - 1: Inlcude router port, 0, exclude router port + * pEnabled - 1: Include router port, 0, exclude router port * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h index 13ef60df8..e5b22e287 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes Leaky module high-layer API defination + * Feature : The file includes Leaky module high-layer API definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h index 71acc7c92..7706107ef 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes LED module high-layer API defination + * Feature : The file includes LED module high-layer API definition * */ @@ -107,7 +107,7 @@ typedef enum rtk_led_serialOutput_e /* Function Name: * rtk_led_enable_set * Description: - * Set Led enable congiuration + * Set Led enable configuration * Input: * group - LED group id. * pPortmask - LED enable port mask. @@ -126,7 +126,7 @@ extern rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *p /* Function Name: * rtk_led_enable_get * Description: - * Get Led enable congiuration + * Get Led enable configuration * Input: * group - LED group id. * Output: @@ -188,7 +188,7 @@ extern rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode); /* Function Name: * rtk_led_modeForce_set * Description: - * Set Led group to congiuration force mode + * Set Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -214,7 +214,7 @@ extern rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t grou /* Function Name: * rtk_led_modeForce_get * Description: - * Get Led group to congiuration force mode + * Get Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -276,7 +276,7 @@ extern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate); /* Function Name: * rtk_led_groupConfig_set * Description: - * Set per group Led to congiuration mode + * Set per group Led to configuration mode * Input: * group - LED group. * config - LED configuration @@ -312,7 +312,7 @@ extern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_cong /* Function Name: * rtk_led_groupConfig_get * Description: - * Get Led group congiuration mode + * Get Led group configuration mode * Input: * group - LED group. * Output: @@ -370,7 +370,7 @@ extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_abi /* Function Name: * rtk_led_serialMode_set * Description: - * Set Led serial mode active congiuration + * Set Led serial mode active configuration * Input: * active - LED group. * Output: @@ -381,14 +381,14 @@ extern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_abi * RT_ERR_SMI - SMI access error * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set LED serial mode active congiuration. + * The API can set LED serial mode active configuration. */ extern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active); /* Function Name: * rtk_led_serialMode_get * Description: - * Get Led group congiuration mode + * Get Led group configuration mode * Input: * group - LED group. * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h index 1e984b7d8..8d179ce2d 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes Mirror module high-layer API defination + * Feature : The file includes Mirror module high-layer API definition * */ @@ -81,7 +81,7 @@ extern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_p * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror isolation function that prevent normal forwarding packets to miror port. + * The API is to set mirror isolation function that prevent normal forwarding packets to mirror port. */ extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable); @@ -118,7 +118,7 @@ extern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable); * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror VLAN leaky function forwarding packets to miror port. + * The API is to set mirror VLAN leaky function forwarding packets to mirror port. */ extern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); @@ -157,7 +157,7 @@ extern rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enabl * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror VLAN leaky function forwarding packets to miror port. + * The API is to set mirror VLAN leaky function forwarding packets to mirror port. */ extern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable); diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h index fcac1bcb8..458f16bf6 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes port module high-layer API defination + * Feature : The file includes port module high-layer API definition * */ @@ -222,7 +222,7 @@ typedef struct rtk_rtctResult_s /* Function Name: * rtk_port_phyAutoNegoAbility_set * Description: - * Set ethernet PHY auto-negotiation desired ability. + * Set Ethernet PHY auto-negotiation desired ability. * Input: * port - port id. * pAbility - Ability structure @@ -259,7 +259,7 @@ extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_p * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); @@ -303,14 +303,14 @@ extern rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_ * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ extern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility); /* Function Name: * rtk_port_phyStatus_get * Description: - * Get ethernet PHY linking status + * Get Ethernet PHY linking status * Input: * port - Port id. * Output: @@ -459,7 +459,7 @@ extern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_abilit * For UTP port, This API will also enable the digital * loopback bit in PHY register for sync of speed between * PHY and MAC. For EXT port, users need to force the - * link state by themself. + * link state by themselves. */ extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable); @@ -527,7 +527,7 @@ extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg /* Function Name: * rtk_port_backpressureEnable_set * Description: - * Set the half duplex backpressure enable status of the specific port. + * Set the half duplex back-pressure enable status of the specific port. * Input: * port - port id. * enable - Back pressure status. @@ -540,8 +540,8 @@ extern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid enable input. * Note: - * This API can set the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can set the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE * - ENABLE */ @@ -550,7 +550,7 @@ extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable /* Function Name: * rtk_port_backpressureEnable_get * Description: - * Get the half duplex backpressure enable status of the specific port. + * Get the half duplex back-pressure enable status of the specific port. * Input: * port - Port id. * Output: @@ -561,8 +561,8 @@ extern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API can get the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can get the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE * - ENABLE */ @@ -594,7 +594,7 @@ extern rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enab /* Function Name: * rtk_port_adminEnable_get * Description: - * Get port admin configurationof the specific port. + * Get port admin configuration of the specific port. * Input: * port - Port id. * Output: @@ -628,7 +628,7 @@ extern rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEn * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_PORT_MASK - Invalid portmask. * Note: - * This API set the port mask that a port can trasmit packet to of each port + * This API set the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask); @@ -647,7 +647,7 @@ extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPo * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API get the port mask that a port can trasmit packet to of each port + * This API get the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask); @@ -669,7 +669,7 @@ extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPo * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay. */ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay); @@ -690,7 +690,7 @@ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDe * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay. */ extern rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay); diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h index 6c4aca5a5..d18c4a01e 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes time module high-layer API defination + * Feature : The file includes time module high-layer API definition * */ @@ -310,7 +310,7 @@ extern rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnab /* Function Name: * rtk_ptp_portTimestamp_get * Description: - * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device. * Input: * unit - unit id * port - port id diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h index 4be417486..d2d8fac24 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes QoS module high-layer API defination + * Feature : The file includes QoS module high-layer API definition * */ @@ -123,7 +123,7 @@ typedef rtk_uint32 rtk_queue_num_t; /* queue number*/ /* Function Name: * rtk_qos_init * Description: - * Configure Qos default settings with queue number assigment to each port. + * Configure QoS default settings with queue number assignment to each port. * Input: * queueNum - Queue number of each port. * Output: @@ -135,7 +135,7 @@ typedef rtk_uint32 rtk_queue_num_t; /* queue number*/ * RT_ERR_QUEUE_NUM - Invalid queue number. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This API will initialize related Qos setting with queue number assigment. + * This API will initialize related QoS setting with queue number assignment. * The queue number is from 1 to 8. */ extern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum); @@ -235,7 +235,7 @@ extern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_p * RT_ERR_VLAN_PRIORITY - Invalid priority. * RT_ERR_QOS_INT_PRIORITY - Invalid priority. * Note: - * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. */ extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri); diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h index 231ed01bb..b3cdf432f 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h @@ -9,7 +9,7 @@ * * Purpose : RTL8367/RTL8367C switch high-level API * - * Feature : The file includes rate module high-layer API defination + * Feature : The file includes rate module high-layer API definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h index dc9c0bed3..54d1a13f3 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h @@ -40,7 +40,7 @@ typedef enum rt_error_code_e RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */ RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */ RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */ - RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */ + RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy waiting time out */ RT_ERR_MAC, /* 0x0000000b, invalid mac address */ RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */ RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */ @@ -57,7 +57,7 @@ typedef enum rt_error_code_e /* 0x0001xxxx for vlan */ RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */ RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */ - RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */ + RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, empty entry of vlan table */ RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */ RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */ RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */ @@ -165,7 +165,7 @@ typedef enum rt_error_code_e RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */ RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */ RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */ - RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */ + RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incoming packet for input bandwidth control */ RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth */ /* 0x000dxxxx for QoS */ @@ -220,7 +220,7 @@ typedef enum rt_error_code_e RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */ RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */ RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */ - RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */ + RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch error */ RT_ERR_END /* The symbol is the latest symbol */ } rt_error_code_t; diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h index b0ca13682..0a43c0dbd 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h @@ -185,10 +185,10 @@ typedef enum rtk_switch_maxPktLen_linkSpeed_e { #define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK) #define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__) for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++) if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK) -/* Port mask defination */ +/* Port mask definition */ #define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get()) -/* Port defination*/ +/* Port definition*/ #define RTK_MAX_LOGICAL_PORT_ID (rtk_switch_maxLogicalPort_get()) /* Function Name: @@ -477,7 +477,7 @@ extern rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask); /* Function Name: * rtk_switch_portmask_L2P_get * Description: - * Get physicl portmask from logical portmask + * Get physical portmask from logical portmask * Input: * pLogicalPmask - logical port mask * Output: @@ -546,7 +546,7 @@ rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask); /* Function Name: * rtk_switch_init * Description: - * Set chip to default configuration enviroment + * Set chip to default configuration environment * Input: * None * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h index 589ecb781..cafc7ff9d 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h @@ -56,13 +56,13 @@ typedef enum rtk_enable_e #define ETHER_ADDR_LEN 6 #endif -/* ethernet address type */ +/* Ethernet address type */ typedef struct rtk_mac_s { rtk_uint8 octet[ETHER_ADDR_LEN]; } rtk_mac_t; -typedef rtk_uint32 rtk_pri_t; /* priority vlaue */ +typedef rtk_uint32 rtk_pri_t; /* priority value */ typedef rtk_uint32 rtk_qid_t; /* queue id type */ typedef rtk_uint32 rtk_data_t; typedef rtk_uint32 rtk_dscp_t; /* dscp vlaue */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h index f7a460145..982e2c4bf 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h @@ -38,7 +38,7 @@ extern ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode); extern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode); extern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri); extern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri); -extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion); +extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position); extern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion); extern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode); extern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode); diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h index 38fd085d0..95c1b20bd 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Green ethernet related functions + * Feature : Green Ethernet related functions * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h index 26042bfa1..d0a899587 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Qos related functions + * Feature : QoS related functions * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h index d142d25cf..e492e715b 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Unkown multicast related functions + * Feature : Unknown multicast related functions * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h index 676ca8ed7..7a70e158f 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Regsiter MACRO related definition + * Feature : Register MACRO related definition * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h index eb4f48b83..f973c7bcb 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h @@ -20357,8 +20357,8 @@ auto-generated register address and field data #define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000 #define RTL8367C_REPORT_FORWARD_OFFSET 12 #define RTL8367C_REPORT_FORWARD_MASK 0x1000 -#define RTL8367C_ROBURSTNESS_VAR_OFFSET 9 -#define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00 +#define RTL8367C_ROBUSTNESS_VAR_OFFSET 9 +#define RTL8367C_ROBUSTNESS_VAR_MASK 0xE00 #define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8 #define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100 #define RTL8367C_REPORT_SUPPRESSION_OFFSET 7 diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c index feff0b240..e73199a4e 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c @@ -86,7 +86,7 @@ rtk_api_ret_t rtk_l2_init(void) * RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the unicast mac address already existed in LUT, it will udpate the status of the entry. + * If the unicast mac address already existed in LUT, it will update the status of the entry. * Otherwise, it will find an empty or asic auto learned entry to write. If all the entries * with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. */ @@ -453,7 +453,7 @@ rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data) * RT_ERR_PORT_MASK - Invalid portmask. * RT_ERR_INPUT - Invalid input parameters. * Note: - * If the multicast mac address already existed in the LUT, it will udpate the + * If the multicast mac address already existed in the LUT, it will update the * port mask of the entry. Otherwise, it will find an empty or asic auto learned * entry to write. If all the entries with the same hash value can't be replaced, * ASIC will return a RT_ERR_L2_INDEXTBL_FULL error. @@ -800,7 +800,7 @@ rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr) /* Function Name: * rtk_l2_ipMcastAddr_add * Description: - * Add Lut IP multicast entry + * Add LUT IP multicast entry * Input: * pIpMcastAddr - IP Multicast entry * Output: @@ -914,7 +914,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr) * RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get Lut table of IP multicast entry. + * The API can get LUT table of IP multicast entry. */ rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr) { @@ -1080,7 +1080,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr) /* Function Name: * rtk_l2_ipVidMcastAddr_add * Description: - * Add Lut IP multicast+VID entry + * Add LUT IP multicast+VID entry * Input: * pIpVidMcastAddr - IP & VID multicast Entry * Output: @@ -2143,7 +2143,7 @@ rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt) * Set flooding portmask * Input: * type - flooding type. - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Output: * None * Return: @@ -2204,7 +2204,7 @@ rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_port * Input: * type - flooding type. * Output: - * pFlood_portmask - flooding porkmask + * pFlood_portmask - flooding portmask * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -2259,10 +2259,10 @@ rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_port /* Function Name: * rtk_l2_localPktPermit_set * Description: - * Set permittion of frames if source port and destination port are the same. + * Set permission of frames if source port and destination port are the same. * Input: * port - Port id. - * permit - permittion status + * permit - permission status * Output: * None * Return: @@ -2272,7 +2272,7 @@ rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_port * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid permit value. * Note: - * This API is setted to permit frame if its source port is equal to destination port. + * This API is set to permit frame if its source port is equal to destination port. */ rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) { @@ -2296,18 +2296,18 @@ rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit) /* Function Name: * rtk_l2_localPktPermit_get * Description: - * Get permittion of frames if source port and destination port are the same. + * Get permission of frames if source port and destination port are the same. * Input: * port - Port id. * Output: - * pPermit - permittion status + * pPermit - permission status * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API is to get permittion status for frames if its source port is equal to destination port. + * This API is to get permission status for frames if its source port is equal to destination port. */ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) { @@ -2331,9 +2331,9 @@ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) /* Function Name: * rtk_l2_aging_set * Description: - * Set LUT agging out speed + * Set LUT ageing out speed * Input: - * aging_time - Agging out time. + * aging_time - Ageing out time. * Output: * None * Return: @@ -2342,7 +2342,7 @@ rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit) * RT_ERR_SMI - SMI access error * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can set LUT agging out period for each entry and the range is from 45s to 458s. + * The API can set LUT ageing out period for each entry and the range is from 45s to 458s. */ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) { @@ -2371,7 +2371,7 @@ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) /* Function Name: * rtk_l2_aging_get * Description: - * Get LUT agging out time + * Get LUT ageing out time * Input: * None * Output: @@ -2382,7 +2382,7 @@ rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * The API can get LUT agging out period for each entry. + * The API can get LUT ageing out period for each entry. */ rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time) { @@ -2416,7 +2416,7 @@ rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time) /* Function Name: * rtk_l2_ipMcastAddrLookup_set * Description: - * Set Lut IP multicast lookup function + * Set LUT IP multicast lookup function * Input: * type - Lookup type for IPMC packet. * Output: @@ -2473,7 +2473,7 @@ rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type) /* Function Name: * rtk_l2_ipMcastAddrLookup_get * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * None. * Output: @@ -2518,9 +2518,9 @@ rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType) /* Function Name: * rtk_l2_ipMcastForwardRouterPort_set * Description: - * Set IPMC packet forward to rounter port also or not + * Set IPMC packet forward to router port also or not * Input: - * enabled - 1: Inlcude router port, 0, exclude router port + * enabled - 1: Include router port, 0, exclude router port * Output: * None. * Return: @@ -2549,11 +2549,11 @@ rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled) /* Function Name: * rtk_l2_ipMcastForwardRouterPort_get * Description: - * Get IPMC packet forward to rounter port also or not + * Get IPMC packet forward to router port also or not * Input: * None. * Output: - * pEnabled - 1: Inlcude router port, 0, exclude router port + * pEnabled - 1: Include router port, 0, exclude router port * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c index c00c331d8..02e0829dc 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c @@ -27,7 +27,7 @@ /* Function Name: * rtk_led_enable_set * Description: - * Set Led enable congiuration + * Set Led enable configuration * Input: * group - LED group id. * pPortmask - LED enable port mask. @@ -74,7 +74,7 @@ rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmas /* Function Name: * rtk_led_enable_get * Description: - * Get Led enable congiuration + * Get Led enable configuration * Input: * group - LED group id. * Output: @@ -205,7 +205,7 @@ rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode) /* Function Name: * rtk_led_modeForce_set * Description: - * Set Led group to congiuration force mode + * Set Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -255,7 +255,7 @@ rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_ /* Function Name: * rtk_led_modeForce_get * Description: - * Get Led group to congiuration force mode + * Get Led group to configuration force mode * Input: * port - port ID * group - Support LED group id. @@ -369,7 +369,7 @@ rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate) /* Function Name: * rtk_led_groupConfig_set * Description: - * Set per group Led to congiuration mode + * Set per group Led to configuration mode * Input: * group - LED group. * config - LED configuration @@ -422,7 +422,7 @@ rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t co /* Function Name: * rtk_led_groupConfig_get * Description: - * Get Led group congiuration mode + * Get Led group configuration mode * Input: * group - LED group. * Output: @@ -583,7 +583,7 @@ rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t /* Function Name: * rtk_led_serialMode_set * Description: - * Set Led serial mode active congiuration + * Set Led serial mode active configuration * Input: * active - LED group. * Output: @@ -594,7 +594,7 @@ rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t * RT_ERR_SMI - SMI access error * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set LED serial mode active congiuration. + * The API can set LED serial mode active configuration. */ rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c index 1921d1a5a..3bbad8adb 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c @@ -66,7 +66,7 @@ rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask); - /*Mirror Sorce Port Mask Check*/ + /*Mirror Source Port Mask Check*/ if (pMirrored_tx_portmask->bits[0]!=pMirrored_rx_portmask->bits[0]&&pMirrored_tx_portmask->bits[0]!=0&&pMirrored_rx_portmask->bits[0]!=0) return RT_ERR_PORT_MASK; @@ -353,7 +353,7 @@ rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pR * RT_ERR_SMI - SMI access error * RT_ERR_ENABLE - Invalid enable input * Note: - * The API is to set mirror VLAN leaky function forwarding packets to miror port. + * The API is to set mirror VLAN leaky function forwarding packets to mirror port. */ rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c index 9f99d1b3d..9c7bcd0e3 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c @@ -410,7 +410,7 @@ static rtk_api_ret_t _rtk_port_FiberModeAbility_get(rtk_port_t port, rtk_port_ph /* Function Name: * rtk_port_phyAutoNegoAbility_set * Description: - * Set ethernet PHY auto-negotiation desired ability. + * Set Ethernet PHY auto-negotiation desired ability. * Input: * port - port id. * pAbility - Ability structure @@ -618,7 +618,7 @@ rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_abil * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) { @@ -836,7 +836,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_abi if (1 == pAbility->AsyFC) { - /*Asymetric flow control in reg 4.11*/ + /*Asymmetric flow control in reg 4.11*/ phyEnMsk4 = phyEnMsk4 | (1 << 11); } if (1 == pAbility->FC) @@ -892,7 +892,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_abi * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy * Note: - * Get the capablity of specified PHY. + * Get the capability of specified PHY. */ rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility) { @@ -982,7 +982,7 @@ rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_abi /* Function Name: * rtk_port_phyStatus_get * Description: - * Get ethernet PHY linking status + * Get Ethernet PHY linking status * Input: * port - Port id. * Output: @@ -1363,7 +1363,7 @@ rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pP * For UTP port, This API will also enable the digital * loopback bit in PHY register for sync of speed between * PHY and MAC. For EXT port, users need to force the - * link state by themself. + * link state by themselves. */ rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable) { @@ -1508,7 +1508,7 @@ rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_p /* Function Name: * rtk_port_backpressureEnable_set * Description: - * Set the half duplex backpressure enable status of the specific port. + * Set the half duplex back-pressure enable status of the specific port. * Input: * port - port id. * enable - Back pressure status. @@ -1521,10 +1521,10 @@ rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_p * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_ENABLE - Invalid enable input. * Note: - * This API can set the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can set the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE(Defer) - * - ENABLE (Backpressure) + * - ENABLE (Back-pressure) */ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable) { @@ -1548,7 +1548,7 @@ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enab /* Function Name: * rtk_port_backpressureEnable_get * Description: - * Get the half duplex backpressure enable status of the specific port. + * Get the half duplex back-pressure enable status of the specific port. * Input: * port - Port id. * Output: @@ -1559,10 +1559,10 @@ rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enab * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API can get the half duplex backpressure enable status of the specific port. - * The half duplex backpressure enable status of the port is as following: + * This API can get the half duplex back-pressure enable status of the specific port. + * The half duplex back-pressure enable status of the port is as following: * - DISABLE(Defer) - * - ENABLE (Backpressure) + * - ENABLE (Back-pressure) */ rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable) { @@ -1643,7 +1643,7 @@ rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable) /* Function Name: * rtk_port_adminEnable_get * Description: - * Get port admin configurationof the specific port. + * Get port admin configuration of the specific port. * Input: * port - Port id. * Output: @@ -1704,7 +1704,7 @@ rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable) * RT_ERR_PORT_ID - Invalid port number. * RT_ERR_PORT_MASK - Invalid portmask. * Note: - * This API set the port mask that a port can trasmit packet to of each port + * This API set the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) @@ -1747,7 +1747,7 @@ rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number. * Note: - * This API get the port mask that a port can trasmit packet to of each port + * This API get the port mask that a port can transmit packet to of each port * A port can only transmit packet to ports included in permitted portmask */ rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) @@ -1790,7 +1790,7 @@ rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask) * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay. */ rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay) { @@ -1841,7 +1841,7 @@ rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rt * Note: * This API can set external interface 2 RGMII delay. * In TX delay, there are 2 selection: no-delay and 2ns delay. - * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay. + * In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay. */ rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c index 40962a0e6..af8ce3091 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c @@ -401,7 +401,7 @@ rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable) /* Function Name: * rtk_ptp_portTimestamp_get * Description: - * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device. + * Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device. * Input: * unit - unit id * port - port id diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c index 70067a301..9bcb49cfb 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c @@ -28,7 +28,7 @@ /* Function Name: * rtk_qos_init * Description: - * Configure Qos default settings with queue number assigment to each port. + * Configure QoS default settings with queue number assignment to each port. * Input: * queueNum - Queue number of each port. * Output: @@ -40,7 +40,7 @@ * RT_ERR_QUEUE_NUM - Invalid queue number. * RT_ERR_INPUT - Invalid input parameters. * Note: - * This API will initialize related Qos setting with queue number assigment. + * This API will initialize related QoS setting with queue number assignment. * The queue number is from 1 to 8. */ rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum) @@ -143,7 +143,7 @@ rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum) return retVal; } - /* Finetune B/T value */ + /* Fine-tune B/T value */ if((retVal = rtl8367c_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK) return retVal; @@ -455,7 +455,7 @@ rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri) * RT_ERR_VLAN_PRIORITY - Invalid priority. * RT_ERR_QOS_INT_PRIORITY - Invalid priority. * Note: - * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling. + * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling. */ rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c index d3ca02975..0ecc32a6b 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c @@ -8,7 +8,7 @@ * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt * * $Revision: 76306 $ - * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $ + * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : Declaration of RLDP and RLPP API * @@ -404,7 +404,7 @@ rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pP * RT_ERR_NULL_POINTER * Note: * Clear operation effect loop_enter and loop_leave only, other field in - * the structure are don't care. Loop status cab't be clean. + * the structure are don't care. Loop status can't be clean. */ rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c index 0bb0db077..20542f259 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c @@ -152,7 +152,7 @@ static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl = /* Minimum physical port number */ 0, - /* Maxmum physical port number */ + /* Maximum physical port number */ 10, /* Physical port mask */ @@ -221,7 +221,7 @@ static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl = /* Minimum physical port number */ 0, - /* Maxmum physical port number */ + /* Maximum physical port number */ 7, /* Physical port mask */ @@ -290,7 +290,7 @@ static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl = /* Minimum physical port number */ 0, - /* Maxmum physical port number */ + /* Maximum physical port number */ 7, /* Physical port mask */ @@ -1215,7 +1215,7 @@ rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask) /* Function Name: * rtk_switch_portmask_L2P_get * Description: - * Get physicl portmask from logical portmask + * Get physical portmask from logical portmask * Input: * pLogicalPmask - logical port mask * Output: @@ -1351,7 +1351,7 @@ rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask) /* Function Name: * rtk_switch_init * Description: - * Set chip to default configuration enviroment + * Set chip to default configuration environment * Input: * None * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c index d9ccd9711..1e4d2961e 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c @@ -173,7 +173,7 @@ static void _rtl8367c_aclActStUser2Smi(rtl8367c_acl_act_t *pAclUser, rtk_uint16 /* Function Name: * rtl8367c_setAsicAcl * Description: - * Set port acl function enable/disable + * Set port ACL function enable/disable * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -196,7 +196,7 @@ ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicAcl * Description: - * Get port acl function enable/disable + * Get port ACL function enable/disable * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -219,7 +219,7 @@ ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicAclUnmatchedPermit * Description: - * Set port acl function unmatched permit action + * Set port ACL function unmatched permit action * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -242,7 +242,7 @@ ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicAclUnmatchedPermit * Description: - * Get port acl function unmatched permit action + * Get port ACL function unmatched permit action * Input: * port - Physical port number (0~10) * enabled - 1: enabled, 0: disabled @@ -266,10 +266,10 @@ ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicAclRule * Description: - * Set acl rule content + * Set ACL rule content * Input: * index - ACL rule index (0-95) of 96 ACL rules - * pAclRule - ACL rule stucture for setting + * pAclRule - ACL rule structure for setting * Output: * None * Return: @@ -278,8 +278,8 @@ ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled) * RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95) * Note: * System supported 95 shared 289-bit ACL ingress rule. Index was available at range 0-95 only. - * If software want to modify ACL rule, the ACL function should be disable at first or unspecify - * acl action will be executed. + * If software want to modify ACL rule, the ACL function should be disabled at first or unspecified + * ACL action will be executed. * One ACL rule structure has three parts setting: * Bit 0-147 Data Bits of this Rule * Bit 148 Valid Bit @@ -410,10 +410,10 @@ ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule* pAclRule) /* Function Name: * rtl8367c_getAsicAclRule * Description: - * Get acl rule content + * Get ACL rule content * Input: * index - ACL rule index (0-63) of 64 ACL rules - * pAclRule - ACL rule stucture for setting + * pAclRule - ACL rule structure for setting * Output: * None * Return: @@ -588,7 +588,7 @@ ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot) * Set fields of a ACL Template * Input: * index - ACL template index(0~4) - * pAclType - ACL type stucture for setting + * pAclType - ACL type structure for setting * Output: * None * Return: @@ -598,7 +598,7 @@ ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot) * Note: * The API can set type field of the 5 ACL rule templates. * Each type has 8 fields. One field means what data in one field of a ACL rule means - * 8 fields of ACL rule 0~95 is descripted by one type in ACL group + * 8 fields of ACL rule 0~95 is described by one type in ACL group */ ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType) { @@ -630,7 +630,7 @@ ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAcl * Get fields of a ACL Template * Input: * index - ACL template index(0~4) - * pAclType - ACL type stucture for setting + * pAclType - ACL type structure for setting * Output: * None * Return: @@ -669,7 +669,7 @@ ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAcl * Set ACL rule matched Action * Input: * index - ACL rule index (0-95) of 96 ACL rules - * pAclAct - ACL action stucture for setting + * pAclAct - ACL action structure for setting * Output: * None * Return: @@ -734,7 +734,7 @@ ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct) * Get ACL rule matched Action * Input: * index - ACL rule index (0-95) of 96 ACL rules - * pAclAct - ACL action stucture for setting + * pAclAct - ACL action structure for setting * Output: * None * Return: @@ -1137,7 +1137,7 @@ ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* /* Function Name: * rtl8367c_setAsicAclGpioPolarity * Description: - * Set ACL Goip control palarity + * Set ACL Goip control polarity * Input: * polarity - 1: High, 0: Low * Output: @@ -1155,7 +1155,7 @@ ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity) /* Function Name: * rtl8367c_getAsicAclGpioPolarity * Description: - * Get ACL Goip control palarity + * Get ACL Goip control polarity * Input: * pPolarity - 1: High, 0: Low * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c index d22bf65ea..ec9c332e1 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c @@ -18,7 +18,7 @@ /* Function Name: * rtl8367c_setAsicCputagEnable * Description: - * Set cpu tag function enable/disable + * Set CPU tag function enable/disable * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -41,7 +41,7 @@ ret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicCputagEnable * Description: - * Get cpu tag function enable/disable + * Get CPU tag function enable/disable * Input: * pEnabled - 1: enabled, 0: disabled * Output: @@ -59,7 +59,7 @@ ret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled) /* Function Name: * rtl8367c_setAsicCputagTrapPort * Description: - * Set cpu tag trap port + * Set CPU tag trap port * Input: * port - port number * Output: @@ -91,7 +91,7 @@ ret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port) /* Function Name: * rtl8367c_getAsicCputagTrapPort * Description: - * Get cpu tag trap port + * Get CPU tag trap port * Input: * pPort - port number * Output: @@ -248,9 +248,9 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe /* Function Name: * rtl8367c_setAsicCputagPosition * Description: - * Set cpu tag insert position + * Set CPU tag insert position * Input: - * postion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) + * position - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) * Output: * None * Return: @@ -259,14 +259,14 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe * Note: * None */ -ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion) +ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position) { - return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion); + return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, position); } /* Function Name: * rtl8367c_getAsicCputagPosition * Description: - * Get cpu tag insert position + * Get CPU tag insert position * Input: * pPostion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default) * Output: @@ -285,7 +285,7 @@ ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion) /* Function Name: * rtl8367c_setAsicCputagMode * Description: - * Set cpu tag mode + * Set CPU tag mode * Input: * mode - 1: 4bytes mode, 0: 8bytes mode * Output: @@ -308,7 +308,7 @@ ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicCputagMode * Description: - * Get cpu tag mode + * Get CPU tag mode * Input: * pMode - 1: 4bytes mode, 0: 8bytes mode * Output: @@ -326,7 +326,7 @@ ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode) /* Function Name: * rtl8367c_setAsicCputagRxMinLength * Description: - * Set cpu tag mode + * Set CPU tag mode * Input: * mode - 1: 64bytes, 0: 72bytes * Output: @@ -349,7 +349,7 @@ ret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicCputagRxMinLength * Description: - * Get cpu tag mode + * Get CPU tag mode * Input: * pMode - 1: 64bytes, 0: 72bytes * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c index 370b7c6f3..811ee4795 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c @@ -100,7 +100,7 @@ ret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac) * Description: * Set PTP parser tag TPID. * Input: - * outerTag - outter tag TPID + * outerTag - outer tag TPID * innerTag - inner tag TPID * Output: * None @@ -128,7 +128,7 @@ ret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag) * Input: * None * Output: - * pOuterTag - outter tag TPID + * pOuterTag - outer tag TPID * pInnerTag - inner tag TPID * Return: * RT_ERR_OK - Success @@ -161,7 +161,7 @@ ret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * The time granuality is 8 nano seconds. + * The time granularity is 8 nano seconds. */ ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond) { @@ -218,7 +218,7 @@ ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * The time granuality is 8 nano seconds. + * The time granularity is 8 nano seconds. */ ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond) { @@ -265,7 +265,7 @@ ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond) * Description: * Set PTP system time adjust * Input: - * type - incresae or decrease + * type - increase or decrease * second - seconds * nanoSecond - nano seconds * Output: @@ -481,7 +481,7 @@ ret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1. + * This API can be used to clear ASIC interrupt status and register will be cleared by writing 1. * [0]:TX_SYNC, * [1]:TX_DELAY, * [2]:TX_PDELAY_REQ, @@ -570,7 +570,7 @@ ret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number * Note: - * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping + * If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping */ ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled) { @@ -646,7 +646,7 @@ ret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * The time granuality is 8 nano seconds. + * The time granularity is 8 nano seconds. */ ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp) { @@ -796,7 +796,7 @@ ret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled) * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number * Note: - * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping + * If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping */ ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c index 28f49b1ba..b7b102243 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c @@ -55,7 +55,7 @@ ret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect) /* Function Name: * rtl8367c_setAsicFlowControlJumboMode * Description: - * Set Jumbo threhsold for flow control + * Set Jumbo threshold for flow control * Input: * enabled - Jumbo mode flow control 1: Enable 0:Disable * Output: @@ -73,7 +73,7 @@ ret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicFlowControlJumboMode * Description: - * Get Jumbo threhsold for flow control + * Get Jumbo threshold for flow control * Input: * pEnabled - Jumbo mode flow control 1: Enable 0:Disable * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c index a38623850..3fb5f57b9 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Green ethernet related functions + * Feature : Green Ethernet related functions * */ #include @@ -22,7 +22,7 @@ * Get per-Port ingress page usage per second * Input: * port - Physical port number (0~7) - * pPage - page number of ingress packet occuping per second + * pPage - page number of ingress packet occurring per second * Output: * None * Return: @@ -30,7 +30,7 @@ * RT_ERR_SMI - SMI access error * RT_ERR_PORT_ID - Invalid port number * Note: - * Ingress traffic occuping page number per second for high layer green feature usage + * Ingress traffic occurring page number per second for high layer green feature usage */ ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage) { @@ -134,7 +134,7 @@ ret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port) * Get indicator which ASIC had received high priority traffic or not * Input: * port - Physical port number (0~7) - * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking priod + * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking period * Output: * None * Return: @@ -153,14 +153,14 @@ ret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pInd } /* -@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green ethernet function. +@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green Ethernet function. @parm rtk_uint32 | green | Green feature function usage 1:enable 0:disable. @rvalue RT_ERR_OK | Success. @rvalue RT_ERR_SMI | SMI access error. @comm The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic detect the cable length and then select different power mode for best performance with minimums power consumption. Link down - ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled. + ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled. */ ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green) { @@ -286,14 +286,14 @@ ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green) } /* -@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green ethernet function. +@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green Ethernet function. @parm rtk_uint32 | *green | Green feature function usage 1:enable 0:disable. @rvalue RT_ERR_OK | Success. @rvalue RT_ERR_SMI | SMI access error. @comm The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic detect the cable length and then select different power mode for best performance with minimums power consumption. Link down - ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled. + ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled. */ ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c index 435368d51..1b8ef59d9 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c @@ -30,7 +30,7 @@ * RT_ERR_SMI - SMI access error * RT_ERR_OUT_OF_RANGE - input parameter out of range * Note: - * System support 16 user defined field selctors. + * System support 16 user defined field selectors. * Each selector can be enabled or disable. User can defined retrieving 16-bits in many predefiend * standard l2/l3/l4 payload. */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c index e0e734d61..c915d2d61 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c @@ -429,8 +429,8 @@ ret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var) if(rob_var > RTL8367C_MAX_ROB_VAR) return RT_ERR_OUT_OF_RANGE; - /* Bourstness variable */ - retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var); + /* Robustness variable */ + retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, rob_var); if(retVal != RT_ERR_OK) return retVal; @@ -456,8 +456,8 @@ ret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *prob_var) ret_t retVal; rtk_uint32 value; - /* Bourstness variable */ - retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value); + /* Robustness variable */ + retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, &value); if(retVal != RT_ERR_OK) return retVal; @@ -1813,7 +1813,7 @@ ret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood) /* Function Name: * rtl8367c_setAsicIGMPDropLeaveZero * Description: - * Set the function of droppping Leave packet with group IP = 0.0.0.0 + * Set the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * drop - 1: Drop, 0:Bypass * Output: @@ -1838,7 +1838,7 @@ ret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop) /* Function Name: * rtl8367c_getAsicIGMPDropLeaveZero * Description: - * Get the function of droppping Leave packet with group IP = 0.0.0.0 + * Get the function of dropping Leave packet with group IP = 0.0.0.0 * Input: * None * Output: @@ -1865,7 +1865,7 @@ ret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop) /* Function Name: * rtl8367c_setAsicIGMPBypassStormCTRL * Description: - * Set the function of bypass strom control for IGMP/MLD packet + * Set the function of bypass storm control for IGMP/MLD packet * Input: * bypass - 1: Bypass, 0:not bypass * Output: @@ -1890,7 +1890,7 @@ ret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass) /* Function Name: * rtl8367c_getAsicIGMPBypassStormCTRL * Description: - * Set the function of bypass strom control for IGMP/MLD packet + * Set the function of bypass storm control for IGMP/MLD packet * Input: * None * Output: @@ -1944,7 +1944,7 @@ ret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky) * Description: * Get Port Isolation leaky for IGMP/MLD packet * Input: - * Noen + * None * Output: * pLeaky - 1: Leaky, 0:not leaky * Return: @@ -1996,7 +1996,7 @@ ret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky) * Description: * Get VLAN leaky for IGMP/MLD packet * Input: - * Noen + * None * Output: * pLeaky - 1: Leaky, 0:not leaky * Return: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c index abb36bec2..13a7b1424 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c @@ -128,7 +128,7 @@ ret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwid /* Function Name: * rtl8367c_setAsicPortIngressBandwidthBypass * Description: - * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP + * Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -146,7 +146,7 @@ ret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicPortIngressBandwidthBypass * Description: - * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP + * Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP * Input: * pEnabled - 1: enabled, 0: disabled * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c index fb6cbcdf1..1d5ccfc90 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c @@ -99,10 +99,10 @@ ret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1. + * This API can be used to clear ASIC interrupt status and register will be cleared by writing 1. * [0]:Link change, * [1]:Share meter exceed, - * [2]:Learn number overed, + * [2]:Learn number over, * [3]:Speed Change, * [4]:Tx special congestion * [5]:1 second green feature diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c index 118902816..6f2617f5a 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c @@ -607,7 +607,7 @@ ret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimo /* @func ret_t | rtl8367c_setAsicLedOutputEnable | Set LED output enable -@parm rtk_uint32 | enabled | enable or disalbe. +@parm rtk_uint32 | enabled | enable or disable. @rvalue RT_ERR_OK | Success. @rvalue RT_ERR_SMI | SMI access error. @rvalue RT_ERR_INPUT | Invalid input value. diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c index 343a6f159..1521467aa 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c @@ -207,7 +207,7 @@ static void _rtl8367c_fdbStSmi2User( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi /* Function Name: * rtl8367c_setAsicLutIpMulticastLookup * Description: - * Set Lut IP multicast lookup function + * Set LUT IP multicast lookup function * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -225,7 +225,7 @@ ret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicLutIpMulticastLookup * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * pEnabled - 1: enabled, 0: disabled * Output: @@ -244,7 +244,7 @@ ret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicLutIpMulticastLookup * Description: - * Set Lut IP multicast + VID lookup function + * Set LUT IP multicast + VID lookup function * Input: * enabled - 1: enabled, 0: disabled * Output: @@ -263,7 +263,7 @@ ret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicLutIpMulticastVidLookup * Description: - * Get Lut IP multicast lookup function + * Get LUT IP multicast lookup function * Input: * pEnabled - 1: enabled, 0: disabled * Output: @@ -282,7 +282,7 @@ ret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled) /* Function Name: * rtl8367c_setAsicLutIpLookupMethod * Description: - * Set Lut IP lookup hash with DIP or {DIP,SIP} pair + * Set LUT IP lookup hash with DIP or {DIP,SIP} pair * Input: * type - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash. * 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash. @@ -301,7 +301,7 @@ ret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type) /* Function Name: * rtl8367c_getAsicLutIpLookupMethod * Description: - * Get Lut IP lookup hash with DIP or {DIP,SIP} pair + * Get LUT IP lookup hash with DIP or {DIP,SIP} pair * Input: * pType - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash. * 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash. @@ -320,10 +320,10 @@ ret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType) /* Function Name: * rtl8367c_setAsicLutAgeTimerSpeed * Description: - * Set LUT agging out speed + * Set LUT ageing out speed * Input: - * timer - Agging out timer 0:Has been aged out - * speed - Agging out speed 0-fastest 3-slowest + * timer - Ageing out timer 0:Has been aged out + * speed - Ageing out speed 0-fastest 3-slowest * Output: * None * Return: @@ -346,10 +346,10 @@ ret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed) /* Function Name: * rtl8367c_getAsicLutAgeTimerSpeed * Description: - * Get LUT agging out speed + * Get LUT ageing out speed * Input: - * pTimer - Agging out timer 0:Has been aged out - * pSpeed - Agging out speed 0-fastest 3-slowest + * pTimer - Ageing out timer 0:Has been aged out + * pSpeed - Ageing out speed 0-fastest 3-slowest * Output: * None * Return: @@ -378,7 +378,7 @@ ret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed) /* Function Name: * rtl8367c_setAsicLutCamTbUsage * Description: - * Configure Lut CAM table usage + * Configure LUT CAM table usage * Input: * enabled - L2 CAM table usage 1: enabled, 0: disabled * Output: @@ -400,7 +400,7 @@ ret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicLutCamTbUsage * Description: - * Get Lut CAM table usage + * Get LUT CAM table usage * Input: * pEnabled - L2 CAM table usage 1: enabled, 0: disabled * Output: @@ -439,7 +439,7 @@ ret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled) * Note: * None */ - /*޸: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ + /*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number) { if(port > RTL8367C_PORTIDMAX) @@ -470,7 +470,7 @@ ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number) * Note: * None */ - /*޸: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ + /*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/ ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber) { if(port > RTL8367C_PORTIDMAX) @@ -498,7 +498,7 @@ ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber) * Note: * None */ - /*޸: RTL8367C_LUT_LEARNLIMITMAX*/ + /*modification: RTL8367C_LUT_LEARNLIMITMAX*/ ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number) { if(number > RTL8367C_LUT_LEARNLIMITMAX) @@ -632,7 +632,7 @@ ret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction) * Note: * None */ - /*޸: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ + /*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask) { ret_t retVal; @@ -666,7 +666,7 @@ ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask) * Note: * None */ - /*޸: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ + /*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/ ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask) { rtk_uint32 tmpmask; @@ -966,7 +966,7 @@ ret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table) * Note: * None */ - /*޸RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not contnious, wait for updating of base.h*/ + /*modification:RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not continuous, wait for updating of base.h*/ ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber) { ret_t retVal; @@ -1047,7 +1047,7 @@ ret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus) * Note: * None */ - /*port8~port10һregister, wait for updating of base.h, reg.h*/ + /*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/ ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask) { ret_t retVal; @@ -1079,7 +1079,7 @@ ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask) * Note: * None */ - /*port8~port10һregister, wait for updating of base.h, reg.h*/ + /*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/ ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask) { rtk_uint32 tmpMask; @@ -1142,7 +1142,7 @@ ret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode) * Description: * Get L2 LUT flush type * Input: - * type - 0: dynamice unicast; 1: both dynamic and static unicast entry + * type - 0: dynamic unicast; 1: both dynamic and static unicast entry * Output: * None * Return: @@ -1160,7 +1160,7 @@ ret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type) * Description: * Set L2 LUT flush type * Input: - * pType - 0: dynamice unicast; 1: both dynamic and static unicast entry + * pType - 0: dynamic unicast; 1: both dynamic and static unicast entry * Output: * None * Return: @@ -1271,7 +1271,7 @@ ret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid) * Note: * None */ - /*޸RTL8367C_PORTIDMAX*/ + /*modification:RTL8367C_PORTIDMAX*/ ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled) { if(port > RTL8367C_PORTIDMAX) @@ -1295,7 +1295,7 @@ ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled) * Note: * None */ - /*޸RTL8367C_PORTIDMAX*/ + /*modification:RTL8367C_PORTIDMAX*/ ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled) { if(port > RTL8367C_PORTIDMAX) @@ -1504,9 +1504,9 @@ ret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable) /* Function Name: * rtl8367c_setAsicLutIpmcFwdRouterPort * Description: - * Set IPMC packet forward to rounter port also or not + * Set IPMC packet forward to router port also or not * Input: - * enable - 1: Inlcude router port, 0, exclude router port + * enable - 1: Include router port, 0, exclude router port * Output: * None * Return: @@ -1527,11 +1527,11 @@ ret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable) /* Function Name: * rtl8367c_getAsicLutIpmcFwdRouterPort * Description: - * Get IPMC packet forward to rounter port also or not + * Get IPMC packet forward to router port also or not * Input: * None * Output: - * pEnable - 1: Inlcude router port, 0, exclude router port + * pEnable - 1: Include router port, 0, exclude router port * Return: * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c index c9aaa01d3..7da098c49 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c @@ -22,7 +22,7 @@ * Reset global/queue manage or per-port MIB counter * Input: * greset - Global reset - * qmreset - Queue maganement reset + * qmreset - Queue management reset * portmask - Port reset mask * Output: * None @@ -59,7 +59,7 @@ ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rt * Input: * port - Physical port number (0~7) * mibIdx - MIB counter index - * pCounter - MIB retrived counter + * pCounter - MIB retrieved counter * Output: * None * Return: @@ -69,9 +69,9 @@ ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rt * RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving * RT_ERR_STAT_CNTR_FAIL - MIB is resetting * Note: - * Before MIBs counter retrieving, writting accessing address to ASIC at first and check the MIB + * Before MIBs counter retrieving, writing accessing address to ASIC at first and check the MIB * control register status. If busy bit of MIB control is set, that means MIB counter have been - * waiting for preparing, then software must wait atfer this busy flag reset by ASIC. This driver + * waiting for preparing, then software must wait after this busy flag reset by ASIC. This driver * did not recycle reading user desired counter. Software must use driver again to get MIB counter * if return value is not RT_ERR_OK. */ @@ -124,7 +124,7 @@ ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, r /*writing access counter address first*/ /*This address is SRAM address, and SRAM address = MIB register address >> 2*/ - /*then ASIC will prepare 64bits counter wait for being retrived*/ + /*then ASIC will prepare 64bits counter wait for being retrieved*/ /*Write Mib related address to access control register*/ retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2)); if(retVal != RT_ERR_OK) @@ -183,7 +183,7 @@ ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, r /* Function Name: * rtl8367c_getAsicMIBsLogCounter * Description: - * Get MIBs Loggin counter + * Get MIBs Logging counter * Input: * index - The index of 32 logging counter (0 ~ 31) * Output: @@ -260,7 +260,7 @@ ret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter) * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error * Note: - * Software need to check this control register atfer doing port resetting or global resetting + * Software need to check this control register after doing port resetting or global resetting */ ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask) { @@ -513,7 +513,7 @@ ret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index) /* Function Name: * rtl8367c_setAsicMIBsLength * Description: - * Set MIB length couting mode + * Set MIB length counting mode * Input: * txLengthMode - 0: tag length doesn't be counted. 1: tag length is counted. * rxLengthMode - 0: tag length doesn't be counted. 1: tag length is counted. @@ -542,7 +542,7 @@ ret_t rtl8367c_setAsicMIBsLength(rtk_uint32 txLengthMode, rtk_uint32 rxLengthMod /* Function Name: * rtl8367c_setAsicMIBsLength * Description: - * Set MIB length couting mode + * Set MIB length counting mode * Input: * None. * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c index 78e80a0b2..fae046639 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c @@ -951,7 +951,7 @@ rtk_uint8 Sgmii_Init[SGMII_INIT_SIZE] = { * Set UNDA behavior * Input: * port - port ID - * behavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding + * behavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding * Output: * None * Return: @@ -981,7 +981,7 @@ ret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior * Input: * port - port ID * Output: - * pBehavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding + * pBehavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding * Return: * RT_ERR_OK - Success * RT_ERR_SMI - SMI access error @@ -3724,7 +3724,7 @@ ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode) return retVal; /* 1: MAC link = SGMII SerDes link - 0: MAC link = SGMII config link cfg_sgmii_link + 0: MAC link = SGMII config link (cfg_sgmii_link) */ if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) return retVal; @@ -4032,7 +4032,7 @@ ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode) if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK) return retVal; - /*select MAC link source when port6/7 be set sgmii mode cfg_sgmii_link*/ + /*select MAC link source when port6/7 be set sgmii mode (cfg_sgmii_link)*/ if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK) return retVal; } diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c index 89c3c3e02..69081049e 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Qos related functions + * Feature : QoS related functions * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c index 8ebd6796d..32d9b2084 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c @@ -19,7 +19,7 @@ /* Function Name: * rtl8367c_setAsicLeakyBucketParameter * Description: - * Set Leaky Bucket Paramters + * Set Leaky Bucket Parameters * Input: * tick - Tick is used for time slot size unit * token - Token is used for adding budget in each time slot @@ -55,7 +55,7 @@ ret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token) /* Function Name: * rtl8367c_getAsicLeakyBucketParameter * Description: - * Get Leaky Bucket Paramters + * Get Leaky Bucket Parameters * Input: * tick - Tick is used for time slot size unit * token - Token is used for adding budget in each time slot @@ -166,7 +166,7 @@ ret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apri * Set per-port APR enable * Input: * port - Physical port number (0~7) - * aprEnable - APR enable seting 1:enable 0:disable + * aprEnable - APR enable setting 1:enable 0:disable * Output: * None * Return: @@ -193,7 +193,7 @@ ret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable) * Get per-port APR enable * Input: * port - Physical port number (0~7) - * aprEnable - APR enable seting 1:enable 0:disable + * aprEnable - APR enable setting 1:enable 0:disable * Output: * None * Return: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c index f19ceba5a..e199664b5 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c @@ -140,7 +140,7 @@ ret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask) * RT_ERR_SMI - SMI access error * Note: * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 - * for Q-in-Q SLAN design. User can set mathced ether type as service provider supported protocol + * for Q-in-Q SLAN design. User can set matched ether type as service provider supported protocol */ ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType) { @@ -344,7 +344,7 @@ ret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex) /* Function Name: * rtl8367c_setAsicSvlanIngressUntag * Description: - * Set action received un-Stag frame from unplink port + * Set action received un-Stag frame from uplink port * Input: * mode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -362,7 +362,7 @@ ret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicSvlanIngressUntag * Description: - * Get action received un-Stag frame from unplink port + * Get action received un-Stag frame from uplink port * Input: * pMode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -380,7 +380,7 @@ ret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode) /* Function Name: * rtl8367c_setAsicSvlanIngressUnmatch * Description: - * Set action received unmatched Stag frame from unplink port + * Set action received unmatched Stag frame from uplink port * Input: * mode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -398,7 +398,7 @@ ret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode) /* Function Name: * rtl8367c_getAsicSvlanIngressUnmatch * Description: - * Get action received unmatched Stag frame from unplink port + * Get action received unmatched Stag frame from uplink port * Input: * pMode - 0:Drop 1:Trap 2:Assign SVLAN * Output: @@ -417,7 +417,7 @@ ret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode) /* Function Name: * rtl8367c_setAsicSvlanEgressUnassign * Description: - * Set unplink stream without egress SVID action + * Set uplink stream without egress SVID action * Input: * enabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID * Output: @@ -435,7 +435,7 @@ ret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled) /* Function Name: * rtl8367c_getAsicSvlanEgressUnassign * Description: - * Get unplink stream without egress SVID action + * Get uplink stream without egress SVID action * Input: * pEnabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID * Output: @@ -580,7 +580,7 @@ ret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_m * RT_ERR_SMI - SMI access error * RT_ERR_ENTRY_INDEX - Invalid entry index * Note: - * ASIC will check upstream's VID and assign related SVID to mathed packet + * ASIC will check upstream's VID and assign related SVID to matched packet */ ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c index fcebd1b7f..a3455bbeb 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c @@ -11,7 +11,7 @@ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $ * * Purpose : RTL8367C switch high-level API for RTL8367C - * Feature : Unkown multicast related functions + * Feature : Unknown multicast related functions * */ diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c index c272cad48..70e767f42 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c @@ -421,7 +421,7 @@ rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) con = 0; do { con++; - _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */ + _smi_readBit(1, &ACK); /* ACK for writing data [7:0] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; @@ -430,7 +430,7 @@ rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData) con = 0; do { con++; - _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */ + _smi_readBit(1, &ACK); /* ACK for writing data [15:8] */ } while ((ACK != 0) && (con < ack_timer)); if (ACK != 0) ret = RT_ERR_FAILED; diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c index 3a328b0ca..3fd028a29 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c @@ -140,7 +140,7 @@ rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_coun if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX) return RT_ERR_STAT_INVALID_GLOBAL_CNTR; - if ((retVal = rtl8367c_getAsicMIBsCounter(0, cntr_idx, pCntr)) != RT_ERR_OK) + if ((retVal = rtl8367c_getAsicMIBsCounter(0, (RTL8367C_MIBCOUNTER)cntr_idx, pCntr)) != RT_ERR_OK) return retVal; return RT_ERR_OK; @@ -172,7 +172,7 @@ rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs) if(NULL == pGlobal_cntrs) return RT_ERR_NULL_POINTER; - if ((retVal = rtl8367c_getAsicMIBsCounter(0,DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK) + if ((retVal = rtl8367c_getAsicMIBsCounter(0, dot1dTpLearnedEntryDiscards, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK) return retVal; return RT_ERR_OK; @@ -265,7 +265,7 @@ static rtk_api_ret_t _get_asic_mib_idx(rtk_stat_port_type_t cnt_idx, RTL8367C_MI * port - port id. * cntr_idx - port counter index. * Output: - * pCntr - MIB retrived counter. + * pCntr - MIB retrieved counter. * Return: * RT_ERR_OK - OK * RT_ERR_FAILED - Failed @@ -592,7 +592,7 @@ rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_len /* Function Name: * rtk_stat_lengthMode_get * Description: - * Get Legnth mode. + * Get Length mode. * Input: * None. * Output: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c index 13cf4e3cb..68063cdfa 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c @@ -279,7 +279,7 @@ rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_stor * RT_ERR_ENABLE - Invalid IFG parameter * Note: * - * This API can set per-port bypass stomr filter control frame type including RMA and igmp. + * This API can set per-port bypass storm filter control frame type including RMA and IGMP. * The bypass frame type is as following: * - BYPASS_BRG_GROUP, * - BYPASS_FD_PAUSE, @@ -414,7 +414,7 @@ rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable) * RT_ERR_SMI - SMI access error * RT_ERR_INPUT - Invalid input parameters. * Note: - * This API can get per-port bypass stomr filter control frame type including RMA and igmp. + * This API can get per-port bypass storm filter control frame type including RMA and IGMP. * The bypass frame type is as following: * - BYPASS_BRG_GROUP, * - BYPASS_FD_PAUSE, @@ -526,7 +526,7 @@ rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnabl /* Function Name: * rtk_rate_stormControlExtPortmask_set * Description: - * Set externsion storm control port mask + * Set extension storm control port mask * Input: * pPortmask - port mask * Output: @@ -562,7 +562,7 @@ rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask) /* Function Name: * rtk_rate_stormControlExtPortmask_get * Description: - * Set externsion storm control port mask + * Set extension storm control port mask * Input: * None * Output: @@ -598,10 +598,10 @@ rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask) /* Function Name: * rtk_rate_stormControlExtEnable_set * Description: - * Set externsion storm control state + * Set extension storm control state * Input: * stormType - storm group type - * enable - externsion storm control state + * enable - extension storm control state * Output: * None * Return: @@ -653,11 +653,11 @@ rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormTyp /* Function Name: * rtk_rate_stormControlExtEnable_get * Description: - * Get externsion storm control state + * Get extension storm control state * Input: * stormType - storm group type * Output: - * pEnable - externsion storm control state + * pEnable - extension storm control state * Return: * RT_ERR_OK * RT_ERR_FAILED @@ -707,10 +707,10 @@ rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormTyp /* Function Name: * rtk_rate_stormControlExtMeterIdx_set * Description: - * Set externsion storm control meter index + * Set extension storm control meter index * Input: * stormType - storm group type - * index - externsion storm control state + * index - extension storm control state * Output: * None * Return: @@ -762,10 +762,10 @@ rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormT /* Function Name: * rtk_rate_stormControlExtMeterIdx_get * Description: - * Get externsion storm control meter index + * Get extension storm control meter index * Input: * stormType - storm group type - * pIndex - externsion storm control state + * pIndex - extension storm control state * Output: * None * Return: diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c index bf4ef044d..067291526 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c @@ -41,7 +41,7 @@ rtk_svlan_lookupType_t svlan_lookupType; * RT_ERR_SMI - SMI access error * Note: * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. - * User can set mathced ether type as service provider supported protocol. + * User can set matched ether type as service provider supported protocol. */ rtk_api_ret_t rtk_svlan_init(void) { @@ -250,7 +250,7 @@ rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port) * RT_ERR_INPUT - Invalid input parameter. * Note: * Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design. - * User can set mathced ether type as service provider supported protocol. + * User can set matched ether type as service provider supported protocol. */ rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlan_tag_id) { @@ -391,8 +391,8 @@ rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef) * RT_ERR_PORT_MASK - Invalid portmask. * RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full. * Note: - * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted - * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup. + * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped by default setup. * - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration. * - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration. * - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration. @@ -626,8 +626,8 @@ rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted - * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped. */ rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg) { @@ -794,8 +794,8 @@ rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_member * RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted - * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped. + * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted + * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped. */ rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg) { @@ -948,7 +948,7 @@ rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid) * RT_ERR_INPUT - Invalid input parameters. * Note: * The API can set system C2S configuration. ASIC will check upstream's VID and assign related - * SVID to mathed packet. There are 128 SVLAN C2S configurations. + * SVID to matched packet. There are 128 SVLAN C2S configurations. */ rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid) { @@ -1011,7 +1011,7 @@ rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t } else { - /* New svidx, remove src_port and find a new slot to add a new enrty */ + /* New svidx, remove src_port and find a new slot to add a new entry */ pmsk = pmsk & ~(1 << phyPort); if(pmsk == 0) c2s_svidx = 0; @@ -1263,7 +1263,7 @@ rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vl * Note: * The API can Get action of downstream Un-Stag packet. A SVID assigned * to the un-stag is also retrieved by this API. The parameter pSvid is - * only refernced when the action is UNTAG_ASSIGN + * only referenced when the action is UNTAG_ASSIGN */ rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid) { @@ -1313,8 +1313,8 @@ rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_ * RT_ERR_INPUT - Invalid input parameters. * Note: * The API can configure action of downstream Un-match packet. A SVID assigned - * to the un-match is also supported by this API. The parameter od svid is - * only refernced when the action is set to UNMATCH_ASSIGN + * to the un-match is also supported by this API. The parameter of svid is + * only referenced when the action is set to UNMATCH_ASSIGN */ rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid) { @@ -1379,7 +1379,7 @@ rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rt * Note: * The API can Get action of downstream Un-match packet. A SVID assigned * to the un-match is also retrieved by this API. The parameter pSvid is - * only refernced when the action is UNMATCH_ASSIGN + * only referenced when the action is UNMATCH_ASSIGN */ rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid) { @@ -1567,7 +1567,7 @@ rtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable) * RT_ERR_OUT_OF_RANGE - input out of range. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast + * The API can set IP multicast to SVID configuration. If upstream packet is IPv4 multicast * packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet. * There are 32 SVLAN multicast configurations for IP and L2 multicast. */ @@ -1662,7 +1662,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk,rtk_vlan_t sv * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can delete IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk) { @@ -1714,7 +1714,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk) * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can get IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid) { @@ -1771,7 +1771,7 @@ rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t * * RT_ERR_OUT_OF_RANGE - input out of range. * RT_ERR_INPUT - Invalid input parameters. * Note: - * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast + * The API can set L2 Multicast to SVID configuration. If upstream packet is L2 multicast * packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32 * SVLAN multicast configurations for IP and L2 multicast. */ @@ -1868,7 +1868,7 @@ rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t s * RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can delete Multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk) { @@ -1924,7 +1924,7 @@ rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk) * RT_ERR_INPUT - Invalid input parameters. * RT_ERR_OUT_OF_RANGE - input out of range. * Note: - * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. + * The API can get L2 multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast. */ rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid) { diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c index f7480c490..b407c3008 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c @@ -106,7 +106,7 @@ rtk_api_ret_t rtk_vlan_init(void) return retVal; } - /* Updata Databse */ + /* Update Database */ vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN; vlan_mbrCfgVid[0] = 1; @@ -950,7 +950,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto { if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK) return retVal; - tmp = pInfo->frame_type; + tmp = (rtl8367c_provlan_frametype)pInfo->frame_type; if (ppb_data_cfg.etherType == pInfo->proto_type && ppb_data_cfg.frameType == tmp) { /*Already exist*/ @@ -976,7 +976,7 @@ rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_proto else if (emptyframe_type; + ppb_data_cfg.frameType = (rtl8367c_provlan_frametype)pInfo->frame_type; ppb_data_cfg.etherType = pInfo->proto_type; if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(empty, &ppb_data_cfg)) != RT_ERR_OK) return retVal; @@ -1267,7 +1267,7 @@ rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode) if (tag_mode >= VLAN_TAG_MODE_END) return RT_ERR_PORT_ID; - if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), tag_mode)) != RT_ERR_OK) + if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), (rtl8367c_egtagmode)tag_mode)) != RT_ERR_OK) return retVal; return RT_ERR_OK; @@ -1576,7 +1576,7 @@ rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg) * Set port-based filtering database * Input: * port - Port id. - * enable - ebable port-based FID + * enable - enable port-based FID * fid - Specified filtering database. * Output: * None @@ -1624,7 +1624,7 @@ rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid * Input: * port - Port id. * Output: - * pEnable - ebable port-based FID + * pEnable - enable port-based FID * pFid - Specified filtering database. * Return: * RT_ERR_OK - OK diff --git a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c index 08d2b57d4..b4d4554d4 100644 --- a/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c +++ b/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c @@ -211,7 +211,7 @@ void init_gsw(void) set_rtl8367s_rgmii(); } -// bleow are platform driver +// below are platform driver static const struct of_device_id rtk_gsw_match[] = { { .compatible = "mediatek,rtk-gsw" }, {}, @@ -258,7 +258,7 @@ static int rtk_gsw_probe(struct platform_device *pdev) init_gsw(); - //init default vlan or init swocnfig + //init default vlan or init swconfig if(!of_property_read_string(pdev->dev.of_node, "mediatek,port_map", &pm)) { diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index 52d761805..16d8617c5 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -6,33 +6,120 @@ board=$(board_name) board_config_update case $board in -abt,asr3000) - ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" +confiabits,mt7981) + ucidef_set_led_netdev "lan1" "lan1" "blue:lan-1" "lan1" "link tx rx" + ucidef_set_led_netdev "lan2" "lan2" "blue:lan-2" "lan2" "link tx rx" + ucidef_set_led_netdev "lan3" "lan3" "blue:lan-3" "lan3" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx" ;; -bananapi,bpi-r4) +bananapi,bpi-r3-mini) + ucidef_set_led_netdev "lan1" "LAN" "mdio-bus:0e:green:lan" "eth0" "link_2500 link_1000 tx rx" + ucidef_set_led_netdev "lan2" "LAN" "mdio-bus:0e:yellow:lan" "eth0" "link_2500 link_100 tx rx" + ucidef_set_led_netdev "wan1" "WAN" "mdio-bus:0f:green:wan" "eth1" "link_2500 link_1000 tx rx" + ucidef_set_led_netdev "wan2" "WAN" "mdio-bus:0f:yellow:wan" "eth1" "link_2500 link_100 tx rx" + ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan-1" "phy0-ap0" + ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0" + ;; +bananapi,bpi-r4|\ +bananapi,bpi-r4-poe) ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx" ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx" ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx" ucidef_set_led_netdev "lan3" "lan3" "mt7530-0:03:green:lan" "lan3" "link tx rx" ;; -hf,m7986r1*) - ucidef_set_led_netdev "led-1" "LAN1" "led-1" "lan1" - ucidef_set_led_netdev "led-2" "LAN2" "led-2" "lan2" - ucidef_set_led_netdev "led-3" "LAN3" "led-3" "lan3" - ucidef_set_led_netdev "led-4" "LAN4" "led-4" "lan4" - ucidef_set_led_netdev "led-5" "WWAN" "led-5" "usb0" +cudy,re3000-v1) + ucidef_set_led_netdev "lan" "lan" "green:lan" "eth0" "link tx rx" + ;; +cudy,wr3000-v1) + ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" + ;; +glinet,gl-x3000|\ +glinet,gl-xe3000) + ucidef_set_led_default "power" "POWER" "green:power" "1" + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" + ucidef_set_led_netdev "5g_1" "5G_1" "green:5g:led1" "wwan0" + ucidef_set_led_netdev "5g_2" "5G_2" "green:5g:led2" "wwan0" + ucidef_set_led_netdev "5g_3" "5G_3" "green:5g:led3" "wwan0" + ucidef_set_led_netdev "5g_4" "5G_4" "green:5g:led4" "wwan0" + ucidef_set_led_netdev "wlan2g" "WLAN2G" "green:wifi2g" "phy0-ap0" + ucidef_set_led_netdev "wlan5g" "WLAN5G" "green:wifi5g" "phy1-ap0" + ;; +mercusys,mr90x-v1) + ucidef_set_led_netdev "lan-0" "lan-0" "green:lan-0" "lan0" "link tx rx" + ucidef_set_led_netdev "lan-1" "lan-1" "green:lan-1" "lan1" "link tx rx" + ucidef_set_led_netdev "lan-2" "lan-2" "green:lan-2" "lan2" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "green:wan" "eth1" "link tx rx" + ;; +netgear,wax220) + ucidef_set_led_netdev "eth0" "LAN" "green:lan" "eth0" + ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0" + ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0" ;; -imou,lc-hx3001|\ nokia,ea0326gmp) - ucidef_set_led_netdev "lan" "LAN" "green:lan" "br-lan" - ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" "link" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "br-lan" "link" + ucidef_set_led_netdev "wlan" "WLAN" "green:wlan" "phy1-ap0" "link" ;; -xiaomi,mi-router-wr30u) - ucidef_set_led_netdev "wan" "wan" "blue:internet" "wan" +openembed,som7981) + ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx" + ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link" ;; -xiaomi,redmi-router-ax6000) +openwrt,one) + ucidef_set_led_netdev "wanact" "WANACT" "mdio-bus:0f:green:wan" "eth0" "rx tx" + ucidef_set_led_netdev "wanlink" "WANLINK" "mdio-bus:0f:amber:wan" "eth0" "link" + ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx" + ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link" + ;; +routerich,ax3000) + ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx" + ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx" + ucidef_set_led_netdev "lan-3" "lan-3" "blue:lan-3" "lan3" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx" + ucidef_set_led_netdev "wan-off" "wan-off" "red:wan" "wan" "link" + ;; +smartrg,sdg-8733|\ +smartrg,sdg-8734) + ucidef_set_led_netdev "lan-1-green" "LAN1" "mdio-bus:08:green:lan" "lan1" "link_2500 link_5000" + ucidef_set_led_netdev "lan-1-orange" "LAN1" "mdio-bus:08:orange:lan" "lan1" "link_100 link_1000" + ucidef_set_led_netdev "lan-1-white" "LAN1" "mdio-bus:08:white:lan" "lan1" "link_10000" + ucidef_set_led_netdev "lan-2-green" "LAN2" "mt7530-0:01:green:lan" "lan2" "link_1000" + ucidef_set_led_netdev "lan-2-amber" "LAN2" "mt7530-0:01:amber:lan" "lan2" "link_100 link_10" + ucidef_set_led_netdev "lan-3-green" "LAN3" "mt7530-0:02:green:lan" "lan3" "link_1000" + ucidef_set_led_netdev "lan-3-amber" "LAN3" "mt7530-0:02:amber:lan" "lan3" "link_100 link_10" + ucidef_set_led_netdev "lan-4-green" "LAN4" "mt7530-0:03:green:lan" "lan4" "link_1000" + ucidef_set_led_netdev "lan-4-amber" "LAN4" "mt7530-0:03:amber:lan" "lan4" "link_100 link_10" + ucidef_set_led_netdev "wan-green" "WAN" "mdio-bus:00:green:wan" "wan" "link_2500 link_5000" + ucidef_set_led_netdev "wan-orange" "WAN" "mdio-bus:00:orange:wan" "wan" "link_100 link_1000" + ucidef_set_led_netdev "wan-white" "WAN" "mdio-bus:00:white:wan" "wan" "link_10000" + ;; +wavlink,wl-wn586x3) + ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx" + ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "blue:wan" "eth1" "link tx rx" + ;; +tplink,re6000xd) + ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-0" "lan1" "link tx rx" + ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-1" "lan2" "link tx rx" + ucidef_set_led_netdev "eth1" "lan-3" "blue:lan-2" "eth1" "link tx rx" + ;; +xiaomi,mi-router-wr30u-stock|\ +xiaomi,mi-router-wr30u-ubootmod) + ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx" + ;; +xiaomi,redmi-router-ax6000-stock|\ +xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_led_netdev "wan" "wan" "rgb:network" "wan" ;; +zbtlink,zbt-z8103ax) + ucidef_set_led_netdev "wan" "wan" "green:wan" "eth1" "link tx rx" + ;; +zyxel_ex5601-t0-stock|\ +zyxel,ex5601-t0-ubootmod) + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" "link tx rx" + ucidef_set_led_netdev "wan" "WAN" "green:inet" "eth1" "link tx rx" + ucidef_set_led_netdev "wifi-24g" "WIFI-2.4G" "green:wifi24g" "phy0-ap0" "link tx rx" + ucidef_set_led_netdev "wifi-5g" "WIFI-5G" "green:wifi5g" "phy1-ap0" "link tx rx" + ;; esac board_config_flush diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 5586a6a8b..1a210810b 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -8,59 +8,113 @@ mediatek_setup_interfaces() local board="$1" case $board in - abt,asr3000|\ - cmcc,rax3000m*|\ - h3c,magic-nx30-pro|\ - imou,lc-hx3001|\ - nokia,ea0326gmp) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1 + acelink,ew-7886cax) + ucidef_set_interface_lan "eth0" "dhcp" + ;; + acer,predator-w6) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1 + ;; + asus,rt-ax59u|\ + cetron,ct3003|\ + confiabits,mt7981|\ + cudy,wr3000-v1|\ + jcg,q30-pro|\ + qihoo,360t7|\ + routerich,ax3000) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan ;; asus,tuf-ax4200|\ - jdcloud,re-cs-05|\ + jdcloud,re-cp-03|\ + mediatek,mt7981-rfb|\ netcore,n60|\ - ruijie,rg-x60-pro) + ruijie,rg-x60-pro|\ + unielec,u7981-01*|\ + zbtlink,zbt-z8102ax) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 ;; + asus,tuf-ax6000) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1 + ;; bananapi,bpi-r3) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan" ;; - bananapi,bpi-r4) + bananapi,bpi-r3-mini|\ + edgecore,eap111) + ucidef_set_interfaces_lan_wan eth0 eth1 + ;; + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 eth1" "wan eth2" ;; - cetron,ct3003*|\ - fzs,5gcpe-p3|\ - jcg,q30-pro|\ - qihoo,360t7) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan + cmcc,rax3000m|\ + h3c,magic-nx30-pro|\ + nokia,ea0326gmp|\ + zbtlink,zbt-z8103ax) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1 ;; - hf,m7986r1*) - ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" lan1 + comfast,cf-e393ax) + ucidef_set_interfaces_lan_wan "lan1" eth1 ;; + cudy,m3000-v1|\ + cudy,tr3000-v1|\ glinet,gl-mt2500|\ - glinet,gl-mt3000) + glinet,gl-mt3000|\ + glinet,gl-x3000|\ + glinet,gl-xe3000|\ + openembed,som7981|\ + openwrt,one) ucidef_set_interfaces_lan_wan eth1 eth0 ;; - mediatek,mt7986a-rfb|\ + dlink,aquila-pro-ai-m30-a1) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet + ;; + glinet,gl-mt6000|\ + tplink,tl-xdr4288|\ + tplink,tl-xdr6088) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1 + ;; + mediatek,mt7986a-rfb) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan6" "eth1 wan" + ;; mediatek,mt7986b-rfb) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1 ;; mediatek,mt7988a-rfb) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth1" eth2 ;; - glinet,gl-mt6000|\ - tplink,tl-xdr4288|\ - tplink,tl-xdr6088|\ - tplink,tl-xtr8488) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1 + mercusys,mr90x-v1) + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1 ;; - tplink,tl-xdr6086) + cudy,re3000-v1|\ + netgear,wax220|\ + ubnt,unifi-6-plus|\ + zyxel,nwa50ax-pro) + ucidef_set_interface_lan "eth0" + ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632|\ + yuncore,ax835) + ucidef_set_interfaces_lan_wan lan wan + ;; + tplink,tl-xdr6086|\ + wavlink,wl-wn586x3) ucidef_set_interfaces_lan_wan "lan1 lan2" eth1 ;; - xiaomi,mi-router-wr30u|\ + tplink,re6000xd) + ucidef_set_interface_lan "lan1 lan2 eth1" + ;; xiaomi,mi-router-ax3000t|\ - xiaomi,redmi-router-ax6000) + xiaomi,mi-router-ax3000t-ubootmod|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,mi-router-wr30u-ubootmod|\ + xiaomi,redmi-router-ax6000-stock|\ + xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan ;; + zyxel,ex5601-t0-stock|\ + zyxel,ex5601-t0-ubootmod) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 + ;; *) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan ;; @@ -75,50 +129,32 @@ mediatek_setup_macs() local label_mac="" case $board in - asus,tuf-ax4200) - CI_UBIPART="UBI_DEV" - addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) - wan_mac="${addr}" - lan_mac="${addr}" - ;; bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4) wan_mac=$(macaddr_add $(cat /sys/class/net/eth0/address) 1) ;; - cmcc,rax3000m-emmc) - wan_mac=$(mmc_get_mac_binary factory 0x2a) - lan_mac=$(mmc_get_mac_binary factory 0x24) - label_mac=$wan_mac + cmcc,rax3000m) + case "$(cmdline_get_var root)" in + /dev/mmc*) + wan_mac=$(mmc_get_mac_binary factory 0x2a) + lan_mac=$(mmc_get_mac_binary factory 0x24) + label_mac=$wan_mac ;; - cmcc,rax3000m-nand) - wan_mac=$(mtd_get_mac_binary factory 0x2a) - lan_mac=$(mtd_get_mac_binary factory 0x24) - label_mac=$lan_mac - ;; - glinet,gl-mt2500) - label_mac="$(get_mac_binary "/dev/mmcblk0boot1" 0xa)" - wan_mac="$label_mac" - lan_mac="$(macaddr_add $label_mac 1)" - ;; - glinet,gl-mt6000) - label_mac=$(mmc_get_mac_binary factory 0x0a) - wan_mac=$label_mac - lan_mac=$(macaddr_add "$label_mac" 2) + esac ;; h3c,magic-nx30-pro) wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr) lan_mac=$(macaddr_add "$wan_mac" 1) label_mac=$wan_mac ;; - imou,lc-hx3001) - lan_mac=$(mtd_get_mac_ascii u-boot-env mac) - wan_mac=$(macaddr_add "$lan_mac" 2) - label_mac=$lan_mac + mercusys,mr90x-v1|\ + tplink,re6000xd) + label_mac=$(get_mac_binary "/tmp/tp_data/default-mac" 0) + lan_mac=$label_mac ;; - jdcloud,re-cs-05) - wan_mac=$(mmc_get_mac_binary factory 0x24) - lan_mac=$(mmc_get_mac_binary factory 0x2a) + netgear,wax220) + lan_mac=$(mtd_get_mac_ascii u-boot-env mac) label_mac=$lan_mac ;; qihoo,360t7) @@ -131,12 +167,28 @@ mediatek_setup_macs() wan_mac=$label_mac lan_mac=$(macaddr_add "$label_mac" 1) ;; - xiaomi,mi-router-wr30u|\ + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632|\ + smartrg,sdg-8733|\ + smartrg,sdg-8734) + label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC) + wan_mac=$label_mac + lan_mac=$(macaddr_add "$label_mac" 1) + ;; xiaomi,mi-router-ax3000t|\ - xiaomi,redmi-router-ax6000) + xiaomi,mi-router-ax3000t-ubootmod|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,mi-router-wr30u-ubootmod|\ + xiaomi,redmi-router-ax6000-stock|\ + xiaomi,redmi-router-ax6000-ubootmod) wan_mac=$(mtd_get_mac_ascii Bdata ethaddr_wan) label_mac=$wan_mac ;; + yuncore,ax835) + label_mac=$(mtd_get_mac_binary "Factory" 0x4) + ;; esac [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches b/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches new file mode 100644 index 000000000..4cbec1ef0 --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/03_gpio_switches @@ -0,0 +1,19 @@ +. /lib/functions/uci-defaults.sh + +board_config_update + +board=$(board_name) + +case "$board" in +zbtlink,zbt-z8102ax) + ucidef_add_gpio_switch "5g1" "Power 1st modem" "5g1" "1" + ucidef_add_gpio_switch "5g2" "Power 2nd modem" "5g2" "1" + ucidef_add_gpio_switch "pcie" "Power PCIe port" "pcie" "1" + ucidef_add_gpio_switch "sim1" "SIM 1" "sim1" "1" + ucidef_add_gpio_switch "sim2" "SIM 2" "sim2" "1" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version index e0e1a8ecc..d0cfd8f0a 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version @@ -6,7 +6,7 @@ board_config_update case "$(board_name)" in bananapi,bpi-r3) - ucidef_set_compat_version "1.1" + ucidef_set_compat_version "1.2" ;; esac diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index 742abc5f4..920a16d05 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -7,25 +7,53 @@ board=$(board_name) case "$FIRMWARE" in +"mediatek/mt7915_eeprom.bin") + case "$board" in + smartrg,sdg-8622) + caldata_extract_mmc "factory" 0xa0000 0x1000 + ;; + esac + ;; +"mediatek/mt7916_eeprom.bin") + case "$board" in + acer,predator-w6|\ + smartrg,sdg-8632) + caldata_extract_mmc "factory" 0xa0000 0x1000 + ;; + esac + ;; "mediatek/mt7981_eeprom_mt7976_dbdc.bin") case "$board" in - cmcc,rax3000m-emmc) + cmcc,rax3000m) + case "$(cmdline_get_var root)" in + /dev/mmc*) + caldata_extract_mmc "factory" 0x0 0x1000 + ;; + esac + ;; + ubnt,unifi-6-plus) caldata_extract_mmc "factory" 0x0 0x1000 ;; esac ;; -"mediatek/mt7986_eeprom_mt7976_dbdc.bin") +"mediatek/mt7986_eeprom_mt7975_dual.bin") case "$board" in - asus,tuf-ax4200) - CI_UBIPART="UBI_DEV" - caldata_extract_ubi "Factory" 0x0 0x1000 + mercusys,mr90x-v1|\ + tplink,re6000xd) + ln -sf /tmp/tp_data/MT7986_EEPROM.bin \ + /lib/firmware/$FIRMWARE + ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632) + caldata_extract_mmc "factory" 0x0 0x1000 ;; esac ;; -"mediatek/mt7986_eeprom_mt7976_dual.bin") +"mediatek/mt7986_eeprom_mt7976.bin") case "$board" in - glinet,gl-mt6000|\ - jdcloud,re-cs-05) + acer,predator-w6) caldata_extract_mmc "factory" 0x0 0x1000 ;; esac diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index a1e86697f..942facee8 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -10,12 +10,24 @@ PHYNBR=${DEVPATH##*/phy} board=$(board_name) case "$board" in - abt,asr3000) - addr=$(mtd_get_mac_binary "art" 0x6) - [ "$PHYNBR" = "1" ] && \ - macaddr_setbit_la "$(macaddr_add $addr 0x600000)" > /sys${DEVPATH}/macaddress + acer,predator-w6) + key_path="/var/qcidata/data" + [ "$PHYNBR" = "0" ] && cat $key_path/2gMAC > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && cat $key_path/6gMAC > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "2" ] && cat $key_path/5gMAC > /sys${DEVPATH}/macaddress ;; - asus,tuf-ax4200) + asus,rt-ax59u) + CI_UBIPART="UBI_DEV" + addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) + # Originally, phy1 is phy0 mac with LA and 28th bits set. However, this would conflict + # addresses on multiple VIFs with the other radio when bit 28 is already set. + # Set LA and 28 bits and increment mac-address instead. + [ "$PHYNBR" = "1" ] && \ + macaddr_setbit_la $(macaddr_setbit $(macaddr_add $addr 1) 28) > \ + /sys${DEVPATH}/macaddress + ;; + asus,tuf-ax4200|\ + asus,tuf-ax6000) CI_UBIPART="UBI_DEV" addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) # Originally, phy0 is phy1 mac with LA bit set. However, this would conflict @@ -24,23 +36,61 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress ;; - bananapi,bpi-r3) + bananapi,bpi-r3|\ + bananapi,bpi-r3-mini) addr=$(cat /sys/class/net/eth0/address) [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; - bananapi,bpi-r4) + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe) addr=$(cat /sys/class/net/eth0/address) [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress ;; - cetron,ct3003*) + cetron,ct3003) addr=$(mtd_get_mac_binary "art" 0) [ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 2) > /sys${DEVPATH}/macaddress ;; - glinet,gl-mt6000) + cmcc,rax3000m) + case "$(cmdline_get_var root)" in + /dev/mmc*) + addr=$(mmc_get_mac_binary factory 0xa) + ;; + *) + addr=$(mtd_get_mac_binary factory 0xa) + ;; + esac + [ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress + ;; + comfast,cf-e393ax) + addr=$(mtd_get_mac_binary "Factory" 0x8000) + [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress + ;; + cudy,tr3000-v1|\ + cudy,re3000-v1) + addr=$(mtd_get_mac_binary bdinfo 0xde00) + [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress + ;; + cudy,m3000-v1|\ + cudy,wr3000-v1) + addr=$(mtd_get_mac_binary bdinfo 0xde00) + # Originally, phy0 is phy1 mac with LA bit set. However, this would conflict + # addresses on multiple VIFs with the other radio. Set LA bit and increment + # mac-address instead. + [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress + ;; + dlink,aquila-pro-ai-m30-a1) + addr=$(mtd_get_mac_binary "Odm" 0x81) + [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress + ;; + glinet,gl-mt6000|\ + glinet,gl-x3000|\ + glinet,gl-xe3000) addr=$(mmc_get_mac_binary factory 0x04) [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress @@ -50,21 +100,34 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; - imou,lc-hx3001) - addr=$(mtd_get_mac_ascii u-boot-env mac) - [ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress - [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress - ;; jcg,q30-pro|\ netcore,n60) # Originally, phy1 is phy0 mac with LA bit set. However, this would conflict # addresses on multiple VIFs with the other radio. Use label mac to set LA bit. [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(get_mac_label) > /sys${DEVPATH}/macaddress ;; + jdcloud,re-cp-03) + [ "$PHYNBR" = "1" ] && mmc_get_mac_binary factory 0xa > /sys${DEVPATH}/macaddress + ;; + mercusys,mr90x-v1|\ + tplink,re6000xd) + addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0) + [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr -1 > /sys${DEVPATH}/macaddress + ;; + netgear,wax220) + hw_mac_addr=$(mtd_get_mac_ascii u-boot-env mac) + [ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 3 > /sys${DEVPATH}/macaddress + ;; nokia,ea0326gmp) - addr=$(mtd_get_mac_binary Factory 0x28) + addr=$(cat /sys/class/net/eth0/address) + [ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress ;; + openembed,som7981) + [ "$PHYNBR" = "1" ] && cat /sys/class/net/eth0/address > /sys${DEVPATH}/macaddress + ;; qihoo,360t7) addr=$(mtd_get_mac_ascii factory lanMac) [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress @@ -75,12 +138,43 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress + ;; + smartrg,sdg-8733|\ + smartrg,sdg-8634) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + [ "$PHYNBR" = "0" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr a > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "2" ] && macaddr_add $addr 6 > /sys${DEVPATH}/macaddress + ;; tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088) - [ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "0" ] && get_mac_label > /sys${DEVPATH}/macaddress ;; - tplink,tl-xtr8488) - [ "$PHYNBR" = "2" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress + ubnt,unifi-6-plus) + addr=$(mtd_get_mac_binary EEPROM 0x6) + [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress + ;; + routerich,ax3000|\ + zbtlink,zbt-z8102ax|\ + zbtlink,zbt-z8103ax|\ + zyxel,ex5601-t0|\ + zyxel,ex5601-t0-ubootmod) + addr=$(mtd_get_mac_binary "Factory" 0x4) + [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress + ;; + zyxel,nwa50ax-pro) + hw_mac_addr="$(mtd_get_mac_binary mrd 0x1fff8)" + [ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress ;; esac diff --git a/target/linux/mediatek/filogic/base-files/etc/init.d/bootcount b/target/linux/mediatek/filogic/base-files/etc/init.d/bootcount new file mode 100755 index 000000000..e186589f2 --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/etc/init.d/bootcount @@ -0,0 +1,19 @@ +#!/bin/sh /etc/rc.common +# SPDX-License-Identifier: GPL-2.0-only + +START=99 + +boot() { + case $(board_name) in + dlink,aquila-pro-ai-m30-a1) + if grep -q bootpart=ubi0 /proc/cmdline; then + fw_setenv bootpart 0 + else + fw_setenv bootpart 1 + fi + ;; + zyxel,ex5700-telenor) + fw_setenv uboot_bootcount 0 + ;; + esac +} diff --git a/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version index 4486f2f09..f39d2575e 100644 --- a/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version +++ b/target/linux/mediatek/filogic/base-files/etc/uci-defaults/05_fix-compat-version @@ -2,7 +2,7 @@ case "$(board_name)" in bananapi,bpi-r3) - uci set system.@system[0].compat_version="1.1" + uci set system.@system[0].compat_version="1.2" uci commit system ;; esac diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label b/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label new file mode 100644 index 000000000..110e023b9 --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label @@ -0,0 +1,15 @@ +set_netdev_labels() { + local dir + local label + local netdev + + for dir in /sys/class/net/*; do + [ -r "$dir/of_node/label" ] || continue + read -r label < "$dir/of_node/label" + netdev="${dir##*/}" + [ "$netdev" = "$label" ] && continue + ip link set "$netdev" name "$label" + done +} + +boot_hook_add preinit_main set_netdev_labels diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh new file mode 100644 index 000000000..87287a7d1 --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh @@ -0,0 +1,25 @@ +. /lib/functions/system.sh + +predator_w6_factory_extract() { + local mmc_part + + mmc_part="$(find_mmc_part qcidata)" + + mkdir -p /var/qcidata/data + mkdir -p /var/qcidata/mount + + mount -r "$mmc_part" /var/qcidata/mount + + cp /var/qcidata/mount/factory/*MAC "/var/qcidata/data/" + umount "/var/qcidata/mount" +} + +preinit_extract_factory() { + case $(board_name) in + acer,predator-w6) + predator_w6_factory_extract + ;; + esac +} + +boot_hook_add preinit_main preinit_extract_factory diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part b/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part new file mode 100644 index 000000000..11e3b598a --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part @@ -0,0 +1,24 @@ +. /lib/functions/system.sh + +mount_ubi_part() { + local part_name="$1" + local mtd_num=$(grep $part_name /proc/mtd | cut -c4) + local ubi_num=$(ubiattach -m $mtd_num | \ + awk -F',' '/UBI device number [0-9]{1,}/{print $1}' | \ + awk '{print $4}') + mkdir /tmp/$part_name + mount -r -t ubifs ubi$ubi_num:$part_name /tmp/$part_name +} + +preinit_mount_cfg_part() { + case $(board_name) in + mercusys,mr90x-v1|\ + tplink,re6000xd) + mount_ubi_part "tp_data" + ;; + *) + ;; + esac +} + +boot_hook_add preinit_main preinit_mount_cfg_part diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh index ec078741c..fefca2327 100644 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh @@ -2,12 +2,47 @@ preinit_set_mac_address() { case $(board_name) in - asus,tuf-ax4200) + acer,predator-w6) + key_path="/var/qcidata/data" + ip link set dev lan1 address "$(cat $key_path/LANMAC)" + ip link set dev lan2 address "$(cat $key_path/LANMAC)" + ip link set dev lan3 address "$(cat $key_path/LANMAC)" + ip link set dev game address "$(cat $key_path/LANMAC)" + ip link set dev eth1 address "$(cat $key_path/WANMAC)" + ;; + asus,tuf-ax4200|\ + asus,tuf-ax6000) CI_UBIPART="UBI_DEV" addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) ip link set dev eth0 address "$addr" ip link set dev eth1 address "$addr" ;; + mercusys,mr90x-v1|\ + tplink,re6000xd) + addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0) + ip link set dev eth1 address "$(macaddr_add $addr 1)" + ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8733|\ + smartrg,sdg-8734) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + lan_addr=$(macaddr_add $addr 1) + ip link set dev wan address "$addr" + ip link set dev eth0 address "$lan_addr" + ip link set dev lan1 address "$lan_addr" + ip link set dev lan2 address "$lan_addr" + ip link set dev lan3 address "$lan_addr" + ip link set dev lan4 address "$lan_addr" + ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + ip link set dev wan address "$addr" + ip link set dev lan address "$(macaddr_add $addr 1)" + ;; + *) + ;; esac } diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/75_rootfs_prepare b/target/linux/mediatek/filogic/base-files/lib/preinit/75_rootfs_prepare new file mode 100644 index 000000000..0a32073e0 --- /dev/null +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/75_rootfs_prepare @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + +rootfs_create() { + local blocks + + blocks=$(cat /sys/class/ubi/ubi0/avail_eraseblocks) + [ -z "$blocks" ] && { + echo "Failed to read amount of available erase blocks" >&2 + return + } + + # Delete after getting available blocks: Make sure enough space is + # left to recreate these volumes. + ubirmvol /dev/ubi0 -N kernel_backup + ubirmvol /dev/ubi0 -N rootfs_backup + + # Use 90% of remaining flash size for "rootfs_data" + ubimkvol /dev/ubi0 -n 20 -N rootfs_data --lebs $((blocks / 100 * 90)) + mknod -m 0600 /dev/ubi0_20 c 250 21 +} + +rootfs_prepare() { + case $(board_name) in + netgear,wax220) + if ! ubinfo /dev/ubi0 -N rootfs_data &>/dev/null; then + echo "Creating \"rootfs_data\" UBI volume" + rootfs_create + fi + ;; + *) + ;; + esac +} + +boot_hook_add preinit_main rootfs_prepare diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom b/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom deleted file mode 100644 index ee36ffe7c..000000000 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom +++ /dev/null @@ -1,23 +0,0 @@ -. /lib/functions/caldata.sh - -preinit_fix_eeprom() { - case $(board_name) in - glinet,gl-mt6000|\ - jdcloud,re-cs-05) - mmc_part=$(find_mmc_part factory) - FIRMWARE="mediatek/mt7986_eeprom_mt7976_dual.bin" - [ ! -e /lib/firmware/"$FIRMWARE" ] && \ - export FIRMWARE="$FIRMWARE" && \ - caldata_extract_mmc "factory" 0x0 0x1000 - ;; - mercusys,mr90x-v1) - eeprom="/lib/firmware/mediatek/mt7986_eeprom_mt7975_dual.bin" - [ ! -e $eeprom ] && \ - ln -sf /tmp/tp_data/MT7986_EEPROM.bin $eeprom - ;; - *) - ;; - esac -} - -boot_hook_add preinit_main preinit_fix_eeprom diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index e87b2e17c..2fed8a0ab 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -1,4 +1,5 @@ REQUIRE_IMAGE_METADATA=1 +RAMFS_COPY_BIN='fitblk' asus_initial_setup() { @@ -11,28 +12,93 @@ asus_initial_setup() ubimkvol /dev/ubi0 -N jffs2 -s 0x3e000 } +xiaomi_initial_setup() +{ + # initialize UBI and setup uboot-env if it's running on initramfs + [ "$(rootfs_type)" = "tmpfs" ] || return 0 + + local mtdnum="$( find_mtd_index ubi )" + if [ ! "$mtdnum" ]; then + echo "unable to find mtd partition ubi" + return 1 + fi + + local kern_mtdnum="$( find_mtd_index ubi_kernel )" + if [ ! "$kern_mtdnum" ]; then + echo "unable to find mtd partition ubi_kernel" + return 1 + fi + + ubidetach -m "$mtdnum" + ubiformat /dev/mtd$mtdnum -y + + ubidetach -m "$kern_mtdnum" + ubiformat /dev/mtd$kern_mtdnum -y + + if ! fw_printenv -n flag_try_sys2_failed &>/dev/null; then + echo "failed to access u-boot-env. skip env setup." + return 0 + fi + + fw_setenv boot_wait on + fw_setenv uart_en 1 + fw_setenv flag_boot_rootfs 0 + fw_setenv flag_last_success 1 + fw_setenv flag_boot_success 1 + fw_setenv flag_try_sys1_failed 8 + fw_setenv flag_try_sys2_failed 8 + + local board=$(board_name) + case "$board" in + xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-wr30u-stock) + fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),34816k(ubi),34816k(ubi1),32768k(overlay),12288k(data),256k(KF)" + ;; + xiaomi,redmi-router-ax6000-stock) + fw_setenv mtdparts "nmbm0:1024k(bl2),256k(Nvram),256k(Bdata),2048k(factory),2048k(fip),256k(crash),256k(crash_log),30720k(ubi),30720k(ubi1),51200k(overlay)" + ;; + esac +} + platform_do_upgrade() { local board=$(board_name) case "$board" in - asus,tuf-ax4200) + acer,predator-w6|\ + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632|\ + smartrg,sdg-8733|\ + smartrg,sdg-8734) + CI_KERNPART="kernel" + CI_ROOTPART="rootfs" + emmc_do_upgrade "$1" + ;; + asus,rt-ax59u|\ + asus,tuf-ax4200|\ + asus,tuf-ax6000) CI_UBIPART="UBI_DEV" CI_KERNPART="linux" nand_do_upgrade "$1" ;; bananapi,bpi-r3|\ - bananapi,bpi-r4) - local rootdev="$(cmdline_get_var root)" - rootdev="${rootdev##*/}" - rootdev="${rootdev%p[0-9]*}" - case "$rootdev" in - mmc*) - CI_ROOTDEV="$rootdev" - CI_KERNPART="production" + bananapi,bpi-r3-mini|\ + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe|\ + jdcloud,re-cp-03|\ + mediatek,mt7988a-rfb|\ + openwrt,one) + [ -e /dev/fit0 ] && fitblk /dev/fit0 + [ -e /dev/fitrw ] && fitblk /dev/fitrw + bootdev="$(fitblk_get_bootdev)" + case "$bootdev" in + mmcblk*) + EMMC_KERN_DEV="/dev/$bootdev" emmc_do_upgrade "$1" ;; mtdblock*) - PART_NAME="fit" + PART_NAME="/dev/mtd${bootdev:8}" default_do_upgrade "$1" ;; ubiblock*) @@ -41,14 +107,90 @@ platform_do_upgrade() { ;; esac ;; - cmcc,rax3000m-emmc|\ + cmcc,rax3000m) + case "$(cmdline_get_var root)" in + /dev/mmc*) + CI_KERNPART="production" + emmc_do_upgrade "$1" + ;; + *) + CI_KERNPART="fit" + nand_do_upgrade "$1" + ;; + esac + ;; + cudy,re3000-v1|\ + cudy,wr3000-v1|\ + yuncore,ax835) + default_do_upgrade "$1" + ;; glinet,gl-mt2500|\ glinet,gl-mt6000|\ - jdcloud,re-cs-05) + glinet,gl-x3000|\ + glinet,gl-xe3000) CI_KERNPART="kernel" CI_ROOTPART="rootfs" emmc_do_upgrade "$1" ;; + h3c,magic-nx30-pro|\ + jcg,q30-pro|\ + mediatek,mt7981-rfb|\ + netcore,n60|\ + qihoo,360t7|\ + xiaomi,mi-router-ax3000t-ubootmod|\ + xiaomi,mi-router-wr30u-ubootmod) + CI_KERNPART="fit" + nand_do_upgrade "$1" + ;; + mercusys,mr90x-v1|\ + tplink,re6000xd) + CI_UBIPART="ubi0" + nand_do_upgrade "$1" + ;; + nokia,ea0326gmp|\ + tplink,tl-xdr4288|\ + tplink,tl-xdr6086|\ + tplink,tl-xdr6088|\ + xiaomi,redmi-router-ax6000-ubootmod) + [ -e /dev/fit0 ] && fitblk /dev/fit0 + [ -e /dev/fitrw ] && fitblk /dev/fitrw + CI_KERNPART="fit" + nand_do_upgrade "$1" + ;; + ubnt,unifi-6-plus) + CI_KERNPART="kernel0" + EMMC_ROOT_DEV="$(cmdline_get_var root)" + emmc_do_upgrade "$1" + ;; + xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,redmi-router-ax6000-stock) + CI_KERN_UBIPART=ubi_kernel + CI_ROOT_UBIPART=ubi + nand_do_upgrade "$1" + ;; + zyxel,ex5601-t0-ubootmod) + CI_KERNPART="fit" + CI_ROOTPART="ubi_rootfs" + nand_do_upgrade "$1" + ;; + unielec,u7981-01*) + local rootdev="$(cmdline_get_var root)" + rootdev="${rootdev##*/}" + rootdev="${rootdev%p[0-9]*}" + case "$rootdev" in + mmc*) + CI_ROOTDEV="$rootdev" + CI_KERNPART="kernel" + CI_ROOTPART="rootfs" + emmc_do_upgrade "$1" + ;; + *) + CI_KERNPART="fit" + nand_do_upgrade "$1" + ;; + esac + ;; *) nand_do_upgrade "$1" ;; @@ -65,7 +207,10 @@ platform_check_image() { case "$board" in bananapi,bpi-r3|\ - bananapi,bpi-r4) + bananapi,bpi-r3-mini|\ + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe|\ + cmcc,rax3000m) [ "$magic" != "d00dfeed" ] && { echo "Invalid image type." return 1 @@ -74,7 +219,7 @@ platform_check_image() { ;; *) nand_do_platform_check "$board" "$1" - return 0 + return $? ;; esac @@ -83,35 +228,54 @@ platform_check_image() { platform_copy_config() { case "$(board_name)" in - bananapi,bpi-r3) + cmcc,rax3000m) case "$(cmdline_get_var root)" in /dev/mmc*) emmc_copy_config ;; esac ;; - bananapi,bpi-r4) - case "$(platform_get_bootdev)" in + bananapi,bpi-r3|\ + bananapi,bpi-r3-mini|\ + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe) + case "$(fitblk_get_bootdev)" in mmcblk*) emmc_copy_config ;; esac ;; - cmcc,rax3000m-emmc|\ + acer,predator-w6|\ glinet,gl-mt2500|\ glinet,gl-mt6000|\ - jdcloud,re-cs-05) + glinet,gl-x3000|\ + glinet,gl-xe3000|\ + jdcloud,re-cp-03|\ + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632|\ + smartrg,sdg-8733|\ + smartrg,sdg-8734|\ + ubnt,unifi-6-plus) emmc_copy_config ;; esac - } - +} + platform_pre_upgrade() { local board=$(board_name) case "$board" in - asus,tuf-ax4200) + asus,rt-ax59u|\ + asus,tuf-ax4200|\ + asus,tuf-ax6000) asus_initial_setup ;; + xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,redmi-router-ax6000-stock) + xiaomi_initial_setup + ;; esac } diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15 deleted file mode 100644 index c8af636c2..000000000 --- a/target/linux/mediatek/filogic/config-5.15 +++ /dev/null @@ -1,442 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2712 is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7981=y -CONFIG_COMMON_CLK_MT7981_ETHSYS=y -CONFIG_COMMON_CLK_MT7986=y -CONFIG_COMMON_CLK_MT7986_ETHSYS=y -CONFIG_COMMON_CLK_MT7988=y -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_2P5G_PHY=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_GE_SOC_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_EFUSE=y -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_USXGMII=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -# CONFIG_PCIE_MEDIATEK is not set -CONFIG_PCIE_MEDIATEK_GEN3=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -CONFIG_PHY_MTK_XSPHY=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6797 is not set -# CONFIG_PINCTRL_MT7622 is not set -CONFIG_PINCTRL_MT7981=y -CONFIG_PINCTRL_MT7986=y -CONFIG_PINCTRL_MT7988=y -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_REGULATOR_RT5190A=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_TI_SYSCON=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1 deleted file mode 100644 index 36cb9c1e4..000000000 --- a/target/linux/mediatek/filogic/config-6.1 +++ /dev/null @@ -1,473 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2712 is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7981=y -CONFIG_COMMON_CLK_MT7981_ETHSYS=y -CONFIG_COMMON_CLK_MT7986=y -CONFIG_COMMON_CLK_MT7986_ETHSYS=y -CONFIG_COMMON_CLK_MT7988=y -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_2P5G_PHY=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_GE_SOC_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_USXGMII=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_MTK_EFUSE=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -# CONFIG_PCIE_MEDIATEK is not set -CONFIG_PCIE_MEDIATEK_GEN3=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -CONFIG_PHY_MTK_XSPHY=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -# CONFIG_PINCTRL_MT7622 is not set -CONFIG_PINCTRL_MT7981=y -CONFIG_PINCTRL_MT7986=y -CONFIG_PINCTRL_MT7988=y -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -# CONFIG_PINCTRL_MT8516 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POLYNOMIAL=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_REGULATOR_RT5190A=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_TI_SYSCON=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPI_MTK_SNFI=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/filogic/config-6.6 b/target/linux/mediatek/filogic/config-6.6 index f6c8ec6d9..6d9d42853 100644 --- a/target/linux/mediatek/filogic/config-6.6 +++ b/target/linux/mediatek/filogic/config-6.6 @@ -48,7 +48,6 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_NVMEM=y CONFIG_BLK_PM=y CONFIG_BLOCK_NOTIFIERS=y CONFIG_BSD_PROCESS_ACCT=y diff --git a/target/linux/mediatek/filogic/target.mk b/target/linux/mediatek/filogic/target.mk index 4e5cde3d6..d1637e06a 100644 --- a/target/linux/mediatek/filogic/target.mk +++ b/target/linux/mediatek/filogic/target.mk @@ -2,7 +2,7 @@ ARCH:=aarch64 SUBTARGET:=filogic BOARDNAME:=Filogic 8x0 (MT798x) CPU_TYPE:=cortex-a53 -DEFAULT_PACKAGES += kmod-crypto-hw-safexcel kmod-mt7915e wpad-openssl uboot-envtools +DEFAULT_PACKAGES += fitblk kmod-phy-aquantia kmod-crypto-hw-safexcel wpad-basic-mbedtls uboot-envtools KERNELNAME:=Image dtbs define Target/Description diff --git a/target/linux/mediatek/image/Makefile b/target/linux/mediatek/image/Makefile index 97164428e..d4f79ec97 100644 --- a/target/linux/mediatek/image/Makefile +++ b/target/linux/mediatek/image/Makefile @@ -6,6 +6,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk +DEVICE_VARS += NETGEAR_ENC_MODEL NETGEAR_ENC_REGION NETGEAR_ENC_HW_ID_LIST NETGEAR_ENC_MODEL_LIST + loadaddr-$(CONFIG_TARGET_mediatek_mt7622) := 0x44000000 loadaddr-$(CONFIG_TARGET_mediatek_mt7623) := 0x80008000 loadaddr-$(CONFIG_TARGET_mediatek_mt7629) := 0x40008000 @@ -22,6 +24,10 @@ define Device/Default KERNEL_LOADADDR = $(loadaddr-y) FILESYSTEMS := squashfs DEVICE_DTS_DIR := $(DTS_DIR) + NETGEAR_ENC_MODEL := + NETGEAR_ENC_REGION := + NETGEAR_ENC_HW_ID_LIST := + NETGEAR_ENC_MODEL_LIST := IMAGES := sysupgrade.bin IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | \ pad-rootfs | append-metadata diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index d5eb8b811..94b3098b3 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -52,6 +52,44 @@ define Build/mt798x-gpt rm $@.tmp endef +metadata_gl_json = \ + '{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \ + "metadata_version": "1.1", \ + "compat_version": "$(call json_quote,$(compat_version))", \ + $(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \ + $(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \ + [$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \ + "supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \ + $(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \ + "version": { \ + "release": "$(call json_quote,$(VERSION_NUMBER))", \ + "date": "$(shell TZ='Asia/Chongqing' date '+%Y%m%d%H%M%S')", \ + "dist": "$(call json_quote,$(VERSION_DIST))", \ + "version": "$(call json_quote,$(VERSION_NUMBER))", \ + "revision": "$(call json_quote,$(REVISION))", \ + "target": "$(call json_quote,$(TARGETID))", \ + "board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \ + } \ + }' + +define Build/append-gl-metadata + $(if $(SUPPORTED_DEVICES),-echo $(call metadata_gl_json,$(SUPPORTED_DEVICES)) | fwtool -I - $@) + sha256sum "$@" | cut -d" " -f1 > "$@.sha256sum" + [ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \ + cp "$(BUILD_KEY).ucert" "$@.ucert" ;\ + usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\ + ucert -A -c "$@.ucert" -x "$@.sig" ;\ + fwtool -S "$@.ucert" "$@" ;\ + } +endef + +define Build/zyxel-nwa-fit-filogic + $(TOPDIR)/scripts/mkits-zyxel-fit-filogic.sh \ + $@.its $@ "80 e1 ff ff ff ff ff ff ff ff" + PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new + @mv $@.new $@ +endef + define Build/cetron-header $(eval magic=$(word 1,$(1))) $(eval model=$(word 2,$(1))) @@ -67,19 +105,102 @@ define Build/cetron-header rm $@.tmp endef -define Device/abt_asr3000 - DEVICE_VENDOR := ABT - DEVICE_MODEL := ASR3000 - DEVICE_DTS := mt7981b-abt-asr3000 +define Device/acelink_ew-7886cax + DEVICE_VENDOR := Acelink + DEVICE_MODEL := EW-7886CAX + DEVICE_DTS := mt7986a-acelink-ew-7886cax DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 + IMAGE_SIZE := 65536k KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef -TARGET_DEVICES += abt_asr3000 +TARGET_DEVICES += acelink_ew-7886cax + +define Device/acer_predator-w6 + DEVICE_VENDOR := Acer + DEVICE_MODEL := Predator W6 + DEVICE_DTS := mt7986a-acer-predator-w6 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7916-firmware kmod-mt7986-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs + IMAGES := sysupgrade.bin + KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += acer_predator-w6 + +define Device/adtran_smartrg + DEVICE_VENDOR := Adtran + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-hwmon-pwmfan + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +define Device/smartrg_sdg-8612 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8612 + DEVICE_DTS := mt7986a-smartrg-SDG-8612 + DEVICE_PACKAGES += kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware +endef +TARGET_DEVICES += smartrg_sdg-8612 + +define Device/smartrg_sdg-8614 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8614 + DEVICE_DTS := mt7986a-smartrg-SDG-8614 + DEVICE_PACKAGES += kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware +endef +TARGET_DEVICES += smartrg_sdg-8614 + +define Device/smartrg_sdg-8622 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8622 + DEVICE_DTS := mt7986a-smartrg-SDG-8622 + DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware +endef +TARGET_DEVICES += smartrg_sdg-8622 + +define Device/smartrg_sdg-8632 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8632 + DEVICE_DTS := mt7986a-smartrg-SDG-8632 + DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware +endef +TARGET_DEVICES += smartrg_sdg-8632 + +define Device/smartrg_sdg-8733 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8733 + DEVICE_DTS := mt7988a-smartrg-SDG-8733 + DEVICE_PACKAGES += kmod-mt7996-firmware kmod-phy-aquantia kmod-usb3 +endef +TARGET_DEVICES += smartrg_sdg-8733 + +define Device/smartrg_sdg-8734 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8734 + DEVICE_DTS := mt7988a-smartrg-SDG-8734 + DEVICE_PACKAGES += kmod-mt7996-firmware kmod-phy-aquantia kmod-sfp kmod-usb3 +endef +TARGET_DEVICES += smartrg_sdg-8734 + +define Device/asus_rt-ax59u + DEVICE_VENDOR := ASUS + DEVICE_MODEL := RT-AX59U + DEVICE_DTS := mt7986a-asus-rt-ax59u + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += asus_rt-ax59u define Device/asus_tuf-ax4200 DEVICE_VENDOR := ASUS @@ -87,7 +208,7 @@ define Device/asus_tuf-ax4200 DEVICE_DTS := mt7986a-asus-tuf-ax4200 DEVICE_DTS_DIR := ../dts DEVICE_DTS_LOADADDR := 0x47000000 - DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware + DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware IMAGES := sysupgrade.bin KERNEL := kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb @@ -97,14 +218,34 @@ define Device/asus_tuf-ax4200 endef TARGET_DEVICES += asus_tuf-ax4200 +define Device/asus_tuf-ax6000 + DEVICE_VENDOR := ASUS + DEVICE_MODEL := TUF-AX6000 + DEVICE_DTS := mt7986a-asus-tuf-ax6000 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + IMAGES := sysupgrade.bin + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += asus_tuf-ax6000 + define Device/bananapi_bpi-r3 DEVICE_VENDOR := Bananapi DEVICE_MODEL := BPi-R3 DEVICE_DTS := mt7986a-bananapi-bpi-r3 DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3 - DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-emmc mt7986a-bananapi-bpi-r3-nand mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-sd + DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-emmc mt7986a-bananapi-bpi-r3-nand \ + mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-sd \ + mt7986a-bananapi-bpi-r3-respeaker-2mics DEVICE_DTS_DIR := $(DTS_DIR)/ - DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7915e kmod-mt7986-firmware kmod-sfp kmod-usb3 \ + e2fsprogs f2fsck mkf2fs mt7986-wo-firmware IMAGES := sysupgrade.itb KERNEL_LOADADDR := 0x44000000 KERNEL_INITRAMFS_SUFFIX := -recovery.itb @@ -117,7 +258,7 @@ define Device/bananapi_bpi-r3 ARTIFACT/emmc-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-emmc ARTIFACT/nor-preloader.bin := mt7986-bl2 nor-ddr4 ARTIFACT/nor-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-nor - ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ddr4 + ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ubi-ddr4 ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-snand ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ pad-to 17k | mt7986-bl2 sdmmc-ddr4 |\ @@ -125,7 +266,7 @@ define Device/bananapi_bpi-r3 $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\ ) \ - pad-to 44M | mt7986-bl2 spim-nand-ddr4 |\ + pad-to 44M | mt7986-bl2 spim-nand-ubi-ddr4 |\ pad-to 45M | mt7986-bl31-uboot bananapi_bpi-r3-snand |\ pad-to 49M | mt7986-bl2 nor-ddr4 |\ pad-to 50M | mt7986-bl31-uboot bananapi_bpi-r3-nor |\ @@ -136,17 +277,64 @@ define Device/bananapi_bpi-r3 pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\ ) \ gzip +ifeq ($(DUMP),) IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m +endif KERNEL := kernel-bin | gzip KERNEL_INITRAMFS := kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata DEVICE_DTC_FLAGS := --pad 4096 - DEVICE_COMPAT_VERSION := 1.1 - DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update + DEVICE_COMPAT_VERSION := 1.2 + DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update endef TARGET_DEVICES += bananapi_bpi-r3 +define Device/bananapi_bpi-r3-mini + DEVICE_VENDOR := Bananapi + DEVICE_MODEL := BPi-R3 Mini + DEVICE_DTS := mt7986a-bananapi-bpi-r3-mini + DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3-mini + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7915e kmod-mt7986-firmware kmod-phy-airoha-en8811h \ + kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware + KERNEL_LOADADDR := 0x44000000 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := snand-factory.bin sysupgrade.itb +ifeq ($(DUMP),) + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m +endif + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \ + pad-rootfs | append-metadata + ARTIFACTS := \ + emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \ + snand-factory.bin snand-preloader.bin snand-bl31-uboot.fip + ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc + ARTIFACT/emmc-preloader.bin := mt7986-bl2 emmc-ddr4 + ARTIFACT/emmc-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-mini-emmc + ARTIFACT/snand-factory.bin := mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \ + mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \ + mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \ + mt7986-bl2 spim-nand-ubi-ddr4 | pad-to 2048k | \ + ubinize-image fit squashfs-sysupgrade.itb + ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ubi-ddr4 + ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-mini-snand + UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7986_bananapi_bpi-r3-mini-snand-u-boot.fip +ifneq ($(CONFIG_PACKAGE_airoha-en8811h-firmware),) + UBINIZE_PARTS += en8811h-fw=:$(STAGING_DIR_IMAGE)/EthMD32.bin +endif +endef +TARGET_DEVICES += bananapi_bpi-r3-mini + define Device/bananapi_bpi-r4-common DEVICE_VENDOR := Bananapi DEVICE_DTS_DIR := $(DTS_DIR)/ @@ -196,13 +384,22 @@ define Device/bananapi_bpi-r4 endef TARGET_DEVICES += bananapi_bpi-r4 +define Device/bananapi_bpi-r4-poe + DEVICE_MODEL := BPi-R4 2.5GE + DEVICE_DTS := mt7988a-bananapi-bpi-r4-poe + DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4-poe + $(call Device/bananapi_bpi-r4-common) + DEVICE_PACKAGES += mt7988-2p5g-phy-firmware +endef +TARGET_DEVICES += bananapi_bpi-r4-poe + define Device/cetron_ct3003 DEVICE_VENDOR := Cetron DEVICE_MODEL := CT3003 DEVICE_DTS := mt7981b-cetron-ct3003 DEVICE_DTS_DIR := ../dts SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 @@ -213,78 +410,199 @@ define Device/cetron_ct3003 endef TARGET_DEVICES += cetron_ct3003 -define Device/cetron_ct3003-mod - DEVICE_VENDOR := Cetron - DEVICE_MODEL := CT3003 (U-Boot mod) - DEVICE_DTS := mt7981b-cetron-ct3003-mod - DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - KERNEL_IN_UBI := 1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += cetron_ct3003-mod - -define Device/cmcc_rax3000m-emmc +define Device/cmcc_rax3000m DEVICE_VENDOR := CMCC - DEVICE_MODEL := RAX3000M (eMMC version) - DEVICE_DTS := mt7981b-cmcc-rax3000m-emmc + DEVICE_MODEL := RAX3000M + DEVICE_DTS := mt7981b-cmcc-rax3000m + DEVICE_DTS_OVERLAY := mt7981b-cmcc-rax3000m-emmc mt7981b-cmcc-rax3000m-nand DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 \ - automount f2fsck mkf2fs - KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 \ + e2fsprogs f2fsck mkf2fs + KERNEL_LOADADDR := 0x44000000 + KERNEL := kernel-bin | gzip KERNEL_INITRAMFS := kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \ + pad-rootfs | append-metadata + ARTIFACTS := \ + emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \ + nand-preloader.bin nand-bl31-uboot.fip + ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc + ARTIFACT/emmc-preloader.bin := mt7981-bl2 emmc-ddr4 + ARTIFACT/emmc-bl31-uboot.fip := mt7981-bl31-uboot cmcc_rax3000m-emmc + ARTIFACT/nand-preloader.bin := mt7981-bl2 spim-nand-ddr4 + ARTIFACT/nand-bl31-uboot.fip := mt7981-bl31-uboot cmcc_rax3000m-nand endef -TARGET_DEVICES += cmcc_rax3000m-emmc +TARGET_DEVICES += cmcc_rax3000m -define Device/cmcc_rax3000m-nand - DEVICE_VENDOR := CMCC - DEVICE_MODEL := RAX3000M (NAND version) - DEVICE_DTS := mt7981b-cmcc-rax3000m-nand +define Device/comfast_cf-e393ax + DEVICE_VENDOR := Comfast + DEVICE_MODEL := CF-E393AX + DEVICE_DTS := mt7981a-comfast-cf-e393ax DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 automount + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + KERNEL_LOADADDR := 0x44000000 + KERNEL = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 - IMAGE_SIZE := 116736k + IMAGE_SIZE := 65536k KERNEL_IN_UBI := 1 - IMAGES += factory.bin + IMAGES := sysupgrade.bin factory.bin IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata - KERNEL = kernel-bin | lzma | \ - fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb - KERNEL_INITRAMFS = kernel-bin | lzma | \ - fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd endef -TARGET_DEVICES += cmcc_rax3000m-nand +TARGET_DEVICES += comfast_cf-e393ax -define Device/fzs_5gcpe-p3 - DEVICE_VENDOR := FZS - DEVICE_MODEL := 5GCPE P3 - DEVICE_DTS := mt7981b-fzs-5gcpe-p3 +define Device/confiabits_mt7981 + DEVICE_VENDOR := Confiabits + DEVICE_MODEL := MT7981 + DEVICE_DTS := mt7981b-confiabits-mt7981 DEVICE_DTS_DIR := ../dts + SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-2500wan-gmac2-rfb UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 + IMAGE_SIZE := 65536k KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware endef -TARGET_DEVICES += fzs_5gcpe-p3 +TARGET_DEVICES += confiabits_mt7981 + +define Device/cudy_m3000-v1 + DEVICE_VENDOR := Cudy + DEVICE_MODEL := M3000 + DEVICE_VARIANT := v1 + DEVICE_DTS := mt7981b-cudy-m3000-v1 + DEVICE_DTS_DIR := ../dts + SUPPORTED_DEVICES += R37 + DEVICE_DTS_LOADADDR := 0x44000000 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += cudy_m3000-v1 + +define Device/cudy_re3000-v1 + DEVICE_VENDOR := Cudy + DEVICE_MODEL := RE3000 + DEVICE_VARIANT := v1 + DEVICE_DTS := mt7981b-cudy-re3000-v1 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + IMAGES := sysupgrade.bin + IMAGE_SIZE := 15424k + SUPPORTED_DEVICES += R36 + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += cudy_re3000-v1 + +define Device/cudy_tr3000-v1 + DEVICE_VENDOR := Cudy + DEVICE_MODEL := TR3000 + DEVICE_VARIANT := v1 + DEVICE_DTS := mt7981b-cudy-tr3000-v1 + DEVICE_DTS_DIR := ../dts + SUPPORTED_DEVICES += R47 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += cudy_tr3000-v1 + +define Device/cudy_wr3000-v1 + DEVICE_VENDOR := Cudy + DEVICE_MODEL := WR3000 + DEVICE_VARIANT := v1 + DEVICE_DTS := mt7981b-cudy-wr3000-v1 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + IMAGES := sysupgrade.bin + IMAGE_SIZE := 15424k + SUPPORTED_DEVICES += R31 + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += cudy_wr3000-v1 + +define Device/dlink_aquila-pro-ai-m30-a1 + DEVICE_VENDOR := D-Link + DEVICE_MODEL := AQUILA PRO AI M30 + DEVICE_VARIANT := A1 + DEVICE_DTS := mt7981b-dlink-aquila-pro-ai-m30-a1 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-leds-gca230718 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + KERNEL_IN_UBI := 1 + IMAGES += recovery.bin + IMAGE_SIZE := 51200k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/recovery.bin := sysupgrade-tar | pad-to $$(IMAGE_SIZE) | dlink-ai-recovery-header DLK6E6110001 \x6A\x28\xEE\x0B \x00\x00\x2C\x00 \x00\x00\x20\x03 \x61\x6E +endef +TARGET_DEVICES += dlink_aquila-pro-ai-m30-a1 + +define Device/edgecore_eap111 + DEVICE_VENDOR := Edgecore + DEVICE_MODEL := EAP111 + DEVICE_DTS := mt7981a-edgecore-eap111 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_OPTS := -E 5 + KERNEL_IN_UBI := 1 + IMAGE_SIZE := 65536k + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += edgecore_eap111 define Device/glinet_gl-mt2500 DEVICE_VENDOR := GL.iNet DEVICE_MODEL := GL-MT2500 DEVICE_DTS := mt7981b-glinet-gl-mt2500 DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 + DEVICE_DTS_LOADADDR := 0x47000000 + DEVICE_PACKAGES := -wpad-basic-mbedtls e2fsprogs f2fsck mkf2fs kmod-usb3 SUPPORTED_DEVICES += glinet,mt2500-emmc IMAGES := sysupgrade.bin - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata endef TARGET_DEVICES += glinet_gl-mt2500 @@ -293,12 +611,14 @@ define Device/glinet_gl-mt3000 DEVICE_MODEL := GL-MT3000 DEVICE_DTS := mt7981b-glinet-gl-mt3000 DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3 + SUPPORTED_DEVICES += glinet,mt3000-snand + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3 UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 + IMAGE_SIZE := 246272k KERNEL_IN_UBI := 1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata endef TARGET_DEVICES += glinet_gl-mt3000 @@ -307,15 +627,41 @@ define Device/glinet_gl-mt6000 DEVICE_MODEL := GL-MT6000 DEVICE_DTS := mt7986a-glinet-gl-mt6000 DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGES := sysupgrade.bin - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + IMAGES += factory.bin + IMAGE/factory.bin := append-kernel | pad-to 32M | append-rootfs + IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 emmc-ddr4 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot glinet_gl-mt6000 endef TARGET_DEVICES += glinet_gl-mt6000 +define Device/glinet_gl-x3000-xe3000-common + DEVICE_VENDOR := GL.iNet + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware mkf2fs \ + kmod-fs-f2fs kmod-hwmon-pwmfan kmod-usb3 kmod-usb-serial-option \ + kmod-usb-storage kmod-usb-net-qmi-wwan uqmi + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +define Device/glinet_gl-x3000 + DEVICE_MODEL := GL-X3000 + DEVICE_DTS := mt7981a-glinet-gl-x3000 + SUPPORTED_DEVICES := glinet,gl-x3000 + $(call Device/glinet_gl-x3000-xe3000-common) +endef +TARGET_DEVICES += glinet_gl-x3000 + +define Device/glinet_gl-xe3000 + DEVICE_MODEL := GL-XE3000 + DEVICE_DTS := mt7981a-glinet-gl-xe3000 + SUPPORTED_DEVICES := glinet,gl-xe3000 + $(call Device/glinet_gl-x3000-xe3000-common) +endef +TARGET_DEVICES += glinet_gl-xe3000 + define Device/h3c_magic-nx30-pro DEVICE_VENDOR := H3C DEVICE_MODEL := Magic NX30 Pro @@ -325,26 +671,22 @@ define Device/h3c_magic-nx30-pro BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 IMAGE_SIZE := 65536k - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot h3c_magic-nx30-pro endef TARGET_DEVICES += h3c_magic-nx30-pro -define Device/imou_lc-hx3001 - DEVICE_VENDOR := IMOU - DEVICE_MODEL := LC-HX3001 - DEVICE_DTS := mt7981b-imou-lc-hx3001 - DEVICE_DTS_DIR := ../dts - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += imou_lc-hx3001 - define Device/jcg_q30-pro DEVICE_VENDOR := JCG DEVICE_MODEL := Q30 PRO @@ -354,27 +696,109 @@ define Device/jcg_q30-pro BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot jcg_q30-pro endef TARGET_DEVICES += jcg_q30-pro -define Device/jdcloud_re-cs-05 +define Device/jdcloud_re-cp-03 DEVICE_VENDOR := JDCloud - DEVICE_MODEL := AX6000 - DEVICE_DTS := mt7986a-jdcloud-re-cs-05 + DEVICE_MODEL := RE-CP-03 + DEVICE_DTS := mt7986a-jdcloud-re-cp-03 DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-mt7986-firmware mt7986-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware \ + e2fsprogs f2fsck mkf2fs + KERNEL_LOADADDR := 0x44000000 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + IMAGES := sysupgrade.itb + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | \ + pad-rootfs | append-metadata + ARTIFACTS :=gpt.bin preloader.bin bl31-uboot.fip + ARTIFACT/gpt.bin := mt798x-gpt emmc + ARTIFACT/preloader.bin := mt7986-bl2 emmc-ddr4 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot jdcloud_re-cp-03 endef -TARGET_DEVICES += jdcloud_re-cs-05 +TARGET_DEVICES += jdcloud_re-cp-03 -define Device/mediatek_mt7986a-rfb +define Device/mediatek_mt7981-rfb DEVICE_VENDOR := MediaTek - DEVICE_MODEL := MTK7986 rfba AP + DEVICE_MODEL := MT7981 rfb + DEVICE_DTS := mt7981-rfb + DEVICE_DTS_OVERLAY:= \ + mt7981-rfb-spim-nand \ + mt7981-rfb-mxl-2p5g-phy-eth1 \ + mt7981-rfb-mxl-2p5g-phy-swp5 + DEVICE_DTS_DIR := $(DTS_DIR)/ + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware + KERNEL_LOADADDR := 0x44000000 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + KERNEL_INITRAMFS_SUFFIX := .itb + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m + IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := \ + emmc-preloader.bin emmc-bl31-uboot.fip \ + nor-preloader.bin nor-bl31-uboot.fip \ + sdcard.img.gz \ + snfi-nand-preloader.bin snfi-nand-bl31-uboot.fip \ + spim-nand-preloader.bin spim-nand-bl31-uboot.fip + ARTIFACT/emmc-preloader.bin := mt7981-bl2 emmc-ddr3 + ARTIFACT/emmc-bl31-uboot.fip := mt7981-bl31-uboot rfb-emmc + ARTIFACT/nor-preloader.bin := mt7981-bl2 nor-ddr3 + ARTIFACT/nor-bl31-uboot.fip := mt7981-bl31-uboot rfb-emmc + ARTIFACT/snfi-nand-preloader.bin := mt7981-bl2 snand-ddr3 + ARTIFACT/snfi-nand-bl31-uboot.fip := mt7981-bl31-uboot rfb-snfi + ARTIFACT/spim-nand-preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/spim-nand-bl31-uboot.fip := mt7981-bl31-uboot rfb-spim-nand + ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ + pad-to 17k | mt7981-bl2 sdmmc-ddr3 |\ + pad-to 6656k | mt7981-bl31-uboot rfb-sd |\ + $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ + pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\ + ) \ + pad-to 44M | mt7981-bl2 spim-nand-ddr3 |\ + pad-to 45M | mt7981-bl31-uboot rfb-spim-nand |\ + pad-to 49M | mt7981-bl2 nor-ddr3 |\ + pad-to 50M | mt7981-bl31-uboot rfb-nor |\ + pad-to 51M | mt7981-bl2 snand-ddr3 |\ + pad-to 53M | mt7981-bl31-uboot rfb-snfi |\ + $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ + pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\ + ) \ + gzip +endef +TARGET_DEVICES += mediatek_mt7981-rfb + +define Device/mediatek_mt7986a-rfb-nand + DEVICE_VENDOR := MediaTek + DEVICE_MODEL := MT7986 rfba AP (NAND) DEVICE_DTS := mt7986a-rfb-spim-nand DEVICE_DTS_DIR := $(DTS_DIR)/ - SUPPORTED_DEVICES := mediatek,mt7986a-rfb + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 @@ -388,14 +812,14 @@ define Device/mediatek_mt7986a-rfb KERNEL_INITRAMFS = kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd endef -TARGET_DEVICES += mediatek_mt7986a-rfb +TARGET_DEVICES += mediatek_mt7986a-rfb-nand define Device/mediatek_mt7986b-rfb DEVICE_VENDOR := MediaTek DEVICE_MODEL := MTK7986 rfbb AP DEVICE_DTS := mt7986b-rfb DEVICE_DTS_DIR := $(DTS_DIR)/ - DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware SUPPORTED_DEVICES := mediatek,mt7986b-rfb UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k @@ -417,6 +841,7 @@ define Device/mediatek_mt7988a-rfb mt7988a-rfb-sd \ mt7988a-rfb-snfi-nand \ mt7988a-rfb-spim-nand \ + mt7988a-rfb-spim-nand-factory \ mt7988a-rfb-spim-nor \ mt7988a-rfb-eth1-aqr \ mt7988a-rfb-eth1-i2p5g-phy \ @@ -428,7 +853,7 @@ define Device/mediatek_mt7988a-rfb DEVICE_DTS_DIR := $(DTS_DIR)/ DEVICE_DTC_FLAGS := --pad 4096 DEVICE_DTS_LOADADDR := 0x45f00000 - DEVICE_PACKAGES := kmod-sfp + DEVICE_PACKAGES := mt7988-2p5g-phy-firmware kmod-sfp KERNEL_LOADADDR := 0x46000000 KERNEL := kernel-bin | gzip KERNEL_INITRAMFS := kernel-bin | lzma | \ @@ -448,7 +873,7 @@ define Device/mediatek_mt7988a-rfb ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot rfb-emmc ARTIFACT/nor-preloader.bin := mt7988-bl2 nor-comb ARTIFACT/nor-bl31-uboot.fip := mt7988-bl31-uboot rfb-nor - ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-comb + ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-ubi-comb ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot rfb-snand ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ pad-to 17k | mt7988-bl2 sdmmc-comb |\ @@ -470,21 +895,19 @@ define Device/mediatek_mt7988a-rfb endef TARGET_DEVICES += mediatek_mt7988a-rfb -define Device/hf_m7986r1-nand - DEVICE_VENDOR := HF - DEVICE_MODEL := M7986R1 - DEVICE_DTS := mt7986a-hf-m7986r1-nand +define Device/mercusys_mr90x-v1 + DEVICE_VENDOR := MERCUSYS + DEVICE_MODEL := MR90X v1 + DEVICE_DTS := mt7986b-mercusys-mr90x-v1 DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 - IMAGE_SIZE := 116736k - KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-usb3 kmod-mt7921e kmod-usb-serial-option kmod-usb-net-rndis - SUPPORTED_DEVICES += HF-M7986R1 + IMAGE_SIZE := 51200k IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef -TARGET_DEVICES +=hf_m7986r1-nand +TARGET_DEVICES += mercusys_mr90x-v1 define Device/netcore_n60 DEVICE_VENDOR := Netcore @@ -495,25 +918,128 @@ define Device/netcore_n60 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot netcore_n60 endef TARGET_DEVICES += netcore_n60 +define Device/netgear_wax220 + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := WAX220 + DEVICE_DTS := mt7986b-netgear-wax220 + DEVICE_DTS_DIR := ../dts + NETGEAR_ENC_MODEL := WAX220 + NETGEAR_ENC_REGION := US + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + IMAGE_SIZE := 32768k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGES += factory.img + # Padding to 10M seems to be required by OEM web interface + IMAGE/factory.img := sysupgrade-tar | \ + pad-to 10M | check-size | netgear-encrypted-factory +endef +TARGET_DEVICES += netgear_wax220 + define Device/nokia_ea0326gmp DEVICE_VENDOR := Nokia DEVICE_MODEL := EA0326GMP DEVICE_DTS := mt7981b-nokia-ea0326gmp DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot nokia_ea0326gmp endef TARGET_DEVICES += nokia_ea0326gmp +define Device/openembed_som7981 + DEVICE_VENDOR := OpenEmbed + DEVICE_MODEL := SOM7981 + DEVICE_DTS := mt7981b-openembed-som7981 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 244224k + KERNEL_IN_UBI := 1 + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += openembed_som7981 + +define Build/append-openwrt-one-eeprom + dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@ +endef + +define Device/openwrt_one + DEVICE_VENDOR := OpenWrt + DEVICE_MODEL := One + DEVICE_DTS := mt7981b-openwrt-one + DEVICE_DTS_DIR := ../dts + DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x43f00000 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-rtc-pcf8563 kmod-usb3 kmod-nvme kmod-phy-airoha-en8811h + KERNEL_LOADADDR := 0x44000000 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + KERNEL_INITRAMFS_SUFFIX := .itb + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m + IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := \ + nor-preloader.bin nor-bl31-uboot.fip \ + snand-preloader.bin snand-bl31-uboot.fip \ + factory.ubi snand-factory.bin nor-factory.bin + ARTIFACT/nor-preloader.bin := mt7981-bl2 nor-ddr4 + ARTIFACT/nor-bl31-uboot.fip := mt7981-bl31-uboot openwrt_one-nor + ARTIFACT/snand-preloader.bin := mt7981-bl2 spim-nand-ubi-ddr4 + ARTIFACT/snand-bl31-uboot.fip := mt7981-bl31-uboot openwrt_one-snand + ARTIFACT/factory.ubi := ubinize-image fit squashfs-sysupgrade.itb + ARTIFACT/snand-factory.bin := mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \ + mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \ + mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \ + mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 1024k | \ + ubinize-image fit squashfs-sysupgrade.itb + ARTIFACT/nor-factory.bin := mt7981-bl2 nor-ddr4 | pad-to 256k | \ + append-openwrt-one-eeprom | pad-to 1024k | \ + mt7981-bl31-uboot openwrt_one-nor | pad-to 512k | \ + append-image-stage initramfs.itb + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7981_openwrt_one-snand-u-boot.fip recovery=:$(KDIR)/tmp/openwrt-mediatek-filogic-openwrt_one-initramfs.itb \ + $(if $(wildcard $(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb), calibration=:$(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb) +endef +TARGET_DEVICES += openwrt_one + define Device/qihoo_360t7 DEVICE_VENDOR := Qihoo DEVICE_MODEL := 360T7 @@ -523,99 +1049,411 @@ define Device/qihoo_360t7 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot qihoo_360t7 endef TARGET_DEVICES += qihoo_360t7 +define Device/routerich_ax3000 + DEVICE_VENDOR := Routerich + DEVICE_MODEL := AX3000 + DEVICE_DTS := mt7981b-routerich-ax3000 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb +endef +TARGET_DEVICES += routerich_ax3000 + define Device/ruijie_rg-x60-pro DEVICE_VENDOR := Ruijie DEVICE_MODEL := RG-X60 Pro DEVICE_DTS := mt7986a-ruijie-rg-x60-pro DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef TARGET_DEVICES += ruijie_rg-x60-pro -define Device/tplink_tl-common +define Device/tplink_re6000xd + DEVICE_VENDOR := TP-Link + DEVICE_MODEL := RE6000XD + DEVICE_DTS := mt7986b-tplink-re6000xd + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 51200k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += tplink_re6000xd + +define Device/tplink_tl-xdr-common DEVICE_VENDOR := TP-Link DEVICE_DTS_DIR := ../dts UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata + DEVICE_PACKAGES := fitblk kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3 endef define Device/tplink_tl-xdr4288 DEVICE_MODEL := TL-XDR4288 DEVICE_DTS := mt7986a-tplink-tl-xdr4288 - $(call Device/tplink_tl-common) + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr4288 + $(call Device/tplink_tl-xdr-common) endef TARGET_DEVICES += tplink_tl-xdr4288 define Device/tplink_tl-xdr6086 DEVICE_MODEL := TL-XDR6086 DEVICE_DTS := mt7986a-tplink-tl-xdr6086 - $(call Device/tplink_tl-common) + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr6086 + $(call Device/tplink_tl-xdr-common) endef TARGET_DEVICES += tplink_tl-xdr6086 define Device/tplink_tl-xdr6088 DEVICE_MODEL := TL-XDR6088 DEVICE_DTS := mt7986a-tplink-tl-xdr6088 - $(call Device/tplink_tl-common) + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr6088 + $(call Device/tplink_tl-xdr-common) endef TARGET_DEVICES += tplink_tl-xdr6088 -define Device/tplink_tl-xtr8488 - DEVICE_MODEL := TL-XTR8488 - DEVICE_DTS := mt7986a-tplink-tl-xtr8488 - DEVICE_PACKAGES += kmod-mt7915-firmware - $(call Device/tplink_tl-common) +define Device/ubnt_unifi-6-plus + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 Plus + DEVICE_DTS := mt7981a-ubnt-unifi-6-plus + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware e2fsprogs f2fsck mkf2fs fdisk partx-utils + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef -TARGET_DEVICES += tplink_tl-xtr8488 +TARGET_DEVICES += ubnt_unifi-6-plus + +define Device/unielec_u7981-01 + DEVICE_VENDOR := Unielec + DEVICE_MODEL := U7981-01 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs fdisk partx-utils + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +define Device/unielec_u7981-01-emmc + DEVICE_DTS := mt7981b-unielec-u7981-01-emmc + DEVICE_VARIANT := (EMMC) + $(call Device/unielec_u7981-01) +endef +TARGET_DEVICES += unielec_u7981-01-emmc + +define Device/unielec_u7981-01-nand + DEVICE_DTS := mt7981b-unielec-u7981-01-nand + DEVICE_VARIANT := (NAND) + $(call Device/unielec_u7981-01) +endef +TARGET_DEVICES += unielec_u7981-01-nand + +define Device/wavlink_wl-wn586x3 + DEVICE_VENDOR := WAVLINK + DEVICE_MODEL := WL-WN586X3 + DEVICE_DTS := mt7981b-wavlink-wl-wn586x3 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + IMAGE_SIZE := 15424k + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += wavlink_wl-wn586x3 define Device/xiaomi_mi-router-ax3000t DEVICE_VENDOR := Xiaomi DEVICE_MODEL := Mi Router AX3000T - DEVICE_DTS := mt7981b-xiaomi-ax3000t + DEVICE_DTS := mt7981b-xiaomi-mi-router-ax3000t DEVICE_DTS_DIR := ../dts UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 - KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS := initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel +endif IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef TARGET_DEVICES += xiaomi_mi-router-ax3000t -define Device/xiaomi_mi-router-wr30u +define Device/xiaomi_mi-router-ax3000t-ubootmod DEVICE_VENDOR := Xiaomi - DEVICE_MODEL := Mi Router WR30U - DEVICE_DTS := mt7981b-xiaomi-wr30u + DEVICE_MODEL := Mi Router AX3000T (OpenWrt U-Boot layout) + DEVICE_DTS := mt7981b-xiaomi-mi-router-ax3000t-ubootmod DEVICE_DTS_DIR := ../dts UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware KERNEL_IN_UBI := 1 - DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot xiaomi_mi-router-ax3000t +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif endef -TARGET_DEVICES += xiaomi_mi-router-wr30u +TARGET_DEVICES += xiaomi_mi-router-ax3000t-ubootmod -define Device/xiaomi_redmi-router-ax6000 +define Device/xiaomi_mi-router-wr30u-stock DEVICE_VENDOR := Xiaomi - DEVICE_MODEL := Redmi Router AX6000 - DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000 + DEVICE_MODEL := Mi Router WR30U (stock layout) + DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-stock DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS := initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel +endif + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += xiaomi_mi-router-wr30u-stock + +define Device/xiaomi_mi-router-wr30u-ubootmod + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Mi Router WR30U (OpenWrt U-Boot layout) + DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-ubootmod + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3 + ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot xiaomi_mi-router-wr30u +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif +endef +TARGET_DEVICES += xiaomi_mi-router-wr30u-ubootmod + +define Device/xiaomi_redmi-router-ax6000-stock + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Redmi Router AX6000 (stock layout) + DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-stock + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS := initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel +endif + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += xiaomi_redmi-router-ax6000-stock + +define Device/xiaomi_redmi-router-ax6000-ubootmod + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Redmi Router AX6000 (OpenWrt U-Boot layout) + DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + IMAGES := sysupgrade.itb UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | \ + fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr4 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot xiaomi_redmi-router-ax6000 +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif +endef +TARGET_DEVICES += xiaomi_redmi-router-ax6000-ubootmod + +define Device/yuncore_ax835 + DEVICE_VENDOR := YunCore + DEVICE_MODEL := AX835 + DEVICE_DTS := mt7981b-yuncore-ax835 + DEVICE_DTS_DIR := ../dts + DEVICE_DTS_LOADADDR := 0x47000000 + IMAGES := sysupgrade.bin + IMAGE_SIZE := 14336k + SUPPORTED_DEVICES += mediatek,mt7981-spim-nor-rfb + KERNEL := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware +endef +TARGET_DEVICES += yuncore_ax835 + + +define Device/zbtlink_zbt-z8102ax + DEVICE_VENDOR := Zbtlink + DEVICE_MODEL := ZBT-Z8102AX + DEVICE_DTS := mt7981b-zbtlink-zbt-z8102ax + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option + KERNEL_IN_UBI := 1 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$(IMAGE_SIZE) IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef -TARGET_DEVICES += xiaomi_redmi-router-ax6000 +TARGET_DEVICES += zbtlink_zbt-z8102ax + +define Device/zbtlink_zbt-z8103ax + DEVICE_VENDOR := Zbtlink + DEVICE_MODEL := ZBT-Z8103AX + DEVICE_DTS := mt7981b-zbtlink-zbt-z8103ax + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + KERNEL_IN_UBI := 1 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += zbtlink_zbt-z8103ax + +define Device/zyxel_ex5601-t0-stock + DEVICE_VENDOR := Zyxel + DEVICE_MODEL := EX5601-T0 + DEVICE_VARIANT := (stock layout) + DEVICE_DTS := mt7986a-zyxel-ex5601-t0-stock + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3 + SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 256k + PAGESIZE := 4096 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + KERNEL = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd +endef +TARGET_DEVICES += zyxel_ex5601-t0-stock + +define Device/zyxel_ex5601-t0-ubootmod + DEVICE_VENDOR := Zyxel + DEVICE_MODEL := EX5601-T0 + DEVICE_VARIANT := (OpenWrt U-Boot layout) + DEVICE_DTS := mt7986a-zyxel-ex5601-t0-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3 + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + IMAGES := sysupgrade.itb + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 256k + PAGESIZE := 4096 + KERNEL_IN_UBI := 1 + UBOOTENV_IN_UBI := 1 + KERNEL := kernel-bin | lzma + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd + IMAGE/sysupgrade.itb := append-kernel | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-4k-ddr4 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot zyxel_ex5601-t0 +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + ARTIFACTS += initramfs-factory.ubi + ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel +endif +endef +TARGET_DEVICES += zyxel_ex5601-t0-ubootmod + +define Device/zyxel_ex5700-telenor + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := EX5700 (Telenor) + DEVICE_DTS := mt7986a-zyxel-ex5700-telenor + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-ubootenv-nvram kmod-usb3 kmod-mt7915e kmod-mt7916-firmware kmod-mt7986-firmware mt7986-wo-firmware + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += zyxel_ex5700-telenor + +define Device/zyxel_nwa50ax-pro + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := NWA50AX Pro + DEVICE_DTS := mt7981b-zyxel-nwa50ax-pro + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig + DEVICE_DTS_LOADADDR := 0x44000000 + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 51200k + KERNEL_IN_UBI := 1 + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) | zyxel-nwa-fit-filogic + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += zyxel_nwa50ax-pro diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 3bd8bcb15..f91720479 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -1,27 +1,13 @@ DTS_DIR := $(DTS_DIR)/mediatek +DEVICE_VARS += BUFFALO_TRX_MAGIC + define Image/Prepare # For UBI we want only one extra block rm -f $(KDIR)/ubi_mark echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark endef -define Build/buffalo-kernel-trx - $(eval magic=$(word 1,$(1))) - $(eval dummy=$(word 2,$(1))) - $(eval kern_size=$(if $(KERNEL_SIZE),$(KERNEL_SIZE),0x400000)) - - $(if $(dummy),touch $(dummy)) - $(STAGING_DIR_HOST)/bin/otrx create $@.new \ - $(if $(magic),-M $(magic),) \ - -f $@ \ - $(if $(dummy),\ - -a 0x20000 \ - -b $$(( $(subst k, * 1024,$(kern_size)) )) \ - -f $(dummy),) - mv $@.new $@ -endef - define Build/bl2 cat $(STAGING_DIR_IMAGE)/mt7622-$1-bl2.img >> $@ endef @@ -30,6 +16,21 @@ define Build/bl31-uboot cat $(STAGING_DIR_IMAGE)/mt7622_$1-u-boot.fip >> $@ endef +define Build/uboot-bin + cat $(STAGING_DIR_IMAGE)/mt7622_$1-u-boot.bin >> $@ +endef + +define Build/uboot-fit + $(TOPDIR)/scripts/mkits.sh \ + -D $(DEVICE_NAME) -o $@.its -k $@ \ + -C $(word 1,$(1)) \ + -a 0x41e00000 -e 0x41e00000 \ + -c "config-1" \ + -A $(LINUX_KARCH) -v u-boot + PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new + @mv $@.new $@ +endef + define Build/mt7622-gpt cp $@ $@.tmp 2>/dev/null || true ptgen -g -o $@.tmp -a 1 -l 1024 \ @@ -51,19 +52,6 @@ define Build/mt7622-gpt rm $@.tmp endef -define Build/trx-nand - # kernel: always use 4 MiB (-28 B or TRX header) to allow upgrades even - # if it grows up between releases - # root: UBI with one extra block containing UBI mark to trigger erasing - # rest of partition - $(STAGING_DIR_HOST)/bin/otrx create $@.new \ - -M 0x32504844 \ - -f $(IMAGE_KERNEL) -a 0x20000 -b 0x400000 \ - -f $@ \ - -A $(KDIR)/ubi_mark -a 0x20000 - mv $@.new $@ -endef - define Device/bananapi_bpi-r64 DEVICE_VENDOR := Bananapi DEVICE_MODEL := BPi-R64 @@ -71,12 +59,13 @@ define Device/bananapi_bpi-r64 DEVICE_DTS_OVERLAY := mt7622-bananapi-bpi-r64-pcie1 mt7622-bananapi-bpi-r64-sata DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3 e2fsprogs mkf2fs f2fsck DEVICE_DTC_FLAGS := --pad 4096 + DEVICE_DTS_LOADADDR := 0x43f00000 ARTIFACTS := emmc-preloader.bin emmc-bl31-uboot.fip sdcard.img.gz snand-preloader.bin snand-bl31-uboot.fip IMAGES := sysupgrade.itb KERNEL_INITRAMFS_SUFFIX := -recovery.itb ARTIFACT/emmc-preloader.bin := bl2 emmc-2ddr ARTIFACT/emmc-bl31-uboot.fip := bl31-uboot bananapi_bpi-r64-emmc - ARTIFACT/snand-preloader.bin := bl2 snand-2ddr + ARTIFACT/snand-preloader.bin := bl2 snand-ubi-2ddr ARTIFACT/snand-bl31-uboot.fip := bl31-uboot bananapi_bpi-r64-snand ARTIFACT/sdcard.img.gz := mt7622-gpt sdmmc |\ pad-to 512k | bl2 sdmmc-2ddr |\ @@ -87,50 +76,104 @@ define Device/bananapi_bpi-r64 pad-to 38912k | mt7622-gpt emmc |\ pad-to 39424k | bl2 emmc-2ddr |\ pad-to 40960k | bl31-uboot bananapi_bpi-r64-emmc |\ - pad-to 43008k | bl2 snand-2ddr |\ + pad-to 43008k | bl2 snand-ubi-2ddr |\ pad-to 43520k | bl31-uboot bananapi_bpi-r64-snand |\ $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS), \ pad-to 46080k | append-image squashfs-sysupgrade.itb | check-size |\ ) \ gzip +ifeq ($(DUMP),) IMAGE_SIZE := $$(shell expr 45 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m +endif KERNEL := kernel-bin | gzip KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata - DEVICE_COMPAT_VERSION := 1.1 - DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update + DEVICE_COMPAT_VERSION := 1.2 + DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update endef TARGET_DEVICES += bananapi_bpi-r64 -define Device/buffalo_wsr-2533dhp2 +define Device/buffalo_wsr DEVICE_VENDOR := Buffalo - DEVICE_MODEL := WSR-2533DHP2 - DEVICE_DTS := mt7622-buffalo-wsr-2533dhp2 DEVICE_DTS_DIR := ../dts - IMAGE_SIZE := 59392k - KERNEL_SIZE := 4096k + KERNEL_SIZE := 6144k BLOCKSIZE := 128k PAGESIZE := 2048 - SUBPAGESIZE := 512 UBINIZE_OPTS := -E 5 BUFFALO_TAG_PLATFORM := MTK BUFFALO_TAG_VERSION := 9.99 BUFFALO_TAG_MINOR := 9.99 IMAGES += factory.bin factory-uboot.bin - KERNEL_INITRAMFS := kernel-bin | lzma | \ + KERNEL_INITRAMFS = kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | \ - buffalo-kernel-trx - IMAGE/factory.bin := append-ubi | trx-nand | \ - buffalo-enc WSR-2533DHP2 $$(BUFFALO_TAG_VERSION) -l | \ - buffalo-tag-dhp WSR-2533DHP2 JP JP | buffalo-enc-tag -l | buffalo-dhp-image - IMAGE/factory-uboot.bin := append-ubi | trx-nand - IMAGE/sysupgrade.bin := append-kernel | \ - buffalo-kernel-trx 0x32504844 $(KDIR)/tmp/$$(DEVICE_NAME).null | \ + buffalo-trx + IMAGE/factory.bin = append-ubi | \ + buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark | \ + buffalo-enc $$(DEVICE_MODEL) $$(BUFFALO_TAG_VERSION) -l | \ + buffalo-tag-dhp $$(DEVICE_MODEL) JP JP | buffalo-enc-tag -l | buffalo-dhp-image + IMAGE/factory-uboot.bin := append-ubi | \ + buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark + IMAGE/sysupgrade.bin := \ + buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $(KDIR)/tmp/$$(DEVICE_NAME).null | \ sysupgrade-tar kernel=$$$$@ | append-metadata +endef + +define Device/buffalo_wsr-2533dhp2 + $(Device/buffalo_wsr) + DEVICE_MODEL := WSR-2533DHP2 + DEVICE_DTS := mt7622-buffalo-wsr-2533dhp2 + IMAGE_SIZE := 59392k + SUBPAGESIZE := 512 + BUFFALO_TRX_MAGIC := 0x32504844 DEVICE_PACKAGES := kmod-mt7615-firmware swconfig + DEVICE_COMPAT_VERSION := 1.1 + DEVICE_COMPAT_MESSAGE := Partition table has been changed due to kernel size restrictions. \ + Please upgrade via sysupgrade with factory-uboot.bin image and '-F' option. \ + (Warning: your configurations will be erased!) endef TARGET_DEVICES += buffalo_wsr-2533dhp2 +define Device/buffalo_wsr-3200ax4s + $(Device/buffalo_wsr) + DEVICE_MODEL := WSR-3200AX4S + DEVICE_DTS := mt7622-buffalo-wsr-3200ax4s + IMAGE_SIZE := 24576k + BUFFALO_TRX_MAGIC := 0x33504844 + DEVICE_PACKAGES := kmod-mt7915-firmware +endef +TARGET_DEVICES += buffalo_wsr-3200ax4s + +define Device/dlink_eagle-pro-ai-ax3200-a1 + IMAGE_SIZE := 46080k + DEVICE_VENDOR := D-Link + DEVICE_VARIANT := A1 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware + KERNEL_SIZE := 8192k + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_OPTS := -E 5 + IMAGES += tftp.bin recovery.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/tftp.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | check-size +endef + +define Device/dlink_eagle-pro-ai-m32-a1 + $(Device/dlink_eagle-pro-ai-ax3200-a1) + DEVICE_MODEL := EAGLE PRO AI M32 + DEVICE_DTS := mt7622-dlink-eagle-pro-ai-m32-a1 + IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | dlink-ai-recovery-header DLK6E6010001 \x8D\x57\x30\x0B \x00\x00\x2C\x00 \x00\x00\xD0\x02 \x60\x6E +endef +TARGET_DEVICES += dlink_eagle-pro-ai-m32-a1 + +define Device/dlink_eagle-pro-ai-r32-a1 + $(Device/dlink_eagle-pro-ai-ax3200-a1) + DEVICE_MODEL := EAGLE PRO AI R32 + DEVICE_DTS := mt7622-dlink-eagle-pro-ai-r32-a1 + IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | pad-to $$(IMAGE_SIZE) | dlink-ai-recovery-header DLK6E6015001 \x8D\x57\x30\x0B \x00\x00\x2C\x00 \x00\x00\xD0\x02 \x60\x6E +endef +TARGET_DEVICES += dlink_eagle-pro-ai-r32-a1 + define Device/elecom_wrc-2533gent DEVICE_VENDOR := Elecom DEVICE_MODEL := WRC-2533GENT @@ -194,8 +237,10 @@ define Device/linksys_e8450-ubi IMAGES := sysupgrade.itb IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata ARTIFACTS := preloader.bin bl31-uboot.fip - ARTIFACT/preloader.bin := bl2 snand-1ddr + ARTIFACT/preloader.bin := bl2 snand-ubi-1ddr ARTIFACT/bl31-uboot.fip := bl31-uboot linksys_e8450 + DEVICE_COMPAT_VERSION := 2.0 + DEVICE_COMPAT_MESSAGE := SPI-NAND flash layout changes require bootloader update. Please run the UBI installer version 1.1.0+ (unsigned) first. endef TARGET_DEVICES += linksys_e8450-ubi @@ -217,7 +262,7 @@ define Device/mediatek_mt7622-rfb1-ubi UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 - KERNEL_SIZE := 4194304 + KERNEL_SIZE := 6291456 IMAGE_SIZE := 32768k IMAGES += factory.bin IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \ @@ -262,12 +307,21 @@ define Device/ruijie_rg-ew3200gx-pro endef TARGET_DEVICES += ruijie_rg-ew3200gx-pro +define Device/reyee_ax3200-e5 + DEVICE_VENDOR := reyee + DEVICE_MODEL := AX3200 E5 + DEVICE_DTS := mt7622-reyee-ax3200-e5 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware +endef +TARGET_DEVICES += reyee_ax3200-e5 + define Device/totolink_a8000ru DEVICE_VENDOR := TOTOLINK DEVICE_MODEL := A8000RU DEVICE_DTS := mt7622-totolink-a8000ru DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-mt7615-firmware swconfig + DEVICE_PACKAGES := kmod-mt7615-firmware kmod-usb3 swconfig IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef TARGET_DEVICES += totolink_a8000ru @@ -298,7 +352,7 @@ define Device/ubnt_unifi-6-lr-v1-ubootmod IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata ARTIFACTS := preloader.bin bl31-uboot.fip ARTIFACT/preloader.bin := bl2 nor-2ddr - ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr-v1 SUPPORTED_DEVICES += ubnt,unifi-6-lr-ubootmod endef TARGET_DEVICES += ubnt_unifi-6-lr-v1-ubootmod @@ -328,10 +382,39 @@ define Device/ubnt_unifi-6-lr-v2-ubootmod IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata ARTIFACTS := preloader.bin bl31-uboot.fip ARTIFACT/preloader.bin := bl2 nor-2ddr - ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr-v2 endef TARGET_DEVICES += ubnt_unifi-6-lr-v2-ubootmod +define Device/ubnt_unifi-6-lr-v3 + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v3 + DEVICE_DTS_CONFIG := config@1 + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v3 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware +endef +TARGET_DEVICES += ubnt_unifi-6-lr-v3 + +define Device/ubnt_unifi-6-lr-v3-ubootmod + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v3 U-Boot mod + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v3-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915-firmware + KERNEL := kernel-bin | lzma + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.itb + IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := bl2 nor-2ddr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr-v3 +endef +TARGET_DEVICES += ubnt_unifi-6-lr-v3-ubootmod + define Device/xiaomi_redmi-router-ax6s DEVICE_VENDOR := Xiaomi DEVICE_MODEL := Redmi Router AX6S @@ -342,12 +425,20 @@ define Device/xiaomi_redmi-router-ax6s BOARD_NAME := xiaomi,redmi-router-ax6s DEVICE_PACKAGES := kmod-mt7915-firmware UBINIZE_OPTS := -E 5 - IMAGES += factory.bin BLOCKSIZE := 128k PAGESIZE := 2048 - KERNEL_SIZE := 4096k + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k KERNEL_INITRAMFS_SUFFIX := -recovery.itb - IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGES := sysupgrade.itb + IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata + ARTIFACTS := ubi-loader.itb + ARTIFACT/ubi-loader.itb := uboot-bin xiaomi_redmi-router-ax6s-ubi-loader | lzma | uboot-fit lzma +ifneq ($(CONFIG_TARGET_ROOTFS_SQUASHFS),) + ARTIFACTS += factory.bin + ARTIFACT/factory.bin := uboot-bin xiaomi_redmi-router-ax6s-ubi-loader | lzma | uboot-fit lzma | pad-to 512k | ubinize-image fit squashfs-sysupgrade.itb +endif + DEVICE_COMPAT_VERSION := 2.0 + DEVICE_COMPAT_MESSAGE := Flash layout changes require a manual reinstall using factory.bin. endef TARGET_DEVICES += xiaomi_redmi-router-ax6s diff --git a/target/linux/mediatek/image/mt7623.mk b/target/linux/mediatek/image/mt7623.mk index 5828c4d76..93625c405 100644 --- a/target/linux/mediatek/image/mt7623.mk +++ b/target/linux/mediatek/image/mt7623.mk @@ -1,3 +1,7 @@ +ifneq ($(KERNEL),6.1) +DTS_DIR := $(DTS_DIR)/mediatek +endif + DEVICE_VARS += UBOOT_TARGET UBOOT_OFFSET UBOOT_IMAGE # The bootrom of MT7623 expects legacy MediaTek headers present in @@ -96,7 +100,9 @@ define Device/bananapi_bpi-r2 KERNEL := kernel-bin | gzip KERNEL_INITRAMFS_SUFFIX := -recovery.itb KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd +ifeq ($(DUMP),) IMAGE_SIZE := $$(shell expr 48 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m +endif IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata ARTIFACT/preloader.bin := mt7623-mbr emmc |\ pad-to 2k | append-preloader $$(UBOOT_TARGET) @@ -114,6 +120,8 @@ define Device/bananapi_bpi-r2 gzip ARTIFACTS := u-boot.bin preloader.bin sdcard.img.gz SUPPORTED_DEVICES := bananapi,bpi-r2 + DEVICE_COMPAT_VERSION := 1.1 + DEVICE_COMPAT_MESSAGE := Bootloader update required for switch to fitblk endef TARGET_DEVICES += bananapi_bpi-r2 @@ -130,7 +138,9 @@ define Device/unielec_u7623-02 UBOOT_TARGET := mt7623a_unielec_u7623 UBOOT_IMAGE := u-boot-mtk.bin UBOOT_PATH := $(STAGING_DIR_IMAGE)/$$(UBOOT_TARGET)-$$(UBOOT_IMAGE) +ifeq ($(DUMP),) IMAGE_SIZE := $$(shell expr 48 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m +endif IMAGES := sysupgrade.itb KERNEL := kernel-bin | gzip KERNEL_INITRAMFS_SUFFIX := -recovery.itb diff --git a/target/linux/mediatek/image/mt7629.mk b/target/linux/mediatek/image/mt7629.mk index ef4b75235..9f0ea9895 100644 --- a/target/linux/mediatek/image/mt7629.mk +++ b/target/linux/mediatek/image/mt7629.mk @@ -1,3 +1,7 @@ +ifneq ($(KERNEL),6.1) +DTS_DIR := $(DTS_DIR)/mediatek +endif + define Device/mediatek_mt7629-rfb DEVICE_VENDOR := MediaTek DEVICE_MODEL := MT7629 rfb AP @@ -5,3 +9,55 @@ define Device/mediatek_mt7629-rfb DEVICE_PACKAGES := swconfig endef TARGET_DEVICES += mediatek_mt7629-rfb + +define Device/iptime_a6004mx + DEVICE_VENDOR := ipTIME + DEVICE_MODEL := A6004MX + DEVICE_DTS := mt7629-iptime-a6004mx + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-usb3 uboot-envtools + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL := $$(KERNEL) | pad-offset 128k 2048 | iptime-crc32 a6004mx + KERNEL_INITRAMFS := $$(KERNEL_INITRAMFS) | pad-offset 128k 2048 | iptime-crc32 a6004mx + IMAGES += recovery.bin + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + IMAGE/recovery.bin := append-kernel | pad-to 128k | append-ubi | append-metadata +endef +TARGET_DEVICES += iptime_a6004mx + +define Device/netgear_ex6250-v2 + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := EX6250 + DEVICE_VARIANT := v2 + DEVICE_ALT0_VENDOR := NETGEAR + DEVICE_ALT0_MODEL := EX6400 + DEVICE_ALT0_VARIANT := v3 + DEVICE_ALT1_VENDOR := NETGEAR + DEVICE_ALT1_MODEL := EX6410 + DEVICE_ALT1_VARIANT := v2 + DEVICE_ALT2_VENDOR := NETGEAR + DEVICE_ALT2_MODEL := EX6470 + DEVICE_DTS := mt7629-netgear-ex6250-v2 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := uboot-envtools + NETGEAR_ENC_MODEL := EX6250v2 + NETGEAR_ENC_REGION := US + NETGEAR_ENC_HW_ID_LIST := 1010000003630000_NETGEAR;1010000003540000_NETGEAR + NETGEAR_ENC_MODEL_LIST := EX6250v2;EX6400v3;EX6470;EX6410v2 + IMAGE_SIZE := 13120k + IMAGES += factory.img + IMAGE/factory.img := append-kernel | pad-to 128k | append-rootfs | \ + pad-rootfs | check-size | netgear-encrypted-factory +endef +TARGET_DEVICES += netgear_ex6250-v2 + +define Device/tplink_eap225-v5 + DEVICE_VENDOR := TP-Link + DEVICE_MODEL := EAP225 + DEVICE_VARIANT := v5 + DEVICE_DTS := mt7629-tplink_eap225-v5 + DEVICE_DTS_DIR := ../dts +endef +TARGET_DEVICES += tplink_eap225-v5 diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network index cf18c25f8..6bda6e11f 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network @@ -8,34 +8,41 @@ mediatek_setup_interfaces() local board="$1" case $board in - bananapi,bpi-r64|\ - elecom,wrc-x3200gst3|\ - linksys,e8450|\ - linksys,e8450-ubi|\ - mediatek,mt7622-rfb1|\ - mediatek,mt7622-rfb1-ubi|\ - netgear,wax206|\ - ruijie,rg-ew3200gx-pro) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan - ;; buffalo,wsr-2533dhp2) ucidef_add_switch "switch0" \ "0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6@eth0" ;; - ubnt,unifi-6-lr|\ - ubnt,unifi-6-lr-ubootmod) + dlink,eagle-pro-ai-m32-a1) + ucidef_set_interfaces_lan_wan "lan1 lan2" wan + ;; + elecom,wrc-2533gent|\ + totolink,a8000ru) + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1" + ;; + ubnt,unifi-6-lr*) ucidef_set_interface_lan "eth0" ;; xiaomi,redmi-router-ax6s) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan ;; *) - ucidef_add_switch "switch0" \ - "0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1" + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan ;; esac } +DEV_PATH_WMAC=platform/18000000.wmac +DEV_PATH_PCIE0=1a143000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0 +DEV_PATH_PCIE1=1a145000.pcie/pci0001:00/0001:00:01.0/0001:01:00.0 + +mediatek_setup_wlan() +{ + dt_is_enabled wmac@18000000 && ucidef_add_wlan $DEV_PATH_WMAC + dt_is_enabled pcie@1a143000 && ucidef_add_wlan $DEV_PATH_PCIE0 + dt_is_enabled pcie@1a145000 && ucidef_add_wlan $DEV_PATH_PCIE1 +} + mediatek_setup_macs() { local board="$1" @@ -44,6 +51,12 @@ mediatek_setup_macs() local label_mac="" case $board in + buffalo,wsr-3200ax4s) + lan_mac=$(mtd_get_mac_ascii board_data "mac") + wan_mac=$lan_mac + label_mac=$lan_mac + ;; + reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) lan_mac=$(macaddr_add $(get_mac_label) 1) ;; @@ -62,6 +75,7 @@ board_config_update board=$(board_name) mediatek_setup_interfaces $board mediatek_setup_macs $board +mediatek_setup_wlan $board board_config_flush exit 0 diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version index c8fb2c08f..68c397a95 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/05_compat-version @@ -6,7 +6,10 @@ board_config_update case "$(board_name)" in bananapi,bpi-r64) - ucidef_set_compat_version "1.1" + ucidef_set_compat_version "1.2" + ;; + linksys,e8450-ubi) + ucidef_set_compat_version "2.0" ;; esac diff --git a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index d57346574..7ee9f2407 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -10,6 +10,15 @@ PHYNBR=${DEVPATH##*/phy} board=$(board_name) case "$board" in + bananapi,bpi-r64) + [ "$PHYNBR" = "0" ] && macaddr_add $(cat /sys/class/net/eth0/address) 2 > /sys${DEVPATH}/macaddress + ;; + buffalo,wsr-3200ax4s) + basemac=$(mtd_get_mac_ascii board_data "mac") + [ "$PHYNBR" = "0" ] && macaddr_add $basemac 1 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $basemac 8 > /sys${DEVPATH}/macaddress + ;; + reyee,ax3200-e5|\ ruijie,rg-ew3200gx-pro) [ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount b/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount index bc4eeb653..19a321b48 100755 --- a/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount +++ b/target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount @@ -4,6 +4,14 @@ START=99 boot() { case $(board_name) in + dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-r32-a1) + if grep -q boot_part=Kernel1 /proc/cmdline; then + fw_setenv boot_part 1 + else + fw_setenv boot_part 2 + fi + ;; linksys,e8450) mtd erase senv || true ;; diff --git a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version index c77e1cb8b..dd224f3d8 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version +++ b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/05_fix-compat-version @@ -2,9 +2,18 @@ case "$(board_name)" in bananapi,bpi-r64) + uci set system.@system[0].compat_version="1.2" + uci commit system + ;; + buffalo,wsr-2533dhp2) uci set system.@system[0].compat_version="1.1" uci commit system ;; + linksys,e8450-ubi|\ + xiaomi,redmi-router-ax6s) + uci set system.@system[0].compat_version="2.0" + uci commit system + ;; esac exit 0 diff --git a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc index 81cb6b18b..59b00a6e6 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc +++ b/target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc @@ -7,4 +7,8 @@ buffalo,wsr-2533dhp2) mtd -M 0x44485032 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0 exit 1 ;; +buffalo,wsr-3200ax4s) + mtd -M 0x44485033 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0 + exit 1 + ;; esac diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh index a9899edf4..59375ccd9 100755 --- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh @@ -1,27 +1,38 @@ REQUIRE_IMAGE_METADATA=1 +RAMFS_COPY_BIN='fitblk' platform_do_upgrade() { local board=$(board_name) local file_type=$(identify $1) case "$board" in - bananapi,bpi-r64) - local rootdev="$(cmdline_get_var root)" - rootdev="${rootdev##*/}" - rootdev="${rootdev%p[0-9]*}" - case "$rootdev" in - mmc*) - CI_ROOTDEV="$rootdev" - CI_KERNPART="production" + bananapi,bpi-r64|\ + linksys,e8450-ubi|\ + ubnt,unifi-6-lr-v1-ubootmod|\ + ubnt,unifi-6-lr-v2-ubootmod|\ + ubnt,unifi-6-lr-v3-ubootmod|\ + xiaomi,redmi-router-ax6s) + [ -e /dev/fit0 ] && fitblk /dev/fit0 + [ -e /dev/fitrw ] && fitblk /dev/fitrw + bootdev="$(fitblk_get_bootdev)" + case "$bootdev" in + mmcblk*) + EMMC_KERN_DEV="/dev/$bootdev" emmc_do_upgrade "$1" ;; - *) + mtdblock*) + PART_NAME="/dev/mtd${bootdev:8}" + default_do_upgrade "$1" + ;; + ubiblock*) CI_KERNPART="fit" nand_do_upgrade "$1" ;; esac ;; - buffalo,wsr-2533dhp2) + + buffalo,wsr-2533dhp2|\ + buffalo,wsr-3200ax4s) local magic="$(get_magic_long "$1")" # use "mtd write" if the magic is "DHP2 (0x44485032)" @@ -33,15 +44,12 @@ platform_do_upgrade() { nand_do_upgrade "$1" fi ;; + dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-r32-a1|\ elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ - totolink,a8000ru|\ - xiaomi,redmi-router-ax6s) - nand_do_upgrade "$1" - ;; - linksys,e8450-ubi) - CI_KERNPART="fit" + totolink,a8000ru) nand_do_upgrade "$1" ;; linksys,e8450) @@ -67,15 +75,18 @@ platform_check_image() { [ "$#" -gt 1 ] && return 1 case "$board" in - buffalo,wsr-2533dhp2) + buffalo,wsr-2533dhp2|\ + buffalo,wsr-3200ax4s) buffalo_check_image "$board" "$magic" "$1" || return 1 ;; + dlink,eagle-pro-ai-m32-a1|\ + dlink,eagle-pro-ai-r32-a1|\ elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ - totolink,a8000ru|\ - xiaomi,redmi-router-ax6s) + totolink,a8000ru) nand_do_platform_check "$board" "$1" + return $? ;; *) [ "$magic" != "d00dfeed" ] && { @@ -92,9 +103,7 @@ platform_check_image() { platform_copy_config() { case "$(board_name)" in bananapi,bpi-r64) - export_bootdevice - export_partdevice rootdev 0 - if echo $rootdev | grep -q mmc; then + if fitblk_get_bootdev | grep -q mmc; then emmc_copy_config fi ;; diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 deleted file mode 100644 index 47df81b14..000000000 --- a/target/linux/mediatek/mt7622/config-5.15 +++ /dev/null @@ -1,464 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_CNP is not set -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set -# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set -# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set -# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set -# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set -# CONFIG_COMMON_CLK_MT8183_MMSYS is not set -# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set -# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set -# CONFIG_COMMON_CLK_MT8516 is not set -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_2P5G_PHY is not set -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_GE_SOC_PHY is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_EFUSE=y -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -# CONFIG_PINCTRL_MT7981 is not set -# CONFIG_PINCTRL_MT7986 is not set -# CONFIG_PINCTRL_MT7988 is not set -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -# CONFIG_REGULATOR_RT5190A is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1 deleted file mode 100644 index 7055e4d72..000000000 --- a/target/linux/mediatek/mt7622/config-6.1 +++ /dev/null @@ -1,472 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=2048 -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_2P5G_PHY is not set -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_GE_SOC_PHY is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_MTK_EFUSE=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -# CONFIG_PINCTRL_MT7981 is not set -# CONFIG_PINCTRL_MT7986 is not set -# CONFIG_PINCTRL_MT7988 is not set -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -# CONFIG_PINCTRL_MT8516 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/target.mk b/target/linux/mediatek/mt7622/target.mk index b1c67f46f..ea0e22e31 100644 --- a/target/linux/mediatek/mt7622/target.mk +++ b/target/linux/mediatek/mt7622/target.mk @@ -2,7 +2,7 @@ ARCH:=aarch64 SUBTARGET:=mt7622 BOARDNAME:=MT7622 CPU_TYPE:=cortex-a53 -DEFAULT_PACKAGES += kmod-mt7622-firmware wpad-openssl uboot-envtools +DEFAULT_PACKAGES += fitblk kmod-mt7622-firmware wpad-basic-mbedtls uboot-envtools KERNELNAME:=Image dtbs define Target/Description diff --git a/target/linux/mediatek/mt7623/base-files/etc/board.d/05_compat-version b/target/linux/mediatek/mt7623/base-files/etc/board.d/05_compat-version new file mode 100644 index 000000000..a4cf133a6 --- /dev/null +++ b/target/linux/mediatek/mt7623/base-files/etc/board.d/05_compat-version @@ -0,0 +1,14 @@ +. /lib/functions.sh +. /lib/functions/uci-defaults.sh + +board_config_update + +case "$(board_name)" in +bananapi,bpi-r2) + ucidef_set_compat_version "1.1" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/mediatek/mt7623/base-files/etc/uci-defaults/05_fix-compat-version b/target/linux/mediatek/mt7623/base-files/etc/uci-defaults/05_fix-compat-version new file mode 100644 index 000000000..ae3f16002 --- /dev/null +++ b/target/linux/mediatek/mt7623/base-files/etc/uci-defaults/05_fix-compat-version @@ -0,0 +1,10 @@ +. /lib/functions.sh + +case "$(board_name)" in +bananapi,bpi-r2) + uci set system.@system[0].compat_version="1.1" + uci commit system + ;; +esac + +exit 0 diff --git a/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh index 5d12b6989..9cfb15cf3 100755 --- a/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh @@ -83,10 +83,10 @@ platform_do_upgrade() { case "$board" in bananapi,bpi-r2|\ unielec,u7623-02) - export_bootdevice - export_partdevice fitpart 3 - [ "$fitpart" ] || return 1 - EMMC_KERN_DEV="/dev/$fitpart" + [ -e /dev/fit0 ] && fitblk /dev/fit0 + [ -e /dev/fitrw ] && fitblk /dev/fitrw + bootdev="$(fitblk_get_bootdev)" + EMMC_KERN_DEV="/dev/$bootdev" emmc_do_upgrade "$1" ;; unielec,u7623-02-emmc-512m) diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 deleted file mode 100644 index 5ae596d41..000000000 --- a/target/linux/mediatek/mt7623/config-5.15 +++ /dev/null @@ -1,579 +0,0 @@ -# CONFIG_AIO is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLEANCACHE=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_PREEMPT=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -CONFIG_DEBUG_UNCOMPRESS=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_GE_PHY_SOC is not set -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_ECC_MEDIATEK is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CQDMA=y -CONFIG_MTK_EFUSE=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -CONFIG_MTK_MMSYS=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SMI=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_MTK_HDMI=y -CONFIG_PHY_MTK_MIPI_DSI=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -CONFIG_PINCTRL_MT6397=y -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_RT5190A is not set -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1 deleted file mode 100644 index b6a75ab80..000000000 --- a/target/linux/mediatek/mt7623/config-6.1 +++ /dev/null @@ -1,609 +0,0 @@ -# CONFIG_AIO is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_PREEMPT=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_DMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -# CONFIG_DRM_MEDIATEK_DP is not set -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_NOMODESET=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_WARN=1024 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -# CONFIG_KEYBOARD_MT6779 is not set -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_QCOM_LPG is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_ECC_MEDIATEK is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_ADSP_MBOX is not set -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CQDMA=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -CONFIG_MTK_MMSYS=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SMI=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_MTK_EFUSE=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -CONFIG_PHY_MTK_HDMI=y -CONFIG_PHY_MTK_MIPI_DSI=y -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -# CONFIG_PINCTRL_MT6397 is not set -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_BUILD=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6331 is not set -# CONFIG_REGULATOR_MT6332 is not set -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_SPMI_MTK_PMIF is not set -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/target.mk b/target/linux/mediatek/mt7623/target.mk index 1338b091e..4f84a98ff 100644 --- a/target/linux/mediatek/mt7623/target.mk +++ b/target/linux/mediatek/mt7623/target.mk @@ -9,7 +9,7 @@ CPU_TYPE:=cortex-a7 CPU_SUBTYPE:=neon-vfpv4 KERNELNAME:=Image dtbs zImage FEATURES+=display usbgadget -DEFAULT_PACKAGES+=kmod-crypto-hw-safexcel uboot-envtools +DEFAULT_PACKAGES+=fitblk kmod-crypto-hw-safexcel uboot-envtools define Target/Description Build firmware images for MediaTek mt7623 ARM based boards. diff --git a/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds b/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds new file mode 100644 index 000000000..c42ab4713 --- /dev/null +++ b/target/linux/mediatek/mt7629/base-files/etc/board.d/01_leds @@ -0,0 +1,20 @@ +. /lib/functions/leds.sh +. /lib/functions/uci-defaults.sh + +board=$(board_name) + +board_config_update + +case $board in +iptime,a6004mx) + ucidef_set_led_netdev "wan" "WAN" "orange:wan" "eth1" + ;; +netgear,ex6250-v2) + ucidef_set_led_netdev "eth_act" "LAN act" "yellow:eth" "eth0" "tx rx" + ucidef_set_led_netdev "eth_link" "LAN link" "green:eth" "eth0" "link" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network index c39417abb..df042f8ad 100644 --- a/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7629/base-files/etc/board.d/02_network @@ -8,11 +8,18 @@ mediatek_setup_interfaces() local board="$1" case $board in + iptime,a6004mx) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "eth1" + ;; mediatek,mt7629-rfb) ucidef_set_interface_wan "eth1" ucidef_add_switch "switch0" \ "0:lan" "1:lan" "2:lan" "3:lan" "6@eth0" ;; + netgear,ex6250-v2|\ + tplink,eap225-v5) + ucidef_set_interface_lan "eth0" + ;; esac } @@ -21,7 +28,15 @@ mediatek_setup_macs() local board="$1" case $board in + netgear,ex6250-v2) + lan_mac=$(mtd_get_mac_ascii Config mac) + label_mac=$lan_mac + ;; esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac } board_config_update diff --git a/target/linux/mediatek/mt7629/base-files/etc/init.d/bootcount b/target/linux/mediatek/mt7629/base-files/etc/init.d/bootcount new file mode 100755 index 000000000..a6b8fac1d --- /dev/null +++ b/target/linux/mediatek/mt7629/base-files/etc/init.d/bootcount @@ -0,0 +1,17 @@ +#!/bin/sh /etc/rc.common +# SPDX-License-Identifier: GPL-2.0-only + +START=99 + +boot() { + case $(board_name) in + iptime,a6004mx) + if [ `fw_printenv boot_sector` = "boot_sector=B" ]; then + echo "bootcount: boot_sector must be A. Rebooting..." + fw_setenv boot_sector A + reboot + exit 1 + fi + ;; + esac +} diff --git a/target/linux/mediatek/mt7629/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7629/base-files/lib/upgrade/platform.sh index 9a613c43b..f10ad14b4 100755 --- a/target/linux/mediatek/mt7629/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7629/base-files/lib/upgrade/platform.sh @@ -9,6 +9,9 @@ platform_do_upgrade() { local board=$(board_name) case "$board" in + iptime,a6004mx) + nand_do_upgrade "$1" + ;; *) default_do_upgrade "$1" ;; diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15 deleted file mode 100644 index fcf7ae32f..000000000 --- a/target/linux/mediatek/mt7629/config-5.15 +++ /dev/null @@ -1,328 +0,0 @@ -CONFIG_AF_UNIX_OOB=y -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINARY_PRINTF=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DIMLIB=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_HARDENED_USERCOPY is not set -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LTO_NONE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_EFUSE is not set -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -# CONFIG_PINCTRL_MT7986 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1 deleted file mode 100644 index c0c501e59..000000000 --- a/target/linux/mediatek/mt7629/config-6.1 +++ /dev/null @@ -1,349 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DIMLIB=y -CONFIG_DMA_OPS=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_WARN=1024 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -# CONFIG_NVMEM_MTK_EFUSE is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index 7029b2cbf..000000000 --- a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,119 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -23,7 +22,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -40,23 +39,22 @@ - - gpio-keys { - compatible = "gpio-keys"; -- poll-interval = <100>; - - factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory@40000000 { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - device_type = "memory"; - }; - -@@ -133,22 +131,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -237,15 +235,28 @@ - - &pcie { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; -+ -+ pcie@1,0 { -+ status = "okay"; -+ }; - }; - - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -522,11 +533,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index 254b5f9eb..000000000 --- a/target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -272,3 +281,17 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+}; diff --git a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch deleted file mode 100644 index 04df7b927..000000000 --- a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch +++ /dev/null @@ -1,20 +0,0 @@ -From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Fri, 29 Apr 2022 10:40:56 +0800 -Subject: [PATCH] arm: mediatek: select arch timer for mt7623 - -Signed-off-by: Chuanhong Guo ---- - arch/arm/mach-mediatek/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -26,6 +26,7 @@ config MACH_MT6592 - config MACH_MT7623 - bool "MediaTek MT7623 SoCs support" - default ARCH_MEDIATEK -+ select HAVE_ARM_ARCH_TIMER - - config MACH_MT7629 - bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch deleted file mode 100644 index 88aab4129..000000000 --- a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -556,6 +556,7 @@ - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; -+ interrupts = ; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index da42c0772..000000000 --- a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -111,7 +111,7 @@ - }; - - psci { -- compatible = "arm,psci-0.2"; -+ compatible = "arm,psci-1.0"; - method = "smc"; - }; - -@@ -127,6 +127,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 8dc53d298..000000000 --- a/target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch deleted file mode 100644 index 07a2eae24..000000000 --- a/target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -22,7 +22,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index e88913c30..000000000 --- a/target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -18,6 +18,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -161,22 +162,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@6 { diff --git a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index f728b9656..000000000 --- a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -19,6 +19,10 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -42,8 +46,8 @@ - compatible = "gpio-keys"; - - factory { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -57,17 +61,25 @@ - leds { - compatible = "gpio-leds"; - -- green { -- label = "bpi-r64:pio:green"; -- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; -+ led_system_blue: blue { -+ label = "bpi-r64:pio:blue"; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- red { -- label = "bpi-r64:pio:red"; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_green: green { -+ label = "bpi-r64:pio:green"; -+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; -+ -+/* -+ * red { -+ * label = "bpi-r64:pio:red"; -+ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ * default-state = "off"; -+ * }; -+ */ - }; - - memory@40000000 { diff --git a/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index 8e19168ac..000000000 --- a/target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -565,12 +565,16 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { -- status = "disable"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "disable"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch deleted file mode 100644 index 508dd2b57..000000000 --- a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -260,14 +260,42 @@ - status = "disabled"; - }; - --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+&bch { -+ status = "okay"; -+}; - -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; - flash@0 { -- compatible = "jedec,spi-nor"; -+ compatible = "spi-nand"; - reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; -+ -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch deleted file mode 100644 index 7fb62e740..000000000 --- a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch +++ /dev/null @@ -1,214 +0,0 @@ -From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 16 Dec 2021 12:16:38 +0100 -Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware - engines - -Add the necessary helpers to register/unregister hardware ECC engines -that will be called from ECC engine drivers. - -Also add helpers to get the right engine from the user -perspective. Keep a reference of the in use ECC engine in order to -prevent modules to be unloaded. Put the reference when the engine gets -retired. - -A static list of hardware (only) ECC engines is setup to keep track of -the registered engines. - -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com -(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152) ---- - drivers/mtd/nand/core.c | 10 +++-- - drivers/mtd/nand/ecc.c | 88 ++++++++++++++++++++++++++++++++++++++++ - include/linux/mtd/nand.h | 28 +++++++++++++ - 3 files changed, 123 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/nand/core.c -+++ b/drivers/mtd/nand/core.c -@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct - nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand); - break; - case NAND_ECC_ENGINE_TYPE_ON_HOST: -- pr_err("On-host hardware ECC engines not supported yet\n"); -+ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand); -+ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; - break; - default: - pr_err("Missing ECC engine type\n"); -@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct - { - switch (nand->ecc.ctx.conf.engine_type) { - case NAND_ECC_ENGINE_TYPE_ON_HOST: -- pr_err("On-host hardware ECC engines not supported yet\n"); -+ nand_ecc_put_on_host_hw_engine(nand); - break; - case NAND_ECC_ENGINE_TYPE_NONE: - case NAND_ECC_ENGINE_TYPE_SOFT: -@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_ - /* Look for the ECC engine to use */ - ret = nanddev_get_ecc_engine(nand); - if (ret) { -- pr_err("No ECC engine found\n"); -+ if (ret != -EPROBE_DEFER) -+ pr_err("No ECC engine found\n"); -+ - return ret; - } - ---- a/drivers/mtd/nand/ecc.c -+++ b/drivers/mtd/nand/ecc.c -@@ -96,6 +96,12 @@ - #include - #include - #include -+#include -+#include -+#include -+ -+static LIST_HEAD(on_host_hw_engines); -+static DEFINE_MUTEX(on_host_hw_engines_mutex); - - /** - * nand_ecc_init_ctx - Init the ECC engine context -@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_ - } - EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine); - -+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine) -+{ -+ struct nand_ecc_engine *item; -+ -+ if (!engine) -+ return -EINVAL; -+ -+ /* Prevent multiple registrations of one engine */ -+ list_for_each_entry(item, &on_host_hw_engines, node) -+ if (item == engine) -+ return 0; -+ -+ mutex_lock(&on_host_hw_engines_mutex); -+ list_add_tail(&engine->node, &on_host_hw_engines); -+ mutex_unlock(&on_host_hw_engines_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine); -+ -+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine) -+{ -+ if (!engine) -+ return -EINVAL; -+ -+ mutex_lock(&on_host_hw_engines_mutex); -+ list_del(&engine->node); -+ mutex_unlock(&on_host_hw_engines_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine); -+ -+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev) -+{ -+ struct nand_ecc_engine *item; -+ -+ list_for_each_entry(item, &on_host_hw_engines, node) -+ if (item->dev == dev) -+ return item; -+ -+ return NULL; -+} -+ -+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand) -+{ -+ struct nand_ecc_engine *engine = NULL; -+ struct device *dev = &nand->mtd.dev; -+ struct platform_device *pdev; -+ struct device_node *np; -+ -+ if (list_empty(&on_host_hw_engines)) -+ return NULL; -+ -+ /* Check for an explicit nand-ecc-engine property */ -+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0); -+ if (np) { -+ pdev = of_find_device_by_node(np); -+ if (!pdev) -+ return ERR_PTR(-EPROBE_DEFER); -+ -+ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev); -+ platform_device_put(pdev); -+ of_node_put(np); -+ -+ if (!engine) -+ return ERR_PTR(-EPROBE_DEFER); -+ } -+ -+ if (engine) -+ get_device(engine->dev); -+ -+ return engine; -+} -+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine); -+ -+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) -+{ -+ put_device(nand->ecc.engine->dev); -+} -+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); -+ - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Miquel Raynal "); - MODULE_DESCRIPTION("Generic ECC engine"); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops { - }; - - /** -+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated -+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value -+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly -+ * correction, does not need to copy -+ * data around -+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the -+ * data into its own area before use -+ */ -+enum nand_ecc_engine_integration { -+ NAND_ECC_ENGINE_INTEGRATION_INVALID, -+ NAND_ECC_ENGINE_INTEGRATION_PIPELINED, -+ NAND_ECC_ENGINE_INTEGRATION_EXTERNAL, -+}; -+ -+/** - * struct nand_ecc_engine - ECC engine abstraction for NAND devices -+ * @dev: Host device -+ * @node: Private field for registration time - * @ops: ECC engine operations -+ * @integration: How the engine is integrated with the host -+ * (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines) -+ * @priv: Private data - */ - struct nand_ecc_engine { -+ struct device *dev; -+ struct list_head node; - struct nand_ecc_engine_ops *ops; -+ enum nand_ecc_engine_integration integration; -+ void *priv; - }; - - void of_get_nand_ecc_user_config(struct nand_device *nand); -@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_ - int nand_ecc_finish_io_req(struct nand_device *nand, - struct nand_page_io_req *req); - bool nand_ecc_is_strong_enough(struct nand_device *nand); -+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine); -+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine); - struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); - struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); -+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); -+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); - - #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) - struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch deleted file mode 100644 index 61a39ee0e..000000000 --- a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 16 Dec 2021 12:16:39 +0100 -Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context - -Introduce nand_to_ecc_ctx() which will allow to easily jump to the -private pointer of an ECC context given a NAND device. This is very -handy, from the prepare or finish ECC hook, to get the internal context -out of the NAND device object. - -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com -(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4) ---- - include/linux/mtd/nand.h | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device * - int nanddev_ecc_engine_init(struct nand_device *nand); - void nanddev_ecc_engine_cleanup(struct nand_device *nand); - -+static inline void *nand_to_ecc_ctx(struct nand_device *nand) -+{ -+ return nand->ecc.ctx.priv; -+} -+ - /* BBT related functions */ - enum nand_bbt_block_status { - NAND_BBT_BLOCK_STATUS_UNKNOWN, diff --git a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch deleted file mode 100644 index 29b62880a..000000000 --- a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 16 Dec 2021 12:16:41 +0100 -Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a - pilelined engine device - -In a pipelined engine situation, we might either have the host which -internally has support for error correction, or have it using an -external hardware block for this purpose. In the former case, the host -is also the ECC engine. In the latter case, it is not. In order to get -the right pointers on the right devices (for example: in order to devm_* -allocate variables), let's introduce this helper which can safely be -called by pipelined ECC engines in order to retrieve the right device -structure. - -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com -(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309) ---- - drivers/mtd/nand/ecc.c | 31 +++++++++++++++++++++++++++++++ - include/linux/mtd/nand.h | 1 + - 2 files changed, 32 insertions(+) - ---- a/drivers/mtd/nand/ecc.c -+++ b/drivers/mtd/nand/ecc.c -@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru - } - EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); - -+/* -+ * In the case of a pipelined engine, the device registering the ECC -+ * engine is not necessarily the ECC engine itself but may be a host controller. -+ * It is then useful to provide a helper to retrieve the right device object -+ * which actually represents the ECC engine. -+ */ -+struct device *nand_ecc_get_engine_dev(struct device *host) -+{ -+ struct platform_device *ecc_pdev; -+ struct device_node *np; -+ -+ /* -+ * If the device node contains this property, it means we need to follow -+ * it in order to get the right ECC engine device we are looking for. -+ */ -+ np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0); -+ if (!np) -+ return host; -+ -+ ecc_pdev = of_find_device_by_node(np); -+ if (!ecc_pdev) { -+ of_node_put(np); -+ return NULL; -+ } -+ -+ platform_device_put(ecc_pdev); -+ of_node_put(np); -+ -+ return &ecc_pdev->dev; -+} -+ - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Miquel Raynal "); - MODULE_DESCRIPTION("Generic ECC engine"); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_ - struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); - struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); - void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); -+struct device *nand_ecc_get_engine_dev(struct device *host); - - #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) - struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch deleted file mode 100644 index 1e7f572dd..000000000 --- a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:17:56 +0100 -Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure - -Create a spi_controller_mem_caps structure and put it within the -spi_controller structure close to the spi_controller_mem_ops -strucure. So far the only field in this structure is the support for dtr -operations, but soon we will add another parameter. - -Also create a helper to parse the capabilities and check if the -requested capability has been set or not. - -Signed-off-by: Miquel Raynal -Reviewed-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Reviewed-by: Mark Brown -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com -(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20) ---- - include/linux/spi/spi-mem.h | 11 +++++++++++ - include/linux/spi/spi.h | 3 +++ - 2 files changed, 14 insertions(+) - ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -286,6 +286,17 @@ struct spi_controller_mem_ops { - }; - - /** -+ * struct spi_controller_mem_caps - SPI memory controller capabilities -+ * @dtr: Supports DTR operations -+ */ -+struct spi_controller_mem_caps { -+ bool dtr; -+}; -+ -+#define spi_mem_controller_is_capable(ctlr, cap) \ -+ ((ctlr)->mem_caps && (ctlr)->mem_caps->cap) -+ -+/** - * struct spi_mem_driver - SPI memory driver - * @spidrv: inherit from a SPI driver - * @probe: probe a SPI memory. Usually where detection/initialization takes ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -23,6 +23,7 @@ struct software_node; - struct spi_controller; - struct spi_transfer; - struct spi_controller_mem_ops; -+struct spi_controller_mem_caps; - - /* - * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, -@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill - * @mem_ops: optimized/dedicated operations for interactions with SPI memory. - * This field is optional and should only be implemented if the - * controller has native support for memory like operations. -+ * @mem_caps: controller capabilities for the handling of memory operations. - * @unprepare_message: undo any work done by prepare_message(). - * @slave_abort: abort the ongoing transfer request on an SPI slave controller - * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per -@@ -643,6 +645,7 @@ struct spi_controller { - - /* Optimized handlers for SPI memory-like operations. */ - const struct spi_controller_mem_ops *mem_ops; -+ const struct spi_controller_mem_caps *mem_caps; - - /* gpio chip select */ - int *cs_gpios; diff --git a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch deleted file mode 100644 index 9f01fdb83..000000000 --- a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:17:57 +0100 -Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities - -Controllers can now provide a spi-mem capabilities structure. Let's make -use of it in spi_mem_controller_default_supports_op(). As we want to -check for DTR operations as well as normal operations in a single -helper, let's pull the necessary checks from spi_mem_dtr_supports_op() -for now. - -However, because no controller provide these extra capabilities, this -change has no effect so far. - -Signed-off-by: Miquel Raynal -Reviewed-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com -(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37) ---- - drivers/spi/spi-mem.c | 17 +++++++++++++---- - 1 file changed, 13 insertions(+), 4 deletions(-) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o - bool spi_mem_default_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { -- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) -- return false; -+ struct spi_controller *ctlr = mem->spi->controller; -+ bool op_is_dtr = -+ op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; - -- if (op->cmd.nbytes != 1) -- return false; -+ if (op_is_dtr) { -+ if (!spi_mem_controller_is_capable(ctlr, dtr)) -+ return false; -+ -+ if (op->cmd.nbytes != 2) -+ return false; -+ } else { -+ if (op->cmd.nbytes != 1) -+ return false; -+ } - - return spi_mem_check_buswidth(mem, op); - } diff --git a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch deleted file mode 100644 index c313a455b..000000000 --- a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:00 +0100 -Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper - -Now that spi_mem_default_supports_op() has access to the static -controller capabilities (relating to memory operations), and now that -these capabilities have been filled by the relevant controllers, there -is no need for a specific helper checking only DTR operations, so let's -just kill spi_mem_dtr_supports_op() and simply use -spi_mem_default_supports_op() instead. - -Signed-off-by: Miquel Raynal -Reviewed-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com -(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20) ---- - drivers/spi/spi-cadence-quadspi.c | 5 +---- - drivers/spi/spi-mem.c | 10 ---------- - drivers/spi/spi-mxic.c | 10 +--------- - include/linux/spi/spi-mem.h | 11 ----------- - 4 files changed, 2 insertions(+), 34 deletions(-) - ---- a/drivers/spi/spi-cadence-quadspi.c -+++ b/drivers/spi/spi-cadence-quadspi.c -@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct - return false; - } - -- if (all_true) -- return spi_mem_dtr_supports_op(mem, op); -- else -- return spi_mem_default_supports_op(mem, op); -+ return spi_mem_default_supports_op(mem, op); - } - - static int cqspi_of_get_flash_pdata(struct platform_device *pdev, ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc - return true; - } - --bool spi_mem_dtr_supports_op(struct spi_mem *mem, -- const struct spi_mem_op *op) --{ -- if (op->cmd.nbytes != 2) -- return false; -- -- return spi_mem_check_buswidth(mem, op); --} --EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); -- - bool spi_mem_default_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { ---- a/drivers/spi/spi-mxic.c -+++ b/drivers/spi/spi-mxic.c -@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi - static bool mxic_spi_mem_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op) - { -- bool all_false; -- - if (op->data.buswidth > 8 || op->addr.buswidth > 8 || - op->dummy.buswidth > 8 || op->cmd.buswidth > 8) - return false; -@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str - if (op->addr.nbytes > 7) - return false; - -- all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && -- !op->data.dtr; -- -- if (all_false) -- return spi_mem_default_supports_op(mem, op); -- else -- return spi_mem_dtr_supports_op(mem, op); -+ return spi_mem_default_supports_op(mem, op); - } - - static int mxic_spi_mem_exec_op(struct spi_mem *mem, ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat - - bool spi_mem_default_supports_op(struct spi_mem *mem, - const struct spi_mem_op *op); -- --bool spi_mem_dtr_supports_op(struct spi_mem *mem, -- const struct spi_mem_op *op); -- - #else - static inline int - spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, -@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct - { - return false; - } -- --static inline --bool spi_mem_dtr_supports_op(struct spi_mem *mem, -- const struct spi_mem_op *op) --{ -- return false; --} - #endif /* CONFIG_SPI_MEM */ - - int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); diff --git a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch deleted file mode 100644 index 6d7e47650..000000000 --- a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:01 +0100 -Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op - structure - -Soon the SPI-NAND core will need a way to request a SPI controller to -enable ECC support for a given operation. This is because of the -pipelined integration of certain ECC engines, which are directly managed -by the SPI controller itself. - -Introduce a spi_mem_op additional field for this purpose: ecc. - -So far this field is left unset and checked to be false by all -the SPI controller drivers in their ->supports_op() hook, as they all -call spi_mem_default_supports_op(). - -Signed-off-by: Miquel Raynal -Acked-by: Pratyush Yadav -Reviewed-by: Boris Brezillon -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com -(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7) ---- - drivers/spi/spi-mem.c | 5 +++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 9 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct - return false; - } - -+ if (op->data.ecc) { -+ if (!spi_mem_controller_is_capable(ctlr, ecc)) -+ return false; -+ } -+ - return spi_mem_check_buswidth(mem, op); - } - EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -89,6 +89,7 @@ enum spi_mem_data_dir { - * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not - * @data.buswidth: number of IO lanes used to send/receive the data - * @data.dtr: whether the data should be sent in DTR mode or not -+ * @data.ecc: whether error correction is required or not - * @data.dir: direction of the transfer - * @data.nbytes: number of data bytes to send/receive. Can be zero if the - * operation does not involve transferring data -@@ -119,6 +120,7 @@ struct spi_mem_op { - struct { - u8 buswidth; - u8 dtr : 1; -+ u8 ecc : 1; - enum spi_mem_data_dir dir; - unsigned int nbytes; - union { -@@ -288,9 +290,11 @@ struct spi_controller_mem_ops { - /** - * struct spi_controller_mem_caps - SPI memory controller capabilities - * @dtr: Supports DTR operations -+ * @ecc: Supports operations with error correction - */ - struct spi_controller_mem_caps { - bool dtr; -+ bool ecc; - }; - - #define spi_mem_controller_is_capable(ctlr, cap) \ diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch deleted file mode 100644 index 192b1221e..000000000 --- a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:02 +0100 -Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation - -As we will soon tweak the dirmap creation to act a little bit -differently depending on the picked ECC engine, we need to initialize -dirmaps after ECC engines. This should not have any effect as dirmaps -are not yet used at this point. - -Signed-off-by: Miquel Raynal -Reviewed-by: Boris Brezillon -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com -(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949) ---- - drivers/mtd/nand/spi/core.c | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1210,14 +1210,6 @@ static int spinand_init(struct spinand_d - if (ret) - goto err_free_bufs; - -- ret = spinand_create_dirmaps(spinand); -- if (ret) { -- dev_err(dev, -- "Failed to create direct mappings for read/write operations (err = %d)\n", -- ret); -- goto err_manuf_cleanup; -- } -- - ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); - if (ret) - goto err_manuf_cleanup; -@@ -1252,6 +1244,14 @@ static int spinand_init(struct spinand_d - mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; - mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; - -+ ret = spinand_create_dirmaps(spinand); -+ if (ret) { -+ dev_err(dev, -+ "Failed to create direct mappings for read/write operations (err = %d)\n", -+ ret); -+ goto err_cleanup_ecc_engine; -+ } -+ - return 0; - - err_cleanup_ecc_engine: diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch deleted file mode 100644 index 86df0270d..000000000 --- a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch +++ /dev/null @@ -1,98 +0,0 @@ -From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Thu, 27 Jan 2022 10:18:03 +0100 -Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC - operations - -In order for pipelined ECC engines to be able to enable/disable the ECC -engine only when needed and avoid races when future parallel-operations -will be supported, we need to provide the information about the use of -the ECC engine in the direct mapping hooks. As direct mapping -configurations are meant to be static, it is best to create two new -mappings: one for regular 'raw' accesses and one for accesses involving -correction. It is up to the driver to use or not the new ECC enable -boolean contained in the spi-mem operation. - -As dirmaps are not free (they consume a few pages of MMIO address space) -and because these extra entries are only meant to be used by pipelined -engines, let's limit their use to this specific type of engine and save -a bit of memory with all the other setups. - -Signed-off-by: Miquel Raynal -Reviewed-by: Boris Brezillon -Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com -(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2) ---- - drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++-- - include/linux/mtd/spinand.h | 2 ++ - 2 files changed, 35 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st - } - } - -- rdesc = spinand->dirmaps[req->pos.plane].rdesc; -+ if (req->mode == MTD_OPS_RAW) -+ rdesc = spinand->dirmaps[req->pos.plane].rdesc; -+ else -+ rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; - - while (nbytes) { - ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); -@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str - req->ooblen); - } - -- wdesc = spinand->dirmaps[req->pos.plane].wdesc; -+ if (req->mode == MTD_OPS_RAW) -+ wdesc = spinand->dirmaps[req->pos.plane].wdesc; -+ else -+ wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; - - while (nbytes) { - ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); -@@ -865,6 +871,31 @@ static int spinand_create_dirmap(struct - - spinand->dirmaps[plane].rdesc = desc; - -+ if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { -+ spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; -+ spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; -+ -+ return 0; -+ } -+ -+ info.op_tmpl = *spinand->op_templates.update_cache; -+ info.op_tmpl.data.ecc = true; -+ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, -+ spinand->spimem, &info); -+ if (IS_ERR(desc)) -+ return PTR_ERR(desc); -+ -+ spinand->dirmaps[plane].wdesc_ecc = desc; -+ -+ info.op_tmpl = *spinand->op_templates.read_cache; -+ info.op_tmpl.data.ecc = true; -+ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, -+ spinand->spimem, &info); -+ if (IS_ERR(desc)) -+ return PTR_ERR(desc); -+ -+ spinand->dirmaps[plane].rdesc_ecc = desc; -+ - return 0; - } - ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -391,6 +391,8 @@ struct spinand_info { - struct spinand_dirmap { - struct spi_mem_dirmap_desc *wdesc; - struct spi_mem_dirmap_desc *rdesc; -+ struct spi_mem_dirmap_desc *wdesc_ecc; -+ struct spi_mem_dirmap_desc *rdesc_ecc; - }; - - /** diff --git a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch deleted file mode 100644 index fd9098eae..000000000 --- a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch +++ /dev/null @@ -1,1383 +0,0 @@ -From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Tue, 22 Mar 2022 18:44:21 +0800 -Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module - -this code will be used in mediatek snfi spi-mem controller with -pipelined ECC engine. - -Signed-off-by: Chuanhong Guo -(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d) ---- - drivers/mtd/nand/Kconfig | 7 +++++++ - drivers/mtd/nand/Makefile | 1 + - drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} | 3 +-- - drivers/mtd/nand/raw/Kconfig | 1 + - drivers/mtd/nand/raw/Makefile | 2 +- - drivers/mtd/nand/raw/mtk_nand.c | 2 +- - .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0 - 7 files changed, 12 insertions(+), 4 deletions(-) - rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%) - rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%) - ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT - bool "Support MediaTek NAND Bad-block Management Table" - default n - -+config MTD_NAND_ECC_MEDIATEK -+ tristate "Mediatek hardware ECC engine" -+ depends on HAS_IOMEM -+ select MTD_NAND_ECC -+ help -+ This enables support for the hardware ECC engine from Mediatek. -+ - endmenu - - endmenu ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -3,6 +3,7 @@ - nandcore-objs := core.o bbt.o - obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o - obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o -+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o - - obj-y += onenand/ - obj-y += raw/ ---- a/drivers/mtd/nand/raw/mtk_ecc.c -+++ /dev/null -@@ -1,599 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 OR MIT --/* -- * MTK ECC controller driver. -- * Copyright (C) 2016 MediaTek Inc. -- * Authors: Xiaolei Li -- * Jorge Ramirez-Ortiz -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "mtk_ecc.h" -- --#define ECC_IDLE_MASK BIT(0) --#define ECC_IRQ_EN BIT(0) --#define ECC_PG_IRQ_SEL BIT(1) --#define ECC_OP_ENABLE (1) --#define ECC_OP_DISABLE (0) -- --#define ECC_ENCCON (0x00) --#define ECC_ENCCNFG (0x04) --#define ECC_MS_SHIFT (16) --#define ECC_ENCDIADDR (0x08) --#define ECC_ENCIDLE (0x0C) --#define ECC_DECCON (0x100) --#define ECC_DECCNFG (0x104) --#define DEC_EMPTY_EN BIT(31) --#define DEC_CNFG_CORRECT (0x3 << 12) --#define ECC_DECIDLE (0x10C) --#define ECC_DECENUM0 (0x114) -- --#define ECC_TIMEOUT (500000) -- --#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) --#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) -- --struct mtk_ecc_caps { -- u32 err_mask; -- u32 err_shift; -- const u8 *ecc_strength; -- const u32 *ecc_regs; -- u8 num_ecc_strength; -- u8 ecc_mode_shift; -- u32 parity_bits; -- int pg_irq_sel; --}; -- --struct mtk_ecc { -- struct device *dev; -- const struct mtk_ecc_caps *caps; -- void __iomem *regs; -- struct clk *clk; -- -- struct completion done; -- struct mutex lock; -- u32 sectors; -- -- u8 *eccdata; --}; -- --/* ecc strength that each IP supports */ --static const u8 ecc_strength_mt2701[] = { -- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -- 40, 44, 48, 52, 56, 60 --}; -- --static const u8 ecc_strength_mt2712[] = { -- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -- 40, 44, 48, 52, 56, 60, 68, 72, 80 --}; -- --static const u8 ecc_strength_mt7622[] = { -- 4, 6, 8, 10, 12 --}; -- --enum mtk_ecc_regs { -- ECC_ENCPAR00, -- ECC_ENCIRQ_EN, -- ECC_ENCIRQ_STA, -- ECC_DECDONE, -- ECC_DECIRQ_EN, -- ECC_DECIRQ_STA, --}; -- --static int mt2701_ecc_regs[] = { -- [ECC_ENCPAR00] = 0x10, -- [ECC_ENCIRQ_EN] = 0x80, -- [ECC_ENCIRQ_STA] = 0x84, -- [ECC_DECDONE] = 0x124, -- [ECC_DECIRQ_EN] = 0x200, -- [ECC_DECIRQ_STA] = 0x204, --}; -- --static int mt2712_ecc_regs[] = { -- [ECC_ENCPAR00] = 0x300, -- [ECC_ENCIRQ_EN] = 0x80, -- [ECC_ENCIRQ_STA] = 0x84, -- [ECC_DECDONE] = 0x124, -- [ECC_DECIRQ_EN] = 0x200, -- [ECC_DECIRQ_STA] = 0x204, --}; -- --static int mt7622_ecc_regs[] = { -- [ECC_ENCPAR00] = 0x10, -- [ECC_ENCIRQ_EN] = 0x30, -- [ECC_ENCIRQ_STA] = 0x34, -- [ECC_DECDONE] = 0x11c, -- [ECC_DECIRQ_EN] = 0x140, -- [ECC_DECIRQ_STA] = 0x144, --}; -- --static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, -- enum mtk_ecc_operation op) --{ -- struct device *dev = ecc->dev; -- u32 val; -- int ret; -- -- ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, -- val & ECC_IDLE_MASK, -- 10, ECC_TIMEOUT); -- if (ret) -- dev_warn(dev, "%s NOT idle\n", -- op == ECC_ENCODE ? "encoder" : "decoder"); --} -- --static irqreturn_t mtk_ecc_irq(int irq, void *id) --{ -- struct mtk_ecc *ecc = id; -- u32 dec, enc; -- -- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) -- & ECC_IRQ_EN; -- if (dec) { -- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -- if (dec & ecc->sectors) { -- /* -- * Clear decode IRQ status once again to ensure that -- * there will be no extra IRQ. -- */ -- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); -- ecc->sectors = 0; -- complete(&ecc->done); -- } else { -- return IRQ_HANDLED; -- } -- } else { -- enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) -- & ECC_IRQ_EN; -- if (enc) -- complete(&ecc->done); -- else -- return IRQ_NONE; -- } -- -- return IRQ_HANDLED; --} -- --static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) --{ -- u32 ecc_bit, dec_sz, enc_sz; -- u32 reg, i; -- -- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -- if (ecc->caps->ecc_strength[i] == config->strength) -- break; -- } -- -- if (i == ecc->caps->num_ecc_strength) { -- dev_err(ecc->dev, "invalid ecc strength %d\n", -- config->strength); -- return -EINVAL; -- } -- -- ecc_bit = i; -- -- if (config->op == ECC_ENCODE) { -- /* configure ECC encoder (in bits) */ -- enc_sz = config->len << 3; -- -- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -- reg |= (enc_sz << ECC_MS_SHIFT); -- writel(reg, ecc->regs + ECC_ENCCNFG); -- -- if (config->mode != ECC_NFI_MODE) -- writel(lower_32_bits(config->addr), -- ecc->regs + ECC_ENCDIADDR); -- -- } else { -- /* configure ECC decoder (in bits) */ -- dec_sz = (config->len << 3) + -- config->strength * ecc->caps->parity_bits; -- -- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -- reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; -- reg |= DEC_EMPTY_EN; -- writel(reg, ecc->regs + ECC_DECCNFG); -- -- if (config->sectors) -- ecc->sectors = 1 << (config->sectors - 1); -- } -- -- return 0; --} -- --void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, -- int sectors) --{ -- u32 offset, i, err; -- u32 bitflips = 0; -- -- stats->corrected = 0; -- stats->failed = 0; -- -- for (i = 0; i < sectors; i++) { -- offset = (i >> 2) << 2; -- err = readl(ecc->regs + ECC_DECENUM0 + offset); -- err = err >> ((i % 4) * ecc->caps->err_shift); -- err &= ecc->caps->err_mask; -- if (err == ecc->caps->err_mask) { -- /* uncorrectable errors */ -- stats->failed++; -- continue; -- } -- -- stats->corrected += err; -- bitflips = max_t(u32, bitflips, err); -- } -- -- stats->bitflips = bitflips; --} --EXPORT_SYMBOL(mtk_ecc_get_stats); -- --void mtk_ecc_release(struct mtk_ecc *ecc) --{ -- clk_disable_unprepare(ecc->clk); -- put_device(ecc->dev); --} --EXPORT_SYMBOL(mtk_ecc_release); -- --static void mtk_ecc_hw_init(struct mtk_ecc *ecc) --{ -- mtk_ecc_wait_idle(ecc, ECC_ENCODE); -- writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); -- -- mtk_ecc_wait_idle(ecc, ECC_DECODE); -- writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); --} -- --static struct mtk_ecc *mtk_ecc_get(struct device_node *np) --{ -- struct platform_device *pdev; -- struct mtk_ecc *ecc; -- -- pdev = of_find_device_by_node(np); -- if (!pdev) -- return ERR_PTR(-EPROBE_DEFER); -- -- ecc = platform_get_drvdata(pdev); -- if (!ecc) { -- put_device(&pdev->dev); -- return ERR_PTR(-EPROBE_DEFER); -- } -- -- clk_prepare_enable(ecc->clk); -- mtk_ecc_hw_init(ecc); -- -- return ecc; --} -- --struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) --{ -- struct mtk_ecc *ecc = NULL; -- struct device_node *np; -- -- np = of_parse_phandle(of_node, "ecc-engine", 0); -- if (np) { -- ecc = mtk_ecc_get(np); -- of_node_put(np); -- } -- -- return ecc; --} --EXPORT_SYMBOL(of_mtk_ecc_get); -- --int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) --{ -- enum mtk_ecc_operation op = config->op; -- u16 reg_val; -- int ret; -- -- ret = mutex_lock_interruptible(&ecc->lock); -- if (ret) { -- dev_err(ecc->dev, "interrupted when attempting to lock\n"); -- return ret; -- } -- -- mtk_ecc_wait_idle(ecc, op); -- -- ret = mtk_ecc_config(ecc, config); -- if (ret) { -- mutex_unlock(&ecc->lock); -- return ret; -- } -- -- if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { -- init_completion(&ecc->done); -- reg_val = ECC_IRQ_EN; -- /* -- * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it -- * means this chip can only generate one ecc irq during page -- * read / write. If is 0, generate one ecc irq each ecc step. -- */ -- if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) -- reg_val |= ECC_PG_IRQ_SEL; -- if (op == ECC_ENCODE) -- writew(reg_val, ecc->regs + -- ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -- else -- writew(reg_val, ecc->regs + -- ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -- } -- -- writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); -- -- return 0; --} --EXPORT_SYMBOL(mtk_ecc_enable); -- --void mtk_ecc_disable(struct mtk_ecc *ecc) --{ -- enum mtk_ecc_operation op = ECC_ENCODE; -- -- /* find out the running operation */ -- if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) -- op = ECC_DECODE; -- -- /* disable it */ -- mtk_ecc_wait_idle(ecc, op); -- if (op == ECC_DECODE) { -- /* -- * Clear decode IRQ status in case there is a timeout to wait -- * decode IRQ. -- */ -- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -- } else { -- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -- } -- -- writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); -- -- mutex_unlock(&ecc->lock); --} --EXPORT_SYMBOL(mtk_ecc_disable); -- --int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) --{ -- int ret; -- -- ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); -- if (!ret) { -- dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", -- (op == ECC_ENCODE) ? "encoder" : "decoder"); -- return -ETIMEDOUT; -- } -- -- return 0; --} --EXPORT_SYMBOL(mtk_ecc_wait_done); -- --int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, -- u8 *data, u32 bytes) --{ -- dma_addr_t addr; -- u32 len; -- int ret; -- -- addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); -- ret = dma_mapping_error(ecc->dev, addr); -- if (ret) { -- dev_err(ecc->dev, "dma mapping error\n"); -- return -EINVAL; -- } -- -- config->op = ECC_ENCODE; -- config->addr = addr; -- ret = mtk_ecc_enable(ecc, config); -- if (ret) { -- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -- return ret; -- } -- -- ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); -- if (ret) -- goto timeout; -- -- mtk_ecc_wait_idle(ecc, ECC_ENCODE); -- -- /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ -- len = (config->strength * ecc->caps->parity_bits + 7) >> 3; -- -- /* write the parity bytes generated by the ECC back to temp buffer */ -- __ioread32_copy(ecc->eccdata, -- ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], -- round_up(len, 4)); -- -- /* copy into possibly unaligned OOB region with actual length */ -- memcpy(data + bytes, ecc->eccdata, len); --timeout: -- -- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -- mtk_ecc_disable(ecc); -- -- return ret; --} --EXPORT_SYMBOL(mtk_ecc_encode); -- --void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) --{ -- const u8 *ecc_strength = ecc->caps->ecc_strength; -- int i; -- -- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -- if (*p <= ecc_strength[i]) { -- if (!i) -- *p = ecc_strength[i]; -- else if (*p != ecc_strength[i]) -- *p = ecc_strength[i - 1]; -- return; -- } -- } -- -- *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; --} --EXPORT_SYMBOL(mtk_ecc_adjust_strength); -- --unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) --{ -- return ecc->caps->parity_bits; --} --EXPORT_SYMBOL(mtk_ecc_get_parity_bits); -- --static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { -- .err_mask = 0x3f, -- .err_shift = 8, -- .ecc_strength = ecc_strength_mt2701, -- .ecc_regs = mt2701_ecc_regs, -- .num_ecc_strength = 20, -- .ecc_mode_shift = 5, -- .parity_bits = 14, -- .pg_irq_sel = 0, --}; -- --static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { -- .err_mask = 0x7f, -- .err_shift = 8, -- .ecc_strength = ecc_strength_mt2712, -- .ecc_regs = mt2712_ecc_regs, -- .num_ecc_strength = 23, -- .ecc_mode_shift = 5, -- .parity_bits = 14, -- .pg_irq_sel = 1, --}; -- --static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { -- .err_mask = 0x1f, -- .err_shift = 5, -- .ecc_strength = ecc_strength_mt7622, -- .ecc_regs = mt7622_ecc_regs, -- .num_ecc_strength = 5, -- .ecc_mode_shift = 4, -- .parity_bits = 13, -- .pg_irq_sel = 0, --}; -- --static const struct of_device_id mtk_ecc_dt_match[] = { -- { -- .compatible = "mediatek,mt2701-ecc", -- .data = &mtk_ecc_caps_mt2701, -- }, { -- .compatible = "mediatek,mt2712-ecc", -- .data = &mtk_ecc_caps_mt2712, -- }, { -- .compatible = "mediatek,mt7622-ecc", -- .data = &mtk_ecc_caps_mt7622, -- }, -- {}, --}; -- --static int mtk_ecc_probe(struct platform_device *pdev) --{ -- struct device *dev = &pdev->dev; -- struct mtk_ecc *ecc; -- struct resource *res; -- u32 max_eccdata_size; -- int irq, ret; -- -- ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); -- if (!ecc) -- return -ENOMEM; -- -- ecc->caps = of_device_get_match_data(dev); -- -- max_eccdata_size = ecc->caps->num_ecc_strength - 1; -- max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; -- max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; -- max_eccdata_size = round_up(max_eccdata_size, 4); -- ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); -- if (!ecc->eccdata) -- return -ENOMEM; -- -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- ecc->regs = devm_ioremap_resource(dev, res); -- if (IS_ERR(ecc->regs)) -- return PTR_ERR(ecc->regs); -- -- ecc->clk = devm_clk_get(dev, NULL); -- if (IS_ERR(ecc->clk)) { -- dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); -- return PTR_ERR(ecc->clk); -- } -- -- irq = platform_get_irq(pdev, 0); -- if (irq < 0) -- return irq; -- -- ret = dma_set_mask(dev, DMA_BIT_MASK(32)); -- if (ret) { -- dev_err(dev, "failed to set DMA mask\n"); -- return ret; -- } -- -- ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); -- if (ret) { -- dev_err(dev, "failed to request irq\n"); -- return -EINVAL; -- } -- -- ecc->dev = dev; -- mutex_init(&ecc->lock); -- platform_set_drvdata(pdev, ecc); -- dev_info(dev, "probed\n"); -- -- return 0; --} -- --#ifdef CONFIG_PM_SLEEP --static int mtk_ecc_suspend(struct device *dev) --{ -- struct mtk_ecc *ecc = dev_get_drvdata(dev); -- -- clk_disable_unprepare(ecc->clk); -- -- return 0; --} -- --static int mtk_ecc_resume(struct device *dev) --{ -- struct mtk_ecc *ecc = dev_get_drvdata(dev); -- int ret; -- -- ret = clk_prepare_enable(ecc->clk); -- if (ret) { -- dev_err(dev, "failed to enable clk\n"); -- return ret; -- } -- -- return 0; --} -- --static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); --#endif -- --MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); -- --static struct platform_driver mtk_ecc_driver = { -- .probe = mtk_ecc_probe, -- .driver = { -- .name = "mtk-ecc", -- .of_match_table = of_match_ptr(mtk_ecc_dt_match), --#ifdef CONFIG_PM_SLEEP -- .pm = &mtk_ecc_pm_ops, --#endif -- }, --}; -- --module_platform_driver(mtk_ecc_driver); -- --MODULE_AUTHOR("Xiaolei Li "); --MODULE_DESCRIPTION("MTK Nand ECC Driver"); --MODULE_LICENSE("Dual MIT/GPL"); ---- /dev/null -+++ b/drivers/mtd/nand/ecc-mtk.c -@@ -0,0 +1,598 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* -+ * MTK ECC controller driver. -+ * Copyright (C) 2016 MediaTek Inc. -+ * Authors: Xiaolei Li -+ * Jorge Ramirez-Ortiz -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define ECC_IDLE_MASK BIT(0) -+#define ECC_IRQ_EN BIT(0) -+#define ECC_PG_IRQ_SEL BIT(1) -+#define ECC_OP_ENABLE (1) -+#define ECC_OP_DISABLE (0) -+ -+#define ECC_ENCCON (0x00) -+#define ECC_ENCCNFG (0x04) -+#define ECC_MS_SHIFT (16) -+#define ECC_ENCDIADDR (0x08) -+#define ECC_ENCIDLE (0x0C) -+#define ECC_DECCON (0x100) -+#define ECC_DECCNFG (0x104) -+#define DEC_EMPTY_EN BIT(31) -+#define DEC_CNFG_CORRECT (0x3 << 12) -+#define ECC_DECIDLE (0x10C) -+#define ECC_DECENUM0 (0x114) -+ -+#define ECC_TIMEOUT (500000) -+ -+#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) -+#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) -+ -+struct mtk_ecc_caps { -+ u32 err_mask; -+ u32 err_shift; -+ const u8 *ecc_strength; -+ const u32 *ecc_regs; -+ u8 num_ecc_strength; -+ u8 ecc_mode_shift; -+ u32 parity_bits; -+ int pg_irq_sel; -+}; -+ -+struct mtk_ecc { -+ struct device *dev; -+ const struct mtk_ecc_caps *caps; -+ void __iomem *regs; -+ struct clk *clk; -+ -+ struct completion done; -+ struct mutex lock; -+ u32 sectors; -+ -+ u8 *eccdata; -+}; -+ -+/* ecc strength that each IP supports */ -+static const u8 ecc_strength_mt2701[] = { -+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -+ 40, 44, 48, 52, 56, 60 -+}; -+ -+static const u8 ecc_strength_mt2712[] = { -+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, -+ 40, 44, 48, 52, 56, 60, 68, 72, 80 -+}; -+ -+static const u8 ecc_strength_mt7622[] = { -+ 4, 6, 8, 10, 12 -+}; -+ -+enum mtk_ecc_regs { -+ ECC_ENCPAR00, -+ ECC_ENCIRQ_EN, -+ ECC_ENCIRQ_STA, -+ ECC_DECDONE, -+ ECC_DECIRQ_EN, -+ ECC_DECIRQ_STA, -+}; -+ -+static int mt2701_ecc_regs[] = { -+ [ECC_ENCPAR00] = 0x10, -+ [ECC_ENCIRQ_EN] = 0x80, -+ [ECC_ENCIRQ_STA] = 0x84, -+ [ECC_DECDONE] = 0x124, -+ [ECC_DECIRQ_EN] = 0x200, -+ [ECC_DECIRQ_STA] = 0x204, -+}; -+ -+static int mt2712_ecc_regs[] = { -+ [ECC_ENCPAR00] = 0x300, -+ [ECC_ENCIRQ_EN] = 0x80, -+ [ECC_ENCIRQ_STA] = 0x84, -+ [ECC_DECDONE] = 0x124, -+ [ECC_DECIRQ_EN] = 0x200, -+ [ECC_DECIRQ_STA] = 0x204, -+}; -+ -+static int mt7622_ecc_regs[] = { -+ [ECC_ENCPAR00] = 0x10, -+ [ECC_ENCIRQ_EN] = 0x30, -+ [ECC_ENCIRQ_STA] = 0x34, -+ [ECC_DECDONE] = 0x11c, -+ [ECC_DECIRQ_EN] = 0x140, -+ [ECC_DECIRQ_STA] = 0x144, -+}; -+ -+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, -+ enum mtk_ecc_operation op) -+{ -+ struct device *dev = ecc->dev; -+ u32 val; -+ int ret; -+ -+ ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, -+ val & ECC_IDLE_MASK, -+ 10, ECC_TIMEOUT); -+ if (ret) -+ dev_warn(dev, "%s NOT idle\n", -+ op == ECC_ENCODE ? "encoder" : "decoder"); -+} -+ -+static irqreturn_t mtk_ecc_irq(int irq, void *id) -+{ -+ struct mtk_ecc *ecc = id; -+ u32 dec, enc; -+ -+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) -+ & ECC_IRQ_EN; -+ if (dec) { -+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -+ if (dec & ecc->sectors) { -+ /* -+ * Clear decode IRQ status once again to ensure that -+ * there will be no extra IRQ. -+ */ -+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); -+ ecc->sectors = 0; -+ complete(&ecc->done); -+ } else { -+ return IRQ_HANDLED; -+ } -+ } else { -+ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) -+ & ECC_IRQ_EN; -+ if (enc) -+ complete(&ecc->done); -+ else -+ return IRQ_NONE; -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) -+{ -+ u32 ecc_bit, dec_sz, enc_sz; -+ u32 reg, i; -+ -+ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -+ if (ecc->caps->ecc_strength[i] == config->strength) -+ break; -+ } -+ -+ if (i == ecc->caps->num_ecc_strength) { -+ dev_err(ecc->dev, "invalid ecc strength %d\n", -+ config->strength); -+ return -EINVAL; -+ } -+ -+ ecc_bit = i; -+ -+ if (config->op == ECC_ENCODE) { -+ /* configure ECC encoder (in bits) */ -+ enc_sz = config->len << 3; -+ -+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -+ reg |= (enc_sz << ECC_MS_SHIFT); -+ writel(reg, ecc->regs + ECC_ENCCNFG); -+ -+ if (config->mode != ECC_NFI_MODE) -+ writel(lower_32_bits(config->addr), -+ ecc->regs + ECC_ENCDIADDR); -+ -+ } else { -+ /* configure ECC decoder (in bits) */ -+ dec_sz = (config->len << 3) + -+ config->strength * ecc->caps->parity_bits; -+ -+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); -+ reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; -+ reg |= DEC_EMPTY_EN; -+ writel(reg, ecc->regs + ECC_DECCNFG); -+ -+ if (config->sectors) -+ ecc->sectors = 1 << (config->sectors - 1); -+ } -+ -+ return 0; -+} -+ -+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, -+ int sectors) -+{ -+ u32 offset, i, err; -+ u32 bitflips = 0; -+ -+ stats->corrected = 0; -+ stats->failed = 0; -+ -+ for (i = 0; i < sectors; i++) { -+ offset = (i >> 2) << 2; -+ err = readl(ecc->regs + ECC_DECENUM0 + offset); -+ err = err >> ((i % 4) * ecc->caps->err_shift); -+ err &= ecc->caps->err_mask; -+ if (err == ecc->caps->err_mask) { -+ /* uncorrectable errors */ -+ stats->failed++; -+ continue; -+ } -+ -+ stats->corrected += err; -+ bitflips = max_t(u32, bitflips, err); -+ } -+ -+ stats->bitflips = bitflips; -+} -+EXPORT_SYMBOL(mtk_ecc_get_stats); -+ -+void mtk_ecc_release(struct mtk_ecc *ecc) -+{ -+ clk_disable_unprepare(ecc->clk); -+ put_device(ecc->dev); -+} -+EXPORT_SYMBOL(mtk_ecc_release); -+ -+static void mtk_ecc_hw_init(struct mtk_ecc *ecc) -+{ -+ mtk_ecc_wait_idle(ecc, ECC_ENCODE); -+ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); -+ -+ mtk_ecc_wait_idle(ecc, ECC_DECODE); -+ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); -+} -+ -+static struct mtk_ecc *mtk_ecc_get(struct device_node *np) -+{ -+ struct platform_device *pdev; -+ struct mtk_ecc *ecc; -+ -+ pdev = of_find_device_by_node(np); -+ if (!pdev) -+ return ERR_PTR(-EPROBE_DEFER); -+ -+ ecc = platform_get_drvdata(pdev); -+ if (!ecc) { -+ put_device(&pdev->dev); -+ return ERR_PTR(-EPROBE_DEFER); -+ } -+ -+ clk_prepare_enable(ecc->clk); -+ mtk_ecc_hw_init(ecc); -+ -+ return ecc; -+} -+ -+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) -+{ -+ struct mtk_ecc *ecc = NULL; -+ struct device_node *np; -+ -+ np = of_parse_phandle(of_node, "ecc-engine", 0); -+ if (np) { -+ ecc = mtk_ecc_get(np); -+ of_node_put(np); -+ } -+ -+ return ecc; -+} -+EXPORT_SYMBOL(of_mtk_ecc_get); -+ -+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) -+{ -+ enum mtk_ecc_operation op = config->op; -+ u16 reg_val; -+ int ret; -+ -+ ret = mutex_lock_interruptible(&ecc->lock); -+ if (ret) { -+ dev_err(ecc->dev, "interrupted when attempting to lock\n"); -+ return ret; -+ } -+ -+ mtk_ecc_wait_idle(ecc, op); -+ -+ ret = mtk_ecc_config(ecc, config); -+ if (ret) { -+ mutex_unlock(&ecc->lock); -+ return ret; -+ } -+ -+ if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { -+ init_completion(&ecc->done); -+ reg_val = ECC_IRQ_EN; -+ /* -+ * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it -+ * means this chip can only generate one ecc irq during page -+ * read / write. If is 0, generate one ecc irq each ecc step. -+ */ -+ if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) -+ reg_val |= ECC_PG_IRQ_SEL; -+ if (op == ECC_ENCODE) -+ writew(reg_val, ecc->regs + -+ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -+ else -+ writew(reg_val, ecc->regs + -+ ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -+ } -+ -+ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); -+ -+ return 0; -+} -+EXPORT_SYMBOL(mtk_ecc_enable); -+ -+void mtk_ecc_disable(struct mtk_ecc *ecc) -+{ -+ enum mtk_ecc_operation op = ECC_ENCODE; -+ -+ /* find out the running operation */ -+ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) -+ op = ECC_DECODE; -+ -+ /* disable it */ -+ mtk_ecc_wait_idle(ecc, op); -+ if (op == ECC_DECODE) { -+ /* -+ * Clear decode IRQ status in case there is a timeout to wait -+ * decode IRQ. -+ */ -+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); -+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); -+ } else { -+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); -+ } -+ -+ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); -+ -+ mutex_unlock(&ecc->lock); -+} -+EXPORT_SYMBOL(mtk_ecc_disable); -+ -+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) -+{ -+ int ret; -+ -+ ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); -+ if (!ret) { -+ dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", -+ (op == ECC_ENCODE) ? "encoder" : "decoder"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(mtk_ecc_wait_done); -+ -+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, -+ u8 *data, u32 bytes) -+{ -+ dma_addr_t addr; -+ u32 len; -+ int ret; -+ -+ addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); -+ ret = dma_mapping_error(ecc->dev, addr); -+ if (ret) { -+ dev_err(ecc->dev, "dma mapping error\n"); -+ return -EINVAL; -+ } -+ -+ config->op = ECC_ENCODE; -+ config->addr = addr; -+ ret = mtk_ecc_enable(ecc, config); -+ if (ret) { -+ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -+ return ret; -+ } -+ -+ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); -+ if (ret) -+ goto timeout; -+ -+ mtk_ecc_wait_idle(ecc, ECC_ENCODE); -+ -+ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ -+ len = (config->strength * ecc->caps->parity_bits + 7) >> 3; -+ -+ /* write the parity bytes generated by the ECC back to temp buffer */ -+ __ioread32_copy(ecc->eccdata, -+ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], -+ round_up(len, 4)); -+ -+ /* copy into possibly unaligned OOB region with actual length */ -+ memcpy(data + bytes, ecc->eccdata, len); -+timeout: -+ -+ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); -+ mtk_ecc_disable(ecc); -+ -+ return ret; -+} -+EXPORT_SYMBOL(mtk_ecc_encode); -+ -+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) -+{ -+ const u8 *ecc_strength = ecc->caps->ecc_strength; -+ int i; -+ -+ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { -+ if (*p <= ecc_strength[i]) { -+ if (!i) -+ *p = ecc_strength[i]; -+ else if (*p != ecc_strength[i]) -+ *p = ecc_strength[i - 1]; -+ return; -+ } -+ } -+ -+ *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; -+} -+EXPORT_SYMBOL(mtk_ecc_adjust_strength); -+ -+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) -+{ -+ return ecc->caps->parity_bits; -+} -+EXPORT_SYMBOL(mtk_ecc_get_parity_bits); -+ -+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { -+ .err_mask = 0x3f, -+ .err_shift = 8, -+ .ecc_strength = ecc_strength_mt2701, -+ .ecc_regs = mt2701_ecc_regs, -+ .num_ecc_strength = 20, -+ .ecc_mode_shift = 5, -+ .parity_bits = 14, -+ .pg_irq_sel = 0, -+}; -+ -+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { -+ .err_mask = 0x7f, -+ .err_shift = 8, -+ .ecc_strength = ecc_strength_mt2712, -+ .ecc_regs = mt2712_ecc_regs, -+ .num_ecc_strength = 23, -+ .ecc_mode_shift = 5, -+ .parity_bits = 14, -+ .pg_irq_sel = 1, -+}; -+ -+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { -+ .err_mask = 0x1f, -+ .err_shift = 5, -+ .ecc_strength = ecc_strength_mt7622, -+ .ecc_regs = mt7622_ecc_regs, -+ .num_ecc_strength = 5, -+ .ecc_mode_shift = 4, -+ .parity_bits = 13, -+ .pg_irq_sel = 0, -+}; -+ -+static const struct of_device_id mtk_ecc_dt_match[] = { -+ { -+ .compatible = "mediatek,mt2701-ecc", -+ .data = &mtk_ecc_caps_mt2701, -+ }, { -+ .compatible = "mediatek,mt2712-ecc", -+ .data = &mtk_ecc_caps_mt2712, -+ }, { -+ .compatible = "mediatek,mt7622-ecc", -+ .data = &mtk_ecc_caps_mt7622, -+ }, -+ {}, -+}; -+ -+static int mtk_ecc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mtk_ecc *ecc; -+ struct resource *res; -+ u32 max_eccdata_size; -+ int irq, ret; -+ -+ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); -+ if (!ecc) -+ return -ENOMEM; -+ -+ ecc->caps = of_device_get_match_data(dev); -+ -+ max_eccdata_size = ecc->caps->num_ecc_strength - 1; -+ max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; -+ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; -+ max_eccdata_size = round_up(max_eccdata_size, 4); -+ ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); -+ if (!ecc->eccdata) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ecc->regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(ecc->regs)) -+ return PTR_ERR(ecc->regs); -+ -+ ecc->clk = devm_clk_get(dev, NULL); -+ if (IS_ERR(ecc->clk)) { -+ dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); -+ return PTR_ERR(ecc->clk); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = dma_set_mask(dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(dev, "failed to set DMA mask\n"); -+ return ret; -+ } -+ -+ ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); -+ if (ret) { -+ dev_err(dev, "failed to request irq\n"); -+ return -EINVAL; -+ } -+ -+ ecc->dev = dev; -+ mutex_init(&ecc->lock); -+ platform_set_drvdata(pdev, ecc); -+ dev_info(dev, "probed\n"); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM_SLEEP -+static int mtk_ecc_suspend(struct device *dev) -+{ -+ struct mtk_ecc *ecc = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(ecc->clk); -+ -+ return 0; -+} -+ -+static int mtk_ecc_resume(struct device *dev) -+{ -+ struct mtk_ecc *ecc = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = clk_prepare_enable(ecc->clk); -+ if (ret) { -+ dev_err(dev, "failed to enable clk\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); -+#endif -+ -+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); -+ -+static struct platform_driver mtk_ecc_driver = { -+ .probe = mtk_ecc_probe, -+ .driver = { -+ .name = "mtk-ecc", -+ .of_match_table = of_match_ptr(mtk_ecc_dt_match), -+#ifdef CONFIG_PM_SLEEP -+ .pm = &mtk_ecc_pm_ops, -+#endif -+ }, -+}; -+ -+module_platform_driver(mtk_ecc_driver); -+ -+MODULE_AUTHOR("Xiaolei Li "); -+MODULE_DESCRIPTION("MTK Nand ECC Driver"); -+MODULE_LICENSE("Dual MIT/GPL"); ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -360,6 +360,7 @@ config MTD_NAND_QCOM - - config MTD_NAND_MTK - tristate "MTK NAND controller" -+ depends on MTD_NAND_ECC_MEDIATEK - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - help ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ - obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o --obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o -+obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o - obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o - obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o - obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o ---- a/drivers/mtd/nand/raw/mtk_nand.c -+++ b/drivers/mtd/nand/raw/mtk_nand.c -@@ -17,7 +17,7 @@ - #include - #include - #include --#include "mtk_ecc.h" -+#include - - /* NAND controller register definition */ - #define NFI_CNFG (0x00) ---- a/drivers/mtd/nand/raw/mtk_ecc.h -+++ /dev/null -@@ -1,47 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 OR MIT */ --/* -- * MTK SDG1 ECC controller -- * -- * Copyright (c) 2016 Mediatek -- * Authors: Xiaolei Li -- * Jorge Ramirez-Ortiz -- */ -- --#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ --#define __DRIVERS_MTD_NAND_MTK_ECC_H__ -- --#include -- --enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; --enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; -- --struct device_node; --struct mtk_ecc; -- --struct mtk_ecc_stats { -- u32 corrected; -- u32 bitflips; -- u32 failed; --}; -- --struct mtk_ecc_config { -- enum mtk_ecc_operation op; -- enum mtk_ecc_mode mode; -- dma_addr_t addr; -- u32 strength; -- u32 sectors; -- u32 len; --}; -- --int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); --void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); --int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); --int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); --void mtk_ecc_disable(struct mtk_ecc *); --void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); --unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); -- --struct mtk_ecc *of_mtk_ecc_get(struct device_node *); --void mtk_ecc_release(struct mtk_ecc *); -- --#endif ---- /dev/null -+++ b/include/linux/mtd/nand-ecc-mtk.h -@@ -0,0 +1,47 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -+/* -+ * MTK SDG1 ECC controller -+ * -+ * Copyright (c) 2016 Mediatek -+ * Authors: Xiaolei Li -+ * Jorge Ramirez-Ortiz -+ */ -+ -+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ -+#define __DRIVERS_MTD_NAND_MTK_ECC_H__ -+ -+#include -+ -+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; -+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; -+ -+struct device_node; -+struct mtk_ecc; -+ -+struct mtk_ecc_stats { -+ u32 corrected; -+ u32 bitflips; -+ u32 failed; -+}; -+ -+struct mtk_ecc_config { -+ enum mtk_ecc_operation op; -+ enum mtk_ecc_mode mode; -+ dma_addr_t addr; -+ u32 strength; -+ u32 sectors; -+ u32 len; -+}; -+ -+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); -+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); -+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); -+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); -+void mtk_ecc_disable(struct mtk_ecc *); -+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); -+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); -+ -+struct mtk_ecc *of_mtk_ecc_get(struct device_node *); -+void mtk_ecc_release(struct mtk_ecc *); -+ -+#endif diff --git a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch deleted file mode 100644 index ed2090501..000000000 --- a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch +++ /dev/null @@ -1,1537 +0,0 @@ -From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sat, 2 Apr 2022 10:16:11 +0800 -Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface - -This driver implements support for the SPI-NAND mode of MTK NAND Flash -Interface as a SPI-MEM controller with pipelined ECC capability. - -Signed-off-by: Chuanhong Guo -Tested-by: Daniel Golle ---- -Change since v1: - fix CI warnings - -Changes since v2: - use streamed DMA api to avoid an extra memory copy during read - make ECC engine config a per-nand context - take user-requested ECC strength into account - -Change since v3: none -Changes since v4: - fix missing OOB write - print page format with dev_dbg - replace uint*_t copied from vendor driver with u* - -Changes since v5: - add missing nfi mode register configuration in probe - fix an off-by-one bug in mtk_snand_mac_io - - drivers/spi/Kconfig | 10 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 1481 insertions(+) - create mode 100644 drivers/spi/spi-mtk-snfi.c - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -529,6 +529,16 @@ config SPI_MTK_NOR - SPI interface as well as several SPI NOR specific instructions - via SPI MEM interface. - -+config SPI_MTK_SNFI -+ tristate "MediaTek SPI NAND Flash Interface" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ depends on MTD_NAND_ECC_MEDIATEK -+ help -+ This enables support for SPI-NAND mode on the MediaTek NAND -+ Flash Interface found on MediaTek ARM SoCs. This controller -+ is implemented as a SPI-MEM controller with pipelined ECC -+ capcability. -+ - config SPI_NPCM_FIU - tristate "Nuvoton NPCM FLASH Interface Unit" - depends on ARCH_NPCM || COMPILE_TEST ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52x - obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o - obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o - obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o -+obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o - obj-$(CONFIG_SPI_MXIC) += spi-mxic.o - obj-$(CONFIG_SPI_MXS) += spi-mxs.o - obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o ---- /dev/null -+++ b/drivers/spi/spi-mtk-snfi.c -@@ -0,0 +1,1470 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface -+// -+// Copyright (c) 2022 Chuanhong Guo -+// -+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK: -+// -+// Copyright (C) 2020 MediaTek Inc. -+// Author: Weijie Gao -+// -+// This controller organize the page data as several interleaved sectors -+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size) -+// +---------+------+------+---------+------+------+-----+ -+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... | -+// +---------+------+------+---------+------+------+-----+ -+// With auto-format turned on, DMA only returns this part: -+// +---------+---------+-----+ -+// | Sector1 | Sector2 | ... | -+// +---------+---------+-----+ -+// The FDM data will be filled to the registers, and ECC parity data isn't -+// accessible. -+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA -+// in it's original order shown in the first table. ECC can't be turned on when -+// auto-format is off. -+// -+// However, Linux SPI-NAND driver expects the data returned as: -+// +------+-----+ -+// | Page | OOB | -+// +------+-----+ -+// where the page data is continuously stored instead of interleaved. -+// So we assume all instructions matching the page_op template between ECC -+// prepare_io_req and finish_io_req are for page cache r/w. -+// Here's how this spi-mem driver operates when reading: -+// 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off). -+// 2. Perform page ops and let the controller fill the DMA bounce buffer with -+// de-interleaved sector data and set FDM registers. -+// 3. Return the data as: -+// +---------+---------+-----+------+------+-----+ -+// | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... | -+// +---------+---------+-----+------+------+-----+ -+// 4. For other matching spi_mem ops outside a prepare/finish_io_req pair, -+// read the data with auto-format off into the bounce buffer and copy -+// needed data to the buffer specified in the request. -+// -+// Write requests operates in a similar manner. -+// As a limitation of this strategy, we won't be able to access any ECC parity -+// data at all in Linux. -+// -+// Here's the bad block mark situation on MTK chips: -+// In older chips like mt7622, MTK uses the first FDM byte in the first sector -+// as the bad block mark. After de-interleaving, this byte appears at [pagesize] -+// in the returned data, which is the BBM position expected by kernel. However, -+// the conventional bad block mark is the first byte of the OOB, which is part -+// of the last sector data in the interleaved layout. Instead of fixing their -+// hardware, MTK decided to address this inconsistency in software. On these -+// later chips, the BootROM expects the following: -+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at -+// (page_size - (nsectors - 1) * spare_size) in the DMA buffer. -+// 2. The original byte stored at that position in the DMA buffer will be stored -+// as the first byte of the FDM section in the last sector. -+// We can't disagree with the BootROM, so after de-interleaving, we need to -+// perform the following swaps in read: -+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size], -+// which is the expected BBM position by kernel. -+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to -+// [page_size - (nsectors - 1) * spare_size] -+// Similarly, when writing, we need to perform swaps in the other direction. -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+// NFI registers -+#define NFI_CNFG 0x000 -+#define CNFG_OP_MODE_S 12 -+#define CNFG_OP_MODE_CUST 6 -+#define CNFG_OP_MODE_PROGRAM 3 -+#define CNFG_AUTO_FMT_EN BIT(9) -+#define CNFG_HW_ECC_EN BIT(8) -+#define CNFG_DMA_BURST_EN BIT(2) -+#define CNFG_READ_MODE BIT(1) -+#define CNFG_DMA_MODE BIT(0) -+ -+#define NFI_PAGEFMT 0x0004 -+#define NFI_SPARE_SIZE_LS_S 16 -+#define NFI_FDM_ECC_NUM_S 12 -+#define NFI_FDM_NUM_S 8 -+#define NFI_SPARE_SIZE_S 4 -+#define NFI_SEC_SEL_512 BIT(2) -+#define NFI_PAGE_SIZE_S 0 -+#define NFI_PAGE_SIZE_512_2K 0 -+#define NFI_PAGE_SIZE_2K_4K 1 -+#define NFI_PAGE_SIZE_4K_8K 2 -+#define NFI_PAGE_SIZE_8K_16K 3 -+ -+#define NFI_CON 0x008 -+#define CON_SEC_NUM_S 12 -+#define CON_BWR BIT(9) -+#define CON_BRD BIT(8) -+#define CON_NFI_RST BIT(1) -+#define CON_FIFO_FLUSH BIT(0) -+ -+#define NFI_INTR_EN 0x010 -+#define NFI_INTR_STA 0x014 -+#define NFI_IRQ_INTR_EN BIT(31) -+#define NFI_IRQ_CUS_READ BIT(8) -+#define NFI_IRQ_CUS_PG BIT(7) -+ -+#define NFI_CMD 0x020 -+#define NFI_CMD_DUMMY_READ 0x00 -+#define NFI_CMD_DUMMY_WRITE 0x80 -+ -+#define NFI_STRDATA 0x040 -+#define STR_DATA BIT(0) -+ -+#define NFI_STA 0x060 -+#define NFI_NAND_FSM GENMASK(28, 24) -+#define NFI_FSM GENMASK(19, 16) -+#define READ_EMPTY BIT(12) -+ -+#define NFI_FIFOSTA 0x064 -+#define FIFO_WR_REMAIN_S 8 -+#define FIFO_RD_REMAIN_S 0 -+ -+#define NFI_ADDRCNTR 0x070 -+#define SEC_CNTR GENMASK(16, 12) -+#define SEC_CNTR_S 12 -+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) -+ -+#define NFI_STRADDR 0x080 -+ -+#define NFI_BYTELEN 0x084 -+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) -+ -+#define NFI_FDM0L 0x0a0 -+#define NFI_FDM0M 0x0a4 -+#define NFI_FDML(n) (NFI_FDM0L + (n)*8) -+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8) -+ -+#define NFI_DEBUG_CON1 0x220 -+#define WBUF_EN BIT(2) -+ -+#define NFI_MASTERSTA 0x224 -+#define MAS_ADDR GENMASK(11, 9) -+#define MAS_RD GENMASK(8, 6) -+#define MAS_WR GENMASK(5, 3) -+#define MAS_RDDLY GENMASK(2, 0) -+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) -+ -+// SNFI registers -+#define SNF_MAC_CTL 0x500 -+#define MAC_XIO_SEL BIT(4) -+#define SF_MAC_EN BIT(3) -+#define SF_TRIG BIT(2) -+#define WIP_READY BIT(1) -+#define WIP BIT(0) -+ -+#define SNF_MAC_OUTL 0x504 -+#define SNF_MAC_INL 0x508 -+ -+#define SNF_RD_CTL2 0x510 -+#define DATA_READ_DUMMY_S 8 -+#define DATA_READ_MAX_DUMMY 0xf -+#define DATA_READ_CMD_S 0 -+ -+#define SNF_RD_CTL3 0x514 -+ -+#define SNF_PG_CTL1 0x524 -+#define PG_LOAD_CMD_S 8 -+ -+#define SNF_PG_CTL2 0x528 -+ -+#define SNF_MISC_CTL 0x538 -+#define SW_RST BIT(28) -+#define FIFO_RD_LTC_S 25 -+#define PG_LOAD_X4_EN BIT(20) -+#define DATA_READ_MODE_S 16 -+#define DATA_READ_MODE GENMASK(18, 16) -+#define DATA_READ_MODE_X1 0 -+#define DATA_READ_MODE_X2 1 -+#define DATA_READ_MODE_X4 2 -+#define DATA_READ_MODE_DUAL 5 -+#define DATA_READ_MODE_QUAD 6 -+#define PG_LOAD_CUSTOM_EN BIT(7) -+#define DATARD_CUSTOM_EN BIT(6) -+#define CS_DESELECT_CYC_S 0 -+ -+#define SNF_MISC_CTL2 0x53c -+#define PROGRAM_LOAD_BYTE_NUM_S 16 -+#define READ_DATA_BYTE_NUM_S 11 -+ -+#define SNF_DLY_CTL3 0x548 -+#define SFCK_SAM_DLY_S 0 -+ -+#define SNF_STA_CTL1 0x550 -+#define CUS_PG_DONE BIT(28) -+#define CUS_READ_DONE BIT(27) -+#define SPI_STATE_S 0 -+#define SPI_STATE GENMASK(3, 0) -+ -+#define SNF_CFG 0x55c -+#define SPI_MODE BIT(0) -+ -+#define SNF_GPRAM 0x800 -+#define SNF_GPRAM_SIZE 0xa0 -+ -+#define SNFI_POLL_INTERVAL 1000000 -+ -+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; -+ -+struct mtk_snand_caps { -+ u16 sector_size; -+ u16 max_sectors; -+ u16 fdm_size; -+ u16 fdm_ecc_size; -+ u16 fifo_size; -+ -+ bool bbm_swap; -+ bool empty_page_check; -+ u32 mastersta_mask; -+ -+ const u8 *spare_sizes; -+ u32 num_spare_size; -+}; -+ -+static const struct mtk_snand_caps mt7622_snand_caps = { -+ .sector_size = 512, -+ .max_sectors = 8, -+ .fdm_size = 8, -+ .fdm_ecc_size = 1, -+ .fifo_size = 32, -+ .bbm_swap = false, -+ .empty_page_check = false, -+ .mastersta_mask = NFI_MASTERSTA_MASK_7622, -+ .spare_sizes = mt7622_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) -+}; -+ -+static const struct mtk_snand_caps mt7629_snand_caps = { -+ .sector_size = 512, -+ .max_sectors = 8, -+ .fdm_size = 8, -+ .fdm_ecc_size = 1, -+ .fifo_size = 32, -+ .bbm_swap = true, -+ .empty_page_check = false, -+ .mastersta_mask = NFI_MASTERSTA_MASK_7622, -+ .spare_sizes = mt7622_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) -+}; -+ -+struct mtk_snand_conf { -+ size_t page_size; -+ size_t oob_size; -+ u8 nsectors; -+ u8 spare_size; -+}; -+ -+struct mtk_snand { -+ struct spi_controller *ctlr; -+ struct device *dev; -+ struct clk *nfi_clk; -+ struct clk *pad_clk; -+ void __iomem *nfi_base; -+ int irq; -+ struct completion op_done; -+ const struct mtk_snand_caps *caps; -+ struct mtk_ecc_config *ecc_cfg; -+ struct mtk_ecc *ecc; -+ struct mtk_snand_conf nfi_cfg; -+ struct mtk_ecc_stats ecc_stats; -+ struct nand_ecc_engine ecc_eng; -+ bool autofmt; -+ u8 *buf; -+ size_t buf_len; -+}; -+ -+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand) -+{ -+ struct nand_ecc_engine *eng = nand->ecc.engine; -+ -+ return container_of(eng, struct mtk_snand, ecc_eng); -+} -+ -+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size) -+{ -+ if (snf->buf_len >= size) -+ return 0; -+ kfree(snf->buf); -+ snf->buf = kmalloc(size, GFP_KERNEL); -+ if (!snf->buf) -+ return -ENOMEM; -+ snf->buf_len = size; -+ memset(snf->buf, 0xff, snf->buf_len); -+ return 0; -+} -+ -+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg) -+{ -+ return readl(snf->nfi_base + reg); -+} -+ -+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val) -+{ -+ writel(val, snf->nfi_base + reg); -+} -+ -+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val) -+{ -+ writew(val, snf->nfi_base + reg); -+} -+ -+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) -+{ -+ u32 val; -+ -+ val = readl(snf->nfi_base + reg); -+ val &= ~clr; -+ val |= set; -+ writel(val, snf->nfi_base + reg); -+} -+ -+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len) -+{ -+ u32 i, val = 0, es = sizeof(u32); -+ -+ for (i = reg; i < reg + len; i++) { -+ if (i == reg || i % es == 0) -+ val = nfi_read32(snf, i & ~(es - 1)); -+ -+ *data++ = (u8)(val >> (8 * (i % es))); -+ } -+} -+ -+static int mtk_nfi_reset(struct mtk_snand *snf) -+{ -+ u32 val, fifo_mask; -+ int ret; -+ -+ nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); -+ -+ ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, -+ !(val & snf->caps->mastersta_mask), 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "NFI master is still busy after reset\n"); -+ return ret; -+ } -+ -+ ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, -+ !(val & (NFI_FSM | NFI_NAND_FSM)), 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Failed to reset NFI\n"); -+ return ret; -+ } -+ -+ fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) | -+ ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S); -+ ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, -+ !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "NFI FIFOs are not empty\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mtk_snand_mac_reset(struct mtk_snand *snf) -+{ -+ int ret; -+ u32 val; -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); -+ -+ ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, -+ !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); -+ if (ret) -+ dev_err(snf->dev, "Failed to reset SNFI MAC\n"); -+ -+ nfi_write32(snf, SNF_MISC_CTL, -+ (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S)); -+ -+ return ret; -+} -+ -+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen) -+{ -+ int ret; -+ u32 val; -+ -+ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); -+ nfi_write32(snf, SNF_MAC_OUTL, outlen); -+ nfi_write32(snf, SNF_MAC_INL, inlen); -+ -+ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); -+ -+ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, -+ val & WIP_READY, 0, SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Timed out waiting for WIP_READY\n"); -+ goto cleanup; -+ } -+ -+ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP), -+ 0, SNFI_POLL_INTERVAL); -+ if (ret) -+ dev_err(snf->dev, "Timed out waiting for WIP cleared\n"); -+ -+cleanup: -+ nfi_write32(snf, SNF_MAC_CTL, 0); -+ -+ return ret; -+} -+ -+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op) -+{ -+ u32 rx_len = 0; -+ u32 reg_offs = 0; -+ u32 val = 0; -+ const u8 *tx_buf = NULL; -+ u8 *rx_buf = NULL; -+ int i, ret; -+ u8 b; -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ rx_len = op->data.nbytes; -+ rx_buf = op->data.buf.in; -+ } else { -+ tx_buf = op->data.buf.out; -+ } -+ -+ mtk_snand_mac_reset(snf); -+ -+ for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) { -+ b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; -+ val |= b << (8 * (reg_offs % 4)); -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ -+ for (i = 0; i < op->addr.nbytes; i++, reg_offs++) { -+ b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; -+ val |= b << (8 * (reg_offs % 4)); -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ -+ for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) { -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ -+ if (op->data.dir == SPI_MEM_DATA_OUT) { -+ for (i = 0; i < op->data.nbytes; i++, reg_offs++) { -+ val |= tx_buf[i] << (8 * (reg_offs % 4)); -+ if (reg_offs % 4 == 3) { -+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); -+ val = 0; -+ } -+ } -+ } -+ -+ if (reg_offs % 4) -+ nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val); -+ -+ for (i = 0; i < reg_offs; i += 4) -+ dev_dbg(snf->dev, "%d: %08X", i, -+ nfi_read32(snf, SNF_GPRAM + i)); -+ -+ dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len); -+ -+ ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len); -+ if (ret) -+ return ret; -+ -+ if (!rx_len) -+ return 0; -+ -+ nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len); -+ return 0; -+} -+ -+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size, -+ u32 oob_size) -+{ -+ int spare_idx = -1; -+ u32 spare_size, spare_size_shift, pagesize_idx; -+ u32 sector_size_512; -+ u8 nsectors; -+ int i; -+ -+ // skip if it's already configured as required. -+ if (snf->nfi_cfg.page_size == page_size && -+ snf->nfi_cfg.oob_size == oob_size) -+ return 0; -+ -+ nsectors = page_size / snf->caps->sector_size; -+ if (nsectors > snf->caps->max_sectors) { -+ dev_err(snf->dev, "too many sectors required.\n"); -+ goto err; -+ } -+ -+ if (snf->caps->sector_size == 512) { -+ sector_size_512 = NFI_SEC_SEL_512; -+ spare_size_shift = NFI_SPARE_SIZE_S; -+ } else { -+ sector_size_512 = 0; -+ spare_size_shift = NFI_SPARE_SIZE_LS_S; -+ } -+ -+ switch (page_size) { -+ case SZ_512: -+ pagesize_idx = NFI_PAGE_SIZE_512_2K; -+ break; -+ case SZ_2K: -+ if (snf->caps->sector_size == 512) -+ pagesize_idx = NFI_PAGE_SIZE_2K_4K; -+ else -+ pagesize_idx = NFI_PAGE_SIZE_512_2K; -+ break; -+ case SZ_4K: -+ if (snf->caps->sector_size == 512) -+ pagesize_idx = NFI_PAGE_SIZE_4K_8K; -+ else -+ pagesize_idx = NFI_PAGE_SIZE_2K_4K; -+ break; -+ case SZ_8K: -+ if (snf->caps->sector_size == 512) -+ pagesize_idx = NFI_PAGE_SIZE_8K_16K; -+ else -+ pagesize_idx = NFI_PAGE_SIZE_4K_8K; -+ break; -+ case SZ_16K: -+ pagesize_idx = NFI_PAGE_SIZE_8K_16K; -+ break; -+ default: -+ dev_err(snf->dev, "unsupported page size.\n"); -+ goto err; -+ } -+ -+ spare_size = oob_size / nsectors; -+ // If we're using the 1KB sector size, HW will automatically double the -+ // spare size. We should only use half of the value in this case. -+ if (snf->caps->sector_size == 1024) -+ spare_size /= 2; -+ -+ for (i = snf->caps->num_spare_size - 1; i >= 0; i--) { -+ if (snf->caps->spare_sizes[i] <= spare_size) { -+ spare_size = snf->caps->spare_sizes[i]; -+ if (snf->caps->sector_size == 1024) -+ spare_size *= 2; -+ spare_idx = i; -+ break; -+ } -+ } -+ -+ if (spare_idx < 0) { -+ dev_err(snf->dev, "unsupported spare size: %u\n", spare_size); -+ goto err; -+ } -+ -+ nfi_write32(snf, NFI_PAGEFMT, -+ (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | -+ (snf->caps->fdm_size << NFI_FDM_NUM_S) | -+ (spare_idx << spare_size_shift) | -+ (pagesize_idx << NFI_PAGE_SIZE_S) | -+ sector_size_512); -+ -+ snf->nfi_cfg.page_size = page_size; -+ snf->nfi_cfg.oob_size = oob_size; -+ snf->nfi_cfg.nsectors = nsectors; -+ snf->nfi_cfg.spare_size = spare_size; -+ -+ dev_dbg(snf->dev, "page format: (%u + %u) * %u\n", -+ snf->caps->sector_size, spare_size, nsectors); -+ return snand_prepare_bouncebuf(snf, page_size + oob_size); -+err: -+ dev_err(snf->dev, "page size %u + %u is not supported\n", page_size, -+ oob_size); -+ return -EOPNOTSUPP; -+} -+ -+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc) -+{ -+ // ECC area is not accessible -+ return -ERANGE; -+} -+ -+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree) -+{ -+ struct nand_device *nand = mtd_to_nanddev(mtd); -+ struct mtk_snand *ms = nand_to_mtk_snand(nand); -+ -+ if (section >= ms->nfi_cfg.nsectors) -+ return -ERANGE; -+ -+ oobfree->length = ms->caps->fdm_size - 1; -+ oobfree->offset = section * ms->caps->fdm_size + 1; -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { -+ .ecc = mtk_snand_ooblayout_ecc, -+ .free = mtk_snand_ooblayout_free, -+}; -+ -+static int mtk_snand_ecc_init_ctx(struct nand_device *nand) -+{ -+ struct mtk_snand *snf = nand_to_mtk_snand(nand); -+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; -+ struct nand_ecc_props *reqs = &nand->ecc.requirements; -+ struct nand_ecc_props *user = &nand->ecc.user_conf; -+ struct mtd_info *mtd = nanddev_to_mtd(nand); -+ int step_size = 0, strength = 0, desired_correction = 0, steps; -+ bool ecc_user = false; -+ int ret; -+ u32 parity_bits, max_ecc_bytes; -+ struct mtk_ecc_config *ecc_cfg; -+ -+ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, -+ nand->memorg.oobsize); -+ if (ret) -+ return ret; -+ -+ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); -+ if (!ecc_cfg) -+ return -ENOMEM; -+ -+ nand->ecc.ctx.priv = ecc_cfg; -+ -+ if (user->step_size && user->strength) { -+ step_size = user->step_size; -+ strength = user->strength; -+ ecc_user = true; -+ } else if (reqs->step_size && reqs->strength) { -+ step_size = reqs->step_size; -+ strength = reqs->strength; -+ } -+ -+ if (step_size && strength) { -+ steps = mtd->writesize / step_size; -+ desired_correction = steps * strength; -+ strength = desired_correction / snf->nfi_cfg.nsectors; -+ } -+ -+ ecc_cfg->mode = ECC_NFI_MODE; -+ ecc_cfg->sectors = snf->nfi_cfg.nsectors; -+ ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size; -+ -+ // calculate the max possible strength under current page format -+ parity_bits = mtk_ecc_get_parity_bits(snf->ecc); -+ max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size; -+ ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits; -+ mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength); -+ -+ // if there's a user requested strength, find the minimum strength that -+ // meets the requirement. Otherwise use the maximum strength which is -+ // expected by BootROM. -+ if (ecc_user && strength) { -+ u32 s_next = ecc_cfg->strength - 1; -+ -+ while (1) { -+ mtk_ecc_adjust_strength(snf->ecc, &s_next); -+ if (s_next >= ecc_cfg->strength) -+ break; -+ if (s_next < strength) -+ break; -+ s_next = ecc_cfg->strength - 1; -+ } -+ } -+ -+ mtd_set_ooblayout(mtd, &mtk_snand_ooblayout); -+ -+ conf->step_size = snf->caps->sector_size; -+ conf->strength = ecc_cfg->strength; -+ -+ if (ecc_cfg->strength < strength) -+ dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n", -+ strength); -+ dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n", -+ ecc_cfg->strength, snf->caps->sector_size); -+ -+ return 0; -+} -+ -+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand) -+{ -+ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); -+ -+ kfree(ecc_cfg); -+} -+ -+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand, -+ struct nand_page_io_req *req) -+{ -+ struct mtk_snand *snf = nand_to_mtk_snand(nand); -+ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); -+ int ret; -+ -+ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, -+ nand->memorg.oobsize); -+ if (ret) -+ return ret; -+ snf->autofmt = true; -+ snf->ecc_cfg = ecc_cfg; -+ return 0; -+} -+ -+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand, -+ struct nand_page_io_req *req) -+{ -+ struct mtk_snand *snf = nand_to_mtk_snand(nand); -+ struct mtd_info *mtd = nanddev_to_mtd(nand); -+ -+ snf->ecc_cfg = NULL; -+ snf->autofmt = false; -+ if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ)) -+ return 0; -+ -+ if (snf->ecc_stats.failed) -+ mtd->ecc_stats.failed += snf->ecc_stats.failed; -+ mtd->ecc_stats.corrected += snf->ecc_stats.corrected; -+ return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips; -+} -+ -+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = { -+ .init_ctx = mtk_snand_ecc_init_ctx, -+ .cleanup_ctx = mtk_snand_ecc_cleanup_ctx, -+ .prepare_io_req = mtk_snand_ecc_prepare_io_req, -+ .finish_io_req = mtk_snand_ecc_finish_io_req, -+}; -+ -+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf) -+{ -+ u32 vall, valm; -+ u8 *oobptr = buf; -+ int i, j; -+ -+ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { -+ vall = nfi_read32(snf, NFI_FDML(i)); -+ valm = nfi_read32(snf, NFI_FDMM(i)); -+ -+ for (j = 0; j < snf->caps->fdm_size; j++) -+ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); -+ -+ oobptr += snf->caps->fdm_size; -+ } -+} -+ -+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf) -+{ -+ u32 fdm_size = snf->caps->fdm_size; -+ const u8 *oobptr = buf; -+ u32 vall, valm; -+ int i, j; -+ -+ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { -+ vall = 0; -+ valm = 0; -+ -+ for (j = 0; j < 8; j++) { -+ if (j < 4) -+ vall |= (j < fdm_size ? oobptr[j] : 0xff) -+ << (j * 8); -+ else -+ valm |= (j < fdm_size ? oobptr[j] : 0xff) -+ << ((j - 4) * 8); -+ } -+ -+ nfi_write32(snf, NFI_FDML(i), vall); -+ nfi_write32(snf, NFI_FDMM(i), valm); -+ -+ oobptr += fdm_size; -+ } -+} -+ -+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf) -+{ -+ u32 buf_bbm_pos, fdm_bbm_pos; -+ -+ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) -+ return; -+ -+ // swap [pagesize] byte on nand with the first fdm byte -+ // in the last sector. -+ buf_bbm_pos = snf->nfi_cfg.page_size - -+ (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size; -+ fdm_bbm_pos = snf->nfi_cfg.page_size + -+ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; -+ -+ swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]); -+} -+ -+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) -+{ -+ u32 fdm_bbm_pos1, fdm_bbm_pos2; -+ -+ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) -+ return; -+ -+ // swap the first fdm byte in the first and the last sector. -+ fdm_bbm_pos1 = snf->nfi_cfg.page_size; -+ fdm_bbm_pos2 = snf->nfi_cfg.page_size + -+ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; -+ swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]); -+} -+ -+static int mtk_snand_read_page_cache(struct mtk_snand *snf, -+ const struct spi_mem_op *op) -+{ -+ u8 *buf = snf->buf; -+ u8 *buf_fdm = buf + snf->nfi_cfg.page_size; -+ // the address part to be sent by the controller -+ u32 op_addr = op->addr.val; -+ // where to start copying data from bounce buffer -+ u32 rd_offset = 0; -+ u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth); -+ u32 op_mode = 0; -+ u32 dma_len = snf->buf_len; -+ int ret = 0; -+ u32 rd_mode, rd_bytes, val; -+ dma_addr_t buf_dma; -+ -+ if (snf->autofmt) { -+ u32 last_bit; -+ u32 mask; -+ -+ dma_len = snf->nfi_cfg.page_size; -+ op_mode = CNFG_AUTO_FMT_EN; -+ if (op->data.ecc) -+ op_mode |= CNFG_HW_ECC_EN; -+ // extract the plane bit: -+ // Find the highest bit set in (pagesize+oobsize). -+ // Bits higher than that in op->addr are kept and sent over SPI -+ // Lower bits are used as an offset for copying data from DMA -+ // bounce buffer. -+ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); -+ mask = (1 << last_bit) - 1; -+ rd_offset = op_addr & mask; -+ op_addr &= ~mask; -+ -+ // check if we can dma to the caller memory -+ if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size) -+ buf = op->data.buf.in; -+ } -+ mtk_snand_mac_reset(snf); -+ mtk_nfi_reset(snf); -+ -+ // command and dummy cycles -+ nfi_write32(snf, SNF_RD_CTL2, -+ (dummy_clk << DATA_READ_DUMMY_S) | -+ (op->cmd.opcode << DATA_READ_CMD_S)); -+ -+ // read address -+ nfi_write32(snf, SNF_RD_CTL3, op_addr); -+ -+ // Set read op_mode -+ if (op->data.buswidth == 4) -+ rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD : -+ DATA_READ_MODE_X4; -+ else if (op->data.buswidth == 2) -+ rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL : -+ DATA_READ_MODE_X2; -+ else -+ rd_mode = DATA_READ_MODE_X1; -+ rd_mode <<= DATA_READ_MODE_S; -+ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, -+ rd_mode | DATARD_CUSTOM_EN); -+ -+ // Set bytes to read -+ rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * -+ snf->nfi_cfg.nsectors; -+ nfi_write32(snf, SNF_MISC_CTL2, -+ (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes); -+ -+ // NFI read prepare -+ nfi_write16(snf, NFI_CNFG, -+ (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN | -+ CNFG_READ_MODE | CNFG_DMA_MODE | op_mode); -+ -+ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); -+ -+ buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE); -+ if (dma_mapping_error(snf->dev, buf_dma)) { -+ dev_err(snf->dev, "DMA mapping failed.\n"); -+ goto cleanup; -+ } -+ nfi_write32(snf, NFI_STRADDR, buf_dma); -+ if (op->data.ecc) { -+ snf->ecc_cfg->op = ECC_DECODE; -+ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); -+ if (ret) -+ goto cleanup_dma; -+ } -+ // Prepare for custom read interrupt -+ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); -+ reinit_completion(&snf->op_done); -+ -+ // Trigger NFI into custom mode -+ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); -+ -+ // Start DMA read -+ nfi_rmw32(snf, NFI_CON, 0, CON_BRD); -+ nfi_write16(snf, NFI_STRDATA, STR_DATA); -+ -+ if (!wait_for_completion_timeout( -+ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { -+ dev_err(snf->dev, "DMA timed out for reading from cache.\n"); -+ ret = -ETIMEDOUT; -+ goto cleanup; -+ } -+ -+ // Wait for BUS_SEC_CNTR returning expected value -+ ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, -+ BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n"); -+ goto cleanup2; -+ } -+ -+ // Wait for bus becoming idle -+ ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, -+ !(val & snf->caps->mastersta_mask), 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) { -+ dev_err(snf->dev, "Timed out waiting for bus becoming idle\n"); -+ goto cleanup2; -+ } -+ -+ if (op->data.ecc) { -+ ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE); -+ if (ret) { -+ dev_err(snf->dev, "wait ecc done timeout\n"); -+ goto cleanup2; -+ } -+ // save status before disabling ecc -+ mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats, -+ snf->nfi_cfg.nsectors); -+ } -+ -+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); -+ -+ if (snf->autofmt) { -+ mtk_snand_read_fdm(snf, buf_fdm); -+ if (snf->caps->bbm_swap) { -+ mtk_snand_bm_swap(snf, buf); -+ mtk_snand_fdm_bm_swap(snf); -+ } -+ } -+ -+ // copy data back -+ if (nfi_read32(snf, NFI_STA) & READ_EMPTY) { -+ memset(op->data.buf.in, 0xff, op->data.nbytes); -+ snf->ecc_stats.bitflips = 0; -+ snf->ecc_stats.failed = 0; -+ snf->ecc_stats.corrected = 0; -+ } else { -+ if (buf == op->data.buf.in) { -+ u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size; -+ u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size; -+ -+ if (req_left) -+ memcpy(op->data.buf.in + snf->nfi_cfg.page_size, -+ buf_fdm, -+ cap_len < req_left ? cap_len : req_left); -+ } else if (rd_offset < snf->buf_len) { -+ u32 cap_len = snf->buf_len - rd_offset; -+ -+ if (op->data.nbytes < cap_len) -+ cap_len = op->data.nbytes; -+ memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len); -+ } -+ } -+cleanup2: -+ if (op->data.ecc) -+ mtk_ecc_disable(snf->ecc); -+cleanup_dma: -+ // unmap dma only if any error happens. (otherwise it's done before -+ // data copying) -+ if (ret) -+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); -+cleanup: -+ // Stop read -+ nfi_write32(snf, NFI_CON, 0); -+ nfi_write16(snf, NFI_CNFG, 0); -+ -+ // Clear SNF done flag -+ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); -+ nfi_write32(snf, SNF_STA_CTL1, 0); -+ -+ // Disable interrupt -+ nfi_read32(snf, NFI_INTR_STA); -+ nfi_write32(snf, NFI_INTR_EN, 0); -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); -+ return ret; -+} -+ -+static int mtk_snand_write_page_cache(struct mtk_snand *snf, -+ const struct spi_mem_op *op) -+{ -+ // the address part to be sent by the controller -+ u32 op_addr = op->addr.val; -+ // where to start copying data from bounce buffer -+ u32 wr_offset = 0; -+ u32 op_mode = 0; -+ int ret = 0; -+ u32 wr_mode = 0; -+ u32 dma_len = snf->buf_len; -+ u32 wr_bytes, val; -+ size_t cap_len; -+ dma_addr_t buf_dma; -+ -+ if (snf->autofmt) { -+ u32 last_bit; -+ u32 mask; -+ -+ dma_len = snf->nfi_cfg.page_size; -+ op_mode = CNFG_AUTO_FMT_EN; -+ if (op->data.ecc) -+ op_mode |= CNFG_HW_ECC_EN; -+ -+ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); -+ mask = (1 << last_bit) - 1; -+ wr_offset = op_addr & mask; -+ op_addr &= ~mask; -+ } -+ mtk_snand_mac_reset(snf); -+ mtk_nfi_reset(snf); -+ -+ if (wr_offset) -+ memset(snf->buf, 0xff, wr_offset); -+ -+ cap_len = snf->buf_len - wr_offset; -+ if (op->data.nbytes < cap_len) -+ cap_len = op->data.nbytes; -+ memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); -+ if (snf->autofmt) { -+ if (snf->caps->bbm_swap) { -+ mtk_snand_fdm_bm_swap(snf); -+ mtk_snand_bm_swap(snf, snf->buf); -+ } -+ mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size); -+ } -+ -+ // Command -+ nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S)); -+ -+ // write address -+ nfi_write32(snf, SNF_PG_CTL2, op_addr); -+ -+ // Set read op_mode -+ if (op->data.buswidth == 4) -+ wr_mode = PG_LOAD_X4_EN; -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, -+ wr_mode | PG_LOAD_CUSTOM_EN); -+ -+ // Set bytes to write -+ wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * -+ snf->nfi_cfg.nsectors; -+ nfi_write32(snf, SNF_MISC_CTL2, -+ (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes); -+ -+ // NFI write prepare -+ nfi_write16(snf, NFI_CNFG, -+ (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | -+ CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode); -+ -+ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); -+ buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE); -+ if (dma_mapping_error(snf->dev, buf_dma)) { -+ dev_err(snf->dev, "DMA mapping failed.\n"); -+ goto cleanup; -+ } -+ nfi_write32(snf, NFI_STRADDR, buf_dma); -+ if (op->data.ecc) { -+ snf->ecc_cfg->op = ECC_ENCODE; -+ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); -+ if (ret) -+ goto cleanup_dma; -+ } -+ // Prepare for custom write interrupt -+ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); -+ reinit_completion(&snf->op_done); -+ ; -+ -+ // Trigger NFI into custom mode -+ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); -+ -+ // Start DMA write -+ nfi_rmw32(snf, NFI_CON, 0, CON_BWR); -+ nfi_write16(snf, NFI_STRDATA, STR_DATA); -+ -+ if (!wait_for_completion_timeout( -+ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { -+ dev_err(snf->dev, "DMA timed out for program load.\n"); -+ ret = -ETIMEDOUT; -+ goto cleanup_ecc; -+ } -+ -+ // Wait for NFI_SEC_CNTR returning expected value -+ ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, -+ NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, -+ SNFI_POLL_INTERVAL); -+ if (ret) -+ dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n"); -+ -+cleanup_ecc: -+ if (op->data.ecc) -+ mtk_ecc_disable(snf->ecc); -+cleanup_dma: -+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE); -+cleanup: -+ // Stop write -+ nfi_write32(snf, NFI_CON, 0); -+ nfi_write16(snf, NFI_CNFG, 0); -+ -+ // Clear SNF done flag -+ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); -+ nfi_write32(snf, SNF_STA_CTL1, 0); -+ -+ // Disable interrupt -+ nfi_read32(snf, NFI_INTR_STA); -+ nfi_write32(snf, NFI_INTR_EN, 0); -+ -+ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); -+ -+ return ret; -+} -+ -+/** -+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op. -+ * @op spi-mem op to check -+ * -+ * Check whether op can be executed with read_from_cache or program_load -+ * mode in the controller. -+ * This controller can execute typical Read From Cache and Program Load -+ * instructions found on SPI-NAND with 2-byte address. -+ * DTR and cmd buswidth & nbytes should be checked before calling this. -+ * -+ * Return: true if the op matches the instruction template -+ */ -+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op) -+{ -+ if (op->addr.nbytes != 2) -+ return false; -+ -+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && -+ op->addr.buswidth != 4) -+ return false; -+ -+ // match read from page instructions -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ // check dummy cycle first -+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > -+ DATA_READ_MAX_DUMMY) -+ return false; -+ // quad io / quad out -+ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) && -+ op->data.buswidth == 4) -+ return true; -+ -+ // dual io / dual out -+ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) && -+ op->data.buswidth == 2) -+ return true; -+ -+ // standard spi -+ if (op->addr.buswidth == 1 && op->data.buswidth == 1) -+ return true; -+ } else if (op->data.dir == SPI_MEM_DATA_OUT) { -+ // check dummy cycle first -+ if (op->dummy.nbytes) -+ return false; -+ // program load quad out -+ if (op->addr.buswidth == 1 && op->data.buswidth == 4) -+ return true; -+ // standard spi -+ if (op->addr.buswidth == 1 && op->data.buswidth == 1) -+ return true; -+ } -+ return false; -+} -+ -+static bool mtk_snand_supports_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ if (!spi_mem_default_supports_op(mem, op)) -+ return false; -+ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) -+ return false; -+ if (mtk_snand_is_page_ops(op)) -+ return true; -+ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) && -+ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) && -+ (op->data.nbytes == 0 || op->data.buswidth == 1)); -+} -+ -+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) -+{ -+ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); -+ // page ops transfer size must be exactly ((sector_size + spare_size) * -+ // nsectors). Limit the op size if the caller requests more than that. -+ // exec_op will read more than needed and discard the leftover if the -+ // caller requests less data. -+ if (mtk_snand_is_page_ops(op)) { -+ size_t l; -+ // skip adjust_op_size for page ops -+ if (ms->autofmt) -+ return 0; -+ l = ms->caps->sector_size + ms->nfi_cfg.spare_size; -+ l *= ms->nfi_cfg.nsectors; -+ if (op->data.nbytes > l) -+ op->data.nbytes = l; -+ } else { -+ size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; -+ -+ if (hl >= SNF_GPRAM_SIZE) -+ return -EOPNOTSUPP; -+ if (op->data.nbytes > SNF_GPRAM_SIZE - hl) -+ op->data.nbytes = SNF_GPRAM_SIZE - hl; -+ } -+ return 0; -+} -+ -+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) -+{ -+ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); -+ -+ dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, -+ op->addr.val, op->addr.buswidth, op->addr.nbytes, -+ op->data.buswidth, op->data.nbytes); -+ if (mtk_snand_is_page_ops(op)) { -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ return mtk_snand_read_page_cache(ms, op); -+ else -+ return mtk_snand_write_page_cache(ms, op); -+ } else { -+ return mtk_snand_mac_io(ms, op); -+ } -+} -+ -+static const struct spi_controller_mem_ops mtk_snand_mem_ops = { -+ .adjust_op_size = mtk_snand_adjust_op_size, -+ .supports_op = mtk_snand_supports_op, -+ .exec_op = mtk_snand_exec_op, -+}; -+ -+static const struct spi_controller_mem_caps mtk_snand_mem_caps = { -+ .ecc = true, -+}; -+ -+static irqreturn_t mtk_snand_irq(int irq, void *id) -+{ -+ struct mtk_snand *snf = id; -+ u32 sta, ien; -+ -+ sta = nfi_read32(snf, NFI_INTR_STA); -+ ien = nfi_read32(snf, NFI_INTR_EN); -+ -+ if (!(sta & ien)) -+ return IRQ_NONE; -+ -+ nfi_write32(snf, NFI_INTR_EN, 0); -+ complete(&snf->op_done); -+ return IRQ_HANDLED; -+} -+ -+static const struct of_device_id mtk_snand_ids[] = { -+ { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps }, -+ { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, mtk_snand_ids); -+ -+static int mtk_snand_enable_clk(struct mtk_snand *ms) -+{ -+ int ret; -+ -+ ret = clk_prepare_enable(ms->nfi_clk); -+ if (ret) { -+ dev_err(ms->dev, "unable to enable nfi clk\n"); -+ return ret; -+ } -+ ret = clk_prepare_enable(ms->pad_clk); -+ if (ret) { -+ dev_err(ms->dev, "unable to enable pad clk\n"); -+ goto err1; -+ } -+ return 0; -+err1: -+ clk_disable_unprepare(ms->nfi_clk); -+ return ret; -+} -+ -+static void mtk_snand_disable_clk(struct mtk_snand *ms) -+{ -+ clk_disable_unprepare(ms->pad_clk); -+ clk_disable_unprepare(ms->nfi_clk); -+} -+ -+static int mtk_snand_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *dev_id; -+ struct spi_controller *ctlr; -+ struct mtk_snand *ms; -+ int ret; -+ -+ dev_id = of_match_node(mtk_snand_ids, np); -+ if (!dev_id) -+ return -EINVAL; -+ -+ ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms)); -+ if (!ctlr) -+ return -ENOMEM; -+ platform_set_drvdata(pdev, ctlr); -+ -+ ms = spi_controller_get_devdata(ctlr); -+ -+ ms->ctlr = ctlr; -+ ms->caps = dev_id->data; -+ -+ ms->ecc = of_mtk_ecc_get(np); -+ if (IS_ERR(ms->ecc)) -+ return PTR_ERR(ms->ecc); -+ else if (!ms->ecc) -+ return -ENODEV; -+ -+ ms->nfi_base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ms->nfi_base)) { -+ ret = PTR_ERR(ms->nfi_base); -+ goto release_ecc; -+ } -+ -+ ms->dev = &pdev->dev; -+ -+ ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk"); -+ if (IS_ERR(ms->nfi_clk)) { -+ ret = PTR_ERR(ms->nfi_clk); -+ dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret); -+ goto release_ecc; -+ } -+ -+ ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk"); -+ if (IS_ERR(ms->pad_clk)) { -+ ret = PTR_ERR(ms->pad_clk); -+ dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret); -+ goto release_ecc; -+ } -+ -+ ret = mtk_snand_enable_clk(ms); -+ if (ret) -+ goto release_ecc; -+ -+ init_completion(&ms->op_done); -+ -+ ms->irq = platform_get_irq(pdev, 0); -+ if (ms->irq < 0) { -+ ret = ms->irq; -+ goto disable_clk; -+ } -+ ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0, -+ "mtk-snand", ms); -+ if (ret) { -+ dev_err(ms->dev, "failed to request snfi irq\n"); -+ goto disable_clk; -+ } -+ -+ ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(ms->dev, "failed to set dma mask\n"); -+ goto disable_clk; -+ } -+ -+ // switch to SNFI mode -+ nfi_write32(ms, SNF_CFG, SPI_MODE); -+ -+ // setup an initial page format for ops matching page_cache_op template -+ // before ECC is called. -+ ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, -+ ms->caps->spare_sizes[0]); -+ if (ret) { -+ dev_err(ms->dev, "failed to set initial page format\n"); -+ goto disable_clk; -+ } -+ -+ // setup ECC engine -+ ms->ecc_eng.dev = &pdev->dev; -+ ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; -+ ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops; -+ ms->ecc_eng.priv = ms; -+ -+ ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to register ecc engine.\n"); -+ goto disable_clk; -+ } -+ -+ ctlr->num_chipselect = 1; -+ ctlr->mem_ops = &mtk_snand_mem_ops; -+ ctlr->mem_caps = &mtk_snand_mem_caps; -+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8); -+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; -+ ctlr->dev.of_node = pdev->dev.of_node; -+ ret = spi_register_controller(ctlr); -+ if (ret) { -+ dev_err(&pdev->dev, "spi_register_controller failed.\n"); -+ goto disable_clk; -+ } -+ -+ return 0; -+disable_clk: -+ mtk_snand_disable_clk(ms); -+release_ecc: -+ mtk_ecc_release(ms->ecc); -+ return ret; -+} -+ -+static int mtk_snand_remove(struct platform_device *pdev) -+{ -+ struct spi_controller *ctlr = platform_get_drvdata(pdev); -+ struct mtk_snand *ms = spi_controller_get_devdata(ctlr); -+ -+ spi_unregister_controller(ctlr); -+ mtk_snand_disable_clk(ms); -+ mtk_ecc_release(ms->ecc); -+ kfree(ms->buf); -+ return 0; -+} -+ -+static struct platform_driver mtk_snand_driver = { -+ .probe = mtk_snand_probe, -+ .remove = mtk_snand_remove, -+ .driver = { -+ .name = "mtk-snand", -+ .of_match_table = mtk_snand_ids, -+ }, -+}; -+ -+module_platform_driver(mtk_snand_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhong Guo "); -+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); diff --git a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch deleted file mode 100644 index 01d9d1208..000000000 --- a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Mon, 4 Apr 2022 00:05:38 +0800 -Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if - available - -The recently added ECC engine support introduced a generic property -named nand-ecc-engine for ecc engine phandle. This patch adds support -for this new property. - -Signed-off-by: Chuanhong Guo -(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54) ---- - drivers/mtd/nand/ecc-mtk.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/ecc-mtk.c -+++ b/drivers/mtd/nand/ecc-mtk.c -@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de - struct mtk_ecc *ecc = NULL; - struct device_node *np; - -- np = of_parse_phandle(of_node, "ecc-engine", 0); -+ np = of_parse_phandle(of_node, "nand-ecc-engine", 0); -+ /* for backward compatibility */ -+ if (!np) -+ np = of_parse_phandle(of_node, "ecc-engine", 0); - if (np) { - ecc = mtk_ecc_get(np); - of_node_put(np); diff --git a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch deleted file mode 100644 index 56548f3ac..000000000 --- a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 3 Apr 2022 10:19:29 +0800 -Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622 - -This patch adds a device-tree node for the MTK SPI-NAND Flash Interface -for MT7622 device tree. - -Signed-off-by: Chuanhong Guo -(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af) ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -550,6 +550,18 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7622-snand"; -+ reg = <0 0x1100d000 0 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - bch: ecc@1100e000 { - compatible = "mediatek,mt7622-ecc"; - reg = <0 0x1100e000 0 0x1000>; diff --git a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch deleted file mode 100644 index 770a7ff9b..000000000 --- a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -714,7 +714,7 @@ static int spinand_mtd_write(struct mtd_ - static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) - { - struct spinand_device *spinand = nand_to_spinand(nand); -- u8 marker[2] = { }; -+ u8 marker[1] = { }; - struct nand_page_io_req req = { - .pos = *pos, - .ooblen = sizeof(marker), -@@ -725,7 +725,7 @@ static bool spinand_isbad(struct nand_de - - spinand_select_target(spinand, pos->target); - spinand_read_page(spinand, &req); -- if (marker[0] != 0xff || marker[1] != 0xff) -+ if (marker[0] != 0xff) - return true; - - return false; diff --git a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index be0018a38..000000000 --- a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,94 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,27 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@1100e000 { -+ compatible = "mediatek,mt7622-ecc"; -+ reg = <0x1100e000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,50 @@ - }; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index 966c8ba52..000000000 --- a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -540,6 +540,65 @@ - status = "disabled"; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index a8964421b..000000000 --- a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -581,7 +581,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -642,5 +642,6 @@ - &wmac { - pinctrl-names = "default"; - pinctrl-0 = <&wmac_pins>; -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 5b63bf422..000000000 --- a/target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -951,17 +951,15 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; -+ status = "okay"; - }; - - bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 091cffc3c..000000000 --- a/target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index d1bafc152..000000000 --- a/target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index f6745add5..000000000 --- a/target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index b1dd75a41..000000000 --- a/target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch deleted file mode 100644 index ba1d1fe20..000000000 --- a/target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001 -From: Sungbo Eo -Date: Sun, 8 Aug 2021 21:38:40 +0900 -Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes - -MT7623 has an musb controller that is compatible with the one from MT2701. - -Signed-off-by: Sungbo Eo ---- - arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7623a.dtsi | 4 ++++ - 2 files changed, 38 insertions(+) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -585,6 +585,40 @@ - status = "disabled"; - }; - -+ usb0: usb@11200000 { -+ compatible = "mediatek,mt7623-musb", -+ "mediatek,mtk-musb"; -+ reg = <0 0x11200000 0 0x1000>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&u2port2 PHY_TYPE_USB2>; -+ dr_mode = "otg"; -+ clocks = <&pericfg CLK_PERI_USB0>, -+ <&pericfg CLK_PERI_USB0_MCU>, -+ <&pericfg CLK_PERI_USB_SLV>; -+ clock-names = "main","mcu","univpll"; -+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -+ status = "disabled"; -+ }; -+ -+ u2phy1: t-phy@11210000 { -+ compatible = "mediatek,mt7623-tphy", -+ "mediatek,generic-tphy-v1"; -+ reg = <0 0x11210000 0 0x0800>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ u2port2: usb-phy@11210800 { -+ reg = <0 0x11210800 0 0x0100>; -+ clocks = <&topckgen CLK_TOP_USB_PHY48M>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; -+ - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7623-audsys", - "mediatek,mt2701-audsys", ---- a/arch/arm/boot/dts/mt7623a.dtsi -+++ b/arch/arm/boot/dts/mt7623a.dtsi -@@ -35,6 +35,10 @@ - clock-names = "ethif"; - }; - -+&usb0 { -+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -+}; -+ - &usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; - }; diff --git a/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch deleted file mode 100644 index fabee390c..000000000 --- a/target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -161,6 +161,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch deleted file mode 100644 index 8b41000a6..000000000 --- a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ /dev/null @@ -1,106 +0,0 @@ -From patchwork Tue Apr 26 19:51:36 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 12827872 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF - for ; - Tue, 26 Apr 2022 19:53:05 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: - From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: - Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: - List-Owner; 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- interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, -- <0 0x10320000 0 0x1000>, -+ <0 0x1032f000 0 0x2000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; diff --git a/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch deleted file mode 100644 index 8851fefbb..000000000 --- a/target/linux/mediatek/patches-5.15/191-v5.19-arm64-dts-mt7622-specify-the-L2-cache-topology.patch +++ /dev/null @@ -1,132 +0,0 @@ -From patchwork Thu Apr 28 22:57:55 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Rui Salvaterra -X-Patchwork-Id: 12831311 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF - for ; 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- Thu, 28 Apr 2022 15:58:06 -0700 (PDT) -From: Rui Salvaterra -To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, - linux-kernel@vger.kernel.org -Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, - Rui Salvaterra -Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology -Date: Thu, 28 Apr 2022 23:57:55 +0100 -Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com> -X-Mailer: git-send-email 2.36.0 -MIME-Version: 1.0 -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220428_155811_895571_B63D2806 -X-CRM114-Status: GOOD ( 10.27 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -On an MT7622 system, the kernel complains of not being able to detect the cache -hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in -order to fix this. - -Signed-off-by: Rui Salvaterra ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -80,6 +80,7 @@ - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; -+ next-level-cache = <&L2>; - }; - - cpu1: cpu@1 { -@@ -94,6 +95,12 @@ - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; -+ next-level-cache = <&L2>; -+ }; -+ -+ L2: l2-cache { -+ compatible = "cache"; -+ cache-level = <2>; - }; - }; - diff --git a/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch deleted file mode 100644 index 506a65266..000000000 --- a/target/linux/mediatek/patches-5.15/192-v5.19-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch +++ /dev/null @@ -1,122 +0,0 @@ -From patchwork Fri Apr 29 08:42:25 2022 -Content-Type: text/plain; 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- Fri, 29 Apr 2022 01:42:32 -0700 (PDT) -Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt. - [109.49.0.175]) by smtp.gmail.com with ESMTPSA id - el10-20020a170907284a00b006f3ef214e32sm429064ejc.152.2022.04.29.01.42.31 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Fri, 29 Apr 2022 01:42:31 -0700 (PDT) -From: Rui Salvaterra -To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, - linux-kernel@vger.kernel.org -Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, - Rui Salvaterra -Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests -Date: Fri, 29 Apr 2022 09:42:25 +0100 -Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com> -X-Mailer: git-send-email 2.36.0 -MIME-Version: 1.0 -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220429_014236_944696_097D1E73 -X-CRM114-Status: UNSURE ( 8.85 ) -X-CRM114-Notice: Please train this message. -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -The MT7622 device tree never bothered to specify the number of virtual DMA -channels for the HSDMA controller, always falling back to the default value of -3. Make this value explicit, in order to avoid the following dmesg notification: - -mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property - -Signed-off-by: Rui Salvaterra ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -938,6 +938,7 @@ - clock-names = "hsdma"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - #dma-cells = <1>; -+ dma-requests = <3>; - }; - - pcie_mirror: pcie-mirror@10000400 { diff --git a/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch deleted file mode 100644 index 1cfb53d62..000000000 --- a/target/linux/mediatek/patches-5.15/193-dts-mt7623-thermal_zone_fix.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 -From: Bruno Umuarama -Date: Thu, 13 Oct 2022 21:18:21 +0000 -Subject: [PATCH] mediatek: mt7623: fix thermal zone -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Raising the temperatures for passive and active trips. @VA1DER -proposed at issue 9396 to remove passive trip. This commit relates to -his suggestion. - -Without this patch. the CPU will be throttled all the way down to 98MHz -if the temperature rises even a degree above the trip point, and it was -further discovered that if the internal temperature of the device is -above the first trip point temperature when it boots then it will start -in a throttled state and even -$ echo disabled > /sys/class/thermal/thermal_zone0/mode -will have no effect. - -The patch increases the passive trip point and active cooling map. The -throttling temperature will then be at 77°C and 82°C, which is still a -low enough temperature for ARM devices to not be in the real danger -zone, and gives some operational headroom. - -Signed-off-by: Bruno Umuarama ---- - arch/arm/boot/dts/mt7623.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -160,13 +160,13 @@ - - trips { - cpu_passive: cpu-passive { -- temperature = <57000>; -+ temperature = <77000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { -- temperature = <67000>; -+ temperature = <82000>; - hysteresis = <2000>; - type = "active"; - }; diff --git a/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch deleted file mode 100644 index 161c1e751..000000000 --- a/target/linux/mediatek/patches-5.15/194-dts-mt7968a-add-ramoops.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -68,6 +68,14 @@ - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch deleted file mode 100644 index 336920baf..000000000 --- a/target/linux/mediatek/patches-5.15/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ /dev/null @@ -1,196 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -23,6 +23,10 @@ - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; -+ led-boot = &green_led; -+ led-failsafe = &green_led; -+ led-running = &green_led; -+ led-upgrade = &blue_led; - }; - - chosen { -@@ -419,27 +423,27 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port5: port@5 { - reg = <5>; -- label = "lan4"; -+ label = "sfp2"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; -@@ -490,9 +494,137 @@ - - &wifi { - status = "okay"; -- pinctrl-names = "default", "dbdc"; -+ pinctrl-names = "default"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 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0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - - led { - led-active-low; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -55,6 +55,7 @@ - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; -+ compatible = "denx,fit"; - }; - }; - }; diff --git a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index cfb0556d1..000000000 --- a/target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -18,6 +18,8 @@ - #include - #include - #include -+#include -+#include - - /* version V1 sub-banks offset base address */ - /* banks shared by multiple phys */ -@@ -311,6 +313,9 @@ - - #define TPHY_CLKS_CNT 2 - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -377,6 +382,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); - tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); - tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); -@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_coef); - } - -+ if (of_find_property(np, "mediatek,phy-switch", NULL)) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch deleted file mode 100644 index 0761e1da1..000000000 --- a/target/linux/mediatek/patches-5.15/210-v6.1-pinctrl-mediatek-add-support-for-MT7986-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -120,6 +120,13 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7986 -+ bool "Mediatek MT7986 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "Mediatek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch b/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch deleted file mode 100644 index 15de8aa3d..000000000 --- a/target/linux/mediatek/patches-5.15/211-v5.16-clk-mediatek-Add-API-for-clock-resource-recycle.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -43,6 +43,15 @@ err_out: - return NULL; - } - -+void mtk_free_clk_data(struct clk_onecell_data *clk_data) -+{ -+ if (!clk_data) -+ return; -+ -+ kfree(clk_data->clks); -+ kfree(clk_data); -+} -+ - void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, - int num, struct clk_onecell_data *clk_data) - { ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str - struct clk_onecell_data *clk_data); - - struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); -+void mtk_free_clk_data(struct clk_onecell_data *clk_data); - - #define HAVE_RST_BAR BIT(0) - #define PLL_AO BIT(1) diff --git a/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch b/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch deleted file mode 100644 index 8e2365a49..000000000 --- a/target/linux/mediatek/patches-5.15/212-v5.17-clk-mediatek-add-mt7986-clock-support.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7986 -+ bool "Clock driver for MediaTek MT7986" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7986 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ -+config COMMON_CLK_MT7986_ETHSYS -+ bool "Clock driver for MediaTek MT7986 ETHSYS" -+ depends on COMMON_CLK_MT7986 -+ default COMMON_CLK_MT7986 -+ help -+ This driver add support for clocks for Ethernet and SGMII -+ required on MediaTek MT7986 SoC. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch b/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch deleted file mode 100644 index 2d6fc55ae..000000000 --- a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch +++ /dev/null @@ -1,917 +0,0 @@ -From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Apr 2022 11:40:22 +0800 -Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986 - spi design - -this patch add the support of ipm design and upgrade devicetree binding - -The patch is comming from following threads -- https://lore.kernel.org/all/20220315032411.2826-1-leilk.liu@mediatek.com/ -- https://lore.kernel.org/all/20220401071616.8874-1-leilk.liu@mediatek.com/ - -Signed-off-by: Sam Shih ---- - .../bindings/spi/mediatek,spi-mt65xx.yaml | 111 ++++ - drivers/spi/spi-mt65xx.c | 509 ++++++++++++++++-- - 2 files changed, 572 insertions(+), 48 deletions(-) - create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml -@@ -0,0 +1,111 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SPI Bus controller for MediaTek ARM SoCs -+ -+maintainers: -+ - Leilk Liu -+ -+allOf: -+ - $ref: "/schemas/spi/spi-controller.yaml#" -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - mediatek,mt7629-spi -+ - const: mediatek,mt7622-spi -+ - items: -+ - enum: -+ - mediatek,mt8516-spi -+ - const: mediatek,mt2712-spi -+ - items: -+ - enum: -+ - mediatek,mt6779-spi -+ - mediatek,mt8186-spi -+ - mediatek,mt8192-spi -+ - mediatek,mt8195-spi -+ - const: mediatek,mt6765-spi -+ - items: -+ - enum: -+ - mediatek,mt7986-spi-ipm -+ - const: mediatek,spi-ipm -+ - items: -+ - enum: -+ - mediatek,mt2701-spi -+ - mediatek,mt2712-spi -+ - mediatek,mt6589-spi -+ - mediatek,mt6765-spi -+ - mediatek,mt6893-spi -+ - mediatek,mt7622-spi -+ - mediatek,mt8135-spi -+ - mediatek,mt8173-spi -+ - mediatek,mt8183-spi -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 3 -+ items: -+ - description: clock used for the parent clock -+ - description: clock used for the muxes clock -+ - description: clock used for the clock gate -+ - description: clock used for the AHB bus, this clock is optional -+ -+ clock-names: -+ minItems: 3 -+ items: -+ - const: parent-clk -+ - const: sel-clk -+ - const: spi-clk -+ - const: hclk -+ -+ mediatek,pad-select: -+ $ref: /schemas/types.yaml#/definitions/uint32-array -+ minItems: 1 -+ maxItems: 4 -+ items: -+ enum: [0, 1, 2, 3] -+ description: -+ specify which pins group(ck/mi/mo/cs) spi controller used. -+ This is an array. -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - '#address-cells' -+ - '#size-cells' -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ -+ spi@1100a000 { -+ compatible = "mediatek,mt8173-spi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1100a000 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&pericfg CLK_PERI_SPI0>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk"; -+ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; -+ mediatek,pad-select = <1>, <0>; -+ }; ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -12,11 +12,12 @@ - #include - #include - #include --#include -+#include - #include - #include - #include - #include -+#include - #include - - #define SPI_CFG0_REG 0x0000 -@@ -31,6 +32,7 @@ - #define SPI_CFG2_REG 0x0028 - #define SPI_TX_SRC_REG_64 0x002c - #define SPI_RX_DST_REG_64 0x0030 -+#define SPI_CFG3_IPM_REG 0x0040 - - #define SPI_CFG0_SCK_HIGH_OFFSET 0 - #define SPI_CFG0_SCK_LOW_OFFSET 8 -@@ -51,6 +53,7 @@ - #define SPI_CFG1_CS_IDLE_MASK 0xff - #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 - #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 -+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) - #define SPI_CFG2_SCK_HIGH_OFFSET 0 - #define SPI_CFG2_SCK_LOW_OFFSET 16 - -@@ -71,6 +74,24 @@ - #define SPI_CMD_TX_ENDIAN BIT(15) - #define SPI_CMD_FINISH_IE BIT(16) - #define SPI_CMD_PAUSE_IE BIT(17) -+#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) -+#define SPI_CMD_IPM_SPIM_LOOP BIT(21) -+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 -+ -+#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) -+ -+#define PIN_MODE_CFG(x) ((x) / 2) -+ -+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) -+#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) -+#define SPI_CFG3_IPM_XMODE_EN BIT(4) -+#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) -+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 -+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 -+ -+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) -+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) -+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) - - #define MT8173_SPI_MAX_PAD_SEL 3 - -@@ -81,6 +102,9 @@ - - #define MTK_SPI_MAX_FIFO_SIZE 32U - #define MTK_SPI_PACKET_SIZE 1024 -+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K -+#define MTK_SPI_IPM_PACKET_LOOP SZ_256 -+ - #define MTK_SPI_32BITS_MASK (0xffffffff) - - #define DMA_ADDR_EXT_BITS (36) -@@ -96,6 +120,8 @@ struct mtk_spi_compatible { - bool dma_ext; - /* some IC no need unprepare SPI clk */ - bool no_need_unprepare; -+ /* IPM design adjust and extend register to support more features */ -+ bool ipm_design; - }; - - struct mtk_spi { -@@ -103,7 +129,7 @@ struct mtk_spi { - u32 state; - int pad_num; - u32 *pad_sel; -- struct clk *parent_clk, *sel_clk, *spi_clk; -+ struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; - struct spi_transfer *cur_transfer; - u32 xfer_len; - u32 num_xfered; -@@ -111,6 +137,11 @@ struct mtk_spi { - u32 tx_sgl_len, rx_sgl_len; - const struct mtk_spi_compatible *dev_comp; - u32 spi_clk_hz; -+ struct completion spimem_done; -+ bool use_spimem; -+ struct device *dev; -+ dma_addr_t tx_dma; -+ dma_addr_t rx_dma; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m - .must_tx = true, - }; - -+static const struct mtk_spi_compatible mtk_ipm_compat = { -+ .enhance_timing = true, -+ .dma_ext = true, -+ .ipm_design = true, -+}; -+ - static const struct mtk_spi_compatible mt6765_compat = { - .need_pad_sel = true, - .must_tx = true, -@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_ - }; - - static const struct of_device_id mtk_spi_of_match[] = { -+ { .compatible = "mediatek,spi-ipm", -+ .data = (void *)&mtk_ipm_compat, -+ }, - { .compatible = "mediatek,mt2701-spi", - .data = (void *)&mtk_common_compat, - }, -@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru - return 0; - } - --static int mtk_spi_prepare_message(struct spi_master *master, -- struct spi_message *msg) -+static int mtk_spi_hw_init(struct spi_master *master, -+ struct spi_device *spi) - { - u16 cpha, cpol; - u32 reg_val; -- struct spi_device *spi = msg->spi; - struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); - -@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc - cpol = spi->mode & SPI_CPOL ? 1 : 0; - - reg_val = readl(mdata->base + SPI_CMD_REG); -+ if (mdata->dev_comp->ipm_design) { -+ /* SPI transfer without idle time until packet length done */ -+ reg_val |= SPI_CMD_IPM_NONIDLE_MODE; -+ if (spi->mode & SPI_LOOP) -+ reg_val |= SPI_CMD_IPM_SPIM_LOOP; -+ else -+ reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; -+ } -+ - if (cpha) - reg_val |= SPI_CMD_CPHA; - else -@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc - mdata->base + SPI_PAD_SEL_REG); - - /* tick delay */ -- reg_val = readl(mdata->base + SPI_CFG1_REG); - if (mdata->dev_comp->enhance_timing) { -- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -- << SPI_CFG1_GET_TICK_DLY_OFFSET); -+ if (mdata->dev_comp->ipm_design) { -+ reg_val = readl(mdata->base + SPI_CMD_REG); -+ reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -+ reg_val |= ((chip_config->tick_delay & 0x7) -+ << SPI_CMD_IPM_GET_TICKDLY_OFFSET); -+ writel(reg_val, mdata->base + SPI_CMD_REG); -+ } else { -+ reg_val = readl(mdata->base + SPI_CFG1_REG); -+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -+ reg_val |= ((chip_config->tick_delay & 0x7) -+ << SPI_CFG1_GET_TICK_DLY_OFFSET); -+ writel(reg_val, mdata->base + SPI_CFG1_REG); -+ } - } else { -+ reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; - reg_val |= ((chip_config->tick_delay & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); -+ writel(reg_val, mdata->base + SPI_CFG1_REG); - } -- writel(reg_val, mdata->base + SPI_CFG1_REG); - - /* set hw cs timing */ - mtk_spi_set_hw_cs_timing(spi); - return 0; - } - -+static int mtk_spi_prepare_message(struct spi_master *master, -+ struct spi_message *msg) -+{ -+ return mtk_spi_hw_init(master, msg->spi); -+} -+ - static void mtk_spi_set_cs(struct spi_device *spi, bool enable) - { - u32 reg_val; -@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de - } - - static void mtk_spi_prepare_transfer(struct spi_master *master, -- struct spi_transfer *xfer) -+ u32 speed_hz) - { - u32 div, sck_time, reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); - -- if (xfer->speed_hz < mdata->spi_clk_hz / 2) -- div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz); -+ if (speed_hz < mdata->spi_clk_hz / 2) -+ div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); - else - div = 1; - -@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct - u32 packet_size, packet_loop, reg_val; - struct mtk_spi *mdata = spi_master_get_devdata(master); - -- packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); -+ if (mdata->dev_comp->ipm_design) -+ packet_size = min_t(u32, -+ mdata->xfer_len, -+ MTK_SPI_IPM_PACKET_SIZE); -+ else -+ packet_size = min_t(u32, -+ mdata->xfer_len, -+ MTK_SPI_PACKET_SIZE); -+ - packet_loop = mdata->xfer_len / packet_size; - - reg_val = readl(mdata->base + SPI_CFG1_REG); -- reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); -+ if (mdata->dev_comp->ipm_design) -+ reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; -+ else -+ reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; - reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; -+ reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; - reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct - mdata->cur_transfer = xfer; - mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); - mdata->num_xfered = 0; -- mtk_spi_prepare_transfer(master, xfer); -+ mtk_spi_prepare_transfer(master, xfer->speed_hz); - mtk_spi_setup_packet(master); - - if (xfer->tx_buf) { -@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s - mdata->cur_transfer = xfer; - mdata->num_xfered = 0; - -- mtk_spi_prepare_transfer(master, xfer); -+ mtk_spi_prepare_transfer(master, xfer->speed_hz); - - cmd = readl(mdata->base + SPI_CMD_REG); - if (xfer->tx_buf) -@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s - struct spi_device *spi, - struct spi_transfer *xfer) - { -+ struct mtk_spi *mdata = spi_master_get_devdata(spi->master); -+ u32 reg_val = 0; -+ -+ /* prepare xfer direction and duplex mode */ -+ if (mdata->dev_comp->ipm_design) { -+ if (!xfer->tx_buf || !xfer->rx_buf) { -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; -+ if (xfer->rx_buf) -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ } -+ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); -+ } -+ - if (master->can_dma(master, spi, xfer)) - return mtk_spi_dma_transfer(master, spi, xfer); - else -@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi - if (!spi->controller_data) - spi->controller_data = (void *)&mtk_default_chip_info; - -- if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) -- gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); -+ if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) -+ /* CS de-asserted, gpiolib will handle inversion */ -+ gpiod_direction_output(spi->cs_gpiod, 0); - - return 0; - } -@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int - else - mdata->state = MTK_SPI_IDLE; - -+ /* SPI-MEM ops */ -+ if (mdata->use_spimem) { -+ complete(&mdata->spimem_done); -+ return IRQ_HANDLED; -+ } -+ - if (!master->can_dma(master, NULL, trans)) { - if (trans->rx_buf) { - cnt = mdata->xfer_len / 4; -@@ -718,6 +814,274 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_HANDLED; - } - -+static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, -+ struct spi_mem_op *op) -+{ -+ int opcode_len; -+ -+ if (op->data.dir != SPI_MEM_NO_DATA) { -+ opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; -+ if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { -+ op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; -+ /* force data buffer dma-aligned. */ -+ op->data.nbytes -= op->data.nbytes % 4; -+ } -+ } -+ -+ return 0; -+} -+ -+static bool mtk_spi_mem_supports_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ if (!spi_mem_default_supports_op(mem, op)) -+ return false; -+ -+ if (op->addr.nbytes && op->dummy.nbytes && -+ op->addr.buswidth != op->dummy.buswidth) -+ return false; -+ -+ if (op->addr.nbytes + op->dummy.nbytes > 16) -+ return false; -+ -+ if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { -+ if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > -+ MTK_SPI_IPM_PACKET_LOOP || -+ op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) -+ return false; -+ } -+ -+ return true; -+} -+ -+static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, -+ const struct spi_mem_op *op) -+{ -+ struct mtk_spi *mdata = spi_master_get_devdata(master); -+ -+ writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), -+ mdata->base + SPI_TX_SRC_REG); -+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT -+ if (mdata->dev_comp->dma_ext) -+ writel((u32)(mdata->tx_dma >> 32), -+ mdata->base + SPI_TX_SRC_REG_64); -+#endif -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), -+ mdata->base + SPI_RX_DST_REG); -+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT -+ if (mdata->dev_comp->dma_ext) -+ writel((u32)(mdata->rx_dma >> 32), -+ mdata->base + SPI_RX_DST_REG_64); -+#endif -+ } -+} -+ -+static int mtk_spi_transfer_wait(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); -+ /* -+ * For each byte we wait for 8 cycles of the SPI clock. -+ * Since speed is defined in Hz and we want milliseconds, -+ * so it should be 8 * 1000. -+ */ -+ u64 ms = 8000LL; -+ -+ if (op->data.dir == SPI_MEM_NO_DATA) -+ ms *= 32; /* prevent we may get 0 for short transfers. */ -+ else -+ ms *= op->data.nbytes; -+ ms = div_u64(ms, mem->spi->max_speed_hz); -+ ms += ms + 1000; /* 1s tolerance */ -+ -+ if (ms > UINT_MAX) -+ ms = UINT_MAX; -+ -+ if (!wait_for_completion_timeout(&mdata->spimem_done, -+ msecs_to_jiffies(ms))) { -+ dev_err(mdata->dev, "spi-mem transfer timeout\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int mtk_spi_mem_exec_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); -+ u32 reg_val, nio, tx_size; -+ char *tx_tmp_buf, *rx_tmp_buf; -+ int ret = 0; -+ -+ mdata->use_spimem = true; -+ reinit_completion(&mdata->spimem_done); -+ -+ mtk_spi_reset(mdata); -+ mtk_spi_hw_init(mem->spi->master, mem->spi); -+ mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); -+ -+ reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); -+ /* opcode byte len */ -+ reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; -+ reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; -+ -+ /* addr & dummy byte len */ -+ reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; -+ if (op->addr.nbytes || op->dummy.nbytes) -+ reg_val |= (op->addr.nbytes + op->dummy.nbytes) << -+ SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; -+ -+ /* data byte len */ -+ if (op->data.dir == SPI_MEM_NO_DATA) { -+ reg_val |= SPI_CFG3_IPM_NODATA_FLAG; -+ writel(0, mdata->base + SPI_CFG1_REG); -+ } else { -+ reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; -+ mdata->xfer_len = op->data.nbytes; -+ mtk_spi_setup_packet(mem->spi->master); -+ } -+ -+ if (op->addr.nbytes || op->dummy.nbytes) { -+ if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) -+ reg_val |= SPI_CFG3_IPM_XMODE_EN; -+ else -+ reg_val &= ~SPI_CFG3_IPM_XMODE_EN; -+ } -+ -+ if (op->addr.buswidth == 2 || -+ op->dummy.buswidth == 2 || -+ op->data.buswidth == 2) -+ nio = 2; -+ else if (op->addr.buswidth == 4 || -+ op->dummy.buswidth == 4 || -+ op->data.buswidth == 4) -+ nio = 4; -+ else -+ nio = 1; -+ -+ reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; -+ reg_val |= PIN_MODE_CFG(nio); -+ -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ else -+ reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; -+ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); -+ -+ tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ tx_size += op->data.nbytes; -+ -+ tx_size = max_t(u32, tx_size, 32); -+ -+ tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); -+ if (!tx_tmp_buf) { -+ mdata->use_spimem = false; -+ return -ENOMEM; -+ } -+ -+ tx_tmp_buf[0] = op->cmd.opcode; -+ -+ if (op->addr.nbytes) { -+ int i; -+ -+ for (i = 0; i < op->addr.nbytes; i++) -+ tx_tmp_buf[i + 1] = op->addr.val >> -+ (8 * (op->addr.nbytes - i - 1)); -+ } -+ -+ if (op->dummy.nbytes) -+ memset(tx_tmp_buf + op->addr.nbytes + 1, -+ 0xff, -+ op->dummy.nbytes); -+ -+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) -+ memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, -+ op->data.buf.out, -+ op->data.nbytes); -+ -+ mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, -+ tx_size, DMA_TO_DEVICE); -+ if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { -+ ret = -ENOMEM; -+ goto err_exit; -+ } -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { -+ rx_tmp_buf = kzalloc(op->data.nbytes, -+ GFP_KERNEL | GFP_DMA); -+ if (!rx_tmp_buf) { -+ ret = -ENOMEM; -+ goto unmap_tx_dma; -+ } -+ } else { -+ rx_tmp_buf = op->data.buf.in; -+ } -+ -+ mdata->rx_dma = dma_map_single(mdata->dev, -+ rx_tmp_buf, -+ op->data.nbytes, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { -+ ret = -ENOMEM; -+ goto kfree_rx_tmp_buf; -+ } -+ } -+ -+ reg_val = readl(mdata->base + SPI_CMD_REG); -+ reg_val |= SPI_CMD_TX_DMA; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val |= SPI_CMD_RX_DMA; -+ writel(reg_val, mdata->base + SPI_CMD_REG); -+ -+ mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); -+ -+ mtk_spi_enable_transfer(mem->spi->master); -+ -+ /* Wait for the interrupt. */ -+ ret = mtk_spi_transfer_wait(mem, op); -+ if (ret) -+ goto unmap_rx_dma; -+ -+ /* spi disable dma */ -+ reg_val = readl(mdata->base + SPI_CMD_REG); -+ reg_val &= ~SPI_CMD_TX_DMA; -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ reg_val &= ~SPI_CMD_RX_DMA; -+ writel(reg_val, mdata->base + SPI_CMD_REG); -+ -+unmap_rx_dma: -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ dma_unmap_single(mdata->dev, mdata->rx_dma, -+ op->data.nbytes, DMA_FROM_DEVICE); -+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) -+ memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); -+ } -+kfree_rx_tmp_buf: -+ if (op->data.dir == SPI_MEM_DATA_IN && -+ !IS_ALIGNED((size_t)op->data.buf.in, 4)) -+ kfree(rx_tmp_buf); -+unmap_tx_dma: -+ dma_unmap_single(mdata->dev, mdata->tx_dma, -+ tx_size, DMA_TO_DEVICE); -+err_exit: -+ kfree(tx_tmp_buf); -+ mdata->use_spimem = false; -+ -+ return ret; -+} -+ -+static const struct spi_controller_mem_ops mtk_spi_mem_ops = { -+ .adjust_op_size = mtk_spi_mem_adjust_op_size, -+ .supports_op = mtk_spi_mem_supports_op, -+ .exec_op = mtk_spi_mem_exec_op, -+}; -+ - static int mtk_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; -@@ -741,6 +1105,7 @@ static int mtk_spi_probe(struct platform - master->can_dma = mtk_spi_can_dma; - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; -+ master->use_gpio_descriptors = true; - - of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); - if (!of_id) { -@@ -757,6 +1122,14 @@ static int mtk_spi_probe(struct platform - - if (mdata->dev_comp->must_tx) - master->flags = SPI_MASTER_MUST_TX; -+ if (mdata->dev_comp->ipm_design) -+ master->mode_bits |= SPI_LOOP; -+ -+ if (mdata->dev_comp->ipm_design) { -+ mdata->dev = &pdev->dev; -+ master->mem_ops = &mtk_spi_mem_ops; -+ init_completion(&mdata->spimem_done); -+ } - - if (mdata->dev_comp->need_pad_sel) { - mdata->pad_num = of_property_count_u32_elems( -@@ -833,25 +1206,40 @@ static int mtk_spi_probe(struct platform - goto err_put_master; - } - -+ mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk"); -+ if (IS_ERR(mdata->spi_hclk)) { -+ ret = PTR_ERR(mdata->spi_hclk); -+ dev_err(&pdev->dev, "failed to get hclk: %d\n", ret); -+ goto err_put_master; -+ } -+ -+ ret = clk_prepare_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret); -+ goto err_put_master; -+ } -+ - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); -- goto err_put_master; -+ goto err_disable_spi_hclk; - } - - ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); -- clk_disable_unprepare(mdata->spi_clk); -- goto err_put_master; -+ goto err_disable_spi_clk; - } - - mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - clk_disable(mdata->spi_clk); -- else -+ clk_disable(mdata->spi_hclk); -+ } else { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - pm_runtime_enable(&pdev->dev); - -@@ -864,25 +1252,12 @@ static int mtk_spi_probe(struct platform - goto err_disable_runtime_pm; - } - -- if (!master->cs_gpios && master->num_chipselect > 1) { -+ if (!master->cs_gpiods && master->num_chipselect > 1) { - dev_err(&pdev->dev, - "cs_gpios not specified and num_chipselect > 1\n"); - ret = -EINVAL; - goto err_disable_runtime_pm; - } -- -- if (master->cs_gpios) { -- for (i = 0; i < master->num_chipselect; i++) { -- ret = devm_gpio_request(&pdev->dev, -- master->cs_gpios[i], -- dev_name(&pdev->dev)); -- if (ret) { -- dev_err(&pdev->dev, -- "can't get CS GPIO %i\n", i); -- goto err_disable_runtime_pm; -- } -- } -- } - } - - if (mdata->dev_comp->dma_ext) -@@ -904,6 +1279,10 @@ static int mtk_spi_probe(struct platform - - err_disable_runtime_pm: - pm_runtime_disable(&pdev->dev); -+err_disable_spi_clk: -+ clk_disable_unprepare(mdata->spi_clk); -+err_disable_spi_hclk: -+ clk_disable_unprepare(mdata->spi_hclk); - err_put_master: - spi_master_put(master); - -@@ -922,8 +1301,10 @@ static int mtk_spi_remove(struct platfor - - mtk_spi_reset(mdata); - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - clk_unprepare(mdata->spi_clk); -+ clk_unprepare(mdata->spi_hclk); -+ } - - pm_runtime_put_noidle(&pdev->dev); - pm_runtime_disable(&pdev->dev); -@@ -942,8 +1323,10 @@ static int mtk_spi_suspend(struct device - if (ret) - return ret; - -- if (!pm_runtime_suspended(dev)) -+ if (!pm_runtime_suspended(dev)) { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - return ret; - } -@@ -960,11 +1343,20 @@ static int mtk_spi_resume(struct device - dev_err(dev, "failed to enable spi_clk (%d)\n", ret); - return ret; - } -+ -+ ret = clk_prepare_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); -+ clk_disable_unprepare(mdata->spi_clk); -+ return ret; -+ } - } - - ret = spi_master_resume(master); -- if (ret < 0) -+ if (ret < 0) { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - return ret; - } -@@ -976,10 +1368,13 @@ static int mtk_spi_runtime_suspend(struc - struct spi_master *master = dev_get_drvdata(dev); - struct mtk_spi *mdata = spi_master_get_devdata(master); - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - clk_disable(mdata->spi_clk); -- else -+ clk_disable(mdata->spi_hclk); -+ } else { - clk_disable_unprepare(mdata->spi_clk); -+ clk_disable_unprepare(mdata->spi_hclk); -+ } - - return 0; - } -@@ -990,13 +1385,31 @@ static int mtk_spi_runtime_resume(struct - struct mtk_spi *mdata = spi_master_get_devdata(master); - int ret; - -- if (mdata->dev_comp->no_need_unprepare) -+ if (mdata->dev_comp->no_need_unprepare) { - ret = clk_enable(mdata->spi_clk); -- else -+ if (ret < 0) { -+ dev_err(dev, "failed to enable spi_clk (%d)\n", ret); -+ return ret; -+ } -+ ret = clk_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); -+ clk_disable(mdata->spi_clk); -+ return ret; -+ } -+ } else { - ret = clk_prepare_enable(mdata->spi_clk); -- if (ret < 0) { -- dev_err(dev, "failed to enable spi_clk (%d)\n", ret); -- return ret; -+ if (ret < 0) { -+ dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(mdata->spi_hclk); -+ if (ret < 0) { -+ dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); -+ clk_disable_unprepare(mdata->spi_clk); -+ return ret; -+ } - } - - return 0; diff --git a/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch b/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch deleted file mode 100644 index 631eb0409..000000000 --- a/target/linux/mediatek/patches-5.15/214-v6.3-clk-mediatek-add-mt7981-clock-support.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7981 -+ bool "Clock driver for MediaTek MT7981" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7981 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ -+config COMMON_CLK_MT7981_ETHSYS -+ bool "Clock driver for MediaTek MT7981 ETHSYS" -+ depends on COMMON_CLK_MT7981 -+ default COMMON_CLK_MT7981 -+ help -+ This driver add support for clocks for Ethernet and SGMII -+ required on MediaTek MT7981 SoC. -+ - config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o diff --git a/target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch b/target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch deleted file mode 100644 index 43983339b..000000000 --- a/target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/mtd/mtdblock.c -+++ b/drivers/mtd/mtdblock.c -@@ -261,10 +261,6 @@ static int mtdblock_open(struct mtd_blkt - return 0; - } - -- if (mtd_type_is_nand(mbd->mtd)) -- pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", -- mbd->tr->name, mbd->mtd->name); -- - /* OK, it's not open. Create cache info for it */ - mtdblk->count = 1; - mutex_init(&mtdblk->cache_mutex); ---- a/drivers/mtd/mtdblock_ro.c -+++ b/drivers/mtd/mtdblock_ro.c -@@ -46,10 +46,6 @@ static void mtdblock_add_mtd(struct mtd_ - dev->tr = tr; - dev->readonly = 1; - -- if (mtd_type_is_nand(mtd)) -- pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", -- tr->name, mtd->name); -- - if (add_mtd_blktrans_dev(dev)) - kfree(dev); - } diff --git a/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch deleted file mode 100644 index ae99685df..000000000 --- a/target/linux/mediatek/patches-5.15/215-v6.3-pinctrl-mediatek-add-support-for-MT7981-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -120,6 +120,13 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7981 -+ bool "Mediatek MT7981 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT7986 - bool "Mediatek MT7986 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch deleted file mode 100644 index cbee45bc1..000000000 --- a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -134,6 +134,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "Mediatek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch deleted file mode 100644 index 23a5b7c91..000000000 --- a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -233,6 +233,7 @@ struct mtk_pll_data { - u32 pcw_reg; - int pcw_shift; - u32 pcw_chg_reg; -+ int pcw_chg_shift; - const struct mtk_pll_div_table *div_table; - const char *parent_name; - u32 en_reg; ---- a/drivers/clk/mediatek/clk-pll.c -+++ b/drivers/clk/mediatek/clk-pll.c -@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct - pll->data->pcw_shift); - val |= pcw << pll->data->pcw_shift; - writel(val, pll->pcw_addr); -- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; -+ if (pll->data->pcw_chg_shift) -+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); -+ else -+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; - writel(chg, pll->pcw_chg_addr); - if (pll->tuner_addr) - writel(val + 1, pll->tuner_addr); diff --git a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch deleted file mode 100644 index bf9146352..000000000 --- a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver add support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7988 -+ bool "Clock driver for MediaTek MT7988" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7988 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch deleted file mode 100644 index 56ffa73c0..000000000 --- a/target/linux/mediatek/patches-5.15/320-mmc-mediatek-add-support-for-MT7986-SoC.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sat, 25 Jun 2022 02:10:13 +0800 -Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC - -Adding mt7986 own characteristics and of_device_id to have support -of MT7986 SoC. - -Signed-off-by: Sam Shih -Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a ---- - drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -540,6 +540,19 @@ static const struct mtk_mmc_compatible m - .support_64g = false, - }; - -+static const struct mtk_mmc_compatible mt7986_compat = { -+ .clk_div_bits = 12, -+ .recheck_sdio_irq = true, -+ .hs400_tune = false, -+ .pad_tune_reg = MSDC_PAD_TUNE0, -+ .async_fifo = true, -+ .data_tune = true, -+ .busy_check = true, -+ .stop_clk_fix = true, -+ .enhance_rx = true, -+ .support_64g = true, -+}; -+ - static const struct mtk_mmc_compatible mt8516_compat = { - .clk_div_bits = 12, - .recheck_sdio_irq = true, -@@ -584,6 +597,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, - { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, - { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, -+ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch deleted file mode 100644 index 48bfb0d35..000000000 --- a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) - { -@@ -1332,6 +1333,7 @@ static int spinand_probe(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_attach(mtd); - ret = mtd_device_register(mtd, NULL, 0); - if (ret) - goto err_spinand_cleanup; -@@ -1339,6 +1341,7 @@ static int spinand_probe(struct spi_mem - return 0; - - err_spinand_cleanup: -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return ret; -@@ -1357,6 +1360,7 @@ static int spinand_remove(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return 0; diff --git a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index 504928cb2..000000000 --- a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -554,6 +554,7 @@ - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - nand-ecc-engine = <&snfi>; -+ mediatek,bmt-v2; - - partitions { - compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch deleted file mode 100644 index e6d39c0f1..000000000 --- a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 -From: Davide Fioravanti -Date: Fri, 8 Jan 2021 15:35:24 +0100 -Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA - -Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf - -Signed-off-by: Davide Fioravanti ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/fidelix.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,3 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o -+spinand-objs := core.o esmt.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -929,6 +929,7 @@ static const struct nand_ops spinand_ops - - static const struct spinand_manufacturer *spinand_manufacturers[] = { - &esmt_c8_spinand_manufacturer, -+ &fidelix_spinand_manufacturer, - &gigadevice_spinand_manufacturer, - ¯onix_spinand_manufacturer, - µn_spinand_manufacturer, ---- /dev/null -+++ b/drivers/mtd/nand/spi/fidelix.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Davide Fioravanti -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_FIDELIX 0xE5 -+#define FIDELIX_ECCSR_MASK 0x0F -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 2; -+ region->length = 6; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { -+ .ecc = fm35x1ga_ooblayout_ecc, -+ .free = fm35x1ga_ooblayout_free, -+}; -+ -+static const struct spinand_info fidelix_spinand_table[] = { -+ SPINAND_INFO("FM35X1GA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), -+}; -+ -+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer fidelix_spinand_manufacturer = { -+ .id = SPINAND_MFR_FIDELIX, -+ .name = "Fidelix", -+ .chips = fidelix_spinand_table, -+ .nchips = ARRAY_SIZE(fidelix_spinand_table), -+ .ops = &fidelix_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -261,6 +261,7 @@ struct spinand_manufacturer { - - /* SPI NAND manufacturers */ - extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; -+extern const struct spinand_manufacturer fidelix_spinand_manufacturer; - extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; - extern const struct spinand_manufacturer macronix_spinand_manufacturer; - extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch b/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch deleted file mode 100644 index 8fad64a57..000000000 --- a/target/linux/mediatek/patches-5.15/350-01-cpufreq-mediatek-Cleanup-variables-and-error-handlin.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 7a768326fdba542144833b9198a6d0edab52fad2 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 8 Apr 2022 12:58:56 +0800 -Subject: [PATCH 01/21] cpufreq: mediatek: Cleanup variables and error handling - in mtk_cpu_dvfs_info_init() - -- Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init(). -- Unify error message format and use dev_err_probe() if possible. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++------------------ - 1 file changed, 34 insertions(+), 55 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -302,96 +302,75 @@ static int mtk_cpufreq_set_target(struct - static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) - { - struct device *cpu_dev; -- struct regulator *proc_reg = ERR_PTR(-ENODEV); -- struct regulator *sram_reg = ERR_PTR(-ENODEV); -- struct clk *cpu_clk = ERR_PTR(-ENODEV); -- struct clk *inter_clk = ERR_PTR(-ENODEV); - struct dev_pm_opp *opp; - unsigned long rate; - int ret; - - cpu_dev = get_cpu_device(cpu); - if (!cpu_dev) { -- pr_err("failed to get cpu%d device\n", cpu); -+ dev_err(cpu_dev, "failed to get cpu%d device\n", cpu); - return -ENODEV; - } -+ info->cpu_dev = cpu_dev; - -- cpu_clk = clk_get(cpu_dev, "cpu"); -- if (IS_ERR(cpu_clk)) { -- if (PTR_ERR(cpu_clk) == -EPROBE_DEFER) -- pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu); -- else -- pr_err("failed to get cpu clk for cpu%d\n", cpu); -- -- ret = PTR_ERR(cpu_clk); -- return ret; -- } -- -- inter_clk = clk_get(cpu_dev, "intermediate"); -- if (IS_ERR(inter_clk)) { -- if (PTR_ERR(inter_clk) == -EPROBE_DEFER) -- pr_warn("intermediate clk for cpu%d not ready, retry.\n", -- cpu); -- else -- pr_err("failed to get intermediate clk for cpu%d\n", -- cpu); -+ info->cpu_clk = clk_get(cpu_dev, "cpu"); -+ if (IS_ERR(info->cpu_clk)) { -+ ret = PTR_ERR(info->cpu_clk); -+ return dev_err_probe(cpu_dev, ret, -+ "cpu%d: failed to get cpu clk\n", cpu); -+ } - -- ret = PTR_ERR(inter_clk); -+ info->inter_clk = clk_get(cpu_dev, "intermediate"); -+ if (IS_ERR(info->inter_clk)) { -+ ret = PTR_ERR(info->inter_clk); -+ dev_err_probe(cpu_dev, ret, -+ "cpu%d: failed to get intermediate clk\n", cpu); - goto out_free_resources; - } - -- proc_reg = regulator_get_optional(cpu_dev, "proc"); -- if (IS_ERR(proc_reg)) { -- if (PTR_ERR(proc_reg) == -EPROBE_DEFER) -- pr_warn("proc regulator for cpu%d not ready, retry.\n", -- cpu); -- else -- pr_err("failed to get proc regulator for cpu%d\n", -- cpu); -- -- ret = PTR_ERR(proc_reg); -+ info->proc_reg = regulator_get_optional(cpu_dev, "proc"); -+ if (IS_ERR(info->proc_reg)) { -+ ret = PTR_ERR(info->proc_reg); -+ dev_err_probe(cpu_dev, ret, -+ "cpu%d: failed to get proc regulator\n", cpu); - goto out_free_resources; - } - - /* Both presence and absence of sram regulator are valid cases. */ -- sram_reg = regulator_get_exclusive(cpu_dev, "sram"); -+ info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); -+ if (IS_ERR(info->sram_reg)) -+ info->sram_reg = NULL; - - /* Get OPP-sharing information from "operating-points-v2" bindings */ - ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); - if (ret) { -- pr_err("failed to get OPP-sharing information for cpu%d\n", -- cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to get OPP-sharing information\n", cpu); - goto out_free_resources; - } - - ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); - if (ret) { -- pr_warn("no OPP table for cpu%d\n", cpu); -+ dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); - goto out_free_resources; - } - - /* Search a safe voltage for intermediate frequency. */ -- rate = clk_get_rate(inter_clk); -+ rate = clk_get_rate(info->inter_clk); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); - if (IS_ERR(opp)) { -- pr_err("failed to get intermediate opp for cpu%d\n", cpu); -+ dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); - ret = PTR_ERR(opp); - goto out_free_opp_table; - } - info->intermediate_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); - -- info->cpu_dev = cpu_dev; -- info->proc_reg = proc_reg; -- info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; -- info->cpu_clk = cpu_clk; -- info->inter_clk = inter_clk; -- - /* - * If SRAM regulator is present, software "voltage tracking" is needed - * for this CPU power domain. - */ -- info->need_voltage_tracking = !IS_ERR(sram_reg); -+ info->need_voltage_tracking = (info->sram_reg != NULL); - - return 0; - -@@ -399,14 +378,14 @@ out_free_opp_table: - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - - out_free_resources: -- if (!IS_ERR(proc_reg)) -- regulator_put(proc_reg); -- if (!IS_ERR(sram_reg)) -- regulator_put(sram_reg); -- if (!IS_ERR(cpu_clk)) -- clk_put(cpu_clk); -- if (!IS_ERR(inter_clk)) -- clk_put(inter_clk); -+ if (!IS_ERR(info->proc_reg)) -+ regulator_put(info->proc_reg); -+ if (!IS_ERR(info->sram_reg)) -+ regulator_put(info->sram_reg); -+ if (!IS_ERR(info->cpu_clk)) -+ clk_put(info->cpu_clk); -+ if (!IS_ERR(info->inter_clk)) -+ clk_put(info->inter_clk); - - return ret; - } diff --git a/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch b/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch deleted file mode 100644 index eebeeb090..000000000 --- a/target/linux/mediatek/patches-5.15/350-02-cpufreq-mediatek-Remove-unused-headers.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 756104b856d4bc3121420af3ced342f5fc2b2123 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 8 Apr 2022 12:58:57 +0800 -Subject: [PATCH 02/21] cpufreq: mediatek: Remove unused headers - -Remove unused headers. - -Signed-off-by: Jia-Wei Chang -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -13,8 +13,6 @@ - #include - #include - #include --#include --#include - - #define MIN_VOLT_SHIFT (100000) - #define MAX_VOLT_SHIFT (200000) diff --git a/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch b/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch deleted file mode 100644 index c97d5fc3d..000000000 --- a/target/linux/mediatek/patches-5.15/350-03-cpufreq-mediatek-Enable-clocks-and-regulators.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 342d5545e9f40496db9ae0d31c2427dd5f369a43 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 8 Apr 2022 12:58:58 +0800 -Subject: [PATCH 03/21] cpufreq: mediatek: Enable clocks and regulators - -We need to enable regulators so that the max and min requested values will -be recorded. -The intermediate clock is not always enabled by CCF in different projects, -so we should enable it in the cpufreq driver. - -Signed-off-by: Andrew-sh.Cheng -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 50 +++++++++++++++++++++++++++--- - 1 file changed, 45 insertions(+), 5 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -334,10 +334,23 @@ static int mtk_cpu_dvfs_info_init(struct - goto out_free_resources; - } - -+ ret = regulator_enable(info->proc_reg); -+ if (ret) { -+ dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); -+ goto out_free_resources; -+ } -+ - /* Both presence and absence of sram regulator are valid cases. */ - info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); - if (IS_ERR(info->sram_reg)) - info->sram_reg = NULL; -+ else { -+ ret = regulator_enable(info->sram_reg); -+ if (ret) { -+ dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); -+ goto out_free_resources; -+ } -+ } - - /* Get OPP-sharing information from "operating-points-v2" bindings */ - ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); -@@ -353,13 +366,21 @@ static int mtk_cpu_dvfs_info_init(struct - goto out_free_resources; - } - -+ ret = clk_prepare_enable(info->cpu_clk); -+ if (ret) -+ goto out_free_opp_table; -+ -+ ret = clk_prepare_enable(info->inter_clk); -+ if (ret) -+ goto out_disable_mux_clock; -+ - /* Search a safe voltage for intermediate frequency. */ - rate = clk_get_rate(info->inter_clk); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); - if (IS_ERR(opp)) { - dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); - ret = PTR_ERR(opp); -- goto out_free_opp_table; -+ goto out_disable_inter_clock; - } - info->intermediate_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); -@@ -372,10 +393,21 @@ static int mtk_cpu_dvfs_info_init(struct - - return 0; - -+out_disable_inter_clock: -+ clk_disable_unprepare(info->inter_clk); -+ -+out_disable_mux_clock: -+ clk_disable_unprepare(info->cpu_clk); -+ - out_free_opp_table: - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - - out_free_resources: -+ if (regulator_is_enabled(info->proc_reg)) -+ regulator_disable(info->proc_reg); -+ if (info->sram_reg && regulator_is_enabled(info->sram_reg)) -+ regulator_disable(info->sram_reg); -+ - if (!IS_ERR(info->proc_reg)) - regulator_put(info->proc_reg); - if (!IS_ERR(info->sram_reg)) -@@ -390,14 +422,22 @@ out_free_resources: - - static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) - { -- if (!IS_ERR(info->proc_reg)) -+ if (!IS_ERR(info->proc_reg)) { -+ regulator_disable(info->proc_reg); - regulator_put(info->proc_reg); -- if (!IS_ERR(info->sram_reg)) -+ } -+ if (!IS_ERR(info->sram_reg)) { -+ regulator_disable(info->sram_reg); - regulator_put(info->sram_reg); -- if (!IS_ERR(info->cpu_clk)) -+ } -+ if (!IS_ERR(info->cpu_clk)) { -+ clk_disable_unprepare(info->cpu_clk); - clk_put(info->cpu_clk); -- if (!IS_ERR(info->inter_clk)) -+ } -+ if (!IS_ERR(info->inter_clk)) { -+ clk_disable_unprepare(info->inter_clk); - clk_put(info->inter_clk); -+ } - - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - } diff --git a/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch b/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch deleted file mode 100644 index 18e1da728..000000000 --- a/target/linux/mediatek/patches-5.15/350-04-cpufreq-mediatek-Use-device-print-to-show-logs.patch +++ /dev/null @@ -1,161 +0,0 @@ -From a02e2b359141035d2d6999940bc1b9f83ec88587 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Fri, 22 Apr 2022 15:52:27 +0800 -Subject: [PATCH 04/21] cpufreq: mediatek: Use device print to show logs - -- Replace pr_* with dev_* to show logs. -- Remove usage of __func__. - -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++-------------- - 1 file changed, 28 insertions(+), 26 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -67,7 +67,8 @@ static int mtk_cpufreq_voltage_tracking( - - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ -@@ -83,14 +84,14 @@ static int mtk_cpufreq_voltage_tracking( - do { - old_vsram = regulator_get_voltage(sram_reg); - if (old_vsram < 0) { -- pr_err("%s: invalid Vsram value: %d\n", -- __func__, old_vsram); -+ dev_err(info->cpu_dev, -+ "invalid Vsram value: %d\n", old_vsram); - return old_vsram; - } - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", -- __func__, old_vproc); -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - -@@ -138,14 +139,14 @@ static int mtk_cpufreq_voltage_tracking( - do { - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", -- __func__, old_vproc); -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - old_vsram = regulator_get_voltage(sram_reg); - if (old_vsram < 0) { -- pr_err("%s: invalid Vsram value: %d\n", -- __func__, old_vsram); -+ dev_err(info->cpu_dev, -+ "invalid Vsram value: %d\n", old_vsram); - return old_vsram; - } - -@@ -216,7 +217,7 @@ static int mtk_cpufreq_set_target(struct - old_freq_hz = clk_get_rate(cpu_clk); - old_vproc = regulator_get_voltage(info->proc_reg); - if (old_vproc < 0) { -- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); -+ dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); - return old_vproc; - } - -@@ -224,8 +225,8 @@ static int mtk_cpufreq_set_target(struct - - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); - if (IS_ERR(opp)) { -- pr_err("cpu%d: failed to find OPP for %ld\n", -- policy->cpu, freq_hz); -+ dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", -+ policy->cpu, freq_hz); - return PTR_ERR(opp); - } - vproc = dev_pm_opp_get_voltage(opp); -@@ -239,8 +240,8 @@ static int mtk_cpufreq_set_target(struct - if (old_vproc < target_vproc) { - ret = mtk_cpufreq_set_voltage(info, target_vproc); - if (ret) { -- pr_err("cpu%d: failed to scale up voltage!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to scale up voltage!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, old_vproc); - return ret; - } -@@ -249,8 +250,8 @@ static int mtk_cpufreq_set_target(struct - /* Reparent the CPU clock to intermediate clock. */ - ret = clk_set_parent(cpu_clk, info->inter_clk); - if (ret) { -- pr_err("cpu%d: failed to re-parent cpu clock!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, old_vproc); - WARN_ON(1); - return ret; -@@ -259,8 +260,8 @@ static int mtk_cpufreq_set_target(struct - /* Set the original PLL to target rate. */ - ret = clk_set_rate(armpll, freq_hz); - if (ret) { -- pr_err("cpu%d: failed to scale cpu clock rate!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); - clk_set_parent(cpu_clk, armpll); - mtk_cpufreq_set_voltage(info, old_vproc); - return ret; -@@ -269,8 +270,8 @@ static int mtk_cpufreq_set_target(struct - /* Set parent of CPU clock back to the original PLL. */ - ret = clk_set_parent(cpu_clk, armpll); - if (ret) { -- pr_err("cpu%d: failed to re-parent cpu clock!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, inter_vproc); - WARN_ON(1); - return ret; -@@ -283,8 +284,8 @@ static int mtk_cpufreq_set_target(struct - if (vproc < inter_vproc || vproc < old_vproc) { - ret = mtk_cpufreq_set_voltage(info, vproc); - if (ret) { -- pr_err("cpu%d: failed to scale down voltage!\n", -- policy->cpu); -+ dev_err(cpu_dev, -+ "cpu%d: failed to scale down voltage!\n", policy->cpu); - clk_set_parent(cpu_clk, info->inter_clk); - clk_set_rate(armpll, old_freq_hz); - clk_set_parent(cpu_clk, armpll); -@@ -450,15 +451,16 @@ static int mtk_cpufreq_init(struct cpufr - - info = mtk_cpu_dvfs_info_lookup(policy->cpu); - if (!info) { -- pr_err("dvfs info for cpu%d is not initialized.\n", -- policy->cpu); -+ dev_err(info->cpu_dev, -+ "dvfs info for cpu%d is not initialized.\n", policy->cpu); - return -EINVAL; - } - - ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); - if (ret) { -- pr_err("failed to init cpufreq table for cpu%d: %d\n", -- policy->cpu, ret); -+ dev_err(info->cpu_dev, -+ "failed to init cpufreq table for cpu%d: %d\n", -+ policy->cpu, ret); - return ret; - } - diff --git a/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch b/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch deleted file mode 100644 index 8506f4e47..000000000 --- a/target/linux/mediatek/patches-5.15/350-05-cpufreq-mediatek-Replace-old_-with-pre_.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 35832d9f9c5c1da01420d962dc56e7e61d104829 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Fri, 22 Apr 2022 15:52:28 +0800 -Subject: [PATCH 05/21] cpufreq: mediatek: Replace old_* with pre_* - -To make driver more readable, replace old_* with pre_*. - -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++--------------- - 1 file changed, 42 insertions(+), 42 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -63,18 +63,18 @@ static int mtk_cpufreq_voltage_tracking( - { - struct regulator *proc_reg = info->proc_reg; - struct regulator *sram_reg = info->sram_reg; -- int old_vproc, old_vsram, new_vsram, vsram, vproc, ret; -+ int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; - -- old_vproc = regulator_get_voltage(proc_reg); -- if (old_vproc < 0) { -+ pre_vproc = regulator_get_voltage(proc_reg); -+ if (pre_vproc < 0) { - dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); - -- if (old_vproc < new_vproc) { -+ if (pre_vproc < new_vproc) { - /* - * When scaling up voltages, Vsram and Vproc scale up step - * by step. At each step, set Vsram to (Vproc + 200mV) first, -@@ -82,20 +82,20 @@ static int mtk_cpufreq_voltage_tracking( - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { -- old_vsram = regulator_get_voltage(sram_reg); -- if (old_vsram < 0) { -+ pre_vsram = regulator_get_voltage(sram_reg); -+ if (pre_vsram < 0) { - dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", old_vsram); -- return old_vsram; -+ "invalid Vsram value: %d\n", pre_vsram); -+ return pre_vsram; - } -- old_vproc = regulator_get_voltage(proc_reg); -- if (old_vproc < 0) { -+ pre_vproc = regulator_get_voltage(proc_reg); -+ if (pre_vproc < 0) { - dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } - -- vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT); -+ vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); - - if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { - vsram = MAX_VOLT_LIMIT; -@@ -124,12 +124,12 @@ static int mtk_cpufreq_voltage_tracking( - ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); - if (ret) { -- regulator_set_voltage(sram_reg, old_vsram, -- old_vsram); -+ regulator_set_voltage(sram_reg, pre_vsram, -+ pre_vsram); - return ret; - } - } while (vproc < new_vproc || vsram < new_vsram); -- } else if (old_vproc > new_vproc) { -+ } else if (pre_vproc > new_vproc) { - /* - * When scaling down voltages, Vsram and Vproc scale down step - * by step. At each step, set Vproc to (Vsram - 200mV) first, -@@ -137,20 +137,20 @@ static int mtk_cpufreq_voltage_tracking( - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { -- old_vproc = regulator_get_voltage(proc_reg); -- if (old_vproc < 0) { -+ pre_vproc = regulator_get_voltage(proc_reg); -+ if (pre_vproc < 0) { - dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } -- old_vsram = regulator_get_voltage(sram_reg); -- if (old_vsram < 0) { -+ pre_vsram = regulator_get_voltage(sram_reg); -+ if (pre_vsram < 0) { - dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", old_vsram); -- return old_vsram; -+ "invalid Vsram value: %d\n", pre_vsram); -+ return pre_vsram; - } - -- vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT); -+ vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); - ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); - if (ret) -@@ -180,8 +180,8 @@ static int mtk_cpufreq_voltage_tracking( - } - - if (ret) { -- regulator_set_voltage(proc_reg, old_vproc, -- old_vproc); -+ regulator_set_voltage(proc_reg, pre_vproc, -+ pre_vproc); - return ret; - } - } while (vproc > new_vproc + VOLT_TOL || -@@ -209,16 +209,16 @@ static int mtk_cpufreq_set_target(struct - struct mtk_cpu_dvfs_info *info = policy->driver_data; - struct device *cpu_dev = info->cpu_dev; - struct dev_pm_opp *opp; -- long freq_hz, old_freq_hz; -- int vproc, old_vproc, inter_vproc, target_vproc, ret; -+ long freq_hz, pre_freq_hz; -+ int vproc, pre_vproc, inter_vproc, target_vproc, ret; - - inter_vproc = info->intermediate_voltage; - -- old_freq_hz = clk_get_rate(cpu_clk); -- old_vproc = regulator_get_voltage(info->proc_reg); -- if (old_vproc < 0) { -- dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); -- return old_vproc; -+ pre_freq_hz = clk_get_rate(cpu_clk); -+ pre_vproc = regulator_get_voltage(info->proc_reg); -+ if (pre_vproc < 0) { -+ dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); -+ return pre_vproc; - } - - freq_hz = freq_table[index].frequency * 1000; -@@ -237,12 +237,12 @@ static int mtk_cpufreq_set_target(struct - * current voltage, scale up voltage first. - */ - target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; -- if (old_vproc < target_vproc) { -+ if (pre_vproc < target_vproc) { - ret = mtk_cpufreq_set_voltage(info, target_vproc); - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to scale up voltage!\n", policy->cpu); -- mtk_cpufreq_set_voltage(info, old_vproc); -+ mtk_cpufreq_set_voltage(info, pre_vproc); - return ret; - } - } -@@ -252,7 +252,7 @@ static int mtk_cpufreq_set_target(struct - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); -- mtk_cpufreq_set_voltage(info, old_vproc); -+ mtk_cpufreq_set_voltage(info, pre_vproc); - WARN_ON(1); - return ret; - } -@@ -263,7 +263,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); - clk_set_parent(cpu_clk, armpll); -- mtk_cpufreq_set_voltage(info, old_vproc); -+ mtk_cpufreq_set_voltage(info, pre_vproc); - return ret; - } - -@@ -281,13 +281,13 @@ static int mtk_cpufreq_set_target(struct - * If the new voltage is lower than the intermediate voltage or the - * original voltage, scale down to the new voltage. - */ -- if (vproc < inter_vproc || vproc < old_vproc) { -+ if (vproc < inter_vproc || vproc < pre_vproc) { - ret = mtk_cpufreq_set_voltage(info, vproc); - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to scale down voltage!\n", policy->cpu); - clk_set_parent(cpu_clk, info->inter_clk); -- clk_set_rate(armpll, old_freq_hz); -+ clk_set_rate(armpll, pre_freq_hz); - clk_set_parent(cpu_clk, armpll); - return ret; - } diff --git a/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch b/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch deleted file mode 100644 index 94e6617d2..000000000 --- a/target/linux/mediatek/patches-5.15/350-06-cpufreq-mediatek-Record-previous-target-vproc-value.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 34737eb8d0daa0d4183f10286a2f55d8788066bc Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 22 Apr 2022 15:52:29 +0800 -Subject: [PATCH 06/21] cpufreq: mediatek: Record previous target vproc value - -We found the buck voltage may not be exactly the same with what we set -because CPU may share the same buck with other module. -Therefore, we need to record the previous desired value instead of reading -it from regulators. - -Signed-off-by: Andrew-sh.Cheng -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++---- - 1 file changed, 16 insertions(+), 4 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info { - struct list_head list_head; - int intermediate_voltage; - bool need_voltage_tracking; -+ int pre_vproc; - }; - - static struct platform_device *cpufreq_pdev; -@@ -193,11 +194,17 @@ static int mtk_cpufreq_voltage_tracking( - - static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) - { -+ int ret; -+ - if (info->need_voltage_tracking) -- return mtk_cpufreq_voltage_tracking(info, vproc); -+ ret = mtk_cpufreq_voltage_tracking(info, vproc); - else -- return regulator_set_voltage(info->proc_reg, vproc, -- vproc + VOLT_TOL); -+ ret = regulator_set_voltage(info->proc_reg, vproc, -+ MAX_VOLT_LIMIT); -+ if (!ret) -+ info->pre_vproc = vproc; -+ -+ return ret; - } - - static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, -@@ -215,7 +222,12 @@ static int mtk_cpufreq_set_target(struct - inter_vproc = info->intermediate_voltage; - - pre_freq_hz = clk_get_rate(cpu_clk); -- pre_vproc = regulator_get_voltage(info->proc_reg); -+ -+ if (unlikely(info->pre_vproc <= 0)) -+ pre_vproc = regulator_get_voltage(info->proc_reg); -+ else -+ pre_vproc = info->pre_vproc; -+ - if (pre_vproc < 0) { - dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; diff --git a/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch b/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch deleted file mode 100644 index 4b74873b1..000000000 --- a/target/linux/mediatek/patches-5.15/350-07-cpufreq-mediatek-Make-sram-regulator-optional.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f6114c2bc563a8050e9dc874ad87e1448865f031 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 22 Apr 2022 15:52:33 +0800 -Subject: [PATCH 07/21] cpufreq: mediatek: Make sram regulator optional - -For some MediaTek SoCs, like MT8186, it's possible that the sram regulator -is shared between CPU and CCI. -We hope regulator framework can return error for error handling rather -than a dummy handler from regulator_get api. -Therefore, we choose to use regulator_get_optional. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -354,7 +354,7 @@ static int mtk_cpu_dvfs_info_init(struct - } - - /* Both presence and absence of sram regulator are valid cases. */ -- info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); -+ info->sram_reg = regulator_get_optional(cpu_dev, "sram"); - if (IS_ERR(info->sram_reg)) - info->sram_reg = NULL; - else { diff --git a/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch b/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch deleted file mode 100644 index f2f572a75..000000000 --- a/target/linux/mediatek/patches-5.15/350-08-cpufreq-mediatek-Fix-NULL-pointer-dereference-in-med.patch +++ /dev/null @@ -1,32 +0,0 @@ -From fa7030d8ad4638acfd9e0fac84a20716d031dc95 Mon Sep 17 00:00:00 2001 -From: Wan Jiabing -Date: Tue, 26 Apr 2022 19:17:14 +0800 -Subject: [PATCH 08/21] cpufreq: mediatek: Fix NULL pointer dereference in - mediatek-cpufreq - -Fix following coccicheck error: -drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced. - -Use pr_err instead of dev_err to avoid dereferring a NULL pointer. - -Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs") -Signed-off-by: Wan Jiabing -Reviewed-by: Matthias Brugger -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -463,8 +463,8 @@ static int mtk_cpufreq_init(struct cpufr - - info = mtk_cpu_dvfs_info_lookup(policy->cpu); - if (!info) { -- dev_err(info->cpu_dev, -- "dvfs info for cpu%d is not initialized.\n", policy->cpu); -+ pr_err("dvfs info for cpu%d is not initialized.\n", -+ policy->cpu); - return -EINVAL; - } - diff --git a/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch b/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch deleted file mode 100644 index 23b319648..000000000 --- a/target/linux/mediatek/patches-5.15/350-09-cpufreq-mediatek-Move-voltage-limits-to-platform-dat.patch +++ /dev/null @@ -1,227 +0,0 @@ -From be2354b064e6bafbbad599ae2e10569ba4f7d5a6 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Thu, 5 May 2022 19:52:19 +0800 -Subject: [PATCH 09/21] cpufreq: mediatek: Move voltage limits to platform data - -Voltages and shifts are defined as macros originally. -There are different requirements of these values for each MediaTek SoCs. -Therefore, we add the platform data and move these values into it. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++--------- - 1 file changed, 58 insertions(+), 26 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -10,15 +10,21 @@ - #include - #include - #include -+#include - #include - #include - #include - --#define MIN_VOLT_SHIFT (100000) --#define MAX_VOLT_SHIFT (200000) --#define MAX_VOLT_LIMIT (1150000) - #define VOLT_TOL (10000) - -+struct mtk_cpufreq_platform_data { -+ int min_volt_shift; -+ int max_volt_shift; -+ int proc_max_volt; -+ int sram_min_volt; -+ int sram_max_volt; -+}; -+ - /* - * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS - * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in -@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info { - int intermediate_voltage; - bool need_voltage_tracking; - int pre_vproc; -+ const struct mtk_cpufreq_platform_data *soc_data; - }; - - static struct platform_device *cpufreq_pdev; -@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu - static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, - int new_vproc) - { -+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; - struct regulator *proc_reg = info->proc_reg; - struct regulator *sram_reg = info->sram_reg; - int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; -@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking( - return pre_vproc; - } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ -- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); -+ new_vsram = min(new_vproc + soc_data->min_volt_shift, -+ soc_data->sram_max_volt); - - if (pre_vproc < new_vproc) { - /* -@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking( - return pre_vproc; - } - -- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); -+ vsram = min(new_vsram, -+ pre_vproc + soc_data->min_volt_shift); - -- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { -- vsram = MAX_VOLT_LIMIT; -+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -+ vsram = soc_data->sram_max_volt; - - /* - * If the target Vsram hits the maximum voltage, -@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking( - ret = regulator_set_voltage(sram_reg, vsram, - vsram + VOLT_TOL); - -- vproc = vsram - MIN_VOLT_SHIFT; -+ vproc = vsram - soc_data->min_volt_shift; - } - if (ret) - return ret; -@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking( - return pre_vsram; - } - -- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); -+ vproc = max(new_vproc, -+ pre_vsram - soc_data->max_volt_shift); - ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); - if (ret) -@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking( - if (vproc == new_vproc) - vsram = new_vsram; - else -- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT); -+ vsram = max(new_vsram, -+ vproc + soc_data->min_volt_shift); - -- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { -- vsram = MAX_VOLT_LIMIT; -+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -+ vsram = soc_data->sram_max_volt; - - /* - * If the target Vsram hits the maximum voltage, -@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking( - - static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) - { -+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; - int ret; - - if (info->need_voltage_tracking) - ret = mtk_cpufreq_voltage_tracking(info, vproc); - else - ret = regulator_set_voltage(info->proc_reg, vproc, -- MAX_VOLT_LIMIT); -+ soc_data->proc_max_volt); - if (!ret) - info->pre_vproc = vproc; - -@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq - - static int mtk_cpufreq_probe(struct platform_device *pdev) - { -+ const struct mtk_cpufreq_platform_data *data; - struct mtk_cpu_dvfs_info *info, *tmp; - int cpu, ret; - -+ data = dev_get_platdata(&pdev->dev); -+ if (!data) { -+ dev_err(&pdev->dev, -+ "failed to get mtk cpufreq platform data\n"); -+ return -ENODEV; -+ } -+ - for_each_possible_cpu(cpu) { - info = mtk_cpu_dvfs_info_lookup(cpu); - if (info) -@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct plat - goto release_dvfs_info_list; - } - -+ info->soc_data = data; - ret = mtk_cpu_dvfs_info_init(info, cpu); - if (ret) { - dev_err(&pdev->dev, -@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufre - .probe = mtk_cpufreq_probe, - }; - -+static const struct mtk_cpufreq_platform_data mt2701_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1150000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+}; -+ - /* List of machines supported by this driver */ - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { -- { .compatible = "mediatek,mt2701", }, -- { .compatible = "mediatek,mt2712", }, -- { .compatible = "mediatek,mt7622", }, -- { .compatible = "mediatek,mt7623", }, -- { .compatible = "mediatek,mt8167", }, -- { .compatible = "mediatek,mt817x", }, -- { .compatible = "mediatek,mt8173", }, -- { .compatible = "mediatek,mt8176", }, -- { .compatible = "mediatek,mt8183", }, -- { .compatible = "mediatek,mt8365", }, -- { .compatible = "mediatek,mt8516", }, -- -+ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, - { } - }; - MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); -@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_ini - { - struct device_node *np; - const struct of_device_id *match; -+ const struct mtk_cpufreq_platform_data *data; - int err; - - np = of_find_node_by_path("/"); -@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_ini - pr_debug("Machine is not compatible with mtk-cpufreq\n"); - return -ENODEV; - } -+ data = match->data; - - err = platform_driver_register(&mtk_cpufreq_platdrv); - if (err) -@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_ini - * and the device registration codes are put here to handle defer - * probing. - */ -- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); -+ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1, -+ data, sizeof(*data)); - if (IS_ERR(cpufreq_pdev)) { - pr_err("failed to register mtk-cpufreq platform device\n"); - platform_driver_unregister(&mtk_cpufreq_platdrv); diff --git a/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch b/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch deleted file mode 100644 index 0ba9471ff..000000000 --- a/target/linux/mediatek/patches-5.15/350-10-cpufreq-mediatek-Refine-mtk_cpufreq_voltage_tracking.patch +++ /dev/null @@ -1,255 +0,0 @@ -From 944b041c91f1e1cd762c39c1222f078550149486 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Thu, 5 May 2022 19:52:20 +0800 -Subject: [PATCH 10/21] cpufreq: mediatek: Refine - mtk_cpufreq_voltage_tracking() - -Because the difference of sram and proc should in a range of min_volt_shift -and max_volt_shift. We need to adjust the sram and proc step by step. - -We replace VOLT_TOL (voltage tolerance) with the platform data and update the -logic to determine the voltage boundary and invoking regulator_set_voltage. - -- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary - of sram regulator. -- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the - voltage boundary of vproc regulator. - -Moreover, to prevent infinite loop when tracking voltage, we calculate the -maximum value for each platform data. -We assume min voltage is 0 and tracking target voltage using -min_volt_shift for each iteration. -The retry_max is 3 times of expeted iteration count. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++------------------- - 1 file changed, 51 insertions(+), 96 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -15,8 +16,6 @@ - #include - #include - --#define VOLT_TOL (10000) -- - struct mtk_cpufreq_platform_data { - int min_volt_shift; - int max_volt_shift; -@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info { - bool need_voltage_tracking; - int pre_vproc; - const struct mtk_cpufreq_platform_data *soc_data; -+ int vtrack_max; - }; - - static struct platform_device *cpufreq_pdev; -@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking( - struct regulator *proc_reg = info->proc_reg; - struct regulator *sram_reg = info->sram_reg; - int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; -+ int retry = info->vtrack_max; - - pre_vproc = regulator_get_voltage(proc_reg); - if (pre_vproc < 0) { -@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking( - "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; - } -- /* Vsram should not exceed the maximum allowed voltage of SoC. */ -- new_vsram = min(new_vproc + soc_data->min_volt_shift, -- soc_data->sram_max_volt); -- -- if (pre_vproc < new_vproc) { -- /* -- * When scaling up voltages, Vsram and Vproc scale up step -- * by step. At each step, set Vsram to (Vproc + 200mV) first, -- * then set Vproc to (Vsram - 100mV). -- * Keep doing it until Vsram and Vproc hit target voltages. -- */ -- do { -- pre_vsram = regulator_get_voltage(sram_reg); -- if (pre_vsram < 0) { -- dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", pre_vsram); -- return pre_vsram; -- } -- pre_vproc = regulator_get_voltage(proc_reg); -- if (pre_vproc < 0) { -- dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", pre_vproc); -- return pre_vproc; -- } - -- vsram = min(new_vsram, -- pre_vproc + soc_data->min_volt_shift); -+ pre_vsram = regulator_get_voltage(sram_reg); -+ if (pre_vsram < 0) { -+ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); -+ return pre_vsram; -+ } - -- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -- vsram = soc_data->sram_max_volt; -+ new_vsram = clamp(new_vproc + soc_data->min_volt_shift, -+ soc_data->sram_min_volt, soc_data->sram_max_volt); -+ -+ do { -+ if (pre_vproc <= new_vproc) { -+ vsram = clamp(pre_vproc + soc_data->max_volt_shift, -+ soc_data->sram_min_volt, new_vsram); -+ ret = regulator_set_voltage(sram_reg, vsram, -+ soc_data->sram_max_volt); - -- /* -- * If the target Vsram hits the maximum voltage, -- * try to set the exact voltage value first. -- */ -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram); -- if (ret) -- ret = regulator_set_voltage(sram_reg, -- vsram - VOLT_TOL, -- vsram); -+ if (ret) -+ return ret; - -+ if (vsram == soc_data->sram_max_volt || -+ new_vsram == soc_data->sram_min_volt) - vproc = new_vproc; -- } else { -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram + VOLT_TOL); -- -+ else - vproc = vsram - soc_data->min_volt_shift; -- } -- if (ret) -- return ret; - - ret = regulator_set_voltage(proc_reg, vproc, -- vproc + VOLT_TOL); -+ soc_data->proc_max_volt); - if (ret) { - regulator_set_voltage(sram_reg, pre_vsram, -- pre_vsram); -+ soc_data->sram_max_volt); - return ret; - } -- } while (vproc < new_vproc || vsram < new_vsram); -- } else if (pre_vproc > new_vproc) { -- /* -- * When scaling down voltages, Vsram and Vproc scale down step -- * by step. At each step, set Vproc to (Vsram - 200mV) first, -- * then set Vproc to (Vproc + 100mV). -- * Keep doing it until Vsram and Vproc hit target voltages. -- */ -- do { -- pre_vproc = regulator_get_voltage(proc_reg); -- if (pre_vproc < 0) { -- dev_err(info->cpu_dev, -- "invalid Vproc value: %d\n", pre_vproc); -- return pre_vproc; -- } -- pre_vsram = regulator_get_voltage(sram_reg); -- if (pre_vsram < 0) { -- dev_err(info->cpu_dev, -- "invalid Vsram value: %d\n", pre_vsram); -- return pre_vsram; -- } -- -+ } else if (pre_vproc > new_vproc) { - vproc = max(new_vproc, - pre_vsram - soc_data->max_volt_shift); - ret = regulator_set_voltage(proc_reg, vproc, -- vproc + VOLT_TOL); -+ soc_data->proc_max_volt); - if (ret) - return ret; - -@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking( - vsram = max(new_vsram, - vproc + soc_data->min_volt_shift); - -- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { -- vsram = soc_data->sram_max_volt; -- -- /* -- * If the target Vsram hits the maximum voltage, -- * try to set the exact voltage value first. -- */ -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram); -- if (ret) -- ret = regulator_set_voltage(sram_reg, -- vsram - VOLT_TOL, -- vsram); -- } else { -- ret = regulator_set_voltage(sram_reg, vsram, -- vsram + VOLT_TOL); -- } -- -+ ret = regulator_set_voltage(sram_reg, vsram, -+ soc_data->sram_max_volt); - if (ret) { - regulator_set_voltage(proc_reg, pre_vproc, -- pre_vproc); -+ soc_data->proc_max_volt); - return ret; - } -- } while (vproc > new_vproc + VOLT_TOL || -- vsram > new_vsram + VOLT_TOL); -- } -+ } -+ -+ pre_vproc = vproc; -+ pre_vsram = vsram; -+ -+ if (--retry < 0) { -+ dev_err(info->cpu_dev, -+ "over loop count, failed to set voltage\n"); -+ return -EINVAL; -+ } -+ } while (vproc != new_vproc || vsram != new_vsram); - - return 0; - } -@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct - * If the new voltage or the intermediate voltage is higher than the - * current voltage, scale up voltage first. - */ -- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; -- if (pre_vproc < target_vproc) { -+ target_vproc = max(inter_vproc, vproc); -+ if (pre_vproc <= target_vproc) { - ret = mtk_cpufreq_set_voltage(info, target_vproc); - if (ret) { - dev_err(cpu_dev, -@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct - */ - info->need_voltage_tracking = (info->sram_reg != NULL); - -+ /* -+ * We assume min voltage is 0 and tracking target voltage using -+ * min_volt_shift for each iteration. -+ * The vtrack_max is 3 times of expeted iteration count. -+ */ -+ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt, -+ info->soc_data->proc_max_volt), -+ info->soc_data->min_volt_shift); -+ - return 0; - - out_disable_inter_clock: diff --git a/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch b/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch deleted file mode 100644 index 2cb99b907..000000000 --- a/target/linux/mediatek/patches-5.15/350-11-cpufreq-mediatek-Add-opp-notification-support.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 01be227eff7e5fc01f7c8de8f6daddd5fb17ddd1 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Thu, 5 May 2022 19:52:21 +0800 -Subject: [PATCH 11/21] cpufreq: mediatek: Add opp notification support - -From this opp notifier, cpufreq should listen to opp notification and do -proper actions when receiving events of disable and voltage adjustment. - -One of the user for this opp notifier is MediaTek SVS. -The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates -suitable SVS bank voltages to OPP voltage table. - -Signed-off-by: Andrew-sh.Cheng -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -[ Viresh: Renamed opp_freq as current_freq and moved its initialization ] -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 90 +++++++++++++++++++++++++++--- - 1 file changed, 82 insertions(+), 8 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info { - int intermediate_voltage; - bool need_voltage_tracking; - int pre_vproc; -+ /* Avoid race condition for regulators between notify and policy */ -+ struct mutex reg_lock; -+ struct notifier_block opp_nb; -+ unsigned int opp_cpu; -+ unsigned long current_freq; - const struct mtk_cpufreq_platform_data *soc_data; - int vtrack_max; - }; -@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct - - pre_freq_hz = clk_get_rate(cpu_clk); - -+ mutex_lock(&info->reg_lock); -+ - if (unlikely(info->pre_vproc <= 0)) - pre_vproc = regulator_get_voltage(info->proc_reg); - else -@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to scale up voltage!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, pre_vproc); -- return ret; -+ goto out; - } - } - -@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, pre_vproc); -- WARN_ON(1); -- return ret; -+ goto out; - } - - /* Set the original PLL to target rate. */ -@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct - "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); - clk_set_parent(cpu_clk, armpll); - mtk_cpufreq_set_voltage(info, pre_vproc); -- return ret; -+ goto out; - } - - /* Set parent of CPU clock back to the original PLL. */ -@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct - dev_err(cpu_dev, - "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, inter_vproc); -- WARN_ON(1); -- return ret; -+ goto out; - } - - /* -@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct - clk_set_parent(cpu_clk, info->inter_clk); - clk_set_rate(armpll, pre_freq_hz); - clk_set_parent(cpu_clk, armpll); -- return ret; -+ goto out; - } - } - -- return 0; -+ info->current_freq = freq_hz; -+ -+out: -+ mutex_unlock(&info->reg_lock); -+ -+ return ret; - } - - #define DYNAMIC_POWER "dynamic-power-coefficient" - -+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, -+ unsigned long event, void *data) -+{ -+ struct dev_pm_opp *opp = data; -+ struct dev_pm_opp *new_opp; -+ struct mtk_cpu_dvfs_info *info; -+ unsigned long freq, volt; -+ struct cpufreq_policy *policy; -+ int ret = 0; -+ -+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); -+ -+ if (event == OPP_EVENT_ADJUST_VOLTAGE) { -+ freq = dev_pm_opp_get_freq(opp); -+ -+ mutex_lock(&info->reg_lock); -+ if (info->current_freq == freq) { -+ volt = dev_pm_opp_get_voltage(opp); -+ ret = mtk_cpufreq_set_voltage(info, volt); -+ if (ret) -+ dev_err(info->cpu_dev, -+ "failed to scale voltage: %d\n", ret); -+ } -+ mutex_unlock(&info->reg_lock); -+ } else if (event == OPP_EVENT_DISABLE) { -+ freq = dev_pm_opp_get_freq(opp); -+ -+ /* case of current opp item is disabled */ -+ if (info->current_freq == freq) { -+ freq = 1; -+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev, -+ &freq); -+ if (IS_ERR(new_opp)) { -+ dev_err(info->cpu_dev, -+ "all opp items are disabled\n"); -+ ret = PTR_ERR(new_opp); -+ return notifier_from_errno(ret); -+ } -+ -+ dev_pm_opp_put(new_opp); -+ policy = cpufreq_cpu_get(info->opp_cpu); -+ if (policy) { -+ cpufreq_driver_target(policy, freq / 1000, -+ CPUFREQ_RELATION_L); -+ cpufreq_cpu_put(policy); -+ } -+ } -+ } -+ -+ return notifier_from_errno(ret); -+} -+ - static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) - { - struct device *cpu_dev; -@@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct - info->intermediate_voltage = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); - -+ mutex_init(&info->reg_lock); -+ info->current_freq = clk_get_rate(info->cpu_clk); -+ -+ info->opp_cpu = cpu; -+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; -+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); -+ if (ret) { -+ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu); -+ goto out_disable_inter_clock; -+ } -+ - /* - * If SRAM regulator is present, software "voltage tracking" is needed - * for this CPU power domain. -@@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(st - } - - dev_pm_opp_of_cpumask_remove_table(&info->cpus); -+ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); - } - - static int mtk_cpufreq_init(struct cpufreq_policy *policy) diff --git a/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch b/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch deleted file mode 100644 index 76bd795c0..000000000 --- a/target/linux/mediatek/patches-5.15/350-12-cpufreq-mediatek-Fix-potential-deadlock-problem-in-m.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 6a1bd7cf4ed7a1948f564aaf16d34b7352c0029b Mon Sep 17 00:00:00 2001 -From: Wan Jiabing -Date: Tue, 10 May 2022 17:05:31 +0800 -Subject: [PATCH 12/21] cpufreq: mediatek: Fix potential deadlock problem in - mtk_cpufreq_set_target - -Fix following coccichek error: -./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line -./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line - -mutex_lock is acquired but not released before return. -Use 'goto out' to help releasing the mutex_lock. - -Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support") -Signed-off-by: Wan Jiabing -Reviewed-by: Rex-BC Chen -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct - - if (pre_vproc < 0) { - dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); -- return pre_vproc; -+ ret = pre_vproc; -+ goto out; - } - - freq_hz = freq_table[index].frequency * 1000; -@@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct - if (IS_ERR(opp)) { - dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", - policy->cpu, freq_hz); -- return PTR_ERR(opp); -+ ret = PTR_ERR(opp); -+ goto out; - } - vproc = dev_pm_opp_get_voltage(opp); - dev_pm_opp_put(opp); diff --git a/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch b/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch deleted file mode 100644 index eeaa466c3..000000000 --- a/target/linux/mediatek/patches-5.15/350-13-cpufreq-mediatek-Link-CCI-device-to-CPU.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 15aaf74fb734a3e69b10d00b97b322711b81e222 Mon Sep 17 00:00:00 2001 -From: Rex-BC Chen -Date: Thu, 5 May 2022 19:52:22 +0800 -Subject: [PATCH 13/21] cpufreq: mediatek: Link CCI device to CPU - -In some MediaTek SoCs, like MT8183, CPU and CCI share the same power -supplies. Cpufreq needs to check if CCI devfreq exists and wait until -CCI devfreq ready before scaling frequency. - -Before CCI devfreq is ready, we record the voltage when booting to -kernel and use the max(cpu target voltage, booting voltage) to -prevent cpufreq adjust to the lower voltage which will cause the CCI -crash because of high frequency and low voltage. - -- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start - DVFS when CCI is ready. -- Add platform data for MT8183. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Kevin Hilman -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++- - 1 file changed, 81 insertions(+), 1 deletion(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data { - int proc_max_volt; - int sram_min_volt; - int sram_max_volt; -+ bool ccifreq_supported; - }; - - /* -@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data { - struct mtk_cpu_dvfs_info { - struct cpumask cpus; - struct device *cpu_dev; -+ struct device *cci_dev; - struct regulator *proc_reg; - struct regulator *sram_reg; - struct clk *cpu_clk; -@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info { - struct list_head list_head; - int intermediate_voltage; - bool need_voltage_tracking; -+ int vproc_on_boot; - int pre_vproc; - /* Avoid race condition for regulators between notify and policy */ - struct mutex reg_lock; -@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info { - unsigned long current_freq; - const struct mtk_cpufreq_platform_data *soc_data; - int vtrack_max; -+ bool ccifreq_bound; - }; - - static struct platform_device *cpufreq_pdev; -@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struc - return ret; - } - -+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) -+{ -+ struct device_link *sup_link; -+ -+ if (info->ccifreq_bound) -+ return true; -+ -+ sup_link = device_link_add(info->cpu_dev, info->cci_dev, -+ DL_FLAG_AUTOREMOVE_CONSUMER); -+ if (!sup_link) { -+ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu); -+ return false; -+ } -+ -+ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) -+ return false; -+ -+ info->ccifreq_bound = true; -+ -+ return true; -+} -+ - static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, - unsigned int index) - { -@@ -213,6 +239,14 @@ static int mtk_cpufreq_set_target(struct - dev_pm_opp_put(opp); - - /* -+ * If MediaTek cci is supported but is not ready, we will use the value -+ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy -+ * low voltage crash. -+ */ -+ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info)) -+ vproc = max(vproc, info->vproc_on_boot); -+ -+ /* - * If the new voltage or the intermediate voltage is higher than the - * current voltage, scale up voltage first. - */ -@@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(stru - return notifier_from_errno(ret); - } - -+static struct device *of_get_cci(struct device *cpu_dev) -+{ -+ struct device_node *np; -+ struct platform_device *pdev; -+ -+ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); -+ if (IS_ERR_OR_NULL(np)) -+ return NULL; -+ -+ pdev = of_find_device_by_node(np); -+ of_node_put(np); -+ if (IS_ERR_OR_NULL(pdev)) -+ return NULL; -+ -+ return &pdev->dev; -+} -+ - static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) - { - struct device *cpu_dev; -@@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct - } - info->cpu_dev = cpu_dev; - -+ info->ccifreq_bound = false; -+ if (info->soc_data->ccifreq_supported) { -+ info->cci_dev = of_get_cci(info->cpu_dev); -+ if (IS_ERR_OR_NULL(info->cci_dev)) { -+ ret = PTR_ERR(info->cci_dev); -+ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); -+ return -ENODEV; -+ } -+ } -+ - info->cpu_clk = clk_get(cpu_dev, "cpu"); - if (IS_ERR(info->cpu_clk)) { - ret = PTR_ERR(info->cpu_clk); -@@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct - if (ret) - goto out_disable_mux_clock; - -+ if (info->soc_data->ccifreq_supported) { -+ info->vproc_on_boot = regulator_get_voltage(info->proc_reg); -+ if (info->vproc_on_boot < 0) { -+ dev_err(info->cpu_dev, -+ "invalid Vproc value: %d\n", info->vproc_on_boot); -+ goto out_disable_inter_clock; -+ } -+ } -+ - /* Search a safe voltage for intermediate frequency. */ - rate = clk_get_rate(info->inter_clk); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); -@@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform - .proc_max_volt = 1150000, - .sram_min_volt = 0, - .sram_max_volt = 1150000, -+ .ccifreq_supported = false, -+}; -+ -+static const struct mtk_cpufreq_platform_data mt8183_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1150000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+ .ccifreq_supported = true, - }; - - /* List of machines supported by this driver */ -@@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, - { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, - { } diff --git a/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch b/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch deleted file mode 100644 index 31000cfbe..000000000 --- a/target/linux/mediatek/patches-5.15/350-14-cpufreq-mediatek-Add-support-for-MT8186.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b6be0baa6615afc65c3963adab674e36af1d4d5f Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Thu, 5 May 2022 19:52:23 +0800 -Subject: [PATCH 14/21] cpufreq: mediatek: Add support for MT8186 - -The platform data of MT8186 is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Jia-Wei Chang -Signed-off-by: Rex-BC Chen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = true, - }; - -+static const struct mtk_cpufreq_platform_data mt8186_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 250000, -+ .proc_max_volt = 1118750, -+ .sram_min_volt = 850000, -+ .sram_max_volt = 1118750, -+ .ccifreq_supported = true, -+}; -+ - /* List of machines supported by this driver */ - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, -@@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, -+ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, - { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, - { } diff --git a/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch b/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch deleted file mode 100644 index c0137894c..000000000 --- a/target/linux/mediatek/patches-5.15/350-15-cpufreq-mediatek-Handle-sram-regulator-probe-deferra.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 75d19b24aa3203d6c78e4c431c2cc07157ce12fe Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 13 Jul 2022 13:15:36 +0200 -Subject: [PATCH 15/21] cpufreq: mediatek: Handle sram regulator probe deferral - -If the regulator_get_optional() call for the SRAM regulator returns -a probe deferral, we must bail out and retry probing later: failing -to do this will produce unstabilities on platforms requiring the -handling for this regulator. - -Fixes: ffa7bdf7f344 ("cpufreq: mediatek: Make sram regulator optional") -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -439,9 +439,13 @@ static int mtk_cpu_dvfs_info_init(struct - - /* Both presence and absence of sram regulator are valid cases. */ - info->sram_reg = regulator_get_optional(cpu_dev, "sram"); -- if (IS_ERR(info->sram_reg)) -+ if (IS_ERR(info->sram_reg)) { -+ ret = PTR_ERR(info->sram_reg); -+ if (ret == -EPROBE_DEFER) -+ goto out_free_resources; -+ - info->sram_reg = NULL; -- else { -+ } else { - ret = regulator_enable(info->sram_reg); - if (ret) { - dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); diff --git a/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch b/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch deleted file mode 100644 index 45c4477ff..000000000 --- a/target/linux/mediatek/patches-5.15/350-16-cpufreq-mediatek-fix-error-return-code-in-mtk_cpu_dv.patch +++ /dev/null @@ -1,29 +0,0 @@ -From dd1174c21dacacd6c0129c1dabc5decad35c02c2 Mon Sep 17 00:00:00 2001 -From: Yang Yingliang -Date: Tue, 17 May 2022 21:34:50 +0800 -Subject: [PATCH 16/21] cpufreq: mediatek: fix error return code in - mtk_cpu_dvfs_info_init() - -If regulator_get_voltage() fails, it should return the error code in -mtk_cpu_dvfs_info_init(). - -Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU") -Reported-by: Hulk Robot -Signed-off-by: Yang Yingliang -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Rex-BC Chen -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct - if (info->soc_data->ccifreq_supported) { - info->vproc_on_boot = regulator_get_voltage(info->proc_reg); - if (info->vproc_on_boot < 0) { -+ ret = info->vproc_on_boot; - dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", info->vproc_on_boot); - goto out_disable_inter_clock; diff --git a/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch b/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch deleted file mode 100644 index 557d02b82..000000000 --- a/target/linux/mediatek/patches-5.15/350-17-cpufreq-mediatek-fix-passing-zero-to-PTR_ERR.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 230a74d459244411db91bfd678f17fcf7aedfcd0 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 24 Mar 2023 18:11:27 +0800 -Subject: [PATCH 17/21] cpufreq: mediatek: fix passing zero to 'PTR_ERR' - -In order to prevent passing zero to 'PTR_ERR' in -mtk_cpu_dvfs_info_init(), we fix the return value of of_get_cci() using -error pointer by explicitly casting error number. - -Signed-off-by: Jia-Wei Chang -Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU") -Reported-by: Dan Carpenter -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -373,13 +373,13 @@ static struct device *of_get_cci(struct - struct platform_device *pdev; - - np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); -- if (IS_ERR_OR_NULL(np)) -- return NULL; -+ if (!np) -+ return ERR_PTR(-ENODEV); - - pdev = of_find_device_by_node(np); - of_node_put(np); -- if (IS_ERR_OR_NULL(pdev)) -- return NULL; -+ if (!pdev) -+ return ERR_PTR(-ENODEV); - - return &pdev->dev; - } -@@ -401,7 +401,7 @@ static int mtk_cpu_dvfs_info_init(struct - info->ccifreq_bound = false; - if (info->soc_data->ccifreq_supported) { - info->cci_dev = of_get_cci(info->cpu_dev); -- if (IS_ERR_OR_NULL(info->cci_dev)) { -+ if (IS_ERR(info->cci_dev)) { - ret = PTR_ERR(info->cci_dev); - dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); - return -ENODEV; diff --git a/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch b/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch deleted file mode 100644 index 61531d38a..000000000 --- a/target/linux/mediatek/patches-5.15/350-18-cpufreq-mediatek-fix-KP-caused-by-handler-usage-afte.patch +++ /dev/null @@ -1,149 +0,0 @@ -From fced531b7c7e18192e7982637c8e8f20c29aad64 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 24 Mar 2023 18:11:28 +0800 -Subject: [PATCH 18/21] cpufreq: mediatek: fix KP caused by handler usage after - regulator_put/clk_put - -Any kind of failure in mtk_cpu_dvfs_info_init() will lead to calling -regulator_put() or clk_put() and the KP will occur since the regulator/clk -handlers are used after released in mtk_cpu_dvfs_info_release(). - -To prevent the usage after regulator_put()/clk_put(), the regulator/clk -handlers are addressed in a way of "Free the Last Thing Style". - -Signed-off-by: Jia-Wei Chang -Fixes: 4b9ceb757bbb ("cpufreq: mediatek: Enable clocks and regulators") -Suggested-by: AngeloGioacchino Del Regno -Suggested-by: Dan Carpenter -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 62 +++++++++++++++--------------- - 1 file changed, 30 insertions(+), 32 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -420,7 +420,7 @@ static int mtk_cpu_dvfs_info_init(struct - ret = PTR_ERR(info->inter_clk); - dev_err_probe(cpu_dev, ret, - "cpu%d: failed to get intermediate clk\n", cpu); -- goto out_free_resources; -+ goto out_free_mux_clock; - } - - info->proc_reg = regulator_get_optional(cpu_dev, "proc"); -@@ -428,13 +428,13 @@ static int mtk_cpu_dvfs_info_init(struct - ret = PTR_ERR(info->proc_reg); - dev_err_probe(cpu_dev, ret, - "cpu%d: failed to get proc regulator\n", cpu); -- goto out_free_resources; -+ goto out_free_inter_clock; - } - - ret = regulator_enable(info->proc_reg); - if (ret) { - dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); -- goto out_free_resources; -+ goto out_free_proc_reg; - } - - /* Both presence and absence of sram regulator are valid cases. */ -@@ -442,14 +442,14 @@ static int mtk_cpu_dvfs_info_init(struct - if (IS_ERR(info->sram_reg)) { - ret = PTR_ERR(info->sram_reg); - if (ret == -EPROBE_DEFER) -- goto out_free_resources; -+ goto out_disable_proc_reg; - - info->sram_reg = NULL; - } else { - ret = regulator_enable(info->sram_reg); - if (ret) { - dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); -- goto out_free_resources; -+ goto out_free_sram_reg; - } - } - -@@ -458,13 +458,13 @@ static int mtk_cpu_dvfs_info_init(struct - if (ret) { - dev_err(cpu_dev, - "cpu%d: failed to get OPP-sharing information\n", cpu); -- goto out_free_resources; -+ goto out_disable_sram_reg; - } - - ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); - if (ret) { - dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); -- goto out_free_resources; -+ goto out_disable_sram_reg; - } - - ret = clk_prepare_enable(info->cpu_clk); -@@ -533,43 +533,41 @@ out_disable_mux_clock: - out_free_opp_table: - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - --out_free_resources: -- if (regulator_is_enabled(info->proc_reg)) -- regulator_disable(info->proc_reg); -- if (info->sram_reg && regulator_is_enabled(info->sram_reg)) -+out_disable_sram_reg: -+ if (info->sram_reg) - regulator_disable(info->sram_reg); - -- if (!IS_ERR(info->proc_reg)) -- regulator_put(info->proc_reg); -- if (!IS_ERR(info->sram_reg)) -+out_free_sram_reg: -+ if (info->sram_reg) - regulator_put(info->sram_reg); -- if (!IS_ERR(info->cpu_clk)) -- clk_put(info->cpu_clk); -- if (!IS_ERR(info->inter_clk)) -- clk_put(info->inter_clk); -+ -+out_disable_proc_reg: -+ regulator_disable(info->proc_reg); -+ -+out_free_proc_reg: -+ regulator_put(info->proc_reg); -+ -+out_free_inter_clock: -+ clk_put(info->inter_clk); -+ -+out_free_mux_clock: -+ clk_put(info->cpu_clk); - - return ret; - } - - static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) - { -- if (!IS_ERR(info->proc_reg)) { -- regulator_disable(info->proc_reg); -- regulator_put(info->proc_reg); -- } -- if (!IS_ERR(info->sram_reg)) { -+ regulator_disable(info->proc_reg); -+ regulator_put(info->proc_reg); -+ if (info->sram_reg) { - regulator_disable(info->sram_reg); - regulator_put(info->sram_reg); - } -- if (!IS_ERR(info->cpu_clk)) { -- clk_disable_unprepare(info->cpu_clk); -- clk_put(info->cpu_clk); -- } -- if (!IS_ERR(info->inter_clk)) { -- clk_disable_unprepare(info->inter_clk); -- clk_put(info->inter_clk); -- } -- -+ clk_disable_unprepare(info->cpu_clk); -+ clk_put(info->cpu_clk); -+ clk_disable_unprepare(info->inter_clk); -+ clk_put(info->inter_clk); - dev_pm_opp_of_cpumask_remove_table(&info->cpus); - dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); - } diff --git a/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch b/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch deleted file mode 100644 index 2b7d229f1..000000000 --- a/target/linux/mediatek/patches-5.15/350-19-cpufreq-mediatek-raise-proc-sram-max-voltage-for-MT8.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 24bc42a2d44cb821818717a5c607270921ec5d20 Mon Sep 17 00:00:00 2001 -From: Jia-Wei Chang -Date: Fri, 24 Mar 2023 18:11:29 +0800 -Subject: [PATCH 19/21] cpufreq: mediatek: raise proc/sram max voltage for - MT8516 - -Since the upper boundary of proc/sram voltage of MT8516 is 1300 mV, -which is greater than the value of MT2701 1150 mV, we fix it by adding -the corresponding platform data and specify proc/sram_max_volt to -support MT8516. - -Signed-off-by: Jia-Wei Chang -Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data") -Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") -Reported-by: Nick Hainke -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -711,20 +711,29 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = true, - }; - -+static const struct mtk_cpufreq_platform_data mt8516_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1310000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1310000, -+ .ccifreq_supported = false, -+}; -+ - /* List of machines supported by this driver */ - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, - { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, - { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt8516", .data = &mt8516_platform_data }, - { } - }; - MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); diff --git a/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch b/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch deleted file mode 100644 index 2de8eb639..000000000 --- a/target/linux/mediatek/patches-5.15/350-20-cpufreq-mediatek-Raise-proc-and-sram-max-voltage-for.patch +++ /dev/null @@ -1,58 +0,0 @@ -From fe6ef09358dc0cfead9d383a8676fbe7a40fcef7 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 24 Mar 2023 18:11:30 +0800 -Subject: [PATCH 20/21] cpufreq: mediatek: Raise proc and sram max voltage for - MT7622/7623 - -During the addition of SRAM voltage tracking for CCI scaling, this -driver got some voltage limits set for the vtrack algorithm: these -were moved to platform data first, then enforced in a later commit -6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") -using these as max values for the regulator_set_voltage() calls. - -In this case, the vsram/vproc constraints for MT7622 and MT7623 -were supposed to be the same as MT2701 (and a number of other SoCs), -but that turned out to be a mistake because the aforementioned two -SoCs' maximum voltage for both VPROC and VPROC_SRAM is 1.36V. - -Fix that by adding new platform data for MT7622/7623 declaring the -right {proc,sram}_max_volt parameter. - -Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data") -Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()") -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Jia-Wei Chang -Signed-off-by: Viresh Kumar ---- - drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -693,6 +693,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7622_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1360000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1360000, -+ .ccifreq_supported = false, -+}; -+ - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -724,8 +733,8 @@ static const struct mtk_cpufreq_platform - static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, -- { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, -+ { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, -+ { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch deleted file mode 100644 index 6acd3d607..000000000 --- a/target/linux/mediatek/patches-5.15/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 28 Feb 2023 19:59:22 +0800 -Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988 - -This add cpufreq support for mediatek MT7988 SoC. - -The platform data of MT7988 is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Sam Shih ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -702,6 +702,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7988_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 900000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+ .ccifreq_supported = true, -+}; -+ - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -735,6 +744,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, -+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch deleted file mode 100644 index 6ab05b897..000000000 --- a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch +++ /dev/null @@ -1,53 +0,0 @@ -From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 26 May 2023 10:31:40 +0100 -Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623 - -The MT6380 regulator typically used together with MT7622 does not -support the current maximum processor and SRAM voltage in the cpufreq -driver (1360000uV). -For MT7622 limit processor and SRAM supply voltages to 1350000uV to -avoid having the tracking algorithm request unsupported voltages from -the regulator. - -On MT7623 there is no separate SRAM supply and the maximum voltage used -is 1300000uV. Create dedicated platform data for MT7623 to cover that -case as well. - -Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623") -Suggested-by: Jia-wei Chang -Signed-off-by: Daniel Golle ---- - drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++--- - 1 file changed, 10 insertions(+), 3 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform - static const struct mtk_cpufreq_platform_data mt7622_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -- .proc_max_volt = 1360000, -+ .proc_max_volt = 1350000, - .sram_min_volt = 0, -- .sram_max_volt = 1360000, -+ .sram_max_volt = 1350000, -+ .ccifreq_supported = false, -+}; -+ -+static const struct mtk_cpufreq_platform_data mt7623_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 1300000, - .ccifreq_supported = false, - }; - -@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, -- { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, -+ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, - { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index 25ca9485e..000000000 --- a/target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -315,6 +315,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index 186c66f68..000000000 --- a/target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -737,6 +737,9 @@ enum safexcel_eip_version { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -55,9 +55,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch deleted file mode 100644 index 332f17bae..000000000 --- a/target/linux/mediatek/patches-5.15/405-mt7986-trng-add-rng-support.patch +++ /dev/null @@ -1,41 +0,0 @@ -From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001 -From: "Mingming.Su" -Date: Wed, 30 Jun 2021 16:59:32 +0800 -Subject: [PATCH] mt7986: trng: add rng support - -1. Add trng compatible name for MT7986 -2. Fix mtk_rng_wait_ready() function - -Signed-off-by: Mingming.Su ---- - drivers/char/hw_random/mtk-rng.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -22,7 +22,7 @@ - #define RNG_AUTOSUSPEND_TIMEOUT 100 - - #define USEC_POLL 2 --#define TIMEOUT_POLL 20 -+#define TIMEOUT_POLL 60 - - #define RNG_CTRL 0x00 - #define RNG_EN BIT(0) -@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw - readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready, - ready & RNG_READY, USEC_POLL, - TIMEOUT_POLL); -- return !!ready; -+ return !!(ready & RNG_READY); - } - - static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p - #endif /* CONFIG_PM */ - - static const struct of_device_id mtk_rng_match[] = { -+ { .compatible = "mediatek,mt7986-rng" }, - { .compatible = "mediatek,mt7623-rng" }, - {}, - }; diff --git a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch deleted file mode 100644 index 4f703dbc0..000000000 --- a/target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -85,6 +85,7 @@ struct serial8250_config { - #define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks: - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ -+#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */ - - #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -289,7 +289,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2746,6 +2746,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch deleted file mode 100644 index cc9e9c55e..000000000 --- a/target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: David Bauer -To: linux-mtd@lists.infradead.org -Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV -Date: Sat, 13 Feb 2021 16:10:47 +0100 - -The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K -sectors as well as block protection and Dual-/Quad-read. - -Tested on: Ubiquiti UniFi 6 LR - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/winbond.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/spi-nor/winbond.c -+++ b/drivers/mtd/spi-nor/winbond.c -@@ -98,6 +98,10 @@ static const struct flash_info winbond_p - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024, -+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | -+ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | -+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, - { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, - { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024, diff --git a/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch deleted file mode 100644 index 3b67343a7..000000000 --- a/target/linux/mediatek/patches-5.15/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ /dev/null @@ -1,130 +0,0 @@ -From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:29:51 +0800 -Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private - data - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 29 +++++++++--------------- - include/linux/platform_data/spi-mt65xx.h | 17 -------------- - 2 files changed, 11 insertions(+), 35 deletions(-) - delete mode 100644 include/linux/platform_data/spi-mt65xx.h - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -14,7 +14,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -142,6 +141,8 @@ struct mtk_spi { - struct device *dev; - dma_addr_t tx_dma; - dma_addr_t rx_dma; -+ u32 sample_sel; -+ u32 get_tick_dly; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m - .no_need_unprepare = true, - }; - --/* -- * A piece of default chip info unless the platform -- * supplies it. -- */ --static const struct mtk_chip_config mtk_default_chip_info = { -- .sample_sel = 0, -- .tick_delay = 0, --}; -- - static const struct of_device_id mtk_spi_of_match[] = { - { .compatible = "mediatek,spi-ipm", - .data = (void *)&mtk_ipm_compat, -@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma - { - u16 cpha, cpol; - u32 reg_val; -- struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); - - cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma - else - reg_val &= ~SPI_CMD_CS_POL; - -- if (chip_config->sample_sel) -+ if (mdata->sample_sel) - reg_val |= SPI_CMD_SAMPLE_SEL; - else - reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma - if (mdata->dev_comp->ipm_design) { - reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CMD_IPM_GET_TICKDLY_OFFSET); - writel(reg_val, mdata->base + SPI_CMD_REG); - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; -- reg_val |= ((chip_config->tick_delay & 0x3) -+ reg_val |= ((mdata->get_tick_dly & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi - { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); - -- if (!spi->controller_data) -- spi->controller_data = (void *)&mtk_default_chip_info; -- - if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) - /* CS de-asserted, gpiolib will handle inversion */ - gpiod_direction_output(spi->cs_gpiod, 0); -@@ -1117,6 +1105,10 @@ static int mtk_spi_probe(struct platform - mdata = spi_master_get_devdata(master); - mdata->dev_comp = of_id->data; - -+ /* Set device configs to default first. Calibrate it later. */ -+ mdata->sample_sel = 0; -+ mdata->get_tick_dly = 2; -+ - if (mdata->dev_comp->enhance_timing) - master->mode_bits |= SPI_CS_HIGH; - ---- a/include/linux/platform_data/spi-mt65xx.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * MTK SPI bus driver definitions -- * -- * Copyright (c) 2015 MediaTek Inc. -- * Author: Leilk Liu -- */ -- --#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H --#define ____LINUX_PLATFORM_DATA_SPI_MTK_H -- --/* Board specific platform_data */ --struct mtk_chip_config { -- u32 sample_sel; -- u32 tick_delay; --}; --#endif diff --git a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch deleted file mode 100644 index a335f8c54..000000000 --- a/target/linux/mediatek/patches-5.15/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ /dev/null @@ -1,236 +0,0 @@ -From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:35:52 +0800 -Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ - include/linux/spi/spi.h | 42 ++++++++++++ - 2 files changed, 179 insertions(+) - ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -1250,6 +1250,70 @@ static int spi_transfer_wait(struct spi_ - return 0; - } - -+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) -+{ -+ int datalen = ctlr->cal_rule->datalen; -+ int addrlen = ctlr->cal_rule->addrlen; -+ u8 *buf; -+ int ret; -+ int i; -+ struct list_head *cal_head, *listptr; -+ struct spi_cal_target *target; -+ -+ /* Calculate calibration result */ -+ int hit_val, total_hit, origin; -+ bool hit; -+ -+ /* Make sure we can start calibration */ -+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) -+ return 0; -+ -+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); -+ if(!buf) -+ return -ENOMEM; -+ -+ ret = ctlr->append_caldata(ctlr); -+ if (ret) -+ goto cal_end; -+ -+ cal_head = ctlr->cal_target; -+ list_for_each(listptr, cal_head) { -+ target = list_entry(listptr, struct spi_cal_target, list); -+ -+ hit = false; -+ hit_val = 0; -+ total_hit = 0; -+ origin = *target->cal_item; -+ -+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { -+ *target->cal_item = i; -+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); -+ if(ret) -+ break; -+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); -+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { -+ hit = true; -+ hit_val += i; -+ total_hit++; -+ dev_dbg(&spi->dev, "golden data matches data read!\n"); -+ } -+ } -+ if(hit) { -+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); -+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); -+ } else { -+ *target->cal_item = origin; -+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); -+ } -+ } -+ -+cal_end: -+ kfree(buf); -+ return ret? ret: 0; -+} -+EXPORT_SYMBOL_GPL(spi_do_calibration); -+ - static void _spi_transfer_delay_ns(u32 ns) - { - if (!ns) -@@ -2037,6 +2101,75 @@ void spi_flush_queue(struct spi_controll - /*-------------------------------------------------------------------------*/ - - #if defined(CONFIG_OF) -+static inline void alloc_cal_data(struct list_head **cal_target, -+ struct spi_cal_rule **cal_rule, bool enable) -+{ -+ if(enable) { -+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); -+ INIT_LIST_HEAD(*cal_target); -+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); -+ } else { -+ kfree(*cal_target); -+ kfree(*cal_rule); -+ } -+} -+ -+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, -+ struct device_node *nc) -+{ -+ u32 value; -+ int rc; -+ const char *cal_mode; -+ -+ rc = of_property_read_bool(nc, "spi-cal-enable"); -+ if (rc) -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); -+ else -+ return 0; -+ -+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); -+ if(!rc) { -+ if(strcmp("read-data", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; -+ } else if(strcmp("read-pp", cal_mode) == 0) { -+ ctlr->cal_rule->mode = SPI_CAL_READ_PP; -+ return 0; -+ } else if(strcmp("read-sfdp", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; -+ return 0; -+ } -+ } else -+ goto err; -+ -+ ctlr->cal_rule->datalen = 0; -+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->datalen = value; -+ -+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); -+ rc = of_property_read_u8_array(nc, "spi-cal-data", -+ ctlr->cal_rule->match_data, value); -+ if(rc) -+ kfree(ctlr->cal_rule->match_data); -+ } -+ -+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->addrlen = value; -+ -+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); -+ rc = of_property_read_u32_array(nc, "spi-cal-addr", -+ ctlr->cal_rule->addr, value); -+ if(rc) -+ kfree(ctlr->cal_rule->addr); -+ } -+ return 0; -+ -+err: -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); -+ return 0; -+} -+ - static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, - struct device_node *nc) - { -@@ -2155,6 +2288,10 @@ of_register_spi_device(struct spi_contro - if (rc) - goto err_out; - -+ rc = of_spi_parse_cal_dt(ctlr, spi, nc); -+ if (rc) -+ goto err_out; -+ - /* Store a pointer to the node in the device structure */ - of_node_get(nc); - spi->dev.of_node = nc; ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -290,6 +290,40 @@ struct spi_driver { - struct device_driver driver; - }; - -+enum { -+ SPI_CAL_READ_DATA = 0, -+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ -+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ -+}; -+ -+struct nand_addr { -+ unsigned int lun; -+ unsigned int plane; -+ unsigned int eraseblock; -+ unsigned int page; -+ unsigned int dataoffs; -+}; -+ -+/** -+ * Read calibration rule from device dts node. -+ * Once calibration result matches the rule, we regard is as success. -+ */ -+struct spi_cal_rule { -+ int datalen; -+ u8 *match_data; -+ int addrlen; -+ u32 *addr; -+ int mode; -+}; -+ -+struct spi_cal_target { -+ u32 *cal_item; -+ int cal_min; /* min of cal_item */ -+ int cal_max; /* max of cal_item */ -+ int step; /* Increase/decrease cal_item */ -+ struct list_head list; -+}; -+ - static inline struct spi_driver *to_spi_driver(struct device_driver *drv) - { - return drv ? container_of(drv, struct spi_driver, driver) : NULL; -@@ -665,6 +699,11 @@ struct spi_controller { - void *dummy_rx; - void *dummy_tx; - -+ /* For calibration */ -+ int (*append_caldata)(struct spi_controller *ctlr); -+ struct list_head *cal_target; -+ struct spi_cal_rule *cal_rule; -+ - int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); - - /* -@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board - { return 0; } - #endif - -+extern int spi_do_calibration(struct spi_controller *ctlr, -+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); -+ - /* If you're hotplugging an adapter with devices (parport, usb, etc) - * use spi_new_device() to describe each device. You can also call - * spi_unregister_device() to start making that device vanish, but diff --git a/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch deleted file mode 100644 index aaacab013..000000000 --- a/target/linux/mediatek/patches-5.15/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:37:55 +0800 -Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mem.c | 8 ++++++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem, - } - EXPORT_SYMBOL_GPL(spi_mem_exec_op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), -+ void *priv) -+{ -+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); -+} -+EXPORT_SYMBOL_GPL(spi_mem_do_calibration); -+ - /** - * spi_mem_get_name() - Return the SPI mem device name to be used by the - * upper layer if necessary ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem - int spi_mem_exec_op(struct spi_mem *mem, - const struct spi_mem_op *op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *, u32 *, int, u8 *, int), -+ void *priv); -+ - const char *spi_mem_get_name(struct spi_mem *mem); - - struct spi_mem_dirmap_desc * diff --git a/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch deleted file mode 100644 index 0044c9cc2..000000000 --- a/target/linux/mediatek/patches-5.15/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ /dev/null @@ -1,43 +0,0 @@ -From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:03 +0800 -Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration - paramter - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -802,6 +802,21 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_HANDLED; - } - -+static int mtk_spi_append_caldata(struct spi_controller *ctlr) -+{ -+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); -+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr); -+ -+ cal_target->cal_item = &mdata->get_tick_dly; -+ cal_target->cal_min = 0; -+ cal_target->cal_max = 7; -+ cal_target->step = 1; -+ -+ list_add(&cal_target->list, ctlr->cal_target); -+ -+ return 0; -+} -+ - static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, - struct spi_mem_op *op) - { -@@ -1094,6 +1109,7 @@ static int mtk_spi_probe(struct platform - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; - master->use_gpio_descriptors = true; -+ master->append_caldata = mtk_spi_append_caldata; - - of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); - if (!of_id) { diff --git a/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch deleted file mode 100644 index 5f1e2b9ce..000000000 --- a/target/linux/mediatek/patches-5.15/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:56 +0800 -Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for - spinand - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -966,6 +966,56 @@ static int spinand_manufacturer_match(st - return -ENOTSUPP; - } - -+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { -+ struct spinand_device *spinand = (struct spinand_device *)priv; -+ struct device *dev = &spinand->spimem->spi->dev; -+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); -+ struct nand_pos pos; -+ struct nand_page_io_req req; -+ u8 status; -+ int ret; -+ -+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { -+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); -+ return -EINVAL; -+ } -+ -+ ret = spinand_reset_op(spinand); -+ if (ret) -+ return ret; -+ -+ /* We should store our golden data in first target because -+ * we can't switch target at this moment. -+ */ -+ pos = (struct nand_pos){ -+ .target = 0, -+ .lun = *addr, -+ .plane = *(addr+1), -+ .eraseblock = *(addr+2), -+ .page = *(addr+3), -+ }; -+ -+ req = (struct nand_page_io_req){ -+ .pos = pos, -+ .dataoffs = *(addr+4), -+ .datalen = readlen, -+ .databuf.in = buf, -+ .mode = MTD_OPS_AUTO_OOB, -+ }; -+ -+ ret = spinand_load_page_op(spinand, &req); -+ if (ret) -+ return ret; -+ -+ ret = spinand_wait(spinand, &status); -+ if (ret < 0) -+ return ret; -+ -+ ret = spi_mem_exec_op(spinand->spimem, &op); -+ -+ return 0; -+} -+ - static int spinand_id_detect(struct spinand_device *spinand) - { - u8 *id = spinand->id.data; -@@ -1216,6 +1266,10 @@ static int spinand_init(struct spinand_d - if (!spinand->scratchbuf) - return -ENOMEM; - -+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); -+ if (ret) -+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); -+ - ret = spinand_detect(spinand); - if (ret) - goto err_free_bufs; diff --git a/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch deleted file mode 100644 index 279e6a9c2..000000000 --- a/target/linux/mediatek/patches-5.15/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:40:59 +0800 -Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for - spi-nor - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 5 ++++- - drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1007,7 +1007,10 @@ int spinand_cal_read(void *priv, u32 *ad - if (ret) - return ret; - -- ret = spinand_wait(spinand, &status); -+ ret = spinand_wait(spinand, -+ SPINAND_READ_INITIAL_DELAY_US, -+ SPINAND_READ_POLL_DELAY_US, -+ &status); - if (ret < 0) - return ret; - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -3112,6 +3112,18 @@ static void spi_nor_debugfs_init(struct - info->id_len, info->id); - } - -+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) -+{ -+ struct spi_nor *nor = (struct spi_nor *)priv; -+ -+ nor->reg_proto = SNOR_PROTO_1_1_1; -+ nor->read_proto = SNOR_PROTO_1_1_1; -+ nor->read_opcode = SPINOR_OP_READ; -+ nor->read_dummy = 0; -+ -+ return nor->controller_ops->read(nor, *addr, readlen, buf); -+} -+ - static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, - const char *name) - { -@@ -3185,6 +3197,9 @@ int spi_nor_scan(struct spi_nor *nor, co - if (!nor->bouncebuf) - return -ENOMEM; - -+ if(nor->spimem) -+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); -+ - info = spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) - return PTR_ERR(info); diff --git a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index b8964f4e7..000000000 --- a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -367,6 +367,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch deleted file mode 100644 index 4ca9f9c72..000000000 --- a/target/linux/mediatek/patches-5.15/600-v5.16-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch +++ /dev/null @@ -1,332 +0,0 @@ -From: Chuanjia Liu -Date: Mon, 23 Aug 2021 11:27:59 +0800 -Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 - -There are two independent PCIe controllers in MT2712 and MT7622 -platform. Each of them should contain an independent MSI domain. - -In old dts architecture, MSI domain will be inherited from the root -bridge, and all of the devices will share the same MSI domain. -Hence that, the PCIe devices will not work properly if the irq number -which required is more than 32. - -Split the PCIe node for MT2712 and MT7622 platform to comply with -the hardware design and fix MSI issue. - -Signed-off-by: Chuanjia Liu -Acked-by: Ryder Lee -Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com -Signed-off-by: Matthias Brugger ---- - ---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi -@@ -916,64 +916,67 @@ - }; - }; - -- pcie: pcie@11700000 { -+ pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; -- reg = <0 0x11700000 0 0x1000>, -- <0 0x112ff000 0 0x1000>; -- reg-names = "port0", "port1"; -+ reg = <0 0x112ff000 0 0x1000>; -+ reg-names = "port1"; -+ linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, -- <&pericfg CLK_PERI_PCIE0>, -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; -- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ clock-names = "sys_ck1", "ahb_ck1"; -+ phys = <&u3port1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0000 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <1>; -- ranges; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; - }; -+ }; -+ -+ pcie0: pcie@11700000 { -+ compatible = "mediatek,mt2712-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11700000 0 0x1000>; -+ reg-names = "port0"; -+ linux,pci-domain = <0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -+ <&pericfg CLK_PERI_PCIE0>; -+ clock-names = "sys_ck0", "ahb_ck0"; -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0800 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <1>; -- ranges; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; - }; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -303,18 +303,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -233,18 +233,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -804,75 +804,83 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,generic-pciecfg", "syscon"; -+ reg = <0 0x1a140000 0 0x1000>; -+ }; -+ -+ pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; -- reg = <0 0x1a140000 0 0x1000>, -- <0 0x1a143000 0 0x1000>, -- <0 0x1a145000 0 0x1000>; -- reg-names = "subsys", "port0", "port1"; -+ reg = <0 0x1a143000 0 0x1000>; -+ reg-names = "port0"; -+ linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, -- <&pciesys CLK_PCIE_P1_MAC_EN>, -- <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, -- <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, -- <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, -- <&pciesys CLK_PCIE_P1_OBFF_EN>, -- <&pciesys CLK_PCIE_P0_PIPE_EN>, -- <&pciesys CLK_PCIE_P1_PIPE_EN>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", -- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", -- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; -+ <&pciesys CLK_PCIE_P0_PIPE_EN>; -+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", -+ "axi_ck0", "obff_ck0", "pipe_ck0"; -+ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; - -- pcie0: pcie@0,0 { -- reg = <0x0000 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <1>; -- ranges; -- status = "disabled"; -- -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; - }; -+ }; - -- pcie1: pcie@1,0 { -- reg = <0x0800 0 0 0 0>; -- #address-cells = <3>; -- #size-cells = <2>; -- #interrupt-cells = <1>; -- ranges; -- status = "disabled"; -+ pcie1: pcie@1a145000 { -+ compatible = "mediatek,mt7622-pcie"; -+ device_type = "pci"; -+ reg = <0 0x1a145000 0 0x1000>; -+ reg-names = "port1"; -+ linux,pci-domain = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, -+ /* designer has connect RC1 with p0_ahb clock */ -+ <&pciesys CLK_PCIE_P0_AHB_EN>, -+ <&pciesys CLK_PCIE_P1_AUX_EN>, -+ <&pciesys CLK_PCIE_P1_AXI_EN>, -+ <&pciesys CLK_PCIE_P1_OBFF_EN>, -+ <&pciesys CLK_PCIE_P1_PIPE_EN>; -+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", -+ "axi_ck1", "obff_ck1", "pipe_ck1"; -+ -+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; -+ status = "disabled"; - -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -- interrupt-controller; -- #address-cells = <0>; -- #interrupt-cells = <1>; -- }; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; - }; - }; - diff --git a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch deleted file mode 100644 index b7311e042..000000000 --- a/target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: qizhong cheng -Date: Mon, 27 Dec 2021 21:31:10 +0800 -Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to - stabilize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -be delayed 100ms (TPVPERL) for the power and clock to become stable. - -Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com -Signed-off-by: qizhong cheng -Signed-off-by: Lorenzo Pieralisi -Acked-by: Pali Rohár ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); - -+ /* -+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -+ * be delayed 100ms (TPVPERL) for the power and clock to become stable. -+ */ -+ msleep(100); -+ - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val = readl(port->base + PCIE_RST_CTRL); - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | diff --git a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch deleted file mode 100644 index d58082aa6..000000000 --- a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -844,6 +844,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - pcie1: pcie@1a145000 { -@@ -882,6 +888,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - sata: sata@1a200000 { diff --git a/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch deleted file mode 100644 index 252ef080f..000000000 --- a/target/linux/mediatek/patches-5.15/603-v5.16-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch +++ /dev/null @@ -1,203 +0,0 @@ -From patchwork Thu May 28 06:16:48 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Chuanjia Liu -X-Patchwork-Id: 11574797 -Return-Path: - -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30A5E1392 - for ; - Thu, 28 May 2020 06:29:05 +0000 (UTC) -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by mail.kernel.org (Postfix) with ESMTPS id 08B6320721 - for ; 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Thu, 28 May 2020 14:18:52 +0800 -From: -To: , , -Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node -Date: Thu, 28 May 2020 14:16:48 +0800 -Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com> -X-Mailer: git-send-email 2.18.0 -In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -References: <20200528061648.32078-1-chuanjia.liu@mediatek.com> -MIME-Version: 1.0 -X-MTK: N -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20200527_232901_719172_E5A99C62 -X-CRM114-Status: GOOD ( 11.61 ) -X-Spam-Score: -0.2 (/) -X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: - Content analysis details: (-0.2 points) - pts rule name description - ---- ---------------------- - -------------------------------------------------- - -0.0 SPF_PASS SPF: sender matches SPF record - 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record - 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 - encoding - -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from - author's domain - 0.1 DKIM_SIGNED Message has a DKIM or DK signature, - not necessarily - valid - -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature - -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from - envelope-from domain - 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay - lines -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.29 -Precedence: list -List-Id: -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, - srv_heupstream@mediatek.com, "chuanjia.liu" , - linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, - jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org, - yong.wu@mediatek.com, bhelgaas@google.com, - linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk -Sender: "Linux-mediatek" -Errors-To: - linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org - -From: "chuanjia.liu" - -Remove unused property and add pciecfg node. - -Signed-off-by: chuanjia.liu ---- - arch/arm/boot/dts/mt7629-rfb.dts | 3 ++- - arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++---------- - 2 files changed, 15 insertions(+), 11 deletions(-) - ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -149,9 +149,10 @@ - }; - }; - --&pcie { -+&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; -+ status = "okay"; - }; - - &pciephy1 { ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -382,16 +382,21 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7629-pciecfg", "syscon"; -+ reg = <0x1a140000 0x1000>; -+ }; -+ -+ pcie1: pcie@1a145000 { - compatible = "mediatek,mt7629-pcie"; - device_type = "pci"; -- reg = <0x1a140000 0x1000>, -- <0x1a145000 0x1000>; -- reg-names = "subsys","port1"; -+ reg = <0x1a145000 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, -@@ -412,21 +417,19 @@ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; -- - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; diff --git a/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index 2bebfddf5..000000000 --- a/target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - generic_handle_domain_irq(port->irq_domain, - bit - INTX_SHIFT); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch deleted file mode 100644 index da33aaa72..000000000 --- a/target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Tue, 4 Jan 2022 12:07:00 +0000 -Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and - devad fields - -Add a couple of helpers and definitions to extract the clause 45 regad -and devad fields from the regnum passed into MDIO drivers. - -Tested-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: Russell King (Oracle) -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - include/linux/mdio.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/include/linux/mdio.h -+++ b/include/linux/mdio.h -@@ -7,6 +7,7 @@ - #define __LINUX_MDIO_H__ - - #include -+#include - #include - - /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit -@@ -14,6 +15,7 @@ - */ - #define MII_ADDR_C45 (1<<30) - #define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) - #define MII_REGADDR_C45_MASK GENMASK(15, 0) - - struct gpio_desc; -@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; - } - -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+ - static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, - u16 regnum) - { diff --git a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch deleted file mode 100644 index efda5fda4..000000000 --- a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ /dev/null @@ -1,128 +0,0 @@ -From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 4 Jan 2022 12:07:46 +0000 -Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO - access - -Implement read and write access to IEEE 802.3 Clause 45 Ethernet -phy registers while making use of new mdiobus_c45_regad and -mdiobus_c45_devad helpers. - -Tested on the Ubiquiti UniFi 6 LR access point featuring -MediaTek MT7622BV WiSoC with Aquantia AQR112C. - -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + - 2 files changed, 60 insertions(+), 13 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -323,13 +323,35 @@ static int _mtk_mdio_write(struct mtk_et - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_WRITE | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr) | -- PHY_IAC_DATA(write_data), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -346,12 +368,33 @@ static int _mtk_mdio_read(struct mtk_eth - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_C22_READ | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_READ | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_C22_READ | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -897,6 +940,7 @@ static int mtk_mdio_init(struct mtk_eth - eth->mii_bus->name = "mdio"; - eth->mii_bus->read = mtk_mdio_read; - eth->mii_bus->write = mtk_mdio_write; -+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; - eth->mii_bus->priv = eth; - eth->mii_bus->parent = eth->dev; - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -402,9 +402,12 @@ - #define PHY_IAC_ADDR_MASK GENMASK(24, 20) - #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) - #define PHY_IAC_CMD_MASK GENMASK(19, 18) -+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) - #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) - #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) -+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) - #define PHY_IAC_START_MASK GENMASK(17, 16) -+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) - #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) - #define PHY_IAC_DATA_MASK GENMASK(15, 0) - #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index 917a458d3..000000000 --- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,91 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -832,6 +832,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -876,6 +879,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -937,7 +943,7 @@ - }; - - hifsys: clock-controller@1af00000 { -- compatible = "mediatek,mt7622-hifsys"; -+ compatible = "mediatek,mt7622-hifsys", "syscon"; - reg = <0 0x1af00000 0 0x70>; - #clock-cells = <1>; - }; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err, slot; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - slot = of_get_pci_domain_nr(dev->of_node); - if (slot < 0) { - for_each_available_child_of_node(node, child) { diff --git a/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd0..000000000 --- a/target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch deleted file mode 100644 index 52069496c..000000000 --- a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -23,11 +23,17 @@ - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <950000>; -- }; -- -+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low -+ * voltage condition that can cause a hang when rebooting the RT3200/E8450. -+ * -+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 -+ * -+ * opp-300000000 { -+ * opp-hz = /bits/ 64 <300000000>; -+ * opp-microvolt = <950000>; -+ * }; -+ * -+ */ - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index 7b27bd2f6..000000000 --- a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,1204 +0,0 @@ -From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 11 Jun 2023 00:48:10 +0100 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c. -Add support for such PHYs by introducing a new driver with basic -support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. - -Signed-off-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1140 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -11798,6 +11798,15 @@ S: Maintained - F: drivers/net/pcs/pcs-mtk-lynxi.c - F: include/linux/pcs/pcs-mtk-lynxi.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- /dev/null -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -0,0 +1,1116 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_GPHY_ID_MT7981 0x03a29461 -+#define MTK_GPHY_ID_MT7988 0x03a29481 -+ -+#define MTK_EXT_PAGE_ACCESS 0x1f -+#define MTK_PHY_PAGE_STANDARD 0x0000 -+#define MTK_PHY_PAGE_EXTENDED_3 0x0003 -+ -+#define MTK_PHY_LPI_REG_14 0x14 -+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) -+ -+#define MTK_PHY_LPI_REG_1c 0x1c -+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 -+ -+#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -+#define TXRESERVE_MIN 0 -+#define TXRESERVE_MAX 7 -+ -+#define MTK_PHY_ANARG_RG 0x10 -+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) -+ -+/* Registers on MDIO_MMD_VEND1 */ -+#define MTK_PHY_TXVLD_DA_RG 0x12 -+#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -+#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -+#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -+#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -+#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -+#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -+#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -+#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) -+ -+#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) -+ -+#define MTK_PHY_LDO_OUTPUT_V 0xd7 -+ -+#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -+#define MTK_PHY_RG_CAL_CKINV BIT(12) -+#define MTK_PHY_RG_ANA_CALEN BIT(8) -+#define MTK_PHY_RG_ZCALEN_A BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -+#define MTK_PHY_RG_ZCALEN_B BIT(12) -+#define MTK_PHY_RG_ZCALEN_C BIT(8) -+#define MTK_PHY_RG_ZCALEN_D BIT(4) -+#define MTK_PHY_RG_TXVOS_CALEN BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_RG_TX_FILTER 0xfe -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -+#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -+#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) -+ -+#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -+#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -+#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -+#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_AD_CAL_COMP 0x17a -+#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) -+ -+#define MTK_PHY_RG_AD_CAL_CLK 0x17b -+#define MTK_PHY_DA_CAL_CLK BIT(0) -+ -+#define MTK_PHY_RG_AD_CALIN 0x17c -+#define MTK_PHY_DA_CALIN_FLAG BIT(0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -+#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -+#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -+#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -+#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -+#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -+#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -+#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -+#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG19b 0x19b -+#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) -+ -+#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -+#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -+#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -+#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -+#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -+#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -+#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -+#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -+#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -+#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 -+ -+#define MTK_PHY_RG_DEV1E_REG234 0x234 -+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) -+ -+#define MTK_PHY_RG_LPF_CNT_VAL 0x235 -+ -+#define MTK_PHY_RG_DEV1E_REG238 0x238 -+#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG239 0x239 -+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG27C 0x27c -+#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -+#define MTK_PHY_RG_DEV1E_REG27D 0x27d -+#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -+#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -+#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) -+ -+#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -+#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -+#define MTK_PHY_LPI_TR_READY BIT(9) -+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) -+ -+#define MTK_PHY_RG_DEV1E_REG323 0x323 -+#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -+#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) -+ -+#define MTK_PHY_RG_DEV1E_REG324 0x324 -+#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -+#define MTK_PHY_SMI_DET_MAX_EN BIT(8) -+ -+#define MTK_PHY_RG_DEV1E_REG326 0x326 -+#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -+#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -+#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -+#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -+#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) -+ -+#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -+#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 -+ -+#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -+#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -+#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -+#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 -+ -+#define MTK_PHY_RG_BG_RASEL 0x115 -+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) -+ -+/* These macro privides efuse parsing for internal phy. */ -+#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) -+ -+#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -+#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) -+ -+enum { -+ NO_PAIR, -+ PAIR_A, -+ PAIR_B, -+ PAIR_C, -+ PAIR_D, -+}; -+ -+enum { -+ GPHY_PORT0, -+ GPHY_PORT1, -+ GPHY_PORT2, -+ GPHY_PORT3, -+}; -+ -+enum calibration_mode { -+ EFUSE_K, -+ SW_K -+}; -+ -+enum CAL_ITEM { -+ REXT, -+ TX_OFFSET, -+ TX_AMP, -+ TX_R50, -+ TX_VCM -+}; -+ -+enum CAL_MODE { -+ EFUSE_M, -+ SW_M -+}; -+ -+static int mtk_socphy_read_page(struct phy_device *phydev) -+{ -+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -+} -+ -+static int mtk_socphy_write_page(struct phy_device *phydev, int page) -+{ -+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -+} -+ -+/* One calibration cycle consists of: -+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high -+ * until AD_CAL_COMP is ready to output calibration result. -+ * 2.Wait until DA_CAL_CLK is available. -+ * 3.Fetch AD_CAL_COMP_OUT. -+ */ -+static int cal_cycle(struct phy_device *phydev, int devad, -+ u32 regnum, u16 mask, u16 cal_val) -+{ -+ int reg_val; -+ int ret; -+ -+ phy_modify_mmd(phydev, devad, regnum, -+ mask, cal_val); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ -+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_AD_CAL_CLK, reg_val, -+ reg_val & MTK_PHY_DA_CAL_CLK, 500, -+ ANALOG_INTERNAL_OPERATION_MAX_US, false); -+ if (ret) { -+ phydev_err(phydev, "Calibration cycle timeout\n"); -+ return ret; -+ } -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> -+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; -+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); -+ -+ return ret; -+} -+ -+static int rext_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, -+ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, -+ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); -+ -+ return 0; -+} -+ -+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 rext_cal_val[2]; -+ -+ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); -+ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); -+ rext_fill_result(phydev, rext_cal_val); -+ -+ return 0; -+} -+ -+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); -+ -+ return 0; -+} -+ -+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_offset_cal_val[4]; -+ -+ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); -+ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); -+ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); -+ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); -+ -+ tx_offset_fill_result(phydev, tx_offset_cal_val); -+ -+ return 0; -+} -+ -+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ int i; -+ int bias[16] = {}; -+ const int vals_9461[16] = { 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7 }; -+ const int vals_9481[16] = { 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10 }; -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ /* We add some calibration to efuse values -+ * due to board level influence. -+ * GBE: +7, TBT: +1, HBT: +4, TST: +7 -+ */ -+ memcpy(bias, (const void *)vals_9461, sizeof(bias)); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ memcpy(bias, (const void *)vals_9481, sizeof(bias)); -+ break; -+ } -+ -+ /* Prevent overflow */ -+ for (i = 0; i < 12; i++) { -+ if (buf[i >> 2] + bias[i] > 63) { -+ buf[i >> 2] = 63; -+ bias[i] = 0; -+ } -+ } -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); -+ -+ return 0; -+} -+ -+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_amp_cal_val[4]; -+ -+ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); -+ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); -+ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); -+ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); -+ tx_amp_fill_result(phydev, tx_amp_cal_val); -+ -+ return 0; -+} -+ -+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, -+ u8 txg_calen_x) -+{ -+ int bias = 0; -+ u16 reg, val; -+ -+ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) -+ bias = -2; -+ -+ val = clamp_val(bias + tx_r50_cal_val, 0, 63); -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ reg = MTK_PHY_DA_TX_R50_PAIR_A; -+ break; -+ case PAIR_B: -+ reg = MTK_PHY_DA_TX_R50_PAIR_B; -+ break; -+ case PAIR_C: -+ reg = MTK_PHY_DA_TX_R50_PAIR_C; -+ break; -+ case PAIR_D: -+ reg = MTK_PHY_DA_TX_R50_PAIR_D; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); -+ -+ return 0; -+} -+ -+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, -+ u8 txg_calen_x) -+{ -+ u16 tx_r50_cal_val; -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); -+ break; -+ case PAIR_B: -+ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); -+ break; -+ case PAIR_C: -+ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); -+ break; -+ case PAIR_D: -+ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); -+ break; -+ default: -+ return -EINVAL; -+ } -+ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); -+ -+ return 0; -+} -+ -+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -+{ -+ u8 lower_idx, upper_idx, txreserve_val; -+ u8 lower_ret, upper_ret; -+ int ret; -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_CAL_CKINV); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ -+ switch (rg_txreserve_x) { -+ case PAIR_A: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_A, -+ MTK_PHY_DASN_DAC_IN0_A_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_A, -+ MTK_PHY_DASN_DAC_IN1_A_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ break; -+ case PAIR_B: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_B, -+ MTK_PHY_DASN_DAC_IN0_B_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_B, -+ MTK_PHY_DASN_DAC_IN1_B_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B); -+ break; -+ case PAIR_C: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_C, -+ MTK_PHY_DASN_DAC_IN0_C_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_C, -+ MTK_PHY_DASN_DAC_IN1_C_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_C); -+ break; -+ case PAIR_D: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_D, -+ MTK_PHY_DASN_DAC_IN0_D_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_D, -+ MTK_PHY_DASN_DAC_IN1_D_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_D); -+ break; -+ default: -+ ret = -EINVAL; -+ goto restore; -+ } -+ -+ lower_idx = TXRESERVE_MIN; -+ upper_idx = TXRESERVE_MAX; -+ -+ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); -+ while ((upper_idx - lower_idx) > 1) { -+ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); -+ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ txreserve_val << 12 | txreserve_val << 8 | -+ txreserve_val << 4 | txreserve_val); -+ if (ret == 1) { -+ upper_idx = txreserve_val; -+ upper_ret = ret; -+ } else if (ret == 0) { -+ lower_idx = txreserve_val; -+ lower_ret = ret; -+ } else { -+ goto restore; -+ } -+ } -+ -+ if (lower_idx == TXRESERVE_MIN) { -+ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ ret = lower_ret; -+ } else if (upper_idx == TXRESERVE_MAX) { -+ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ ret = upper_ret; -+ } -+ if (ret < 0) -+ goto restore; -+ -+ /* We calibrate TX-VCM in different logic. Check upper index and then -+ * lower index. If this calibration is valid, apply lower index's result. -+ */ -+ ret = upper_ret - lower_ret; -+ if (ret == 1) { -+ ret = 0; -+ /* Make sure we use upper_idx in our calibration system */ -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); -+ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && -+ lower_ret == 1) { -+ ret = 0; -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", -+ lower_idx); -+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && -+ lower_ret == 0) { -+ ret = 0; -+ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", -+ upper_idx); -+ } else { -+ ret = -EINVAL; -+ } -+ -+restore: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | -+ MTK_PHY_RG_ZCALEN_D); -+ -+ return ret; -+} -+ -+static void mt798x_phy_common_finetune(struct phy_device *phydev) -+{ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* EnabRandUpdTrig = 1 */ -+ __phy_write(phydev, 0x11, 0x2f00); -+ __phy_write(phydev, 0x12, 0xe); -+ __phy_write(phydev, 0x10, 0x8fb0); -+ -+ /* NormMseLoThresh = 85 */ -+ __phy_write(phydev, 0x11, 0x55a0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x83aa); -+ -+ /* TrFreeze = 0 */ -+ __phy_write(phydev, 0x11, 0x0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9686); -+ -+ /* SSTrKp1000Slv = 5 */ -+ __phy_write(phydev, 0x11, 0xbaef); -+ __phy_write(phydev, 0x12, 0x2e); -+ __phy_write(phydev, 0x10, 0x968c); -+ -+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, -+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 -+ */ -+ __phy_write(phydev, 0x11, 0xd10a); -+ __phy_write(phydev, 0x12, 0x34); -+ __phy_write(phydev, 0x10, 0x8f82); -+ -+ /* VcoSlicerThreshBitsHigh */ -+ __phy_write(phydev, 0x11, 0x5555); -+ __phy_write(phydev, 0x12, 0x55); -+ __phy_write(phydev, 0x10, 0x8ec0); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, -+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, -+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); -+ -+ /* rg_tr_lpf_cnt_val = 512 */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); -+ -+ /* IIR2 related */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); -+ -+ /* FFE peaking */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, -+ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, -+ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); -+ -+ /* Disable LDO pump */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); -+ /* Adjust LDO output voltage */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -+} -+ -+static void mt7981_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[8] = { 0x01ce, 0x01c1, -+ 0x020f, 0x0202, -+ 0x03d0, 0x03c0, -+ 0x0013, 0x0005 }; -+ int i, k; -+ -+ /* 100M eye finetune: -+ * Keep middle level of TX MLT3 shapper as default. -+ * Only change TX MLT3 overshoot level here. -+ */ -+ for (k = 0, i = 1; i < 12; i++) { -+ if (i % 3 == 0) -+ continue; -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); -+ } -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ -+ __phy_write(phydev, 0x11, 0xc71); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 6 */ -+ __phy_write(phydev, 0x11, 0x600); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate = 1 */ -+ __phy_write(phydev, 0x11, 0x4c2a); -+ __phy_write(phydev, 0x12, 0x3e); -+ __phy_write(phydev, 0x10, 0x8fa4); -+ -+ /* FfeUpdGainForce = 4 */ -+ __phy_write(phydev, 0x11, 0x240); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9680); -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt7988_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, -+ 0x020d, 0x0206, 0x0384, 0x03d0, -+ 0x03c6, 0x030a, 0x0011, 0x0005 }; -+ int i; -+ -+ /* Set default MLT3 shaper first */ -+ for (i = 0; i < 12; i++) -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); -+ -+ /* TCT finetune */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); -+ -+ /* Disable TX power saving */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, -+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ -+ __phy_write(phydev, 0x11, 0x671); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 5 */ -+ __phy_write(phydev, 0x11, 0x500); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate is 1 at default on mt7988 */ -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); -+ /* TxClkOffset = 2 */ -+ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, -+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt798x_phy_eee(struct phy_device *phydev) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, -+ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | -+ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ 0xff)); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_TESTMUX_ADC_CTRL, -+ MTK_PHY_RG_TXEN_DIG_MASK); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, -+ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | -+ MTK_PHY_LPI_SLV_SEND_TX_EN, -+ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, -+ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | -+ MTK_PHY_LPI_TXPCS_LOC_RCV, -+ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, -+ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, -+ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | -+ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, -+ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ 0x33) | -+ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | -+ MTK_PHY_LPI_VCO_EEE_STG0_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, -+ MTK_PHY_EEE_WAKE_MAS_INT_DC | -+ MTK_PHY_EEE_WAKE_SLV_INT_DC); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, -+ MTK_PHY_SMI_DETCNT_MAX_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | -+ MTK_PHY_SMI_DET_MAX_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, -+ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | -+ MTK_PHY_TREC_UPDATE_ENAB_CLR | -+ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | -+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* Regsigdet_sel_1000 = 0 */ -+ __phy_write(phydev, 0x11, 0xb); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9690); -+ -+ /* REG_EEE_st2TrKf1000 = 3 */ -+ __phy_write(phydev, 0x11, 0x114f); -+ __phy_write(phydev, 0x12, 0x2); -+ __phy_write(phydev, 0x10, 0x969a); -+ -+ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ -+ __phy_write(phydev, 0x11, 0x3028); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x969e); -+ -+ /* RegEEE_slv_wake_int_timer_tar = 8 */ -+ __phy_write(phydev, 0x11, 0x5010); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a0); -+ -+ /* RegEEE_trfreeze_timer2 = 586 */ -+ __phy_write(phydev, 0x11, 0x24a); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a8); -+ -+ /* RegEEE100Stg1_tar = 16 */ -+ __phy_write(phydev, 0x11, 0x3210); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96b8); -+ -+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ -+ __phy_write(phydev, 0x11, 0x1463); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96ca); -+ -+ /* DfeTailEnableVgaThresh1000 = 27 */ -+ __phy_write(phydev, 0x11, 0x36); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8f80); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); -+ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); -+ -+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -+} -+ -+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_OFFSET & TX_AMP have no SW calibration. */ -+ switch (cal_item) { -+ case TX_VCM: -+ ret = tx_vcm_cal_sw(phydev, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair, u32 *buf) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_VCM has no efuse calibration. */ -+ switch (cal_item) { -+ case REXT: -+ ret = rext_cal_efuse(phydev, buf); -+ break; -+ case TX_OFFSET: -+ ret = tx_offset_cal_efuse(phydev, buf); -+ break; -+ case TX_AMP: -+ ret = tx_amp_cal_efuse(phydev, buf); -+ break; -+ case TX_R50: -+ ret = tx_r50_cal_efuse(phydev, buf, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ enum CAL_MODE cal_mode, u8 start_pair, -+ u8 end_pair, u32 *buf) -+{ -+ int ret; -+ -+ switch (cal_mode) { -+ case EFUSE_M: -+ ret = cal_efuse(phydev, cal_item, start_pair, -+ end_pair, buf); -+ break; -+ case SW_M: -+ ret = cal_sw(phydev, cal_item, start_pair, end_pair); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (ret) { -+ phydev_err(phydev, "cal %d failed\n", cal_item); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt798x_phy_calibration(struct phy_device *phydev) -+{ -+ int ret = 0; -+ u32 *buf; -+ size_t len; -+ struct nvmem_cell *cell; -+ -+ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); -+ if (IS_ERR(cell)) { -+ if (PTR_ERR(cell) == -EPROBE_DEFER) -+ return PTR_ERR(cell); -+ return 0; -+ } -+ -+ buf = (u32 *)nvmem_cell_read(cell, &len); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ nvmem_cell_put(cell); -+ -+ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { -+ phydev_err(phydev, "invalid efuse data\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); -+ if (ret) -+ goto out; -+ -+out: -+ kfree(buf); -+ return ret; -+} -+ -+static int mt798x_phy_config_init(struct phy_device *phydev) -+{ -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ mt7981_phy_finetune(phydev); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ mt7988_phy_finetune(phydev); -+ break; -+ } -+ -+ mt798x_phy_common_finetune(phydev); -+ mt798x_phy_eee(phydev); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ -+static struct phy_driver mtk_socphy_driver[] = { -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -+ .name = "MediaTek MT7981 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), -+ .name = "MediaTek MT7988 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_socphy_driver); -+ -+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, -+ { } -+}; -+ -+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -+MODULE_AUTHOR("Daniel Golle "); -+MODULE_AUTHOR("SkyLake Huang "); -+MODULE_LICENSE("GPL"); -+ -+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch deleted file mode 100644 index 83d0f26bf..000000000 --- a/target/linux/mediatek/patches-5.15/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch +++ /dev/null @@ -1,213 +0,0 @@ -From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 13 Jun 2023 03:27:14 +0100 -Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default - state - -Initialize LEDs and set sane default values. -Read boottrap register and apply LED polarities accordingly to get -uniform behavior from all LEDs on MT7988. -Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus -which should point to the syscon holding the boottrap register. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++-- - 1 file changed, 136 insertions(+), 8 deletions(-) - ---- a/drivers/net/phy/mediatek-ge-soc.c -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -1,11 +1,13 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #define MTK_GPHY_ID_MT7981 0x03a29461 - #define MTK_GPHY_ID_MT7988 0x03a29481 -@@ -208,9 +210,40 @@ - #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f - #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -+/* Registers on MDIO_MMD_VEND2 */ -+#define MTK_PHY_LED0_ON_CTRL 0x24 -+#define MTK_PHY_LED1_ON_CTRL 0x26 -+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) -+#define MTK_PHY_LED_ON_LINK1000 BIT(0) -+#define MTK_PHY_LED_ON_LINK100 BIT(1) -+#define MTK_PHY_LED_ON_LINK10 BIT(2) -+#define MTK_PHY_LED_ON_LINKDOWN BIT(3) -+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ -+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ -+#define MTK_PHY_LED_FORCE_ON BIT(6) -+#define MTK_PHY_LED_POLARITY BIT(14) -+#define MTK_PHY_LED_ENABLE BIT(15) -+ -+#define MTK_PHY_LED0_BLINK_CTRL 0x25 -+#define MTK_PHY_LED1_BLINK_CTRL 0x27 -+#define MTK_PHY_LED_1000TX BIT(0) -+#define MTK_PHY_LED_1000RX BIT(1) -+#define MTK_PHY_LED_100TX BIT(2) -+#define MTK_PHY_LED_100RX BIT(3) -+#define MTK_PHY_LED_10TX BIT(4) -+#define MTK_PHY_LED_10RX BIT(5) -+#define MTK_PHY_LED_COLLISION BIT(6) -+#define MTK_PHY_LED_RX_CRC_ERR BIT(7) -+#define MTK_PHY_LED_RX_IDLE_ERR BIT(8) -+#define MTK_PHY_LED_FORCE_BLINK BIT(9) -+ - #define MTK_PHY_RG_BG_RASEL 0x115 - #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */ -+#define RG_GPIO_MISC_TPBANK0 0x6f0 -+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) -+ - /* These macro privides efuse parsing for internal phy. */ - #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) - #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -@@ -238,13 +271,6 @@ enum { - PAIR_D, - }; - --enum { -- GPHY_PORT0, -- GPHY_PORT1, -- GPHY_PORT2, -- GPHY_PORT3, --}; -- - enum calibration_mode { - EFUSE_K, - SW_K -@@ -263,6 +289,10 @@ enum CAL_MODE { - SW_M - }; - -+struct mtk_socphy_shared { -+ u32 boottrap; -+}; -+ - static int mtk_socphy_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct - return mt798x_phy_calibration(phydev); - } - -+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted) -+{ -+ struct pinctrl *pinctrl; -+ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE | -+ MTK_PHY_LED_ON_LINK1000 | -+ MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK10; -+ const u16 led_blink_defaults = MTK_PHY_LED_1000TX | -+ MTK_PHY_LED_1000RX | -+ MTK_PHY_LED_100TX | -+ MTK_PHY_LED_100RX | -+ MTK_PHY_LED_10TX | -+ MTK_PHY_LED_10RX; -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ led_on_ctrl_defaults ^ -+ (inverted ? MTK_PHY_LED_POLARITY : 0)); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, -+ led_on_ctrl_defaults); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, -+ led_blink_defaults); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, -+ led_blink_defaults); -+ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); -+ if (IS_ERR(pinctrl)) -+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n"); -+ -+ return 0; -+} -+ -+static int mt7988_phy_probe_shared(struct phy_device *phydev) -+{ -+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ struct regmap *regmap; -+ u32 reg; -+ int ret; -+ -+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, -+ * LED_C and LED_D respectively. At the same time those pins are used to -+ * bootstrap configuration of the reference clock source (LED_A), -+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). -+ * In practise this is done using a LED and a resistor pulling the pin -+ * either to GND or to VIO. -+ * The detected value at boot time is accessible at run-time using the -+ * TPBANK0 register located in the gpio base of the pinctrl, in order -+ * to read it here it needs to be referenced by a phandle called -+ * 'mediatek,pio' in the MDIO bus hosting the PHY. -+ * The 4 bits in TPBANK0 are kept as package shared data and are used to -+ * set LED polarity for each of the LED0. -+ */ -+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); -+ if (ret) -+ return ret; -+ -+ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); -+ -+ return 0; -+} -+ -+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev) -+{ -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ -+ if (priv->boottrap & BIT(phydev->mdio.addr)) -+ return false; -+ -+ return true; -+} -+ -+static int mt7988_phy_probe(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, -+ sizeof(struct mtk_socphy_shared)); -+ if (err) -+ return err; -+ -+ if (phy_package_probe_once(phydev)) { -+ err = mt7988_phy_probe_shared(phydev); -+ if (err) -+ return err; -+ } -+ -+ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ - static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, diff --git a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch deleted file mode 100644 index 598d9d0d2..000000000 --- a/target/linux/mediatek/patches-5.15/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch +++ /dev/null @@ -1,63 +0,0 @@ -From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 6 Apr 2023 23:36:50 +0100 -Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink - -MAC drivers using phylink expect SGMII in-band-status to be switched off -when attached to a PHY. Make sure this is the case also for mxl-gpy which -keeps SGMII in-band-status in case of SGMII interface mode is used. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -191,8 +191,11 @@ static bool gpy_2500basex_chk(struct phy - - phydev->speed = SPEED_2500; - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -+ -+ if (!phydev->phylink) -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ - return true; - } - -@@ -216,6 +219,14 @@ static int gpy_config_aneg(struct phy_de - u32 adv; - int ret; - -+ /* Disable SGMII auto-negotiation if using phylink */ -+ if (phydev->phylink) { -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ } -+ - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. -@@ -306,6 +317,8 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ if (phydev->phylink) -+ break; - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, - VSPEC1_SGMII_CTRL_ANEN, 0); - if (ret < 0) -@@ -317,7 +330,7 @@ static void gpy_update_interface(struct - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) - break; - /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed - * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch deleted file mode 100644 index 7151eb35c..000000000 --- a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 28 Feb 2023 17:53:37 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/Kconfig | 7 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++ - 3 files changed, 226 insertions(+) - create mode 100644 drivers/net/phy/mediatek-2p5ge.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -305,6 +305,13 @@ config MEDIATEK_GE_SOC_PHY - present in the SoCs efuse and will dynamically calibrate VCM - (common-mode voltage) during startup. - -+config MEDIATEK_2P5G_PHY -+ tristate "MediaTek 2.5G Ethernet PHY" -+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST -+ default NET_MEDIATEK_SOC -+ help -+ Supports the MediaTek 2.5G Ethernet PHY. -+ - config MICREL_PHY - tristate "Micrel PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell - obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o -+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o - obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o diff --git a/target/linux/mediatek/patches-5.15/800-v5.17-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch b/target/linux/mediatek/patches-5.15/800-v5.17-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch deleted file mode 100644 index 785bfe53f..000000000 --- a/target/linux/mediatek/patches-5.15/800-v5.17-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 98e2c4efae214fb7086cac9117616eb6ea11475d Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun -Date: Thu, 9 Dec 2021 17:42:34 +0000 -Subject: [PATCH] nvmem: mtk-efuse: support minimum one byte access stride and - granularity - -In order to support nvmem bits property, should support minimum 1 byte -read stride and minimum 1 byte read granularity at the same time. - -Signed-off-by: Chunfeng Yun -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20211209174235.14049-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/mtk-efuse.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - ---- a/drivers/nvmem/mtk-efuse.c -+++ b/drivers/nvmem/mtk-efuse.c -@@ -19,11 +19,12 @@ static int mtk_reg_read(void *context, - unsigned int reg, void *_val, size_t bytes) - { - struct mtk_efuse_priv *priv = context; -- u32 *val = _val; -- int i = 0, words = bytes / 4; -+ void __iomem *addr = priv->base + reg; -+ u8 *val = _val; -+ int i; - -- while (words--) -- *val++ = readl(priv->base + reg + (i++ * 4)); -+ for (i = 0; i < bytes; i++, val++) -+ *val = readb(addr + i); - - return 0; - } -@@ -45,8 +46,8 @@ static int mtk_efuse_probe(struct platfo - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -- econfig.stride = 4; -- econfig.word_size = 4; -+ econfig.stride = 1; -+ econfig.word_size = 1; - econfig.reg_read = mtk_reg_read; - econfig.size = resource_size(res); - econfig.priv = priv; diff --git a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch b/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch deleted file mode 100644 index 691a7c039..000000000 --- a/target/linux/mediatek/patches-5.15/801-phy-phy-mtk-tphy-Add-PCIe-2-lane-efuse-support.patch +++ /dev/null @@ -1,225 +0,0 @@ -From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Tue, 25 Jan 2022 16:50:47 +0800 -Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support - -Add PCIe 2 lane efuse support in tphy driver. - -Signed-off-by: Jie Yang -Signed-off-by: Zhanyong Wang ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++ - 1 file changed, 140 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -44,6 +44,15 @@ - #define SSUSB_SIFSLV_V2_U3PHYD 0x200 - #define SSUSB_SIFSLV_V2_U3PHYA 0x400 - -+/* version V4 sub-banks offset base address */ -+/* pcie phy banks */ -+#define SSUSB_SIFSLV_V4_SPLLC 0x000 -+#define SSUSB_SIFSLV_V4_CHIP 0x100 -+#define SSUSB_SIFSLV_V4_U3PHYD 0x900 -+#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 -+ -+#define SSUSB_LN1_OFFSET 0x10000 -+ - #define U3P_MISC_REG1 0x04 - #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) - -@@ -320,6 +329,7 @@ enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, - MTK_PHY_V3, -+ MTK_PHY_V4, - }; - - struct mtk_phy_pdata { -@@ -369,6 +379,9 @@ struct mtk_phy_instance { - u32 efuse_intr; - u32 efuse_tx_imp; - u32 efuse_rx_imp; -+ u32 efuse_intr_ln1; -+ u32 efuse_tx_imp_ln1; -+ u32 efuse_rx_imp_ln1; - int eye_src; - int eye_vrt; - int eye_term; -@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk - } - } - -+static void phy_v4_banks_init(struct mtk_tphy *tphy, -+ struct mtk_phy_instance *instance) -+{ -+ struct u2phy_banks *u2_banks = &instance->u2_banks; -+ struct u3phy_banks *u3_banks = &instance->u3_banks; -+ -+ switch (instance->type) { -+ case PHY_TYPE_USB2: -+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; -+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; -+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; -+ break; -+ case PHY_TYPE_USB3: -+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; -+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; -+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; -+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; -+ break; -+ case PHY_TYPE_PCIE: -+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; -+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; -+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; -+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; -+ break; -+ default: -+ dev_err(tphy->dev, "incompatible PHY type\n"); -+ return; -+ } -+} -+ - static void phy_parse_property(struct mtk_tphy *tphy, - struct mtk_phy_instance *instance) - { -@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy - - dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", - instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); -+ -+ if (tphy->pdata->version != MTK_PHY_V4) -+ break; -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); -+ break; -+ } -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); -+ break; -+ } -+ -+ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); -+ if (ret) { -+ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); -+ break; -+ } -+ -+ /* no efuse, ignore it */ -+ if (!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) { -+ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); -+ instance->efuse_sw_en = 0; -+ break; -+ } -+ -+ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", -+ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, -+ instance->efuse_tx_imp_ln1); - break; - default: - dev_err(dev, "no sw efuse for type %d\n", instance->type); -@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy - writel(tmp, u2_banks->com + U3P_USBPHYACR1); - break; - case PHY_TYPE_USB3: -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); -+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -+ -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); -+ tmp &= ~P3D_RG_TX_IMPEL; -+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp); -+ tmp |= P3D_RG_FORCE_TX_IMPEL; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); -+ -+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); -+ tmp &= ~P3D_RG_RX_IMPEL; -+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp); -+ tmp |= P3D_RG_FORCE_RX_IMPEL; -+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); -+ -+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); -+ tmp &= ~P3A_RG_IEXT_INTR; -+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); -+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -+ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n", -+ __func__, instance->efuse_tx_imp, -+ instance->efuse_rx_imp, instance->efuse_intr); -+ -+ break; - case PHY_TYPE_PCIE: - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy - tmp &= ~P3A_RG_IEXT_INTR; - tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -+ if (!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) -+ break; -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); -+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); -+ tmp &= ~P3D_RG_TX_IMPEL; -+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1); -+ tmp |= P3D_RG_FORCE_TX_IMPEL; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0); -+ -+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); -+ tmp &= ~P3D_RG_RX_IMPEL; -+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1); -+ tmp |= P3D_RG_FORCE_RX_IMPEL; -+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1); -+ -+ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); -+ tmp &= ~P3A_RG_IEXT_INTR; -+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1); -+ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0); -+ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", -+ __func__, instance->efuse_tx_imp_ln1, -+ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); - break; - default: - dev_warn(dev, "no sw efuse for type %d\n", instance->type); -@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct - case MTK_PHY_V3: - phy_v2_banks_init(tphy, instance); - break; -+ case MTK_PHY_V4: -+ phy_v4_banks_init(tphy, instance); -+ break; - default: - dev_err(dev, "phy version is not supported\n"); - return ERR_PTR(-EINVAL); -@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v - .version = MTK_PHY_V3, - }; - -+static const struct mtk_phy_pdata tphy_v4_pdata = { -+ .avoid_rx_sen_degradation = false, -+ .sw_efuse_supported = true, -+ .version = MTK_PHY_V4, -+}; -+ - static const struct mtk_phy_pdata mt8173_pdata = { - .avoid_rx_sen_degradation = true, - .version = MTK_PHY_V1, -@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph - { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, - { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, - { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, -+ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, - { }, - }; - MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); diff --git a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch b/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch deleted file mode 100644 index 3b8285bf4..000000000 --- a/target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001 -From: Zhanyong Wang -Date: Tue, 25 Jan 2022 19:03:34 +0800 -Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism - support - -add auto-load-valid check mechanism support - -Signed-off-by: Zhanyong Wang ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++-- - 1 file changed, 64 insertions(+), 3 deletions(-) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -376,9 +376,13 @@ struct mtk_phy_instance { - u32 type_sw_reg; - u32 type_sw_index; - u32 efuse_sw_en; -+ bool efuse_alv_en; -+ u32 efuse_autoloadvalid; - u32 efuse_intr; - u32 efuse_tx_imp; - u32 efuse_rx_imp; -+ bool efuse_alv_ln1_en; -+ u32 efuse_ln1_autoloadvalid; - u32 efuse_intr_ln1; - u32 efuse_tx_imp_ln1; - u32 efuse_rx_imp_ln1; -@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy - { - struct device *dev = &instance->phy->dev; - int ret = 0; -+ bool alv = false; - - /* tphy v1 doesn't support sw efuse, skip it */ - if (!tphy->pdata->sw_efuse_supported) { -@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy - - switch (instance->type) { - case PHY_TYPE_USB2: -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); -+ if (alv) { -+ instance->efuse_alv_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", -+ &instance->efuse_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "u2 auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); - if (ret) { - dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); -@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy - - case PHY_TYPE_USB3: - case PHY_TYPE_PCIE: -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid"); -+ if (alv) { -+ instance->efuse_alv_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid", -+ &instance->efuse_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "u3 auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); - if (ret) { - dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); -@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy - if (tphy->pdata->version != MTK_PHY_V4) - break; - -+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1"); -+ if (alv) { -+ instance->efuse_alv_ln1_en = alv; -+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1", -+ &instance->efuse_ln1_autoloadvalid); -+ if (ret) { -+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret); -+ break; -+ } -+ dev_info(dev, -+ "pcie auto load valid efuse: ENABLE with value: %u\n", -+ instance->efuse_ln1_autoloadvalid); -+ } -+ - ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); - if (ret) { - dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); -@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy - - switch (instance->type) { - case PHY_TYPE_USB2: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u2_banks->misc + U3P_MISC_REG1); - tmp |= MR1_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u2_banks->misc + U3P_MISC_REG1); -@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy - writel(tmp, u2_banks->com + U3P_USBPHYACR1); - break; - case PHY_TYPE_USB3: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy - - break; - case PHY_TYPE_PCIE: -+ if (instance->efuse_alv_en && -+ instance->efuse_autoloadvalid == 1) -+ break; -+ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); - tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS; - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV); -@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy - tmp &= ~P3A_RG_IEXT_INTR; - tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); -- if (!instance->efuse_intr_ln1 && -- !instance->efuse_rx_imp_ln1 && -- !instance->efuse_tx_imp_ln1) -+ -+ if ((!instance->efuse_intr_ln1 && -+ !instance->efuse_rx_imp_ln1 && -+ !instance->efuse_tx_imp_ln1) || -+ (instance->efuse_alv_ln1_en && -+ instance->efuse_ln1_autoloadvalid == 1)) - break; - - tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV); diff --git a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch deleted file mode 100644 index 7a10dac05..000000000 --- a/target/linux/mediatek/patches-5.15/804-pwm-add-mt7986-support.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data - .has_ck_26m_sel = true, - }; - -+static const struct pwm_mediatek_of_data mt7986_pwm_data = { -+ .num_pwms = 2, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+}; -+ - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, -@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, - { }, diff --git a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch deleted file mode 100644 index c58ae9640..000000000 --- a/target/linux/mediatek/patches-5.15/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 18 Jan 2023 02:48:41 +0000 -Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for - raw_to_mcelsius - -Instead of having if-else logic selecting either raw_to_mcelsius_v1 or -raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function -pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the -probe function. - -Signed-off-by: Daniel Golle ---- - drivers/thermal/mtk_thermal.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -292,6 +292,8 @@ struct mtk_thermal { - - const struct mtk_thermal_data *conf; - struct mtk_thermal_bank banks[MAX_NUM_ZONES]; -+ -+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); - }; - - /* MT8183 thermal sensor data */ -@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature( - for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { - raw = readl(mt->thermal_base + conf->msr[i]); - -- if (mt->conf->version == MTK_THERMAL_V1) { -- temp = raw_to_mcelsius_v1( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } else { -- temp = raw_to_mcelsius_v2( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } -+ temp = mt->raw_to_mcelsius( -+ mt, conf->bank_data[bank->id].sensors[i], raw); -+ - - /* - * The first read of a sensor often contains very high bogus -@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -+ if (mt->conf->version == MTK_THERMAL_V1) -+ mt->raw_to_mcelsius = raw_to_mcelsius_v1; -+ else -+ mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) - mtk_thermal_init_bank(mt, i, apmixed_phys_base, diff --git a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch deleted file mode 100644 index 65311d571..000000000 --- a/target/linux/mediatek/patches-5.15/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch +++ /dev/null @@ -1,240 +0,0 @@ -From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 30 Nov 2022 13:19:39 +0000 -Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981 - -Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. -Brings code to assign values from efuse as well as new function to -convert raw temperature to millidegree celsius, as found in MediaTek's -SDK sources (but cleaned up and de-duplicated) - -[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b -Signed-off-by: Daniel Golle ---- - drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++-- - 1 file changed, 132 insertions(+), 5 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -150,6 +150,20 @@ - #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) - #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) - -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros can be used for MT7981 and MT7986. -+ */ -+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) -+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) -+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) -+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) -+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) -+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) -+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) -+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) -+ - enum { - VTS1, - VTS2, -@@ -163,6 +177,7 @@ enum { - enum mtk_thermal_version { - MTK_THERMAL_V1 = 1, - MTK_THERMAL_V2, -+ MTK_THERMAL_V3, - }; - - /* MT2701 thermal sensors */ -@@ -245,6 +260,27 @@ enum mtk_thermal_version { - /* The calibration coefficient of sensor */ - #define MT8183_CALIBRATION 153 - -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT7986_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT7986 */ -+#define MT7986_NUM_SENSORS 1 -+ -+/* The number of banks in the MT7986 */ -+#define MT7986_NUM_ZONES 1 -+ -+/* The number of sensing points per bank */ -+#define MT7986_NUM_SENSORS_PER_ZONE 1 -+ -+/* MT7986 thermal sensors */ -+#define MT7986_TS1 0 -+ -+/* The number of controller in the MT7986 */ -+#define MT7986_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT7986_CALIBRATION 165 -+ - struct mtk_thermal; - - struct thermal_bank_cfg { -@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762 - static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; - static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; - -+/* MT7986 thermal sensor data */ -+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; -+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; -+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; -+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; -+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; -+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; -+ - /* - * The MT8173 thermal controller has four banks. Each bank can read up to - * four temperature sensors simultaneously. The MT8173 has a total of 5 -@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8 - .version = MTK_THERMAL_V1, - }; - -+/* -+ * MT7986 uses AUXADC Channel 11 for raw data access. -+ */ -+static const struct mtk_thermal_data mt7986_thermal_data = { -+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT7986_NUM_ZONES, -+ .num_sensors = MT7986_NUM_SENSORS, -+ .vts_index = mt7986_vts_index, -+ .cali_val = MT7986_CALIBRATION, -+ .num_controller = MT7986_NUM_CONTROLLER, -+ .controller_offset = mt7986_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 1, -+ .sensors = mt7986_bank_data, -+ }, -+ }, -+ .msr = mt7986_msr, -+ .adcpnp = mt7986_adcpnp, -+ .sensor_mux_values = mt7986_mux_values, -+ .version = MTK_THERMAL_V3, -+}; -+ - /** - * raw_to_mcelsius - convert a raw ADC value to mcelsius - * @mt: The thermal controller -@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk - return (format_2 - tmp) * 100; - } - -+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 tmp; -+ -+ if (raw == 0) -+ return 0; -+ -+ raw &= 0xfff; -+ tmp = 100000 * 15 / 16 * 10000; -+ tmp /= 4096 - 512 + mt->adc_ge; -+ tmp /= 1490; -+ tmp *= raw - mt->vts[sensno] - 2900; -+ -+ return mt->degc_cali * 500 - tmp; -+} -+ - /** - * mtk_thermal_get_bank - get bank - * @bank: The bank -@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2( - return 0; - } - -+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) -+{ -+ if (!CALIB_BUF1_VALID_V3(buf[1])) -+ return -EINVAL; -+ -+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); -+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); -+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); -+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); -+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); -+ -+ if (CALIB_BUF1_ID_V3(buf[1]) == 0) -+ mt->o_slope = 0; -+ -+ return 0; -+} -+ - static int mtk_thermal_get_calibration_data(struct device *dev, - struct mtk_thermal *mt) - { -@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d - - /* Start with default values */ - mt->adc_ge = 512; -+ mt->adc_oe = 512; - for (i = 0; i < mt->conf->num_sensors; i++) - mt->vts[i] = 260; - mt->degc_cali = 40; -@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d - goto out; - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - ret = mtk_thermal_extract_efuse_v1(mt, buf); -- else -+ break; -+ case MTK_THERMAL_V2: - ret = mtk_thermal_extract_efuse_v2(mt, buf); -+ break; -+ case MTK_THERMAL_V3: -+ ret = mtk_thermal_extract_efuse_v3(mt, buf); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } - - if (ret) { - dev_info(dev, "Device not calibrated, using default calibration values\n"); -@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the - .data = (void *)&mt7622_thermal_data, - }, - { -+ .compatible = "mediatek,mt7986-thermal", -+ .data = (void *)&mt7986_thermal_data, -+ }, -+ { - .compatible = "mediatek,mt8183-thermal", - .data = (void *)&mt8183_thermal_data, - }, { -@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat - goto err_disable_clk_auxadc; - } - -- if (mt->conf->version == MTK_THERMAL_V2) { -+ if (mt->conf->version != MTK_THERMAL_V1) { - mtk_thermal_turn_on_buffer(apmixed_base); - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - mt->raw_to_mcelsius = raw_to_mcelsius_v1; -- else -+ break; -+ case MTK_THERMAL_V2: - mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ break; -+ case MTK_THERMAL_V3: -+ mt->raw_to_mcelsius = raw_to_mcelsius_v3; -+ break; -+ default: -+ break; -+ } - - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) diff --git a/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch deleted file mode 100644 index 8f27462cb..000000000 --- a/target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 19 Apr 2023 20:25:51 +0100 -Subject: [PATCH] pwm: mediatek: Add support for MT7981 - -The PWM unit on MT7981 uses different register offsets than previous -MediaTek PWM units. Add support for these new offsets and add support -for PWM on MT7981 which has 3 PWM channels, one of them is typically -used for a temperature controlled fan. - -Signed-off-by: Daniel Golle ---- - drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++-------- - 1 file changed, 33 insertions(+), 8 deletions(-) - ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { - unsigned int num_pwms; - bool pwm45_fixup; - bool has_ck_26m_sel; -+ const unsigned int *reg_offset; - }; - - /** -@@ -59,10 +60,14 @@ struct pwm_mediatek_chip { - const struct pwm_mediatek_of_data *soc; - }; - --static const unsigned int pwm_mediatek_reg_offset[] = { -+static const unsigned int mtk_pwm_reg_offset_v1[] = { - 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 - }; - -+static const unsigned int mtk_pwm_reg_offset_v2[] = { -+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 -+}; -+ - static inline struct pwm_mediatek_chip * - to_pwm_mediatek_chip(struct pwm_chip *chip) - { -@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s - unsigned int num, unsigned int offset, - u32 value) - { -- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); -+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset); - } - - static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, -@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data - .num_pwms = 8, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7622_pwm_data = { - .num_pwms = 6, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7623_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = true, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7628_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = true, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7629_pwm_data = { - .num_pwms = 1, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt8183_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, -+}; -+ -+static const struct pwm_mediatek_of_data mt7981_pwm_data = { -+ .num_pwms = 3, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v2, - }; - - static const struct pwm_mediatek_of_data mt7986_pwm_data = { - .num_pwms = 2, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct of_device_id pwm_mediatek_of_match[] = { -@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, - { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch b/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch deleted file mode 100644 index f2be73714..000000000 --- a/target/linux/mediatek/patches-5.15/820-v5.16-dt-bindings-pinctrl-mt8195-add-rsel-define.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 26564c44357e19d03c124550bbd0b5851e6638c2 Mon Sep 17 00:00:00 2001 -From: Zhiyong Tao -Date: Fri, 24 Sep 2021 16:06:28 +0800 -Subject: [PATCH] dt-bindings: pinctrl: mt8195: add rsel define - -This patch adds rsel define for mt8195. - -Signed-off-by: Zhiyong Tao -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com -Signed-off-by: Linus Walleij ---- - include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/include/dt-bindings/pinctrl/mt65xx.h -+++ b/include/dt-bindings/pinctrl/mt65xx.h -@@ -16,6 +16,15 @@ - #define MTK_PUPD_SET_R1R0_10 102 - #define MTK_PUPD_SET_R1R0_11 103 - -+#define MTK_PULL_SET_RSEL_000 200 -+#define MTK_PULL_SET_RSEL_001 201 -+#define MTK_PULL_SET_RSEL_010 202 -+#define MTK_PULL_SET_RSEL_011 203 -+#define MTK_PULL_SET_RSEL_100 204 -+#define MTK_PULL_SET_RSEL_101 205 -+#define MTK_PULL_SET_RSEL_110 206 -+#define MTK_PULL_SET_RSEL_111 207 -+ - #define MTK_DRIVE_2mA 2 - #define MTK_DRIVE_4mA 4 - #define MTK_DRIVE_6mA 6 diff --git a/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch b/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch deleted file mode 100644 index aa9f879e3..000000000 --- a/target/linux/mediatek/patches-5.15/821-v5.16-pinctrl-mediatek-moore-check-if-pin_desc-is-valid-be.patch +++ /dev/null @@ -1,93 +0,0 @@ -From d8b94c9ff96c2024a527086d850eb0b314337ff9 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 14 Sep 2021 16:51:32 +0800 -Subject: [PATCH] pinctrl: mediatek: moore: check if pin_desc is valid before - use - -Certain SoC are missing the middle part gpios in consecutive pins, -it's better to check if mtk_pin_desc is a valid pin for the extensibility - -Signed-off-by: Sam Shih -Acked-by: Sean Wang -Link: https://lore.kernel.org/r/20210914085137.31761-5-sam.shih@mediatek.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-moore.c -+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c -@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pin - int pin = grp->pins[i]; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, - pin_modes[i]); -@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enabl - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, - hw->soc->gpio_m); -@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - /* hardware would take 0 as input direction */ - return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); -@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctr - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctr - int cfg, err = 0; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -+ if (!desc->name) -+ return -ENOTSUPP; - - for (cfg = 0; cfg < num_configs; cfg++) { - param = pinconf_to_config_param(configs[cfg]); -@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip - int value, err; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; -+ if (!desc->name) -+ return -ENOTSUPP; - - err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); - if (err) -@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chi - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; -+ if (!desc->name) { -+ dev_err(hw->dev, "Failed to set gpio %d\n", gpio); -+ return; -+ } - - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); - } -@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gp - u32 debounce; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; -+ if (!desc->name) -+ return -ENOTSUPP; - - if (!hw->eint || - pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || diff --git a/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch b/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch deleted file mode 100644 index d30e09ef9..000000000 --- a/target/linux/mediatek/patches-5.15/822-v5.16-pinctrl-mediatek-support-rsel-feature.patch +++ /dev/null @@ -1,457 +0,0 @@ -From fb34a9ae383ae26326d4889fd2513e49f1019b88 Mon Sep 17 00:00:00 2001 -From: Zhiyong Tao -Date: Fri, 24 Sep 2021 16:06:31 +0800 -Subject: [PATCH] pinctrl: mediatek: support rsel feature - -This patch supports rsel(resistance selection) feature for I2C pins. -It provides more resistance selection solution in different ICs. -It provides rsel define and si unit solution by identifying -"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node. - -Signed-off-by: Zhiyong Tao -Reviewed-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com -Signed-off-by: Linus Walleij ---- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 231 +++++++++++++++--- - .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 46 ++++ - drivers/pinctrl/mediatek/pinctrl-paris.c | 60 +++-- - 3 files changed, 289 insertions(+), 48 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -665,6 +665,181 @@ out: - return err; - } - -+static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg, u32 *rsel_val) -+{ -+ const struct mtk_pin_rsel *rsel; -+ int check; -+ bool found = false; -+ -+ rsel = hw->soc->pin_rsel; -+ -+ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { -+ if (desc->number >= rsel[check].s_pin && -+ desc->number <= rsel[check].e_pin) { -+ if (pullup) { -+ if (rsel[check].up_rsel == arg) { -+ found = true; -+ *rsel_val = rsel[check].rsel_index; -+ break; -+ } -+ } else { -+ if (rsel[check].down_rsel == arg) { -+ found = true; -+ *rsel_val = rsel[check].rsel_index; -+ break; -+ } -+ } -+ } -+ } -+ -+ if (!found) { -+ dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n", -+ arg, desc->number, desc->name); -+ return -ENOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err, rsel_val; -+ -+ if (hw->rsel_si_unit) { -+ /* find pin rsel_index from pin_rsel array*/ -+ err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val); -+ if (err) -+ goto out; -+ } else { -+ if (arg < MTK_PULL_SET_RSEL_000 || -+ arg > MTK_PULL_SET_RSEL_111) { -+ err = -EINVAL; -+ goto out; -+ } -+ -+ rsel_val = arg - MTK_PULL_SET_RSEL_000; -+ } -+ -+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val); -+ if (err) -+ goto out; -+ -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE); -+ -+out: -+ return err; -+} -+ -+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err = -ENOTSUPP; -+ u32 try_all_type; -+ -+ if (hw->soc->pull_type) -+ try_all_type = hw->soc->pull_type[desc->number]; -+ else -+ try_all_type = MTK_PULL_TYPE_MASK; -+ -+ if (try_all_type & MTK_PULL_RSEL_TYPE) { -+ err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PU_PD_TYPE) { -+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PULLSEL_TYPE) { -+ err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, -+ pullup, arg); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) -+ err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); -+ -+ if (err) -+ dev_err(hw->dev, "Invalid pull argument\n"); -+ -+ return err; -+} -+EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); -+ -+static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 rsel_val, u32 *si_unit) -+{ -+ const struct mtk_pin_rsel *rsel; -+ int check; -+ -+ rsel = hw->soc->pin_rsel; -+ -+ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) { -+ if (desc->number >= rsel[check].s_pin && -+ desc->number <= rsel[check].e_pin) { -+ if (rsel_val == rsel[check].rsel_index) { -+ if (pullup) -+ *si_unit = rsel[check].up_rsel; -+ else -+ *si_unit = rsel[check].down_rsel; -+ break; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 *pullup, u32 *enable) -+{ -+ int pu, pd, rsel, err; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel); -+ if (err) -+ goto out; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); -+ if (err) -+ goto out; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ -+ if (pu == 0 && pd == 0) { -+ *pullup = 0; -+ *enable = MTK_DISABLE; -+ } else if (pu == 1 && pd == 0) { -+ *pullup = 1; -+ if (hw->rsel_si_unit) -+ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); -+ else -+ *enable = rsel + MTK_PULL_SET_RSEL_000; -+ } else if (pu == 0 && pd == 1) { -+ *pullup = 0; -+ if (hw->rsel_si_unit) -+ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable); -+ else -+ *enable = rsel + MTK_PULL_SET_RSEL_000; -+ } else { -+ err = -EINVAL; -+ goto out; -+ } -+ -+out: -+ return err; -+} -+ - static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) -@@ -746,44 +921,40 @@ out: - return err; - } - --int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, -- const struct mtk_pin_desc *desc, -- u32 pullup, u32 arg) --{ -- int err; -- -- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); -- if (!err) -- goto out; -- -- err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg); -- if (!err) -- goto out; -- -- err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); -- --out: -- return err; --} --EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); -- - int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) - { -- int err; -+ int err = -ENOTSUPP; -+ u32 try_all_type; - -- err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); -- if (!err) -- goto out; -+ if (hw->soc->pull_type) -+ try_all_type = hw->soc->pull_type[desc->number]; -+ else -+ try_all_type = MTK_PULL_TYPE_MASK; - -- err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable); -- if (!err) -- goto out; -+ if (try_all_type & MTK_PULL_RSEL_TYPE) { -+ err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PU_PD_TYPE) { -+ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } -+ -+ if (try_all_type & MTK_PULL_PULLSEL_TYPE) { -+ err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, -+ pullup, enable); -+ if (!err) -+ return err; -+ } - -- err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); -+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE) -+ err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); - --out: - return err; - } - EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -@@ -17,6 +17,22 @@ - #define MTK_ENABLE 1 - #define MTK_PULLDOWN 0 - #define MTK_PULLUP 1 -+#define MTK_PULL_PU_PD_TYPE BIT(0) -+#define MTK_PULL_PULLSEL_TYPE BIT(1) -+#define MTK_PULL_PUPD_R1R0_TYPE BIT(2) -+/* MTK_PULL_RSEL_TYPE can select resistance and can be -+ * turned on/off itself. But it can't be selected pull up/down -+ */ -+#define MTK_PULL_RSEL_TYPE BIT(3) -+/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by -+ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. -+ */ -+#define MTK_PULL_PU_PD_RSEL_TYPE (MTK_PULL_PU_PD_TYPE \ -+ | MTK_PULL_RSEL_TYPE) -+#define MTK_PULL_TYPE_MASK (MTK_PULL_PU_PD_TYPE |\ -+ MTK_PULL_PULLSEL_TYPE |\ -+ MTK_PULL_PUPD_R1R0_TYPE |\ -+ MTK_PULL_RSEL_TYPE) - - #define EINT_NA U16_MAX - #define NO_EINT_SUPPORT EINT_NA -@@ -42,6 +58,14 @@ - PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -+#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) { \ -+ .s_pin = _s_pin, \ -+ .e_pin = _e_pin, \ -+ .rsel_index = _rsel_index, \ -+ .up_rsel = _up_resl, \ -+ .down_rsel = _down_rsel, \ -+ } -+ - /* List these attributes which could be modified for the pin */ - enum { - PINCTRL_PIN_REG_MODE, -@@ -67,6 +91,7 @@ enum { - PINCTRL_PIN_REG_DRV_E0, - PINCTRL_PIN_REG_DRV_E1, - PINCTRL_PIN_REG_DRV_ADV, -+ PINCTRL_PIN_REG_RSEL, - PINCTRL_PIN_REG_MAX, - }; - -@@ -129,6 +154,22 @@ struct mtk_pin_field_calc { - u8 fixed; - }; - -+/** -+ * struct mtk_pin_rsel - the structure that provides bias resistance selection. -+ * @s_pin: the start pin within the rsel range -+ * @e_pin: the end pin within the rsel range -+ * @rsel_index: the rsel bias resistance index -+ * @up_rsel: the pullup rsel bias resistance value -+ * @down_rsel: the pulldown rsel bias resistance value -+ */ -+struct mtk_pin_rsel { -+ u16 s_pin; -+ u16 e_pin; -+ u16 rsel_index; -+ u32 up_rsel; -+ u32 down_rsel; -+}; -+ - /* struct mtk_pin_reg_calc - the structure that holds all ranges used to - * determine which register the pin would make use of - * for certain pin attribute. -@@ -206,6 +247,9 @@ struct mtk_pin_soc { - bool ies_present; - const char * const *base_names; - unsigned int nbase_names; -+ const unsigned int *pull_type; -+ const struct mtk_pin_rsel *pin_rsel; -+ unsigned int npin_rsel; - - /* Specific pinconfig operations */ - int (*bias_disable_set)(struct mtk_pinctrl *hw, -@@ -254,6 +298,8 @@ struct mtk_pinctrl { - const char **grp_names; - /* lock pin's register resource to avoid multiple threads issue*/ - spinlock_t lock; -+ /* identify rsel setting by si unit or rsel define in dts node */ -+ bool rsel_si_unit; - }; - - void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); ---- a/drivers/pinctrl/mediatek/pinctrl-paris.c -+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c -@@ -538,8 +538,9 @@ static int mtk_hw_get_value_wrap(struct - ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, - unsigned int gpio, char *buf, unsigned int buf_len) - { -- int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1; -+ int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1; - const struct mtk_pin_desc *desc; -+ u32 try_all_type; - - if (gpio >= hw->soc->npins) - return -EINVAL; -@@ -553,24 +554,39 @@ ssize_t mtk_pctrl_show_one_pin(struct mt - pinmux -= hw->soc->nfuncs; - - mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen); -- if (pullen == MTK_PUPD_SET_R1R0_00) { -- pullen = 0; -- r1 = 0; -- r0 = 0; -- } else if (pullen == MTK_PUPD_SET_R1R0_01) { -- pullen = 1; -- r1 = 0; -- r0 = 1; -- } else if (pullen == MTK_PUPD_SET_R1R0_10) { -- pullen = 1; -- r1 = 1; -- r0 = 0; -- } else if (pullen == MTK_PUPD_SET_R1R0_11) { -+ -+ if (hw->soc->pull_type) -+ try_all_type = hw->soc->pull_type[desc->number]; -+ -+ if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) { -+ rsel = pullen; - pullen = 1; -- r1 = 1; -- r0 = 1; -- } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) { -- pullen = 0; -+ } else { -+ /* Case for: R1R0 */ -+ if (pullen == MTK_PUPD_SET_R1R0_00) { -+ pullen = 0; -+ r1 = 0; -+ r0 = 0; -+ } else if (pullen == MTK_PUPD_SET_R1R0_01) { -+ pullen = 1; -+ r1 = 0; -+ r0 = 1; -+ } else if (pullen == MTK_PUPD_SET_R1R0_10) { -+ pullen = 1; -+ r1 = 1; -+ r0 = 0; -+ } else if (pullen == MTK_PUPD_SET_R1R0_11) { -+ pullen = 1; -+ r1 = 1; -+ r0 = 1; -+ } -+ -+ /* Case for: RSEL */ -+ if (pullen >= MTK_PULL_SET_RSEL_000 && -+ pullen <= MTK_PULL_SET_RSEL_111) { -+ rsel = pullen - MTK_PULL_SET_RSEL_000; -+ pullen = 1; -+ } - } - len += scnprintf(buf + len, buf_len - len, - "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d", -@@ -588,6 +604,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mt - if (r1 != -1) { - len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", - r1, r0); -+ } else if (rsel != -1) { -+ len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); - } else { - len += scnprintf(buf + len, buf_len - len, "\n"); - } -@@ -930,6 +948,12 @@ int mtk_paris_pinctrl_probe(struct platf - - hw->nbase = hw->soc->nbase_names; - -+ if (of_find_property(hw->dev->of_node, -+ "mediatek,rsel_resistance_in_si_unit", NULL)) -+ hw->rsel_si_unit = true; -+ else -+ hw->rsel_si_unit = false; -+ - spin_lock_init(&hw->lock); - - err = mtk_pctrl_build_state(pdev); diff --git a/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch b/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch deleted file mode 100644 index 6752b4093..000000000 --- a/target/linux/mediatek/patches-5.15/823-v5.17-pinctrl-mediatek-add-a-check-for-error-in-mtk_pincon.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Sat, 27 Nov 2021 17:08:36 +0300 -Subject: [PATCH] pinctrl: mediatek: add a check for error in - mtk_pinconf_bias_get_rsel() - -All the other mtk_hw_get_value() calls have a check for "if (err)" so -we can add one here as well. This silences a Smatch warning: - - drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel() - error: uninitialized symbol 'pd'. - -Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -Signed-off-by: Dan Carpenter -Link: https://lore.kernel.org/r/20211127140836.GB24002@kili -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(str - goto out; - - err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ if (err) -+ goto out; - - if (pu == 0 && pd == 0) { - *pullup = 0; diff --git a/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch b/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch deleted file mode 100644 index 47a29fbdb..000000000 --- a/target/linux/mediatek/patches-5.15/824-v6.1-pinctrl-mediatek-Fix-EINT-pins-input-debounce-time-c.patch +++ /dev/null @@ -1,297 +0,0 @@ -From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 11 Nov 2022 10:41:06 +0100 -Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time - configuration - -The External Interrupt Controller (EINTC) on all of the supported -MediaTek SoCs does support input debouncing, but not all of them -index the debounce time values (DBNC_SETTING registers) the same way. - -Before this change, in some cases, as an example, requesting a debounce -time of 16 milliseconds would mistakenly set the relative DBNC_SETTING -register to 0x2, resulting in a way shorter debounce time of 500uS. - -To fix the aforementioned issue, define three different debounce_time -arrays, reflecting the correct register index for each value and for -each register index variant, and make sure that each SoC pinctrl -driver uses the right one. - -Signed-off-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/mtk-eint.c | 31 +++++++++++++++++++---- - drivers/pinctrl/mediatek/mtk-eint.h | 6 +++++ - drivers/pinctrl/mediatek/pinctrl-mt2701.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt2712.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt6765.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt6779.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7629.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8127.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8135.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8167.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8192.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 + - drivers/pinctrl/mediatek/pinctrl-mt8516.c | 1 + - 22 files changed, 53 insertions(+), 5 deletions(-) - ---- a/drivers/pinctrl/mediatek/mtk-eint.c -+++ b/drivers/pinctrl/mediatek/mtk-eint.c -@@ -24,6 +24,7 @@ - #define MTK_EINT_EDGE_SENSITIVE 0 - #define MTK_EINT_LEVEL_SENSITIVE 1 - #define MTK_EINT_DBNC_SET_DBNC_BITS 4 -+#define MTK_EINT_DBNC_MAX 16 - #define MTK_EINT_DBNC_RST_BIT (0x1 << 1) - #define MTK_EINT_DBNC_SET_EN (0x1 << 0) - -@@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge - .dbnc_clr = 0x700, - }; - -+const unsigned int debounce_time_mt2701[] = { -+ 500, 1000, 16000, 32000, 64000, 128000, 256000, 0 -+}; -+ -+const unsigned int debounce_time_mt6765[] = { -+ 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 -+}; -+ -+const unsigned int debounce_time_mt6795[] = { -+ 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 -+}; -+ - static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, - unsigned int eint_num, - unsigned int offset) -@@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein - int virq, eint_offset; - unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, - dbnc; -- static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, -- 64000, 128000, 256000}; - struct irq_data *d; - -+ if (!eint->hw->db_time) -+ return -EOPNOTSUPP; -+ - virq = irq_find_mapping(eint->domain, eint_num); - eint_offset = (eint_num % 4) * 8; - d = irq_get_irq_data(virq); -@@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein - if (!mtk_eint_can_en_debounce(eint, eint_num)) - return -EINVAL; - -- dbnc = ARRAY_SIZE(debounce_time); -- for (i = 0; i < ARRAY_SIZE(debounce_time); i++) { -- if (debounce <= debounce_time[i]) { -+ dbnc = eint->num_db_time; -+ for (i = 0; i < eint->num_db_time; i++) { -+ if (debounce <= eint->hw->db_time[i]) { - dbnc = i; - break; - } -@@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei - if (!eint->domain) - return -ENOMEM; - -+ if (eint->hw->db_time) { -+ for (i = 0; i < MTK_EINT_DBNC_MAX; i++) -+ if (eint->hw->db_time[i] == 0) -+ break; -+ eint->num_db_time = i; -+ } -+ - mtk_eint_hw_init(eint); - for (i = 0; i < eint->hw->ap_num; i++) { - int virq = irq_create_mapping(eint->domain, i); ---- a/drivers/pinctrl/mediatek/mtk-eint.h -+++ b/drivers/pinctrl/mediatek/mtk-eint.h -@@ -37,8 +37,13 @@ struct mtk_eint_hw { - u8 ports; - unsigned int ap_num; - unsigned int db_cnt; -+ const unsigned int *db_time; - }; - -+extern const unsigned int debounce_time_mt2701[]; -+extern const unsigned int debounce_time_mt6765[]; -+extern const unsigned int debounce_time_mt6795[]; -+ - struct mtk_eint; - - struct mtk_eint_xt { -@@ -62,6 +67,7 @@ struct mtk_eint { - /* Used to fit into various EINT device */ - const struct mtk_eint_hw *hw; - const struct mtk_eint_regs *regs; -+ u16 num_db_time; - - /* Used to fit into various pinctrl device */ - void *pctl; ---- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c -@@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 169, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c -@@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata - .ports = 8, - .ap_num = 229, - .db_cnt = 40, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c -@@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e - .ports = 6, - .ap_num = 160, - .db_cnt = 13, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt6765_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c -@@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e - .ports = 6, - .ap_num = 195, - .db_cnt = 13, -+ .db_time = debounce_time_mt2701, - }; - - static const struct mtk_pin_soc mt6779_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c -@@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e - .ports = 7, - .ap_num = ARRAY_SIZE(mt7622_pins), - .db_cnt = 20, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt7622_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c -@@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e - .ports = 6, - .ap_num = 169, - .db_cnt = 20, -+ .db_time = debounce_time_mt2701, - }; - - static struct mtk_pin_soc mt7623_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c -@@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e - .ports = 7, - .ap_num = ARRAY_SIZE(mt7629_pins), - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }; - - static struct mtk_pin_soc mt7629_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c -@@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 143, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c -@@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 192, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c -@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 169, - .db_cnt = 64, -+ .db_time = debounce_time_mt6795, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c -@@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 224, - .db_cnt = 16, -+ .db_time = debounce_time_mt2701, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c -@@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e - .ports = 6, - .ap_num = 212, - .db_cnt = 13, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt8183_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c -@@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e - .ports = 7, - .ap_num = 224, - .db_cnt = 32, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c -@@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e - .ports = 7, - .ap_num = 225, - .db_cnt = 32, -+ .db_time = debounce_time_mt6765, - }; - - static const struct mtk_pin_soc mt8195_data = { ---- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c -@@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata - .ports = 5, - .ap_num = 160, - .db_cnt = 160, -+ .db_time = debounce_time_mt6765, - }, - }; - ---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c -@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata - .ports = 6, - .ap_num = 169, - .db_cnt = 64, -+ .db_time = debounce_time_mt6795, - }, - }; - diff --git a/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch b/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch deleted file mode 100644 index 92f4e842e..000000000 --- a/target/linux/mediatek/patches-5.15/825-v6.1-pinctrl-mediatek-Export-debounce-time-tables.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 2e35b25dd8e666b8619355fc3defb1b246a5dc02 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Tue, 15 Nov 2022 09:11:07 +0100 -Subject: [PATCH] pinctrl: mediatek: Export debounce time tables - -The kernel test robot complains that in certain combinations -when building the Mediatek drivers as modules we lack some -debounce table symbols, so export them. - -Reported-by: kernel test robot -Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration") -Cc: AngeloGioacchino Del Regno -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/mtk-eint.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/pinctrl/mediatek/mtk-eint.c -+++ b/drivers/pinctrl/mediatek/mtk-eint.c -@@ -52,14 +52,17 @@ static const struct mtk_eint_regs mtk_ge - const unsigned int debounce_time_mt2701[] = { - 500, 1000, 16000, 32000, 64000, 128000, 256000, 0 - }; -+EXPORT_SYMBOL_GPL(debounce_time_mt2701); - - const unsigned int debounce_time_mt6765[] = { - 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 - }; -+EXPORT_SYMBOL_GPL(debounce_time_mt6765); - - const unsigned int debounce_time_mt6795[] = { - 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0 - }; -+EXPORT_SYMBOL_GPL(debounce_time_mt6795); - - static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, - unsigned int eint_num, diff --git a/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch deleted file mode 100644 index f130fdbc5..000000000 --- a/target/linux/mediatek/patches-5.15/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch +++ /dev/null @@ -1,129 +0,0 @@ -From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:12 +0100 -Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias - functions - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo -and mtk_pinconf_bias_get_combo, and make the functions able to support -almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. - -This patch enables pinctrl_moore to support these functions. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++---- - 1 file changed, 42 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-moore.c -+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c -@@ -8,6 +8,7 @@ - * - */ - -+#include - #include - #include "pinctrl-moore.h" - -@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr - { - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); - u32 param = pinconf_to_config_param(*config); -- int val, val2, err, reg, ret = 1; -+ int val, val2, err, pullup, reg, ret = 1; - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) -+ return -EINVAL; -+ } else if (hw->soc->bias_disable_get) { - err = hw->soc->bias_disable_get(hw, desc, &ret); - if (err) - return err; -@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (!pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 1, &ret); - if (err) - return err; -@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 0, &ret); - if (err) - return err; -@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_disable_set) { - err = hw->soc->bias_disable_set(hw, desc); - if (err) - return err; -@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 1, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 1); - if (err) - return err; -@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 0); - if (err) - return err; diff --git a/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch b/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch deleted file mode 100644 index 30891d348..000000000 --- a/target/linux/mediatek/patches-5.15/830-v5.18-regulator-Add-bindings-for-Richtek-RT5190A-PMIC.patch +++ /dev/null @@ -1,180 +0,0 @@ -From b77e70f6b8f2cc62fba847f3008a430a09ef275d Mon Sep 17 00:00:00 2001 -From: ChiYuan Huang -Date: Wed, 9 Mar 2022 16:01:42 +0800 -Subject: [PATCH 1/2] regulator: Add bindings for Richtek RT5190A PMIC - -Add bindings for Richtek RT5190A PMIC. - -Signed-off-by: ChiYuan Huang -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/1646812903-32496-2-git-send-email-u0084500@gmail.com -Signed-off-by: Mark Brown ---- - .../regulator/richtek,rt5190a-regulator.yaml | 141 ++++++++++++++++++ - .../regulator/richtek,rt5190a-regulator.h | 15 ++ - 2 files changed, 156 insertions(+) - create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml - create mode 100644 include/dt-bindings/regulator/richtek,rt5190a-regulator.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml -@@ -0,0 +1,141 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/regulator/richtek,rt5190a-regulator.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Richtek RT5190A PMIC Regulator -+ -+maintainers: -+ - ChiYuan Huang -+ -+description: | -+ The RT5190A integrates 1 channel buck controller, 3 channels high efficiency -+ synchronous buck converters, 1 LDO, I2C control interface and peripherial -+ logical control. -+ -+ It also supports mute AC OFF depop sound and quick setting storage while -+ input power is removed. -+ -+properties: -+ compatible: -+ enum: -+ - richtek,rt5190a -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ vin2-supply: -+ description: phandle to buck2 input voltage. -+ -+ vin3-supply: -+ description: phandle to buck3 input voltage. -+ -+ vin4-supply: -+ description: phandle to buck4 input voltage. -+ -+ vinldo-supply: -+ description: phandle to ldo input voltage -+ -+ richtek,mute-enable: -+ description: | -+ The mute function uses 'mutein', 'muteout', and 'vdet' pins as the control -+ signal. When enabled, The normal behavior is to bypass the 'mutein' signal -+ 'muteout'. But if the power source removal is detected from 'vdet', -+ whatever the 'mutein' signal is, it will pull down the 'muteout' to force -+ speakers mute. this function is commonly used to prevent the speaker pop -+ noise during AC power turned off in the modern TV system design. -+ type: boolean -+ -+ regulators: -+ type: object -+ -+ patternProperties: -+ "^buck[1-4]$|^ldo$": -+ type: object -+ $ref: regulator.yaml# -+ description: | -+ regulator description for buck1 and buck4. -+ -+ properties: -+ regulator-allowed-modes: -+ description: | -+ buck operating mode, only buck1/4 support mode operating. -+ 0: auto mode -+ 1: force pwm mode -+ items: -+ enum: [0, 1] -+ -+ richtek,latchup-enable: -+ type: boolean -+ description: | -+ If specified, undervolt protection mode changes from the default -+ hiccup to latchup. -+ -+ unevaluatedProperties: false -+ -+ additionalProperties: false -+ -+required: -+ - compatible -+ - reg -+ - regulators -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ i2c { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pmic@64 { -+ compatible = "richtek,rt5190a"; -+ reg = <0x64>; -+ interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>; -+ vin2-supply = <&rt5190_buck1>; -+ vin3-supply = <&rt5190_buck1>; -+ vin4-supply = <&rt5190_buck1>; -+ -+ regulators { -+ rt5190_buck1: buck1 { -+ regulator-name = "rt5190a-buck1"; -+ regulator-min-microvolt = <5090000>; -+ regulator-max-microvolt = <5090000>; -+ regulator-allowed-modes = ; -+ regulator-boot-on; -+ }; -+ buck2 { -+ regulator-name = "rt5190a-buck2"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck3 { -+ regulator-name = "rt5190a-buck3"; -+ regulator-min-microvolt = <600000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-boot-on; -+ }; -+ buck4 { -+ regulator-name = "rt5190a-buck4"; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-allowed-modes = ; -+ regulator-boot-on; -+ }; -+ ldo { -+ regulator-name = "rt5190a-ldo"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+ }; ---- /dev/null -+++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ -+#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__ -+ -+/* -+ * BUCK/LDO mode constants which may be used in devicetree properties -+ * (eg. regulator-allowed-modes). -+ * See the manufacturer's datasheet for more information on these modes. -+ */ -+ -+#define RT5190A_OPMODE_AUTO 0 -+#define RT5190A_OPMODE_FPWM 1 -+ -+#endif diff --git a/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch b/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch deleted file mode 100644 index 0e0f099e5..000000000 --- a/target/linux/mediatek/patches-5.15/831-v5.18-regulator-rt5190a-Add-support-for-Richtek-RT5190A-PM.patch +++ /dev/null @@ -1,562 +0,0 @@ -From 760423dfad53877b468490758fe7ea968ded9402 Mon Sep 17 00:00:00 2001 -From: ChiYuan Huang -Date: Wed, 9 Mar 2022 16:01:43 +0800 -Subject: [PATCH 2/2] regulator: rt5190a: Add support for Richtek RT5190A PMIC - -Add support for Richtek RT5190A PMIC. - -Signed-off-by: ChiYuan Huang -Link: https://lore.kernel.org/r/1646812903-32496-3-git-send-email-u0084500@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/Kconfig | 10 + - drivers/regulator/Makefile | 1 + - drivers/regulator/rt5190a-regulator.c | 513 ++++++++++++++++++++++++++ - 3 files changed, 524 insertions(+) - create mode 100644 drivers/regulator/rt5190a-regulator.c - ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1037,6 +1037,16 @@ config REGULATOR_RT5033 - RT5033 PMIC. The device supports multiple regulators like - current source, LDO and Buck. - -+config REGULATOR_RT5190A -+ tristate "Richtek RT5190A PMIC" -+ depends on I2C -+ select REGMAP_I2C -+ help -+ This adds support for voltage regulator in Richtek RT5190A PMIC. -+ It integratas 1 channel buck controller, 3 channels high efficiency -+ buck converters, 1 LDO, mute AC OFF depop function, with the general -+ I2C control interface. -+ - config REGULATOR_RT6160 - tristate "Richtek RT6160 BuckBoost voltage regulator" - depends on I2C ---- a/drivers/regulator/Makefile -+++ b/drivers/regulator/Makefile -@@ -125,6 +125,7 @@ obj-$(CONFIG_REGULATOR_ROHM) += rohm-reg - obj-$(CONFIG_REGULATOR_RT4801) += rt4801-regulator.o - obj-$(CONFIG_REGULATOR_RT4831) += rt4831-regulator.o - obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o -+obj-$(CONFIG_REGULATOR_RT5190A) += rt5190a-regulator.o - obj-$(CONFIG_REGULATOR_RT6160) += rt6160-regulator.o - obj-$(CONFIG_REGULATOR_RT6245) += rt6245-regulator.o - obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o ---- /dev/null -+++ b/drivers/regulator/rt5190a-regulator.c -@@ -0,0 +1,513 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define RT5190A_REG_MANUFACTURE 0x00 -+#define RT5190A_REG_BUCK2VSEL 0x04 -+#define RT5190A_REG_BUCK3VSEL 0x05 -+#define RT5190A_REG_DCDCCNTL 0x06 -+#define RT5190A_REG_ENABLE 0x07 -+#define RT5190A_REG_DISCHARGE 0x09 -+#define RT5190A_REG_PROTMODE 0x0A -+#define RT5190A_REG_MUTECNTL 0x0B -+#define RT5190A_REG_PGSTAT 0x0F -+#define RT5190A_REG_OVINT 0x10 -+#define RT5190A_REG_HOTDIEMASK 0x17 -+ -+#define RT5190A_VSEL_MASK GENMASK(6, 0) -+#define RT5190A_RID_BITMASK(rid) BIT(rid + 1) -+#define RT5190A_BUCK1_DISCHG_MASK GENMASK(1, 0) -+#define RT5190A_BUCK1_DISCHG_ONVAL 0x01 -+#define RT5190A_OVERVOLT_MASK GENMASK(7, 0) -+#define RT5190A_UNDERVOLT_MASK GENMASK(15, 8) -+#define RT5190A_CH234OT_MASK BIT(29) -+#define RT5190A_CHIPOT_MASK BIT(28) -+ -+#define RT5190A_BUCK23_MINUV 600000 -+#define RT5190A_BUCK23_MAXUV 1400000 -+#define RT5190A_BUCK23_STEPUV 10000 -+#define RT5190A_BUCK23_STEPNUM ((1400000 - 600000) / 10000 + 1) -+ -+enum { -+ RT5190A_IDX_BUCK1 = 0, -+ RT5190A_IDX_BUCK2, -+ RT5190A_IDX_BUCK3, -+ RT5190A_IDX_BUCK4, -+ RT5190A_IDX_LDO, -+ RT5190A_MAX_IDX -+}; -+ -+struct rt5190a_priv { -+ struct device *dev; -+ struct regmap *regmap; -+ struct regulator_desc rdesc[RT5190A_MAX_IDX]; -+ struct regulator_dev *rdev[RT5190A_MAX_IDX]; -+}; -+ -+static int rt5190a_get_error_flags(struct regulator_dev *rdev, -+ unsigned int *flags) -+{ -+ struct regmap *regmap = rdev_get_regmap(rdev); -+ int rid = rdev_get_id(rdev); -+ unsigned int pgood_stat; -+ int ret; -+ -+ ret = regmap_read(regmap, RT5190A_REG_PGSTAT, &pgood_stat); -+ if (ret) -+ return ret; -+ -+ if (!(pgood_stat & RT5190A_RID_BITMASK(rid))) -+ *flags = REGULATOR_ERROR_FAIL; -+ else -+ *flags = 0; -+ -+ return 0; -+} -+ -+static int rt5190a_fixed_buck_set_mode(struct regulator_dev *rdev, -+ unsigned int mode) -+{ -+ struct regmap *regmap = rdev_get_regmap(rdev); -+ int rid = rdev_get_id(rdev); -+ unsigned int mask = RT5190A_RID_BITMASK(rid), val; -+ -+ switch (mode) { -+ case REGULATOR_MODE_FAST: -+ val = mask; -+ break; -+ case REGULATOR_MODE_NORMAL: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return regmap_update_bits(regmap, RT5190A_REG_DCDCCNTL, mask, val); -+} -+ -+static unsigned int rt5190a_fixed_buck_get_mode(struct regulator_dev *rdev) -+{ -+ struct regmap *regmap = rdev_get_regmap(rdev); -+ int rid = rdev_get_id(rdev); -+ unsigned int val; -+ int ret; -+ -+ ret = regmap_read(regmap, RT5190A_REG_DCDCCNTL, &val); -+ if (ret) { -+ dev_err(&rdev->dev, "Failed to get mode [%d]\n", ret); -+ return ret; -+ } -+ -+ if (val & RT5190A_RID_BITMASK(rid)) -+ return REGULATOR_MODE_FAST; -+ -+ return REGULATOR_MODE_NORMAL; -+} -+ -+static const struct regulator_ops rt5190a_ranged_buck_ops = { -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ .set_voltage_sel = regulator_set_voltage_sel_regmap, -+ .get_voltage_sel = regulator_get_voltage_sel_regmap, -+ .list_voltage = regulator_list_voltage_linear, -+ .set_active_discharge = regulator_set_active_discharge_regmap, -+ .get_error_flags = rt5190a_get_error_flags, -+}; -+ -+static const struct regulator_ops rt5190a_fixed_buck_ops = { -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ .set_active_discharge = regulator_set_active_discharge_regmap, -+ .set_mode = rt5190a_fixed_buck_set_mode, -+ .get_mode = rt5190a_fixed_buck_get_mode, -+ .get_error_flags = rt5190a_get_error_flags, -+}; -+ -+static const struct regulator_ops rt5190a_fixed_ldo_ops = { -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ .set_active_discharge = regulator_set_active_discharge_regmap, -+ .get_error_flags = rt5190a_get_error_flags, -+}; -+ -+static irqreturn_t rt5190a_irq_handler(int irq, void *data) -+{ -+ struct rt5190a_priv *priv = data; -+ __le32 raws; -+ unsigned int events, fields; -+ static const struct { -+ unsigned int bitmask; -+ unsigned int report; -+ } event_tbl[] = { -+ { RT5190A_OVERVOLT_MASK, REGULATOR_ERROR_REGULATION_OUT }, -+ { RT5190A_UNDERVOLT_MASK, REGULATOR_ERROR_UNDER_VOLTAGE } -+ }; -+ int i, j, ret; -+ -+ ret = regmap_raw_read(priv->regmap, RT5190A_REG_OVINT, &raws, -+ sizeof(raws)); -+ if (ret) { -+ dev_err(priv->dev, "Failed to read events\n"); -+ return IRQ_NONE; -+ } -+ -+ events = le32_to_cpu(raws); -+ -+ ret = regmap_raw_write(priv->regmap, RT5190A_REG_OVINT, &raws, -+ sizeof(raws)); -+ if (ret) -+ dev_err(priv->dev, "Failed to write-clear events\n"); -+ -+ /* Handle OV,UV events */ -+ for (i = 0; i < ARRAY_SIZE(event_tbl); i++) { -+ fields = events & event_tbl[i].bitmask; -+ fields >>= ffs(event_tbl[i].bitmask) - 1; -+ -+ for (j = 0; j < RT5190A_MAX_IDX; j++) { -+ if (!(fields & RT5190A_RID_BITMASK(j))) -+ continue; -+ -+ regulator_notifier_call_chain(priv->rdev[j], -+ event_tbl[i].report, -+ NULL); -+ } -+ } -+ -+ /* Handle CH234 OT event */ -+ if (events & RT5190A_CH234OT_MASK) { -+ for (j = RT5190A_IDX_BUCK2; j < RT5190A_IDX_LDO; j++) { -+ regulator_notifier_call_chain(priv->rdev[j], -+ REGULATOR_ERROR_OVER_TEMP, -+ NULL); -+ } -+ } -+ -+ /* Warning if CHIP OT occur */ -+ if (events & RT5190A_CHIPOT_MASK) -+ dev_warn(priv->dev, "CHIP overheat\n"); -+ -+ return IRQ_HANDLED; -+} -+ -+static unsigned int rt5190a_of_map_mode(unsigned int mode) -+{ -+ switch (mode) { -+ case RT5190A_OPMODE_AUTO: -+ return REGULATOR_MODE_NORMAL; -+ case RT5190A_OPMODE_FPWM: -+ return REGULATOR_MODE_FAST; -+ default: -+ return REGULATOR_MODE_INVALID; -+ } -+} -+ -+static int rt5190a_of_parse_cb(struct rt5190a_priv *priv, int rid, -+ struct of_regulator_match *match) -+{ -+ struct regulator_desc *desc = priv->rdesc + rid; -+ struct regulator_init_data *init_data = match->init_data; -+ struct device_node *np = match->of_node; -+ bool latchup_enable; -+ unsigned int mask = RT5190A_RID_BITMASK(rid), val; -+ -+ switch (rid) { -+ case RT5190A_IDX_BUCK1: -+ case RT5190A_IDX_BUCK4: -+ case RT5190A_IDX_LDO: -+ init_data->constraints.apply_uV = 0; -+ -+ if (init_data->constraints.min_uV == -+ init_data->constraints.max_uV) -+ desc->fixed_uV = init_data->constraints.min_uV; -+ else { -+ dev_err(priv->dev, -+ "Variable voltage for fixed regulator\n"); -+ return -EINVAL; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ latchup_enable = of_property_read_bool(np, "richtek,latchup-enable"); -+ -+ /* latchup: 0, default hiccup: 1 */ -+ val = !latchup_enable ? mask : 0; -+ -+ return regmap_update_bits(priv->regmap, RT5190A_REG_PROTMODE, mask, val); -+} -+ -+static void rt5190a_fillin_regulator_desc(struct regulator_desc *desc, int rid) -+{ -+ static const char * const regu_name[] = { "buck1", "buck2", -+ "buck3", "buck4", -+ "ldo" }; -+ static const char * const supply[] = { NULL, "vin2", "vin3", "vin4", -+ "vinldo" }; -+ -+ desc->name = regu_name[rid]; -+ desc->supply_name = supply[rid]; -+ desc->owner = THIS_MODULE; -+ desc->type = REGULATOR_VOLTAGE; -+ desc->id = rid; -+ desc->enable_reg = RT5190A_REG_ENABLE; -+ desc->enable_mask = RT5190A_RID_BITMASK(rid); -+ desc->active_discharge_reg = RT5190A_REG_DISCHARGE; -+ desc->active_discharge_mask = RT5190A_RID_BITMASK(rid); -+ desc->active_discharge_on = RT5190A_RID_BITMASK(rid); -+ -+ switch (rid) { -+ case RT5190A_IDX_BUCK1: -+ desc->active_discharge_mask = RT5190A_BUCK1_DISCHG_MASK; -+ desc->active_discharge_on = RT5190A_BUCK1_DISCHG_ONVAL; -+ desc->n_voltages = 1; -+ desc->ops = &rt5190a_fixed_buck_ops; -+ desc->of_map_mode = rt5190a_of_map_mode; -+ break; -+ case RT5190A_IDX_BUCK2: -+ desc->vsel_reg = RT5190A_REG_BUCK2VSEL; -+ desc->vsel_mask = RT5190A_VSEL_MASK; -+ desc->min_uV = RT5190A_BUCK23_MINUV; -+ desc->uV_step = RT5190A_BUCK23_STEPUV; -+ desc->n_voltages = RT5190A_BUCK23_STEPNUM; -+ desc->ops = &rt5190a_ranged_buck_ops; -+ break; -+ case RT5190A_IDX_BUCK3: -+ desc->vsel_reg = RT5190A_REG_BUCK3VSEL; -+ desc->vsel_mask = RT5190A_VSEL_MASK; -+ desc->min_uV = RT5190A_BUCK23_MINUV; -+ desc->uV_step = RT5190A_BUCK23_STEPUV; -+ desc->n_voltages = RT5190A_BUCK23_STEPNUM; -+ desc->ops = &rt5190a_ranged_buck_ops; -+ break; -+ case RT5190A_IDX_BUCK4: -+ desc->n_voltages = 1; -+ desc->ops = &rt5190a_fixed_buck_ops; -+ desc->of_map_mode = rt5190a_of_map_mode; -+ break; -+ case RT5190A_IDX_LDO: -+ desc->n_voltages = 1; -+ desc->ops = &rt5190a_fixed_ldo_ops; -+ break; -+ } -+} -+ -+static struct of_regulator_match rt5190a_regulator_match[] = { -+ { .name = "buck1", }, -+ { .name = "buck2", }, -+ { .name = "buck3", }, -+ { .name = "buck4", }, -+ { .name = "ldo", } -+}; -+ -+static int rt5190a_parse_regulator_dt_data(struct rt5190a_priv *priv) -+{ -+ struct device_node *regulator_np; -+ struct regulator_desc *reg_desc; -+ struct of_regulator_match *match; -+ int i, ret; -+ -+ for (i = 0; i < RT5190A_MAX_IDX; i++) { -+ reg_desc = priv->rdesc + i; -+ match = rt5190a_regulator_match + i; -+ -+ rt5190a_fillin_regulator_desc(reg_desc, i); -+ -+ match->desc = reg_desc; -+ } -+ -+ regulator_np = of_get_child_by_name(priv->dev->of_node, "regulators"); -+ if (!regulator_np) { -+ dev_err(priv->dev, "Could not find 'regulators' node\n"); -+ return -ENODEV; -+ } -+ -+ ret = of_regulator_match(priv->dev, regulator_np, -+ rt5190a_regulator_match, -+ ARRAY_SIZE(rt5190a_regulator_match)); -+ -+ of_node_put(regulator_np); -+ -+ if (ret < 0) { -+ dev_err(priv->dev, -+ "Error parsing regulator init data: %d\n", ret); -+ return ret; -+ } -+ -+ for (i = 0; i < RT5190A_MAX_IDX; i++) { -+ match = rt5190a_regulator_match + i; -+ -+ ret = rt5190a_of_parse_cb(priv, i, match); -+ if (ret) { -+ dev_err(priv->dev, "Failed in [%d] of_parse_cb\n", i); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct reg_sequence rt5190a_init_patch[] = { -+ { 0x09, 0x3d, }, -+ { 0x0a, 0x3e, }, -+ { 0x0b, 0x01, }, -+ { 0x10, 0xff, }, -+ { 0x11, 0xff, }, -+ { 0x12, 0xff, }, -+ { 0x13, 0xff, }, -+ { 0x14, 0, }, -+ { 0x15, 0, }, -+ { 0x16, 0x3e, }, -+ { 0x17, 0, } -+}; -+ -+static int rt5190a_device_initialize(struct rt5190a_priv *priv) -+{ -+ bool mute_enable; -+ int ret; -+ -+ ret = regmap_register_patch(priv->regmap, rt5190a_init_patch, -+ ARRAY_SIZE(rt5190a_init_patch)); -+ if (ret) { -+ dev_err(priv->dev, "Failed to do register patch\n"); -+ return ret; -+ } -+ -+ mute_enable = device_property_read_bool(priv->dev, -+ "richtek,mute-enable"); -+ -+ if (mute_enable) { -+ ret = regmap_write(priv->regmap, RT5190A_REG_MUTECNTL, 0x00); -+ if (ret) { -+ dev_err(priv->dev, "Failed to enable mute function\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static int rt5190a_device_check(struct rt5190a_priv *priv) -+{ -+ u16 devid; -+ int ret; -+ -+ ret = regmap_raw_read(priv->regmap, RT5190A_REG_MANUFACTURE, &devid, -+ sizeof(devid)); -+ if (ret) -+ return ret; -+ -+ if (devid) { -+ dev_err(priv->dev, "Incorrect device id 0x%04x\n", devid); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static const struct regmap_config rt5190a_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = RT5190A_REG_HOTDIEMASK, -+}; -+ -+static int rt5190a_probe(struct i2c_client *i2c) -+{ -+ struct rt5190a_priv *priv; -+ struct regulator_config cfg = {}; -+ int i, ret; -+ -+ priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->dev = &i2c->dev; -+ -+ priv->regmap = devm_regmap_init_i2c(i2c, &rt5190a_regmap_config); -+ if (IS_ERR(priv->regmap)) { -+ dev_err(&i2c->dev, "Failed to allocate regmap\n"); -+ return PTR_ERR(priv->regmap); -+ } -+ -+ ret = rt5190a_device_check(priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to check device %d\n", ret); -+ return ret; -+ } -+ -+ ret = rt5190a_device_initialize(priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to initialize the device\n"); -+ return ret; -+ } -+ -+ ret = rt5190a_parse_regulator_dt_data(priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to parse regulator dt\n"); -+ return ret; -+ } -+ -+ cfg.dev = &i2c->dev; -+ cfg.regmap = priv->regmap; -+ -+ for (i = 0; i < RT5190A_MAX_IDX; i++) { -+ struct regulator_desc *desc = priv->rdesc + i; -+ struct of_regulator_match *match = rt5190a_regulator_match + i; -+ -+ cfg.init_data = match->init_data; -+ cfg.of_node = match->of_node; -+ -+ priv->rdev[i] = devm_regulator_register(&i2c->dev, desc, &cfg); -+ if (IS_ERR(priv->rdev[i])) { -+ dev_err(&i2c->dev, "Failed to register regulator %s\n", -+ desc->name); -+ return PTR_ERR(priv->rdev[i]); -+ } -+ } -+ -+ if (i2c->irq) { -+ ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, -+ rt5190a_irq_handler, -+ IRQF_ONESHOT, -+ dev_name(&i2c->dev), priv); -+ if (ret) { -+ dev_err(&i2c->dev, "Failed to register interrupt\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id __maybe_unused rt5190a_device_table[] = { -+ { .compatible = "richtek,rt5190a", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, rt5190a_device_table); -+ -+static struct i2c_driver rt5190a_driver = { -+ .driver = { -+ .name = "rt5190a", -+ .of_match_table = rt5190a_device_table, -+ }, -+ .probe_new = rt5190a_probe, -+}; -+module_i2c_driver(rt5190a_driver); -+ -+MODULE_AUTHOR("ChiYuan Huang "); -+MODULE_DESCRIPTION("Richtek RT5190A Regulator Driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch b/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch deleted file mode 100644 index 8b0119640..000000000 --- a/target/linux/mediatek/patches-5.15/840-v5.16-i2c-mediatek-Reset-the-handshake-signal-between-i2c-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Sun, 10 Oct 2021 15:05:12 +0800 -Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c - and dma - -Due to changes in the hardware design of the handshaking signal -between i2c and dma, it is necessary to reset the handshaking -signal before each transfer to ensure that the multi-msgs can -be transferred correctly. - -Signed-off-by: Kewei Xu -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -49,6 +50,8 @@ - #define I2C_RD_TRANAC_VALUE 0x0001 - #define I2C_SCL_MIS_COMP_VALUE 0x0000 - #define I2C_CHN_CLR_FLAG 0x0000 -+#define I2C_RELIABILITY 0x0010 -+#define I2C_DMAACK_ENABLE 0x0008 - - #define I2C_DMA_CON_TX 0x0000 - #define I2C_DMA_CON_RX 0x0001 -@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt - u16 restart_flag = 0; - u16 dma_sync = 0; - u32 reg_4g_mode; -+ u32 reg_dma_reset; - u8 *dma_rd_buf = NULL; - u8 *dma_wr_buf = NULL; - dma_addr_t rpaddr = 0; -@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt - - reinit_completion(&i2c->msg_complete); - -+ if (i2c->dev_comp->apdma_sync && -+ i2c->op != I2C_MASTER_WRRD && num > 1) { -+ mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); -+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, -+ i2c->pdmabase + OFFSET_RST); -+ -+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, -+ reg_dma_reset, -+ !(reg_dma_reset & I2C_DMA_WARM_RST), -+ 0, 100); -+ if (ret) { -+ dev_err(i2c->dev, "DMA warm reset timeout\n"); -+ return -ETIMEDOUT; -+ } -+ -+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); -+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); -+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); -+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, -+ OFFSET_DEBUGCTRL); -+ } -+ - control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & - ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); - if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) diff --git a/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch b/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch deleted file mode 100644 index a2d2521c7..000000000 --- a/target/linux/mediatek/patches-5.15/841-v5.16-i2c-mediatek-Dump-i2c-dma-register-when-a-timeout-oc.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Sun, 10 Oct 2021 15:05:13 +0800 -Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout - occurs - -When a timeout error occurs in i2c transter, it is usually related -to the i2c/dma IP hardware configuration. Therefore, the purpose of -this patch is to dump the key register values of i2c/dma when a -timeout occurs in i2c for debugging. - -Signed-off-by: Kewei Xu -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET { - OFFSET_HS, - OFFSET_SOFTRESET, - OFFSET_DCM_EN, -+ OFFSET_MULTI_DMA, - OFFSET_PATH_DIR, - OFFSET_DEBUGSTAT, - OFFSET_DEBUGCTRL, -@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = { - [OFFSET_TRANSFER_LEN_AUX] = 0x44, - [OFFSET_CLOCK_DIV] = 0x48, - [OFFSET_SOFTRESET] = 0x50, -+ [OFFSET_MULTI_DMA] = 0x8c, - [OFFSET_SCL_MIS_COMP_POINT] = 0x90, - [OFFSET_DEBUGSTAT] = 0xe4, - [OFFSET_DEBUGCTRL] = 0xe8, -@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_ - return 0; - } - -+static void i2c_dump_register(struct mtk_i2c *i2c) -+{ -+ dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), -+ mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); -+ dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_INTR_STAT), -+ mtk_i2c_readw(i2c, OFFSET_CONTROL)); -+ dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), -+ mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); -+ dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), -+ mtk_i2c_readw(i2c, OFFSET_TIMING)); -+ dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_START), -+ mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); -+ dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_HS), -+ mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); -+ dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_DCM_EN), -+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); -+ dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), -+ mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); -+ dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), -+ mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); -+ if (i2c->dev_comp->regs == mt_i2c_regs_v2) { -+ dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", -+ mtk_i2c_readw(i2c, OFFSET_LTIMING), -+ mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); -+ } -+ dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_INT_FLAG), -+ readl(i2c->pdmabase + OFFSET_INT_EN)); -+ dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_EN), -+ readl(i2c->pdmabase + OFFSET_CON)); -+ dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), -+ readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); -+ dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", -+ readl(i2c->pdmabase + OFFSET_TX_LEN), -+ readl(i2c->pdmabase + OFFSET_RX_LEN)); -+ dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", -+ readl(i2c->pdmabase + OFFSET_TX_4G_MODE), -+ readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); -+} -+ - static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, - int num, int left_num) - { -@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt - - if (ret == 0) { - dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); -+ i2c_dump_register(i2c); - mtk_i2c_init_hw(i2c); - return -ETIMEDOUT; - } diff --git a/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch b/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch deleted file mode 100644 index 184fe94ff..000000000 --- a/target/linux/mediatek/patches-5.15/842-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8186.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 83630e3c6147bf7bb18a18f3d5a99462464f450b Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Tue, 25 Jan 2022 19:04:13 +0800 -Subject: [PATCH 03/16] i2c: mediatek: Add i2c compatible for Mediatek MT8186 - -Add i2c compatible for MT8186. Compare to MT8192 i2c controller, -MT8186 doesn't need handshake signal witch apdma. - -Signed-off-by: Kewei Xu -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -397,6 +397,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt8186_compat = { -+ .regs = mt_i2c_regs_v2, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 0, -+ .ltiming_adjust = 1, -+ .apdma_sync = 0, -+ .max_dma_support = 36, -+}; -+ - static const struct mtk_i2c_compatible mt8192_compat = { - .quirks = &mt8183_i2c_quirks, - .regs = mt_i2c_regs_v2, -@@ -418,6 +431,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, -+ { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, - { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, - {} - }; diff --git a/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch b/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch deleted file mode 100644 index 0ace4a670..000000000 --- a/target/linux/mediatek/patches-5.15/843-v5.18-i2c-mediatek-modify-bus-speed-calculation-formula.patch +++ /dev/null @@ -1,132 +0,0 @@ -From f606aab3f1a49d723d66e14e545f6ca45005bda6 Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Thu, 17 Feb 2022 20:22:43 +0800 -Subject: [PATCH 04/16] i2c: mediatek: modify bus speed calculation formula - -When clock-div is 0 or greater than 1, the bus speed -calculated by the old speed calculation formula will be -larger than the target speed. So we update the formula. - -Signed-off-by: Kewei Xu -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 51 ++++++++++++++++++++++++++------- - 1 file changed, 41 insertions(+), 10 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -67,11 +67,12 @@ - - #define MAX_SAMPLE_CNT_DIV 8 - #define MAX_STEP_CNT_DIV 64 --#define MAX_CLOCK_DIV 256 -+#define MAX_CLOCK_DIV_8BITS 256 -+#define MAX_CLOCK_DIV_5BITS 32 - #define MAX_HS_STEP_CNT_DIV 8 --#define I2C_STANDARD_MODE_BUFFER (1000 / 2) --#define I2C_FAST_MODE_BUFFER (300 / 2) --#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) -+#define I2C_STANDARD_MODE_BUFFER (1000 / 3) -+#define I2C_FAST_MODE_BUFFER (300 / 3) -+#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) - - #define I2C_CONTROL_RS (0x1 << 1) - #define I2C_CONTROL_DMA_EN (0x1 << 2) -@@ -604,6 +605,31 @@ static int mtk_i2c_max_step_cnt(unsigned - return MAX_STEP_CNT_DIV; - } - -+static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, -+ unsigned int sample_cnt) -+{ -+ int clk_div_restri = 0; -+ -+ if (i2c->dev_comp->ltiming_adjust == 0) -+ return 0; -+ -+ if (sample_cnt == 1) { -+ if (i2c->ac_timing.inter_clk_div == 0) -+ clk_div_restri = 0; -+ else -+ clk_div_restri = 1; -+ } else { -+ if (i2c->ac_timing.inter_clk_div == 0) -+ clk_div_restri = -1; -+ else if (i2c->ac_timing.inter_clk_div == 1) -+ clk_div_restri = 0; -+ else -+ clk_div_restri = 1; -+ } -+ -+ return clk_div_restri; -+} -+ - /* - * Check and Calculate i2c ac-timing - * -@@ -732,6 +758,7 @@ static int mtk_i2c_calculate_speed(struc - unsigned int best_mul; - unsigned int cnt_mul; - int ret = -EINVAL; -+ int clk_div_restri = 0; - - if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) - target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; -@@ -749,7 +776,8 @@ static int mtk_i2c_calculate_speed(struc - * optimizing for sample_cnt * step_cnt being minimal - */ - for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { -- step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); -+ clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); -+ step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); - cnt_mul = step_cnt * sample_cnt; - if (step_cnt > max_step_cnt) - continue; -@@ -763,7 +791,7 @@ static int mtk_i2c_calculate_speed(struc - best_mul = cnt_mul; - base_sample_cnt = sample_cnt; - base_step_cnt = step_cnt; -- if (best_mul == opt_div) -+ if (best_mul == (opt_div + clk_div_restri)) - break; - } - } -@@ -774,7 +802,8 @@ static int mtk_i2c_calculate_speed(struc - sample_cnt = base_sample_cnt; - step_cnt = base_step_cnt; - -- if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { -+ if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > -+ target_speed) { - /* In this case, hardware can't support such - * low i2c_bus_freq - */ -@@ -803,13 +832,16 @@ static int mtk_i2c_set_speed(struct mtk_ - target_speed = i2c->speed_hz; - parent_clk /= i2c->clk_src_div; - -- if (i2c->dev_comp->timing_adjust) -- max_clk_div = MAX_CLOCK_DIV; -+ if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) -+ max_clk_div = MAX_CLOCK_DIV_5BITS; -+ else if (i2c->dev_comp->timing_adjust) -+ max_clk_div = MAX_CLOCK_DIV_8BITS; - else - max_clk_div = 1; - - for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { - clk_src = parent_clk / clk_div; -+ i2c->ac_timing.inter_clk_div = clk_div - 1; - - if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { - /* Set master code speed register */ -@@ -856,7 +888,6 @@ static int mtk_i2c_set_speed(struct mtk_ - break; - } - -- i2c->ac_timing.inter_clk_div = clk_div - 1; - - return 0; - } diff --git a/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch b/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch deleted file mode 100644 index 8f3c965a8..000000000 --- a/target/linux/mediatek/patches-5.15/844-v5.18-i2c-mediatek-remove-redundant-null-check.patch +++ /dev/null @@ -1,41 +0,0 @@ -From eb4a2ae019815946f574cd9f8209e12bdcd8fd34 Mon Sep 17 00:00:00 2001 -From: Xu Wang -Date: Wed, 30 Sep 2020 08:42:33 +0000 -Subject: [PATCH 05/16] i2c: mediatek: remove redundant null check - -Because clk_disable_unprepare already checked NULL clock parameter, -so the additional checks are unnecessary, just remove it - -Signed-off-by: Xu Wang -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 9 +++------ - 1 file changed, 3 insertions(+), 6 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -476,8 +476,7 @@ static int mtk_i2c_clock_enable(struct m - return 0; - - err_arb: -- if (i2c->have_pmic) -- clk_disable_unprepare(i2c->clk_pmic); -+ clk_disable_unprepare(i2c->clk_pmic); - err_pmic: - clk_disable_unprepare(i2c->clk_main); - err_main: -@@ -488,11 +487,9 @@ err_main: - - static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) - { -- if (i2c->clk_arb) -- clk_disable_unprepare(i2c->clk_arb); -+ clk_disable_unprepare(i2c->clk_arb); - -- if (i2c->have_pmic) -- clk_disable_unprepare(i2c->clk_pmic); -+ clk_disable_unprepare(i2c->clk_pmic); - - clk_disable_unprepare(i2c->clk_main); - clk_disable_unprepare(i2c->clk_dma); diff --git a/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch b/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch deleted file mode 100644 index 71d083f31..000000000 --- a/target/linux/mediatek/patches-5.15/845-v5.18-i2c-mt65xx-Simplify-with-clk-bulk.patch +++ /dev/null @@ -1,234 +0,0 @@ -From cc6faa5e0772296d815fd298c231277d47308a6a Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Thu, 3 Mar 2022 10:15:47 +0100 -Subject: [PATCH 06/16] i2c: mt65xx: Simplify with clk-bulk - -Since depending on the SoC or specific bus functionality some clocks -may be optional, we cannot get the benefit of using devm_clk_bulk_get() -but, by migrating to clk-bulk, we are able to remove the custom functions -mtk_i2c_clock_enable() and mtk_i2c_clock_disable(), increasing common -APIs usage, hence (lightly) decreasing kernel footprint. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 124 +++++++++++++------------------- - 1 file changed, 51 insertions(+), 73 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -86,6 +86,27 @@ - - #define I2C_DRV_NAME "i2c-mt65xx" - -+/** -+ * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C -+ * -+ * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus -+ * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA -+ * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC -+ * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c -+ * @I2C_MT65XX_CLK_MAX: Number of supported clocks -+ */ -+enum i2c_mt65xx_clks { -+ I2C_MT65XX_CLK_MAIN = 0, -+ I2C_MT65XX_CLK_DMA, -+ I2C_MT65XX_CLK_PMIC, -+ I2C_MT65XX_CLK_ARB, -+ I2C_MT65XX_CLK_MAX -+}; -+ -+static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { -+ "main", "dma", "pmic", "arb" -+}; -+ - enum DMA_REGS_OFFSET { - OFFSET_INT_FLAG = 0x0, - OFFSET_INT_EN = 0x04, -@@ -244,10 +265,7 @@ struct mtk_i2c { - /* set in i2c probe */ - void __iomem *base; /* i2c base addr */ - void __iomem *pdmabase; /* dma base address*/ -- struct clk *clk_main; /* main clock for i2c bus */ -- struct clk *clk_dma; /* DMA clock for i2c via DMA */ -- struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ -- struct clk *clk_arb; /* Arbitrator clock for i2c */ -+ struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ - bool have_pmic; /* can use i2c pins from PMIC */ - bool use_push_pull; /* IO config push-pull mode */ - -@@ -449,52 +467,6 @@ static void mtk_i2c_writew(struct mtk_i2 - writew(val, i2c->base + i2c->dev_comp->regs[reg]); - } - --static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) --{ -- int ret; -- -- ret = clk_prepare_enable(i2c->clk_dma); -- if (ret) -- return ret; -- -- ret = clk_prepare_enable(i2c->clk_main); -- if (ret) -- goto err_main; -- -- if (i2c->have_pmic) { -- ret = clk_prepare_enable(i2c->clk_pmic); -- if (ret) -- goto err_pmic; -- } -- -- if (i2c->clk_arb) { -- ret = clk_prepare_enable(i2c->clk_arb); -- if (ret) -- goto err_arb; -- } -- -- return 0; -- --err_arb: -- clk_disable_unprepare(i2c->clk_pmic); --err_pmic: -- clk_disable_unprepare(i2c->clk_main); --err_main: -- clk_disable_unprepare(i2c->clk_dma); -- -- return ret; --} -- --static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) --{ -- clk_disable_unprepare(i2c->clk_arb); -- -- clk_disable_unprepare(i2c->clk_pmic); -- -- clk_disable_unprepare(i2c->clk_main); -- clk_disable_unprepare(i2c->clk_dma); --} -- - static void mtk_i2c_init_hw(struct mtk_i2c *i2c) - { - u16 control_reg; -@@ -1191,7 +1163,7 @@ static int mtk_i2c_transfer(struct i2c_a - int left_num = num; - struct mtk_i2c *i2c = i2c_get_adapdata(adap); - -- ret = mtk_i2c_clock_enable(i2c); -+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) - return ret; - -@@ -1245,7 +1217,7 @@ static int mtk_i2c_transfer(struct i2c_a - ret = num; - - err_exit: -- mtk_i2c_clock_disable(i2c); -+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - return ret; - } - -@@ -1323,9 +1295,8 @@ static int mtk_i2c_probe(struct platform - { - int ret = 0; - struct mtk_i2c *i2c; -- struct clk *clk; - struct resource *res; -- int irq; -+ int i, irq, speed_clk; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) -@@ -1371,35 +1342,42 @@ static int mtk_i2c_probe(struct platform - if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) - return -EINVAL; - -- i2c->clk_main = devm_clk_get(&pdev->dev, "main"); -- if (IS_ERR(i2c->clk_main)) { -+ /* Fill in clk-bulk IDs */ -+ for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) -+ i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; -+ -+ /* Get clocks one by one, some may be optional */ -+ i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { - dev_err(&pdev->dev, "cannot get main clock\n"); -- return PTR_ERR(i2c->clk_main); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); - } - -- i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); -- if (IS_ERR(i2c->clk_dma)) { -+ i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { - dev_err(&pdev->dev, "cannot get dma clock\n"); -- return PTR_ERR(i2c->clk_dma); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); - } - -- i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); -- if (IS_ERR(i2c->clk_arb)) -- i2c->clk_arb = NULL; -+ i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); - -- clk = i2c->clk_main; - if (i2c->have_pmic) { -- i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); -- if (IS_ERR(i2c->clk_pmic)) { -+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { - dev_err(&pdev->dev, "cannot get pmic clock\n"); -- return PTR_ERR(i2c->clk_pmic); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); - } -- clk = i2c->clk_pmic; -+ speed_clk = I2C_MT65XX_CLK_PMIC; -+ } else { -+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; -+ speed_clk = I2C_MT65XX_CLK_MAIN; - } - - strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); - -- ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); -+ ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); - if (ret) { - dev_err(&pdev->dev, "Failed to set the speed.\n"); - return -EINVAL; -@@ -1414,13 +1392,13 @@ static int mtk_i2c_probe(struct platform - } - } - -- ret = mtk_i2c_clock_enable(i2c); -+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) { - dev_err(&pdev->dev, "clock enable failed!\n"); - return ret; - } - mtk_i2c_init_hw(i2c); -- mtk_i2c_clock_disable(i2c); -+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - - ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, - IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, -@@ -1465,7 +1443,7 @@ static int mtk_i2c_resume_noirq(struct d - int ret; - struct mtk_i2c *i2c = dev_get_drvdata(dev); - -- ret = mtk_i2c_clock_enable(i2c); -+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) { - dev_err(dev, "clock enable failed!\n"); - return ret; -@@ -1473,7 +1451,7 @@ static int mtk_i2c_resume_noirq(struct d - - mtk_i2c_init_hw(i2c); - -- mtk_i2c_clock_disable(i2c); -+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - - i2c_mark_adapter_resumed(&i2c->adap); - diff --git a/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch b/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch deleted file mode 100644 index fe5be94fc..000000000 --- a/target/linux/mediatek/patches-5.15/846-v5.18-i2c-mediatek-Add-i2c-compatible-for-Mediatek-MT8168.patch +++ /dev/null @@ -1,46 +0,0 @@ -From de054c03f90b3ea22bc346fbf78ac716df192b2d Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Mon, 7 Mar 2022 11:36:49 +0800 -Subject: [PATCH 07/16] i2c: mediatek: Add i2c compatible for Mediatek MT8168 - -Add i2c compatible for MT8168. Compare to MT2712 i2c controller, -MT8168 need to synchronize signal with dma. - -Signed-off-by: Kewei Xu -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -389,6 +389,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 32, - }; - -+static const struct mtk_i2c_compatible mt8168_compat = { -+ .regs = mt_i2c_regs_v1, -+ .pmic_i2c = 0, -+ .dcm = 1, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 1, -+ .ltiming_adjust = 0, -+ .apdma_sync = 0, -+ .max_dma_support = 33, -+}; -+ - static const struct mtk_i2c_compatible mt8173_compat = { - .regs = mt_i2c_regs_v1, - .pmic_i2c = 0, -@@ -448,6 +461,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, - { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, diff --git a/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch b/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch deleted file mode 100644 index 5c4ce4076..000000000 --- a/target/linux/mediatek/patches-5.15/847-v5.19-i2c-mediatek-Optimize-master_xfer-and-avoid-circular.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 2831f9a53ec3a16012d2d23590e3ebad6084b763 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Mon, 11 Apr 2022 15:21:07 +0200 -Subject: [PATCH 08/16] i2c: mediatek: Optimize master_xfer() and avoid - circular locking -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Especially (but not only) during probe, it may happen that multiple -devices are communicating via i2c (or multiple i2c busses) and -sometimes while others are probing asynchronously. -For example, a Cr50 TPM may be filling entropy (or userspace may be -reading random data) while the rt5682 (i2c) codec driver reads/sets -some registers, like while getting/setting a clock's rate, which -happens both during probe and during system operation. - -In this driver, the mtk_i2c_transfer() function (which is the i2c -.master_xfer() callback) was granularly managing the clocks by -performing a clk_bulk_prepare_enable() to start them and its inverse. -This is not only creating possible circular locking dependencies in -the some cases (like former explanation), but it's also suboptimal, -as clk_core prepare/unprepare operations are using mutex locking, -which creates a bit of unwanted overhead (for example, i2c trackpads -will call master_xfer() every few milliseconds!). - -With this commit, we avoid both the circular locking and additional -overhead by changing how we handle the clocks in this driver: -- Prepare the clocks during probe (and PM resume) -- Enable/disable clocks in mtk_i2c_transfer() -- Unprepare the clocks only for driver removal (and PM suspend) - -For the sake of providing a full explanation: during probe, the -clocks are not only prepared but also enabled, as this is needed -for some hardware initialization but, after that, we are disabling -but not unpreparing them, leaving an expected state for the -aforementioned clock handling strategy. - -Signed-off-by: AngeloGioacchino Del Regno -Tested-by: Nícolas F. R. A. Prado -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1177,7 +1177,7 @@ static int mtk_i2c_transfer(struct i2c_a - int left_num = num; - struct mtk_i2c *i2c = i2c_get_adapdata(adap); - -- ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); - if (ret) - return ret; - -@@ -1231,7 +1231,7 @@ static int mtk_i2c_transfer(struct i2c_a - ret = num; - - err_exit: -- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); - return ret; - } - -@@ -1412,7 +1412,7 @@ static int mtk_i2c_probe(struct platform - return ret; - } - mtk_i2c_init_hw(i2c); -- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); - - ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, - IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, -@@ -1439,6 +1439,8 @@ static int mtk_i2c_remove(struct platfor - - i2c_del_adapter(&i2c->adap); - -+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ - return 0; - } - -@@ -1448,6 +1450,7 @@ static int mtk_i2c_suspend_noirq(struct - struct mtk_i2c *i2c = dev_get_drvdata(dev); - - i2c_mark_adapter_suspended(&i2c->adap); -+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); - - return 0; - } -@@ -1465,7 +1468,7 @@ static int mtk_i2c_resume_noirq(struct d - - mtk_i2c_init_hw(i2c); - -- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); - - i2c_mark_adapter_resumed(&i2c->adap); - diff --git a/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch b/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch deleted file mode 100644 index 354f12e21..000000000 --- a/target/linux/mediatek/patches-5.15/848-v5.19-i2c-mediatek-Fix-an-error-handling-path-in-mtk_i2c_p.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 6f3a5814c7aaea4176e0ac8b1ec6dc0a65aa2808 Mon Sep 17 00:00:00 2001 -From: Christophe JAILLET -Date: Sun, 22 May 2022 14:22:07 +0200 -Subject: [PATCH 09/16] i2c: mediatek: Fix an error handling path in - mtk_i2c_probe() - -The clsk are prepared, enabled, then disabled. So if an error occurs after -the disable step, they are still prepared. - -Add an error handling path to unprepare the clks in such a case, as already -done in the .remove function. - -Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking") -Signed-off-by: Christophe JAILLET -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform - if (ret < 0) { - dev_err(&pdev->dev, - "Request I2C IRQ %d fail\n", irq); -- return ret; -+ goto err_bulk_unprepare; - } - - i2c_set_adapdata(&i2c->adap, i2c); - ret = i2c_add_adapter(&i2c->adap); - if (ret) -- return ret; -+ goto err_bulk_unprepare; - - platform_set_drvdata(pdev, i2c); - - return 0; -+ -+err_bulk_unprepare: -+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); -+ -+ return ret; - } - - static int mtk_i2c_remove(struct platform_device *pdev) diff --git a/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch b/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch deleted file mode 100644 index 744aa96ed..000000000 --- a/target/linux/mediatek/patches-5.15/849-v6.0-i2c-mediatek-add-i2c-compatible-for-MT8188.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001 -From: Kewei Xu -Date: Sat, 6 Aug 2022 18:02:49 +0800 -Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188 - -Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since -MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. - -Signed-off-by: Kewei Xu -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Qii Wang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { - [OFFSET_DCM_EN] = 0xf88, - }; - -+static const u16 mt_i2c_regs_v3[] = { -+ [OFFSET_DATA_PORT] = 0x0, -+ [OFFSET_INTR_MASK] = 0x8, -+ [OFFSET_INTR_STAT] = 0xc, -+ [OFFSET_CONTROL] = 0x10, -+ [OFFSET_TRANSFER_LEN] = 0x14, -+ [OFFSET_TRANSAC_LEN] = 0x18, -+ [OFFSET_DELAY_LEN] = 0x1c, -+ [OFFSET_TIMING] = 0x20, -+ [OFFSET_START] = 0x24, -+ [OFFSET_EXT_CONF] = 0x28, -+ [OFFSET_LTIMING] = 0x2c, -+ [OFFSET_HS] = 0x30, -+ [OFFSET_IO_CONFIG] = 0x34, -+ [OFFSET_FIFO_ADDR_CLR] = 0x38, -+ [OFFSET_SDA_TIMING] = 0x3c, -+ [OFFSET_TRANSFER_LEN_AUX] = 0x44, -+ [OFFSET_CLOCK_DIV] = 0x48, -+ [OFFSET_SOFTRESET] = 0x50, -+ [OFFSET_MULTI_DMA] = 0x8c, -+ [OFFSET_SCL_MIS_COMP_POINT] = 0x90, -+ [OFFSET_SLAVE_ADDR] = 0x94, -+ [OFFSET_DEBUGSTAT] = 0xe4, -+ [OFFSET_DEBUGCTRL] = 0xe8, -+ [OFFSET_FIFO_STAT] = 0xf4, -+ [OFFSET_FIFO_THRESH] = 0xf8, -+ [OFFSET_DCM_EN] = 0xf88, -+}; -+ - struct mtk_i2c_compatible { - const struct i2c_adapter_quirks *quirks; - const u16 *regs; -@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 36, - }; - -+static const struct mtk_i2c_compatible mt8188_compat = { -+ .regs = mt_i2c_regs_v3, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 0, -+ .ltiming_adjust = 1, -+ .apdma_sync = 1, -+ .max_dma_support = 36, -+}; -+ - static const struct mtk_i2c_compatible mt8192_compat = { - .quirks = &mt8183_i2c_quirks, - .regs = mt_i2c_regs_v2, -@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, - { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, -+ { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, - { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, - {} - }; diff --git a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch deleted file mode 100644 index 2741aa5bd..000000000 --- a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch +++ /dev/null @@ -1,579 +0,0 @@ -From 2f4ca256a98cc19787b7c861109dd1150a21b0bf Mon Sep 17 00:00:00 2001 -From: Wolfram Sang -Date: Thu, 11 Aug 2022 09:10:30 +0200 -Subject: [PATCH 11/16] i2c: move drivers from strlcpy to strscpy - -Follow the advice of the below link and prefer 'strscpy'. Conversion is -easy because no driver used the return value and has been done with a -simple sed invocation. - -Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ -Signed-off-by: Wolfram Sang -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-altera.c | 2 +- - drivers/i2c/busses/i2c-aspeed.c | 2 +- - drivers/i2c/busses/i2c-au1550.c | 2 +- - drivers/i2c/busses/i2c-axxia.c | 2 +- - drivers/i2c/busses/i2c-bcm-kona.c | 2 +- - drivers/i2c/busses/i2c-cbus-gpio.c | 2 +- - drivers/i2c/busses/i2c-cht-wc.c | 2 +- - drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +- - drivers/i2c/busses/i2c-davinci.c | 2 +- - drivers/i2c/busses/i2c-digicolor.c | 2 +- - drivers/i2c/busses/i2c-eg20t.c | 2 +- - drivers/i2c/busses/i2c-emev2.c | 2 +- - drivers/i2c/busses/i2c-exynos5.c | 2 +- - drivers/i2c/busses/i2c-gpio.c | 2 +- - drivers/i2c/busses/i2c-highlander.c | 2 +- - drivers/i2c/busses/i2c-hix5hd2.c | 2 +- - drivers/i2c/busses/i2c-i801.c | 4 ++-- - drivers/i2c/busses/i2c-ibm_iic.c | 2 +- - drivers/i2c/busses/i2c-icy.c | 2 +- - drivers/i2c/busses/i2c-imx-lpi2c.c | 2 +- - drivers/i2c/busses/i2c-lpc2k.c | 2 +- - drivers/i2c/busses/i2c-meson.c | 2 +- - drivers/i2c/busses/i2c-mt65xx.c | 2 +- - drivers/i2c/busses/i2c-mt7621.c | 2 +- - drivers/i2c/busses/i2c-mv64xxx.c | 2 +- - drivers/i2c/busses/i2c-mxs.c | 2 +- - drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- - drivers/i2c/busses/i2c-omap.c | 2 +- - drivers/i2c/busses/i2c-opal.c | 4 ++-- - drivers/i2c/busses/i2c-parport.c | 2 +- - drivers/i2c/busses/i2c-pxa.c | 2 +- - drivers/i2c/busses/i2c-qcom-geni.c | 2 +- - drivers/i2c/busses/i2c-qup.c | 2 +- - drivers/i2c/busses/i2c-rcar.c | 2 +- - drivers/i2c/busses/i2c-riic.c | 2 +- - drivers/i2c/busses/i2c-rk3x.c | 2 +- - drivers/i2c/busses/i2c-s3c2410.c | 2 +- - drivers/i2c/busses/i2c-sh_mobile.c | 2 +- - drivers/i2c/busses/i2c-simtec.c | 2 +- - drivers/i2c/busses/i2c-taos-evm.c | 2 +- - drivers/i2c/busses/i2c-tegra-bpmp.c | 2 +- - drivers/i2c/busses/i2c-tegra.c | 2 +- - drivers/i2c/busses/i2c-uniphier-f.c | 2 +- - drivers/i2c/busses/i2c-uniphier.c | 2 +- - drivers/i2c/busses/i2c-versatile.c | 2 +- - drivers/i2c/busses/i2c-wmt.c | 2 +- - 46 files changed, 48 insertions(+), 48 deletions(-) - ---- a/drivers/i2c/busses/i2c-altera.c -+++ b/drivers/i2c/busses/i2c-altera.c -@@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platfor - mutex_unlock(&idev->isr_mutex); - - i2c_set_adapdata(&idev->adapter, idev); -- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); -+ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); - idev->adapter.owner = THIS_MODULE; - idev->adapter.algo = &altr_i2c_algo; - idev->adapter.dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-aspeed.c -+++ b/drivers/i2c/busses/i2c-aspeed.c -@@ -1044,7 +1044,7 @@ static int aspeed_i2c_probe_bus(struct p - bus->adap.algo = &aspeed_i2c_algo; - bus->adap.dev.parent = &pdev->dev; - bus->adap.dev.of_node = pdev->dev.of_node; -- strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); -+ strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); - i2c_set_adapdata(&bus->adap, bus); - - bus->dev = &pdev->dev; ---- a/drivers/i2c/busses/i2c-au1550.c -+++ b/drivers/i2c/busses/i2c-au1550.c -@@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device - priv->adap.algo = &au1550_algo; - priv->adap.algo_data = priv; - priv->adap.dev.parent = &pdev->dev; -- strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); - - /* Now, set up the PSC for SMBus PIO mode. */ - i2c_au1550_setup(priv); ---- a/drivers/i2c/busses/i2c-axxia.c -+++ b/drivers/i2c/busses/i2c-axxia.c -@@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platfo - } - - i2c_set_adapdata(&idev->adapter, idev); -- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); -+ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); - idev->adapter.owner = THIS_MODULE; - idev->adapter.algo = &axxia_i2c_algo; - idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; ---- a/drivers/i2c/busses/i2c-bcm-kona.c -+++ b/drivers/i2c/busses/i2c-bcm-kona.c -@@ -849,7 +849,7 @@ static int bcm_kona_i2c_probe(struct pla - adap = &dev->adapter; - i2c_set_adapdata(adap, dev); - adap->owner = THIS_MODULE; -- strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); - adap->algo = &bcm_algo; - adap->dev.parent = &pdev->dev; - adap->dev.of_node = pdev->dev.of_node; ---- a/drivers/i2c/busses/i2c-cbus-gpio.c -+++ b/drivers/i2c/busses/i2c-cbus-gpio.c -@@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platfor - adapter->nr = pdev->id; - adapter->timeout = HZ; - adapter->algo = &cbus_i2c_algo; -- strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); -+ strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); - - spin_lock_init(&chost->lock); - chost->dev = &pdev->dev; ---- a/drivers/i2c/busses/i2c-cht-wc.c -+++ b/drivers/i2c/busses/i2c-cht-wc.c -@@ -334,7 +334,7 @@ static int cht_wc_i2c_adap_i2c_probe(str - adap->adapter.class = I2C_CLASS_HWMON; - adap->adapter.algo = &cht_wc_i2c_adap_algo; - adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops; -- strlcpy(adap->adapter.name, "PMIC I2C Adapter", -+ strscpy(adap->adapter.name, "PMIC I2C Adapter", - sizeof(adap->adapter.name)); - adap->adapter.dev.parent = &pdev->dev; - ---- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c -+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c -@@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_ - bus->dev = dev; - - bus->adap.owner = THIS_MODULE; -- strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); -+ strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name)); - bus->adap.algo = &ec_i2c_algorithm; - bus->adap.algo_data = bus; - bus->adap.dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-davinci.c -+++ b/drivers/i2c/busses/i2c-davinci.c -@@ -847,7 +847,7 @@ static int davinci_i2c_probe(struct plat - i2c_set_adapdata(adap, dev); - adap->owner = THIS_MODULE; - adap->class = I2C_CLASS_DEPRECATED; -- strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); - adap->algo = &i2c_davinci_algo; - adap->dev.parent = &pdev->dev; - adap->timeout = DAVINCI_I2C_TIMEOUT; ---- a/drivers/i2c/busses/i2c-digicolor.c -+++ b/drivers/i2c/busses/i2c-digicolor.c -@@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_ - if (ret < 0) - return ret; - -- strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter", -+ strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter", - sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &dc_i2c_algorithm; ---- a/drivers/i2c/busses/i2c-eg20t.c -+++ b/drivers/i2c/busses/i2c-eg20t.c -@@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev - - pch_adap->owner = THIS_MODULE; - pch_adap->class = I2C_CLASS_HWMON; -- strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); -+ strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); - pch_adap->algo = &pch_algorithm; - pch_adap->algo_data = &adap_info->pch_data[i]; - ---- a/drivers/i2c/busses/i2c-emev2.c -+++ b/drivers/i2c/busses/i2c-emev2.c -@@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_ - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -- strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name)); - - priv->sclk = devm_clk_get(&pdev->dev, "sclk"); - if (IS_ERR(priv->sclk)) ---- a/drivers/i2c/busses/i2c-exynos5.c -+++ b/drivers/i2c/busses/i2c-exynos5.c -@@ -751,7 +751,7 @@ static int exynos5_i2c_probe(struct plat - if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) - i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; - -- strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &exynos5_i2c_algorithm; - i2c->adap.retries = 3; ---- a/drivers/i2c/busses/i2c-gpio.c -+++ b/drivers/i2c/busses/i2c-gpio.c -@@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platfor - - adap->owner = THIS_MODULE; - if (np) -- strlcpy(adap->name, dev_name(dev), sizeof(adap->name)); -+ strscpy(adap->name, dev_name(dev), sizeof(adap->name)); - else - snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); - ---- a/drivers/i2c/busses/i2c-highlander.c -+++ b/drivers/i2c/busses/i2c-highlander.c -@@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct p - i2c_set_adapdata(adap, dev); - adap->owner = THIS_MODULE; - adap->class = I2C_CLASS_HWMON; -- strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name)); - adap->algo = &highlander_i2c_algo; - adap->dev.parent = &pdev->dev; - adap->nr = pdev->id; ---- a/drivers/i2c/busses/i2c-hix5hd2.c -+++ b/drivers/i2c/busses/i2c-hix5hd2.c -@@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct plat - } - clk_prepare_enable(priv->clk); - -- strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); - priv->dev = &pdev->dev; - priv->adap.owner = THIS_MODULE; - priv->adap.algo = &hix5hd2_i2c_algorithm; ---- a/drivers/i2c/busses/i2c-i801.c -+++ b/drivers/i2c/busses/i2c-i801.c -@@ -1103,7 +1103,7 @@ static void dmi_check_onboard_device(u8 - - memset(&info, 0, sizeof(struct i2c_board_info)); - info.addr = dmi_devices[i].i2c_addr; -- strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); -+ strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); - i2c_new_client_device(adap, &info); - break; - } -@@ -1259,7 +1259,7 @@ static void register_dell_lis3lv02d_i2c_ - - memset(&info, 0, sizeof(struct i2c_board_info)); - info.addr = dell_lis3lv02d_devices[i].i2c_addr; -- strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); -+ strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); - i2c_new_client_device(&priv->adapter, &info); - } - ---- a/drivers/i2c/busses/i2c-ibm_iic.c -+++ b/drivers/i2c/busses/i2c-ibm_iic.c -@@ -736,7 +736,7 @@ static int iic_probe(struct platform_dev - adap = &dev->adap; - adap->dev.parent = &ofdev->dev; - adap->dev.of_node = of_node_get(np); -- strlcpy(adap->name, "IBM IIC", sizeof(adap->name)); -+ strscpy(adap->name, "IBM IIC", sizeof(adap->name)); - i2c_set_adapdata(adap, dev); - adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; - adap->algo = &iic_algo; ---- a/drivers/i2c/busses/i2c-icy.c -+++ b/drivers/i2c/busses/i2c-icy.c -@@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z - i2c->adapter.owner = THIS_MODULE; - /* i2c->adapter.algo assigned by i2c_pcf_add_bus() */ - i2c->adapter.algo_data = algo_data; -- strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter", -+ strscpy(i2c->adapter.name, "ICY I2C Zorro adapter", - sizeof(i2c->adapter.name)); - - if (!devm_request_mem_region(&z->dev, ---- a/drivers/i2c/busses/i2c-imx-lpi2c.c -+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c -@@ -564,7 +564,7 @@ static int lpi2c_imx_probe(struct platfo - lpi2c_imx->adapter.algo = &lpi2c_imx_algo; - lpi2c_imx->adapter.dev.parent = &pdev->dev; - lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; -- strlcpy(lpi2c_imx->adapter.name, pdev->name, -+ strscpy(lpi2c_imx->adapter.name, pdev->name, - sizeof(lpi2c_imx->adapter.name)); - - lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); ---- a/drivers/i2c/busses/i2c-lpc2k.c -+++ b/drivers/i2c/busses/i2c-lpc2k.c -@@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platfo - - i2c_set_adapdata(&i2c->adap, i2c); - i2c->adap.owner = THIS_MODULE; -- strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); - i2c->adap.algo = &i2c_lpc2k_algorithm; - i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; ---- a/drivers/i2c/busses/i2c-meson.c -+++ b/drivers/i2c/busses/i2c-meson.c -@@ -451,7 +451,7 @@ static int meson_i2c_probe(struct platfo - return ret; - } - -- strlcpy(i2c->adap.name, "Meson I2C adapter", -+ strscpy(i2c->adap.name, "Meson I2C adapter", - sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &meson_i2c_algorithm; ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform - speed_clk = I2C_MT65XX_CLK_MAIN; - } - -- strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); - - ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); - if (ret) { ---- a/drivers/i2c/busses/i2c-mt7621.c -+++ b/drivers/i2c/busses/i2c-mt7621.c -@@ -315,7 +315,7 @@ static int mtk_i2c_probe(struct platform - adap->dev.parent = &pdev->dev; - i2c_set_adapdata(adap, i2c); - adap->dev.of_node = pdev->dev.of_node; -- strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); -+ strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); - - platform_set_drvdata(pdev, i2c); - ---- a/drivers/i2c/busses/i2c-mv64xxx.c -+++ b/drivers/i2c/busses/i2c-mv64xxx.c -@@ -1000,7 +1000,7 @@ mv64xxx_i2c_probe(struct platform_device - if (IS_ERR(drv_data->reg_base)) - return PTR_ERR(drv_data->reg_base); - -- strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", -+ strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", - sizeof(drv_data->adapter.name)); - - init_waitqueue_head(&drv_data->waitq); ---- a/drivers/i2c/busses/i2c-mxs.c -+++ b/drivers/i2c/busses/i2c-mxs.c -@@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform - return err; - - adap = &i2c->adapter; -- strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); - adap->owner = THIS_MODULE; - adap->algo = &mxs_i2c_algo; - adap->quirks = &mxs_i2c_quirks; ---- a/drivers/i2c/busses/i2c-nvidia-gpu.c -+++ b/drivers/i2c/busses/i2c-nvidia-gpu.c -@@ -319,7 +319,7 @@ static int gpu_i2c_probe(struct pci_dev - - i2c_set_adapdata(&i2cd->adapter, i2cd); - i2cd->adapter.owner = THIS_MODULE; -- strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", -+ strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", - sizeof(i2cd->adapter.name)); - i2cd->adapter.algo = &gpu_i2c_algorithm; - i2cd->adapter.quirks = &gpu_i2c_quirks; ---- a/drivers/i2c/busses/i2c-omap.c -+++ b/drivers/i2c/busses/i2c-omap.c -@@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *p - i2c_set_adapdata(adap, omap); - adap->owner = THIS_MODULE; - adap->class = I2C_CLASS_DEPRECATED; -- strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); - adap->algo = &omap_i2c_algo; - adap->quirks = &omap_i2c_quirks; - adap->dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-opal.c -+++ b/drivers/i2c/busses/i2c-opal.c -@@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platfor - adapter->dev.of_node = of_node_get(pdev->dev.of_node); - pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL); - if (pname) -- strlcpy(adapter->name, pname, sizeof(adapter->name)); -+ strscpy(adapter->name, pname, sizeof(adapter->name)); - else -- strlcpy(adapter->name, "opal", sizeof(adapter->name)); -+ strscpy(adapter->name, "opal", sizeof(adapter->name)); - - platform_set_drvdata(pdev, adapter); - rc = i2c_add_adapter(adapter); ---- a/drivers/i2c/busses/i2c-parport.c -+++ b/drivers/i2c/busses/i2c-parport.c -@@ -308,7 +308,7 @@ static void i2c_parport_attach(struct pa - /* Fill the rest of the structure */ - adapter->adapter.owner = THIS_MODULE; - adapter->adapter.class = I2C_CLASS_HWMON; -- strlcpy(adapter->adapter.name, "Parallel port adapter", -+ strscpy(adapter->adapter.name, "Parallel port adapter", - sizeof(adapter->adapter.name)); - adapter->algo_data = parport_algo_data; - /* Slow down if we can't sense SCL */ ---- a/drivers/i2c/busses/i2c-pxa.c -+++ b/drivers/i2c/busses/i2c-pxa.c -@@ -1463,7 +1463,7 @@ static int i2c_pxa_probe(struct platform - spin_lock_init(&i2c->lock); - init_waitqueue_head(&i2c->wait); - -- strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); - - i2c->clk = devm_clk_get(&dev->dev, NULL); - if (IS_ERR(i2c->clk)) { ---- a/drivers/i2c/busses/i2c-qcom-geni.c -+++ b/drivers/i2c/busses/i2c-qcom-geni.c -@@ -577,7 +577,7 @@ static int geni_i2c_probe(struct platfor - i2c_set_adapdata(&gi2c->adap, gi2c); - gi2c->adap.dev.parent = dev; - gi2c->adap.dev.of_node = dev->of_node; -- strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); -+ strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); - - ret = geni_icc_get(&gi2c->se, "qup-memory"); - if (ret) ---- a/drivers/i2c/busses/i2c-qup.c -+++ b/drivers/i2c/busses/i2c-qup.c -@@ -1885,7 +1885,7 @@ nodma: - qup->adap.dev.of_node = pdev->dev.of_node; - qup->is_last = true; - -- strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); -+ strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); - - pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); - pm_runtime_use_autosuspend(qup->dev); ---- a/drivers/i2c/busses/i2c-rcar.c -+++ b/drivers/i2c/busses/i2c-rcar.c -@@ -1059,7 +1059,7 @@ static int rcar_i2c_probe(struct platfor - adap->bus_recovery_info = &rcar_i2c_bri; - adap->quirks = &rcar_i2c_quirks; - i2c_set_adapdata(adap, priv); -- strlcpy(adap->name, pdev->name, sizeof(adap->name)); -+ strscpy(adap->name, pdev->name, sizeof(adap->name)); - - /* Init DMA */ - sg_init_table(&priv->sg, 1); ---- a/drivers/i2c/busses/i2c-riic.c -+++ b/drivers/i2c/busses/i2c-riic.c -@@ -447,7 +447,7 @@ static int riic_i2c_probe(struct platfor - - adap = &riic->adapter; - i2c_set_adapdata(adap, riic); -- strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); -+ strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); - adap->owner = THIS_MODULE; - adap->algo = &riic_algo; - adap->dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-rk3x.c -+++ b/drivers/i2c/busses/i2c-rk3x.c -@@ -1247,7 +1247,7 @@ static int rk3x_i2c_probe(struct platfor - /* use common interface to get I2C timing properties */ - i2c_parse_fw_timings(&pdev->dev, &i2c->t, true); - -- strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &rk3x_i2c_algorithm; - i2c->adap.retries = 3; ---- a/drivers/i2c/busses/i2c-s3c2410.c -+++ b/drivers/i2c/busses/i2c-s3c2410.c -@@ -1078,7 +1078,7 @@ static int s3c24xx_i2c_probe(struct plat - else - s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); - -- strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); - i2c->adap.owner = THIS_MODULE; - i2c->adap.algo = &s3c24xx_i2c_algorithm; - i2c->adap.retries = 2; ---- a/drivers/i2c/busses/i2c-sh_mobile.c -+++ b/drivers/i2c/busses/i2c-sh_mobile.c -@@ -930,7 +930,7 @@ static int sh_mobile_i2c_probe(struct pl - adap->nr = dev->id; - adap->dev.of_node = dev->dev.of_node; - -- strlcpy(adap->name, dev->name, sizeof(adap->name)); -+ strscpy(adap->name, dev->name, sizeof(adap->name)); - - spin_lock_init(&pd->lock); - init_waitqueue_head(&pd->wait); ---- a/drivers/i2c/busses/i2c-simtec.c -+++ b/drivers/i2c/busses/i2c-simtec.c -@@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platf - pd->adap.algo_data = &pd->bit; - pd->adap.dev.parent = &dev->dev; - -- strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); -+ strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name)); - - pd->bit.data = pd; - pd->bit.setsda = simtec_i2c_setsda; ---- a/drivers/i2c/busses/i2c-taos-evm.c -+++ b/drivers/i2c/busses/i2c-taos-evm.c -@@ -239,7 +239,7 @@ static int taos_connect(struct serio *se - dev_err(&serio->dev, "TAOS EVM identification failed\n"); - goto exit_close; - } -- strlcpy(adapter->name, name, sizeof(adapter->name)); -+ strscpy(adapter->name, name, sizeof(adapter->name)); - - /* Turn echo off for better performance */ - taos->state = TAOS_STATE_EOFF; ---- a/drivers/i2c/busses/i2c-tegra-bpmp.c -+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c -@@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct p - - i2c_set_adapdata(&i2c->adapter, i2c); - i2c->adapter.owner = THIS_MODULE; -- strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter", -+ strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter", - sizeof(i2c->adapter.name)); - i2c->adapter.algo = &tegra_bpmp_i2c_algo; - i2c->adapter.dev.parent = &pdev->dev; ---- a/drivers/i2c/busses/i2c-tegra.c -+++ b/drivers/i2c/busses/i2c-tegra.c -@@ -1799,7 +1799,7 @@ static int tegra_i2c_probe(struct platfo - if (i2c_dev->hw->supports_bus_clear) - i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; - -- strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), -+ strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), - sizeof(i2c_dev->adapter.name)); - - err = i2c_add_numbered_adapter(&i2c_dev->adapter); ---- a/drivers/i2c/busses/i2c-uniphier-f.c -+++ b/drivers/i2c/busses/i2c-uniphier-f.c -@@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct pl - priv->adap.algo = &uniphier_fi2c_algo; - priv->adap.dev.parent = dev; - priv->adap.dev.of_node = dev->of_node; -- strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); - priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; - i2c_set_adapdata(&priv->adap, priv); - platform_set_drvdata(pdev, priv); ---- a/drivers/i2c/busses/i2c-uniphier.c -+++ b/drivers/i2c/busses/i2c-uniphier.c -@@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct pla - priv->adap.algo = &uniphier_i2c_algo; - priv->adap.dev.parent = dev; - priv->adap.dev.of_node = dev->of_node; -- strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); -+ strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name)); - priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info; - i2c_set_adapdata(&priv->adap, priv); - platform_set_drvdata(pdev, priv); ---- a/drivers/i2c/busses/i2c-versatile.c -+++ b/drivers/i2c/busses/i2c-versatile.c -@@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct pl - writel(SCL | SDA, i2c->base + I2C_CONTROLS); - - i2c->adap.owner = THIS_MODULE; -- strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); -+ strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name)); - i2c->adap.algo_data = &i2c->algo; - i2c->adap.dev.parent = &dev->dev; - i2c->adap.dev.of_node = dev->dev.of_node; ---- a/drivers/i2c/busses/i2c-wmt.c -+++ b/drivers/i2c/busses/i2c-wmt.c -@@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform - - adap = &i2c_dev->adapter; - i2c_set_adapdata(adap, i2c_dev); -- strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); -+ strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); - adap->owner = THIS_MODULE; - adap->algo = &wmt_i2c_algo; - adap->dev.parent = &pdev->dev; diff --git a/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch deleted file mode 100644 index 4c398c59f..000000000 --- a/target/linux/mediatek/patches-5.15/851-v6.2-i2c-mediatek-add-mt7986-support.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 9 Oct 2022 12:16:31 +0200 -Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support - -Add i2c support for MT7986 SoC. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7986_compat = { -+ .quirks = &mt7622_i2c_quirks, -+ .regs = mt_i2c_regs_v1, -+ .pmic_i2c = 0, -+ .dcm = 1, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 0, -+ .dma_sync = 1, -+ .ltiming_adjust = 0, -+ .max_dma_support = 32, -+}; -+ - static const struct mtk_i2c_compatible mt8173_compat = { - .regs = mt_i2c_regs_v1, - .pmic_i2c = 0, -@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, diff --git a/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch deleted file mode 100644 index 18c66cdac..000000000 --- a/target/linux/mediatek/patches-5.15/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001 -From: ye xingchen -Date: Thu, 19 Jan 2023 17:19:58 +0800 -Subject: [PATCH 13/16] i2c: mt65xx: Use - devm_platform_get_and_ioremap_resource() - -Convert platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -Signed-off-by: ye xingchen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform - { - int ret = 0; - struct mtk_i2c *i2c; -- struct resource *res; - int i, irq, speed_clk; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(i2c->base)) - return PTR_ERR(i2c->base); - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -- i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); -+ i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(i2c->pdmabase)) - return PTR_ERR(i2c->pdmabase); - diff --git a/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch deleted file mode 100644 index d000d5352..000000000 --- a/target/linux/mediatek/patches-5.15/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Sat, 11 Mar 2023 12:16:54 +0100 -Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver can match only via the DT table so the table should be always -used and the of_match_ptr does not have any sense (this also allows ACPI -matching via PRP0001, even though it might not be relevant here). - - drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=] - -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Guenter Roeck -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr - .driver = { - .name = I2C_DRV_NAME, - .pm = &mtk_i2c_pm, -- .of_match_table = of_match_ptr(mtk_i2c_of_match), -+ .of_match_table = mtk_i2c_of_match, - }, - }; - diff --git a/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch deleted file mode 100644 index e0973741e..000000000 --- a/target/linux/mediatek/patches-5.15/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 10 Apr 2023 17:19:38 +0100 -Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC - -Add support for the I2C units found in the MediaTek MT7981 and MT7988 -SoCs. Just like other recent MediaTek I2C units that also uses v3 -register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being -0x94 instead of 0x4). - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7981_compat = { -+ .regs = mt_i2c_regs_v3, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 1, -+ .ltiming_adjust = 1, -+ .max_dma_support = 33 -+}; -+ - static const struct mtk_i2c_compatible mt7986_compat = { - .quirks = &mt7622_i2c_quirks, - .regs = mt_i2c_regs_v1, -@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, - { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, diff --git a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index b9aca93d3..000000000 --- a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,65 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -319,7 +319,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch deleted file mode 100644 index c51f7576d..000000000 --- a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1730,6 +1730,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns - if (p != NULL && l > 0) - strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -2060,6 +2060,14 @@ config CMDLINE_FORCE - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EFI_STUB - bool - diff --git a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index 268fb7994..000000000 --- a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -646,5 +646,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch b/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch deleted file mode 100644 index d9379721f..000000000 --- a/target/linux/mediatek/patches-5.15/920-v5.16-watchdog-mtk-add-disable_wdt_extrst-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 59b0f51335644ee603260faaa4298c0115fb7187 Mon Sep 17 00:00:00 2001 -From: Fengquan Chen -Date: Tue, 14 Sep 2021 20:34:54 +0800 -Subject: [PATCH] watchdog: mtk: add disable_wdt_extrst support - -In some cases, we may need watchdog just to trigger an -internal soc reset without sending any output signal. - -Provide a disable_wdt_extrst parameter for configuration. -We can disable or enable it just by configuring dts. - -Signed-off-by: Fengquan Chen -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20210914123454.32603-3-Fengquan.Chen@mediatek.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mtk_wdt.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -65,6 +65,7 @@ struct mtk_wdt_dev { - void __iomem *wdt_base; - spinlock_t lock; /* protects WDT_SWSYSRST reg */ - struct reset_controller_dev rcdev; -+ bool disable_wdt_extrst; - }; - - struct mtk_wdt_data { -@@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog - reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); - else - reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); -+ if (mtk_wdt->disable_wdt_extrst) -+ reg &= ~WDT_MODE_EXRST_EN; - reg |= (WDT_MODE_EN | WDT_MODE_KEY); - iowrite32(reg, wdt_base + WDT_MODE); - -@@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform - if (err) - return err; - } -+ -+ mtk_wdt->disable_wdt_extrst = -+ of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); -+ - return 0; - } - diff --git a/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch b/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch deleted file mode 100644 index 96fb215f7..000000000 --- a/target/linux/mediatek/patches-5.15/921-v5.19-watchdog-mtk_wdt-mt7986-Add-toprgu-reset-controller.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 711a5b25bac95dcd1111521ed71693330e74a926 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Wed, 5 Jan 2022 18:04:56 +0800 -Subject: [PATCH] watchdog: mtk_wdt: mt7986: Add toprgu reset controller - support - -Besides watchdog, the mt7986 toprgu module also provides software reset -functionality for various peripheral subsystems -(eg, ethernet, pcie, and connectivity) - -Signed-off-by: Sam Shih -Reviewed-by: Matthias Brugger -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20220105100456.7126-3-sam.shih@mediatek.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mtk_wdt.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -10,6 +10,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt2712_ - .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, - }; - -+static const struct mtk_wdt_data mt7986_data = { -+ .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, -+}; -+ - static const struct mtk_wdt_data mt8183_data = { - .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, - }; -@@ -418,6 +423,7 @@ static int mtk_wdt_resume(struct device - static const struct of_device_id mtk_wdt_dt_ids[] = { - { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, - { .compatible = "mediatek,mt6589-wdt" }, -+ { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, - { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, - { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, - { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, diff --git a/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch b/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch deleted file mode 100644 index 44aed2207..000000000 --- a/target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Felix Fietkau -Date: Wed, 4 May 2022 12:03:42 +0200 -Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3 - -This allows it to coexist with the other mtk pcie driver in the same kernel - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek-gen3.c -+++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d - .probe = mtk_pcie_probe, - .remove = mtk_pcie_remove, - .driver = { -- .name = "mtk-pcie", -+ .name = "mtk-pcie-gen3", - .of_match_table = mtk_pcie_of_match, - .pm = &mtk_pcie_pm_ops, - }, diff --git a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch deleted file mode 100644 index 09ee4bdaa..000000000 --- a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -1233,10 +1233,16 @@ static int mtk_spi_probe(struct platform - goto err_disable_spi_hclk; - } - -+ ret = clk_prepare_enable(mdata->sel_clk); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret); -+ goto err_disable_spi_clk; -+ } -+ - ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); -- goto err_disable_spi_clk; -+ goto err_disable_spi_sel_clk; - } - - mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); -@@ -1287,6 +1293,8 @@ static int mtk_spi_probe(struct platform - - err_disable_runtime_pm: - pm_runtime_disable(&pdev->dev); -+err_disable_spi_sel_clk: -+ clk_disable_unprepare(mdata->sel_clk); - err_disable_spi_clk: - clk_disable_unprepare(mdata->spi_clk); - err_disable_spi_hclk: diff --git a/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch deleted file mode 100644 index 2fe565f3b..000000000 --- a/target/linux/mediatek/patches-5.15/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 -Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 16:40:31 +0100 -Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename - mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region - -This is a preliminary patch to move wed ilm/dlm and cpuboot properties in -dedicated dts nodes. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -215,8 +215,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we - } - - static int --mtk_wed_get_memory_region(struct mtk_wed_wo *wo, -- struct mtk_wed_wo_memory_region *region) -+mtk_wed_get_reserved_memory_region(struct mtk_wed_wo *wo, -+ struct mtk_wed_wo_memory_region *region) - { - struct reserved_mem *rmem; - struct device_node *np; -@@ -311,13 +311,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- ret = mtk_wed_get_memory_region(wo, &mem_region[i]); -+ ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); - if (ret) - return ret; - } - - wo->boot.name = "wo-boot"; -- ret = mtk_wed_get_memory_region(wo, &wo->boot); -+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); - if (ret) - return ret; - diff --git a/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch deleted file mode 100644 index 0a58ae953..000000000 --- a/target/linux/mediatek/patches-5.15/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 -Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 16:32:41 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -121,12 +121,6 @@ - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; -- -- wo_boot: wo-boot@15194000 { -- reg = <0 0x15194000 0 0x1000>; -- no-map; -- }; -- - }; - - timer { -@@ -518,10 +512,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wed1: wed@15011000 { -@@ -531,10 +526,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wo_ccif0: syscon@151a5000 { -@@ -551,6 +547,11 @@ - interrupts = ; - }; - -+ wo_cpuboot: syscon@15194000 { -+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ - eth: ethernet@15100000 { - compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; diff --git a/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch deleted file mode 100644 index 9de4ffa43..000000000 --- a/target/linux/mediatek/patches-5.15/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch +++ /dev/null @@ -1,89 +0,0 @@ -From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 18:13:04 +0100 -Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a - dedicated dts node - -Since the cpuboot memory region is not part of the RAM SoC, move cpuboot -in a deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where cpuboot was -defined as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -18,12 +18,23 @@ - - static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) - { -- return readl(wo->boot.addr + reg); -+ u32 val; -+ -+ if (!wo->boot_regmap) -+ return readl(wo->boot.addr + reg); -+ -+ if (regmap_read(wo->boot_regmap, reg, &val)) -+ val = ~0; -+ -+ return val; - } - - static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) - { -- writel(val, wo->boot.addr + reg); -+ if (wo->boot_regmap) -+ regmap_write(wo->boot_regmap, reg, val); -+ else -+ writel(val, wo->boot.addr + reg); - } - - static struct sk_buff * -@@ -316,10 +327,21 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - return ret; - } - -- wo->boot.name = "wo-boot"; -- ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); -- if (ret) -- return ret; -+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, -+ "mediatek,wo-cpuboot"); -+ if (IS_ERR(wo->boot_regmap)) { -+ if (wo->boot_regmap != ERR_PTR(-ENODEV)) -+ return PTR_ERR(wo->boot_regmap); -+ -+ /* For backward compatibility, we need to check if cpu_boot -+ * is defined through reserved memory property. -+ */ -+ wo->boot_regmap = NULL; -+ wo->boot.name = "wo-boot"; -+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); -+ if (ret) -+ return ret; -+ } - - /* set dummy cr */ - wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL, ---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h -+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h -@@ -228,7 +228,8 @@ struct mtk_wed_wo_queue { - - struct mtk_wed_wo { - struct mtk_wed_hw *hw; -- struct mtk_wed_wo_memory_region boot; -+ struct mtk_wed_wo_memory_region boot; /* backward compatibility */ -+ struct regmap *boot_regmap; - - struct mtk_wed_wo_queue q_tx; - struct mtk_wed_wo_queue q_rx; diff --git a/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch deleted file mode 100644 index 7b6c5d1e2..000000000 --- a/target/linux/mediatek/patches-5.15/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,91 +0,0 @@ -From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 -Message-Id: -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 18:51:47 +0100 -Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts - node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where ilm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- - 1 file changed, 49 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -300,6 +300,52 @@ next: - } - - static int -+mtk_wed_mcu_load_memory_regions(struct mtk_wed_wo *wo, -+ struct mtk_wed_wo_memory_region *region) -+{ -+ struct device_node *np; -+ int ret; -+ -+ /* firmware EMI memory region */ -+ ret = mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_EMI]); -+ if (ret) -+ return ret; -+ -+ /* firmware DATA memory region */ -+ ret = mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_DATA]); -+ if (ret) -+ return ret; -+ -+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); -+ if (np) { -+ struct mtk_wed_wo_memory_region *ilm_region; -+ struct resource res; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ ilm_region = ®ion[MTK_WED_WO_REGION_ILM]; -+ ilm_region->phy_addr = res.start; -+ ilm_region->size = resource_size(&res); -+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, -+ resource_size(&res)); -+ -+ return IS_ERR(ilm_region->addr) ? PTR_ERR(ilm_region->addr) : 0; -+ } -+ -+ /* For backward compatibility, we need to check if ILM -+ * node is defined through reserved memory property. -+ */ -+ return mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_ILM]); -+} -+ -+static int - mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) - { - static struct mtk_wed_wo_memory_region mem_region[] = { -@@ -320,12 +366,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -- /* load firmware region metadata */ -- for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); -- if (ret) -- return ret; -- } -+ ret = mtk_wed_mcu_load_memory_regions(wo, mem_region); -+ if (ret) -+ return ret; - - wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, - "mediatek,wo-cpuboot"); diff --git a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch deleted file mode 100644 index eed97b476..000000000 --- a/target/linux/mediatek/patches-5.15/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: -References: -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:45:16 +0100 -Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts - node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where dlm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_wed.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -821,6 +821,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device - struct device_node *np; - int index; - -+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); -+ if (np) { -+ struct resource res; -+ int ret; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ dev->rro.miod_phys = res.start; -+ goto out; -+ } -+ -+ /* For backward compatibility, we need to check if DLM -+ * node is defined through reserved memory property. -+ */ - index = of_property_match_string(dev->hw->node, "memory-region-names", - "wo-dlm"); - if (index < 0) -@@ -837,6 +855,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device - return -ENODEV; - - dev->rro.miod_phys = rmem->base; -+out: - dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; - - return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch deleted file mode 100644 index 36fe92783..000000000 --- a/target/linux/mediatek/patches-5.15/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 -Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:10:56 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ - 1 file changed, 16 insertions(+), 18 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -97,16 +97,6 @@ - no-map; - }; - -- wo_ilm0: wo-ilm@151e0000 { -- reg = <0 0x151e0000 0 0x8000>; -- no-map; -- }; -- -- wo_ilm1: wo-ilm@151f0000 { -- reg = <0 0x151f0000 0 0x8000>; -- no-map; -- }; -- - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; -@@ -511,11 +501,10 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -525,11 +514,10 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-ilm = <&wo_ilm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -547,6 +535,16 @@ - interrupts = ; - }; - -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_ilm1: syscon@151f0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151f0000 0 0x8000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch deleted file mode 100644 index 55f17286c..000000000 --- a/target/linux/mediatek/patches-5.15/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 -Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:53:30 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- - 1 file changed, 16 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -101,16 +101,6 @@ - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; -- -- wo_dlm0: wo-dlm@151e8000 { -- reg = <0 0x151e8000 0 0x2000>; -- no-map; -- }; -- -- wo_dlm1: wo-dlm@151f8000 { -- reg = <0 0x151f8000 0 0x2000>; -- no-map; -- }; - }; - - timer { -@@ -501,10 +491,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -514,10 +505,11 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; - mediatek,wo-ilm = <&wo_ilm1>; -+ mediatek,wo-dlm = <&wo_dlm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -545,6 +537,16 @@ - reg = <0 0x151f0000 0 0x8000>; - }; - -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_dlm1: syscon@151f8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151f8000 0 0x2000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch deleted file mode 100644 index 17c5c6098..000000000 --- a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001 -From: Andrew Davis -Date: Mon, 24 Oct 2022 12:34:28 -0500 -Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source - files - -Currently DTB Overlays (.dtbo) are build from source files with the same -extension (.dts) as the base DTs (.dtb). This may become confusing and -even lead to wrong results. For example, a composite DTB (created from a -base DTB and a set of overlays) might have the same name as one of the -overlays that create it. - -Different files should be generated from differently named sources. - .dtb <-> .dts - .dtbo <-> .dtso - -We do not remove the ability to compile DTBO files from .dts files here, -only add a new rule allowing the .dtso file name. The current .dts named -overlays can be renamed with time. After all have been renamed we can -remove the other rule. - -Signed-off-by: Andrew Davis -Reviewed-by: Geert Uytterhoeven -Tested-by: Geert Uytterhoeven -Reviewed-by: Frank Rowand -Tested-by: Frank Rowand -Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com -Signed-off-by: Rob Herring ---- - scripts/Makefile.lib | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T - $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE - $(call if_changed_dep,dtc) - -+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE -+ $(call if_changed_dep,dtc) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 diff --git a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch b/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch deleted file mode 100644 index e6c6eb616..000000000 --- a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Sat, 5 Nov 2022 23:36:16 +0100 -Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX - Wireless Ethernet Dispatch - -Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet -Dispatch to offload traffic received by the wlan interface to lan/wan -one. - -Co-developed-by: Sujuan Chen -Signed-off-by: Sujuan Chen -Signed-off-by: Lorenzo Bianconi -Signed-off-by: David S. Miller ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++ - 1 file changed, 65 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -76,6 +76,47 @@ - no-map; - reg = <0 0x4fc00000 0 0x00100000>; - }; -+ -+ wo_emi0: wo-emi@4fd00000 { -+ reg = <0 0x4fd00000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_emi1: wo-emi@4fd40000 { -+ reg = <0 0x4fd40000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_ilm0: wo-ilm@151e0000 { -+ reg = <0 0x151e0000 0 0x8000>; -+ no-map; -+ }; -+ -+ wo_ilm1: wo-ilm@151f0000 { -+ reg = <0 0x151f0000 0 0x8000>; -+ no-map; -+ }; -+ -+ wo_data: wo-data@4fd80000 { -+ reg = <0 0x4fd80000 0 0x240000>; -+ no-map; -+ }; -+ -+ wo_dlm0: wo-dlm@151e8000 { -+ reg = <0 0x151e8000 0 0x2000>; -+ no-map; -+ }; -+ -+ wo_dlm1: wo-dlm@151f8000 { -+ reg = <0 0x151f8000 0 0x2000>; -+ no-map; -+ }; -+ -+ wo_boot: wo-boot@15194000 { -+ reg = <0 0x15194000 0 0x1000>; -+ no-map; -+ }; -+ - }; - - timer { -@@ -240,6 +281,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -+ <&wo_data>, <&wo_boot>; -+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -+ "wo-data", "wo-boot"; -+ mediatek,wo-ccif = <&wo_ccif0>; - }; - - wed1: wed@15011000 { -@@ -248,6 +294,25 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -+ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -+ <&wo_data>, <&wo_boot>; -+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -+ "wo-data", "wo-boot"; -+ mediatek,wo-ccif = <&wo_ccif1>; -+ }; -+ -+ wo_ccif0: syscon@151a5000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ wo_ccif1: syscon@151ad000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151ad000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; - }; - - eth: ethernet@15100000 { diff --git a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch b/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch deleted file mode 100644 index b5091687a..000000000 --- a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:50:24 +0100 -Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order - -This arrange device tree nodes in alphabetical order. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++---------- - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++--- - 2 files changed, 58 insertions(+), 58 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -54,6 +54,53 @@ - }; - }; - -+&pio { -+ uart1_pins: uart1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2"; -+ }; -+ }; -+ -+ wf_2g_5g_pins: wf-2g-5g-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_2g", "wf_5g"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_dbdc_pins: wf-dbdc-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_dbdc"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+}; -+ - &switch { - ports { - #address-cells = <1>; -@@ -121,50 +168,3 @@ - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; - }; -- --&pio { -- uart1_pins: uart1-pins { -- mux { -- function = "uart"; -- groups = "uart1"; -- }; -- }; -- -- uart2_pins: uart2-pins { -- mux { -- function = "uart"; -- groups = "uart2"; -- }; -- }; -- -- wf_2g_5g_pins: wf-2g-5g-pins { -- mux { -- function = "wifi"; -- groups = "wf_2g", "wf_5g"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -- "WF1_TOP_CLK", "WF1_TOP_DATA"; -- drive-strength = <4>; -- }; -- }; -- -- wf_dbdc_pins: wf-dbdc-pins { -- mux { -- function = "wifi"; -- groups = "wf_dbdc"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA"; -- drive-strength = <4>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -25,10 +25,6 @@ - }; - }; - --&uart0 { -- status = "okay"; --}; -- - ð { - status = "okay"; - -@@ -99,13 +95,6 @@ - }; - }; - --&wifi { -- status = "okay"; -- pinctrl-names = "default", "dbdc"; -- pinctrl-0 = <&wf_2g_5g_pins>; -- pinctrl-1 = <&wf_dbdc_pins>; --}; -- - &pio { - wf_2g_5g_pins: wf-2g-5g-pins { - mux { -@@ -138,3 +127,14 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&wifi { -+ status = "okay"; -+ pinctrl-names = "default", "dbdc"; -+ pinctrl-0 = <&wf_2g_5g_pins>; -+ pinctrl-1 = <&wf_dbdc_pins>; -+}; diff --git a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch deleted file mode 100644 index fec048e68..000000000 --- a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch +++ /dev/null @@ -1,68 +0,0 @@ -From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:50:27 +0100 -Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes - -This patch adds crypto engine support for MT7986. - -Signed-off-by: Vic Wu -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ - 3 files changed, 23 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -25,6 +25,10 @@ - }; - }; - -+&crypto { -+ status = "okay"; -+}; -+ - ð { - status = "okay"; - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -224,6 +224,21 @@ - status = "disabled"; - }; - -+ crypto: crypto@10320000 { -+ compatible = "inside-secure,safexcel-eip97"; -+ reg = <0 0x10320000 0 0x40000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; -+ clocks = <&infracfg CLK_INFRA_EIP97_CK>; -+ clock-names = "infra_eip97_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -25,6 +25,10 @@ - }; - }; - -+&crypto { -+ status = "okay"; -+}; -+ - ð { - status = "okay"; - diff --git a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch b/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch deleted file mode 100644 index 132940915..000000000 --- a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Nov 2022 09:50:29 +0100 -Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node - -Add i2c Node to mt7986 devicetree. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -280,6 +280,20 @@ - status = "disabled"; - }; - -+ i2c0: i2c@11008000 { -+ compatible = "mediatek,mt7986-i2c"; -+ reg = <0 0x11008000 0 0x90>, -+ <0 0x10217080 0 0x80>; -+ interrupts = ; -+ clock-div = <5>; -+ clocks = <&infracfg CLK_INFRA_I2C0_CK>, -+ <&infracfg CLK_INFRA_AP_DMA_CK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; diff --git a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch b/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch deleted file mode 100644 index 8201b47df..000000000 --- a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Mon, 14 Nov 2022 13:16:53 +0100 -Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible - -Missing SoC compatible in the board file causes dt bindings check. - -Signed-off-by: Matthias Brugger -Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 + - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +- - arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++ - 4 files changed, 6 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -9,7 +9,7 @@ - - / { - model = "MediaTek MT7986a RFB"; -- compatible = "mediatek,mt7986a-rfb"; -+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; - - aliases { - serial0 = &uart0; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -10,6 +10,7 @@ - #include - - / { -+ compatible = "mediatek,mt7986a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -9,7 +9,7 @@ - - / { - model = "MediaTek MT7986b RFB"; -- compatible = "mediatek,mt7986b-rfb"; -+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; - - aliases { - serial0 = &uart0; ---- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi -@@ -5,6 +5,9 @@ - */ - - #include "mt7986a.dtsi" -+/ { -+ compatible = "mediatek,mt7986b"; -+}; - - &pio { - compatible = "mediatek,mt7986b-pinctrl"; diff --git a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch deleted file mode 100644 index 619bfec09..000000000 --- a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch +++ /dev/null @@ -1,157 +0,0 @@ -From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 18 Nov 2022 20:01:21 +0100 -Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes - -This patch adds spi support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ - 3 files changed, 98 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -59,6 +59,20 @@ - }; - - &pio { -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ - uart1_pins: uart1-pins { - mux { - function = "uart"; -@@ -105,6 +119,27 @@ - }; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+}; -+ - &switch { - ports { - #address-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -295,6 +295,34 @@ - status = "disabled"; - }; - -+ spi0: spi@1100a000 { -+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0 0x1100a000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_SPI0_CK>, -+ <&infracfg CLK_INFRA_SPI0_HCK_CK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@1100b000 { -+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0 0x1100b000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_SPI1_CK>, -+ <&infracfg CLK_INFRA_SPI1_HCK_CK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; -+ status = "disabled"; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -100,6 +100,20 @@ - }; - - &pio { -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; -@@ -132,6 +146,27 @@ - }; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+}; -+ - &uart0 { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch deleted file mode 100644 index 603f33b15..000000000 --- a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:42 +0100 -Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes - -This patch adds USB support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++ - 3 files changed, 71 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -140,6 +140,10 @@ - status = "okay"; - }; - -+&ssusb { -+ status = "okay"; -+}; -+ - &switch { - ports { - #address-cells = <1>; -@@ -201,6 +205,10 @@ - status = "okay"; - }; - -+&usb_phy { -+ status = "okay"; -+}; -+ - &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -323,6 +323,61 @@ - status = "disabled"; - }; - -+ ssusb: usb@11200000 { -+ compatible = "mediatek,mt7986-xhci", -+ "mediatek,mtk-xhci"; -+ reg = <0 0x11200000 0 0x2e00>, -+ <0 0x11203e00 0 0x0100>; -+ reg-names = "mac", "ippc"; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, -+ <&infracfg CLK_INFRA_IUSB_CK>, -+ <&infracfg CLK_INFRA_IUSB_133_CK>, -+ <&infracfg CLK_INFRA_IUSB_66M_CK>, -+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; -+ clock-names = "sys_ck", -+ "ref_ck", -+ "mcu_ck", -+ "dma_ck", -+ "xhci_ck"; -+ phys = <&u2port0 PHY_TYPE_USB2>, -+ <&u3port0 PHY_TYPE_USB3>, -+ <&u2port1 PHY_TYPE_USB2>; -+ status = "disabled"; -+ }; -+ -+ usb_phy: t-phy@11e10000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0 0x11e10000 0x1700>; -+ status = "disabled"; -+ -+ u2port0: usb-phy@0 { -+ reg = <0x0 0x700>; -+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, -+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; -+ clock-names = "ref", "da_ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u3port0: usb-phy@700 { -+ reg = <0x700 0x900>; -+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u2port1: usb-phy@1000 { -+ reg = <0x1000 0x700>; -+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, -+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; -+ clock-names = "ref", "da_ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -167,10 +167,18 @@ - status = "okay"; - }; - -+&ssusb { -+ status = "okay"; -+}; -+ - &uart0 { - status = "okay"; - }; - -+&usb_phy { -+ status = "okay"; -+}; -+ - &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; diff --git a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch deleted file mode 100644 index 40e71cd42..000000000 --- a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch +++ /dev/null @@ -1,160 +0,0 @@ -From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:43 +0100 -Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes - -This patch adds mmc support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++ - 2 files changed, 111 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -5,6 +5,8 @@ - */ - - /dts-v1/; -+#include -+ - #include "mt7986a.dtsi" - - / { -@@ -23,6 +25,24 @@ - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; - }; - - &crypto { -@@ -58,7 +78,83 @@ - }; - }; - -+&mmc0 { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ pinctrl-1 = <&mmc0_pins_uhs>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x14014>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ - &pio { -+ mmc0_pins_default: mmc0-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ mmc0_pins_uhs: mmc0-uhs-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -346,6 +346,21 @@ - status = "disabled"; - }; - -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7986-mmc"; -+ reg = <0 0x11230000 0 0x1000>, -+ <0 0x11c20000 0 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, -+ <&infracfg CLK_INFRA_MSDC_HCK_CK>, -+ <&infracfg CLK_INFRA_MSDC_CK>, -+ <&infracfg CLK_INFRA_MSDC_133M_CK>, -+ <&infracfg CLK_INFRA_MSDC_66M_CK>; -+ clock-names = "source", "hclk", "source_cg", "bus_clk", -+ "sys_cg"; -+ status = "disabled"; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch deleted file mode 100644 index ab039c335..000000000 --- a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:44 +0100 -Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes - -This patch adds PCIe support for MT7986. - -Signed-off-by: Jieyy Yang -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++ - 2 files changed, 68 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -93,6 +93,15 @@ - non-removable; - no-sd; - no-sdio; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pins>; -+ status = "okay"; -+}; -+ -+&pcie_phy { - status = "okay"; - }; - -@@ -155,6 +164,13 @@ - }; - }; - -+ pcie_pins: pcie-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_clk", "pcie_wake", "pcie_pereset"; -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7986a"; -@@ -361,6 +362,57 @@ - status = "disabled"; - }; - -+ pcie: pcie@11280000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0x00 0x11280000 0x00 0x4000>; -+ reg-names = "pcie-mac"; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0x00 0x20000000 0x00 -+ 0x20000000 0x00 0x10000000>; -+ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, -+ <&infracfg CLK_INFRA_IPCIE_CK>, -+ <&infracfg CLK_INFRA_IPCIER_CK>, -+ <&infracfg CLK_INFRA_IPCIEB_CK>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; -+ status = "disabled"; -+ -+ phys = <&pcie_port PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ pcie_intc: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie_phy: t-phy@11c00000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ pcie_port: pcie-phy@11c00000 { -+ reg = <0 0x11c00000 0 0x20000>; -+ clocks = <&clk40m>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch b/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch deleted file mode 100644 index abe0b6e9b..000000000 --- a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch +++ /dev/null @@ -1,689 +0,0 @@ -From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 6 Jan 2023 16:28:45 +0100 -Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3 - -Add support for Bananapi R3 SBC. - -- SD/eMMC support (switching first 4 bits of data-bus with sw6/D) -- SPI-NAND/NOR support (switched CS by sw5/C) -- all rj45 ports and both SFP working (eth1/lan4) -- all USB-Ports + SIM-Slot tested -- i2c and all uarts tested -- wifi tested (with eeprom calibration data) - -The device can boot from all 4 storage options. Both, SPI and MMC, can -be switched using hardware switches on the board, see -https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/Makefile | 5 + - .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++ - .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++ - .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++ - .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 + - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++ - 6 files changed, 630 insertions(+) - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts - ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev - dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/mmc@11230000"; -+ __overlay__ { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x14014>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+ }; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -0,0 +1,55 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+/* -+ * Authors: Daniel Golle -+ * Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/spi@1100a000"; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "reserved"; -+ reg = <0x80000 0x300000>; -+ }; -+ -+ partition@380000 { -+ label = "fip"; -+ reg = <0x380000 0x200000>; -+ read-only; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x7a80000>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -0,0 +1,68 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+/* -+ * Authors: Daniel Golle -+ * Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/spi@1100a000"; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x20000>; -+ read-only; -+ }; -+ -+ partition@20000 { -+ label = "reserved"; -+ reg = <0x20000 0x20000>; -+ }; -+ -+ partition@40000 { -+ label = "u-boot-env"; -+ reg = <0x40000 0x40000>; -+ }; -+ -+ partition@80000 { -+ label = "reserved2"; -+ reg = <0x80000 0x80000>; -+ }; -+ -+ partition@100000 { -+ label = "fip"; -+ reg = <0x100000 0x80000>; -+ read-only; -+ }; -+ -+ partition@180000 { -+ label = "recovery"; -+ reg = <0x180000 0xa80000>; -+ }; -+ -+ partition@c00000 { -+ label = "fit"; -+ reg = <0xc00000 0x1400000>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/mmc@11230000"; -+ __overlay__ { -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ status = "okay"; -+ }; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -0,0 +1,450 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Authors: Sam.Shih -+ * Frank Wunderlich -+ * Daniel Golle -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+ -+#include "mt7986a.dtsi" -+ -+/ { -+ model = "Bananapi BPI-R3"; -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ dcin: regulator-12vd { -+ compatible = "regulator-fixed"; -+ regulator-name = "12vd"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ reset-key { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&pio 9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps-key { -+ label = "wps"; -+ linux,code = ; -+ gpios = <&pio 10 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ /* i2c of the left SFP cage (wan) */ -+ i2c_sfp1: i2c-gpio-0 { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ i2c-gpio,delay-us = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ /* i2c of the right SFP cage (lan) */ -+ i2c_sfp2: i2c-gpio-1 { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ i2c-gpio,delay-us = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ green_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_POWER; -+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ blue_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&pio 86 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1.8vd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&dcin>; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3.3vd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&dcin>; -+ }; -+ -+ /* left SFP cage (wan) */ -+ sfp1: sfp-1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ /* right SFP cage (lan) */ -+ sfp2: sfp-2 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp2>; -+ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&crypto { -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ phy-mode = "2500base-x"; -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ }; -+ -+ mdio: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+}; -+ -+&mdio { -+ switch: switch@31 { -+ compatible = "mediatek,mt7531"; -+ reg = <31>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ pinctrl-1 = <&mmc0_pins_uhs>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pins>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pio { -+ i2c_pins: i2c-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ mmc0_pins_uhs: mmc0-uhs-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ pcie_pins: pcie-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_clk", "pcie_pereset"; -+ }; -+ }; -+ -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_0"; -+ }; -+ }; -+ -+ uart1_pins: uart1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_rx_tx"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_0_rx_tx"; -+ }; -+ }; -+ -+ wf_2g_5g_pins: wf-2g-5g-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_2g", "wf_5g"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_dbdc_pins: wf-dbdc-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_dbdc"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_led_pins: wf-led-pins { -+ mux { -+ function = "led"; -+ groups = "wifi_led"; -+ }; -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ status = "okay"; -+}; -+ -+&ssusb { -+ status = "okay"; -+}; -+ -+&switch { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan0"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan1"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan2"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan3"; -+ }; -+ -+ port5: port@5 { -+ reg = <5>; -+ label = "lan4"; -+ phy-mode = "2500base-x"; -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+}; -+ -+&trng { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+ status = "okay"; -+}; -+ -+&usb_phy { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; -+ -+&wifi { -+ status = "okay"; -+ pinctrl-names = "default", "dbdc"; -+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+}; -+ diff --git a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch b/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch deleted file mode 100644 index 79038334c..000000000 --- a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch +++ /dev/null @@ -1,323 +0,0 @@ -From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 17 May 2023 12:11:08 +0200 -Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible - -The chassis-type string identifies the form-factor of the system: -add this property to all device trees of devices for which the form -factor is known. - -Signed-off-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 + - .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 + - 28 files changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT2712 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6755 EVB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts -@@ -10,6 +10,7 @@ - - / { - model = "MediaTek MT6779 EVB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6795 Evaluation Board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6797 Evaluation Board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts -@@ -12,6 +12,7 @@ - - / { - model = "Mediatek X20 Development Board"; -+ chassis-type = "embedded"; - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -15,6 +15,7 @@ - - / { - model = "Bananapi BPI-R64"; -+ chassis-type = "embedded"; - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -15,6 +15,7 @@ - - / { - model = "MediaTek MT7622 RFB1 board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -16,6 +16,7 @@ - - / { - model = "Bananapi BPI-R3"; -+ chassis-type = "embedded"; - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT7986a RFB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT7986b RFB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts -@@ -11,6 +11,7 @@ - - / { - model = "Pumpkin MT8167"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; - - memory@40000000 { ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Hanawl"; -+ chassis-type = "laptop"; - compatible = "google,hana-rev7", "mediatek,mt8173"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Hana"; -+ chassis-type = "laptop"; - compatible = "google,hana-rev6", "google,hana-rev5", - "google,hana-rev4", "google,hana-rev3", - "google,hana", "mediatek,mt8173"; ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Elm"; -+ chassis-type = "laptop"; - compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", - "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", - "google,elm", "mediatek,mt8173"; ---- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts -@@ -10,6 +10,7 @@ - - / { - model = "MediaTek MT8173 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT8183 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google burnet board"; -+ chassis-type = "convertible"; - compatible = "google,burnet", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google damu board"; -+ chassis-type = "convertible"; - compatible = "google,damu", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google juniper sku16 board"; -+ chassis-type = "convertible"; - compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek kakadu board sku22"; -+ chassis-type = "tablet"; - compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", - "google,kakadu", "mediatek,mt8183"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek kakadu board"; -+ chassis-type = "tablet"; - compatible = "google,kakadu-rev3", "google,kakadu-rev2", - "google,kakadu", "mediatek,mt8183"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku16 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku272 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku288 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts -@@ -14,6 +14,7 @@ - - / { - model = "MediaTek krane sku0 board"; -+ chassis-type = "tablet"; - compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts -@@ -14,6 +14,7 @@ - - / { - model = "MediaTek krane sku176 board"; -+ chassis-type = "tablet"; - compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts -@@ -7,6 +7,7 @@ - - / { - model = "MediaTek MT8186 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; - - aliases { diff --git a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch b/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch deleted file mode 100644 index 915da7984..000000000 --- a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 21 Apr 2023 15:20:44 +0200 -Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM - -This adds pwm node to mt7986. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -241,6 +241,20 @@ - status = "disabled"; - }; - -+ pwm: pwm@10048000 { -+ compatible = "mediatek,mt7986-pwm"; -+ reg = <0 0x10048000 0 0x1000>; -+ #clock-cells = <1>; -+ #pwm-cells = <2>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_PWM_SEL>, -+ <&infracfg CLK_INFRA_PWM_STA>, -+ <&infracfg CLK_INFRA_PWM1_CK>, -+ <&infracfg CLK_INFRA_PWM2_CK>; -+ clock-names = "top", "main", "pwm1", "pwm2"; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; diff --git a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch b/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch deleted file mode 100644 index ce908e3d3..000000000 --- a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 21 Apr 2023 15:20:45 +0200 -Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3 - -Add pwm node and pinctrl to BananaPi R3 devicetree. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -275,6 +275,13 @@ - }; - }; - -+ pwm_pins: pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0", "pwm1_0"; -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; -@@ -345,6 +352,12 @@ - }; - }; - -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; diff --git a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch b/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch deleted file mode 100644 index c7b38484f..000000000 --- a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch +++ /dev/null @@ -1,27 +0,0 @@ -From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 5 Feb 2023 18:48:33 +0100 -Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3 - -Leds for Wifi are low-active, so add property to devicetree. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -460,5 +460,9 @@ - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; - pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ led { -+ led-active-low; -+ }; - }; - diff --git a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch b/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch deleted file mode 100644 index 0b84f1463..000000000 --- a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 28 May 2023 13:33:42 +0200 -Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for - bl2 - -To store uncompressed bl2 more space is required than partition is -actually defined. - -There is currently no known usage of this reserved partition. -Openwrt uses same partition layout. - -We added same change to u-boot with commit d7bb1099 [1]. - -[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e - -Cc: stable@vger.kernel.org -Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Daniel Golle -Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -27,15 +27,10 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x20000>; -+ reg = <0x0 0x40000>; - read-only; - }; - -- partition@20000 { -- label = "reserved"; -- reg = <0x20000 0x20000>; -- }; -- - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; diff --git a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch b/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch deleted file mode 100644 index f1cb0eaf0..000000000 --- a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:33 +0200 -Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse - -Add thermal related nodes to mt7986 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -338,6 +338,15 @@ - status = "disabled"; - }; - -+ auxadc: adc@1100d000 { -+ compatible = "mediatek,mt7986-auxadc"; -+ reg = <0 0x1100d000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "main"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - ssusb: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; -@@ -376,6 +385,21 @@ - status = "disabled"; - }; - -+ thermal: thermal@1100c800 { -+ #thermal-sensor-cells = <1>; -+ compatible = "mediatek,mt7986-thermal"; -+ reg = <0 0x1100c800 0 0x800>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_THERM_CK>, -+ <&infracfg CLK_INFRA_ADC_26M_CK>, -+ <&infracfg CLK_INFRA_ADC_FRC_CK>; -+ clock-names = "therm", "auxadc", "adc_32k"; -+ mediatek,auxadc = <&auxadc>; -+ mediatek,apmixedsys = <&apmixedsys>; -+ nvmem-cells = <&thermal_calibration>; -+ nvmem-cell-names = "calibration-data"; -+ }; -+ - pcie: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; -@@ -427,6 +451,17 @@ - }; - }; - -+ efuse: efuse@11d00000 { -+ compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; -+ reg = <0 0x11d00000 0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ thermal_calibration: calib@274 { -+ reg = <0x274 0xc>; -+ }; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; -@@ -568,5 +603,4 @@ - memory-region = <&wmcpu_emi>; - }; - }; -- - }; diff --git a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch b/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch deleted file mode 100644 index ad21fb8c3..000000000 --- a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:34 +0200 -Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones - -Add thermal-zones to mt7986 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -603,4 +603,32 @@ - memory-region = <&wmcpu_emi>; - }; - }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <1000>; -+ thermal-sensors = <&thermal 0>; -+ -+ trips { -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_passive: passive { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ }; -+ }; -+ }; - }; diff --git a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch b/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch deleted file mode 100644 index ca7d872a1..000000000 --- a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:35 +0200 -Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to - BPI-R3 dts - -Add pwm-fan and cooling-maps to BananaPi-R3 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++ - 1 file changed, 31 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -38,6 +38,15 @@ - regulator-always-on; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ #cooling-cells = <2>; -+ /* cooling level (0, 1, 2) - pwm inverted */ -+ cooling-levels = <255 96 0>; -+ pwms = <&pwm 0 10000 0>; -+ status = "okay"; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - -@@ -133,6 +142,28 @@ - }; - }; - -+&cpu_thermal { -+ cooling-maps { -+ cpu-active-high { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ cpu-active-low { -+ /* active: set fan to cooling level 1 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ -+ cpu-passive { -+ /* passive: set fan to cooling level 0 */ -+ cooling-device = <&fan 0 0>; -+ trip = <&cpu_trip_passive>; -+ }; -+ }; -+}; -+ - &crypto { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch b/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch deleted file mode 100644 index 9cc6cad0a..000000000 --- a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 6 Jun 2023 16:43:20 +0100 -Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of - Bananapi R3 - -The bootrom burned into the MT7986 SoC will try multiple locations on -the SPI-NAND flash to load bl2 in case the bl2 image located at the the -previously attempted offset is corrupt. - -Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND, -allowing for up to four redundant copies of bl2 (typically sized a -bit less than 0x40000). - -Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -29,13 +29,13 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x80000>; -+ reg = <0x0 0x100000>; - read-only; - }; - -- partition@80000 { -+ partition@100000 { - label = "reserved"; -- reg = <0x80000 0x300000>; -+ reg = <0x100000 0x280000>; - }; - - partition@380000 { diff --git a/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch deleted file mode 100644 index 8cba3b205..000000000 --- a/target/linux/mediatek/patches-6.1/020-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch +++ /dev/null @@ -1,34 +0,0 @@ -From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 20 Aug 2023 17:31:33 +0200 -Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on - BPI-R3 - -All SFP power supplies are connected to the system VDD33 which is 3v3/8A. -Set 3A per SFP slot to allow SFPs work which need more power than the -default 1W. - -Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -126,6 +126,7 @@ - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; -+ maximum-power-milliwatt = <3000>; - mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; -@@ -137,6 +138,7 @@ - i2c-bus = <&i2c_sfp2>; - los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; - tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch b/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch deleted file mode 100644 index 318ca43e1..000000000 --- a/target/linux/mediatek/patches-6.1/021-arm64-dts-mt7986-change-cooling-trips.patch +++ /dev/null @@ -1,59 +0,0 @@ -From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 20 Aug 2023 17:31:34 +0200 -Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips - -Add Critical and hot trips for emergency system shutdown and limiting -system load. - -Change passive trip to active to make sure fan is activated on the -lowest trip. - -Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones") -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++---- - 1 file changed, 16 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -611,22 +611,34 @@ - thermal-sensors = <&thermal 0>; - - trips { -+ cpu_trip_crit: crit { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - -- cpu_trip_active_low: active-low { -+ cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - -- cpu_trip_passive: passive { -- temperature = <40000>; -+ cpu_trip_active_low: active-low { -+ temperature = <60000>; - hysteresis = <2000>; -- type = "passive"; -+ type = "active"; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch deleted file mode 100644 index 7166ab6a1..000000000 --- a/target/linux/mediatek/patches-6.1/022-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 20 Aug 2023 17:31:35 +0200 -Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3 - -Apply new naming after mt7986 thermal trips were changed. - -Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts") -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -152,16 +152,16 @@ - trip = <&cpu_trip_active_high>; - }; - -- cpu-active-low { -+ cpu-active-med { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; -- trip = <&cpu_trip_active_low>; -+ trip = <&cpu_trip_active_med>; - }; - -- cpu-passive { -- /* passive: set fan to cooling level 0 */ -+ cpu-active-low { -+ /* active: set fan to cooling level 0 */ - cooling-device = <&fan 0 0>; -- trip = <&cpu_trip_passive>; -+ trip = <&cpu_trip_active_low>; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index 1eeed82c1..000000000 --- a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,107 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -24,7 +23,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -45,18 +44,18 @@ - key-factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - key-wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory@40000000 { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - device_type = "memory"; - }; - -@@ -133,22 +132,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -241,7 +240,22 @@ - status = "okay"; - }; - -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; -+}; -+ - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -518,11 +532,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index b1770371b..000000000 --- a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -273,3 +282,17 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch deleted file mode 100644 index 04df7b927..000000000 --- a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch +++ /dev/null @@ -1,20 +0,0 @@ -From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Fri, 29 Apr 2022 10:40:56 +0800 -Subject: [PATCH] arm: mediatek: select arch timer for mt7623 - -Signed-off-by: Chuanhong Guo ---- - arch/arm/mach-mediatek/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -26,6 +26,7 @@ config MACH_MT6592 - config MACH_MT7623 - bool "MediaTek MT7623 SoCs support" - default ARCH_MEDIATEK -+ select HAVE_ARM_ARCH_TIMER - - config MACH_MT7629 - bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch deleted file mode 100644 index d15d989e9..000000000 --- a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -575,6 +575,7 @@ - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; -+ interrupts = ; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index 93da722e7..000000000 --- a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -134,6 +134,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 8dc53d298..000000000 --- a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch deleted file mode 100644 index f77f10cb9..000000000 --- a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -24,7 +24,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index 7f97ef4ae..000000000 --- a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -20,6 +20,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -165,22 +166,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@6 { diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index bf1912a91..000000000 --- a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -21,6 +21,10 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -44,8 +48,8 @@ - compatible = "gpio-keys"; - - factory-key { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -59,17 +63,17 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ led_system_green: led-0 { - label = "bpi-r64:pio:green"; - color = ; - gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- led-1 { -- label = "bpi-r64:pio:red"; -- color = ; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_blue: led-1 { -+ label = "bpi-r64:pio:blue"; -+ color = ; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index 261579bf3..000000000 --- a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -559,12 +559,16 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { -- status = "disable"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "disable"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch deleted file mode 100644 index 20b0d90b2..000000000 --- a/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -256,14 +256,42 @@ - status = "disabled"; - }; - --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+&bch { -+ status = "okay"; -+}; - -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; - flash@0 { -- compatible = "jedec,spi-nor"; -+ compatible = "spi-nand"; - reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; -+ -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch deleted file mode 100644 index ff5521c44..000000000 --- a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_ - static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) - { - struct spinand_device *spinand = nand_to_spinand(nand); -- u8 marker[2] = { }; -+ u8 marker[1] = { }; - struct nand_page_io_req req = { - .pos = *pos, - .ooblen = sizeof(marker), -@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de - - spinand_select_target(spinand, pos->target); - spinand_read_page(spinand, &req); -- if (marker[0] != 0xff || marker[1] != 0xff) -+ if (marker[0] != 0xff) - return true; - - return false; diff --git a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index 82654e683..000000000 --- a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,94 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,27 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@1100e000 { -+ compatible = "mediatek,mt7622-ecc"; -+ reg = <0x1100e000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -255,6 +255,50 @@ - }; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index 134e5997e..000000000 --- a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -539,6 +539,65 @@ - status = "disabled"; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index 8e6935b43..000000000 --- a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -580,7 +580,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -641,5 +641,6 @@ - &wmac { - pinctrl-names = "default"; - pinctrl-0 = <&wmac_pins>; -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 0860a22c3..000000000 --- a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -984,17 +984,15 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; -+ status = "okay"; - }; - - bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 091cffc3c..000000000 --- a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index d1bafc152..000000000 --- a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index f6745add5..000000000 --- a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index b1dd75a41..000000000 --- a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch deleted file mode 100644 index 3452b108f..000000000 --- a/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -157,6 +157,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch deleted file mode 100644 index 9da8ffe32..000000000 --- a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ /dev/null @@ -1,106 +0,0 @@ -From patchwork Tue Apr 26 19:51:36 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 12827872 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF - for ; - Tue, 26 Apr 2022 19:53:05 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: - From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: - Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: - List-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb - x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg - WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9 - QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh - o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k - AZHmXoQxq1mrsm2FxfnQ==; -Received: from localhost ([::1] helo=bombadil.infradead.org) - by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000 -Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000 -Received: from local - by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) - (Exim 4.94.2) (envelope-from ) - id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200 -Date: Tue, 26 Apr 2022 20:51:36 +0100 -From: Daniel Golle -To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, - linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org -Cc: Rob Herring , - Krzysztof Kozlowski , - Matthias Brugger -Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C -X-CRM114-Status: GOOD ( 12.45 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -With the current range specified for the CPU interface there is an -error message at boot: - -GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set - -Setting irqchip.gicv2_force_probe=1 in bootargs results in: - -GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB -GIC: Adjusting CPU interface base to 0x000000001032f000 -GIC: Using split EOI/Deactivate mode - -Using the adjusted CPU interface base and 8K size results in only the -final line remaining and fully working system as well as /proc/interrupts -showing additional IPI3,4,5,6: - -IPI3: 0 0 CPU stop (for crash dump) interrupts -IPI4: 0 0 Timer broadcast interrupts -IPI5: 0 0 IRQ work interrupts -IPI6: 0 0 CPU wake-up interrupts - -Signed-off-by: Daniel Golle ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -344,7 +344,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, -- <0 0x10320000 0 0x1000>, -+ <0 0x1032f000 0 0x2000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; diff --git a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch deleted file mode 100644 index 1cfb53d62..000000000 --- a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 -From: Bruno Umuarama -Date: Thu, 13 Oct 2022 21:18:21 +0000 -Subject: [PATCH] mediatek: mt7623: fix thermal zone -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Raising the temperatures for passive and active trips. @VA1DER -proposed at issue 9396 to remove passive trip. This commit relates to -his suggestion. - -Without this patch. the CPU will be throttled all the way down to 98MHz -if the temperature rises even a degree above the trip point, and it was -further discovered that if the internal temperature of the device is -above the first trip point temperature when it boots then it will start -in a throttled state and even -$ echo disabled > /sys/class/thermal/thermal_zone0/mode -will have no effect. - -The patch increases the passive trip point and active cooling map. The -throttling temperature will then be at 77°C and 82°C, which is still a -low enough temperature for ARM devices to not be in the real danger -zone, and gives some operational headroom. - -Signed-off-by: Bruno Umuarama ---- - arch/arm/boot/dts/mt7623.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -160,13 +160,13 @@ - - trips { - cpu_passive: cpu-passive { -- temperature = <57000>; -+ temperature = <77000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { -- temperature = <67000>; -+ temperature = <82000>; - hysteresis = <2000>; - type = "active"; - }; diff --git a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch deleted file mode 100644 index 161c1e751..000000000 --- a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -68,6 +68,14 @@ - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch deleted file mode 100644 index 336920baf..000000000 --- a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ /dev/null @@ -1,196 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -23,6 +23,10 @@ - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; -+ led-boot = &green_led; -+ led-failsafe = &green_led; -+ led-running = &green_led; -+ led-upgrade = &blue_led; - }; - - chosen { -@@ -419,27 +423,27 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port5: port@5 { - reg = <5>; -- label = "lan4"; -+ label = "sfp2"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; -@@ -490,9 +494,137 @@ - - &wifi { - status = "okay"; -- pinctrl-names = "default", "dbdc"; -+ pinctrl-names = "default"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 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0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - - led { - led-active-low; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -55,6 +55,7 @@ - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; -+ compatible = "denx,fit"; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index 6347533aa..000000000 --- a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -17,6 +17,8 @@ - #include - #include - #include -+#include -+#include - - #include "phy-mtk-io.h" - -@@ -264,6 +266,9 @@ - - #define TPHY_CLKS_CNT 2 - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -331,6 +336,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, - P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, - FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | -@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_coef); - } - -+ if (of_find_property(np, "mediatek,phy-switch", NULL)) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch b/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch deleted file mode 100644 index 3e16a533e..000000000 --- a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch +++ /dev/null @@ -1,88 +0,0 @@ -From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sat, 8 Oct 2022 18:48:06 +0200 -Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts - separately - -Some mt7986 boards use uart rts/cts pins as gpio, -This patch allows to change rts/cts to gpio mode, but keep -rx/tx as UART function. - -Signed-off-by: Frank Wunderlich -Signed-off-by: Sam Shih -Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++----- - 1 file changed, 25 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4, - static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; - static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; -+static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; -+static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; - --static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; -+static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; -+static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; -+ -+static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; -+static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; -+ -+static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; -+static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; - - static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; - static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; -@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = { - static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; - static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; - -+static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; -+static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; -+ -+static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; -+static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; -+ - static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; - static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; - -@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr - PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), - PINCTRL_PIN_GROUP("i2c", mt7986_i2c), - PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), -+ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), - PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), - PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), - PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), -@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr - PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), - PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), - PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), -- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), -- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), -+ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), -+ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), -+ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), - PINCTRL_PIN_GROUP("spi0", mt7986_spi0), - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), - PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), -@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] = - static const char *mt7986_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; - static const char *mt7986_uart_groups[] = { -- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", -+ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", -+ "uart1_2_rx_tx", "uart1_2_cts_rts", -+ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", - "uart2_0", "uart2_1", "uart0", "uart1", "uart2", - }; - static const char *mt7986_wdt_groups[] = { "watchdog", }; diff --git a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch b/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch deleted file mode 100644 index 47ded1aeb..000000000 --- a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:13 +0100 -Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek - MT7986 SoC - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -add SoC specify 'pull_type' attribute for bias configuration. - -This patch add pull_type attribute to pinctrl-mt7986.c, and make -bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), - }; - -+static const unsigned int mt7986_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -+ MTK_PULL_PU_PD_TYPE,/*100*/ -+}; -+ - static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), -@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, -@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, diff --git a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch deleted file mode 100644 index 46dfa24b7..000000000 --- a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch +++ /dev/null @@ -1,1094 +0,0 @@ -From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 00:34:56 +0000 -Subject: [PATCH] pinctrl: add mt7981 pinctrl driver - -Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver -which can also be found the SDK. - -Signed-off-by: Daniel Golle -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 5 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++ - 3 files changed, 1054 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -127,6 +127,11 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7981 -+ bool "Mediatek MT7981 pin control" -+ depends on OF -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT7986 - bool "Mediatek MT7986 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -0,0 +1,1048 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7981 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include "pinctrl-moore.h" -+ -+#define MT7981_PIN(_number, _name) \ -+ MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { -+ PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { -+ PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { -+ PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { -+ PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), -+ -+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), -+}; -+ -+static const unsigned int mt7981_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -+ MTK_PULL_PU_PD_TYPE,/*100*/ -+}; -+ -+static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7981_pins[] = { -+ MT7981_PIN(0, "GPIO_WPS"), -+ MT7981_PIN(1, "GPIO_RESET"), -+ MT7981_PIN(2, "SYS_WATCHDOG"), -+ MT7981_PIN(3, "PCIE_PERESET_N"), -+ MT7981_PIN(4, "JTAG_JTDO"), -+ MT7981_PIN(5, "JTAG_JTDI"), -+ MT7981_PIN(6, "JTAG_JTMS"), -+ MT7981_PIN(7, "JTAG_JTCLK"), -+ MT7981_PIN(8, "JTAG_JTRST_N"), -+ MT7981_PIN(9, "WO_JTAG_JTDO"), -+ MT7981_PIN(10, "WO_JTAG_JTDI"), -+ MT7981_PIN(11, "WO_JTAG_JTMS"), -+ MT7981_PIN(12, "WO_JTAG_JTCLK"), -+ MT7981_PIN(13, "WO_JTAG_JTRST_N"), -+ MT7981_PIN(14, "USB_VBUS"), -+ MT7981_PIN(15, "PWM0"), -+ MT7981_PIN(16, "SPI0_CLK"), -+ MT7981_PIN(17, "SPI0_MOSI"), -+ MT7981_PIN(18, "SPI0_MISO"), -+ MT7981_PIN(19, "SPI0_CS"), -+ MT7981_PIN(20, "SPI0_HOLD"), -+ MT7981_PIN(21, "SPI0_WP"), -+ MT7981_PIN(22, "SPI1_CLK"), -+ MT7981_PIN(23, "SPI1_MOSI"), -+ MT7981_PIN(24, "SPI1_MISO"), -+ MT7981_PIN(25, "SPI1_CS"), -+ MT7981_PIN(26, "SPI2_CLK"), -+ MT7981_PIN(27, "SPI2_MOSI"), -+ MT7981_PIN(28, "SPI2_MISO"), -+ MT7981_PIN(29, "SPI2_CS"), -+ MT7981_PIN(30, "SPI2_HOLD"), -+ MT7981_PIN(31, "SPI2_WP"), -+ MT7981_PIN(32, "UART0_RXD"), -+ MT7981_PIN(33, "UART0_TXD"), -+ MT7981_PIN(34, "PCIE_CLK_REQ"), -+ MT7981_PIN(35, "PCIE_WAKE_N"), -+ MT7981_PIN(36, "SMI_MDC"), -+ MT7981_PIN(37, "SMI_MDIO"), -+ MT7981_PIN(38, "GBE_INT"), -+ MT7981_PIN(39, "GBE_RESET"), -+ MT7981_PIN(40, "WF_DIG_RESETB"), -+ MT7981_PIN(41, "WF_CBA_RESETB"), -+ MT7981_PIN(42, "WF_XO_REQ"), -+ MT7981_PIN(43, "WF_TOP_CLK"), -+ MT7981_PIN(44, "WF_TOP_DATA"), -+ MT7981_PIN(45, "WF_HB1"), -+ MT7981_PIN(46, "WF_HB2"), -+ MT7981_PIN(47, "WF_HB3"), -+ MT7981_PIN(48, "WF_HB4"), -+ MT7981_PIN(49, "WF_HB0"), -+ MT7981_PIN(50, "WF_HB0_B"), -+ MT7981_PIN(51, "WF_HB5"), -+ MT7981_PIN(52, "WF_HB6"), -+ MT7981_PIN(53, "WF_HB7"), -+ MT7981_PIN(54, "WF_HB8"), -+ MT7981_PIN(55, "WF_HB9"), -+ MT7981_PIN(56, "WF_HB10"), -+}; -+ -+/* List all groups consisting of these pins dedicated to the enablement of -+ * certain hardware block and the corresponding mode for all of the pins. -+ * The hardware probably has multiple combinations of these pinouts. -+ */ -+ -+/* WA_AICE */ -+static int mt7981_wa_aice1_pins[] = { 0, 1, }; -+static int mt7981_wa_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wa_aice2_pins[] = { 0, 1, }; -+static int mt7981_wa_aice2_funcs[] = { 3, 3, }; -+ -+static int mt7981_wa_aice3_pins[] = { 28, 29, }; -+static int mt7981_wa_aice3_funcs[] = { 3, 3, }; -+ -+static int mt7981_wm_aice1_pins[] = { 9, 10, }; -+static int mt7981_wm_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wm_aice2_pins[] = { 30, 31, }; -+static int mt7981_wm_aice2_funcs[] = { 5, 5, }; -+ -+/* WM_UART */ -+static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -+static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; -+ -+static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -+static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -+static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; -+ -+/* DFD */ -+static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -+static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; -+ -+/* SYS_WATCHDOG */ -+static int mt7981_watchdog_pins[] = { 2, }; -+static int mt7981_watchdog_funcs[] = { 1, }; -+ -+static int mt7981_watchdog1_pins[] = { 13, }; -+static int mt7981_watchdog1_funcs[] = { 5, }; -+ -+/* PCIE_PERESET_N */ -+static int mt7981_pcie_pereset_pins[] = { 3, }; -+static int mt7981_pcie_pereset_funcs[] = { 1, }; -+ -+/* JTAG */ -+static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+/* WM_JTAG */ -+static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; -+ -+static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -+static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* WO0_JTAG */ -+static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -+static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* UART2 */ -+static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; -+ -+/* GBE_LED0 */ -+static int mt7981_gbe_led0_pins[] = { 8, }; -+static int mt7981_gbe_led0_funcs[] = { 3, }; -+ -+/* PTA_EXT */ -+static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -+static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; -+ -+static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -+static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; -+ -+/* PWM2 */ -+static int mt7981_pwm2_pins[] = { 7, }; -+static int mt7981_pwm2_funcs[] = { 4, }; -+ -+/* NET_WO0_UART_TXD */ -+static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -+static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; -+ -+static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -+static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; -+ -+static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -+static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; -+ -+/* I2C */ -+static int mt7981_i2c0_0_pins[] = { 6, 7, }; -+static int mt7981_i2c0_0_funcs[] = { 6, 6, }; -+ -+static int mt7981_i2c0_1_pins[] = { 30, 31, }; -+static int mt7981_i2c0_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_i2c0_2_pins[] = { 36, 37, }; -+static int mt7981_i2c0_2_funcs[] = { 2, 2, }; -+ -+static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -+static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; -+ -+static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; -+ -+static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; -+ -+static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; -+ -+/* DFD_NTRST */ -+static int mt7981_dfd_ntrst_pins[] = { 8, }; -+static int mt7981_dfd_ntrst_funcs[] = { 6, }; -+ -+/* PWM0 */ -+static int mt7981_pwm0_0_pins[] = { 13, }; -+static int mt7981_pwm0_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm0_1_pins[] = { 15, }; -+static int mt7981_pwm0_1_funcs[] = { 1, }; -+ -+/* PWM1 */ -+static int mt7981_pwm1_0_pins[] = { 14, }; -+static int mt7981_pwm1_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm1_1_pins[] = { 15, }; -+static int mt7981_pwm1_1_funcs[] = { 3, }; -+ -+/* GBE_LED1 */ -+static int mt7981_gbe_led1_pins[] = { 13, }; -+static int mt7981_gbe_led1_funcs[] = { 3, }; -+ -+/* PCM */ -+static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -+static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; -+ -+/* UDI */ -+static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; -+ -+/* DRV_VBUS */ -+static int mt7981_drv_vbus_pins[] = { 14, }; -+static int mt7981_drv_vbus_funcs[] = { 1, }; -+ -+/* EMMC */ -+static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ -+/* SNFI */ -+static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -+static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -+static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -+static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; -+ -+/* UART1 */ -+static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; -+ -+/* UART2 */ -+static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+ -+/* UART0 */ -+static int mt7981_uart0_pins[] = { 32, 33, }; -+static int mt7981_uart0_funcs[] = { 1, 1, }; -+ -+/* PCIE_CLK_REQ */ -+static int mt7981_pcie_clk_pins[] = { 34, }; -+static int mt7981_pcie_clk_funcs[] = { 2, }; -+ -+/* PCIE_WAKE_N */ -+static int mt7981_pcie_wake_pins[] = { 35, }; -+static int mt7981_pcie_wake_funcs[] = { 2, }; -+ -+/* MDC_MDIO */ -+static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; -+ -+static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; -+ -+/* WF0_MODE1 */ -+static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; -+static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; -+ -+/* WF0_MODE3 */ -+static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -+static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+/* WF2G_LED */ -+static int mt7981_wf2g_led0_pins[] = { 30, }; -+static int mt7981_wf2g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf2g_led1_pins[] = { 34, }; -+static int mt7981_wf2g_led1_funcs[] = { 1, }; -+ -+/* WF5G_LED */ -+static int mt7981_wf5g_led0_pins[] = { 31, }; -+static int mt7981_wf5g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf5g_led1_pins[] = { 35, }; -+static int mt7981_wf5g_led1_funcs[] = { 1, }; -+ -+/* MT7531_INT */ -+static int mt7981_mt7531_int_pins[] = { 38, }; -+static int mt7981_mt7531_int_funcs[] = { 1, }; -+ -+/* ANT_SEL */ -+static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -+static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; -+ -+static const struct group_desc mt7981_groups[] = { -+ /* @GPIO(0,1): WA_AICE(2) */ -+ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), -+ /* @GPIO(0,1): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), -+ /* @GPIO(0,1): WM_UART(5) */ -+ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), -+ /* @GPIO(0,1,4,5): DFD(6) */ -+ PINCTRL_PIN_GROUP("dfd", mt7981_dfd), -+ /* @GPIO(2): SYS_WATCHDOG(1) */ -+ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), -+ /* @GPIO(3): PCIE_PERESET_N(1) */ -+ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), -+ /* @GPIO(4,8) JTAG(1) */ -+ PINCTRL_PIN_GROUP("jtag", mt7981_jtag), -+ /* @GPIO(4,8) WM_JTAG(2) */ -+ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), -+ /* @GPIO(9,13) WO0_JTAG(1) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), -+ /* @GPIO(4,7) WM_JTAG(3) */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(8) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), -+ /* @GPIO(4,6) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), -+ /* @GPIO(7) PWM2(4) */ -+ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), -+ /* @GPIO(8) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), -+ /* @GPIO(4,7) SPI1(5) */ -+ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), -+ /* @GPIO(6,7) I2C(5) */ -+ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), -+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ -+ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), -+ /* @GPIO(9,10): WM_AICE(2) */ -+ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), -+ /* @GPIO(13): PWM0(2) */ -+ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), -+ /* @GPIO(15): PWM0(1) */ -+ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), -+ /* @GPIO(14): PWM1(2) */ -+ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), -+ /* @GPIO(15): PWM1(3) */ -+ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), -+ /* @GPIO(14) NET_WO0_UART_TXD(3) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), -+ /* @GPIO(15) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), -+ /* @GPIO(13) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), -+ /* @GPIO(9,13) PCM(4) */ -+ PINCTRL_PIN_GROUP("pcm", mt7981_pcm), -+ /* @GPIO(13): SYS_WATCHDOG1(5) */ -+ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), -+ /* @GPIO(9,13) UDI(4) */ -+ PINCTRL_PIN_GROUP("udi", mt7981_udi), -+ /* @GPIO(14) DRV_VBUS(1) */ -+ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15,25): EMMC(2) */ -+ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), -+ /* @GPIO(16,21): SNFI(3) */ -+ PINCTRL_PIN_GROUP("snfi", mt7981_snfi), -+ /* @GPIO(16,19): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0", mt7981_spi0), -+ /* @GPIO(20,21): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), -+ /* @GPIO(22,25) SPI1(1) */ -+ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), -+ /* @GPIO(26,29): SPI2(1) */ -+ PINCTRL_PIN_GROUP("spi2", mt7981_spi2), -+ /* @GPIO(30,31): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), -+ /* @GPIO(16,19): UART1(4) */ -+ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), -+ /* @GPIO(26,29): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(22,25): UART1(3) */ -+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), -+ /* @GPIO(22,24) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), -+ /* @GPIO(20,21): WM_UART(4) */ -+ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), -+ /* @GPIO(30,31): WM_UART(3) */ -+ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), -+ /* @GPIO(20,24) WM_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), -+ /* @GPIO(25,29) WO0_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), -+ /* @GPIO(28,29): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), -+ /* @GPIO(30,31): WM_AICE(5) */ -+ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), -+ /* @GPIO(30,31): I2C(4) */ -+ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), -+ /* @GPIO(30,31): I2C(6) */ -+ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), -+ /* @GPIO(32,33): I2C(1) */ -+ PINCTRL_PIN_GROUP("uart0", mt7981_uart0), -+ /* @GPIO(32,33): I2C(2) */ -+ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), -+ /* @GPIO(32,33): I2C(3) */ -+ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), -+ /* @GPIO(32,33): I2C(5) */ -+ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), -+ /* @GPIO(34): PCIE_CLK_REQ(2) */ -+ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), -+ /* @GPIO(35): PCIE_WAKE_N(2) */ -+ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), -+ /* @GPIO(36,37): I2C(2) */ -+ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), -+ /* @GPIO(36,37): MDC_MDIO(1) */ -+ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), -+ /* @GPIO(36,37): MDC_MDIO(3) */ -+ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), -+ /* @GPIO(69,85): WF0_MODE1(1) */ -+ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), -+ /* @GPIO(74,80): WF0_MODE3(3) */ -+ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), -+ /* @GPIO(30): WF2G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), -+ /* @GPIO(34): WF2G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), -+ /* @GPIO(31): WF5G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), -+ /* @GPIO(35): WF5G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), -+ /* @GPIO(38): MT7531_INT(1) */ -+ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), -+ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ -+ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", -+ "wa_aice3", "wm_aice1_2", }; -+static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -+ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -+ "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; -+static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; -+static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; -+static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", -+ "wo0_jtag_1", "wm_jtag_1", }; -+static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", -+ "wf2g_led1", "wf5g_led0", "wf5g_led1", }; -+static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; -+static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", -+ "pwm1_0", "pwm1_1", }; -+static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", -+ "spi2_wp_hold", }; -+static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", -+ "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; -+static const char *mt7981_pcm_groups[] = { "pcm", }; -+static const char *mt7981_udi_groups[] = { "udi", }; -+static const char *mt7981_usb_groups[] = { "drv_vbus", }; -+static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", -+ "wf0_mode1", "wf0_mode3", "mt7531_int", }; -+static const char *mt7981_ant_groups[] = { "ant_sel", }; -+ -+static const struct function_desc mt7981_functions[] = { -+ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, -+ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, -+ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, -+ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, -+ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, -+ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, -+ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, -+ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, -+ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, -+ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, -+ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, -+ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, -+ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, -+ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, -+ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, -+ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, -+ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, -+}; -+ -+static const struct mtk_eint_hw mt7981_eint_hw = { -+ .port_mask = 7, -+ .ports = 7, -+ .ap_num = ARRAY_SIZE(mt7981_pins), -+ .db_cnt = 16, -+}; -+ -+static const char * const mt7981_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", -+ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", -+}; -+ -+static struct mtk_pin_soc mt7981_data = { -+ .reg_cal = mt7981_reg_cals, -+ .pins = mt7981_pins, -+ .npins = ARRAY_SIZE(mt7981_pins), -+ .grps = mt7981_groups, -+ .ngrps = ARRAY_SIZE(mt7981_groups), -+ .funcs = mt7981_functions, -+ .nfuncs = ARRAY_SIZE(mt7981_functions), -+ .eint_hw = &mt7981_eint_hw, -+ .gpio_m = 0, -+ .ies_present = false, -+ .base_names = mt7981_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), -+ .pull_type = mt7981_pull_type, -+ .bias_set_combo = mtk_pinconf_bias_set_combo, -+ .bias_get_combo = mtk_pinconf_bias_get_combo, -+ .drive_set = mtk_pinconf_drive_set_rev1, -+ .drive_get = mtk_pinconf_drive_get_rev1, -+ .adv_pull_get = mtk_pinconf_adv_pull_get, -+ .adv_pull_set = mtk_pinconf_adv_pull_set, -+}; -+ -+static const struct of_device_id mt7981_pinctrl_of_match[] = { -+ { .compatible = "mediatek,mt7981-pinctrl", }, -+ {} -+}; -+ -+static int mt7981_pinctrl_probe(struct platform_device *pdev) -+{ -+ return mtk_moore_pinctrl_probe(pdev, &mt7981_data); -+} -+ -+static struct platform_driver mt7981_pinctrl_driver = { -+ .driver = { -+ .name = "mt7981-pinctrl", -+ .of_match_table = mt7981_pinctrl_of_match, -+ }, -+ .probe = mt7981_pinctrl_probe, -+}; -+ -+static int __init mt7981_pinctrl_init(void) -+{ -+ return platform_driver_register(&mt7981_pinctrl_driver); -+} -+arch_initcall(mt7981_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch b/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch deleted file mode 100644 index 995e0dc7e..000000000 --- a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sat, 18 Feb 2023 09:51:06 +0300 -Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are options missing from PINCTRL_MT7981 whilst being on every other -pin controller. Add them. - -Signed-off-by: Arınç ÜNAL -Acked-by: Daniel Golle -Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -130,6 +130,8 @@ config PINCTRL_MT7622 - config PINCTRL_MT7981 - bool "Mediatek MT7981 pin control" - depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - - config PINCTRL_MT7986 diff --git a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch b/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch deleted file mode 100644 index db2561695..000000000 --- a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 18 Aug 2023 04:02:35 +0100 -Subject: [PATCH] pinctrl: mediatek: fix pull_type data for MT7981 - -MediaTek has released pull_type data for MT7981 in their SDK. -Use it and set functions to configure pin bias. - -Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++---------------- - 1 file changed, 13 insertions(+), 31 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_ty - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -- MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -- MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -- MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -- MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -- MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -- MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -- MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -- MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -- MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -- MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -- MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -- MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -- MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -- MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -- MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -- MTK_PULL_PU_PD_TYPE,/*100*/ -+ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ -+ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ -+ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ -+ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ -+ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ -+ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ -+ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ -+ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ -+ MTK_PULL_PU_PD_TYPE,/*56*/ - }; - - static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { -@@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data = - .ies_present = false, - .base_names = mt7981_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7981_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch b/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch deleted file mode 100644 index d2f055836..000000000 --- a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 26 Aug 2023 21:06:14 +0100 -Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups - -Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups. - -Signed-off-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++--- - 1 file changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { - static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; - static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - -+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; -+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; -+ - /* GBE_LED0 */ - static int mt7981_gbe_led0_pins[] = { 8, }; - static int mt7981_gbe_led0_funcs[] = { 3, }; -@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, - static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; - static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - -+static int mt7981_uart1_2_pins[] = { 9, 10, }; -+static int mt7981_uart1_2_funcs[] = { 2, 2, }; -+ - /* UART2 */ - static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; - static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), - /* @GPIO(4,7) WM_JTAG(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(4,5) WM_JTAG(4) */ -+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), - /* @GPIO(8) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), - /* @GPIO(4,6) PTA_EXT(4) */ -@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), - /* @GPIO(26,29): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(9,10): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ -@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr - */ - static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; --static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", -+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", -+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; - static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; - static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; - static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; diff --git a/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch b/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch deleted file mode 100644 index 7992a0267..000000000 --- a/target/linux/mediatek/patches-6.1/219-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 18 Aug 2023 04:03:26 +0100 -Subject: [PATCH] pinctrl: mediatek: assign functions to configure pin bias on - MT7986 - -Assign bias_disable_get/set and bias_get/set functions to allow -configuring pin bias on MT7986. - -Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, -@@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch b/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch deleted file mode 100644 index c7f37718a..000000000 --- a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch +++ /dev/null @@ -1,140 +0,0 @@ -From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:34 +0100 -Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where - possible - -Take a pointer to a struct device in mtk_clk_register_cpumuxes() and -propagate the same to mtk_clk_register_cpumux() => clk_hw_register(). -Even though runtime pm is unlikely to be used with CPU muxes, this -helps with code consistency and possibly opens to commonization of -some mtk_clk_register_(x) functions. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Markus Schneider-Pargmann -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-cpumux.c | 8 ++++---- - drivers/clk/mediatek/clk-cpumux.h | 2 +- - drivers/clk/mediatek/clk-mt2701.c | 2 +- - drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- - drivers/clk/mediatek/clk-mt7622.c | 4 ++-- - drivers/clk/mediatek/clk-mt7629.c | 4 ++-- - drivers/clk/mediatek/clk-mt8173.c | 4 ++-- - 7 files changed, 14 insertions(+), 13 deletions(-) - ---- a/drivers/clk/mediatek/clk-cpumux.c -+++ b/drivers/clk/mediatek/clk-cpumux.c -@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o - }; - - static struct clk_hw * --mtk_clk_register_cpumux(const struct mtk_composite *mux, -+mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux, - struct regmap *regmap) - { - struct mtk_clk_cpumux *cpumux; -@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk - cpumux->regmap = regmap; - cpumux->hw.init = &init; - -- ret = clk_hw_register(NULL, &cpumux->hw); -+ ret = clk_hw_register(dev, &cpumux->hw); - if (ret) { - kfree(cpumux); - return ERR_PTR(ret); -@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st - kfree(cpumux); - } - --int mtk_clk_register_cpumuxes(struct device_node *node, -+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, - const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data) - { -@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev - continue; - } - -- hw = mtk_clk_register_cpumux(mux, regmap); -+ hw = mtk_clk_register_cpumux(dev, mux, regmap); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mux->name, - hw); ---- a/drivers/clk/mediatek/clk-cpumux.h -+++ b/drivers/clk/mediatek/clk-cpumux.h -@@ -11,7 +11,7 @@ struct clk_hw_onecell_data; - struct device_node; - struct mtk_composite; - --int mtk_clk_register_cpumuxes(struct device_node *node, -+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, - const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data); - ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -762,7 +762,7 @@ static void __init mtk_infrasys_init_ear - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - -- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), -+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - infra_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, ---- a/drivers/clk/mediatek/clk-mt6795-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c -@@ -106,7 +106,8 @@ static int clk_mt6795_infracfg_probe(str - if (ret) - goto free_clk_data; - -- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); -+ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, -+ ARRAY_SIZE(cpu_muxes), clk_data); - if (ret) - goto unregister_gates; - ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -639,8 +639,8 @@ static int mtk_infrasys_init(struct plat - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - -- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, -+ ARRAY_SIZE(infra_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -589,8 +589,8 @@ static int mtk_infrasys_init(struct plat - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - -- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, -+ ARRAY_SIZE(infra_muxes), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); ---- a/drivers/clk/mediatek/clk-mt8173.c -+++ b/drivers/clk/mediatek/clk-mt8173.c -@@ -893,8 +893,8 @@ static void __init mtk_infrasys_init(str - ARRAY_SIZE(infra_clks), clk_data); - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - -- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, -+ ARRAY_SIZE(cpu_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) diff --git a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch b/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch deleted file mode 100644 index c7de44fcf..000000000 --- a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch +++ /dev/null @@ -1,74 +0,0 @@ -From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:37 +0100 -Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops - -In order to migrate some (few) old clock drivers to the common -mtk_clk_simple_probe() function, add dummy clock ops to be able -to insert a dummy clock with ID 0 at the beginning of the list. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++ - drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ - 2 files changed, 35 insertions(+) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -21,6 +21,22 @@ - #include "clk-gate.h" - #include "clk-mux.h" - -+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; -+EXPORT_SYMBOL_GPL(cg_regs_dummy); -+ -+static int mtk_clk_dummy_enable(struct clk_hw *hw) -+{ -+ return 0; -+} -+ -+static void mtk_clk_dummy_disable(struct clk_hw *hw) { } -+ -+const struct clk_ops mtk_clk_dummy_ops = { -+ .enable = mtk_clk_dummy_enable, -+ .disable = mtk_clk_dummy_disable, -+}; -+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); -+ - static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, - unsigned int clk_num) - { ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -22,6 +22,25 @@ - - struct platform_device; - -+/* -+ * We need the clock IDs to start from zero but to maintain devicetree -+ * backwards compatibility we can't change bindings to start from zero. -+ * Only a few platforms are affected, so we solve issues given by the -+ * commonized MTK clocks probe function(s) by adding a dummy clock at -+ * the beginning where needed. -+ */ -+#define CLK_DUMMY 0 -+ -+extern const struct clk_ops mtk_clk_dummy_ops; -+extern const struct mtk_gate_regs cg_regs_dummy; -+ -+#define GATE_DUMMY(_id, _name) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .regs = &cg_regs_dummy, \ -+ .ops = &mtk_clk_dummy_ops, \ -+ } -+ - struct mtk_fixed_clk { - int id; - const char *name; diff --git a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch b/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch deleted file mode 100644 index becfcd0ed..000000000 --- a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch +++ /dev/null @@ -1,790 +0,0 @@ -From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:41 +0100 -Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where - possible - -mtk_clk_simple_probe() is a function that registers mtk gate clocks -and, if reset data is present, a reset controller and across all of -the MTK clock drivers, such a function is duplicated many times: -switch to the common mtk_clk_simple_probe() function for all of the -clock drivers that are registering as platform drivers. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: removed parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++---- - drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++-------- - drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++-------------- - drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++-------- - drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++---------------- - drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++----------- - drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++--------------------- - drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++---------------------- - drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++---------------------- - 9 files changed, 144 insertions(+), 406 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt2701-aud.c -+++ b/drivers/clk/mediatek/clk-mt2701-aud.c -@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3 - }; - - static const struct mtk_gate audio_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "aud_dummy"), - /* AUDIO0 */ - GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), - GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), -@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[ - GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), - }; - -+static const struct mtk_clk_desc audio_desc = { -+ .clks = audio_clks, -+ .num_clks = ARRAY_SIZE(audio_clks), -+}; -+ - static const struct of_device_id of_match_clk_mt2701_aud[] = { -- { .compatible = "mediatek,mt2701-audsys", }, -- {} -+ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, -+ { /* sentinel */ } - }; - - static int clk_mt2701_aud_probe(struct platform_device *pdev) - { -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; - int r; - -- clk_data = mtk_alloc_clk_data(CLK_AUD_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, audio_clks, -- ARRAY_SIZE(audio_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ r = mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - -- goto err_clk_provider; -+ return r; - } - - r = devm_of_platform_populate(&pdev->dev); -@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p - return 0; - - err_plat_populate: -- of_clk_del_provider(node); --err_clk_provider: -+ mtk_clk_simple_remove(pdev); - return r; - } - -+static int clk_mt2701_aud_remove(struct platform_device *pdev) -+{ -+ of_platform_depopulate(&pdev->dev); -+ return mtk_clk_simple_remove(pdev); -+} -+ - static struct platform_driver clk_mt2701_aud_drv = { - .probe = clk_mt2701_aud_probe, -+ .remove = clk_mt2701_aud_remove, - .driver = { - .name = "clk-mt2701-aud", - .of_match_table = of_match_clk_mt2701_aud, ---- a/drivers/clk/mediatek/clk-mt2701-eth.c -+++ b/drivers/clk/mediatek/clk-mt2701-eth.c -@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg - GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - - static const struct mtk_gate eth_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "eth_dummy"), - GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), - GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), - GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), -@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static const struct of_device_id of_match_clk_mt2701_eth[] = { -- { .compatible = "mediatek,mt2701-ethsys", }, -- {} -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+ .rst_desc = &clk_rst_desc, - }; - --static int clk_mt2701_eth_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, eth_clks, -- ARRAY_SIZE(eth_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -+static const struct of_device_id of_match_clk_mt2701_eth[] = { -+ { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, -+ { /* sentinel */ } -+}; - - static struct platform_driver clk_mt2701_eth_drv = { -- .probe = clk_mt2701_eth_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-eth", - .of_match_table = of_match_clk_mt2701_eth, ---- a/drivers/clk/mediatek/clk-mt2701-g3d.c -+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c -@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg - }; - - static const struct mtk_gate g3d_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), - GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), - }; - -@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt2701_g3dsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), -- clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -+static const struct mtk_clk_desc g3d_desc = { -+ .clks = g3d_clks, -+ .num_clks = ARRAY_SIZE(g3d_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt2701_g3d[] = { -- { -- .compatible = "mediatek,mt2701-g3dsys", -- .data = clk_mt2701_g3dsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt2701_g3d_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt2701_g3d_drv = { -- .probe = clk_mt2701_g3d_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-g3d", - .of_match_table = of_match_clk_mt2701_g3d, ---- a/drivers/clk/mediatek/clk-mt2701-hif.c -+++ b/drivers/clk/mediatek/clk-mt2701-hif.c -@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg - GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - - static const struct mtk_gate hif_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "hif_dummy"), - GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), - GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), - GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), -@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static const struct of_device_id of_match_clk_mt2701_hif[] = { -- { .compatible = "mediatek,mt2701-hifsys", }, -- {} -+static const struct mtk_clk_desc hif_desc = { -+ .clks = hif_clks, -+ .num_clks = ARRAY_SIZE(hif_clks), -+ .rst_desc = &clk_rst_desc, - }; - --static int clk_mt2701_hif_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, hif_clks, -- ARRAY_SIZE(hif_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) { -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- return r; -- } -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return 0; --} -+static const struct of_device_id of_match_clk_mt2701_hif[] = { -+ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, -+ { /* sentinel */ } -+}; - - static struct platform_driver clk_mt2701_hif_drv = { -- .probe = clk_mt2701_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-hif", - .of_match_table = of_match_clk_mt2701_hif, ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p - return r; - } - --static int clk_mt2712_infra_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, infra_clks, -- ARRAY_SIZE(infra_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r != 0) -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); -- -- return r; --} -- --static int clk_mt2712_peri_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, peri_clks, -- ARRAY_SIZE(peri_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r != 0) -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); -- -- return r; --} -- - static int clk_mt2712_mcu_probe(struct platform_device *pdev) - { - struct clk_hw_onecell_data *clk_data; -@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc - .compatible = "mediatek,mt2712-topckgen", - .data = clk_mt2712_top_probe, - }, { -- .compatible = "mediatek,mt2712-infracfg", -- .data = clk_mt2712_infra_probe, -- }, { -- .compatible = "mediatek,mt2712-pericfg", -- .data = clk_mt2712_peri_probe, -- }, { - .compatible = "mediatek,mt2712-mcucfg", - .data = clk_mt2712_mcu_probe, - }, { -@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf - return r; - } - -+static const struct mtk_clk_desc infra_desc = { -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .rst_desc = &clk_rst_desc[0], -+}; -+ -+static const struct mtk_clk_desc peri_desc = { -+ .clks = peri_clks, -+ .num_clks = ARRAY_SIZE(peri_clks), -+ .rst_desc = &clk_rst_desc[1], -+}; -+ -+static const struct of_device_id of_match_clk_mt2712_simple[] = { -+ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, -+ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt2712_simple_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt2712-simple", -+ .of_match_table = of_match_clk_mt2712_simple, -+ }, -+}; -+ - static struct platform_driver clk_mt2712_drv = { - .probe = clk_mt2712_probe, - .driver = { -@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712 - - static int __init clk_mt2712_init(void) - { -- return platform_driver_register(&clk_mt2712_drv); -+ int ret = platform_driver_register(&clk_mt2712_drv); -+ -+ if (ret) -+ return ret; -+ return platform_driver_register(&clk_mt2712_simple_drv); - } - - arch_initcall(clk_mt2712_init); ---- a/drivers/clk/mediatek/clk-mt7622-aud.c -+++ b/drivers/clk/mediatek/clk-mt7622-aud.c -@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[ - GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), - }; - --static int clk_mt7622_audiosys_init(struct platform_device *pdev) -+static const struct mtk_clk_desc audio_desc = { -+ .clks = audio_clks, -+ .num_clks = ARRAY_SIZE(audio_clks), -+}; -+ -+static int clk_mt7622_aud_probe(struct platform_device *pdev) - { -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; - int r; - -- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, audio_clks, -- ARRAY_SIZE(audio_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ r = mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - -- goto err_clk_provider; -+ return r; - } - - r = devm_of_platform_populate(&pdev->dev); -@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru - return 0; - - err_plat_populate: -- of_clk_del_provider(node); --err_clk_provider: -+ mtk_clk_simple_remove(pdev); - return r; - } - --static const struct of_device_id of_match_clk_mt7622_aud[] = { -- { -- .compatible = "mediatek,mt7622-audsys", -- .data = clk_mt7622_audiosys_init, -- }, { -- /* sentinel */ -- } --}; -- --static int clk_mt7622_aud_probe(struct platform_device *pdev) -+static int clk_mt7622_aud_remove(struct platform_device *pdev) - { -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; -+ of_platform_depopulate(&pdev->dev); -+ return mtk_clk_simple_remove(pdev); - } - -+static const struct of_device_id of_match_clk_mt7622_aud[] = { -+ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, -+ { /* sentinel */ } -+}; -+ - static struct platform_driver clk_mt7622_aud_drv = { - .probe = clk_mt7622_aud_probe, -+ .remove = clk_mt7622_aud_remove, - .driver = { - .name = "clk-mt7622-aud", - .of_match_table = of_match_clk_mt7622_aud, ---- a/drivers/clk/mediatek/clk-mt7622-eth.c -+++ b/drivers/clk/mediatek/clk-mt7622-eth.c -@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7622_ethsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, eth_clks, -- ARRAY_SIZE(eth_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, -- ARRAY_SIZE(sgmii_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc sgmii_desc = { -+ .clks = sgmii_clks, -+ .num_clks = ARRAY_SIZE(sgmii_clks), -+}; - - static const struct of_device_id of_match_clk_mt7622_eth[] = { -- { -- .compatible = "mediatek,mt7622-ethsys", -- .data = clk_mt7622_ethsys_init, -- }, { -- .compatible = "mediatek,mt7622-sgmiisys", -- .data = clk_mt7622_sgmiisys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, -+ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7622_eth_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7622_eth_drv = { -- .probe = clk_mt7622_eth_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7622-eth", - .of_match_table = of_match_clk_mt7622_eth, ---- a/drivers/clk/mediatek/clk-mt7622-hif.c -+++ b/drivers/clk/mediatek/clk-mt7622-hif.c -@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -- ARRAY_SIZE(ssusb_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7622_pciesys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -- ARRAY_SIZE(pcie_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -+static const struct mtk_clk_desc ssusb_desc = { -+ .clks = ssusb_clks, -+ .num_clks = ARRAY_SIZE(ssusb_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc pcie_desc = { -+ .clks = pcie_clks, -+ .num_clks = ARRAY_SIZE(pcie_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt7622_hif[] = { -- { -- .compatible = "mediatek,mt7622-pciesys", -- .data = clk_mt7622_pciesys_init, -- }, { -- .compatible = "mediatek,mt7622-ssusbsys", -- .data = clk_mt7622_ssusbsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, -+ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7622_hif_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7622_hif_drv = { -- .probe = clk_mt7622_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7622-hif", - .of_match_table = of_match_clk_mt7622_hif, ---- a/drivers/clk/mediatek/clk-mt7629-hif.c -+++ b/drivers/clk/mediatek/clk-mt7629-hif.c -@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -- ARRAY_SIZE(ssusb_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7629_pciesys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -- ARRAY_SIZE(pcie_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -+static const struct mtk_clk_desc ssusb_desc = { -+ .clks = ssusb_clks, -+ .num_clks = ARRAY_SIZE(ssusb_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc pcie_desc = { -+ .clks = pcie_clks, -+ .num_clks = ARRAY_SIZE(pcie_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt7629_hif[] = { -- { -- .compatible = "mediatek,mt7629-pciesys", -- .data = clk_mt7629_pciesys_init, -- }, { -- .compatible = "mediatek,mt7629-ssusbsys", -- .data = clk_mt7629_ssusbsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, -+ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7629_hif_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7629_hif_drv = { -- .probe = clk_mt7629_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7629-hif", - .of_match_table = of_match_clk_mt7629_hif, diff --git a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch b/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch deleted file mode 100644 index bf9a17292..000000000 --- a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:52 +0100 -Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some - clocks enabled - -Instead of calling clk_prepare_enable() on a bunch of clocks at probe -time, set the CLK_IS_CRITICAL flag to the same as these are required -to be always on, and this is the right way of achieving that. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++----------- - 1 file changed, 24 insertions(+), 22 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", - f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, -- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ f_26m_adc_parents, 0x020, 0x024, 0x028, -+ 24, 1, 31, 0x1C0, 11, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - /* CLK_CFG_3 */ -- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, -- 0x1C0, 12), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, -- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, -- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, -+ 0, 1, 7, 0x1C0, 12, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, -+ 8, 2, 15, 0x1C0, 13, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, -+ 16, 2, 23, 0x1C0, 14, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, - 31, 0x1C0, 15), -@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, -- 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -+ sgm_reg_parents, 0x050, 0x054, 0x058, -+ 16, 1, 23, 0x1C0, 22, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), - /* CLK_CFG_6 */ -@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[] - f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, - 0x1C0, 27), - /* CLK_CFG_7 */ -- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", -- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, -- 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ f_26m_adc_parents, 0x070, 0x074, 0x078, -+ 0, 1, 7, 0x1C0, 28, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str - ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - -- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); -- - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) { diff --git a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch b/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch deleted file mode 100644 index d77b859f0..000000000 --- a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:53 +0100 -Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to - mtk_clk_simple_probe() - -There are no more non-common calls in clk_mt7986_topckgen_probe(): -migrate this driver to mtk_clk_simple_probe(). - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++----------------- - 1 file changed, 13 insertions(+), 42 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[] - 0x1C4, 5), - }; - --static int clk_mt7986_topckgen_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- void __iomem *base; -- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + -- ARRAY_SIZE(top_muxes); -- -- base = of_iomap(node, 0); -- if (!base) { -- pr_err("%s(): ioremap failed\n", __func__); -- return -ENOMEM; -- } -- -- clk_data = mtk_alloc_clk_data(nr); -- if (!clk_data) -- return -ENOMEM; -- -- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), -- clk_data); -- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -- mtk_clk_register_muxes(&pdev->dev, top_muxes, -- ARRAY_SIZE(top_muxes), node, -- &mt7986_clk_lock, clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r) { -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- goto free_topckgen_data; -- } -- return r; -- --free_topckgen_data: -- mtk_free_clk_data(clk_data); -- return r; --} -+static const struct mtk_clk_desc topck_desc = { -+ .fixed_clks = top_fixed_clks, -+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .clk_lock = &mt7986_clk_lock, -+}; - - static const struct of_device_id of_match_clk_mt7986_topckgen[] = { -- { .compatible = "mediatek,mt7986-topckgen", }, -- {} -+ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } - }; - - static struct platform_driver clk_mt7986_topckgen_drv = { -- .probe = clk_mt7986_topckgen_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7986-topckgen", - .of_match_table = of_match_clk_mt7986_topckgen, diff --git a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch b/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch deleted file mode 100644 index a47dd4b05..000000000 --- a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Mon, 6 Mar 2023 15:05:21 +0100 -Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set - critical clock - -Instead of calling clk_prepare_enable() at probe time, add the PLL_AO -flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Tested-by: Daniel Golle -Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-apmixed.c -+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c -@@ -42,7 +42,7 @@ - "clkxtal") - - static const struct mtk_pll_data plls[] = { -- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, - 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, - 0x0210, 4, 0, 0x0214, 0), -@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - -- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); -- - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", diff --git a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch b/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch deleted file mode 100644 index ae76940e1..000000000 --- a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch +++ /dev/null @@ -1,237 +0,0 @@ -From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:34:05 +0000 -Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs - -Add MT7981 clock dt-bindings, include topckgen, apmixedsys, -infracfg, and ethernet subsystem clocks. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Stephen Boyd ---- - .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++ - 1 file changed, 215 insertions(+) - create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h - ---- /dev/null -+++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h -@@ -0,0 +1,215 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Wenzhen.Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7981_H -+#define _DT_BINDINGS_CLK_MT7981_H -+ -+/* TOPCKGEN */ -+#define CLK_TOP_CB_CKSQ_40M 0 -+#define CLK_TOP_CB_M_416M 1 -+#define CLK_TOP_CB_M_D2 2 -+#define CLK_TOP_CB_M_D3 3 -+#define CLK_TOP_M_D3_D2 4 -+#define CLK_TOP_CB_M_D4 5 -+#define CLK_TOP_CB_M_D8 6 -+#define CLK_TOP_M_D8_D2 7 -+#define CLK_TOP_CB_MM_720M 8 -+#define CLK_TOP_CB_MM_D2 9 -+#define CLK_TOP_CB_MM_D3 10 -+#define CLK_TOP_CB_MM_D3_D5 11 -+#define CLK_TOP_CB_MM_D4 12 -+#define CLK_TOP_CB_MM_D6 13 -+#define CLK_TOP_MM_D6_D2 14 -+#define CLK_TOP_CB_MM_D8 15 -+#define CLK_TOP_CB_APLL2_196M 16 -+#define CLK_TOP_APLL2_D2 17 -+#define CLK_TOP_APLL2_D4 18 -+#define CLK_TOP_NET1_2500M 19 -+#define CLK_TOP_CB_NET1_D4 20 -+#define CLK_TOP_CB_NET1_D5 21 -+#define CLK_TOP_NET1_D5_D2 22 -+#define CLK_TOP_NET1_D5_D4 23 -+#define CLK_TOP_CB_NET1_D8 24 -+#define CLK_TOP_NET1_D8_D2 25 -+#define CLK_TOP_NET1_D8_D4 26 -+#define CLK_TOP_CB_NET2_800M 27 -+#define CLK_TOP_CB_NET2_D2 28 -+#define CLK_TOP_CB_NET2_D4 29 -+#define CLK_TOP_NET2_D4_D2 30 -+#define CLK_TOP_NET2_D4_D4 31 -+#define CLK_TOP_CB_NET2_D6 32 -+#define CLK_TOP_CB_WEDMCU_208M 33 -+#define CLK_TOP_CB_SGM_325M 34 -+#define CLK_TOP_CKSQ_40M_D2 35 -+#define CLK_TOP_CB_RTC_32K 36 -+#define CLK_TOP_CB_RTC_32P7K 37 -+#define CLK_TOP_USB_TX250M 38 -+#define CLK_TOP_FAUD 39 -+#define CLK_TOP_NFI1X 40 -+#define CLK_TOP_USB_EQ_RX250M 41 -+#define CLK_TOP_USB_CDR_CK 42 -+#define CLK_TOP_USB_LN0_CK 43 -+#define CLK_TOP_SPINFI_BCK 44 -+#define CLK_TOP_SPI 45 -+#define CLK_TOP_SPIM_MST 46 -+#define CLK_TOP_UART_BCK 47 -+#define CLK_TOP_PWM_BCK 48 -+#define CLK_TOP_I2C_BCK 49 -+#define CLK_TOP_PEXTP_TL 50 -+#define CLK_TOP_EMMC_208M 51 -+#define CLK_TOP_EMMC_400M 52 -+#define CLK_TOP_DRAMC_REF 53 -+#define CLK_TOP_DRAMC_MD32 54 -+#define CLK_TOP_SYSAXI 55 -+#define CLK_TOP_SYSAPB 56 -+#define CLK_TOP_ARM_DB_MAIN 57 -+#define CLK_TOP_AP2CNN_HOST 58 -+#define CLK_TOP_NETSYS 59 -+#define CLK_TOP_NETSYS_500M 60 -+#define CLK_TOP_NETSYS_WED_MCU 61 -+#define CLK_TOP_NETSYS_2X 62 -+#define CLK_TOP_SGM_325M 63 -+#define CLK_TOP_SGM_REG 64 -+#define CLK_TOP_F26M 65 -+#define CLK_TOP_EIP97B 66 -+#define CLK_TOP_USB3_PHY 67 -+#define CLK_TOP_AUD 68 -+#define CLK_TOP_A1SYS 69 -+#define CLK_TOP_AUD_L 70 -+#define CLK_TOP_A_TUNER 71 -+#define CLK_TOP_U2U3_REF 72 -+#define CLK_TOP_U2U3_SYS 73 -+#define CLK_TOP_U2U3_XHCI 74 -+#define CLK_TOP_USB_FRMCNT 75 -+#define CLK_TOP_NFI1X_SEL 76 -+#define CLK_TOP_SPINFI_SEL 77 -+#define CLK_TOP_SPI_SEL 78 -+#define CLK_TOP_SPIM_MST_SEL 79 -+#define CLK_TOP_UART_SEL 80 -+#define CLK_TOP_PWM_SEL 81 -+#define CLK_TOP_I2C_SEL 82 -+#define CLK_TOP_PEXTP_TL_SEL 83 -+#define CLK_TOP_EMMC_208M_SEL 84 -+#define CLK_TOP_EMMC_400M_SEL 85 -+#define CLK_TOP_F26M_SEL 86 -+#define CLK_TOP_DRAMC_SEL 87 -+#define CLK_TOP_DRAMC_MD32_SEL 88 -+#define CLK_TOP_SYSAXI_SEL 89 -+#define CLK_TOP_SYSAPB_SEL 90 -+#define CLK_TOP_ARM_DB_MAIN_SEL 91 -+#define CLK_TOP_AP2CNN_HOST_SEL 92 -+#define CLK_TOP_NETSYS_SEL 93 -+#define CLK_TOP_NETSYS_500M_SEL 94 -+#define CLK_TOP_NETSYS_MCU_SEL 95 -+#define CLK_TOP_NETSYS_2X_SEL 96 -+#define CLK_TOP_SGM_325M_SEL 97 -+#define CLK_TOP_SGM_REG_SEL 98 -+#define CLK_TOP_EIP97B_SEL 99 -+#define CLK_TOP_USB3_PHY_SEL 100 -+#define CLK_TOP_AUD_SEL 101 -+#define CLK_TOP_A1SYS_SEL 102 -+#define CLK_TOP_AUD_L_SEL 103 -+#define CLK_TOP_A_TUNER_SEL 104 -+#define CLK_TOP_U2U3_SEL 105 -+#define CLK_TOP_U2U3_SYS_SEL 106 -+#define CLK_TOP_U2U3_XHCI_SEL 107 -+#define CLK_TOP_USB_FRMCNT_SEL 108 -+#define CLK_TOP_AUD_I2S_M 109 -+ -+/* INFRACFG */ -+#define CLK_INFRA_66M_MCK 0 -+#define CLK_INFRA_UART0_SEL 1 -+#define CLK_INFRA_UART1_SEL 2 -+#define CLK_INFRA_UART2_SEL 3 -+#define CLK_INFRA_SPI0_SEL 4 -+#define CLK_INFRA_SPI1_SEL 5 -+#define CLK_INFRA_SPI2_SEL 6 -+#define CLK_INFRA_PWM1_SEL 7 -+#define CLK_INFRA_PWM2_SEL 8 -+#define CLK_INFRA_PWM3_SEL 9 -+#define CLK_INFRA_PWM_BSEL 10 -+#define CLK_INFRA_PCIE_SEL 11 -+#define CLK_INFRA_GPT_STA 12 -+#define CLK_INFRA_PWM_HCK 13 -+#define CLK_INFRA_PWM_STA 14 -+#define CLK_INFRA_PWM1_CK 15 -+#define CLK_INFRA_PWM2_CK 16 -+#define CLK_INFRA_PWM3_CK 17 -+#define CLK_INFRA_CQ_DMA_CK 18 -+#define CLK_INFRA_AUD_BUS_CK 19 -+#define CLK_INFRA_AUD_26M_CK 20 -+#define CLK_INFRA_AUD_L_CK 21 -+#define CLK_INFRA_AUD_AUD_CK 22 -+#define CLK_INFRA_AUD_EG2_CK 23 -+#define CLK_INFRA_DRAMC_26M_CK 24 -+#define CLK_INFRA_DBG_CK 25 -+#define CLK_INFRA_AP_DMA_CK 26 -+#define CLK_INFRA_SEJ_CK 27 -+#define CLK_INFRA_SEJ_13M_CK 28 -+#define CLK_INFRA_THERM_CK 29 -+#define CLK_INFRA_I2C0_CK 30 -+#define CLK_INFRA_UART0_CK 31 -+#define CLK_INFRA_UART1_CK 32 -+#define CLK_INFRA_UART2_CK 33 -+#define CLK_INFRA_SPI2_CK 34 -+#define CLK_INFRA_SPI2_HCK_CK 35 -+#define CLK_INFRA_NFI1_CK 36 -+#define CLK_INFRA_SPINFI1_CK 37 -+#define CLK_INFRA_NFI_HCK_CK 38 -+#define CLK_INFRA_SPI0_CK 39 -+#define CLK_INFRA_SPI1_CK 40 -+#define CLK_INFRA_SPI0_HCK_CK 41 -+#define CLK_INFRA_SPI1_HCK_CK 42 -+#define CLK_INFRA_FRTC_CK 43 -+#define CLK_INFRA_MSDC_CK 44 -+#define CLK_INFRA_MSDC_HCK_CK 45 -+#define CLK_INFRA_MSDC_133M_CK 46 -+#define CLK_INFRA_MSDC_66M_CK 47 -+#define CLK_INFRA_ADC_26M_CK 48 -+#define CLK_INFRA_ADC_FRC_CK 49 -+#define CLK_INFRA_FBIST2FPC_CK 50 -+#define CLK_INFRA_I2C_MCK_CK 51 -+#define CLK_INFRA_I2C_PCK_CK 52 -+#define CLK_INFRA_IUSB_133_CK 53 -+#define CLK_INFRA_IUSB_66M_CK 54 -+#define CLK_INFRA_IUSB_SYS_CK 55 -+#define CLK_INFRA_IUSB_CK 56 -+#define CLK_INFRA_IPCIE_CK 57 -+#define CLK_INFRA_IPCIE_PIPE_CK 58 -+#define CLK_INFRA_IPCIER_CK 59 -+#define CLK_INFRA_IPCIEB_CK 60 -+ -+/* APMIXEDSYS */ -+#define CLK_APMIXED_ARMPLL 0 -+#define CLK_APMIXED_NET2PLL 1 -+#define CLK_APMIXED_MMPLL 2 -+#define CLK_APMIXED_SGMPLL 3 -+#define CLK_APMIXED_WEDMCUPLL 4 -+#define CLK_APMIXED_NET1PLL 5 -+#define CLK_APMIXED_MPLL 6 -+#define CLK_APMIXED_APLL2 7 -+ -+/* SGMIISYS_0 */ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGM0_CK0_EN 2 -+#define CLK_SGM0_CDR_CK0_EN 3 -+ -+/* SGMIISYS_1 */ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGM1_CK1_EN 2 -+#define CLK_SGM1_CDR_CK1_EN 3 -+ -+/* ETHSYS */ -+#define CLK_ETH_FE_EN 0 -+#define CLK_ETH_GP2_EN 1 -+#define CLK_ETH_GP1_EN 2 -+#define CLK_ETH_WOCPU0_EN 3 -+ -+#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch b/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch deleted file mode 100644 index f9dd94a78..000000000 --- a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch +++ /dev/null @@ -1,932 +0,0 @@ -From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:34:24 +0000 -Subject: [PATCH] clk: mediatek: add MT7981 clock support - -Add MT7981 clock support, include topckgen, apmixedsys, infracfg and -ethernet subsystem clocks. - -The drivers are based on clk-mt7981.c which can be found in MediaTek's -SDK sources. To be fit for upstream inclusion the driver has been split -into clock domains and the infracfg part has been significantly -de-bloated by removing all the 1:1 factors (aliases). - -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org -Reviewed-by: AngeloGioacchino Del Regno -[sboyd@kernel.org: Add module license] -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/Kconfig | 17 + - drivers/clk/mediatek/Makefile | 4 + - drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++ - drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++ - drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++ - drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++ - 6 files changed, 870 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c - ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7981 -+ bool "Clock driver for MediaTek MT7981" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7981 basic clocks and clocks -+ required for various peripherals found on this SoC. -+ -+config COMMON_CLK_MT7981_ETHSYS -+ tristate "Clock driver for MediaTek MT7981 ETHSYS" -+ depends on COMMON_CLK_MT7981 -+ default COMMON_CLK_MT7981 -+ help -+ This driver adds support for clocks for Ethernet and SGMII -+ required on MediaTek MT7981 SoC. -+ - config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-gate.h" -+#include "clk-mtk.h" -+#include "clk-mux.h" -+#include "clk-pll.h" -+ -+#include -+#include -+ -+#define MT7981_PLL_FMAX (2500UL * MHZ) -+#define CON0_MT7981_RST_BAR BIT(27) -+ -+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ -+ _div_table, _parent_name) \ -+ { \ -+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, .flags = _flags, \ -+ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ -+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, .div_table = _div_table, \ -+ .parent_name = _parent_name, \ -+ } -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ -+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ -+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ -+ "clkxtal") -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, -+ 32, 0x0200, 4, 0, 0x0204, 0), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, -+ 0x0210, 4, 0, 0x0214, 0), -+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, -+ 0x0220, 4, 0, 0x0224, 0), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, -+ 0x0230, 4, 0, 0x0234, 0), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, -+ 0x0240, 4, 0, 0x0244, 0), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, -+ 0x0250, 4, 0, 0x0254, 0), -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, -+ 0x0260, 4, 0, 0x0264, 0), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, -+ 0x0278, 4, 0, 0x027C, 0), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_apmixed[] = { -+ { .compatible = "mediatek,mt7981-apmixedsys", }, -+ { /* sentinel */ } -+}; -+ -+static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ -+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_apmixed_data; -+ } -+ return r; -+ -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7981_apmixed_drv = { -+ .probe = clk_mt7981_apmixed_probe, -+ .driver = { -+ .name = "clk-mt7981-apmixed", -+ .of_match_table = of_match_clk_mt7981_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_apmixed_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-eth.c -@@ -0,0 +1,118 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-mtk.h" -+#include "clk-gate.h" -+ -+#include -+ -+static const struct mtk_gate_regs sgmii0_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII0(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii0_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] __initconst = { -+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), -+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), -+ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs sgmii1_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII1(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii1_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii1_clks[] __initconst = { -+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), -+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), -+ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs eth_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETH(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ð_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate eth_clks[] __initconst = { -+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), -+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), -+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), -+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), -+}; -+ -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+}; -+ -+static const struct mtk_clk_desc sgmii0_desc = { -+ .clks = sgmii0_clks, -+ .num_clks = ARRAY_SIZE(sgmii0_clks), -+}; -+ -+static const struct mtk_clk_desc sgmii1_desc = { -+ .clks = sgmii1_clks, -+ .num_clks = ARRAY_SIZE(sgmii1_clks), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_eth[] = { -+ { .compatible = "mediatek,mt7981-ethsys", .data = ð_desc }, -+ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc }, -+ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_eth_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-eth", -+ .of_match_table = of_match_clk_mt7981_eth, -+ }, -+}; -+module_platform_driver(clk_mt7981_eth_drv); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor infra_divs[] = { -+ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), -+}; -+ -+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", -+ "spi_sel" }; -+ -+static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", -+ "spim_mst_sel" }; -+ -+static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; -+ -+static const char *const infra_pwm_bsel_parents[] __initconst = { -+ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" -+}; -+ -+static const char *const infra_pcie_parents[] __initconst = { -+ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" -+}; -+ -+static const struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", -+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", -+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, -+ 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", -+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -+ -1, -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra0_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra1_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra2_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+static const struct mtk_gate infra_clks[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), -+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), -+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), -+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), -+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), -+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), -+ -+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), -+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), -+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), -+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), -+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), -+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", -+ 14), -+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), -+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), -+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), -+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), -+ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), -+ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), -+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), -+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), -+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), -+ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), -+ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), -+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), -+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), -+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), -+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), -+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), -+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", -+ 13), -+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", -+ 14), -+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), -+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), -+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), -+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), -+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), -+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), -+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), -+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), -+ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), -+ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), -+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), -+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), -+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), -+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), -+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", -+ 13), -+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), -+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), -+}; -+ -+static const struct mtk_clk_desc infracfg_desc = { -+ .factor_clks = infra_divs, -+ .num_factor_clks = ARRAY_SIZE(infra_divs), -+ .mux_clks = infra_muxes, -+ .num_mux_clks = ARRAY_SIZE(infra_muxes), -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .clk_lock = &mt7981_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_infracfg[] = { -+ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_infracfg_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-infracfg", -+ .of_match_table = of_match_clk_mt7981_infracfg, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_infracfg_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c -@@ -0,0 +1,422 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor top_divs[] = { -+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), -+ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), -+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), -+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), -+ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), -+ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), -+ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), -+ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), -+ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), -+ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), -+ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), -+ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), -+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), -+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), -+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), -+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), -+ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), -+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), -+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), -+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), -+ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), -+ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), -+ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), -+ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), -+ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), -+ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), -+ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), -+ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), -+ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), -+ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), -+ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), -+ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), -+ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), -+}; -+ -+static const char * const nfi1x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "cb_m_d8" -+}; -+ -+static const char * const spinfi_parents[] __initconst = { -+ "cksq_40m_d2", -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "mm_d6_d2", -+ "cb_m_d8" -+}; -+ -+static const char * const spi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const uart_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d8", -+ "m_d8_d2" -+}; -+ -+static const char * const pwm_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "m_d8_d2", -+ "cb_rtc_32k" -+}; -+ -+static const char * const i2c_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const pextp_tl_ck_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_rtc_32k" -+}; -+ -+static const char * const emmc_208m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_net2_d4", -+ "cb_apll2_196m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_mm_d6" -+}; -+ -+static const char * const emmc_400m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d2", -+ "cb_mm_d2", -+ "cb_net2_d2" -+}; -+ -+static const char * const csw_f26m_parents[] __initconst = { -+ "cksq_40m_d2", -+ "m_d8_d2" -+}; -+ -+static const char * const dramc_md32_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_wedmcu_208m" -+}; -+ -+static const char * const sysaxi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2" -+}; -+ -+static const char * const sysapb_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d3_d2" -+}; -+ -+static const char * const arm_db_main_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d6" -+}; -+ -+static const char * const ap2cnn_host_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d4" -+}; -+ -+static const char * const netsys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d2" -+}; -+ -+static const char * const netsys_500m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5" -+}; -+ -+static const char * const netsys_mcu_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_720m", -+ "cb_net1_d4", -+ "cb_net1_d5", -+ "cb_m_416m" -+}; -+ -+static const char * const netsys_2x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_800m", -+ "cb_mm_720m" -+}; -+ -+static const char * const sgm_325m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_sgm_325m" -+}; -+ -+static const char * const sgm_reg_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d4" -+}; -+ -+static const char * const eip97b_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5", -+ "cb_m_416m", -+ "cb_mm_d2", -+ "net1_d5_d2" -+}; -+ -+static const char * const aud_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m" -+}; -+ -+static const char * const a1sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4" -+}; -+ -+static const char * const aud_l_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m", -+ "m_d8_d2" -+}; -+ -+static const char * const a_tuner_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4" -+}; -+ -+static const char * const usb_frmcnt_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d3_d5" -+}; -+ -+static const struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, -+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, -+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, -+ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, -+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, -+ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, -+ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, -+ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", -+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, -+ 0x1C0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", -+ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, -+ 0x1C0, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", -+ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, -+ 0x1C0, 9), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, -+ 0x1C0, 10, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, -+ 31, 0x1C0, 11, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, -+ 7, 0x1C0, 12, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, -+ 0x1C0, 13, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, 16, 1, -+ 23, 0x1C0, 14, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", -+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, -+ 0x1C0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", -+ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, -+ 0x1C0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, -+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", -+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, -+ 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", -+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, -+ 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", -+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, -+ 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", -+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, -+ 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, -+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, -+ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", -+ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, -+ 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, -+ 0x064, 0x068, 8, 1, 15, 0x1C0, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, -+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, -+ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -+ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, -+ 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, -+ 0x074, 0x078, 8, 1, 15, 0x1C0, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, -+ 0x1C0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, -+ 0x1C4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", -+ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, -+ 0x1C4, 1), -+}; -+ -+static struct mtk_composite top_aud_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", -+ 0x0420, 0, 0x0420, 8, 8), -+}; -+ -+static const struct mtk_clk_desc topck_desc = { -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .composite_clks = top_aud_divs, -+ .num_composite_clks = ARRAY_SIZE(top_aud_divs), -+ .clk_lock = &mt7981_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_topckgen[] = { -+ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_topckgen_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-topckgen", -+ .of_match_table = of_match_clk_mt7981_topckgen, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch deleted file mode 100644 index a365f0860..000000000 --- a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -141,6 +141,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "Mediatek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch deleted file mode 100644 index 75ca114a5..000000000 --- a/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/clk/mediatek/clk-pll.c -+++ b/drivers/clk/mediatek/clk-pll.c -@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct - pll->data->pcw_shift); - val |= pcw << pll->data->pcw_shift; - writel(val, pll->pcw_addr); -- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; -+ if (pll->data->pcw_chg_shift) -+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); -+ else -+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; - writel(chg, pll->pcw_chg_addr); - if (pll->tuner_addr) - writel(val + 1, pll->tuner_addr); ---- a/drivers/clk/mediatek/clk-pll.h -+++ b/drivers/clk/mediatek/clk-pll.h -@@ -42,6 +42,7 @@ struct mtk_pll_data { - u32 pcw_reg; - int pcw_shift; - u32 pcw_chg_reg; -+ int pcw_chg_shift; - const struct mtk_pll_div_table *div_table; - const char *parent_name; - u32 en_reg; diff --git a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch deleted file mode 100644 index 3ced01249..000000000 --- a/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver adds support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7988 -+ bool "Clock driver for MediaTek MT7988" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7988 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch deleted file mode 100644 index 5e3afd856..000000000 --- a/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 25 Oct 2022 15:29:53 +0200 -Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC - -Adding mt7986 own characteristics and of_device_id to have support -of MT7986 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m - .support_64g = false, - }; - -+static const struct mtk_mmc_compatible mt7986_compat = { -+ .clk_div_bits = 12, -+ .recheck_sdio_irq = true, -+ .hs400_tune = false, -+ .pad_tune_reg = MSDC_PAD_TUNE0, -+ .async_fifo = true, -+ .data_tune = true, -+ .busy_check = true, -+ .stop_clk_fix = true, -+ .enhance_rx = true, -+ .support_64g = true, -+}; -+ - static const struct mtk_mmc_compatible mt8135_compat = { - .clk_div_bits = 8, - .recheck_sdio_irq = true, -@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, -+ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, - { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, - { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch deleted file mode 100644 index db2802bd0..000000000 --- a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001 -From: Mengqi Zhang -Date: Sun, 6 Nov 2022 11:39:24 +0800 -Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control - -Add crypto clock control and ungate it before CQHCI init. - -Signed-off-by: Mengqi Zhang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -452,6 +452,7 @@ struct msdc_host { - struct clk *bus_clk; /* bus clock which used to access register */ - struct clk *src_clk_cg; /* msdc source clock control gate */ - struct clk *sys_clk_cg; /* msdc subsys clock control gate */ -+ struct clk *crypto_clk; /* msdc crypto clock control gate */ - struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; - u32 mclk; /* mmc subsystem clock frequency */ - u32 src_clk_freq; /* source clock frequency */ -@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct - static void msdc_gate_clock(struct msdc_host *host) - { - clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); -+ clk_disable_unprepare(host->crypto_clk); - clk_disable_unprepare(host->src_clk_cg); - clk_disable_unprepare(host->src_clk); - clk_disable_unprepare(host->bus_clk); -@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc - clk_prepare_enable(host->bus_clk); - clk_prepare_enable(host->src_clk); - clk_prepare_enable(host->src_clk_cg); -+ clk_prepare_enable(host->crypto_clk); - ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); - if (ret) { - dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); -@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor - goto host_free; - } - -+ /* only eMMC has crypto property */ -+ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { -+ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); -+ if (IS_ERR(host->crypto_clk)) -+ host->crypto_clk = NULL; -+ else -+ mmc->caps2 |= MMC_CAP2_CRYPTO; -+ } -+ - host->irq = platform_get_irq(pdev, 0); - if (host->irq < 0) { - ret = host->irq; diff --git a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch deleted file mode 100644 index 921d249f8..000000000 --- a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001 -From: Yu Zhe -Date: Thu, 10 Nov 2022 15:28:19 +0800 -Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment - -spelling mistake fix : "alreay" -> "already" - "checksume" -> "checksum" - -Signed-off-by: Yu Zhe -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct - else - bd[j].bd_info &= ~BDMA_DESC_EOL; - -- /* checksume need to clear first */ -+ /* checksum need to clear first */ - bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; - bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; - } -@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho - !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data -- * may have alreay come when cmd19/cmd21 gets response -+ * may have already come when cmd19/cmd21 gets response - * CRC error. - */ - msdc_reset_hw(host); diff --git a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch b/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch deleted file mode 100644 index 8e2151e16..000000000 --- a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001 -From: ChanWoo Lee -Date: Thu, 24 Nov 2022 17:00:31 +0900 -Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning() - -Replace code with the already defined function. No functional changes. - -Signed-off-by: ChanWoo Lee -Reviewed-by: Adrian Hunter -Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 8 ++------ - 1 file changed, 2 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho - - if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { - if (events & MSDC_INT_CMDTMO || -- (cmd->opcode != MMC_SEND_TUNING_BLOCK && -- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && -- !host->hs400_tuning)) -+ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data - * may have already come when cmd19/cmd21 gets response -@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho - { - if ((cmd->error && - !(cmd->error == -EILSEQ && -- (cmd->opcode == MMC_SEND_TUNING_BLOCK || -- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || -- host->hs400_tuning))) || -+ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || - (mrq->sbc && mrq->sbc->error)) - msdc_request_done(host, mrq); - else if (cmd == mrq->sbc) diff --git a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch deleted file mode 100644 index 55a308e46..000000000 --- a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) - { -@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_attach(mtd); - ret = mtd_device_register(mtd, NULL, 0); - if (ret) - goto err_spinand_cleanup; -@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem - return 0; - - err_spinand_cleanup: -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return ret; -@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return 0; diff --git a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index 9c1a8f284..000000000 --- a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -553,6 +553,7 @@ - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - nand-ecc-engine = <&snfi>; -+ mediatek,bmt-v2; - - partitions { - compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch deleted file mode 100644 index b00c6fc3f..000000000 --- a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 -From: Davide Fioravanti -Date: Fri, 8 Jan 2021 15:35:24 +0100 -Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA - -Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf - -Signed-off-by: Davide Fioravanti ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/fidelix.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,3 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o -+spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops - static const struct spinand_manufacturer *spinand_manufacturers[] = { - &ato_spinand_manufacturer, - &esmt_c8_spinand_manufacturer, -+ &fidelix_spinand_manufacturer, - &etron_spinand_manufacturer, - &gigadevice_spinand_manufacturer, - ¯onix_spinand_manufacturer, ---- /dev/null -+++ b/drivers/mtd/nand/spi/fidelix.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Davide Fioravanti -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_FIDELIX 0xE5 -+#define FIDELIX_ECCSR_MASK 0x0F -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 2; -+ region->length = 6; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { -+ .ecc = fm35x1ga_ooblayout_ecc, -+ .free = fm35x1ga_ooblayout_free, -+}; -+ -+static const struct spinand_info fidelix_spinand_table[] = { -+ SPINAND_INFO("FM35X1GA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), -+}; -+ -+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer fidelix_spinand_manufacturer = { -+ .id = SPINAND_MFR_FIDELIX, -+ .name = "Fidelix", -+ .chips = fidelix_spinand_table, -+ .nchips = ARRAY_SIZE(fidelix_spinand_table), -+ .ops = &fidelix_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -263,6 +263,7 @@ struct spinand_manufacturer { - extern const struct spinand_manufacturer ato_spinand_manufacturer; - extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; - extern const struct spinand_manufacturer etron_spinand_manufacturer; -+extern const struct spinand_manufacturer fidelix_spinand_manufacturer; - extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; - extern const struct spinand_manufacturer macronix_spinand_manufacturer; - extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch deleted file mode 100644 index 49cd62d0a..000000000 --- a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 28 Feb 2023 19:59:22 +0800 -Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988 - -This add cpufreq support for mediatek MT7988 SoC. - -The platform data of MT7988 is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Sam Shih ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7988_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 900000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+ .ccifreq_supported = true, -+}; -+ - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, -+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index 25ca9485e..000000000 --- a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -315,6 +315,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index 186c66f68..000000000 --- a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -737,6 +737,9 @@ enum safexcel_eip_version { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -55,9 +55,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch deleted file mode 100644 index 615a1a1d7..000000000 --- a/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001 -From: "Mingming.Su" -Date: Sat, 8 Oct 2022 18:45:53 +0200 -Subject: [PATCH] hwrng: mtk - add mt7986 support - -1. Add trng compatible name for MT7986 -2. Fix mtk_rng_wait_ready() function - -Signed-off-by: Mingming.Su -Signed-off-by: Frank Wunderlich -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/mtk-rng.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -22,7 +22,7 @@ - #define RNG_AUTOSUSPEND_TIMEOUT 100 - - #define USEC_POLL 2 --#define TIMEOUT_POLL 20 -+#define TIMEOUT_POLL 60 - - #define RNG_CTRL 0x00 - #define RNG_EN BIT(0) -@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw - readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready, - ready & RNG_READY, USEC_POLL, - TIMEOUT_POLL); -- return !!ready; -+ return !!(ready & RNG_READY); - } - - static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p - #endif /* CONFIG_PM */ - - static const struct of_device_id mtk_rng_match[] = { -+ { .compatible = "mediatek,mt7986-rng" }, - { .compatible = "mediatek,mt7623-rng" }, - {}, - }; diff --git a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch deleted file mode 100644 index fa232b5d4..000000000 --- a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -86,6 +86,7 @@ struct serial8250_config { - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ - #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */ -+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */ - - #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -287,7 +287,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2767,6 +2767,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch deleted file mode 100644 index 95fc7f466..000000000 --- a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ /dev/null @@ -1,130 +0,0 @@ -From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:29:51 +0800 -Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private - data - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 29 +++++++++--------------- - include/linux/platform_data/spi-mt65xx.h | 17 -------------- - 2 files changed, 11 insertions(+), 35 deletions(-) - delete mode 100644 include/linux/platform_data/spi-mt65xx.h - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -14,7 +14,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -171,6 +170,8 @@ struct mtk_spi { - struct device *dev; - dma_addr_t tx_dma; - dma_addr_t rx_dma; -+ u32 sample_sel; -+ u32 get_tick_dly; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m - .no_need_unprepare = true, - }; - --/* -- * A piece of default chip info unless the platform -- * supplies it. -- */ --static const struct mtk_chip_config mtk_default_chip_info = { -- .sample_sel = 0, -- .tick_delay = 0, --}; -- - static const struct of_device_id mtk_spi_of_match[] = { - { .compatible = "mediatek,spi-ipm", - .data = (void *)&mtk_ipm_compat, -@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma - { - u16 cpha, cpol; - u32 reg_val; -- struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); - - cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma - else - reg_val &= ~SPI_CMD_CS_POL; - -- if (chip_config->sample_sel) -+ if (mdata->sample_sel) - reg_val |= SPI_CMD_SAMPLE_SEL; - else - reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma - if (mdata->dev_comp->ipm_design) { - reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CMD_IPM_GET_TICKDLY_OFFSET); - writel(reg_val, mdata->base + SPI_CMD_REG); - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; -- reg_val |= ((chip_config->tick_delay & 0x3) -+ reg_val |= ((mdata->get_tick_dly & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi - { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); - -- if (!spi->controller_data) -- spi->controller_data = (void *)&mtk_default_chip_info; -- - if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) - /* CS de-asserted, gpiolib will handle inversion */ - gpiod_direction_output(spi->cs_gpiod, 0); -@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform - mdata = spi_master_get_devdata(master); - mdata->dev_comp = device_get_match_data(dev); - -+ /* Set device configs to default first. Calibrate it later. */ -+ mdata->sample_sel = 0; -+ mdata->get_tick_dly = 2; -+ - if (mdata->dev_comp->enhance_timing) - master->mode_bits |= SPI_CS_HIGH; - ---- a/include/linux/platform_data/spi-mt65xx.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * MTK SPI bus driver definitions -- * -- * Copyright (c) 2015 MediaTek Inc. -- * Author: Leilk Liu -- */ -- --#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H --#define ____LINUX_PLATFORM_DATA_SPI_MTK_H -- --/* Board specific platform_data */ --struct mtk_chip_config { -- u32 sample_sel; -- u32 tick_delay; --}; --#endif diff --git a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch deleted file mode 100644 index 10e528dba..000000000 --- a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ /dev/null @@ -1,236 +0,0 @@ -From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:35:52 +0800 -Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ - include/linux/spi/spi.h | 42 ++++++++++++ - 2 files changed, 179 insertions(+) - ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -1389,6 +1389,70 @@ static int spi_transfer_wait(struct spi_ - return 0; - } - -+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) -+{ -+ int datalen = ctlr->cal_rule->datalen; -+ int addrlen = ctlr->cal_rule->addrlen; -+ u8 *buf; -+ int ret; -+ int i; -+ struct list_head *cal_head, *listptr; -+ struct spi_cal_target *target; -+ -+ /* Calculate calibration result */ -+ int hit_val, total_hit, origin; -+ bool hit; -+ -+ /* Make sure we can start calibration */ -+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) -+ return 0; -+ -+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); -+ if(!buf) -+ return -ENOMEM; -+ -+ ret = ctlr->append_caldata(ctlr); -+ if (ret) -+ goto cal_end; -+ -+ cal_head = ctlr->cal_target; -+ list_for_each(listptr, cal_head) { -+ target = list_entry(listptr, struct spi_cal_target, list); -+ -+ hit = false; -+ hit_val = 0; -+ total_hit = 0; -+ origin = *target->cal_item; -+ -+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { -+ *target->cal_item = i; -+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); -+ if(ret) -+ break; -+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); -+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { -+ hit = true; -+ hit_val += i; -+ total_hit++; -+ dev_dbg(&spi->dev, "golden data matches data read!\n"); -+ } -+ } -+ if(hit) { -+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); -+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); -+ } else { -+ *target->cal_item = origin; -+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); -+ } -+ } -+ -+cal_end: -+ kfree(buf); -+ return ret? ret: 0; -+} -+EXPORT_SYMBOL_GPL(spi_do_calibration); -+ - static void _spi_transfer_delay_ns(u32 ns) - { - if (!ns) -@@ -2227,6 +2291,75 @@ void spi_flush_queue(struct spi_controll - /*-------------------------------------------------------------------------*/ - - #if defined(CONFIG_OF) -+static inline void alloc_cal_data(struct list_head **cal_target, -+ struct spi_cal_rule **cal_rule, bool enable) -+{ -+ if(enable) { -+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); -+ INIT_LIST_HEAD(*cal_target); -+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); -+ } else { -+ kfree(*cal_target); -+ kfree(*cal_rule); -+ } -+} -+ -+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, -+ struct device_node *nc) -+{ -+ u32 value; -+ int rc; -+ const char *cal_mode; -+ -+ rc = of_property_read_bool(nc, "spi-cal-enable"); -+ if (rc) -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); -+ else -+ return 0; -+ -+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); -+ if(!rc) { -+ if(strcmp("read-data", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; -+ } else if(strcmp("read-pp", cal_mode) == 0) { -+ ctlr->cal_rule->mode = SPI_CAL_READ_PP; -+ return 0; -+ } else if(strcmp("read-sfdp", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; -+ return 0; -+ } -+ } else -+ goto err; -+ -+ ctlr->cal_rule->datalen = 0; -+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->datalen = value; -+ -+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); -+ rc = of_property_read_u8_array(nc, "spi-cal-data", -+ ctlr->cal_rule->match_data, value); -+ if(rc) -+ kfree(ctlr->cal_rule->match_data); -+ } -+ -+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->addrlen = value; -+ -+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); -+ rc = of_property_read_u32_array(nc, "spi-cal-addr", -+ ctlr->cal_rule->addr, value); -+ if(rc) -+ kfree(ctlr->cal_rule->addr); -+ } -+ return 0; -+ -+err: -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); -+ return 0; -+} -+ - static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, - struct device_node *nc) - { -@@ -2345,6 +2478,10 @@ of_register_spi_device(struct spi_contro - if (rc) - goto err_out; - -+ rc = of_spi_parse_cal_dt(ctlr, spi, nc); -+ if (rc) -+ goto err_out; -+ - /* Store a pointer to the node in the device structure */ - of_node_get(nc); - spi->dev.of_node = nc; ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -318,6 +318,40 @@ struct spi_driver { - struct device_driver driver; - }; - -+enum { -+ SPI_CAL_READ_DATA = 0, -+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ -+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ -+}; -+ -+struct nand_addr { -+ unsigned int lun; -+ unsigned int plane; -+ unsigned int eraseblock; -+ unsigned int page; -+ unsigned int dataoffs; -+}; -+ -+/** -+ * Read calibration rule from device dts node. -+ * Once calibration result matches the rule, we regard is as success. -+ */ -+struct spi_cal_rule { -+ int datalen; -+ u8 *match_data; -+ int addrlen; -+ u32 *addr; -+ int mode; -+}; -+ -+struct spi_cal_target { -+ u32 *cal_item; -+ int cal_min; /* min of cal_item */ -+ int cal_max; /* max of cal_item */ -+ int step; /* Increase/decrease cal_item */ -+ struct list_head list; -+}; -+ - static inline struct spi_driver *to_spi_driver(struct device_driver *drv) - { - return drv ? container_of(drv, struct spi_driver, driver) : NULL; -@@ -712,6 +746,11 @@ struct spi_controller { - void *dummy_rx; - void *dummy_tx; - -+ /* For calibration */ -+ int (*append_caldata)(struct spi_controller *ctlr); -+ struct list_head *cal_target; -+ struct spi_cal_rule *cal_rule; -+ - int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); - - /* -@@ -1555,6 +1594,9 @@ spi_register_board_info(struct spi_board - { return 0; } - #endif - -+extern int spi_do_calibration(struct spi_controller *ctlr, -+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); -+ - /* If you're hotplugging an adapter with devices (parport, usb, etc) - * use spi_new_device() to describe each device. You can also call - * spi_unregister_device() to start making that device vanish, but diff --git a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch deleted file mode 100644 index e87d63db6..000000000 --- a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:37:55 +0800 -Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mem.c | 8 ++++++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem, - } - EXPORT_SYMBOL_GPL(spi_mem_exec_op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), -+ void *priv) -+{ -+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); -+} -+EXPORT_SYMBOL_GPL(spi_mem_do_calibration); -+ - /** - * spi_mem_get_name() - Return the SPI mem device name to be used by the - * upper layer if necessary ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem - int spi_mem_exec_op(struct spi_mem *mem, - const struct spi_mem_op *op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *, u32 *, int, u8 *, int), -+ void *priv); -+ - const char *spi_mem_get_name(struct spi_mem *mem); - - struct spi_mem_dirmap_desc * diff --git a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch deleted file mode 100644 index dbdb1947a..000000000 --- a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ /dev/null @@ -1,43 +0,0 @@ -From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:03 +0800 -Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration - paramter - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -834,6 +834,21 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_HANDLED; - } - -+static int mtk_spi_append_caldata(struct spi_controller *ctlr) -+{ -+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); -+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr); -+ -+ cal_target->cal_item = &mdata->get_tick_dly; -+ cal_target->cal_min = 0; -+ cal_target->cal_max = 7; -+ cal_target->step = 1; -+ -+ list_add(&cal_target->list, ctlr->cal_target); -+ -+ return 0; -+} -+ - static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, - struct spi_mem_op *op) - { -@@ -1124,6 +1139,7 @@ static int mtk_spi_probe(struct platform - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; - master->use_gpio_descriptors = true; -+ master->append_caldata = mtk_spi_append_caldata; - - mdata = spi_master_get_devdata(master); - mdata->dev_comp = device_get_match_data(dev); diff --git a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch deleted file mode 100644 index 3991d8925..000000000 --- a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:56 +0800 -Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for - spinand - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st - return -ENOTSUPP; - } - -+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { -+ struct spinand_device *spinand = (struct spinand_device *)priv; -+ struct device *dev = &spinand->spimem->spi->dev; -+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); -+ struct nand_pos pos; -+ struct nand_page_io_req req; -+ u8 status; -+ int ret; -+ -+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { -+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); -+ return -EINVAL; -+ } -+ -+ ret = spinand_reset_op(spinand); -+ if (ret) -+ return ret; -+ -+ /* We should store our golden data in first target because -+ * we can't switch target at this moment. -+ */ -+ pos = (struct nand_pos){ -+ .target = 0, -+ .lun = *addr, -+ .plane = *(addr+1), -+ .eraseblock = *(addr+2), -+ .page = *(addr+3), -+ }; -+ -+ req = (struct nand_page_io_req){ -+ .pos = pos, -+ .dataoffs = *(addr+4), -+ .datalen = readlen, -+ .databuf.in = buf, -+ .mode = MTD_OPS_AUTO_OOB, -+ }; -+ -+ ret = spinand_load_page_op(spinand, &req); -+ if (ret) -+ return ret; -+ -+ ret = spinand_wait(spinand, &status); -+ if (ret < 0) -+ return ret; -+ -+ ret = spi_mem_exec_op(spinand->spimem, &op); -+ -+ return 0; -+} -+ - static int spinand_id_detect(struct spinand_device *spinand) - { - u8 *id = spinand->id.data; -@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d - if (!spinand->scratchbuf) - return -ENOMEM; - -+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); -+ if (ret) -+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); -+ - ret = spinand_detect(spinand); - if (ret) - goto err_free_bufs; diff --git a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch deleted file mode 100644 index 1f747d1f4..000000000 --- a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:40:59 +0800 -Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for - spi-nor - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 5 ++++- - drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad - if (ret) - return ret; - -- ret = spinand_wait(spinand, &status); -+ ret = spinand_wait(spinand, -+ SPINAND_READ_INITIAL_DELAY_US, -+ SPINAND_READ_POLL_DELAY_US, -+ &status); - if (ret < 0) - return ret; - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -2900,6 +2900,18 @@ static const struct flash_info *spi_nor_ - return NULL; - } - -+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) -+{ -+ struct spi_nor *nor = (struct spi_nor *)priv; -+ -+ nor->reg_proto = SNOR_PROTO_1_1_1; -+ nor->read_proto = SNOR_PROTO_1_1_1; -+ nor->read_opcode = SPINOR_OP_READ; -+ nor->read_dummy = 0; -+ -+ return nor->controller_ops->read(nor, *addr, readlen, buf); -+} -+ - static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, - const char *name) - { -@@ -3003,6 +3015,9 @@ int spi_nor_scan(struct spi_nor *nor, co - if (!nor->bouncebuf) - return -ENOMEM; - -+ if(nor->spimem) -+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); -+ - info = spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) - return PTR_ERR(info); diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index e37705f38..000000000 --- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -389,6 +389,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -98,6 +98,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch deleted file mode 100644 index 983fde707..000000000 --- a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: qizhong cheng -Date: Mon, 27 Dec 2021 21:31:10 +0800 -Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to - stabilize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -be delayed 100ms (TPVPERL) for the power and clock to become stable. - -Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com -Signed-off-by: qizhong cheng -Signed-off-by: Lorenzo Pieralisi -Acked-by: Pali Rohár ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru - */ - msleep(100); - -+ /* -+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -+ * be delayed 100ms (TPVPERL) for the power and clock to become stable. -+ */ -+ msleep(100); -+ - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val = readl(port->base + PCIE_RST_CTRL); - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | diff --git a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch deleted file mode 100644 index d58082aa6..000000000 --- a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -844,6 +844,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - pcie1: pcie@1a145000 { -@@ -882,6 +888,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - sata: sata@1a200000 { diff --git a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index 2a49b2275..000000000 --- a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - generic_handle_domain_irq(port->irq_domain, - bit - INTX_SHIFT); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index 917a458d3..000000000 --- a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,91 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -832,6 +832,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -876,6 +879,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -937,7 +943,7 @@ - }; - - hifsys: clock-controller@1af00000 { -- compatible = "mediatek,mt7622-hifsys"; -+ compatible = "mediatek,mt7622-hifsys", "syscon"; - reg = <0 0x1af00000 0 0x70>; - #clock-cells = <1>; - }; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err, slot; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - slot = of_get_pci_domain_nr(dev->of_node); - if (slot < 0) { - for_each_available_child_of_node(node, child) { diff --git a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd0..000000000 --- a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch deleted file mode 100644 index 52069496c..000000000 --- a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -23,11 +23,17 @@ - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <950000>; -- }; -- -+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low -+ * voltage condition that can cause a hang when rebooting the RT3200/E8450. -+ * -+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 -+ * -+ * opp-300000000 { -+ * opp-hz = /bits/ 64 <300000000>; -+ * opp-microvolt = <950000>; -+ * }; -+ * -+ */ - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index 8d1b89d69..000000000 --- a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,1204 +0,0 @@ -From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 11 Jun 2023 00:48:10 +0100 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c. -Add support for such PHYs by introducing a new driver with basic -support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. - -Signed-off-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1140 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -12943,6 +12943,15 @@ S: Maintained - F: drivers/net/pcs/pcs-mtk-lynxi.c - F: include/linux/pcs/pcs-mtk-lynxi.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -314,6 +314,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - depends on PTP_1588_CLOCK_OPTIONAL ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -84,6 +84,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- /dev/null -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -0,0 +1,1116 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_GPHY_ID_MT7981 0x03a29461 -+#define MTK_GPHY_ID_MT7988 0x03a29481 -+ -+#define MTK_EXT_PAGE_ACCESS 0x1f -+#define MTK_PHY_PAGE_STANDARD 0x0000 -+#define MTK_PHY_PAGE_EXTENDED_3 0x0003 -+ -+#define MTK_PHY_LPI_REG_14 0x14 -+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) -+ -+#define MTK_PHY_LPI_REG_1c 0x1c -+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 -+ -+#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -+#define TXRESERVE_MIN 0 -+#define TXRESERVE_MAX 7 -+ -+#define MTK_PHY_ANARG_RG 0x10 -+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) -+ -+/* Registers on MDIO_MMD_VEND1 */ -+#define MTK_PHY_TXVLD_DA_RG 0x12 -+#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -+#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -+#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -+#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -+#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -+#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -+#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -+#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) -+ -+#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) -+ -+#define MTK_PHY_LDO_OUTPUT_V 0xd7 -+ -+#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -+#define MTK_PHY_RG_CAL_CKINV BIT(12) -+#define MTK_PHY_RG_ANA_CALEN BIT(8) -+#define MTK_PHY_RG_ZCALEN_A BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -+#define MTK_PHY_RG_ZCALEN_B BIT(12) -+#define MTK_PHY_RG_ZCALEN_C BIT(8) -+#define MTK_PHY_RG_ZCALEN_D BIT(4) -+#define MTK_PHY_RG_TXVOS_CALEN BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_RG_TX_FILTER 0xfe -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -+#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -+#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) -+ -+#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -+#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -+#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -+#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_AD_CAL_COMP 0x17a -+#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) -+ -+#define MTK_PHY_RG_AD_CAL_CLK 0x17b -+#define MTK_PHY_DA_CAL_CLK BIT(0) -+ -+#define MTK_PHY_RG_AD_CALIN 0x17c -+#define MTK_PHY_DA_CALIN_FLAG BIT(0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -+#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -+#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -+#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -+#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -+#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -+#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -+#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -+#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG19b 0x19b -+#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) -+ -+#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -+#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -+#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -+#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -+#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -+#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -+#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -+#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -+#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -+#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 -+ -+#define MTK_PHY_RG_DEV1E_REG234 0x234 -+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) -+ -+#define MTK_PHY_RG_LPF_CNT_VAL 0x235 -+ -+#define MTK_PHY_RG_DEV1E_REG238 0x238 -+#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG239 0x239 -+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG27C 0x27c -+#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -+#define MTK_PHY_RG_DEV1E_REG27D 0x27d -+#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -+#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -+#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) -+ -+#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -+#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -+#define MTK_PHY_LPI_TR_READY BIT(9) -+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) -+ -+#define MTK_PHY_RG_DEV1E_REG323 0x323 -+#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -+#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) -+ -+#define MTK_PHY_RG_DEV1E_REG324 0x324 -+#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -+#define MTK_PHY_SMI_DET_MAX_EN BIT(8) -+ -+#define MTK_PHY_RG_DEV1E_REG326 0x326 -+#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -+#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -+#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -+#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -+#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) -+ -+#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -+#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 -+ -+#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -+#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -+#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -+#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 -+ -+#define MTK_PHY_RG_BG_RASEL 0x115 -+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) -+ -+/* These macro privides efuse parsing for internal phy. */ -+#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) -+ -+#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -+#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) -+ -+enum { -+ NO_PAIR, -+ PAIR_A, -+ PAIR_B, -+ PAIR_C, -+ PAIR_D, -+}; -+ -+enum { -+ GPHY_PORT0, -+ GPHY_PORT1, -+ GPHY_PORT2, -+ GPHY_PORT3, -+}; -+ -+enum calibration_mode { -+ EFUSE_K, -+ SW_K -+}; -+ -+enum CAL_ITEM { -+ REXT, -+ TX_OFFSET, -+ TX_AMP, -+ TX_R50, -+ TX_VCM -+}; -+ -+enum CAL_MODE { -+ EFUSE_M, -+ SW_M -+}; -+ -+static int mtk_socphy_read_page(struct phy_device *phydev) -+{ -+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -+} -+ -+static int mtk_socphy_write_page(struct phy_device *phydev, int page) -+{ -+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -+} -+ -+/* One calibration cycle consists of: -+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high -+ * until AD_CAL_COMP is ready to output calibration result. -+ * 2.Wait until DA_CAL_CLK is available. -+ * 3.Fetch AD_CAL_COMP_OUT. -+ */ -+static int cal_cycle(struct phy_device *phydev, int devad, -+ u32 regnum, u16 mask, u16 cal_val) -+{ -+ int reg_val; -+ int ret; -+ -+ phy_modify_mmd(phydev, devad, regnum, -+ mask, cal_val); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ -+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_AD_CAL_CLK, reg_val, -+ reg_val & MTK_PHY_DA_CAL_CLK, 500, -+ ANALOG_INTERNAL_OPERATION_MAX_US, false); -+ if (ret) { -+ phydev_err(phydev, "Calibration cycle timeout\n"); -+ return ret; -+ } -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> -+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; -+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); -+ -+ return ret; -+} -+ -+static int rext_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, -+ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, -+ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); -+ -+ return 0; -+} -+ -+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 rext_cal_val[2]; -+ -+ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); -+ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); -+ rext_fill_result(phydev, rext_cal_val); -+ -+ return 0; -+} -+ -+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); -+ -+ return 0; -+} -+ -+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_offset_cal_val[4]; -+ -+ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); -+ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); -+ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); -+ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); -+ -+ tx_offset_fill_result(phydev, tx_offset_cal_val); -+ -+ return 0; -+} -+ -+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ int i; -+ int bias[16] = {}; -+ const int vals_9461[16] = { 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7 }; -+ const int vals_9481[16] = { 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10 }; -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ /* We add some calibration to efuse values -+ * due to board level influence. -+ * GBE: +7, TBT: +1, HBT: +4, TST: +7 -+ */ -+ memcpy(bias, (const void *)vals_9461, sizeof(bias)); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ memcpy(bias, (const void *)vals_9481, sizeof(bias)); -+ break; -+ } -+ -+ /* Prevent overflow */ -+ for (i = 0; i < 12; i++) { -+ if (buf[i >> 2] + bias[i] > 63) { -+ buf[i >> 2] = 63; -+ bias[i] = 0; -+ } -+ } -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); -+ -+ return 0; -+} -+ -+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_amp_cal_val[4]; -+ -+ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); -+ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); -+ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); -+ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); -+ tx_amp_fill_result(phydev, tx_amp_cal_val); -+ -+ return 0; -+} -+ -+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, -+ u8 txg_calen_x) -+{ -+ int bias = 0; -+ u16 reg, val; -+ -+ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) -+ bias = -2; -+ -+ val = clamp_val(bias + tx_r50_cal_val, 0, 63); -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ reg = MTK_PHY_DA_TX_R50_PAIR_A; -+ break; -+ case PAIR_B: -+ reg = MTK_PHY_DA_TX_R50_PAIR_B; -+ break; -+ case PAIR_C: -+ reg = MTK_PHY_DA_TX_R50_PAIR_C; -+ break; -+ case PAIR_D: -+ reg = MTK_PHY_DA_TX_R50_PAIR_D; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); -+ -+ return 0; -+} -+ -+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, -+ u8 txg_calen_x) -+{ -+ u16 tx_r50_cal_val; -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); -+ break; -+ case PAIR_B: -+ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); -+ break; -+ case PAIR_C: -+ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); -+ break; -+ case PAIR_D: -+ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); -+ break; -+ default: -+ return -EINVAL; -+ } -+ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); -+ -+ return 0; -+} -+ -+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -+{ -+ u8 lower_idx, upper_idx, txreserve_val; -+ u8 lower_ret, upper_ret; -+ int ret; -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_CAL_CKINV); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ -+ switch (rg_txreserve_x) { -+ case PAIR_A: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_A, -+ MTK_PHY_DASN_DAC_IN0_A_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_A, -+ MTK_PHY_DASN_DAC_IN1_A_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ break; -+ case PAIR_B: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_B, -+ MTK_PHY_DASN_DAC_IN0_B_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_B, -+ MTK_PHY_DASN_DAC_IN1_B_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B); -+ break; -+ case PAIR_C: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_C, -+ MTK_PHY_DASN_DAC_IN0_C_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_C, -+ MTK_PHY_DASN_DAC_IN1_C_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_C); -+ break; -+ case PAIR_D: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_D, -+ MTK_PHY_DASN_DAC_IN0_D_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_D, -+ MTK_PHY_DASN_DAC_IN1_D_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_D); -+ break; -+ default: -+ ret = -EINVAL; -+ goto restore; -+ } -+ -+ lower_idx = TXRESERVE_MIN; -+ upper_idx = TXRESERVE_MAX; -+ -+ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); -+ while ((upper_idx - lower_idx) > 1) { -+ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); -+ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ txreserve_val << 12 | txreserve_val << 8 | -+ txreserve_val << 4 | txreserve_val); -+ if (ret == 1) { -+ upper_idx = txreserve_val; -+ upper_ret = ret; -+ } else if (ret == 0) { -+ lower_idx = txreserve_val; -+ lower_ret = ret; -+ } else { -+ goto restore; -+ } -+ } -+ -+ if (lower_idx == TXRESERVE_MIN) { -+ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ ret = lower_ret; -+ } else if (upper_idx == TXRESERVE_MAX) { -+ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ ret = upper_ret; -+ } -+ if (ret < 0) -+ goto restore; -+ -+ /* We calibrate TX-VCM in different logic. Check upper index and then -+ * lower index. If this calibration is valid, apply lower index's result. -+ */ -+ ret = upper_ret - lower_ret; -+ if (ret == 1) { -+ ret = 0; -+ /* Make sure we use upper_idx in our calibration system */ -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); -+ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && -+ lower_ret == 1) { -+ ret = 0; -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", -+ lower_idx); -+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && -+ lower_ret == 0) { -+ ret = 0; -+ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", -+ upper_idx); -+ } else { -+ ret = -EINVAL; -+ } -+ -+restore: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | -+ MTK_PHY_RG_ZCALEN_D); -+ -+ return ret; -+} -+ -+static void mt798x_phy_common_finetune(struct phy_device *phydev) -+{ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* EnabRandUpdTrig = 1 */ -+ __phy_write(phydev, 0x11, 0x2f00); -+ __phy_write(phydev, 0x12, 0xe); -+ __phy_write(phydev, 0x10, 0x8fb0); -+ -+ /* NormMseLoThresh = 85 */ -+ __phy_write(phydev, 0x11, 0x55a0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x83aa); -+ -+ /* TrFreeze = 0 */ -+ __phy_write(phydev, 0x11, 0x0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9686); -+ -+ /* SSTrKp1000Slv = 5 */ -+ __phy_write(phydev, 0x11, 0xbaef); -+ __phy_write(phydev, 0x12, 0x2e); -+ __phy_write(phydev, 0x10, 0x968c); -+ -+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, -+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 -+ */ -+ __phy_write(phydev, 0x11, 0xd10a); -+ __phy_write(phydev, 0x12, 0x34); -+ __phy_write(phydev, 0x10, 0x8f82); -+ -+ /* VcoSlicerThreshBitsHigh */ -+ __phy_write(phydev, 0x11, 0x5555); -+ __phy_write(phydev, 0x12, 0x55); -+ __phy_write(phydev, 0x10, 0x8ec0); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, -+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, -+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); -+ -+ /* rg_tr_lpf_cnt_val = 512 */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); -+ -+ /* IIR2 related */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); -+ -+ /* FFE peaking */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, -+ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, -+ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); -+ -+ /* Disable LDO pump */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); -+ /* Adjust LDO output voltage */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -+} -+ -+static void mt7981_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[8] = { 0x01ce, 0x01c1, -+ 0x020f, 0x0202, -+ 0x03d0, 0x03c0, -+ 0x0013, 0x0005 }; -+ int i, k; -+ -+ /* 100M eye finetune: -+ * Keep middle level of TX MLT3 shapper as default. -+ * Only change TX MLT3 overshoot level here. -+ */ -+ for (k = 0, i = 1; i < 12; i++) { -+ if (i % 3 == 0) -+ continue; -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); -+ } -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ -+ __phy_write(phydev, 0x11, 0xc71); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 6 */ -+ __phy_write(phydev, 0x11, 0x600); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate = 1 */ -+ __phy_write(phydev, 0x11, 0x4c2a); -+ __phy_write(phydev, 0x12, 0x3e); -+ __phy_write(phydev, 0x10, 0x8fa4); -+ -+ /* FfeUpdGainForce = 4 */ -+ __phy_write(phydev, 0x11, 0x240); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9680); -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt7988_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, -+ 0x020d, 0x0206, 0x0384, 0x03d0, -+ 0x03c6, 0x030a, 0x0011, 0x0005 }; -+ int i; -+ -+ /* Set default MLT3 shaper first */ -+ for (i = 0; i < 12; i++) -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); -+ -+ /* TCT finetune */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); -+ -+ /* Disable TX power saving */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, -+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ -+ __phy_write(phydev, 0x11, 0x671); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 5 */ -+ __phy_write(phydev, 0x11, 0x500); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate is 1 at default on mt7988 */ -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); -+ /* TxClkOffset = 2 */ -+ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, -+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt798x_phy_eee(struct phy_device *phydev) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, -+ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | -+ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ 0xff)); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_TESTMUX_ADC_CTRL, -+ MTK_PHY_RG_TXEN_DIG_MASK); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, -+ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | -+ MTK_PHY_LPI_SLV_SEND_TX_EN, -+ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, -+ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | -+ MTK_PHY_LPI_TXPCS_LOC_RCV, -+ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, -+ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, -+ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | -+ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, -+ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ 0x33) | -+ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | -+ MTK_PHY_LPI_VCO_EEE_STG0_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, -+ MTK_PHY_EEE_WAKE_MAS_INT_DC | -+ MTK_PHY_EEE_WAKE_SLV_INT_DC); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, -+ MTK_PHY_SMI_DETCNT_MAX_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | -+ MTK_PHY_SMI_DET_MAX_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, -+ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | -+ MTK_PHY_TREC_UPDATE_ENAB_CLR | -+ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | -+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* Regsigdet_sel_1000 = 0 */ -+ __phy_write(phydev, 0x11, 0xb); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9690); -+ -+ /* REG_EEE_st2TrKf1000 = 3 */ -+ __phy_write(phydev, 0x11, 0x114f); -+ __phy_write(phydev, 0x12, 0x2); -+ __phy_write(phydev, 0x10, 0x969a); -+ -+ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ -+ __phy_write(phydev, 0x11, 0x3028); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x969e); -+ -+ /* RegEEE_slv_wake_int_timer_tar = 8 */ -+ __phy_write(phydev, 0x11, 0x5010); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a0); -+ -+ /* RegEEE_trfreeze_timer2 = 586 */ -+ __phy_write(phydev, 0x11, 0x24a); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a8); -+ -+ /* RegEEE100Stg1_tar = 16 */ -+ __phy_write(phydev, 0x11, 0x3210); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96b8); -+ -+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ -+ __phy_write(phydev, 0x11, 0x1463); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96ca); -+ -+ /* DfeTailEnableVgaThresh1000 = 27 */ -+ __phy_write(phydev, 0x11, 0x36); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8f80); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); -+ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); -+ -+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -+} -+ -+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_OFFSET & TX_AMP have no SW calibration. */ -+ switch (cal_item) { -+ case TX_VCM: -+ ret = tx_vcm_cal_sw(phydev, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair, u32 *buf) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_VCM has no efuse calibration. */ -+ switch (cal_item) { -+ case REXT: -+ ret = rext_cal_efuse(phydev, buf); -+ break; -+ case TX_OFFSET: -+ ret = tx_offset_cal_efuse(phydev, buf); -+ break; -+ case TX_AMP: -+ ret = tx_amp_cal_efuse(phydev, buf); -+ break; -+ case TX_R50: -+ ret = tx_r50_cal_efuse(phydev, buf, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ enum CAL_MODE cal_mode, u8 start_pair, -+ u8 end_pair, u32 *buf) -+{ -+ int ret; -+ -+ switch (cal_mode) { -+ case EFUSE_M: -+ ret = cal_efuse(phydev, cal_item, start_pair, -+ end_pair, buf); -+ break; -+ case SW_M: -+ ret = cal_sw(phydev, cal_item, start_pair, end_pair); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (ret) { -+ phydev_err(phydev, "cal %d failed\n", cal_item); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt798x_phy_calibration(struct phy_device *phydev) -+{ -+ int ret = 0; -+ u32 *buf; -+ size_t len; -+ struct nvmem_cell *cell; -+ -+ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); -+ if (IS_ERR(cell)) { -+ if (PTR_ERR(cell) == -EPROBE_DEFER) -+ return PTR_ERR(cell); -+ return 0; -+ } -+ -+ buf = (u32 *)nvmem_cell_read(cell, &len); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ nvmem_cell_put(cell); -+ -+ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { -+ phydev_err(phydev, "invalid efuse data\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); -+ if (ret) -+ goto out; -+ -+out: -+ kfree(buf); -+ return ret; -+} -+ -+static int mt798x_phy_config_init(struct phy_device *phydev) -+{ -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ mt7981_phy_finetune(phydev); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ mt7988_phy_finetune(phydev); -+ break; -+ } -+ -+ mt798x_phy_common_finetune(phydev); -+ mt798x_phy_eee(phydev); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ -+static struct phy_driver mtk_socphy_driver[] = { -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -+ .name = "MediaTek MT7981 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), -+ .name = "MediaTek MT7988 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_socphy_driver); -+ -+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, -+ { } -+}; -+ -+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -+MODULE_AUTHOR("Daniel Golle "); -+MODULE_AUTHOR("SkyLake Huang "); -+MODULE_LICENSE("GPL"); -+ -+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch b/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch deleted file mode 100644 index 286ce96a7..000000000 --- a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch +++ /dev/null @@ -1,524 +0,0 @@ -From c66937b0f8dbb4c6c043663c702b1053fb47fab2 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 14 Aug 2023 02:58:14 +0100 -Subject: [PATCH] net: phy: mediatek-ge-soc: support PHY LEDs - -Implement netdev trigger and primitive bliking offloading as well as -simple set_brigthness function for both PHY LEDs of the in-SoC PHYs -found in MT7981 and MT7988. - -For MT7988, read boottrap register and apply LED polarities accordingly -to get uniform behavior from all LEDs on MT7988. -This requires syscon phandle 'mediatek,pio' present in parenting MDIO bus -which should point to the syscon holding the boottrap register. - -Signed-off-by: Daniel Golle -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/dc324d48c00cd7350f3a506eaa785324cae97372.1691977904.git.daniel@makrotopia.org -Signed-off-by: Jakub Kicinski ---- - drivers/net/phy/mediatek-ge-soc.c | 435 +++++++++++++++++++++++++++++- - 1 file changed, 426 insertions(+), 9 deletions(-) - ---- a/drivers/net/phy/mediatek-ge-soc.c -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -1,11 +1,14 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include -+#include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #define MTK_GPHY_ID_MT7981 0x03a29461 - #define MTK_GPHY_ID_MT7988 0x03a29481 -@@ -208,9 +211,42 @@ - #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f - #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -+/* Registers on MDIO_MMD_VEND2 */ -+#define MTK_PHY_LED0_ON_CTRL 0x24 -+#define MTK_PHY_LED1_ON_CTRL 0x26 -+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) -+#define MTK_PHY_LED_ON_LINK1000 BIT(0) -+#define MTK_PHY_LED_ON_LINK100 BIT(1) -+#define MTK_PHY_LED_ON_LINK10 BIT(2) -+#define MTK_PHY_LED_ON_LINKDOWN BIT(3) -+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ -+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ -+#define MTK_PHY_LED_ON_FORCE_ON BIT(6) -+#define MTK_PHY_LED_ON_POLARITY BIT(14) -+#define MTK_PHY_LED_ON_ENABLE BIT(15) -+ -+#define MTK_PHY_LED0_BLINK_CTRL 0x25 -+#define MTK_PHY_LED1_BLINK_CTRL 0x27 -+#define MTK_PHY_LED_BLINK_1000TX BIT(0) -+#define MTK_PHY_LED_BLINK_1000RX BIT(1) -+#define MTK_PHY_LED_BLINK_100TX BIT(2) -+#define MTK_PHY_LED_BLINK_100RX BIT(3) -+#define MTK_PHY_LED_BLINK_10TX BIT(4) -+#define MTK_PHY_LED_BLINK_10RX BIT(5) -+#define MTK_PHY_LED_BLINK_COLLISION BIT(6) -+#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) -+#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) -+#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) -+ -+#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) -+ - #define MTK_PHY_RG_BG_RASEL 0x115 - #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -+/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ -+#define RG_GPIO_MISC_TPBANK0 0x6f0 -+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) -+ - /* These macro privides efuse parsing for internal phy. */ - #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) - #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -@@ -238,13 +274,6 @@ enum { - PAIR_D, - }; - --enum { -- GPHY_PORT0, -- GPHY_PORT1, -- GPHY_PORT2, -- GPHY_PORT3, --}; -- - enum calibration_mode { - EFUSE_K, - SW_K -@@ -263,6 +292,19 @@ enum CAL_MODE { - SW_M - }; - -+#define MTK_PHY_LED_STATE_FORCE_ON 0 -+#define MTK_PHY_LED_STATE_FORCE_BLINK 1 -+#define MTK_PHY_LED_STATE_NETDEV 2 -+ -+struct mtk_socphy_priv { -+ unsigned long led_state; -+}; -+ -+struct mtk_socphy_shared { -+ u32 boottrap; -+ struct mtk_socphy_priv priv[4]; -+}; -+ - static int mtk_socphy_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -@@ -1073,6 +1115,371 @@ static int mt798x_phy_config_init(struct - return mt798x_phy_calibration(phydev); - } - -+static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, -+ bool on) -+{ -+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ bool changed; -+ -+ if (on) -+ changed = !test_and_set_bit(bit_on, &priv->led_state); -+ else -+ changed = !!test_and_clear_bit(bit_on, &priv->led_state); -+ -+ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + -+ (index ? 16 : 0), &priv->led_state); -+ if (changed) -+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_MASK, -+ on ? MTK_PHY_LED_ON_FORCE_ON : 0); -+ else -+ return 0; -+} -+ -+static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, -+ bool blinking) -+{ -+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ bool changed; -+ -+ if (blinking) -+ changed = !test_and_set_bit(bit_blink, &priv->led_state); -+ else -+ changed = !!test_and_clear_bit(bit_blink, &priv->led_state); -+ -+ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + -+ (index ? 16 : 0), &priv->led_state); -+ if (changed) -+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL, -+ blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); -+ else -+ return 0; -+} -+ -+static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, -+ unsigned long *delay_on, -+ unsigned long *delay_off) -+{ -+ bool blinking = false; -+ int err = 0; -+ -+ if (index > 1) -+ return -EINVAL; -+ -+ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { -+ blinking = true; -+ *delay_on = 50; -+ *delay_off = 50; -+ } -+ -+ err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); -+ if (err) -+ return err; -+ -+ return mt798x_phy_hw_led_on_set(phydev, index, false); -+} -+ -+static int mt798x_phy_led_brightness_set(struct phy_device *phydev, -+ u8 index, enum led_brightness value) -+{ -+ int err; -+ -+ err = mt798x_phy_hw_led_blink_set(phydev, index, false); -+ if (err) -+ return err; -+ -+ return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); -+} -+ -+static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | -+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | -+ BIT(TRIGGER_NETDEV_LINK) | -+ BIT(TRIGGER_NETDEV_LINK_10) | -+ BIT(TRIGGER_NETDEV_LINK_100) | -+ BIT(TRIGGER_NETDEV_LINK_1000) | -+ BIT(TRIGGER_NETDEV_RX) | -+ BIT(TRIGGER_NETDEV_TX)); -+ -+static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, -+ unsigned long rules) -+{ -+ if (index > 1) -+ return -EINVAL; -+ -+ /* All combinations of the supported triggers are allowed */ -+ if (rules & ~supported_triggers) -+ return -EOPNOTSUPP; -+ -+ return 0; -+}; -+ -+static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, -+ unsigned long *rules) -+{ -+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); -+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); -+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ int on, blink; -+ -+ if (index > 1) -+ return -EINVAL; -+ -+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, -+ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); -+ -+ if (on < 0) -+ return -EIO; -+ -+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, -+ index ? MTK_PHY_LED1_BLINK_CTRL : -+ MTK_PHY_LED0_BLINK_CTRL); -+ if (blink < 0) -+ return -EIO; -+ -+ if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK10)) || -+ (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | -+ MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX | -+ MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))) -+ set_bit(bit_netdev, &priv->led_state); -+ else -+ clear_bit(bit_netdev, &priv->led_state); -+ -+ if (on & MTK_PHY_LED_ON_FORCE_ON) -+ set_bit(bit_on, &priv->led_state); -+ else -+ clear_bit(bit_on, &priv->led_state); -+ -+ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) -+ set_bit(bit_blink, &priv->led_state); -+ else -+ clear_bit(bit_blink, &priv->led_state); -+ -+ if (!rules) -+ return 0; -+ -+ if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10)) -+ *rules |= BIT(TRIGGER_NETDEV_LINK); -+ -+ if (on & MTK_PHY_LED_ON_LINK10) -+ *rules |= BIT(TRIGGER_NETDEV_LINK_10); -+ -+ if (on & MTK_PHY_LED_ON_LINK100) -+ *rules |= BIT(TRIGGER_NETDEV_LINK_100); -+ -+ if (on & MTK_PHY_LED_ON_LINK1000) -+ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); -+ -+ if (on & MTK_PHY_LED_ON_FDX) -+ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); -+ -+ if (on & MTK_PHY_LED_ON_HDX) -+ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); -+ -+ if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX)) -+ *rules |= BIT(TRIGGER_NETDEV_RX); -+ -+ if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)) -+ *rules |= BIT(TRIGGER_NETDEV_TX); -+ -+ return 0; -+}; -+ -+static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, -+ unsigned long rules) -+{ -+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ u16 on = 0, blink = 0; -+ int ret; -+ -+ if (index > 1) -+ return -EINVAL; -+ -+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) -+ on |= MTK_PHY_LED_ON_FDX; -+ -+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) -+ on |= MTK_PHY_LED_ON_HDX; -+ -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) -+ on |= MTK_PHY_LED_ON_LINK10; -+ -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) -+ on |= MTK_PHY_LED_ON_LINK100; -+ -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) -+ on |= MTK_PHY_LED_ON_LINK1000; -+ -+ if (rules & BIT(TRIGGER_NETDEV_RX)) { -+ blink |= MTK_PHY_LED_BLINK_10RX | -+ MTK_PHY_LED_BLINK_100RX | -+ MTK_PHY_LED_BLINK_1000RX; -+ } -+ -+ if (rules & BIT(TRIGGER_NETDEV_TX)) { -+ blink |= MTK_PHY_LED_BLINK_10TX | -+ MTK_PHY_LED_BLINK_100TX | -+ MTK_PHY_LED_BLINK_1000TX; -+ } -+ -+ if (blink || on) -+ set_bit(bit_netdev, &priv->led_state); -+ else -+ clear_bit(bit_netdev, &priv->led_state); -+ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_ON_CTRL : -+ MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_FDX | -+ MTK_PHY_LED_ON_HDX | -+ MTK_PHY_LED_ON_LINK10 | -+ MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK1000, -+ on); -+ -+ if (ret) -+ return ret; -+ -+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_BLINK_CTRL : -+ MTK_PHY_LED0_BLINK_CTRL, blink); -+}; -+ -+static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) -+{ -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ u32 polarities; -+ -+ if (led_num == 0) -+ polarities = ~(priv->boottrap); -+ else -+ polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; -+ -+ if (polarities & BIT(phydev->mdio.addr)) -+ return true; -+ -+ return false; -+} -+ -+static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) -+{ -+ struct pinctrl *pinctrl; -+ int index; -+ -+ /* Setup LED polarity according to bootstrap use of LED pins */ -+ for (index = 0; index < 2; ++index) -+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_POLARITY, -+ mt7988_phy_led_get_polarity(phydev, index) ? -+ MTK_PHY_LED_ON_POLARITY : 0); -+ -+ /* Only now setup pinctrl to avoid bogus blinking */ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); -+ if (IS_ERR(pinctrl)) -+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n"); -+ -+ return 0; -+} -+ -+static int mt7988_phy_probe_shared(struct phy_device *phydev) -+{ -+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); -+ struct mtk_socphy_shared *shared = phydev->shared->priv; -+ struct regmap *regmap; -+ u32 reg; -+ int ret; -+ -+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, -+ * LED_C and LED_D respectively. At the same time those pins are used to -+ * bootstrap configuration of the reference clock source (LED_A), -+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). -+ * In practise this is done using a LED and a resistor pulling the pin -+ * either to GND or to VIO. -+ * The detected value at boot time is accessible at run-time using the -+ * TPBANK0 register located in the gpio base of the pinctrl, in order -+ * to read it here it needs to be referenced by a phandle called -+ * 'mediatek,pio' in the MDIO bus hosting the PHY. -+ * The 4 bits in TPBANK0 are kept as package shared data and are used to -+ * set LED polarity for each of the LED0. -+ */ -+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); -+ if (ret) -+ return ret; -+ -+ shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); -+ -+ return 0; -+} -+ -+static void mt798x_phy_leds_state_init(struct phy_device *phydev) -+{ -+ int i; -+ -+ for (i = 0; i < 2; ++i) -+ mt798x_phy_led_hw_control_get(phydev, i, NULL); -+} -+ -+static int mt7988_phy_probe(struct phy_device *phydev) -+{ -+ struct mtk_socphy_shared *shared; -+ struct mtk_socphy_priv *priv; -+ int err; -+ -+ if (phydev->mdio.addr > 3) -+ return -EINVAL; -+ -+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, -+ sizeof(struct mtk_socphy_shared)); -+ if (err) -+ return err; -+ -+ if (phy_package_probe_once(phydev)) { -+ err = mt7988_phy_probe_shared(phydev); -+ if (err) -+ return err; -+ } -+ -+ shared = phydev->shared->priv; -+ priv = &shared->priv[phydev->mdio.addr]; -+ -+ phydev->priv = priv; -+ -+ mt798x_phy_leds_state_init(phydev); -+ -+ err = mt7988_phy_fix_leds_polarities(phydev); -+ if (err) -+ return err; -+ -+ return mt798x_phy_calibration(phydev); -+} -+ -+static int mt7981_phy_probe(struct phy_device *phydev) -+{ -+ struct mtk_socphy_priv *priv; -+ -+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), -+ GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ phydev->priv = priv; -+ -+ mt798x_phy_leds_state_init(phydev); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ - static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -@@ -1080,11 +1487,16 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7981_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, -+ .led_blink_set = mt798x_phy_led_blink_set, -+ .led_brightness_set = mt798x_phy_led_brightness_set, -+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, -+ .led_hw_control_set = mt798x_phy_led_hw_control_set, -+ .led_hw_control_get = mt798x_phy_led_hw_control_get, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), -@@ -1092,11 +1504,16 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, -+ .led_blink_set = mt798x_phy_led_blink_set, -+ .led_brightness_set = mt798x_phy_led_brightness_set, -+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, -+ .led_hw_control_set = mt798x_phy_led_hw_control_set, -+ .led_hw_control_get = mt798x_phy_led_hw_control_get, - }, - }; - diff --git a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch deleted file mode 100644 index d74572737..000000000 --- a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch +++ /dev/null @@ -1,63 +0,0 @@ -From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 6 Apr 2023 23:36:50 +0100 -Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink - -MAC drivers using phylink expect SGMII in-band-status to be switched off -when attached to a PHY. Make sure this is the case also for mxl-gpy which -keeps SGMII in-band-status in case of SGMII interface mode is used. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -367,8 +367,11 @@ static bool gpy_2500basex_chk(struct phy - - phydev->speed = SPEED_2500; - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -+ -+ if (!phydev->phylink) -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ - return true; - } - -@@ -392,6 +395,14 @@ static int gpy_config_aneg(struct phy_de - u32 adv; - int ret; - -+ /* Disable SGMII auto-negotiation if using phylink */ -+ if (phydev->phylink) { -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ } -+ - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. -@@ -482,6 +493,8 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ if (phydev->phylink) -+ break; - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, - VSPEC1_SGMII_CTRL_ANEN, 0); - if (ret < 0) -@@ -493,7 +506,7 @@ static void gpy_update_interface(struct - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) - break; - /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed - * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch deleted file mode 100644 index 125bd9b0b..000000000 --- a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 28 Feb 2023 17:53:37 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/Kconfig | 7 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++ - 3 files changed, 226 insertions(+) - create mode 100644 drivers/net/phy/mediatek-2p5ge.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY - present in the SoCs efuse and will dynamically calibrate VCM - (common-mode voltage) during startup. - -+config MEDIATEK_2P5G_PHY -+ tristate "MediaTek 2.5G Ethernet PHY" -+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST -+ default NET_MEDIATEK_SOC -+ help -+ Supports the MediaTek 2.5G Ethernet PHY. -+ - config MICREL_PHY - tristate "Micrel PHYs" - depends on PTP_1588_CLOCK_OPTIONAL ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -83,6 +83,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell - obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o -+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o - obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o diff --git a/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch deleted file mode 100644 index 0c73d520b..000000000 --- a/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data - .has_ck_26m_sel = true, - }; - -+static const struct pwm_mediatek_of_data mt7986_pwm_data = { -+ .num_pwms = 2, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+}; -+ - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, -@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch deleted file mode 100644 index c58ae9640..000000000 --- a/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 18 Jan 2023 02:48:41 +0000 -Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for - raw_to_mcelsius - -Instead of having if-else logic selecting either raw_to_mcelsius_v1 or -raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function -pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the -probe function. - -Signed-off-by: Daniel Golle ---- - drivers/thermal/mtk_thermal.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -292,6 +292,8 @@ struct mtk_thermal { - - const struct mtk_thermal_data *conf; - struct mtk_thermal_bank banks[MAX_NUM_ZONES]; -+ -+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); - }; - - /* MT8183 thermal sensor data */ -@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature( - for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { - raw = readl(mt->thermal_base + conf->msr[i]); - -- if (mt->conf->version == MTK_THERMAL_V1) { -- temp = raw_to_mcelsius_v1( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } else { -- temp = raw_to_mcelsius_v2( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } -+ temp = mt->raw_to_mcelsius( -+ mt, conf->bank_data[bank->id].sensors[i], raw); -+ - - /* - * The first read of a sensor often contains very high bogus -@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -+ if (mt->conf->version == MTK_THERMAL_V1) -+ mt->raw_to_mcelsius = raw_to_mcelsius_v1; -+ else -+ mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) - mtk_thermal_init_bank(mt, i, apmixed_phys_base, diff --git a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch deleted file mode 100644 index 65311d571..000000000 --- a/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch +++ /dev/null @@ -1,240 +0,0 @@ -From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 30 Nov 2022 13:19:39 +0000 -Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981 - -Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. -Brings code to assign values from efuse as well as new function to -convert raw temperature to millidegree celsius, as found in MediaTek's -SDK sources (but cleaned up and de-duplicated) - -[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b -Signed-off-by: Daniel Golle ---- - drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++-- - 1 file changed, 132 insertions(+), 5 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -150,6 +150,20 @@ - #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) - #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) - -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros can be used for MT7981 and MT7986. -+ */ -+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) -+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) -+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) -+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) -+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) -+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) -+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) -+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) -+ - enum { - VTS1, - VTS2, -@@ -163,6 +177,7 @@ enum { - enum mtk_thermal_version { - MTK_THERMAL_V1 = 1, - MTK_THERMAL_V2, -+ MTK_THERMAL_V3, - }; - - /* MT2701 thermal sensors */ -@@ -245,6 +260,27 @@ enum mtk_thermal_version { - /* The calibration coefficient of sensor */ - #define MT8183_CALIBRATION 153 - -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT7986_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT7986 */ -+#define MT7986_NUM_SENSORS 1 -+ -+/* The number of banks in the MT7986 */ -+#define MT7986_NUM_ZONES 1 -+ -+/* The number of sensing points per bank */ -+#define MT7986_NUM_SENSORS_PER_ZONE 1 -+ -+/* MT7986 thermal sensors */ -+#define MT7986_TS1 0 -+ -+/* The number of controller in the MT7986 */ -+#define MT7986_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT7986_CALIBRATION 165 -+ - struct mtk_thermal; - - struct thermal_bank_cfg { -@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762 - static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; - static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; - -+/* MT7986 thermal sensor data */ -+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; -+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; -+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; -+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; -+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; -+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; -+ - /* - * The MT8173 thermal controller has four banks. Each bank can read up to - * four temperature sensors simultaneously. The MT8173 has a total of 5 -@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8 - .version = MTK_THERMAL_V1, - }; - -+/* -+ * MT7986 uses AUXADC Channel 11 for raw data access. -+ */ -+static const struct mtk_thermal_data mt7986_thermal_data = { -+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT7986_NUM_ZONES, -+ .num_sensors = MT7986_NUM_SENSORS, -+ .vts_index = mt7986_vts_index, -+ .cali_val = MT7986_CALIBRATION, -+ .num_controller = MT7986_NUM_CONTROLLER, -+ .controller_offset = mt7986_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 1, -+ .sensors = mt7986_bank_data, -+ }, -+ }, -+ .msr = mt7986_msr, -+ .adcpnp = mt7986_adcpnp, -+ .sensor_mux_values = mt7986_mux_values, -+ .version = MTK_THERMAL_V3, -+}; -+ - /** - * raw_to_mcelsius - convert a raw ADC value to mcelsius - * @mt: The thermal controller -@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk - return (format_2 - tmp) * 100; - } - -+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 tmp; -+ -+ if (raw == 0) -+ return 0; -+ -+ raw &= 0xfff; -+ tmp = 100000 * 15 / 16 * 10000; -+ tmp /= 4096 - 512 + mt->adc_ge; -+ tmp /= 1490; -+ tmp *= raw - mt->vts[sensno] - 2900; -+ -+ return mt->degc_cali * 500 - tmp; -+} -+ - /** - * mtk_thermal_get_bank - get bank - * @bank: The bank -@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2( - return 0; - } - -+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) -+{ -+ if (!CALIB_BUF1_VALID_V3(buf[1])) -+ return -EINVAL; -+ -+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); -+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); -+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); -+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); -+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); -+ -+ if (CALIB_BUF1_ID_V3(buf[1]) == 0) -+ mt->o_slope = 0; -+ -+ return 0; -+} -+ - static int mtk_thermal_get_calibration_data(struct device *dev, - struct mtk_thermal *mt) - { -@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d - - /* Start with default values */ - mt->adc_ge = 512; -+ mt->adc_oe = 512; - for (i = 0; i < mt->conf->num_sensors; i++) - mt->vts[i] = 260; - mt->degc_cali = 40; -@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d - goto out; - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - ret = mtk_thermal_extract_efuse_v1(mt, buf); -- else -+ break; -+ case MTK_THERMAL_V2: - ret = mtk_thermal_extract_efuse_v2(mt, buf); -+ break; -+ case MTK_THERMAL_V3: -+ ret = mtk_thermal_extract_efuse_v3(mt, buf); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } - - if (ret) { - dev_info(dev, "Device not calibrated, using default calibration values\n"); -@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the - .data = (void *)&mt7622_thermal_data, - }, - { -+ .compatible = "mediatek,mt7986-thermal", -+ .data = (void *)&mt7986_thermal_data, -+ }, -+ { - .compatible = "mediatek,mt8183-thermal", - .data = (void *)&mt8183_thermal_data, - }, { -@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat - goto err_disable_clk_auxadc; - } - -- if (mt->conf->version == MTK_THERMAL_V2) { -+ if (mt->conf->version != MTK_THERMAL_V1) { - mtk_thermal_turn_on_buffer(apmixed_base); - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - mt->raw_to_mcelsius = raw_to_mcelsius_v1; -- else -+ break; -+ case MTK_THERMAL_V2: - mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ break; -+ case MTK_THERMAL_V3: -+ mt->raw_to_mcelsius = raw_to_mcelsius_v3; -+ break; -+ default: -+ break; -+ } - - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) diff --git a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch deleted file mode 100644 index f130fdbc5..000000000 --- a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch +++ /dev/null @@ -1,129 +0,0 @@ -From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:12 +0100 -Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias - functions - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo -and mtk_pinconf_bias_get_combo, and make the functions able to support -almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. - -This patch enables pinctrl_moore to support these functions. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++---- - 1 file changed, 42 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-moore.c -+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c -@@ -8,6 +8,7 @@ - * - */ - -+#include - #include - #include "pinctrl-moore.h" - -@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr - { - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); - u32 param = pinconf_to_config_param(*config); -- int val, val2, err, reg, ret = 1; -+ int val, val2, err, pullup, reg, ret = 1; - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) -+ return -EINVAL; -+ } else if (hw->soc->bias_disable_get) { - err = hw->soc->bias_disable_get(hw, desc, &ret); - if (err) - return err; -@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (!pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 1, &ret); - if (err) - return err; -@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 0, &ret); - if (err) - return err; -@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_disable_set) { - err = hw->soc->bias_disable_set(hw, desc); - if (err) - return err; -@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 1, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 1); - if (err) - return err; -@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 0); - if (err) - return err; diff --git a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch deleted file mode 100644 index 4c398c59f..000000000 --- a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 9 Oct 2022 12:16:31 +0200 -Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support - -Add i2c support for MT7986 SoC. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7986_compat = { -+ .quirks = &mt7622_i2c_quirks, -+ .regs = mt_i2c_regs_v1, -+ .pmic_i2c = 0, -+ .dcm = 1, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 0, -+ .dma_sync = 1, -+ .ltiming_adjust = 0, -+ .max_dma_support = 32, -+}; -+ - static const struct mtk_i2c_compatible mt8173_compat = { - .regs = mt_i2c_regs_v1, - .pmic_i2c = 0, -@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, diff --git a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch deleted file mode 100644 index 18c66cdac..000000000 --- a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001 -From: ye xingchen -Date: Thu, 19 Jan 2023 17:19:58 +0800 -Subject: [PATCH 13/16] i2c: mt65xx: Use - devm_platform_get_and_ioremap_resource() - -Convert platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -Signed-off-by: ye xingchen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform - { - int ret = 0; - struct mtk_i2c *i2c; -- struct resource *res; - int i, irq, speed_clk; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(i2c->base)) - return PTR_ERR(i2c->base); - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -- i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); -+ i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(i2c->pdmabase)) - return PTR_ERR(i2c->pdmabase); - diff --git a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch deleted file mode 100644 index d000d5352..000000000 --- a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Sat, 11 Mar 2023 12:16:54 +0100 -Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver can match only via the DT table so the table should be always -used and the of_match_ptr does not have any sense (this also allows ACPI -matching via PRP0001, even though it might not be relevant here). - - drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=] - -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Guenter Roeck -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr - .driver = { - .name = I2C_DRV_NAME, - .pm = &mtk_i2c_pm, -- .of_match_table = of_match_ptr(mtk_i2c_of_match), -+ .of_match_table = mtk_i2c_of_match, - }, - }; - diff --git a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch deleted file mode 100644 index e0973741e..000000000 --- a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 10 Apr 2023 17:19:38 +0100 -Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC - -Add support for the I2C units found in the MediaTek MT7981 and MT7988 -SoCs. Just like other recent MediaTek I2C units that also uses v3 -register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being -0x94 instead of 0x4). - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7981_compat = { -+ .regs = mt_i2c_regs_v3, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 1, -+ .ltiming_adjust = 1, -+ .max_dma_support = 33 -+}; -+ - static const struct mtk_i2c_compatible mt7986_compat = { - .quirks = &mt7622_i2c_quirks, - .regs = mt_i2c_regs_v1, -@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, - { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index 2ee9c6299..000000000 --- a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,65 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -315,7 +315,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch deleted file mode 100644 index f8857bdf7..000000000 --- a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha - if (p != NULL && l > 0) - strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - handle_cmdline: - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -2239,6 +2239,14 @@ config CMDLINE_FORCE - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EFI_STUB - bool - diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index 0c7e64a5e..000000000 --- a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -642,5 +642,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch deleted file mode 100644 index 3d05bf767..000000000 --- a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -1227,8 +1227,15 @@ static int mtk_spi_probe(struct platform - if (ret < 0) - return dev_err_probe(dev, ret, "failed to enable hclk\n"); - -+ ret = clk_prepare_enable(mdata->sel_clk); -+ if (ret < 0) { -+ clk_disable_unprepare(mdata->spi_hclk); -+ return dev_err_probe(dev, ret, "failed to enable sel_clk\n"); -+ } -+ - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { -+ clk_disable_unprepare(mdata->sel_clk); - clk_disable_unprepare(mdata->spi_hclk); - return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); - } diff --git a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch deleted file mode 100644 index 2fe565f3b..000000000 --- a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 -Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 16:40:31 +0100 -Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename - mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region - -This is a preliminary patch to move wed ilm/dlm and cpuboot properties in -dedicated dts nodes. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -215,8 +215,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we - } - - static int --mtk_wed_get_memory_region(struct mtk_wed_wo *wo, -- struct mtk_wed_wo_memory_region *region) -+mtk_wed_get_reserved_memory_region(struct mtk_wed_wo *wo, -+ struct mtk_wed_wo_memory_region *region) - { - struct reserved_mem *rmem; - struct device_node *np; -@@ -311,13 +311,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- ret = mtk_wed_get_memory_region(wo, &mem_region[i]); -+ ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); - if (ret) - return ret; - } - - wo->boot.name = "wo-boot"; -- ret = mtk_wed_get_memory_region(wo, &wo->boot); -+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); - if (ret) - return ret; - diff --git a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch deleted file mode 100644 index 7b791b88d..000000000 --- a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 -Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 16:32:41 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -121,12 +121,6 @@ - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; -- -- wo_boot: wo-boot@15194000 { -- reg = <0 0x15194000 0 0x1000>; -- no-map; -- }; -- - }; - - timer { -@@ -519,10 +513,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wed1: wed@15011000 { -@@ -532,10 +527,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wo_ccif0: syscon@151a5000 { -@@ -552,6 +548,11 @@ - interrupts = ; - }; - -+ wo_cpuboot: syscon@15194000 { -+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ - eth: ethernet@15100000 { - compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; diff --git a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch deleted file mode 100644 index 9de4ffa43..000000000 --- a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch +++ /dev/null @@ -1,89 +0,0 @@ -From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 18:13:04 +0100 -Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a - dedicated dts node - -Since the cpuboot memory region is not part of the RAM SoC, move cpuboot -in a deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where cpuboot was -defined as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -18,12 +18,23 @@ - - static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) - { -- return readl(wo->boot.addr + reg); -+ u32 val; -+ -+ if (!wo->boot_regmap) -+ return readl(wo->boot.addr + reg); -+ -+ if (regmap_read(wo->boot_regmap, reg, &val)) -+ val = ~0; -+ -+ return val; - } - - static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) - { -- writel(val, wo->boot.addr + reg); -+ if (wo->boot_regmap) -+ regmap_write(wo->boot_regmap, reg, val); -+ else -+ writel(val, wo->boot.addr + reg); - } - - static struct sk_buff * -@@ -316,10 +327,21 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - return ret; - } - -- wo->boot.name = "wo-boot"; -- ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); -- if (ret) -- return ret; -+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, -+ "mediatek,wo-cpuboot"); -+ if (IS_ERR(wo->boot_regmap)) { -+ if (wo->boot_regmap != ERR_PTR(-ENODEV)) -+ return PTR_ERR(wo->boot_regmap); -+ -+ /* For backward compatibility, we need to check if cpu_boot -+ * is defined through reserved memory property. -+ */ -+ wo->boot_regmap = NULL; -+ wo->boot.name = "wo-boot"; -+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); -+ if (ret) -+ return ret; -+ } - - /* set dummy cr */ - wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL, ---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h -+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h -@@ -228,7 +228,8 @@ struct mtk_wed_wo_queue { - - struct mtk_wed_wo { - struct mtk_wed_hw *hw; -- struct mtk_wed_wo_memory_region boot; -+ struct mtk_wed_wo_memory_region boot; /* backward compatibility */ -+ struct regmap *boot_regmap; - - struct mtk_wed_wo_queue q_tx; - struct mtk_wed_wo_queue q_rx; diff --git a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch deleted file mode 100644 index 7b6c5d1e2..000000000 --- a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,91 +0,0 @@ -From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 -Message-Id: -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 18:51:47 +0100 -Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts - node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where ilm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- - 1 file changed, 49 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -300,6 +300,52 @@ next: - } - - static int -+mtk_wed_mcu_load_memory_regions(struct mtk_wed_wo *wo, -+ struct mtk_wed_wo_memory_region *region) -+{ -+ struct device_node *np; -+ int ret; -+ -+ /* firmware EMI memory region */ -+ ret = mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_EMI]); -+ if (ret) -+ return ret; -+ -+ /* firmware DATA memory region */ -+ ret = mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_DATA]); -+ if (ret) -+ return ret; -+ -+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); -+ if (np) { -+ struct mtk_wed_wo_memory_region *ilm_region; -+ struct resource res; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ ilm_region = ®ion[MTK_WED_WO_REGION_ILM]; -+ ilm_region->phy_addr = res.start; -+ ilm_region->size = resource_size(&res); -+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, -+ resource_size(&res)); -+ -+ return IS_ERR(ilm_region->addr) ? PTR_ERR(ilm_region->addr) : 0; -+ } -+ -+ /* For backward compatibility, we need to check if ILM -+ * node is defined through reserved memory property. -+ */ -+ return mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_ILM]); -+} -+ -+static int - mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) - { - static struct mtk_wed_wo_memory_region mem_region[] = { -@@ -320,12 +366,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -- /* load firmware region metadata */ -- for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); -- if (ret) -- return ret; -- } -+ ret = mtk_wed_mcu_load_memory_regions(wo, mem_region); -+ if (ret) -+ return ret; - - wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, - "mediatek,wo-cpuboot"); diff --git a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch deleted file mode 100644 index 209580d64..000000000 --- a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: -References: -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:45:16 +0100 -Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts - node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where dlm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_wed.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -814,6 +814,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device - struct device_node *np; - int index; - -+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); -+ if (np) { -+ struct resource res; -+ int ret; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ dev->rro.miod_phys = res.start; -+ goto out; -+ } -+ -+ /* For backward compatibility, we need to check if DLM -+ * node is defined through reserved memory property. -+ */ - index = of_property_match_string(dev->hw->node, "memory-region-names", - "wo-dlm"); - if (index < 0) -@@ -830,6 +848,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device - return -ENODEV; - - dev->rro.miod_phys = rmem->base; -+out: - dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; - - return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch deleted file mode 100644 index 8accda584..000000000 --- a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 -Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:10:56 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ - 1 file changed, 16 insertions(+), 18 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -97,16 +97,6 @@ - no-map; - }; - -- wo_ilm0: wo-ilm@151e0000 { -- reg = <0 0x151e0000 0 0x8000>; -- no-map; -- }; -- -- wo_ilm1: wo-ilm@151f0000 { -- reg = <0 0x151f0000 0 0x8000>; -- no-map; -- }; -- - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; -@@ -512,11 +502,10 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -526,11 +515,10 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-ilm = <&wo_ilm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -548,6 +536,16 @@ - interrupts = ; - }; - -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_ilm1: syscon@151f0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151f0000 0 0x8000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch deleted file mode 100644 index 6bf751591..000000000 --- a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 -Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:53:30 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- - 1 file changed, 16 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -101,16 +101,6 @@ - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; -- -- wo_dlm0: wo-dlm@151e8000 { -- reg = <0 0x151e8000 0 0x2000>; -- no-map; -- }; -- -- wo_dlm1: wo-dlm@151f8000 { -- reg = <0 0x151f8000 0 0x2000>; -- no-map; -- }; - }; - - timer { -@@ -502,10 +492,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -515,10 +506,11 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; - mediatek,wo-ilm = <&wo_ilm1>; -+ mediatek,wo-dlm = <&wo_dlm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -546,6 +538,16 @@ - reg = <0 0x151f0000 0 0x8000>; - }; - -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_dlm1: syscon@151f8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151f8000 0 0x2000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>;
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