Delete 108-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit.patch
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@ -1,254 +0,0 @@
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From cfb1aa4c805e58287dd0ce292b5c64309e3dba2f Mon Sep 17 00:00:00 2001
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From: Frank <Frank.Sae@motor-comm.com>
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Date: Wed, 30 Nov 2022 17:49:28 +0800
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Subject: [PATCH] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
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Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
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verified the patch on AM335x platform which has one YT8531 interface
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card and passed all test cases. The tested cases indluding: YT8531 UTP
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function with support of 10M/100M/1000M and wol(based on magic packet).
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Signed-off-by: Frank <Frank.Sae@motor-comm.com>
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---
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drivers/net/phy/Kconfig | 2 +-
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drivers/net/phy/motorcomm.c | 162 ++++++++++++++++++++++++++++++++++--
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2 files changed, 158 insertions(+), 6 deletions(-)
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -334,7 +334,7 @@ config MOTORCOMM_PHY
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tristate "Motorcomm PHYs"
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help
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Enables support for Motorcomm network PHYs.
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- Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs.
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+ Currently supports the YT8511, YT8521, YT8531, YT8531S Gigabit Ethernet PHYs.
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config NATIONAL_PHY
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tristate "National Semiconductor PHYs"
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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- * Motorcomm 8511/8521/8531S PHY driver.
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+ * Motorcomm 8511/8521/8531/8531S PHY driver.
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*
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* Author: Peter Geis <pgwipeout@gmail.com>
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* Author: Frank <Frank.Sae@motor-comm.com>
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@@ -12,8 +12,9 @@
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#include <linux/phy.h>
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#define PHY_ID_YT8511 0x0000010a
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-#define PHY_ID_YT8521 0x0000011A
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-#define PHY_ID_YT8531S 0x4F51E91A
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+#define PHY_ID_YT8521 0x0000011a
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+#define PHY_ID_YT8531 0x4f51e91b
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+#define PHY_ID_YT8531S 0x4f51e91a
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/* YT8521/YT8531S Register Overview
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* UTP Register space | FIBER Register space
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@@ -225,6 +226,9 @@
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#define YT8531S_SYNCE_CFG_REG 0xA012
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#define YT8531S_SCR_SYNCE_ENABLE BIT(6)
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+#define YT8531_SYNCE_CFG_REG 0xA012
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+#define YT8531_SCR_SYNCE_ENABLE BIT(6)
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+
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/* Extended Register end */
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struct yt8521_priv {
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@@ -479,6 +483,77 @@ static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
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return phy_restore_page(phydev, old_page, ret);
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}
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+/**
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+ * yt8531_set_wol() - turn wake-on-lan on or off
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+ * @phydev: a pointer to a &struct phy_device
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+ * @wol: a pointer to a &struct ethtool_wolinfo
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+ *
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+ * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
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+ * and YTPHY_WOL_MACADDR0_REG are common ext reg.
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+ *
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+ * returns 0 or negative errno code
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+ */
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+static int yt8531_set_wol(struct phy_device *phydev,
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+ struct ethtool_wolinfo *wol)
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+{
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+ struct net_device *p_attached_dev;
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+ const u16 mac_addr_reg[] = {
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+ YTPHY_WOL_MACADDR2_REG,
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+ YTPHY_WOL_MACADDR1_REG,
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+ YTPHY_WOL_MACADDR0_REG,
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+ };
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+ const u8 *mac_addr;
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+ u16 mask;
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+ u16 val;
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+ int ret;
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+ u8 i;
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+
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+ if (wol->wolopts & WAKE_MAGIC) {
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+ p_attached_dev = phydev->attached_dev;
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+ if (!p_attached_dev)
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+ return -ENODEV;
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+
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+ mac_addr = (const u8 *)p_attached_dev->dev_addr;
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+ if (!is_valid_ether_addr(mac_addr))
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+ return -EINVAL;
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+
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+ /* Store the device address for the magic packet */
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+ for (i = 0; i < 3; i++) {
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+ ret = ytphy_write_ext(phydev, mac_addr_reg[i],
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+ ((mac_addr[i * 2] << 8)) |
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+ (mac_addr[i * 2 + 1]));
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ /* Enable WOL feature */
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+ mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
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+ val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
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+ val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
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+ ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Enable WOL interrupt */
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+ ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
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+ YTPHY_IER_WOL);
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+ if (ret < 0)
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+ return ret;
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+ } else {
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+ /* Disable WOL feature */
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+ mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
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+ ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
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+
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+ /* Disable WOL interrupt */
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+ ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
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+ YTPHY_IER_WOL, 0);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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static int yt8511_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, YT8511_PAGE_SELECT);
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@@ -651,6 +726,19 @@ static int yt8521_probe(struct phy_device *phydev)
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return 0;
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}
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+/**
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+ * yt8531_probe() - Now only disable SyncE clock output
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+ * @phydev: a pointer to a &struct phy_device
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+ *
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+ * returns 0 or negative errno code
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+ */
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+static int yt8531_probe(struct phy_device *phydev)
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+{
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+ /* Disable SyncE clock output by default */
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+ return ytphy_modify_ext_with_lock(phydev, YT8531_SYNCE_CFG_REG,
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+ YT8531_SCR_SYNCE_ENABLE, 0);
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+}
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+
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/**
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* yt8531s_probe() - read chip config then set suitable polling_mode
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* @phydev: a pointer to a &struct phy_device
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@@ -1192,6 +1280,59 @@ static int yt8521_config_init(struct phy_device *phydev)
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return phy_restore_page(phydev, old_page, ret);
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}
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+/**
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+ * yt8531_config_init() - called to initialize the PHY
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+ * @phydev: a pointer to a &struct phy_device
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+ *
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+ * returns 0 or negative errno code
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+ */
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+static int yt8531_config_init(struct phy_device *phydev)
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+{
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+ int ret;
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+ u16 val;
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+
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+ switch (phydev->interface) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS;
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+ val |= YT8521_RC1R_RX_DELAY_DIS;
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS;
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+ val |= YT8521_RC1R_RX_DELAY_EN;
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN;
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+ val |= YT8521_RC1R_RX_DELAY_DIS;
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN;
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+ val |= YT8521_RC1R_RX_DELAY_EN;
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+ break;
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+ default: /* do not support other modes */
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+ return -EOPNOTSUPP;
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+ }
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+
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+ /* set rgmii delay mode */
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+ ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG,
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+ (YT8521_RC1R_RX_DELAY_MASK |
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+ YT8521_RC1R_FE_TX_DELAY_MASK |
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+ YT8521_RC1R_GE_TX_DELAY_MASK),
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+ val);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* disable auto sleep */
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+ ret = ytphy_modify_ext_with_lock(phydev,
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+ YT8521_EXTREG_SLEEP_CONTROL1_REG,
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+ YT8521_ESC1R_SLEEP_SW, 0);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* enable RXC clock when no wire plug */
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+ return ytphy_modify_ext_with_lock(phydev, YT8521_CLOCK_GATING_REG,
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+ YT8521_CGR_RX_CLK_EN, 0);
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+}
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+
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/**
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* yt8521_prepare_fiber_features() - A small helper function that setup
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* fiber's features.
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@@ -1774,6 +1915,16 @@ static struct phy_driver motorcomm_phy_drvs[] = {
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.suspend = yt8521_suspend,
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.resume = yt8521_resume,
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},
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+ {
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+ PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
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+ .name = "YT8531 Gigabit Ethernet",
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+ .probe = yt8531_probe,
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+ .config_init = yt8531_config_init,
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+ .suspend = genphy_suspend,
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+ .resume = genphy_resume,
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+ .get_wol = ytphy_get_wol,
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+ .set_wol = yt8531_set_wol,
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+ },
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{
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PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
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.name = "YT8531S Gigabit Ethernet",
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@@ -1795,7 +1946,7 @@ static struct phy_driver motorcomm_phy_drvs[] = {
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module_phy_driver(motorcomm_phy_drvs);
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-MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver");
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+MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver");
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MODULE_AUTHOR("Peter Geis");
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MODULE_AUTHOR("Frank");
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MODULE_LICENSE("GPL");
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@@ -1803,8 +1954,9 @@ MODULE_LICENSE("GPL");
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static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
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+ { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
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- { /* sentinal */ }
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+ { /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
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