From f449543c7f6d91d917c9dd660d914ddf39c7645a Mon Sep 17 00:00:00 2001 From: lean Date: Sat, 26 Feb 2022 19:09:49 +0800 Subject: [PATCH] rockchip:fix rk3399 build with kernel 5.15 --- ...ckchip-enable-LAN-port-on-NanoPi-R2S.patch | 60 ++ ...9-Add-support-for-EmbedFire-DoorNet2.patch | 768 ++++++++++++++++++ ...Add-support-for-OrangePi-R1-Plus-LTS.patch | 101 +++ ...-add-driver-for-Rockchip-USB-3.0-PHY.patch | 41 + ...overclock-to-2.2-1.8-GHz-for-NanoPi4.patch | 193 +++++ 5 files changed, 1163 insertions(+) create mode 100644 target/linux/rockchip/patches-5.15/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch create mode 100644 target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch create mode 100644 target/linux/rockchip/patches-5.15/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch create mode 100644 target/linux/rockchip/patches-5.15/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch create mode 100644 target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch diff --git a/target/linux/rockchip/patches-5.15/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.15/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch new file mode 100644 index 000000000..82e2137a8 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch @@ -0,0 +1,60 @@ +From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:12:16 +0200 +Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S + +Enable the USB3 port on the FriendlyARM NanoPi R2S. +This is required for the USB3 attached LAN port to work. + +Signed-off-by: David Bauer +--- + .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -44,6 +44,18 @@ + }; + }; + ++ vcc_rtl8153: vcc-rtl8153-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtl8153_en_drv>; ++ regulator-always-on; ++ regulator-name = "vcc_rtl8153"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; +@@ -273,6 +285,12 @@ + }; + }; + }; ++ ++ usb { ++ rtl8153_en_drv: rtl8153-en-drv { ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &io_domains { +@@ -379,3 +397,12 @@ + &usb_host0_ohci { + status = "okay"; + }; ++ ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch b/target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch new file mode 100644 index 000000000..02e5c74e1 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/205-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch @@ -0,0 +1,768 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-li + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts +@@ -0,0 +1,115 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include "rk3399-doornet2.dtsi" ++ ++/ { ++ model = "EmbedFire DoorNet2"; ++ compatible = "embedfire,doornet2", "rockchip,rk3399"; ++ ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ ++ /delete-node/ display-subsystem; ++ ++ gpio-leds { ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; ++ ++ /delete-node/ status; ++ ++ lan_led: led-lan { ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ label = "green:lan"; ++ }; ++ ++ sys_led: led-sys { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "red:sys"; ++ default-state = "on"; ++ }; ++ ++ wan_led: led-wan { ++ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ label = "green:wan"; ++ }; ++ }; ++ ++ gpio-keys { ++ pinctrl-0 = <&reset_button_pin>; ++ ++ /delete-node/ power; ++ ++ reset { ++ debounce-interval = <50>; ++ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ label = "reset"; ++ linux,code = ; ++ }; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++}; ++ ++&pcie0 { ++ max-link-speed = <1>; ++ num-lanes = <1>; ++ vpcie3v3-supply = <&vcc3v3_sys>; ++ ++ pcie@0 { ++ reg = <0x00000000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ pcie-eth@0,0 { ++ compatible = "realtek,r8168"; ++ reg = <0x000000 0 0 0 0>; ++ ++ realtek,led-data = <0x870>; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ /delete-node/ leds-gpio; ++ ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rockchip-key { ++ /delete-node/ power-key; ++ ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vdd_5v>; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_sys>; ++}; ++ ++ +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi +@@ -0,0 +1,637 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_sys"; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc5v0_sys"; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ /* switched by pmic_sleep */ ++ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_s3"; ++ vin-supply = <&vcc_1v8>; ++ }; ++ ++ vcc3v0_sd: vcc3v0-sd { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_pwr_h>; ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc3v0_sd"; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vbus_typec: vbus-typec { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vbus_typec"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&power_key>; ++ ++ power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "GPIO Key Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ leds: gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_gpio>; ++ ++ status { ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ label = "status_led"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc3v3_s3>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 100000 50000>; ++ tx_delay = <0x13>; ++ rx_delay = <0x0e>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c7>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <160>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpu_b_sleep>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-ramp-delay = <1000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpu_sleep>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vdd_gpu"; ++ regulator-ramp-delay = <1000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ clock-output-names = "xin32k", "rtc_clko_wifi"; ++ #clock-cells = <1>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_3v0>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-name = "vdd_center"; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-name = "vdd_cpu_l"; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_ddr"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_cam: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_cam"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc3v0_touch"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmupll: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc1v8_pmupll"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <3000000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_sdio"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcca3v0_codec"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc_1v5"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_codec"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_3v0"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ clock-frequency = <200000>; ++ i2c-scl-rising-time-ns = <150>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c7 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc_1v8>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vcc_sdio>; ++ gpio1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; ++ assigned-clock-rates = <100000000>; ++ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; ++ max-link-speed = <2>; ++ num-lanes = <4>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ leds_gpio: leds-gpio { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ ethernet-phy { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ pmic { ++ cpu_b_sleep: cpu-b-sleep { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ gpu_sleep: gpu-sleep { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ power_key: power-key { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdio { ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_reg_on_h: bt-reg-on-h { ++ /* external pullup to VCC1V8_PMUPLL */ ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_reg_on_h: wifi-reg_on-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmc { ++ sdmmc0_det_l: sdmmc0-det-l { ++ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ sdmmc0_pwr_h: sdmmc0-pwr-h { ++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v0_sd>; ++ vqmmc-supply = <&vcc_sdio>; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; ++ diff --git a/target/linux/rockchip/patches-5.15/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-5.15/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch new file mode 100644 index 000000000..eabd5bb3b --- /dev/null +++ b/target/linux/rockchip/patches-5.15/206-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch @@ -0,0 +1,101 @@ +From 9f0bfe430a5a67b34bc2274a898b4375a321810b Mon Sep 17 00:00:00 2001 +From: baiywt +Date: Mon, 15 Nov 2021 16:51:43 +0800 +Subject: [PATCH] Add support for OrangePi R1 Plus LTS + +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 44 +++++++++++++++++++ + 2 files changed, 45 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 23373c752..552d97555 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -5,6 +5,7 @@ + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +new file mode 100644 +index 000000000..c65f7c417 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++#include "rk3328-orangepi-r1-plus.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus LTS"; ++ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; ++}; ++ ++/delete-node/ &rtl8211e; ++&gmac2io { ++ phy-handle = <ðphy3>; ++ snps,reset-delays-us = <0 15000 50000>; ++ tx_delay = <0x19>; ++ rx_delay = <0x05>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy3: ethernet-phy@0 { ++ reg = <0x0>; ++ keep-clkout-on; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_io_sdio>; ++ status = "okay"; ++}; ++ ++&dmc_opp_table { ++ opp-1056000000 { ++ status = "disabled"; ++ }; ++ opp-924000000 { ++ status = "disabled"; ++ }; ++ opp-840000000 { ++ status = "disabled"; ++ }; ++ opp-798000000 { ++ status = "disabled"; ++ }; ++}; ++ ++&sys_led { ++ label = "orangepi-r1-plus-lts:red:sys"; ++}; ++ ++&wan_led { ++ label = "orangepi-r1-plus-lts:green:wan"; ++}; ++ ++&lan_led { ++ label = "orangepi-r1-plus-lts:green:lan"; ++}; +-- +2.25.1 diff --git a/target/linux/rockchip/patches-5.15/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch b/target/linux/rockchip/patches-5.15/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch new file mode 100644 index 000000000..5ff87a5b4 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch @@ -0,0 +1,41 @@ +From faa767a9d0ced5642da0ae50b53d87de258f9525 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Tue, 19 Nov 2019 17:24:30 +0800 +Subject: [PATCH] phy: rockchip: add driver for Rockchip USB 3.0 PHY + +Signed-off-by: hmz007 +--- + drivers/phy/rockchip/Kconfig | 8 + + drivers/phy/rockchip/Makefile | 1 + + drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1175 +++++++++++++++++ + 3 files changed, 1184 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c + +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -56,6 +56,15 @@ config PHY_ROCKCHIP_INNO_DSIDPHY + Enable this to support the Rockchip MIPI/LVDS/TTL PHY with + Innosilicon IP block. + ++config PHY_ROCKCHIP_INNO_USB3 ++ tristate "Rockchip INNO USB 3.0 PHY Driver" ++ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF ++ depends on USB_SUPPORT ++ select GENERIC_PHY ++ select USB_PHY ++ help ++ Support for Rockchip USB 3.0 PHY with Innosilicon IP block. ++ + config PHY_ROCKCHIP_PCIE + tristate "Rockchip PCIe PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy- + obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o ++obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o + obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o + obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch b/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch new file mode 100644 index 000000000..ba31f0751 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch @@ -0,0 +1,193 @@ +From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 19 Dec 2020 12:42:27 +0000 +Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices + +It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, +and for better performance. + +Signed-off-by: Tianling Shen +Co-authored-by: gzelvis +--- + .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++ + .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- + 2 files changed, 157 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi +@@ -0,0 +1,152 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * Copyright (c) 2020 Tianling Shen ++ * Copyright (c) 2020 gzelvis ++ */ ++ ++/ { ++ cluster0_opp: opp-table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1000000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1125000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1225000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1275000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1025000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1100000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1200000>; ++ }; ++ opp08 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1250000>; ++ }; ++ opp09 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1325000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <297000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +@@ -14,7 +14,7 @@ + /dts-v1/; + #include + #include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" ++#include "rk3399-nanopi4-opp.dtsi" + + / { + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi +@@ -3,7 +3,7 @@ + /dts-v1/; + #include + #include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" ++#include "rk3399-nanopi4-opp.dtsi" + + / { + chosen {