171 lines
5.6 KiB
Diff
171 lines
5.6 KiB
Diff
From f581e7b004d0d997acc1f0fa5b2c454f90f0b2de Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 12 May 2021 18:49:30 +0200
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Subject: [PATCH] arm64: dts: ipq8074: add networking nodes
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Add networking nodes required for SSDK and NSS-DP.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 150 ++++++++++++++++++++++++++
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1 file changed, 150 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -899,5 +899,155 @@
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};
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};
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};
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+
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+ ess_switch: ess-switch@3a000000 {
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+ compatible = "qcom,ess-switch-ipq807x";
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+ reg = <0x3a000000 0x1000000>;
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+ switch_access_mode = "local bus";
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+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
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+ switch_inner_bmp = <0x80>; /*inner port bitmap*/
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+ mdio-bus = <&mdio>;
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+ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
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+ <&gcc GCC_CMN_12GPLL_SYS_CLK>,
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+ <&gcc GCC_UNIPHY0_AHB_CLK>,
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+ <&gcc GCC_UNIPHY0_SYS_CLK>,
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+ <&gcc GCC_UNIPHY1_AHB_CLK>,
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+ <&gcc GCC_UNIPHY1_SYS_CLK>,
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+ <&gcc GCC_UNIPHY2_AHB_CLK>,
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+ <&gcc GCC_UNIPHY2_SYS_CLK>,
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+ <&gcc GCC_PORT1_MAC_CLK>,
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+ <&gcc GCC_PORT2_MAC_CLK>,
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+ <&gcc GCC_PORT3_MAC_CLK>,
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+ <&gcc GCC_PORT4_MAC_CLK>,
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+ <&gcc GCC_PORT5_MAC_CLK>,
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+ <&gcc GCC_PORT6_MAC_CLK>,
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+ <&gcc GCC_NSS_PPE_CLK>,
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+ <&gcc GCC_NSS_PPE_CFG_CLK>,
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+ <&gcc GCC_NSSNOC_PPE_CLK>,
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+ <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
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+ <&gcc GCC_NSS_EDMA_CLK>,
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+ <&gcc GCC_NSS_EDMA_CFG_CLK>,
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+ <&gcc GCC_NSS_PPE_IPE_CLK>,
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+ <&gcc GCC_NSS_PPE_BTQ_CLK>,
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+ <&gcc GCC_NSS_NOC_CLK>,
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+ <&gcc GCC_NSSNOC_SNOC_CLK>,
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+ <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
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+ <&gcc GCC_NSS_CRYPTO_CLK>,
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+ <&gcc GCC_NSS_IMEM_CLK>,
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+ <&gcc GCC_NSS_PTP_REF_CLK>,
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+ <&gcc GCC_NSS_PORT1_RX_CLK>,
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+ <&gcc GCC_NSS_PORT1_TX_CLK>,
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+ <&gcc GCC_NSS_PORT2_RX_CLK>,
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+ <&gcc GCC_NSS_PORT2_TX_CLK>,
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+ <&gcc GCC_NSS_PORT3_RX_CLK>,
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+ <&gcc GCC_NSS_PORT3_TX_CLK>,
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+ <&gcc GCC_NSS_PORT4_RX_CLK>,
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+ <&gcc GCC_NSS_PORT4_TX_CLK>,
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+ <&gcc GCC_NSS_PORT5_RX_CLK>,
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+ <&gcc GCC_NSS_PORT5_TX_CLK>,
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+ <&gcc GCC_NSS_PORT6_RX_CLK>,
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+ <&gcc GCC_NSS_PORT6_TX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
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+ <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
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+ <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
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+ <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
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+ <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
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+ <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
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+ <&gcc NSS_PORT5_RX_CLK_SRC>,
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+ <&gcc NSS_PORT5_TX_CLK_SRC>;
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+ clock-names = "cmn_ahb_clk", "cmn_sys_clk",
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+ "uniphy0_ahb_clk", "uniphy0_sys_clk",
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+ "uniphy1_ahb_clk", "uniphy1_sys_clk",
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+ "uniphy2_ahb_clk", "uniphy2_sys_clk",
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+ "port1_mac_clk", "port2_mac_clk",
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+ "port3_mac_clk", "port4_mac_clk",
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+ "port5_mac_clk", "port6_mac_clk",
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+ "nss_ppe_clk", "nss_ppe_cfg_clk",
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+ "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
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+ "nss_edma_clk", "nss_edma_cfg_clk",
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+ "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
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+ "gcc_nss_noc_clk",
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+ "gcc_nssnoc_snoc_clk",
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+ "gcc_mem_noc_nss_axi_clk",
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+ "gcc_nss_crypto_clk",
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+ "gcc_nss_imem_clk",
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+ "gcc_nss_ptp_ref_clk",
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+ "nss_port1_rx_clk", "nss_port1_tx_clk",
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+ "nss_port2_rx_clk", "nss_port2_tx_clk",
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+ "nss_port3_rx_clk", "nss_port3_tx_clk",
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+ "nss_port4_rx_clk", "nss_port4_tx_clk",
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+ "nss_port5_rx_clk", "nss_port5_tx_clk",
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+ "nss_port6_rx_clk", "nss_port6_tx_clk",
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+ "uniphy0_port1_rx_clk",
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+ "uniphy0_port1_tx_clk",
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+ "uniphy0_port2_rx_clk",
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+ "uniphy0_port2_tx_clk",
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+ "uniphy0_port3_rx_clk",
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+ "uniphy0_port3_tx_clk",
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+ "uniphy0_port4_rx_clk",
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+ "uniphy0_port4_tx_clk",
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+ "uniphy0_port5_rx_clk",
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+ "uniphy0_port5_tx_clk",
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+ "uniphy1_port5_rx_clk",
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+ "uniphy1_port5_tx_clk",
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+ "uniphy2_port6_rx_clk",
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+ "uniphy2_port6_tx_clk",
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+ "nss_port5_rx_clk_src",
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+ "nss_port5_tx_clk_src";
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+ resets = <&gcc GCC_PPE_FULL_RESET>,
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+ <&gcc GCC_UNIPHY0_SOFT_RESET>,
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+ <&gcc GCC_UNIPHY0_XPCS_RESET>,
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+ <&gcc GCC_UNIPHY1_SOFT_RESET>,
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+ <&gcc GCC_UNIPHY1_XPCS_RESET>,
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+ <&gcc GCC_UNIPHY2_SOFT_RESET>,
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+ <&gcc GCC_UNIPHY2_XPCS_RESET>,
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+ <&gcc GCC_NSSPORT1_RESET>,
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+ <&gcc GCC_NSSPORT2_RESET>,
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+ <&gcc GCC_NSSPORT3_RESET>,
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+ <&gcc GCC_NSSPORT4_RESET>,
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+ <&gcc GCC_NSSPORT5_RESET>,
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+ <&gcc GCC_NSSPORT6_RESET>;
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+ reset-names = "ppe_rst", "uniphy0_soft_rst",
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+ "uniphy0_xpcs_rst", "uniphy1_soft_rst",
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+ "uniphy1_xpcs_rst", "uniphy2_soft_rst",
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+ "uniphy2_xpcs_rst", "nss_port1_rst",
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+ "nss_port2_rst", "nss_port3_rst",
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+ "nss_port4_rst", "nss_port5_rst",
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+ "nss_port6_rst";
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+ };
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+
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+ ess-uniphy@7a00000 {
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+ compatible = "qcom,ess-uniphy";
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+ reg = <0x7a00000 0x30000>;
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+ uniphy_access_mode = "local bus";
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+ };
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+
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+ edma@3ab00000 {
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+ compatible = "qcom,edma";
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+ reg = <0x3ab00000 0x76900>;
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+ reg-names = "edma-reg-base";
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+ qcom,txdesc-ring-start = <23>;
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+ qcom,txdesc-rings = <1>;
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+ qcom,txcmpl-ring-start = <7>;
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+ qcom,txcmpl-rings = <1>;
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+ qcom,rxfill-ring-start = <7>;
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+ qcom,rxfill-rings = <1>;
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+ qcom,rxdesc-ring-start = <15>;
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+ qcom,rxdesc-rings = <1>;
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+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&gcc GCC_EDMA_HW_RESET>;
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+ reset-names = "edma_rst";
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+ };
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};
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};
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