43 lines
1.7 KiB
Diff
43 lines
1.7 KiB
Diff
From cb272395dceef1652247dad08a50ed4153ffbd43 Mon Sep 17 00:00:00 2001
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From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
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Date: Fri, 12 Jun 2020 13:28:16 +0530
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Subject: [PATCH] mtd: rawnand: qcom: set BAM mode only if not set already
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BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
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is set by writing BAM_MODE_EN bit on NAND_CTRL register.
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NAND_CTRL is an operational register and in BAM mode operational
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registers are read only.
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So, before enabling BAM mode by writing the NAND_CTRL register, check
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if BAM mode was already enabled by the bootloader, and enable BAM mode
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only if it is not enabled already.
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Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/1591948696-16015-3-git-send-email-sivaprak@codeaurora.org
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -2761,7 +2761,16 @@ static int qcom_nandc_setup(struct qcom_
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/* enable ADM or BAM DMA */
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if (nandc->props->is_bam) {
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nand_ctrl = nandc_read(nandc, NAND_CTRL);
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- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
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+
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+ /*
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+ *NAND_CTRL is an operational registers, and CPU
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+ * access to operational registers are read only
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+ * in BAM mode. So update the NAND_CTRL register
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+ * only if it is not in BAM mode. In most cases BAM
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+ * mode will be enabled in bootloader
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+ */
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+ if (!(nand_ctrl & BAM_MODE_EN))
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+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
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} else {
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nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
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}
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