41 lines
1.7 KiB
Diff
41 lines
1.7 KiB
Diff
From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001
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From: Andrew Powers-Holmes <aholmes@omnom.net>
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Date: Sat, 12 Nov 2022 22:41:26 +1100
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Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and
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range mappings
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The register and range mappings for the PCIe controller in Rockchip's
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RK356x SoCs are incorrect. Replace them with corrected values from the
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vendor BSP sources, updated to match current DT schema.
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Tested-by: Ondrej Jirman <megi@xff.cz>
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Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
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2 files changed, 12 insertions(+), 9 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -952,7 +952,7 @@
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0000000 0x0 0x00400000>,
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<0x0 0xfe260000 0x0 0x00010000>,
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- <0x3 0x3f000000 0x0 0x01000000>;
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+ <0x0 0xf4000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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@@ -982,8 +982,9 @@
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phys = <&combphy2 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3568_PD_PIPE>;
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- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
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- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
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+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
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+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
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+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
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resets = <&cru SRST_PCIE20_POWERUP>;
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reset-names = "pipe";
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#address-cells = <3>;
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