Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

include/kernel.mk

@@ -90,6 +90,8 @@ else ifneq (,$(findstring $(ARCH) , mipsel mips64 mips64el ))
   LINUX_KARCH := mips
 else ifneq (,$(findstring $(ARCH) , powerpc64 ))
   LINUX_KARCH := powerpc
+else ifneq (,$(findstring $(ARCH) , riscv64 ))
+  LINUX_KARCH := riscv
 else ifneq (,$(findstring $(ARCH) , sh2 sh3 sh4 ))
   LINUX_KARCH := sh
 else ifneq (,$(findstring $(ARCH) , i386 x86_64 ))

include/prereq-build.mk

@@ -94,6 +94,10 @@ $(eval $(call TestHostCommand,perl-thread-queue, \
 	Please install the Perl Thread::Queue module, \
 	perl -MThread::Queue -e 1))
 
+$(eval $(call TestHostCommand,perl-ipc-cmd, \
+	Please install the Perl IPC:Cmd module, \
+	perl -MIPC::Cmd -e 1))
+
 $(eval $(call SetupHostCommand,tar,Please install GNU 'tar', \
 	gtar --version 2>&1 | grep GNU, \
 	gnutar --version 2>&1 | grep GNU, \

include/site/riscv64

@@ -0,0 +1,30 @@
+#!/bin/sh
+. $TOPDIR/include/site/linux
+ac_cv_c_littleendian=${ac_cv_c_littleendian=yes}
+ac_cv_c_bigendian=${ac_cv_c_bigendian=no}
+
+ac_cv_sizeof___int64=8
+ac_cv_sizeof_char=1
+ac_cv_sizeof_int=4
+ac_cv_sizeof_int16_t=2
+ac_cv_sizeof_int32_t=4
+ac_cv_sizeof_int64_t=8
+ac_cv_sizeof_long_int=8
+ac_cv_sizeof_long_long=8
+ac_cv_sizeof_long=8
+ac_cv_sizeof_off_t=8
+ac_cv_sizeof_short_int=2
+ac_cv_sizeof_short=2
+ac_cv_sizeof_size_t=8
+ac_cv_sizeof_ssize_t=8
+ac_cv_sizeof_u_int16_t=2
+ac_cv_sizeof_u_int32_t=4
+ac_cv_sizeof_u_int64_t=8
+ac_cv_sizeof_uint16_t=2
+ac_cv_sizeof_uint32_t=4
+ac_cv_sizeof_uint64_t=8
+ac_cv_sizeof_unsigned_int=4
+ac_cv_sizeof_unsigned_long=8
+ac_cv_sizeof_unsigned_long_long=8
+ac_cv_sizeof_unsigned_short=2
+ac_cv_sizeof_void_p=8

include/target.mk

@@ -276,6 +276,10 @@ ifeq ($(DUMP),1)
     CPU_CFLAGS_arc700 = -mcpu=arc700
     CPU_CFLAGS_archs = -mcpu=archs
   endif
+  ifeq ($(ARCH),riscv64)
+    CPU_TYPE ?= riscv64
+    CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc
+  endif
   ifneq ($(CPU_TYPE),)
     ifndef CPU_CFLAGS_$(CPU_TYPE)
       $(warning CPU_TYPE "$(CPU_TYPE)" doesn't correspond to a known type)

package/boot/opensbi/Makefile

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2022 OpenWrt.org
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=opensbi
+PKG_RELEASE:=1.2
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL=https://github.com/riscv/opensbi
+PKG_SOURCE_DATE:=2022-12-24
+PKG_SOURCE_VERSION:=6b5188ca14e59ce7bf71afe4e7d3d557c3d31bf8
+PKG_MIRROR_HASH:=edcdd99da6c62975171981c0aa2b73a27091067da11ccd49816b5ad27d000858
+
+PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_TARGETS:=bin
+PKG_FLAGS:=nonshared
+PKG_LICENSE:=BSD-2-Clause
+PKG_LICENSE_FILES:=COPYING.BSD
+PKG_BUILD_PARALLEL:=1
+
+PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/opensbi
+    SECTION:=boot
+    CATEGORY:=Boot Loaders
+    DEPENDS:=@TARGET_sifiveu
+    URL:=https://github.com/riscv/opensbi/blob/master/README.md
+    VARIANT:=$(subst _,/,$(subst opensbi_,,$(1)))
+    TITLE:=OpenSBI generic
+    OPENSBI_IMAGE:=
+    PLAT:=
+endef
+
+define Package/opensbi_generic
+  $(Package/opensbi)
+  TITLE:=OpenSBI generic
+  OPENSBI_IMAGE:=fw_dynamic.bin
+  PLAT:=generic
+endef
+
+export GCC_HONOUR_COPTS=s
+
+MAKE_VARS = \
+	CROSS_COMPILE="$(TARGET_CROSS)"
+
+define Build/Compile
+	$(eval $(Package/opensbi_$(BUILD_VARIANT))) \
+		+$(MAKE_VARS) $(MAKE) -C $(PKG_BUILD_DIR) \
+		PLATFORM=$(PLAT)
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+	$(CP) $(PKG_BUILD_DIR)/build/platform/$(PLAT)/firmware/fw_dynamic.bin $(STAGING_DIR_IMAGE)/fw_dynamic-${BUILD_VARIANT}.bin
+endef
+
+$(eval $(call BuildPackage,opensbi_generic))

package/boot/uboot-layerscape/files/fsl_ls1012a-frwy-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0x8fffffff
 initrd_high=0xffffffffffffffff
 sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr

package/boot/uboot-layerscape/files/fsl_ls1012a-rdb-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr
 bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)

package/boot/uboot-layerscape/files/fsl_ls1021a-iot-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0x8fffffff
 initrd_high=0xffffffff
 sd_boot=ext4load mmc 0:1 ${loadaddr} fitImage;bootm ${loadaddr}

package/boot/uboot-layerscape/files/fsl_ls1021a-twr-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0x8fffffff
 initrd_high=0xffffffff
 sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr

package/boot/uboot-layerscape/files/fsl_ls1021a-twr-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 nor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr
 bootargs=root=/dev/mtdblock6 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(rcw),2m(u-boot),1m(u-boot-env),11m(reserved-1),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) cma=64M@0x0-0xb0000000

package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0x8fffffff
 initrd_high=0xffffffffffffffff
 hwconfig=fsl_ddr:bank_intlv=auto

package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 hwconfig=fsl_ddr:bank_intlv=auto
 nor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr

package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 hwconfig=fsl_ddr:bank_intlv=auto
 sd_boot=ext4load mmc 0:1 ${loadaddr} fitImage;bootm ${loadaddr}

package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 hwconfig=fsl_ddr:bank_intlv=auto
 qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr

package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0x8fffffff
 initrd_high=0xffffffffffffffff
 hwconfig=fsl_ddr:bank_intlv=auto

package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 hwconfig=fsl_ddr:bank_intlv=auto
 qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr

package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0xa0000000
 initrd_high=0xffffffffffffffff
 hwconfig=fsl_ddr:bank_intlv=auto

package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0xa0000000
 initrd_high=0xffffffffffffffff
 hwconfig=fsl_ddr:bank_intlv=auto

package/boot/uboot-layerscape/files/fsl_ls2088a-rdb-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 fdt_high=0xa0000000
 initrd_high=0xffffffffffffffff
 hwconfig=fsl_ddr:bank_intlv=auto

package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-sdboot-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 hwconfig=fsl_ddr:bank_intlv=auto
 mc_init=mmc read 80000000 5000 1800;mmc read 80300000 7000 800;fsl_mc start mc 80000000 80300000;mmc read 80400000 6800 800;fsl_mc apply dpl 80400000

package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-uEnv.txt

@@ -1,5 +1,5 @@
 fdtaddr=0x8f000000
-loadaddr=0x81000000
+loadaddr=0x88000000
 bootm_size=0x10000000
 hwconfig=fsl_ddr:bank_intlv=auto
 mc_init=sf probe 0:0;sf read 80000000 a00000 300000;sf read 80300000 e00000 100000;fsl_mc start mc 80000000 80300000;sf read 80400000 d00000 100000;fsl_mc apply dpl 80400000

package/boot/uboot-sifiveu/Makefile

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2022 OpenWrt.org
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_RELEASE:=1
+PKG_VERSION:=2022.10
+PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
+
+define U-Boot/Default
+  BUILD_TARGET:=sifiveu
+  BUILD_DEVICES=$(1)
+  UBOOT_IMAGE:=u-boot.itb
+  DTS_DIR:=arch/riscv/dts
+  UENV:=default
+  DEFAULT:=y
+endef
+
+define U-Boot/sifive_unleashed
+  NAME:=SiFive Unleashed
+  OPENSBI:=generic
+  DEPENDS:=+opensbi_generic
+  UBOOT_DTS:=hifive-unleashed-a00.dtb
+  BUILD_DEVICES:=sifive_unleashed
+endef
+
+define U-Boot/sifive_unmatched
+  NAME:=SiFive Unmatched
+  OPENSBI:=generic
+  DEPENDS:=+opensbi_generic
+  UBOOT_DTS:=hifive-unmatched-a00.dtb
+  BUILD_DEVICES:=sifive_unmatched
+endef
+
+UBOOT_TARGETS := \
+	sifive_unleashed \
+	sifive_unmatched
+
+UBOOT_MAKE_FLAGS += \
+        OPENSBI=$(STAGING_DIR_IMAGE)/fw_dynamic-${OPENSBI}.bin
+
+define Build/Configure
+	$(call Build/Configure/U-Boot)
+	sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
+endef
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/spl/u-boot-spl.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)-spl
+	$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS)
+
+	mkimage -C none -A arm -T script -d uEnv-$(UENV).txt \
+		$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr
+endef
+
+$(eval $(call BuildPackage/U-Boot))

package/boot/uboot-sifiveu/patches/0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch

@@ -0,0 +1,104 @@
+From 725595e667cc4423347c255da8ca4c5b3aa0980a Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Mon, 15 Nov 2021 03:31:04 -0800
+Subject: [PATCH 2/8] board: sifive: spl: Initialized the PWM setting in the
+ SPL stage
+
+LEDs and multiple fans can be controlled by SPL. This patch ensures
+that all fans have been enabled in the SPL stage. In addition, the
+LED's color will be set to yellow.
+---
+ board/sifive/unmatched/Makefile |  1 +
+ board/sifive/unmatched/pwm.c    | 57 +++++++++++++++++++++++++++++++++
+ board/sifive/unmatched/spl.c    |  2 ++
+ 3 files changed, 60 insertions(+)
+ create mode 100644 board/sifive/unmatched/pwm.c
+
+diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
+index 1345330089..5df01982e9 100644
+--- a/board/sifive/unmatched/Makefile
++++ b/board/sifive/unmatched/Makefile
+@@ -9,3 +9,4 @@ obj-y += spl.o
+ else
+ obj-y += unmatched.o
+ endif
++obj-y += pwm.o
+diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
+new file mode 100644
+index 0000000000..e1cc02310a
+--- /dev/null
++++ b/board/sifive/unmatched/pwm.c
+@@ -0,0 +1,57 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (c) 2021, SiFive Inc
++ *
++ * Authors:
++ *   Vincent Chen <vincent.chen@sifive.com>
++ *   David Abdurachmanov <david.abdurachmanov@sifive.com>
++ */
++
++#include <linux/io.h>
++#include <asm/arch/eeprom.h>
++
++struct pwm_sifive_regs {
++	unsigned int cfg;	/* PWM configuration register */
++	unsigned int pad0;	/* Reserved */
++	unsigned int cnt;	/* PWM count register */
++	unsigned int pad1;	/* Reserved */
++	unsigned int pwms;	/* Scaled PWM count register */
++	unsigned int pad2;	/* Reserved */
++	unsigned int pad3;	/* Reserved */
++	unsigned int pad4;	/* Reserved */
++	unsigned int cmp0;	/* PWM 0 compare register */
++	unsigned int cmp1;	/* PWM 1 compare register */
++	unsigned int cmp2;	/* PWM 2 compare register */
++	unsigned int cmp3;	/* PWM 3 compare register */
++};
++
++#define PWM0_BASE		0x10020000
++#define PWM1_BASE		0x10021000
++#define PWM_CFG_INIT		0x1000
++#define PWM_CMP_ENABLE_VAL	0x0
++#define PWM_CMP_DISABLE_VAL	0xffff
++
++void pwm_device_init(void)
++{
++	struct pwm_sifive_regs *pwm0, *pwm1;
++	pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
++	pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
++	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
++	/* Set the 3-color PWM LEDs to yellow in SPL */
++	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
++	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
++	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
++	writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
++
++	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
++	/* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
++	/* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
++	   so here sets the initial value of PWM_COMP0 as DISABLE */
++	if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
++		writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
++	else
++		writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
++	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
++	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
++	writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
++}
+diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
+index 7c0beedc08..f3a661a81e 100644
+--- a/board/sifive/unmatched/spl.c
++++ b/board/sifive/unmatched/spl.c
+@@ -90,6 +90,8 @@ int spl_board_init_f(void)
+ 		goto end;
+ 	}
+ 
++	pwm_device_init();
++
+ 	ret = spl_gemgxl_init();
+ 	if (ret) {
+ 		debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
+-- 
+2.27.0
+

package/boot/uboot-sifiveu/patches/0003-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch

@@ -0,0 +1,68 @@
+From 7ead6d662a2f9d8498af6650ea38418c64b52048 Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Mon, 24 Jan 2022 02:42:02 -0800
+Subject: [PATCH 3/8] board: sifive: Set LED's color to purple in the U-boot
+ stage
+
+Set LED's color to purple in the U-boot stage. Because there are still
+some functions to be executed before board_early_init_f(), it means
+the LED's is not changed to purple instantly when entering the U-boot
+stage.
+---
+ board/sifive/unmatched/pwm.c       | 7 +++++++
+ board/sifive/unmatched/unmatched.c | 6 ++++++
+ configs/sifive_unmatched_defconfig | 1 +
+ 3 files changed, 14 insertions(+)
+
+diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
+index e1cc02310a..bd67672c22 100644
+--- a/board/sifive/unmatched/pwm.c
++++ b/board/sifive/unmatched/pwm.c
+@@ -36,6 +36,7 @@ void pwm_device_init(void)
+ 	struct pwm_sifive_regs *pwm0, *pwm1;
+ 	pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+ 	pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
++#ifdef CONFIG_SPL_BUILD
+ 	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+ 	/* Set the 3-color PWM LEDs to yellow in SPL */
+ 	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+@@ -54,4 +55,10 @@ void pwm_device_init(void)
+ 	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+ 	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+ 	writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
++#else
++	/* Set the 3-color PWM LEDs to purple in U-boot */
++	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp1);
++	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
++	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp3);
++#endif
+ }
+diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
+index 6295deeae2..30c082d001 100644
+--- a/board/sifive/unmatched/unmatched.c
++++ b/board/sifive/unmatched/unmatched.c
+@@ -22,6 +22,12 @@ void *board_fdt_blob_setup(int *err)
+ 	return (ulong *)&_end;
+ }
+ 
++int board_early_init_f(void)
++{
++	pwm_device_init();
++	return 0;
++}
++
+ int board_init(void)
+ {
+ 	/* enable all cache ways */
+diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
+index d400ed0b23..0758f8e90f 100644
+--- a/configs/sifive_unmatched_defconfig
++++ b/configs/sifive_unmatched_defconfig
+@@ -51,3 +51,4 @@ CONFIG_DM_SCSI=y
+ CONFIG_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_PCI=y
++CONFIG_BOARD_EARLY_INIT_F=y
+-- 
+2.27.0
+

package/boot/uboot-sifiveu/patches/0004-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch

@@ -0,0 +1,30 @@
+From 6ef7023c0dcfde320015ab19e0e0d423921be77d Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Mon, 15 Nov 2021 03:39:07 -0800
+Subject: [PATCH 1/2] board: sifive: Set LED's color to blue before jumping to
+ Linux
+
+The LED's color wil be changed from purple to blue before executing
+the sysboot command. Because the sysboot command includes the image loading
+from the boot partition, It means the LED's color is blue when executing
+"Retrieving file: /Image.gz".
+---
+ include/configs/sifive-unmatched.h | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/include/configs/sifive-unmatched.h
++++ b/include/configs/sifive-unmatched.h
+@@ -49,7 +49,12 @@
+ 	"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+ 	"partitions=" PARTS_DEFAULT "\0" \
+ 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+-	BOOTENV
++	"setled_blue=mw.l 0x10020024 0x0000ffff; mw.l 0x10020028 0x0000ffff; mw.l 0x1002002c 0x0\0" \
++	BOOTENV \
++	"boot_extlinux=" \
++		"run setled_blue; " \
++		"sysboot ${devtype} ${devnum}:${distro_bootpart} any " \
++			"${scriptaddr} ${prefix}${boot_syslinux_conf};\0"
+ 
+ #define CONFIG_SYS_EEPROM_BUS_NUM		0
+ 

package/boot/uboot-sifiveu/patches/0005-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch

@@ -0,0 +1,111 @@
+From 07f84ed283b913cbdf87181ae2ed65467d923df5 Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Mon, 24 Jan 2022 02:57:40 -0800
+Subject: [PATCH 2/2] board: sifive: spl: Set remote thermal of TMP451 to 85
+ deg C for the unmatched board
+
+For TMP451 on the unmatched board, the default value of the remote
+thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL.
+---
+ board/sifive/unmatched/spl.c       | 29 +++++++++++++++++++++++++++++
+ drivers/misc/Kconfig               | 10 ++++++++++
+ include/configs/sifive-unmatched.h |  4 ++++
+ scripts/config_whitelist.txt       |  1 +
+ 4 files changed, 44 insertions(+)
+
+--- a/board/sifive/unmatched/spl.c
++++ b/board/sifive/unmatched/spl.c
+@@ -10,6 +10,8 @@
+ #include <spl.h>
+ #include <misc.h>
+ #include <log.h>
++#include <config.h>
++#include <i2c.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <asm/gpio.h>
+@@ -26,6 +28,27 @@
+ #define MODE_SELECT_SD		0xb
+ #define MODE_SELECT_MASK	GENMASK(3, 0)
+ 
++#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET	0x19
++#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE	0x55
++
++static inline int init_tmp451_remote_therm_limit(void)
++{
++	struct udevice *dev;
++	unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE;
++	int ret;
++
++	ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM,
++				      CONFIG_SYS_I2C_TMP451_ADDR,
++				      CONFIG_SYS_I2C_TMP451_ADDR_LEN,
++				      &dev);
++
++	if (!ret)
++		ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET,
++				   &r_therm_limit,
++				   sizeof(unsigned char));
++	return ret;
++}
++
+ static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
+ {
+ 	int ret;
+@@ -92,6 +115,12 @@ int spl_board_init_f(void)
+ 
+ 	pwm_device_init();
+ 
++	ret = init_tmp451_remote_therm_limit();
++	if (ret) {
++		debug("TMP451 remote THERM limit init failed: %d\n", ret);
++		goto end;
++	}
++
+ 	ret = spl_gemgxl_init();
+ 	if (ret) {
+ 		debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -536,8 +536,18 @@ config SYS_I2C_EEPROM_ADDR
+ 	depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
+ 	default 0
+ 
++config SYS_I2C_TMP451_ADDR
++	hex "Chip address of the TMP451 device"
++	default 0
++
+ if I2C_EEPROM
+ 
++config SYS_I2C_TMP451_ADDR_LEN
++	int "Length in bytes of the TMP451 memory array address"
++	default 1
++	help
++	  Note: This is NOT the chip address length!
++
+ config SYS_I2C_EEPROM_ADDR_OVERFLOW
+ 	hex "EEPROM Address Overflow"
+ 	default 0x0
+--- a/include/configs/sifive-unmatched.h
++++ b/include/configs/sifive-unmatched.h
+@@ -15,6 +15,10 @@
+ 
+ #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
+ 
++#define CONFIG_SYS_TMP451_BUS_NUM	0
++#define CONFIG_SYS_I2C_TMP451_ADDR	0x4c
++#define CONFIG_SYS_I2C_TMP451_ADDR_LEN	0x1
++
+ /* Environment options */
+ 
+ #define BOOT_TARGET_DEVICES(func) \
+--- a/scripts/config_whitelist.txt
++++ b/scripts/config_whitelist.txt
+@@ -1268,6 +1268,7 @@ CONFIG_SYS_TIMER_BASE
+ CONFIG_SYS_TIMER_COUNTER
+ CONFIG_SYS_TIMER_COUNTS_DOWN
+ CONFIG_SYS_TIMER_RATE
++CONFIG_SYS_TMP451_BUS_NUM
+ CONFIG_SYS_TMPVIRT
+ CONFIG_SYS_TSEC1_OFFSET
+ CONFIG_SYS_TX_ETH_BUFFER

package/boot/uboot-sifiveu/patches/0008-riscv-dts-Add-few-PMU-events.patch

@@ -0,0 +1,36 @@
+From c29e4d84cfa17ab96eff2a9044f486ba3c8b5c43 Mon Sep 17 00:00:00 2001
+From: Atish Patra <atish.patra@wdc.com>
+Date: Mon, 25 Oct 2021 11:35:41 -0700
+Subject: [PATCH] riscv: dts: Add few PMU events
+
+fu740 has 2 HPM counters and many HPM events defined in the fu740 manual[1].
+This patch adds some of these events and their mapping as per the
+OpenSBI PMU DT binding for now.
+
+[1]https://sifive.cdn.prismic.io/sifive/de1491e5-077c-461d-9605-e8a0ce57337d_fu740-c000-manual-v1p3.pdf
+
+Signed-off-by: Atish Patra <atish.patra@wdc.com>
+---
+ arch/riscv/dts/fu740-c000.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/riscv/dts/fu740-c000.dtsi
++++ b/arch/riscv/dts/fu740-c000.dtsi
+@@ -140,6 +140,17 @@
+ 		#size-cells = <2>;
+ 		compatible = "simple-bus";
+ 		ranges;
++		pmu {
++			compatible = "riscv,pmu";
++			riscv,raw-event-to-mhpmcounters = <0x00000000 0x200 0x18
++							 0x00000000 0x400 0x18
++							 0x00000000 0x800 0x18>;
++			riscv,event-to-mhpmcounters = <0x05 0x06 0x18
++						     0x10009 0x10009 0x18>;
++			riscv,event-to-mhpmevent = <0x05 0x00000000 0x4000
++						  0x06 0x00000000 0x4001
++						  0x10008 0x00000000 0x102>;
++		};
+ 		plic0: interrupt-controller@c000000 {
+ 			#interrupt-cells = <1>;
+ 			#address-cells = <0>;

package/boot/uboot-sifiveu/patches/0009-riscv-Fix-build-against-binutils.patch

@@ -0,0 +1,50 @@
+commit 1dde977518f13824b847e23275001191139bc384
+Author: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Date:   Mon Oct 3 18:07:54 2022 +0200
+
+    riscv: Fix build against binutils 2.38
+    
+    The following description is copied from the equivalent patch for the
+    Linux Kernel proposed by Aurelien Jarno:
+    
+    >From version 2.38, binutils default to ISA spec version 20191213. This
+    means that the csr read/write (csrr*/csrw*) instructions and fence.i
+    instruction has separated from the `I` extension, become two standalone
+    extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+    this causes the following build failure:
+    
+    arch/riscv/cpu/mtrap.S: Assembler messages:
+    arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+    arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+    arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+    arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+    
+    Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+    Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+    Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+    Tested-by: Heiko Stuebner <heiko@sntech.de>
+    Tested-by: Christian Stewart <christian@paral.in>
+    Reviewed-by: Rick Chen <rick@andestech.com>
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d86..53d1194ffb 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ 	CMODEL = medany
+ endif
+ 
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
+ 	     -mcmodel=$(CMODEL)
+ 
+ PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)

package/boot/uboot-sifiveu/patches/100-mkimage-check-environment-for-dtc-binary-location.patch

@@ -0,0 +1,35 @@
+From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Wed, 19 Jul 2017 22:23:15 +0200
+Subject: mkimage: check environment for dtc binary location
+
+Currently mkimage assumes the dtc binary is in the path and fails
+otherwise. This patch makes it check the DTC environment variable first
+for the dtc binary and then fall back to the default path. This makes
+it possible to call the u-boot build with make DTC=... and build a fit
+image with the dtc binary not being the the default path.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Simon Glass <sjg@chromium.org>
+---
+ tools/fit_image.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/tools/fit_image.c
++++ b/tools/fit_image.c
+@@ -726,9 +726,14 @@ static int fit_handle_file(struct image_
+ 		}
+ 		*cmd = '\0';
+ 	} else if (params->datafile) {
++		const char* dtc = getenv("DTC");
++
++		if (!dtc)
++			dtc = MKIMAGE_DTC;
++
+ 		/* dtc -I dts -O dtb -p 500 -o tmpfile datafile */
+ 		snprintf(cmd, sizeof(cmd), "%s %s -o \"%s\" \"%s\"",
+-			 MKIMAGE_DTC, params->dtc, tmpfile, params->datafile);
++			 dtc, params->dtc, tmpfile, params->datafile);
+ 		debug("Trying to execute \"%s\"\n", cmd);
+ 	} else {
+ 		snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"",

package/boot/uboot-sifiveu/patches/110-no-kwbimage.patch

@@ -0,0 +1,10 @@
+--- a/tools/Makefile
++++ b/tools/Makefile
+@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \
+ 			imximage.o \
+ 			imx8image.o \
+ 			imx8mimage.o \
+-			kwbimage.o \
+ 			lib/md5.o \
+ 			lpc32xximage.o \
+ 			mxsimage.o \

package/boot/uboot-sifiveu/patches/130-fix-mkimage-host-build.patch

@@ -0,0 +1,24 @@
+--- a/tools/image-host.c
++++ b/tools/image-host.c
+@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
+  * 2) get public key (X509_get_pubkey)
+  * 3) provide der format (d2i_RSAPublicKey)
+  */
++#ifdef CONFIG_TOOLS_LIBCRYPTO
+ static int read_pub_key(const char *keydir, const void *name,
+ 			unsigned char **pubkey, int *pubkey_len)
+ {
+@@ -1178,6 +1179,13 @@ err_cert:
+ 	fclose(f);
+ 	return ret;
+ }
++#else
++static int read_pub_key(const char *keydir, const void *name,
++			unsigned char **pubkey, int *pubkey_len)
++{
++	return -ENOSYS;
++}
++#endif
+ 
+ int fit_pre_load_data(const char *keydir, void *keydest, void *fit)
+ {

package/boot/uboot-sifiveu/patches/300-force-pylibfdt-build.patch

@@ -0,0 +1,30 @@
+--- a/Makefile
++++ b/Makefile
+@@ -2028,26 +2028,7 @@ endif
+ # Check dtc and pylibfdt, if DTC is provided, else build them
+ PHONY += scripts_dtc
+ scripts_dtc: scripts_basic
+-	$(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
+-		$(MAKE) $(build)=scripts/dtc; \
+-	else \
+-		if ! $(DTC) -v >/dev/null; then \
+-			echo '*** Failed to check dtc version: $(DTC)'; \
+-			false; \
+-		else \
+-			if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
+-				echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
+-				false; \
+-			else \
+-				if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
+-					if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
+-						echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
+-						false; \
+-					fi; \
+-				fi; \
+-			fi; \
+-		fi; \
+-	fi
++	$(MAKE) $(build)=scripts/dtc
+ 
+ # ---------------------------------------------------------------------------
+ quiet_cmd_cpp_lds = LDS     $@

package/boot/uboot-sifiveu/uEnv-default.txt

@@ -0,0 +1,5 @@
+setenv loadkernel fatload mmc 0:3 \$kernel_addr_r Image
+setenv loaddtb fatload mmc 0:3 \$fdt_addr_r dtb
+setenv bootargs console=ttySIF0,115200 earlycon=sbi root=/dev/mmcblk0p4 rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd

package/kernel/ath10k-ct/Makefile

@@ -1,21 +1,21 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=ath10k-ct
-PKG_RELEASE:=5
+PKG_RELEASE:=1
 
 PKG_LICENSE:=GPLv2
 PKG_LICENSE_FILES:=
 
 PKG_SOURCE_URL:=https://github.com/greearb/ath10k-ct.git
 PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2022-05-13
-PKG_SOURCE_VERSION:=f808496fcc6b1f68942914117aebf8b3f8d52bb3
-PKG_MIRROR_HASH:=39527b3408696594eda5579521a9fb798417be4dda73fa08e8b3a8c7b0d3f3d9
+PKG_SOURCE_DATE:=2023-05-26
+PKG_SOURCE_VERSION:=af342b6171a457e067932615deb203b68b1d076a
+PKG_MIRROR_HASH:=90e145fbe6057da65b637e3a194317c1e4f529b078c7e4a245a286c37e3d1b76
 
-# Build the 5.15 ath10k-ct driver version.
+# Build the 6.2 ath10k-ct driver version.
 # Probably this should match as closely as
 # possible to whatever mac80211 backports version is being used.
-CT_KVER="-5.15"
+CT_KVER="-6.2"
 
 PKG_MAINTAINER:=Ben Greear <greearb@candelatech.com>
 PKG_BUILD_PARALLEL:=1

package/kernel/ath10k-ct/patches/100-api_update.patch

@@ -1,618 +0,0 @@
---- a/ath10k-5.15/mac.c
-+++ b/ath10k-5.15/mac.c
-@@ -788,7 +788,7 @@ int ath10k_mac_vif_chan(struct ieee80211
- 	struct ieee80211_chanctx_conf *conf;
- 
- 	rcu_read_lock();
--	conf = rcu_dereference(vif->chanctx_conf);
-+	conf = rcu_dereference(vif->bss_conf.chanctx_conf);
- 	if (!conf) {
- 		rcu_read_unlock();
- 		return -ENOENT;
-@@ -1764,8 +1764,8 @@ static int ath10k_vdev_start_restart(str
- 		arg.channel.chan_radar =
- 			!!(chandef->chan->flags & IEEE80211_CHAN_RADAR);
- 	} else if (arvif->vdev_type == WMI_VDEV_TYPE_IBSS) {
--		arg.ssid = arvif->vif->bss_conf.ssid;
--		arg.ssid_len = arvif->vif->bss_conf.ssid_len;
-+		arg.ssid = arvif->vif->cfg.ssid;
-+		arg.ssid_len = arvif->vif->cfg.ssid_len;
- 	}
- 
- 	ath10k_dbg(ar, ATH10K_DBG_MAC,
-@@ -1890,7 +1890,7 @@ static int ath10k_mac_setup_bcn_tmpl(str
- 	    arvif->vdev_type != WMI_VDEV_TYPE_IBSS)
- 		return 0;
- 
--	bcn = ieee80211_beacon_get_template(hw, vif, &offs);
-+	bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0);
- 	if (!bcn) {
- 		ath10k_warn(ar, "failed to get beacon template from mac80211\n");
- 		return -EPERM;
-@@ -2083,8 +2083,7 @@ static void ath10k_control_beaconing(str
- }
- 
- static void ath10k_control_ibss(struct ath10k_vif *arvif,
--				struct ieee80211_bss_conf *info,
--				const u8 self_peer[ETH_ALEN])
-+				struct ieee80211_vif *vif)
- {
- 	struct ath10k *ar = arvif->ar;
- 	u32 vdev_param;
-@@ -2092,7 +2091,7 @@ static void ath10k_control_ibss(struct a
- 
- 	lockdep_assert_held(&arvif->ar->conf_mutex);
- 
--	if (!info->ibss_joined) {
-+	if (!vif->cfg.ibss_joined) {
- 		if (is_zero_ether_addr(arvif->bssid))
- 			return;
- 
-@@ -2298,7 +2297,7 @@ static void ath10k_mac_vif_ap_csa_count_
- 	if (arvif->vdev_type != WMI_VDEV_TYPE_AP)
- 		return;
- 
--	if (!vif->csa_active)
-+	if (!vif->bss_conf.csa_active)
- 		return;
- 
- 	if (!arvif->is_up)
-@@ -2433,7 +2432,7 @@ static void ath10k_peer_assoc_h_basic(st
- 	lockdep_assert_held(&ar->conf_mutex);
- 
- 	if (vif->type == NL80211_IFTYPE_STATION)
--		aid = vif->bss_conf.aid;
-+		aid = vif->cfg.aid;
- 	else
- 		aid = sta->aid;
- 
-@@ -2463,7 +2462,8 @@ static void ath10k_peer_assoc_h_crypto(s
- 		return;
- 
- 	bss = cfg80211_get_bss(ar->hw->wiphy, def.chan, info->bssid,
--			       info->ssid_len ? info->ssid : NULL, info->ssid_len,
-+			       vif->cfg.ssid_len ? vif->cfg.ssid : NULL,
-+			       vif->cfg.ssid_len,
- 			       IEEE80211_BSS_TYPE_ANY, IEEE80211_PRIVACY_ANY);
- 	if (bss) {
- 		const struct cfg80211_bss_ies *ies;
-@@ -2521,7 +2521,7 @@ static void ath10k_peer_assoc_h_rates(st
- 
- 	band = def.chan->band;
- 	sband = ar->hw->wiphy->bands[band];
--	ratemask = sta->supp_rates[band];
-+	ratemask = sta->deflink.supp_rates[band];
- 	ratemask &= arvif->bitrate_mask.control[band].legacy;
- 	rates = sband->bitrates;
- 
-@@ -2770,7 +2770,7 @@ static void ath10k_peer_assoc_h_ht(struc
- 				   struct ieee80211_sta *sta,
- 				   struct wmi_peer_assoc_complete_arg *arg)
- {
--	const struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
-+	const struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap;
- 	struct ath10k_vif *arvif = (void *)vif->drv_priv;
- 	struct cfg80211_chan_def def;
- 	enum nl80211_band band;
-@@ -2814,7 +2814,7 @@ static void ath10k_peer_assoc_h_ht(struc
- 	if (ht_cap->cap & IEEE80211_HT_CAP_LDPC_CODING)
- 		arg->peer_flags |= ar->wmi.peer_flags->ldbc;
- 
--	if (sta->bandwidth >= IEEE80211_STA_RX_BW_40) {
-+	if (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) {
- 		arg->peer_flags |= ar->wmi.peer_flags->bw40;
- 		arg->peer_rate_caps |= WMI_RC_CW40_FLAG;
- 	}
-@@ -2883,7 +2883,7 @@ static void ath10k_peer_assoc_h_ht(struc
- 			arg->peer_ht_rates.rates[i] = i;
- 	} else {
- 		arg->peer_ht_rates.num_rates = n;
--		arg->peer_num_spatial_streams = min(sta->rx_nss, max_nss);
-+		arg->peer_num_spatial_streams = min(sta->deflink.rx_nss, max_nss);
- 	}
- 
- 	ath10k_dbg(ar, ATH10K_DBG_MAC, "mac ht peer %pM mcs cnt %d nss %d\n",
-@@ -3045,7 +3045,7 @@ static void ath10k_peer_assoc_h_vht(stru
- 				    struct ieee80211_sta *sta,
- 				    struct wmi_peer_assoc_complete_arg *arg)
- {
--	const struct ieee80211_sta_vht_cap *vht_cap = &sta->vht_cap;
-+	const struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap;
- 	struct ath10k_vif *arvif = (void *)vif->drv_priv;
- 	struct ath10k_hw_params *hw = &ar->hw_params;
- 	struct cfg80211_chan_def def;
-@@ -3087,10 +3087,10 @@ static void ath10k_peer_assoc_h_vht(stru
- 				 (1U << (IEEE80211_HT_MAX_AMPDU_FACTOR +
- 					ampdu_factor)) - 1);
- 
--	if (sta->bandwidth == IEEE80211_STA_RX_BW_80)
-+	if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80)
- 		arg->peer_flags |= ar->wmi.peer_flags->bw80;
- 
--	if (sta->bandwidth == IEEE80211_STA_RX_BW_160)
-+	if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160)
- 		arg->peer_flags |= ar->wmi.peer_flags->bw160;
- 
- 	/* Calculate peer NSS capability from VHT capabilities if STA
-@@ -3104,7 +3104,7 @@ static void ath10k_peer_assoc_h_vht(stru
- 		    vht_mcs_mask[i])
- 			max_nss = i + 1;
- 	}
--	arg->peer_num_spatial_streams = min(sta->rx_nss, max_nss);
-+	arg->peer_num_spatial_streams = min(sta->deflink.rx_nss, max_nss);
- 	arg->peer_vht_rates.rx_max_rate =
- 		__le16_to_cpu(vht_cap->vht_mcs.rx_highest);
- 	arg->peer_vht_rates.rx_mcs_set =
-@@ -3266,7 +3266,7 @@ static bool ath10k_mac_sta_has_ofdm_only
- {
- 	struct ath10k_vif *arvif = (void *)vif->drv_priv;
- 	u32 msk = arvif->bitrate_mask.control[NL80211_BAND_2GHZ].legacy &
--		sta->supp_rates[NL80211_BAND_2GHZ];
-+		sta->deflink.supp_rates[NL80211_BAND_2GHZ];
- 	/* We have 12 bits of legacy rates, first 4 are /b (CCK) rates. */
- 	return (msk & 0xff0) && !(msk & 0xf);
- }
-@@ -3276,7 +3276,7 @@ static bool ath10k_mac_sta_has_ofdm_and_
- {
- 	struct ath10k_vif *arvif = (void *)vif->drv_priv;
- 	u32 msk = arvif->bitrate_mask.control[NL80211_BAND_2GHZ].legacy &
--		sta->supp_rates[NL80211_BAND_2GHZ];
-+		sta->deflink.supp_rates[NL80211_BAND_2GHZ];
- 	/* We have 12 bits of legacy rates, first 4 are /b (CCK) rates. */
- 	return ((msk & 0xf) && (msk & 0xff0));
- }
-@@ -3284,8 +3284,10 @@ static bool ath10k_mac_sta_has_ofdm_and_
- static enum wmi_phy_mode ath10k_mac_get_phymode_vht(struct ath10k *ar,
- 						    struct ieee80211_sta *sta)
- {
--	if (sta->bandwidth == IEEE80211_STA_RX_BW_160) {
--		switch (sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) {
-+	struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap;
-+
-+	if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160) {
-+		switch (vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) {
- 		case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ:
- 			return MODE_11AC_VHT160;
- 		case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ:
-@@ -3296,13 +3298,13 @@ static enum wmi_phy_mode ath10k_mac_get_
- 		}
- 	}
- 
--	if (sta->bandwidth == IEEE80211_STA_RX_BW_80)
-+	if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80)
- 		return MODE_11AC_VHT80;
- 
--	if (sta->bandwidth == IEEE80211_STA_RX_BW_40)
-+	if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40)
- 		return MODE_11AC_VHT40;
- 
--	if (sta->bandwidth == IEEE80211_STA_RX_BW_20)
-+	if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_20)
- 		return MODE_11AC_VHT20;
- 
- 	return MODE_UNKNOWN;
-@@ -3329,15 +3331,15 @@ static void ath10k_peer_assoc_h_phymode(
- 
- 	switch (band) {
- 	case NL80211_BAND_2GHZ:
--		if (sta->vht_cap.vht_supported &&
-+		if (sta->deflink.vht_cap.vht_supported &&
- 		    !ath10k_peer_assoc_h_vht_masked(vht_mcs_mask)) {
--			if (sta->bandwidth == IEEE80211_STA_RX_BW_40)
-+			if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40)
- 				phymode = MODE_11AC_VHT40;
- 			else
- 				phymode = MODE_11AC_VHT20;
--		} else if (sta->ht_cap.ht_supported &&
-+		} else if (sta->deflink.ht_cap.ht_supported &&
- 			   !ath10k_peer_assoc_h_ht_masked(ht_mcs_mask)) {
--			if (sta->bandwidth == IEEE80211_STA_RX_BW_40)
-+			if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40)
- 				phymode = MODE_11NG_HT40;
- 			else
- 				phymode = MODE_11NG_HT20;
-@@ -3354,12 +3356,12 @@ static void ath10k_peer_assoc_h_phymode(
- 		/*
- 		 * Check VHT first.
- 		 */
--		if (sta->vht_cap.vht_supported &&
-+		if (sta->deflink.vht_cap.vht_supported &&
- 		    !ath10k_peer_assoc_h_vht_masked(vht_mcs_mask)) {
- 			phymode = ath10k_mac_get_phymode_vht(ar, sta);
--		} else if (sta->ht_cap.ht_supported &&
-+		} else if (sta->deflink.ht_cap.ht_supported &&
- 			   !ath10k_peer_assoc_h_ht_masked(ht_mcs_mask)) {
--			if (sta->bandwidth >= IEEE80211_STA_RX_BW_40)
-+			if (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40)
- 				phymode = MODE_11NA_HT40;
- 			else
- 				phymode = MODE_11NA_HT20;
-@@ -3373,8 +3375,8 @@ static void ath10k_peer_assoc_h_phymode(
- 	}
- 
- 	ath10k_dbg(ar, ATH10K_DBG_MAC, "mac peer %pM phymode %s  legacy-supp-rates: 0x%x  arvif-legacy-rates: 0x%x vht-supp: %d\n",
--		   sta->addr, ath10k_wmi_phymode_str(phymode), sta->supp_rates[band],
--		   arvif->bitrate_mask.control[band].legacy, sta->vht_cap.vht_supported);
-+		   sta->addr, ath10k_wmi_phymode_str(phymode), sta->deflink.supp_rates[band],
-+		   arvif->bitrate_mask.control[band].legacy, sta->deflink.vht_cap.vht_supported);
- 
- 	arg->peer_phymode = phymode;
- 	WARN_ON(phymode == MODE_UNKNOWN);
-@@ -3677,8 +3679,8 @@ static void ath10k_bss_assoc(struct ieee
- 	/* ap_sta must be accessed only within rcu section which must be left
- 	 * before calling ath10k_setup_peer_smps() which might sleep.
- 	 */
--	ht_cap = ap_sta->ht_cap;
--	vht_cap = ap_sta->vht_cap;
-+	ht_cap = ap_sta->deflink.ht_cap;
-+	vht_cap = ap_sta->deflink.vht_cap;
- 
- 	ret = ath10k_peer_assoc_prepare(ar, vif, ap_sta, &peer_arg);
- 	if (ret) {
-@@ -3713,11 +3715,11 @@ static void ath10k_bss_assoc(struct ieee
- 
- 	ath10k_dbg(ar, ATH10K_DBG_MAC,
- 		   "mac vdev %d up (associated) bssid %pM aid %d bandwidth %d\n",
--		   arvif->vdev_id, bss_conf->bssid, bss_conf->aid, ap_sta->bandwidth);
-+		   arvif->vdev_id, bss_conf->bssid, vif->cfg.aid, ap_sta->deflink.bandwidth);
- 
- 	WARN_ON(arvif->is_up);
- 
--	arvif->aid = bss_conf->aid;
-+	arvif->aid = vif->cfg.aid;
- 	ether_addr_copy(arvif->bssid, bss_conf->bssid);
- 
- 	ret = ath10k_wmi_pdev_set_param(ar,
-@@ -4022,7 +4024,7 @@ static int ath10k_station_assoc(struct a
- 	 */
- 	if (!reassoc) {
- 		ret = ath10k_setup_peer_smps(ar, arvif, sta->addr,
--					     &sta->ht_cap);
-+					     &sta->deflink.ht_cap);
- 		if (ret) {
- 			ath10k_warn(ar, "failed to setup peer SMPS for vdev %d: %d\n",
- 				    arvif->vdev_id, ret);
-@@ -6916,7 +6918,7 @@ static void ath10k_recalculate_mgmt_rate
- static void ath10k_bss_info_changed(struct ieee80211_hw *hw,
- 				    struct ieee80211_vif *vif,
- 				    struct ieee80211_bss_conf *info,
--				    u32 changed)
-+				    u64 changed)
- {
- 	struct ath10k *ar = hw->priv;
- 	struct ath10k_vif *arvif = (void *)vif->drv_priv;
-@@ -6930,7 +6932,7 @@ static void ath10k_bss_info_changed(stru
- 	mutex_lock(&ar->conf_mutex);
- 
- 	if (changed & BSS_CHANGED_IBSS)
--		ath10k_control_ibss(arvif, info, vif->addr);
-+		ath10k_control_ibss(arvif, vif);
- 
- 	if (changed & BSS_CHANGED_BEACON_INT) {
- 		arvif->beacon_interval = info->beacon_int;
-@@ -6995,9 +6997,9 @@ static void ath10k_bss_info_changed(stru
- 
- 	if (changed & BSS_CHANGED_SSID &&
- 	    vif->type == NL80211_IFTYPE_AP) {
--		arvif->u.ap.ssid_len = info->ssid_len;
--		if (info->ssid_len)
--			memcpy(arvif->u.ap.ssid, info->ssid, info->ssid_len);
-+		arvif->u.ap.ssid_len = vif->cfg.ssid_len;
-+		if (vif->cfg.ssid_len)
-+			memcpy(arvif->u.ap.ssid, vif->cfg.ssid, vif->cfg.ssid_len);
- 		arvif->u.ap.hidden_ssid = info->hidden_ssid;
- 	}
- 
-@@ -7074,7 +7076,7 @@ static void ath10k_bss_info_changed(stru
- 	}
- 
- 	if (changed & BSS_CHANGED_ASSOC) {
--		if (info->assoc) {
-+		if (vif->cfg.assoc) {
- 			/* Workaround: Make sure monitor vdev is not running
- 			 * when associating to prevent some firmware revisions
- 			 * (e.g. 10.1 and 10.2) from crashing.
-@@ -7099,7 +7101,7 @@ static void ath10k_bss_info_changed(stru
- 	}
- 
- 	if (changed & BSS_CHANGED_PS) {
--		arvif->ps = vif->bss_conf.ps;
-+		arvif->ps = vif->cfg.ps;
- 
- 		ret = ath10k_config_ps(ar);
- 		if (ret)
-@@ -7699,7 +7701,7 @@ static void ath10k_sta_rc_update_wk(stru
- 
- 	if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) {
- 		ath10k_dbg(ar, ATH10K_DBG_STA, "mac update sta %pM supp rates, bandwidth: %d\n",
--			   sta->addr, sta->bandwidth);
-+			   sta->addr, sta->deflink.bandwidth);
- 
- 		err = ath10k_station_assoc(ar, arvif->vif, sta, true);
- 		if (err)
-@@ -7751,10 +7753,10 @@ static int ath10k_sta_set_txpwr(struct i
- 	int ret = 0;
- 	s16 txpwr;
- 
--	if (sta->txpwr.type == NL80211_TX_POWER_AUTOMATIC) {
-+	if (sta->deflink.txpwr.type == NL80211_TX_POWER_AUTOMATIC) {
- 		txpwr = 0;
- 	} else {
--		txpwr = sta->txpwr.power;
-+		txpwr = sta->deflink.txpwr.power;
- 		if (!txpwr)
- 			return -EINVAL;
- 	}
-@@ -7874,26 +7876,29 @@ static int ath10k_mac_validate_rate_mask
- 					 struct ieee80211_sta *sta,
- 					 u32 rate_ctrl_flag, u8 nss)
- {
--	if (nss > sta->rx_nss) {
-+	struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap;
-+	struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap;
-+
-+	if (nss > sta->deflink.rx_nss) {
- 		ath10k_warn(ar, "Invalid nss field, configured %u limit %u\n",
--			    nss, sta->rx_nss);
-+			    nss, sta->deflink.rx_nss);
- 		return -EINVAL;
- 	}
- 
- 	if (ATH10K_HW_PREAMBLE(rate_ctrl_flag) == WMI_RATE_PREAMBLE_VHT) {
--		if (!sta->vht_cap.vht_supported) {
-+		if (!vht_cap->vht_supported) {
- 			ath10k_warn(ar, "Invalid VHT rate for sta %pM\n",
- 				    sta->addr);
- 			return -EINVAL;
- 		}
- 	} else if (ATH10K_HW_PREAMBLE(rate_ctrl_flag) == WMI_RATE_PREAMBLE_HT) {
--		if (!sta->ht_cap.ht_supported || sta->vht_cap.vht_supported) {
-+		if (!ht_cap->ht_supported || vht_cap->vht_supported) {
- 			ath10k_warn(ar, "Invalid HT rate for sta %pM\n",
- 				    sta->addr);
- 			return -EINVAL;
- 		}
- 	} else {
--		if (sta->ht_cap.ht_supported || sta->vht_cap.vht_supported)
-+		if (ht_cap->ht_supported || vht_cap->vht_supported)
- 			return -EINVAL;
- 	}
- 
-@@ -8567,7 +8572,7 @@ static int ath10k_sta_state(struct ieee8
- 		 * New association.
- 		 */
- 		ath10k_dbg(ar, ATH10K_DBG_STA, "mac sta %pM associated, bandwidth: %d\n",
--			   sta->addr, sta->bandwidth);
-+			   sta->addr, sta->deflink.bandwidth);
- 
- 		ret = ath10k_station_assoc(ar, vif, sta, false);
- 		if (ret)
-@@ -8580,7 +8585,7 @@ static int ath10k_sta_state(struct ieee8
- 		 * Tdls station authorized.
- 		 */
- 		ath10k_dbg(ar, ATH10K_DBG_STA, "mac tdls sta %pM authorized, bandwidth: %d\n",
--			   sta->addr, sta->bandwidth);
-+			   sta->addr, sta->deflink.bandwidth);
- 
- 		ret = ath10k_station_assoc(ar, vif, sta, false);
- 		if (ret) {
-@@ -8721,8 +8726,8 @@ exit:
- 	return ret;
- }
- 
--static int ath10k_conf_tx(struct ieee80211_hw *hw,
--			  struct ieee80211_vif *vif, u16 ac,
-+static int ath10k_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
-+			  unsigned int link_id, u16 ac,
- 			  const struct ieee80211_tx_queue_params *params)
- {
- 	struct ath10k *ar = hw->priv;
-@@ -9308,7 +9313,7 @@ static bool ath10k_mac_set_vht_bitrate_m
- 	u8 rate = arvif->vht_pfr;
- 
- 	/* skip non vht and multiple rate peers */
--	if (!sta->vht_cap.vht_supported || arvif->vht_num_rates != 1)
-+	if (!sta->deflink.vht_cap.vht_supported || arvif->vht_num_rates != 1)
- 		return false;
- 
- 	err = ath10k_wmi_peer_set_param(ar, arvif->vdev_id, sta->addr,
-@@ -9349,7 +9354,7 @@ static void ath10k_mac_clr_bitrate_mask_
- 	int err;
- 
- 	/* clear vht peers only */
--	if (arsta->arvif != arvif || !sta->vht_cap.vht_supported)
-+	if (arsta->arvif != arvif || !sta->deflink.vht_cap.vht_supported)
- 		return;
- 
- 	err = ath10k_wmi_peer_set_param(ar, arvif->vdev_id, sta->addr,
-@@ -9534,13 +9539,13 @@ static void ath10k_sta_rc_update(struct
- 
- 	ath10k_dbg(ar, ATH10K_DBG_STA,
- 		   "mac sta rc update for %pM changed %08x bw %d nss %d smps %d\n",
--		   sta->addr, changed, sta->bandwidth, sta->rx_nss,
--		   sta->smps_mode);
-+		   sta->addr, changed, sta->deflink.bandwidth, sta->deflink.rx_nss,
-+		   sta->deflink.smps_mode);
- 
- 	if (changed & IEEE80211_RC_BW_CHANGED) {
- 		bw = WMI_PEER_CHWIDTH_20MHZ;
- 
--		switch (sta->bandwidth) {
-+		switch (sta->deflink.bandwidth) {
- 		case IEEE80211_STA_RX_BW_20:
- 			bw = WMI_PEER_CHWIDTH_20MHZ;
- 			break;
-@@ -9555,7 +9560,7 @@ static void ath10k_sta_rc_update(struct
- 			break;
- 		default:
- 			ath10k_warn(ar, "Invalid bandwidth %d in rc update for %pM\n",
--				    sta->bandwidth, sta->addr);
-+				    sta->deflink.bandwidth, sta->addr);
- 			bw = WMI_PEER_CHWIDTH_20MHZ;
- 			break;
- 		}
-@@ -9564,12 +9569,12 @@ static void ath10k_sta_rc_update(struct
- 	}
- 
- 	if (changed & IEEE80211_RC_NSS_CHANGED)
--		arsta->nss = sta->rx_nss;
-+		arsta->nss = sta->deflink.rx_nss;
- 
- 	if (changed & IEEE80211_RC_SMPS_CHANGED) {
- 		smps = WMI_PEER_SMPS_PS_NONE;
- 
--		switch (sta->smps_mode) {
-+		switch (sta->deflink.smps_mode) {
- 		case IEEE80211_SMPS_AUTOMATIC:
- 		case IEEE80211_SMPS_OFF:
- 			smps = WMI_PEER_SMPS_PS_NONE;
-@@ -9582,7 +9587,7 @@ static void ath10k_sta_rc_update(struct
- 			break;
- 		case IEEE80211_SMPS_NUM_MODES:
- 			ath10k_warn(ar, "Invalid smps %d in sta rc update for %pM\n",
--				    sta->smps_mode, sta->addr);
-+				    sta->deflink.smps_mode, sta->addr);
- 			smps = WMI_PEER_SMPS_PS_NONE;
- 			break;
- 		}
-@@ -9896,7 +9901,7 @@ ath10k_mac_change_chanctx_cnt_iter(void
- {
- 	struct ath10k_mac_change_chanctx_arg *arg = data;
- 
--	if (rcu_access_pointer(vif->chanctx_conf) != arg->ctx)
-+	if (rcu_access_pointer(vif->bss_conf.chanctx_conf) != arg->ctx)
- 		return;
- 
- 	arg->n_vifs++;
-@@ -9909,7 +9914,7 @@ ath10k_mac_change_chanctx_fill_iter(void
- 	struct ath10k_mac_change_chanctx_arg *arg = data;
- 	struct ieee80211_chanctx_conf *ctx;
- 
--	ctx = rcu_access_pointer(vif->chanctx_conf);
-+	ctx = rcu_access_pointer(vif->bss_conf.chanctx_conf);
- 	if (ctx != arg->ctx)
- 		return;
- 
-@@ -9982,6 +9987,7 @@ unlock:
- static int
- ath10k_mac_op_assign_vif_chanctx(struct ieee80211_hw *hw,
- 				 struct ieee80211_vif *vif,
-+				 struct ieee80211_bss_conf *link_conf,
- 				 struct ieee80211_chanctx_conf *ctx)
- {
- 	struct ath10k *ar = hw->priv;
-@@ -10061,6 +10067,7 @@ err:
- static void
- ath10k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw,
- 				   struct ieee80211_vif *vif,
-+				   struct ieee80211_bss_conf *link_conf,
- 				   struct ieee80211_chanctx_conf *ctx)
- {
- 	struct ath10k *ar = hw->priv;
---- a/ath10k-5.15/txrx.c
-+++ b/ath10k-5.15/txrx.c
-@@ -260,7 +260,7 @@ int ath10k_txrx_tx_unref(struct ath10k_h
- 			nf = ar->debug.nf_sum[0];
- #endif
- 		info->status.ack_signal = nf + tx_done->ack_rssi;
--		info->status.is_valid_ack_signal = true;
-+		info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
- 	}
- 
- 	if (tx_done->tx_rate_code || tx_done->tx_rate_flags || ar->ok_tx_rate_status) {
---- a/ath10k-5.15/wmi.c
-+++ b/ath10k-5.15/wmi.c
-@@ -2587,7 +2587,7 @@ wmi_process_mgmt_tx_comp(struct ath10k *
- 		info->flags |= IEEE80211_TX_STAT_ACK;
- 		info->status.ack_signal = ath10k_get_noisefloor(0, ar) +
- 					  param->ack_rssi;
--		info->status.is_valid_ack_signal = true;
-+		info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
- 	}
- 
- 	ieee80211_tx_status_irqsafe(ar->hw, msdu);
-@@ -4258,13 +4258,13 @@ void ath10k_wmi_event_host_swba(struct a
- 		 * Once CSA counter is completed stop sending beacons until
- 		 * actual channel switch is done
- 		 */
--		if (arvif->vif->csa_active &&
-+		if (arvif->vif->bss_conf.csa_active &&
- 		    ieee80211_beacon_cntdwn_is_complete(arvif->vif)) {
- 			ieee80211_csa_finish(arvif->vif);
- 			continue;
- 		}
- 
--		bcn = ieee80211_beacon_get(ar->hw, arvif->vif);
-+		bcn = ieee80211_beacon_get(ar->hw, arvif->vif, 0);
- 		if (!bcn) {
- 			ath10k_warn(ar, "could not get mac80211 beacon, vdev_id: %i addr: %pM\n",
- 				    arvif->vdev_id, arvif->vif->addr);
---- a/ath10k-5.15/htt_rx.c
-+++ b/ath10k-5.15/htt_rx.c
-@@ -4017,7 +4017,7 @@ ath10k_update_per_peer_tx_stats(struct a
- 	switch (txrate.flags) {
- 	case WMI_RATE_PREAMBLE_OFDM:
- 		if (arsta->arvif && arsta->arvif->vif)
--			conf = rcu_dereference(arsta->arvif->vif->chanctx_conf);
-+			conf = rcu_dereference(arsta->arvif->vif->bss_conf.chanctx_conf);
- 		if (conf && conf->def.chan->band == NL80211_BAND_5GHZ)
- 			arsta->tx_info.status.rates[0].idx = rate_idx - 4;
- 		break;
---- a/ath10k-5.15/wmi-tlv.c
-+++ b/ath10k-5.15/wmi-tlv.c
-@@ -205,7 +205,7 @@ static int ath10k_wmi_tlv_event_bcn_tx_s
- 	}
- 
- 	arvif = ath10k_get_arvif(ar, vdev_id);
--	if (arvif && arvif->is_up && arvif->vif->csa_active)
-+	if (arvif && arvif->is_up && arvif->vif->bss_conf.csa_active)
- 		ieee80211_queue_work(ar->hw, &arvif->ap_csa_work);
- 
- 	kfree(tb);
---- a/ath10k-5.15/core.c
-+++ b/ath10k-5.15/core.c
-@@ -4081,7 +4081,7 @@ static int ath10k_core_probe_fw(struct a
- 		ath10k_debug_print_board_info(ar);
- 	}
- 
--	device_get_mac_address(ar->dev, ar->mac_addr, sizeof(ar->mac_addr));
-+	device_get_mac_address(ar->dev, ar->mac_addr);
- 
- 	/* Try to get mac address from device node (from nvmem cell) */
- 	of_get_mac_address(ar->dev->of_node, ar->mac_addr);
---- a/ath10k-5.15/pci.c
-+++ b/ath10k-5.15/pci.c
-@@ -3547,8 +3547,7 @@ static void ath10k_pci_free_irq(struct a
- 
- void ath10k_pci_init_napi(struct ath10k *ar)
- {
--	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
--		       ATH10K_NAPI_BUDGET);
-+	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll);
- }
- 
- static int ath10k_pci_init_irq(struct ath10k *ar)
---- a/ath10k-5.15/sdio.c
-+++ b/ath10k-5.15/sdio.c
-@@ -2531,8 +2531,7 @@ static int ath10k_sdio_probe(struct sdio
- 		return -ENOMEM;
- 	}
- 
--	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_sdio_napi_poll,
--		       ATH10K_NAPI_BUDGET);
-+	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_sdio_napi_poll);
- 
- 	ath10k_dbg(ar, ATH10K_DBG_BOOT,
- 		   "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
---- a/ath10k-5.15/snoc.c
-+++ b/ath10k-5.15/snoc.c
-@@ -1242,8 +1242,7 @@ static int ath10k_snoc_napi_poll(struct
- 
- static void ath10k_snoc_init_napi(struct ath10k *ar)
- {
--	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll,
--		       ATH10K_NAPI_BUDGET);
-+	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll);
- }
- 
- static int ath10k_snoc_request_irq(struct ath10k *ar)

package/kernel/ath10k-ct/patches/120-ath10k-fetch-calibration-data-via-nvmem-subsystem.patch

@@ -1,162 +0,0 @@
-From e2333703373e8b81294da5d1c73c30154f75b082 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Fri, 15 Oct 2021 18:56:33 +0200
-Subject: [PATCH] ath10k: fetch (pre-)calibration data via nvmem subsystem
-
-On most embedded ath10k devices (like range extenders,
-routers, accesspoints, ...) the calibration data is
-stored in a easily accessible MTD partitions named
-"ART", "caldata", "calibration", etc...
-
-Since commit 4b361cfa8624 ("mtd: core: add OTP nvmem provider support"):
-MTD partitions and portions of them can be specified
-as potential nvmem-cells which are accessible through
-the nvmem subsystem.
-
-This feature - together with an nvmem cell definition either
-in the platform data or via device-tree allows drivers to get
-the (pre-)calibration data which is required for initializing
-the WIFI.
-
-Tested with Netgear EX6150v2 (IPQ4018)
-
-Cc: Robert Marko <robimarko@gmail.com>
-Cc: Thibaut Varene <hacks@slashdirt.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
---- a/ath10k-5.15/core.c
-+++ b/ath10k-5.15/core.c
-@@ -13,6 +13,7 @@
- #include <linux/dmi.h>
- #include <linux/ctype.h>
- #include <linux/pm_qos.h>
-+#include <linux/nvmem-consumer.h>
- #include <asm/byteorder.h>
- #include <linux/ctype.h>
- 
-@@ -1005,7 +1006,8 @@ static int ath10k_core_get_board_id_from
- 	}
- 
- 	if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
--	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
-+	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
-+	    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
- 		bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
- 	else
- 		bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
-@@ -2115,7 +2117,8 @@ static int ath10k_download_and_run_otp(s
- 
- 	/* As of now pre-cal is valid for 10_4 variants */
- 	if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
--	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)
-+	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
-+	    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
- 		bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
- 
- 	ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
-@@ -2249,6 +2252,39 @@ struct ath10k_bss_rom_ie {
- 	__le32 rom_len;
- } __packed;
- 
-+static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)
-+{
-+	struct nvmem_cell *cell;
-+	void *buf;
-+	size_t len;
-+	int ret;
-+
-+	cell = devm_nvmem_cell_get(ar->dev, cell_name);
-+	if (IS_ERR(cell)) {
-+		ret = PTR_ERR(cell);
-+		return ret;
-+	}
-+
-+	buf = nvmem_cell_read(cell, &len);
-+	if (IS_ERR(buf))
-+		return PTR_ERR(buf);
-+
-+	if (ar->hw_params.cal_data_len != len) {
-+		kfree(buf);
-+		ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n",
-+			    cell_name, len, ar->hw_params.cal_data_len);
-+		return -EMSGSIZE;
-+	}
-+
-+	ret = ath10k_download_board_data(ar, buf, len);
-+	kfree(buf);
-+	if (ret)
-+		ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n",
-+			    cell_name, ret);
-+
-+	return ret;
-+}
-+
- int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
- 				     struct ath10k_fw_file *fw_file)
- {
-@@ -2625,6 +2661,18 @@ static int ath10k_core_pre_cal_download(
- {
- 	int ret;
- 
-+	ret = ath10k_download_cal_nvmem(ar, "pre-calibration");
-+	if (ret == 0) {
-+		ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;
-+		goto success;
-+	} else if (ret == -EPROBE_DEFER) {
-+		return ret;
-+	}
-+
-+	ath10k_dbg(ar, ATH10K_DBG_BOOT,
-+		   "boot did not find a pre-calibration nvmem-cell, try file next: %d\n",
-+		   ret);
-+
- 	ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
- 	if (ret == 0) {
- 		ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
-@@ -2691,6 +2739,18 @@ static int ath10k_download_cal_data(stru
- 		   "pre cal download procedure failed, try cal file: %d\n",
- 		   ret);
- 
-+	ret = ath10k_download_cal_nvmem(ar, "calibration");
-+	if (ret == 0) {
-+		ar->cal_mode = ATH10K_CAL_MODE_NVMEM;
-+		goto done;
-+	} else if (ret == -EPROBE_DEFER) {
-+		return ret;
-+	}
-+
-+	ath10k_dbg(ar, ATH10K_DBG_BOOT,
-+		   "boot did not find a calibration nvmem-cell, try file next: %d\n",
-+		   ret);
-+
- 	ret = ath10k_download_cal_file(ar, ar->cal_file);
- 	if (ret == 0) {
- 		ar->cal_mode = ATH10K_CAL_MODE_FILE;
---- a/ath10k-5.15/core.h
-+++ b/ath10k-5.15/core.h
-@@ -1109,8 +1109,10 @@ enum ath10k_cal_mode {
- 	ATH10K_CAL_MODE_FILE,
- 	ATH10K_CAL_MODE_OTP,
- 	ATH10K_CAL_MODE_DT,
-+	ATH10K_CAL_MODE_NVMEM,
- 	ATH10K_PRE_CAL_MODE_FILE,
- 	ATH10K_PRE_CAL_MODE_DT,
-+	ATH10K_PRE_CAL_MODE_NVMEM,
- 	ATH10K_CAL_MODE_EEPROM,
- };
- 
-@@ -1130,10 +1132,14 @@ static inline const char *ath10k_cal_mod
- 		return "otp";
- 	case ATH10K_CAL_MODE_DT:
- 		return "dt";
-+	case ATH10K_CAL_MODE_NVMEM:
-+		return "nvmem";
- 	case ATH10K_PRE_CAL_MODE_FILE:
- 		return "pre-cal-file";
- 	case ATH10K_PRE_CAL_MODE_DT:
- 		return "pre-cal-dt";
-+	case ATH10K_PRE_CAL_MODE_NVMEM:
-+		return "pre-cal-nvmem";
- 	case ATH10K_CAL_MODE_EEPROM:
- 		return "eeprom";
- 	}

package/kernel/ath10k-ct/patches/130-ath10k-read-qcom-coexist-support-as-a-u32.patch

@@ -39,9 +39,9 @@ that the feature is properly initialized:
 
 Signed-off-by: Vincent Tremblay <vincent@vtremblay.dev>
 
---- a/ath10k-5.15/core.c
-+++ b/ath10k-5.15/core.c
-@@ -2798,14 +2798,14 @@ done:
+--- a/ath10k-6.2/core.c
++++ b/ath10k-6.2/core.c
+@@ -2869,14 +2869,14 @@ done:
  static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
  {
  	struct device_node *node;

package/kernel/ath10k-ct/patches/201-ath10k-add-LED-and-GPIO-controlling-support-for-various-chipsets.patch

@@ -66,25 +66,25 @@ v13:
 
 * cleanup includes
 
- ath10k-5.15/Kconfig   |  10 +++
- ath10k-5.15/Makefile  |   1 +
- ath10k-5.15/core.c    |  22 +++++++
- ath10k-5.15/core.h    |   9 ++-
- ath10k-5.15/hw.h      |   1 +
- ath10k-5.15/leds.c    | 103 ++++++++++++++++++++++++++++++
- ath10k-5.15/leds.h    |  45 +++++++++++++
- ath10k-5.15/mac.c     |   1 +
- ath10k-5.15/wmi-ops.h |  32 ++++++++++
- ath10k-5.15/wmi-tlv.c |   2 +
- ath10k-5.15/wmi.c     |  54 ++++++++++++++++
- ath10k-5.15/wmi.h     |  35 ++++++++++
+ ath10k-6.2/Kconfig   |  10 +++
+ ath10k-6.2/Makefile  |   1 +
+ ath10k-6.2/core.c    |  22 +++++++
+ ath10k-6.2/core.h    |   9 ++-
+ ath10k-6.2/hw.h      |   1 +
+ ath10k-6.2/leds.c    | 103 ++++++++++++++++++++++++++++++
+ ath10k-6.2/leds.h    |  45 +++++++++++++
+ ath10k-6.2/mac.c     |   1 +
+ ath10k-6.2/wmi-ops.h |  32 ++++++++++
+ ath10k-6.2/wmi-tlv.c |   2 +
+ ath10k-6.2/wmi.c     |  54 ++++++++++++++++
+ ath10k-6.2/wmi.h     |  35 ++++++++++
  12 files changed, 314 insertions(+), 1 deletion(-)
- create mode 100644 ath10k-5.15/leds.c
- create mode 100644 ath10k-5.15/leds.h
+ create mode 100644 ath10k-6.2/leds.c
+ create mode 100644 ath10k-6.2/leds.h
 
---- a/ath10k-5.15/Kconfig
-+++ b/ath10k-5.15/Kconfig
-@@ -66,6 +66,16 @@ config ATH10K_DEBUGFS
+--- a/ath10k-6.2/Kconfig
++++ b/ath10k-6.2/Kconfig
+@@ -67,6 +67,16 @@ config ATH10K_DEBUGFS
  
  	  If unsure, say Y to make it easier to debug problems.
  
@@ -101,8 +101,8 @@ v13:
  config ATH10K_SPECTRAL
  	bool "Atheros ath10k spectral scan support"
  	depends on ATH10K_DEBUGFS
---- a/ath10k-5.15/Makefile
-+++ b/ath10k-5.15/Makefile
+--- a/ath10k-6.2/Makefile
++++ b/ath10k-6.2/Makefile
 @@ -20,6 +20,7 @@ ath10k_core-$(CONFIG_ATH10K_SPECTRAL) +=
  ath10k_core-$(CONFIG_NL80211_TESTMODE) += testmode.o
  ath10k_core-$(CONFIG_ATH10K_TRACING) += trace.o
@@ -111,8 +111,8 @@ v13:
  ath10k_core-$(CONFIG_MAC80211_DEBUGFS) += debugfs_sta.o
  ath10k_core-$(CONFIG_PM) += wow.o
  ath10k_core-$(CONFIG_ATH10K_CE) += ce.o
---- a/ath10k-5.15/core.c
-+++ b/ath10k-5.15/core.c
+--- a/ath10k-6.2/core.c
++++ b/ath10k-6.2/core.c
 @@ -28,6 +28,7 @@
  #include "testmode.h"
  #include "wmi-ops.h"
@@ -121,7 +121,7 @@ v13:
  
  /* Disable ath10k-ct DBGLOG output by default */
  unsigned int ath10k_debug_mask = ATH10K_DBG_NO_DBGLOG;
-@@ -70,6 +71,7 @@ static const struct ath10k_hw_params ath
+@@ -78,6 +79,7 @@ static const struct ath10k_hw_params ath
  		.dev_id = QCA988X_2_0_DEVICE_ID,
  		.bus = ATH10K_BUS_PCI,
  		.name = "qca988x hw2.0",
@@ -129,7 +129,7 @@ v13:
  		.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  		.uart_pin = 7,
  		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
-@@ -143,6 +145,7 @@ static const struct ath10k_hw_params ath
+@@ -159,6 +161,7 @@ static const struct ath10k_hw_params ath
  		.dev_id = QCA9887_1_0_DEVICE_ID,
  		.bus = ATH10K_BUS_PCI,
  		.name = "qca9887 hw1.0",
@@ -137,7 +137,7 @@ v13:
  		.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
  		.uart_pin = 7,
  		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
-@@ -360,6 +363,7 @@ static const struct ath10k_hw_params ath
+@@ -400,6 +403,7 @@ static const struct ath10k_hw_params ath
  		.dev_id = QCA99X0_2_0_DEVICE_ID,
  		.bus = ATH10K_BUS_PCI,
  		.name = "qca99x0 hw2.0",
@@ -145,7 +145,7 @@ v13:
  		.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  		.uart_pin = 7,
  		.otp_exe_param = 0x00000700,
-@@ -402,6 +406,7 @@ static const struct ath10k_hw_params ath
+@@ -446,6 +450,7 @@ static const struct ath10k_hw_params ath
  		.dev_id = QCA9984_1_0_DEVICE_ID,
  		.bus = ATH10K_BUS_PCI,
  		.name = "qca9984/qca9994 hw1.0",
@@ -153,7 +153,7 @@ v13:
  		.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
  		.uart_pin = 7,
  		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
-@@ -451,6 +456,7 @@ static const struct ath10k_hw_params ath
+@@ -499,6 +504,7 @@ static const struct ath10k_hw_params ath
  		.dev_id = QCA9888_2_0_DEVICE_ID,
  		.bus = ATH10K_BUS_PCI,
  		.name = "qca9888 hw2.0",
@@ -161,7 +161,7 @@ v13:
  		.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
  		.uart_pin = 7,
  		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
-@@ -3977,6 +3983,10 @@ int ath10k_core_start(struct ath10k *ar,
+@@ -4080,6 +4086,10 @@ int ath10k_core_start(struct ath10k *ar,
  			ath10k_wmi_check_apply_board_power_ctl_table(ar);
  	}
  
@@ -172,7 +172,7 @@ v13:
  	return 0;
  
  err_hif_stop:
-@@ -4238,9 +4248,18 @@ static void ath10k_core_register_work(st
+@@ -4341,9 +4351,18 @@ static void ath10k_core_register_work(st
  		goto err_spectral_destroy;
  	}
  
@@ -191,7 +191,7 @@ v13:
  err_spectral_destroy:
  	ath10k_spectral_destroy(ar);
  err_debug_destroy:
-@@ -4300,6 +4319,8 @@ void ath10k_core_unregister(struct ath10
+@@ -4403,6 +4422,8 @@ void ath10k_core_unregister(struct ath10
  	if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  		return;
  
@@ -200,8 +200,8 @@ v13:
  	ath10k_thermal_unregister(ar);
  	/* Stop spectral before unregistering from mac80211 to remove the
  	 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
---- a/ath10k-5.15/core.h
-+++ b/ath10k-5.15/core.h
+--- a/ath10k-6.2/core.h
++++ b/ath10k-6.2/core.h
 @@ -14,6 +14,7 @@
  #include <linux/pci.h>
  #include <linux/uuid.h>
@@ -210,7 +210,7 @@ v13:
  
  #include "htt.h"
  #include "htc.h"
-@@ -1577,6 +1578,13 @@ struct ath10k {
+@@ -1586,6 +1587,13 @@ struct ath10k {
  	} testmode;
  
  	struct {
@@ -224,9 +224,9 @@ v13:
  		/* protected by data_lock */
  		u32 rx_crc_err_drop;
  		u32 fw_crash_counter;
---- a/ath10k-5.15/hw.h
-+++ b/ath10k-5.15/hw.h
-@@ -521,6 +521,7 @@ struct ath10k_hw_params {
+--- a/ath10k-6.2/hw.h
++++ b/ath10k-6.2/hw.h
+@@ -523,6 +523,7 @@ struct ath10k_hw_params {
  	const char *name;
  	u32 patch_load_addr;
  	int uart_pin;
@@ -235,7 +235,7 @@ v13:
  
  	/* Type of hw cycle counter wraparound logic, for more info
 --- /dev/null
-+++ b/ath10k-5.15/leds.c
++++ b/ath10k-6.2/leds.c
 @@ -0,0 +1,103 @@
 +/*
 + * Copyright (c) 2005-2011 Atheros Communications Inc.
@@ -341,7 +341,7 @@ v13:
 +}
 +
 --- /dev/null
-+++ b/ath10k-5.15/leds.h
++++ b/ath10k-6.2/leds.h
 @@ -0,0 +1,41 @@
 +/*
 + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
@@ -384,8 +384,8 @@ v13:
 +
 +#endif
 +#endif /* _LEDS_H_ */
---- a/ath10k-5.15/mac.c
-+++ b/ath10k-5.15/mac.c
+--- a/ath10k-6.2/mac.c
++++ b/ath10k-6.2/mac.c
 @@ -25,6 +25,7 @@
  #include "wmi-tlv.h"
  #include "wmi-ops.h"
@@ -394,8 +394,8 @@ v13:
  
  /*********/
  /* Rates */
---- a/ath10k-5.15/wmi-ops.h
-+++ b/ath10k-5.15/wmi-ops.h
+--- a/ath10k-6.2/wmi-ops.h
++++ b/ath10k-6.2/wmi-ops.h
 @@ -228,7 +228,10 @@ struct wmi_ops {
  			 const struct wmi_bb_timing_cfg_arg *arg);
  	struct sk_buff *(*gen_per_peer_per_tid_cfg)(struct ath10k *ar,
@@ -443,9 +443,9 @@ v13:
  static inline int
  ath10k_wmi_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level)
  {
---- a/ath10k-5.15/wmi-tlv.c
-+++ b/ath10k-5.15/wmi-tlv.c
-@@ -4594,6 +4594,8 @@ static const struct wmi_ops wmi_tlv_ops
+--- a/ath10k-6.2/wmi-tlv.c
++++ b/ath10k-6.2/wmi-tlv.c
+@@ -4601,6 +4601,8 @@ static const struct wmi_ops wmi_tlv_ops
  	.gen_echo = ath10k_wmi_tlv_op_gen_echo,
  	.gen_vdev_spectral_conf = ath10k_wmi_tlv_op_gen_vdev_spectral_conf,
  	.gen_vdev_spectral_enable = ath10k_wmi_tlv_op_gen_vdev_spectral_enable,
@@ -454,9 +454,9 @@ v13:
  };
  
  static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = {
---- a/ath10k-5.15/wmi.c
-+++ b/ath10k-5.15/wmi.c
-@@ -8413,6 +8413,49 @@ ath10k_wmi_op_gen_peer_set_param(struct
+--- a/ath10k-6.2/wmi.c
++++ b/ath10k-6.2/wmi.c
+@@ -8438,6 +8438,49 @@ ath10k_wmi_op_gen_peer_set_param(struct
  	return skb;
  }
  
@@ -506,7 +506,7 @@ v13:
  static struct sk_buff *
  ath10k_wmi_op_gen_set_psmode(struct ath10k *ar, u32 vdev_id,
  			     enum wmi_sta_ps_mode psmode)
-@@ -10244,6 +10287,9 @@ static const struct wmi_ops wmi_ops = {
+@@ -10269,6 +10312,9 @@ static const struct wmi_ops wmi_ops = {
  	.fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill,
  	.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,
  	.gen_echo = ath10k_wmi_op_gen_echo,
@@ -516,7 +516,7 @@ v13:
  	/* .gen_bcn_tmpl not implemented */
  	/* .gen_prb_tmpl not implemented */
  	/* .gen_p2p_go_bcn_ie not implemented */
-@@ -10314,6 +10360,8 @@ static const struct wmi_ops wmi_10_1_ops
+@@ -10339,6 +10385,8 @@ static const struct wmi_ops wmi_10_1_ops
  	.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,
  	.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,
  	.gen_echo = ath10k_wmi_op_gen_echo,
@@ -525,7 +525,7 @@ v13:
  	/* .gen_bcn_tmpl not implemented */
  	/* .gen_prb_tmpl not implemented */
  	/* .gen_p2p_go_bcn_ie not implemented */
-@@ -10393,6 +10441,8 @@ static const struct wmi_ops wmi_10_2_ops
+@@ -10418,6 +10466,8 @@ static const struct wmi_ops wmi_10_2_ops
  	.gen_delba_send = ath10k_wmi_op_gen_delba_send,
  	.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,
  	.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,
@@ -534,7 +534,7 @@ v13:
  	/* .gen_pdev_enable_adaptive_cca not implemented */
  };
  
-@@ -10464,6 +10514,8 @@ static const struct wmi_ops wmi_10_2_4_o
+@@ -10489,6 +10539,8 @@ static const struct wmi_ops wmi_10_2_4_o
  		ath10k_wmi_op_gen_pdev_enable_adaptive_cca,
  	.get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype,
  	.gen_bb_timing = ath10k_wmi_10_2_4_op_gen_bb_timing,
@@ -543,7 +543,7 @@ v13:
  	/* .gen_bcn_tmpl not implemented */
  	/* .gen_prb_tmpl not implemented */
  	/* .gen_p2p_go_bcn_ie not implemented */
-@@ -10546,6 +10598,8 @@ static const struct wmi_ops wmi_10_4_ops
+@@ -10571,6 +10623,8 @@ static const struct wmi_ops wmi_10_4_ops
  	.gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info,
  	.gen_echo = ath10k_wmi_op_gen_echo,
  	.gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config,
@@ -552,8 +552,8 @@ v13:
  };
  
  int ath10k_wmi_attach(struct ath10k *ar)
---- a/ath10k-5.15/wmi.h
-+++ b/ath10k-5.15/wmi.h
+--- a/ath10k-6.2/wmi.h
++++ b/ath10k-6.2/wmi.h
 @@ -3133,6 +3133,41 @@ enum wmi_10_4_feature_mask {
  
  };

package/kernel/ath10k-ct/patches/202-ath10k-use-tpt-trigger-by-default.patch

@@ -9,14 +9,14 @@ traffic.
 
 Signed-off-by: Mathias Kresin <dev@kresin.me>
 ---
- ath10k-5.15/core.h | 4 ++++
- ath10k-5.15/leds.c | 4 +---
- ath10k-5.15/mac.c  | 2 +-
+ ath10k-6.2/core.h | 4 ++++
+ ath10k-6.2/leds.c | 4 +---
+ ath10k-6.2/mac.c  | 2 +-
  3 files changed, 6 insertions(+), 4 deletions(-)
 
---- a/ath10k-5.15/core.h
-+++ b/ath10k-5.15/core.h
-@@ -1692,6 +1692,10 @@ struct ath10k {
+--- a/ath10k-6.2/core.h
++++ b/ath10k-6.2/core.h
+@@ -1701,6 +1701,10 @@ struct ath10k {
  	u8 csi_data[4096];
  	u16 csi_data_len;
  
@@ -27,8 +27,8 @@ Signed-off-by: Mathias Kresin <dev@kresin.me>
  	/* must be last */
  	u8 drv_priv[] __aligned(sizeof(void *));
  };
---- a/ath10k-5.15/leds.c
-+++ b/ath10k-5.15/leds.c
+--- a/ath10k-6.2/leds.c
++++ b/ath10k-6.2/leds.c
 @@ -81,9 +81,7 @@ int ath10k_leds_register(struct ath10k *
  
  	ar->leds.cdev.name = ar->leds.label;
@@ -40,9 +40,9 @@ Signed-off-by: Mathias Kresin <dev@kresin.me>
  
  	ret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev);
  	if (ret)
---- a/ath10k-5.15/mac.c
-+++ b/ath10k-5.15/mac.c
-@@ -11551,7 +11551,7 @@ int ath10k_mac_register(struct ath10k *a
+--- a/ath10k-6.2/mac.c
++++ b/ath10k-6.2/mac.c
+@@ -11617,7 +11617,7 @@ int ath10k_mac_register(struct ath10k *a
  	ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER;
  
  #ifdef CPTCFG_MAC80211_LEDS

package/kernel/ath10k-ct/patches/203-ath10k-ct-fix-compilation-warning-for-debug-level.patch

@@ -1,222 +0,0 @@
-From 3b07c3a6e4adebd0466f5e539f318224db8cfc37 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 6 May 2023 15:29:52 +0200
-Subject: [PATCH] ath10k-ct: fix compilation warning for debug level
-
-Rework read_debug_level function as it does exceed the stack limit for
-some arch.
-Fix compilation error:
-/__w/openwrt/openwrt/openwrt/build_dir/target-mips-openwrt-linux-musl_musl/linux-malta_be/ath10k-ct-regular/ath10k-ct-2022-05-13-f808496f/ath10k-5.15/debug.c: In function 'ath10k_read_debug_level':
-/__w/openwrt/openwrt/openwrt/build_dir/target-mips-openwrt-linux-musl_musl/linux-malta_be/ath10k-ct-regular/ath10k-ct-2022-05-13-f808496f/ath10k-5.15/debug.c:1388:1: error: the frame size of 1440 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
- 1388 | }
-      | ^
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- ath10k-5.15/debug.c | 85 +++++++++++++++++++++++++--------------------
- ath10k-5.17/debug.c | 85 +++++++++++++++++++++++++--------------------
- 2 files changed, 96 insertions(+), 74 deletions(-)
-
-diff --git a/ath10k-5.15/debug.c b/ath10k-5.15/debug.c
-index af84012..d0fa911 100644
---- a/ath10k-5.15/debug.c
-+++ b/ath10k-5.15/debug.c
-@@ -1344,47 +1344,58 @@ static const struct file_operations fops_simulate_fw_crash = {
- 	.llseek = default_llseek,
- };
- 
-+static const char debug_level_buf[] =
-+	"To change debug level, set value adding up desired flags:\n"
-+	"PCI:                0x1\n"
-+	"WMI:                0x2\n"
-+	"HTC:                0x4\n"
-+	"HTT:                0x8\n"
-+	"MAC:               0x10\n"
-+	"BOOT:              0x20\n"
-+	"PCI-DUMP:          0x40\n"
-+	"HTT-DUMP:          0x80\n"
-+	"MGMT:             0x100\n"
-+	"DATA:             0x200\n"
-+	"BMI:              0x400\n"
-+	"REGULATORY:       0x800\n"
-+	"TESTMODE:        0x1000\n"
-+	"WMI-PRINT:       0x2000\n"
-+	"PCI-PS:          0x4000\n"
-+	"AHB:             0x8000\n"
-+	"SDIO:		 0x10000\n"
-+	"SDIO_DUMP:	 0x20000\n"
-+	"USB:		 0x40000\n"
-+	"USB_BULK:	 0x80000\n"
-+	"SNOC:		0x100000\n"
-+	"QMI:		0x200000\n"
-+	"BEACONS:      0x8000000\n"
-+	"NO-FW-DBGLOG:0x10000000\n"
-+	"MAC2:        0x20000000\n"
-+	"INFO-AS-DBG: 0x40000000\n"
-+	"FW:          0x80000000\n"
-+	"ALL:         0xEFFFFFFF\n";
-+
-+#define READ_DEBUG_LEVEL_SIZE sizeof(debug_level_buf) + 60
-+
- static ssize_t ath10k_read_debug_level(struct file *file,
- 				       char __user *user_buf,
- 				       size_t count, loff_t *ppos)
- {
--	int sz;
--	const char buf[] =
--		"To change debug level, set value adding up desired flags:\n"
--		"PCI:                0x1\n"
--		"WMI:                0x2\n"
--		"HTC:                0x4\n"
--		"HTT:                0x8\n"
--		"MAC:               0x10\n"
--		"BOOT:              0x20\n"
--		"PCI-DUMP:          0x40\n"
--		"HTT-DUMP:          0x80\n"
--		"MGMT:             0x100\n"
--		"DATA:             0x200\n"
--		"BMI:              0x400\n"
--		"REGULATORY:       0x800\n"
--		"TESTMODE:        0x1000\n"
--		"WMI-PRINT:       0x2000\n"
--		"PCI-PS:          0x4000\n"
--		"AHB:             0x8000\n"
--		"SDIO:		 0x10000\n"
--		"SDIO_DUMP:	 0x20000\n"
--		"USB:		 0x40000\n"
--		"USB_BULK:	 0x80000\n"
--		"SNOC:		0x100000\n"
--		"QMI:		0x200000\n"
--		"BEACONS:      0x8000000\n"
--		"NO-FW-DBGLOG:0x10000000\n"
--		"MAC2:        0x20000000\n"
--		"INFO-AS-DBG: 0x40000000\n"
--		"FW:          0x80000000\n"
--		"ALL:         0xEFFFFFFF\n";
--	char wbuf[sizeof(buf) + 60];
--	sz = snprintf(wbuf, sizeof(wbuf), "Current debug level: 0x%x\n\n%s",
--		      ath10k_debug_mask, buf);
--	wbuf[sizeof(wbuf) - 1] = 0;
--
--	return simple_read_from_buffer(user_buf, count, ppos, wbuf, sz);
-+	int sz, ret;
-+	char *wbuf;
-+
-+	wbuf = kcalloc(READ_DEBUG_LEVEL_SIZE, sizeof(char), GFP_KERNEL);
-+	if (!wbuf)
-+		return -ENOMEM;
-+
-+	sz = snprintf(wbuf, READ_DEBUG_LEVEL_SIZE,
-+		      "Current debug level: 0x%x\n\n%s",
-+		      ath10k_debug_mask, debug_level_buf);
-+
-+	ret = simple_read_from_buffer(user_buf, count, ppos, wbuf, sz);
-+	kfree(wbuf);
-+
-+	return ret;
- }
- 
- /* Set logging level.
-diff --git a/ath10k-5.17/debug.c b/ath10k-5.17/debug.c
-index af84012..d0fa911 100644
---- a/ath10k-5.17/debug.c
-+++ b/ath10k-5.17/debug.c
-@@ -1344,47 +1344,58 @@ static const struct file_operations fops_simulate_fw_crash = {
- 	.llseek = default_llseek,
- };
- 
-+static const char debug_level_buf[] =
-+	"To change debug level, set value adding up desired flags:\n"
-+	"PCI:                0x1\n"
-+	"WMI:                0x2\n"
-+	"HTC:                0x4\n"
-+	"HTT:                0x8\n"
-+	"MAC:               0x10\n"
-+	"BOOT:              0x20\n"
-+	"PCI-DUMP:          0x40\n"
-+	"HTT-DUMP:          0x80\n"
-+	"MGMT:             0x100\n"
-+	"DATA:             0x200\n"
-+	"BMI:              0x400\n"
-+	"REGULATORY:       0x800\n"
-+	"TESTMODE:        0x1000\n"
-+	"WMI-PRINT:       0x2000\n"
-+	"PCI-PS:          0x4000\n"
-+	"AHB:             0x8000\n"
-+	"SDIO:		 0x10000\n"
-+	"SDIO_DUMP:	 0x20000\n"
-+	"USB:		 0x40000\n"
-+	"USB_BULK:	 0x80000\n"
-+	"SNOC:		0x100000\n"
-+	"QMI:		0x200000\n"
-+	"BEACONS:      0x8000000\n"
-+	"NO-FW-DBGLOG:0x10000000\n"
-+	"MAC2:        0x20000000\n"
-+	"INFO-AS-DBG: 0x40000000\n"
-+	"FW:          0x80000000\n"
-+	"ALL:         0xEFFFFFFF\n";
-+
-+#define READ_DEBUG_LEVEL_SIZE sizeof(debug_level_buf) + 60
-+
- static ssize_t ath10k_read_debug_level(struct file *file,
- 				       char __user *user_buf,
- 				       size_t count, loff_t *ppos)
- {
--	int sz;
--	const char buf[] =
--		"To change debug level, set value adding up desired flags:\n"
--		"PCI:                0x1\n"
--		"WMI:                0x2\n"
--		"HTC:                0x4\n"
--		"HTT:                0x8\n"
--		"MAC:               0x10\n"
--		"BOOT:              0x20\n"
--		"PCI-DUMP:          0x40\n"
--		"HTT-DUMP:          0x80\n"
--		"MGMT:             0x100\n"
--		"DATA:             0x200\n"
--		"BMI:              0x400\n"
--		"REGULATORY:       0x800\n"
--		"TESTMODE:        0x1000\n"
--		"WMI-PRINT:       0x2000\n"
--		"PCI-PS:          0x4000\n"
--		"AHB:             0x8000\n"
--		"SDIO:		 0x10000\n"
--		"SDIO_DUMP:	 0x20000\n"
--		"USB:		 0x40000\n"
--		"USB_BULK:	 0x80000\n"
--		"SNOC:		0x100000\n"
--		"QMI:		0x200000\n"
--		"BEACONS:      0x8000000\n"
--		"NO-FW-DBGLOG:0x10000000\n"
--		"MAC2:        0x20000000\n"
--		"INFO-AS-DBG: 0x40000000\n"
--		"FW:          0x80000000\n"
--		"ALL:         0xEFFFFFFF\n";
--	char wbuf[sizeof(buf) + 60];
--	sz = snprintf(wbuf, sizeof(wbuf), "Current debug level: 0x%x\n\n%s",
--		      ath10k_debug_mask, buf);
--	wbuf[sizeof(wbuf) - 1] = 0;
--
--	return simple_read_from_buffer(user_buf, count, ppos, wbuf, sz);
-+	int sz, ret;
-+	char *wbuf;
-+
-+	wbuf = kcalloc(READ_DEBUG_LEVEL_SIZE, sizeof(char), GFP_KERNEL);
-+	if (!wbuf)
-+		return -ENOMEM;
-+
-+	sz = snprintf(wbuf, READ_DEBUG_LEVEL_SIZE,
-+		      "Current debug level: 0x%x\n\n%s",
-+		      ath10k_debug_mask, debug_level_buf);
-+
-+	ret = simple_read_from_buffer(user_buf, count, ppos, wbuf, sz);
-+	kfree(wbuf);
-+
-+	return ret;
- }
- 
- /* Set logging level.
--- 
-2.39.2
-

package/kernel/ath10k-ct/patches/300-ath10k-ct-Fix-spectral-scan-NULL-pointer.patch

@@ -1,32 +0,0 @@
-From 0d2e335d780bda1432a9ba719c8200f796d27854 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 29 Nov 2021 12:27:12 +0100
-Subject: [PATCH] ath10k-ct: Fix spectral scan NULL pointer
-
-If spectral scan support is enabled then ath10k-ct will cause a NULL
-pointer due to relay_open() being called with a const callback struct
-which is only supported in kernel 5.11 and later.
-
-So, simply check the kernel version and if 5.11 and newer use the const
-callback struct, otherwise use the regular struct.
-
-Fixes: 553a3ac ("ath10k-ct: use 5.15 version")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- ath10k-5.15/spectral.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/ath10k-5.15/spectral.c
-+++ b/ath10k-5.15/spectral.c
-@@ -497,7 +497,11 @@ static int remove_buf_file_handler(struc
- 	return 0;
- }
- 
-+#if LINUX_VERSION_IS_GEQ(5,11,0)
- static const struct rchan_callbacks rfs_spec_scan_cb = {
-+#else
-+static struct rchan_callbacks rfs_spec_scan_cb = {
-+#endif
- 	.create_buf_file = create_buf_file_handler,
- 	.remove_buf_file = remove_buf_file_handler,
- };

package/kernel/ath10k-ct/patches/960-0010-ath10k-limit-htt-rx-ring-size.patch

@@ -1,5 +1,5 @@
---- a/ath10k-5.15/htt.h
-+++ b/ath10k-5.15/htt.h
+--- a/ath10k-6.2/htt.h
++++ b/ath10k-6.2/htt.h
 @@ -237,7 +237,11 @@ enum htt_rx_ring_flags {
  };
  

package/kernel/ath10k-ct/patches/960-0011-ath10k-limit-pci-buffer-size.patch

@@ -1,5 +1,5 @@
---- a/ath10k-5.15/pci.c
-+++ b/ath10k-5.15/pci.c
+--- a/ath10k-6.2/pci.c
++++ b/ath10k-6.2/pci.c
 @@ -131,7 +131,11 @@ static const struct ce_attr pci_host_ce_
  		.flags = CE_ATTR_FLAGS,
  		.src_nentries = 0,

package/kernel/linux/modules/netfilter.mk

@@ -1,6 +1,6 @@
 
 #
-# Copyright (C) 2006-2010 OpenWrt.org
+# Copyright (C) 2006-2023 OpenWrt.org
 #
 # This is free software, licensed under the GNU General Public License v2.
 # See /LICENSE for more information.
@@ -1146,6 +1146,26 @@ endef
 $(eval $(call KernelPackage,nft-bridge))
 
 
+define KernelPackage/nft-dup-inet
+  SUBMENU:=$(NF_MENU)
+  TITLE:=Netfilter nf_tables dup in ip/ip6/inet familly support
+  DEPENDS:=+kmod-nft-core +kmod-nf-conntrack +IPV6:kmod-nf-conntrack6
+  KCONFIG:= \
+	CONFIG_NF_DUP_IPV4 \
+	CONFIG_NF_DUP_IPV6 \
+	CONFIG_NFT_DUP_IPV4 \
+	CONFIG_NFT_DUP_IPV6
+  FILES:= \
+	$(LINUX_DIR)/net/ipv4/netfilter/nf_dup_ipv4.ko \
+	$(LINUX_DIR)/net/ipv6/netfilter/nf_dup_ipv6.ko \
+	$(LINUX_DIR)/net/ipv4/netfilter/nft_dup_ipv4.ko \
+	$(LINUX_DIR)/net/ipv6/netfilter/nft_dup_ipv6.ko
+  AUTOLOAD:=$(call AutoProbe,nf_dup_ipv4 nf_dup_ipv6 nft_dup_ipv4 nft_dup_ipv6)
+endef
+
+$(eval $(call KernelPackage,nft-dup-inet))
+
+
 define KernelPackage/nft-nat
   SUBMENU:=$(NF_MENU)
   TITLE:=Netfilter nf_tables NAT support

package/kernel/qca-nss-dp/patches/0014-nss-dp-edma-v1-use-NAPI-GRO-by-default.patch

@@ -18,8 +18,6 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c      |  8 ++++++--
  2 files changed, 12 insertions(+), 6 deletions(-)
 
-diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
-index 1d748db..e81c461 100644
 --- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
 +++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
 @@ -589,10 +589,12 @@ drop:
@@ -39,11 +37,9 @@ index 1d748db..e81c461 100644
  }
  
  /* TODO - check if this is needed */
-diff --git a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c
-index 5780a30..a002a79 100644
 --- a/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c
 +++ b/hal/dp_ops/edma_dp/edma_v1/edma_tx_rx.c
-@@ -410,8 +410,12 @@ static uint32_t edma_clean_rx(struct edma_hw *ehw,
+@@ -410,8 +410,12 @@ static uint32_t edma_clean_rx(struct edm
  		if (unlikely(EDMA_RXPH_SERVICE_CODE_GET(rxph) ==
  					NSS_PTP_EVENT_SERVICE_CODE))
  			nss_phy_tstamp_rx_buf(ndev, skb);
@@ -58,6 +54,3 @@ index 5780a30..a002a79 100644
  
  next_rx_desc:
  		/*
--- 
-2.38.1
-

package/kernel/qca-nss-dp/patches/0015-nss-dp-allow-setting-netdev-name-from-DTS.patch

@@ -13,11 +13,9 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
  nss_dp_main.c | 17 ++++++++++++++---
  1 file changed, 14 insertions(+), 3 deletions(-)
 
-diff --git a/nss_dp_main.c b/nss_dp_main.c
-index 18e1088..19e14fb 100644
 --- a/nss_dp_main.c
 +++ b/nss_dp_main.c
-@@ -685,18 +685,29 @@ static int32_t nss_dp_probe(struct platform_device *pdev)
+@@ -685,18 +685,29 @@ static int32_t nss_dp_probe(struct platf
  	struct nss_dp_dev *dp_priv;
  	struct device_node *np = pdev->dev.of_node;
  	struct nss_gmac_hal_platform_data gmac_hal_pdata;
@@ -50,6 +48,3 @@ index 18e1088..19e14fb 100644
  		return -ENOMEM;
  	}
  
--- 
-2.38.1
-

package/kernel/qca-nss-dp/patches/0016-nss-dp-netdev-mac_addr-is-const.patch

@@ -0,0 +1,57 @@
+From ff9284e3a59982c78a0132e6f2c5e3f04ba11472 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Thu, 29 Sep 2022 20:37:46 +0200
+Subject: [PATCH 15/16] nss-dp: netdev mac_addr is const
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ exports/nss_dp_api_if.h                      | 2 +-
+ hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 2 +-
+ hal/dp_ops/edma_dp/edma_v2/edma_dp.c         | 2 +-
+ hal/dp_ops/syn_gmac_dp/syn_dp.c              | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/exports/nss_dp_api_if.h
++++ b/exports/nss_dp_api_if.h
+@@ -83,7 +83,7 @@ struct nss_dp_data_plane_ops {
+ 	int (*close)(struct nss_dp_data_plane_ctx *dpc);
+ 	int (*link_state)(struct nss_dp_data_plane_ctx *dpc,
+ 			  uint32_t link_state);
+-	int (*mac_addr)(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr);
++	int (*mac_addr)(struct nss_dp_data_plane_ctx *dpc, const uint8_t *addr);
+ 	int (*change_mtu)(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu);
+ 	netdev_tx_t (*xmit)(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *os_buf);
+ 	void (*set_features)(struct nss_dp_data_plane_ctx *dpc);
+--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
+@@ -494,7 +494,7 @@ static int edma_if_link_state(struct nss
+ /*
+  * edma_if_mac_addr()
+  */
+-static int edma_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
++static int edma_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, const uint8_t *addr)
+ {
+ 	return NSS_DP_SUCCESS;
+ }
+--- a/hal/dp_ops/edma_dp/edma_v2/edma_dp.c
++++ b/hal/dp_ops/edma_dp/edma_v2/edma_dp.c
+@@ -99,7 +99,7 @@ static int edma_dp_link_state(struct nss
+  * edma_dp_mac_addr()
+  *	EDMA data plane MAC address change API
+  */
+-static int edma_dp_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
++static int edma_dp_mac_addr(struct nss_dp_data_plane_ctx *dpc, const uint8_t *addr)
+ {
+ 	return NSS_DP_SUCCESS;
+ }
+--- a/hal/dp_ops/syn_gmac_dp/syn_dp.c
++++ b/hal/dp_ops/syn_gmac_dp/syn_dp.c
+@@ -289,7 +289,7 @@ static int syn_dp_if_link_state(struct n
+ /*
+  * syn_dp_if_mac_addr()
+  */
+-static int syn_dp_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
++static int syn_dp_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, const uint8_t *addr)
+ {
+ 	return NSS_DP_SUCCESS;
+ }

package/kernel/qca-nss-dp/patches/0017-nss-dp-use-proper-netdev-MAC-helpers.patch

@@ -0,0 +1,27 @@
+From 704706969301076961c15423dedce9e2e6f1026e Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Thu, 29 Sep 2022 20:39:07 +0200
+Subject: [PATCH 16/16] nss-dp: use proper netdev MAC helpers
+
+mac_addr is const, so utilize proper helpers for setting random and
+desired MAC addres as old ones were dropped in newer kernels.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ nss_dp_main.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/nss_dp_main.c
++++ b/nss_dp_main.c
+@@ -599,9 +599,9 @@ static int32_t nss_dp_of_get_pdata(struc
+ 
+ 	ret = of_get_mac_address(np, maddr);
+ 	if (!ret && is_valid_ether_addr(maddr)) {
+-		ether_addr_copy(netdev->dev_addr, maddr);
++		eth_hw_addr_set(netdev, maddr);
+ 	} else {
+-		random_ether_addr(netdev->dev_addr);
++		eth_hw_addr_random(netdev);
+ 		pr_info("GMAC%d(%px) Invalid MAC@ - using %pM\n", dp_priv->macid,
+ 						dp_priv, netdev->dev_addr);
+ 	}

package/kernel/qca-nss-dp/patches/0018-nss-dp-adapt-to-netif_napi_add-changes.patch

@@ -0,0 +1,84 @@
+From ba748ab91a62db57f9bdf69dd306e6557315db85 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 3 Oct 2022 23:05:14 +0200
+Subject: [PATCH] nss-dp: adapt to netif_napi_add() changes
+
+netif_napi_add() removed the weight argument and just uses the default
+NAPI_POLL_WEIGHT in background, so for those requiring custom weight use
+netif_napi_add_weight() instead.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 6 +++++-
+ hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.c     | 8 +++++++-
+ hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.c     | 7 ++++++-
+ hal/dp_ops/syn_gmac_dp/syn_dp.c              | 5 +++++
+ 4 files changed, 23 insertions(+), 3 deletions(-)
+
+--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
+@@ -838,8 +838,12 @@ static int edma_register_netdevice(struc
+ 	 * NAPI add
+ 	 */
+ 	if (!edma_hw.napi_added) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
+ 		netif_napi_add(netdev, &edma_hw.napi, edma_napi,
+-				NAPI_POLL_WEIGHT);
++			       NAPI_POLL_WEIGHT);
++#else
++		netif_napi_add(netdev, &edma_hw.napi, edma_napi);
++#endif
+ 		/*
+ 		 * Register the interrupt handlers and enable interrupts
+ 		 */
+--- a/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.c
++++ b/hal/dp_ops/edma_dp/edma_v2/edma_cfg_rx.c
+@@ -1097,8 +1097,14 @@ void edma_cfg_rx_napi_add(struct edma_gb
+ 
+ 	for (i = 0; i < egc->num_rxdesc_rings; i++) {
+ 		struct edma_rxdesc_ring *rxdesc_ring = &egc->rxdesc_rings[i];
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
+ 		netif_napi_add(netdev, &rxdesc_ring->napi,
+-				edma_rx_napi_poll, nss_dp_rx_napi_budget);
++			       edma_rx_napi_poll, nss_dp_rx_napi_budget);
++
++#else
++		netif_napi_add_weight(netdev, &rxdesc_ring->napi,
++				      edma_rx_napi_poll, nss_dp_rx_napi_budget);
++#endif
+ 		rxdesc_ring->napi_added = true;
+ 	}
+ 	edma_info("%s: Rx NAPI budget: %d\n", netdev->name, nss_dp_rx_napi_budget);
+--- a/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.c
++++ b/hal/dp_ops/edma_dp/edma_v2/edma_cfg_tx.c
+@@ -672,8 +672,13 @@ void edma_cfg_tx_napi_add(struct edma_gb
+ 	for (i = 0; i < egc->num_txcmpl_rings; i++) {
+ 		struct edma_txcmpl_ring *txcmpl_ring = &egc->txcmpl_rings[i];
+ 
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
+ 		netif_napi_add(netdev, &txcmpl_ring->napi,
+-				edma_tx_napi_poll, nss_dp_tx_napi_budget);
++			       edma_tx_napi_poll, nss_dp_tx_napi_budget);
++#else
++		netif_napi_add_weight(netdev, &txcmpl_ring->napi,
++				      edma_tx_napi_poll, nss_dp_tx_napi_budget);
++#endif
+ 		txcmpl_ring->napi_added = true;
+ 	}
+ 	edma_info("Tx NAPI budget: %d\n", nss_dp_tx_napi_budget);
+--- a/hal/dp_ops/syn_gmac_dp/syn_dp.c
++++ b/hal/dp_ops/syn_gmac_dp/syn_dp.c
+@@ -189,8 +189,13 @@ static int syn_dp_if_init(struct nss_dp_
+ 	}
+ 
+ 	if (!dev_info->napi_added) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
+ 		netif_napi_add(netdev, &rx_info->napi_rx, syn_dp_napi_poll_rx, SYN_DP_NAPI_BUDGET_RX);
+ 		netif_napi_add(netdev, &tx_info->napi_tx, syn_dp_napi_poll_tx, SYN_DP_NAPI_BUDGET_TX);
++#else
++		netif_napi_add_weight(netdev, &rx_info->napi_rx, syn_dp_napi_poll_rx, SYN_DP_NAPI_BUDGET_RX);
++		netif_napi_add_weight(netdev, &tx_info->napi_tx, syn_dp_napi_poll_tx, SYN_DP_NAPI_BUDGET_TX);
++#endif
+ 
+ 		/*
+ 		 * Requesting irq. Set IRQ_DISABLE_UNLAZY flag, this flag

package/kernel/qca-ssdk/patches/0015-SSDK-config-add-kernel-6.1.patch

@@ -0,0 +1,55 @@
+From 1f9eb43f118b86c0b68e9d82bfae77471d6c3921 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Thu, 29 Sep 2022 09:59:20 +0200
+Subject: [PATCH] SSDK: config: add kernel 6.1
+
+Allow kernel 6.1 to be recognized and compiled under it.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ config            | 6 +++++-
+ make/linux_opt.mk | 4 ++--
+ 2 files changed, 7 insertions(+), 3 deletions(-)
+
+--- a/config
++++ b/config
+@@ -28,6 +28,10 @@ ifeq ($(KVER),$(filter 5.15%,$(KVER)))
+ OS_VER=5_15
+ endif
+ 
++ifeq ($(KVER),$(filter 6.1%,$(KVER)))
++OS_VER=6_1
++endif
++
+ ifeq ($(KVER), 3.4.0)
+ 	OS_VER=3_4
+ endif
+@@ -136,7 +140,7 @@ ifeq ($(ARCH), arm)
+ endif
+ 
+ ifeq ($(ARCH), arm64)
+-	ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.15%,$(KVER)))
++	ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4% 5.15% 6.1%,$(KVER)))
+ 		CPU_CFLAG=  -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large
+ 	endif
+ endif
+--- a/make/linux_opt.mk
++++ b/make/linux_opt.mk
+@@ -437,7 +437,7 @@ ifeq (KSLIB, $(MODULE_TYPE))
+       KASAN_SHADOW_SCALE_SHIFT := 3
+   endif
+ 
+-  ifeq (5_4 5_15, $(OS_VER))
++  ifeq (5_4 5_15 6_1, $(OS_VER))
+       ifeq ($(ARCH), arm64)
+           KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)
+        endif
+@@ -468,7 +468,7 @@ ifeq (KSLIB, $(MODULE_TYPE))
+ 
+   endif
+ 
+-  ifeq ($(OS_VER),$(filter 4_4 5_4 5_15, $(OS_VER)))
++  ifeq ($(OS_VER),$(filter 4_4 5_4 5_15 6_1, $(OS_VER)))
+                 MODULE_CFLAG += -DKVER34
+                 MODULE_CFLAG += -DKVER32
+             MODULE_CFLAG += -DLNX26_22

package/kernel/qca-ssdk/patches/0016-SSDK-qca808x-use-get_random_u32.patch

@@ -0,0 +1,27 @@
+From 55ea8c9b278aafe3211f7250986b1f9d9a06cd21 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 21 Oct 2022 13:40:15 +0200
+Subject: [PATCH] SSDK: qca808x: use get_random_u32
+
+prandom has been removed from the kernel in 6.1-rc1, so use get_random_u32
+instead as its the drop-in replacement.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ src/hsl/phy/qca808x_phy.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/src/hsl/phy/qca808x_phy.c
++++ b/src/hsl/phy/qca808x_phy.c
+@@ -299,7 +299,11 @@ qca808x_phy_ms_random_seed_set(a_uint32_
+ 	phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+ 		QCA808X_DEBUG_LOCAL_SEED);
+ 	phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_CFG);
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
+ 	phy_data |= (prandom_u32()%QCA808X_MASTER_SLAVE_SEED_RANGE) << 2;
++#else
++	phy_data |= (get_random_u32()%QCA808X_MASTER_SLAVE_SEED_RANGE) << 2;
++#endif
+ 	SSDK_DEBUG("QCA808X_DEBUG_LOCAL_SEED:%x\n", phy_data);
+ 	rv = qca808x_phy_debug_write(dev_id, phy_id,
+ 		QCA808X_DEBUG_LOCAL_SEED, phy_data);

package/libs/openssl/patches/110-openwrt_targets.patch

@@ -9,7 +9,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
 
 --- /dev/null
 +++ b/Configurations/25-openwrt.conf
-@@ -0,0 +1,52 @@
+@@ -0,0 +1,56 @@
 +## Openwrt "CONFIG_ARCH" matching targets.
 +
 +# The targets need to end in '-openwrt' for the AFALG patch to work
@@ -53,6 +53,10 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
 +        inherit_from    => [ "linux-ppc64", "openwrt" ],
 +        perlasm_scheme  => "linux64v2",
 +    },
++    "linux-riscv64-openwrt" => {
++        inherit_from    => [ "linux-generic64", "openwrt" ],
++        perlasm_scheme   => "linux64",
++    },
 +    "linux-x86_64-openwrt" => {
 +        inherit_from    => [ "linux-x86_64", "openwrt" ],
 +    },

package/libs/pcre2/Makefile

@@ -66,7 +66,8 @@ CMAKE_HOST_OPTIONS += \
 	-DPCRE2_SUPPORT_JIT=OFF \
 	-DPCRE2_SHOW_REPORT=OFF \
 	-DPCRE2_BUILD_PCRE2GREP=OFF \
-	-DPCRE2_BUILD_TESTS=OFF
+	-DPCRE2_BUILD_TESTS=OFF \
+	-DPCRE2_STATIC_PIC=ON
 
 CMAKE_OPTIONS += \
 	-DBUILD_SHARED_LIBS=ON \

target/Config.in

@@ -184,6 +184,10 @@ config powerpc64
 	select ARCH_64BIT
 	bool
 
+config riscv64
+	select ARCH_64BIT
+	bool
+
 config sh3
 	bool
 
@@ -223,6 +227,7 @@ config ARCH
 	default "mips64el"  if mips64el
 	default "powerpc"   if powerpc
 	default "powerpc64" if powerpc64
+	default "riscv64"   if riscv64
 	default "sh3"       if sh3
 	default "sh3eb"     if sh3eb
 	default "sh4"       if sh4

target/linux/ipq807x/Makefile

@@ -9,6 +9,7 @@ CPU_TYPE:=cortex-a53
 SUBTARGETS:=generic
 
 KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \

target/linux/ipq807x/config-6.1

@@ -0,0 +1,566 @@
+CONFIG_64BIT=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+# CONFIG_ARM_MHU_V2 is not set
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16=y
+CONFIG_CRC8=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCE_AEAD=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
+CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
+CONFIG_CRYPTO_DEV_QCE_SHA=y
+CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SM3_NEON is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEV_COREDUMP=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_QCOM_CCI is not set
+CONFIG_I2C_QUP=y
+CONFIG_IIO=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IPQ_APSS_6018=y
+CONFIG_IPQ_APSS_PLL=y
+# CONFIG_IPQ_GCC_4019 is not set
+# CONFIG_IPQ_GCC_6018 is not set
+# CONFIG_IPQ_GCC_806X is not set
+CONFIG_IPQ_GCC_8074=y
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_KPSS_XCC is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_IPQ4019=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_MFD_QCOM_RPM is not set
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8909 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8939 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8976 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_GPUCC_8998 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+# CONFIG_MSM_MMCC_8998 is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_QCOMSMEM_PARTS=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_QCOM_QFPROM=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_EDP is not set
+# CONFIG_PHY_QCOM_IPQ4019_USB is not set
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_USB is not set
+# CONFIG_PHY_QCOM_PCIE2 is not set
+CONFIG_PHY_QCOM_QMP=y
+CONFIG_PHY_QCOM_QUSB2=y
+# CONFIG_PHY_QCOM_USB_HS_28NM is not set
+# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
+# CONFIG_PHY_QCOM_USB_SS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_IPQ6018 is not set
+CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8976 is not set
+# CONFIG_PINCTRL_MSM8994 is not set
+# CONFIG_PINCTRL_MSM8996 is not set
+# CONFIG_PINCTRL_MSM8998 is not set
+# CONFIG_PINCTRL_QCM2290 is not set
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PINCTRL_QCS404 is not set
+# CONFIG_PINCTRL_SC7180 is not set
+# CONFIG_PINCTRL_SC8280XP is not set
+# CONFIG_PINCTRL_SDM660 is not set
+# CONFIG_PINCTRL_SDM845 is not set
+# CONFIG_PINCTRL_SM6350 is not set
+# CONFIG_PINCTRL_SM6375 is not set
+# CONFIG_PINCTRL_SM8150 is not set
+# CONFIG_PINCTRL_SM8250 is not set
+# CONFIG_PINCTRL_SM8450 is not set
+CONFIG_PM=y
+# CONFIG_PM8916_WATCHDOG is not set
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_MSM is not set
+# CONFIG_POWER_RESET_QCOM_PON is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PREEMPT_DYNAMIC is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+# CONFIG_QCM_DISPCC_2290 is not set
+# CONFIG_QCM_GCC_2290 is not set
+# CONFIG_QCOM_A53PLL is not set
+# CONFIG_QCOM_AOSS_QMP is not set
+CONFIG_QCOM_APCS_IPC=y
+CONFIG_QCOM_APM=y
+# CONFIG_QCOM_APR is not set
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
+# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
+# CONFIG_QCOM_CLK_APCS_SDX55 is not set
+# CONFIG_QCOM_COINCELL is not set
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_CPR is not set
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_FASTRPC is not set
+CONFIG_QCOM_GDSC=y
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_HFPLL is not set
+# CONFIG_QCOM_ICC_BWMON is not set
+# CONFIG_QCOM_IPCC is not set
+# CONFIG_QCOM_LLCC is not set
+CONFIG_QCOM_MDT_LOADER=y
+# CONFIG_QCOM_MPM is not set
+# CONFIG_QCOM_OCMEM is not set
+# CONFIG_QCOM_PDC is not set
+CONFIG_QCOM_PIL_INFO=y
+# CONFIG_QCOM_Q6V5_ADSP is not set
+CONFIG_QCOM_Q6V5_COMMON=y
+# CONFIG_QCOM_Q6V5_MSS is not set
+# CONFIG_QCOM_Q6V5_PAS is not set
+CONFIG_QCOM_Q6V5_WCSS=y
+# CONFIG_QCOM_RMTFS_MEM is not set
+# CONFIG_QCOM_RPMH is not set
+CONFIG_QCOM_RPROC_COMMON=y
+CONFIG_QCOM_SCM=y
+# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+# CONFIG_QCOM_SMD_RPM is not set
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMEM_STATE=y
+CONFIG_QCOM_SMP2P=y
+# CONFIG_QCOM_SMSM is not set
+CONFIG_QCOM_SOCINFO=y
+# CONFIG_QCOM_SPM is not set
+CONFIG_QCOM_SPMI_ADC5=y
+# CONFIG_QCOM_SPMI_RRADC is not set
+# CONFIG_QCOM_STATS is not set
+# CONFIG_QCOM_SYSMON is not set
+CONFIG_QCOM_TSENS=y
+CONFIG_QCOM_VADC_COMMON=y
+# CONFIG_QCOM_WCNSS_CTRL is not set
+# CONFIG_QCOM_WCNSS_PIL is not set
+CONFIG_QCOM_WDT=y
+# CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_Q6SSTOP_404 is not set
+# CONFIG_QCS_TURING_404 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPMI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_CPR3=y
+# CONFIG_REGULATOR_CPR3_NPU is not set
+CONFIG_REGULATOR_CPR4_APSS=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+CONFIG_REGULATOR_QCOM_SPMI=y
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
+CONFIG_RELOCATABLE=y
+CONFIG_REMOTEPROC=y
+CONFIG_REMOTEPROC_CDEV=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+# CONFIG_RPMSG_CTRL is not set
+# CONFIG_RPMSG_NS is not set
+CONFIG_RPMSG_QCOM_GLINK=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_GLINK_SMEM=y
+CONFIG_RPMSG_QCOM_SMD=y
+# CONFIG_RPMSG_TTY is not set
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SCHED_CLUSTER is not set
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SC_CAMCC_7280 is not set
+# CONFIG_SC_DISPCC_7180 is not set
+# CONFIG_SC_GCC_7180 is not set
+# CONFIG_SC_GCC_8280XP is not set
+# CONFIG_SC_GPUCC_7180 is not set
+# CONFIG_SC_LPASSCC_7280 is not set
+# CONFIG_SC_LPASS_CORECC_7180 is not set
+# CONFIG_SC_LPASS_CORECC_7280 is not set
+# CONFIG_SC_MSS_7180 is not set
+# CONFIG_SC_VIDEOCC_7180 is not set
+# CONFIG_SDM_CAMCC_845 is not set
+# CONFIG_SDM_DISPCC_845 is not set
+# CONFIG_SDM_GCC_660 is not set
+# CONFIG_SDM_GCC_845 is not set
+# CONFIG_SDM_GPUCC_845 is not set
+# CONFIG_SDM_LPASSCC_845 is not set
+# CONFIG_SDM_VIDEOCC_845 is not set
+# CONFIG_SDX_GCC_65 is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+# CONFIG_SHADOW_CALL_STACK is not set
+CONFIG_SMP=y
+# CONFIG_SM_CAMCC_8450 is not set
+# CONFIG_SM_GCC_8150 is not set
+# CONFIG_SM_GCC_8250 is not set
+# CONFIG_SM_GCC_8450 is not set
+# CONFIG_SM_GPUCC_6350 is not set
+# CONFIG_SM_GPUCC_8150 is not set
+# CONFIG_SM_GPUCC_8250 is not set
+# CONFIG_SM_GPUCC_8350 is not set
+# CONFIG_SM_VIDEOCC_8150 is not set
+# CONFIG_SM_VIDEOCC_8250 is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_PMIC_CLKDIV is not set
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_ANCHOR=y
+# CONFIG_VIRTIO_BLK is not set
+# CONFIG_VIRTIO_NET is not set
+CONFIG_VMAP_STACK=y
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_SYSFS=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y

target/linux/ipq807x/patches-5.15/0080-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch

@@ -14,7 +14,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -801,6 +801,7 @@
+@@ -766,6 +766,7 @@
  			linux,pci-domain = <1>;
  			bus-range = <0x00 0xff>;
  			num-lanes = <1>;

target/linux/ipq807x/patches-6.1/0040-v6.2-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch

@@ -0,0 +1,32 @@
+From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:06:28 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
+
+Add the required node for A53 PLL which will be used to provide the CPU
+clock via APCS for APSS scaling.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -675,6 +675,14 @@
+ 			#mbox-cells = <1>;
+ 		};
+ 
++		a53pll: clock@b116000 {
++			compatible = "qcom,ipq8074-a53pll";
++			reg = <0x0b116000 0x40>;
++			#clock-cells = <0>;
++			clocks = <&xo>;
++			clock-names = "xo";
++		};
++
+ 		timer@b120000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;

target/linux/ipq807x/patches-6.1/0042-v6.2-thermal-drivers-tsens-Add-support-for-combined-inter.patch

@@ -0,0 +1,134 @@
+From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:42 +0200
+Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
+
+Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
+signaling both up/low and critical trips.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c |  1 +
+ drivers/thermal/qcom/tsens-v0_1.c |  1 +
+ drivers/thermal/qcom/tsens-v1.c   |  1 +
+ drivers/thermal/qcom/tsens-v2.c   |  1 +
+ drivers/thermal/qcom/tsens.c      | 38 ++++++++++++++++++++++++++-----
+ drivers/thermal/qcom/tsens.h      |  2 ++
+ 6 files changed, 38 insertions(+), 6 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
+ static struct tsens_features tsens_8960_feat = {
+ 	.ver_major	= VER_0,
+ 	.crit_int	= 0,
++	.combo_int	= 0,
+ 	.adc		= 1,
+ 	.srot_split	= 0,
+ 	.max_sensors	= 11,
+--- a/drivers/thermal/qcom/tsens-v0_1.c
++++ b/drivers/thermal/qcom/tsens-v0_1.c
+@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
+ static struct tsens_features tsens_v0_1_feat = {
+ 	.ver_major	= VER_0_1,
+ 	.crit_int	= 0,
++	.combo_int	= 0,
+ 	.adc		= 1,
+ 	.srot_split	= 1,
+ 	.max_sensors	= 11,
+--- a/drivers/thermal/qcom/tsens-v1.c
++++ b/drivers/thermal/qcom/tsens-v1.c
+@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
+ static struct tsens_features tsens_v1_feat = {
+ 	.ver_major	= VER_1_X,
+ 	.crit_int	= 0,
++	.combo_int	= 0,
+ 	.adc		= 1,
+ 	.srot_split	= 1,
+ 	.max_sensors	= 11,
+--- a/drivers/thermal/qcom/tsens-v2.c
++++ b/drivers/thermal/qcom/tsens-v2.c
+@@ -31,6 +31,7 @@
+ static struct tsens_features tsens_v2_feat = {
+ 	.ver_major	= VER_2_X,
+ 	.crit_int	= 1,
++	.combo_int	= 0,
+ 	.adc		= 0,
+ 	.srot_split	= 1,
+ 	.max_sensors	= 16,
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
+ 	return IRQ_HANDLED;
+ }
+ 
++/**
++ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
++ * @irq: irq number
++ * @data: tsens controller private data
++ *
++ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
++ * critical handler first and then the up/low one.
++ *
++ * Return: IRQ_HANDLED
++ */
++static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
++{
++	irqreturn_t ret;
++
++	ret = tsens_critical_irq_thread(irq, data);
++	if (ret != IRQ_HANDLED)
++		return ret;
++
++	return tsens_irq_thread(irq, data);
++}
++
+ static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
+ {
+ 	struct tsens_sensor *s = tz->devdata;
+@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
+ 				   tsens_mC_to_hw(priv->sensor, 0));
+ 	}
+ 
+-	ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
+-	if (ret < 0)
+-		return ret;
++	if (priv->feat->combo_int) {
++		ret = tsens_register_irq(priv, "combined",
++					 tsens_combined_irq_thread);
++	} else {
++		ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
++		if (ret < 0)
++			return ret;
+ 
+-	if (priv->feat->crit_int)
+-		ret = tsens_register_irq(priv, "critical",
+-					 tsens_critical_irq_thread);
++		if (priv->feat->crit_int)
++			ret = tsens_register_irq(priv, "critical",
++						 tsens_critical_irq_thread);
++	}
+ 
+ 	return ret;
+ }
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -493,6 +493,7 @@ enum regfield_ids {
+  * struct tsens_features - Features supported by the IP
+  * @ver_major: Major number of IP version
+  * @crit_int: does the IP support critical interrupts?
++ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
+  * @adc:      do the sensors only output adc code (instead of temperature)?
+  * @srot_split: does the IP neatly splits the register space into SROT and TM,
+  *              with SROT only being available to secure boot firmware?
+@@ -502,6 +503,7 @@ enum regfield_ids {
+ struct tsens_features {
+ 	unsigned int ver_major;
+ 	unsigned int crit_int:1;
++	unsigned int combo_int:1;
+ 	unsigned int adc:1;
+ 	unsigned int srot_split:1;
+ 	unsigned int has_watchdog:1;

target/linux/ipq807x/patches-6.1/0043-v6.2-thermal-drivers-tsens-Allow-configuring-min-and-max-.patch

@@ -0,0 +1,101 @@
+From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:43 +0200
+Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
+
+IPQ8074 and IPQ6018 dont support negative trip temperatures and support
+up to 204 degrees C as the max trip temperature.
+
+So, instead of always setting the -40 as min and 120 degrees C as max
+allow it to be configured as part of the features.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/qcom/tsens-8960.c | 2 ++
+ drivers/thermal/qcom/tsens-v0_1.c | 2 ++
+ drivers/thermal/qcom/tsens-v1.c   | 2 ++
+ drivers/thermal/qcom/tsens-v2.c   | 2 ++
+ drivers/thermal/qcom/tsens.c      | 4 ++--
+ drivers/thermal/qcom/tsens.h      | 4 ++++
+ 6 files changed, 14 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens-8960.c
++++ b/drivers/thermal/qcom/tsens-8960.c
+@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
+ 	.adc		= 1,
+ 	.srot_split	= 0,
+ 	.max_sensors	= 11,
++	.trip_min_temp	= -40000,
++	.trip_max_temp	= 120000,
+ };
+ 
+ struct tsens_plat_data data_8960 = {
+--- a/drivers/thermal/qcom/tsens-v0_1.c
++++ b/drivers/thermal/qcom/tsens-v0_1.c
+@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
+ 	.adc		= 1,
+ 	.srot_split	= 1,
+ 	.max_sensors	= 11,
++	.trip_min_temp	= -40000,
++	.trip_max_temp	= 120000,
+ };
+ 
+ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
+--- a/drivers/thermal/qcom/tsens-v1.c
++++ b/drivers/thermal/qcom/tsens-v1.c
+@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
+ 	.adc		= 1,
+ 	.srot_split	= 1,
+ 	.max_sensors	= 11,
++	.trip_min_temp	= -40000,
++	.trip_max_temp	= 120000,
+ };
+ 
+ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
+--- a/drivers/thermal/qcom/tsens-v2.c
++++ b/drivers/thermal/qcom/tsens-v2.c
+@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
+ 	.adc		= 0,
+ 	.srot_split	= 1,
+ 	.max_sensors	= 16,
++	.trip_min_temp	= -40000,
++	.trip_max_temp	= 120000,
+ };
+ 
+ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
+ 	dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
+ 		hw_id, __func__, low, high);
+ 
+-	cl_high = clamp_val(high, -40000, 120000);
+-	cl_low  = clamp_val(low, -40000, 120000);
++	cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
++	cl_low  = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
+ 
+ 	high_val = tsens_mC_to_hw(s, cl_high);
+ 	low_val  = tsens_mC_to_hw(s, cl_low);
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -499,6 +499,8 @@ enum regfield_ids {
+  *              with SROT only being available to secure boot firmware?
+  * @has_watchdog: does this IP support watchdog functionality?
+  * @max_sensors: maximum sensors supported by this version of the IP
++ * @trip_min_temp: minimum trip temperature supported by this version of the IP
++ * @trip_max_temp: maximum trip temperature supported by this version of the IP
+  */
+ struct tsens_features {
+ 	unsigned int ver_major;
+@@ -508,6 +510,8 @@ struct tsens_features {
+ 	unsigned int srot_split:1;
+ 	unsigned int has_watchdog:1;
+ 	unsigned int max_sensors;
++	int trip_min_temp;
++	int trip_max_temp;
+ };
+ 
+ /**

target/linux/ipq807x/patches-6.1/0044-v6.2-thermal-drivers-tsens-Add-IPQ8074-support.patch

@@ -0,0 +1,74 @@
+From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:44 +0200
+Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
+
+Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
+it only has one IRQ, that is used for up/low as well as critical.
+It also does not support negative trip temperatures.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
+ drivers/thermal/qcom/tsens.c    |  3 +++
+ drivers/thermal/qcom/tsens.h    |  2 +-
+ 3 files changed, 21 insertions(+), 1 deletion(-)
+
+--- a/drivers/thermal/qcom/tsens-v2.c
++++ b/drivers/thermal/qcom/tsens-v2.c
+@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
+ 	.trip_max_temp	= 120000,
+ };
+ 
++static struct tsens_features ipq8074_feat = {
++	.ver_major	= VER_2_X,
++	.crit_int	= 1,
++	.combo_int	= 1,
++	.adc		= 0,
++	.srot_split	= 1,
++	.max_sensors	= 16,
++	.trip_min_temp	= 0,
++	.trip_max_temp	= 204000,
++};
++
+ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
+ 	/* ----- SROT ------ */
+ 	/* VERSION */
+@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
+ 	.fields	= tsens_v2_regfields,
+ };
+ 
++struct tsens_plat_data data_ipq8074 = {
++	.ops		= &ops_generic_v2,
++	.feat		= &ipq8074_feat,
++	.fields	= tsens_v2_regfields,
++};
++
+ /* Kept around for backward compatibility with old msm8996.dtsi */
+ struct tsens_plat_data data_8996 = {
+ 	.num_sensors	= 13,
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
+ 		.compatible = "qcom,ipq8064-tsens",
+ 		.data = &data_8960,
+ 	}, {
++		.compatible = "qcom,ipq8074-tsens",
++		.data = &data_ipq8074,
++	}, {
+ 		.compatible = "qcom,mdm9607-tsens",
+ 		.data = &data_9607,
+ 	}, {
+--- a/drivers/thermal/qcom/tsens.h
++++ b/drivers/thermal/qcom/tsens.h
+@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
+ extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
+ 
+ /* TSENS v2 targets */
+-extern struct tsens_plat_data data_8996, data_tsens_v2;
++extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
+ 
+ #endif /* __QCOM_TSENS_H__ */

target/linux/ipq807x/patches-6.1/0045-v6.2-arm64-dts-qcom-ipq8074-add-thermal-nodes.patch

@@ -0,0 +1,130 @@
+From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:02:45 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
+
+IPQ8074 has a tsens v2.3.0 peripheral which monitors
+temperatures around the various subsystems on the
+die.
+
+So lets add the tsens and thermal zone nodes, passive
+CPU cooling will come in later patches after CPU frequency
+scaling is supported.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -274,6 +274,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		tsens: thermal-sensor@4a9000 {
++			compatible = "qcom,ipq8074-tsens";
++			reg = <0x4a9000 0x1000>, /* TM */
++			      <0x4a8000 0x1000>; /* SROT */
++			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "combined";
++			#qcom,sensors = <16>;
++			#thermal-sensor-cells = <1>;
++		};
++
+ 		cryptobam: dma-controller@704000 {
+ 			compatible = "qcom,bam-v1.7.0";
+ 			reg = <0x00704000 0x20000>;
+@@ -874,4 +884,90 @@
+ 			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ 			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ 	};
++
++	thermal-zones {
++		nss-top-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 4>;
++		};
++
++		nss0-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 5>;
++		};
++
++		nss1-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 6>;
++		};
++
++		wcss-phya0-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 7>;
++		};
++
++		wcss-phya1-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 8>;
++		};
++
++		cpu0_thermal: cpu0-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 9>;
++		};
++
++		cpu1_thermal: cpu1-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 10>;
++		};
++
++		cpu2_thermal: cpu2-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 11>;
++		};
++
++		cpu3_thermal: cpu3-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 12>;
++		};
++
++		cluster_thermal: cluster-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 13>;
++		};
++
++		wcss-phyb0-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 14>;
++		};
++
++		wcss-phyb1-thermal {
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
++
++			thermal-sensors = <&tsens 15>;
++		};
++	};
+ };

target/linux/ipq807x/patches-6.1/0046-v6.2-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch

@@ -0,0 +1,29 @@
+From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:08:49 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
+
+APCS now has support for providing the APSS clocks as the child device
+for IPQ8074.
+
+So, add the A53 PLL and XO clocks in order to use APCS as the CPU
+clocksource for APSS scaling.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -680,6 +680,8 @@
+ 		apcs_glb: mailbox@b111000 {
+ 			compatible = "qcom,ipq8074-apcs-apps-global";
+ 			reg = <0x0b111000 0x1000>;
++			clocks = <&a53pll>, <&xo>;
++			clock-names = "pll", "xo";
+ 
+ 			#clock-cells = <1>;
+ 			#mbox-cells = <1>;

target/linux/ipq807x/patches-6.1/0049-v6.2-clk-qcom-reset-support-resetting-multiple-bits.patch

@@ -0,0 +1,59 @@
+From 813ba3e427671ba3ff35c825087b03f0ad91cf02 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 14:28:59 +0100
+Subject: [PATCH] clk: qcom: reset: support resetting multiple bits
+
+This patch adds the support for giving the complete bitmask
+in reset structure and reset operation will use this bitmask
+for all reset operations.
+
+Currently, reset structure only takes a single bit for each reset
+and then calculates the bitmask by using the BIT() macro.
+
+However, this is not sufficient anymore for newer SoC-s like IPQ8074,
+IPQ6018 and more, since their networking resets require multiple bits
+to be asserted in order to properly reset the HW block completely.
+
+So, in order to allow asserting multiple bits add "bitmask" field to
+qcom_reset_map, and then use that bitmask value if its populated in the
+driver, if its not populated, then we just default to existing behaviour
+and calculate the bitmask on the fly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107132901.489240-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/reset.c | 4 ++--
+ drivers/clk/qcom/reset.h | 1 +
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/reset.c
++++ b/drivers/clk/qcom/reset.c
+@@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controlle
+ 
+ 	rst = to_qcom_reset_controller(rcdev);
+ 	map = &rst->reset_map[id];
+-	mask = BIT(map->bit);
++	mask = map->bitmask ? map->bitmask : BIT(map->bit);
+ 
+ 	return regmap_update_bits(rst->regmap, map->reg, mask, mask);
+ }
+@@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_control
+ 
+ 	rst = to_qcom_reset_controller(rcdev);
+ 	map = &rst->reset_map[id];
+-	mask = BIT(map->bit);
++	mask = map->bitmask ? map->bitmask : BIT(map->bit);
+ 
+ 	return regmap_update_bits(rst->regmap, map->reg, mask, 0);
+ }
+--- a/drivers/clk/qcom/reset.h
++++ b/drivers/clk/qcom/reset.h
+@@ -12,6 +12,7 @@ struct qcom_reset_map {
+ 	unsigned int reg;
+ 	u8 bit;
+ 	u8 udelay;
++	u32 bitmask;
+ };
+ 
+ struct regmap;

target/linux/ipq807x/patches-6.1/0050-v6.2-dt-bindings-clock-qcom-ipq8074-add-missing-networkin.patch

@@ -0,0 +1,39 @@
+From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 14:29:00 +0100
+Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
+ resets
+
+Add bindings for the missing networking resets found in IPQ8074 GCC.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
+---
+ include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+@@ -367,6 +367,20 @@
+ #define GCC_PCIE1_AHB_ARES			129
+ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
+ #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131
++#define GCC_PPE_FULL_RESET			132
++#define GCC_UNIPHY0_SOFT_RESET			133
++#define GCC_UNIPHY0_XPCS_RESET			134
++#define GCC_UNIPHY1_SOFT_RESET			135
++#define GCC_UNIPHY1_XPCS_RESET			136
++#define GCC_UNIPHY2_SOFT_RESET			137
++#define GCC_UNIPHY2_XPCS_RESET			138
++#define GCC_EDMA_HW_RESET			139
++#define GCC_NSSPORT1_RESET			140
++#define GCC_NSSPORT2_RESET			141
++#define GCC_NSSPORT3_RESET			142
++#define GCC_NSSPORT4_RESET			143
++#define GCC_NSSPORT5_RESET			144
++#define GCC_NSSPORT6_RESET			145
+ 
+ #define USB0_GDSC				0
+ #define USB1_GDSC				1

target/linux/ipq807x/patches-6.1/0051-v6.2-clk-qcom-ipq8074-add-missing-networking-resets.patch

@@ -0,0 +1,41 @@
+From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 14:29:01 +0100
+Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
+
+Downstream QCA 5.4 kernel defines networking resets which are not present
+in the mainline kernel but are required for the networking drivers.
+
+So, port the downstream resets and avoid using magic values for mask,
+construct mask for resets which require multiple bits to be set/cleared.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -4671,6 +4671,20 @@ static const struct qcom_reset_map gcc_i
+ 	[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
+ 	[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
+ 	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
++	[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
++	[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
++	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
++	[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
++	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
++	[GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
++	[GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
++	[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
++	[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
++	[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
++	[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
++	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
++	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
++	[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
+ };
+ 
+ static struct gdsc *gcc_ipq8074_gdscs[] = {

target/linux/ipq807x/patches-6.1/0052-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch

@@ -0,0 +1,152 @@
+From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:46:55 +0100
+Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
+
+It appears that having only .name populated in parent_data for clocks
+which are only globally searchable currently will not work as the clk core
+won't copy that name if there is no .fw_name present as well.
+
+So, populate .fw_name for all parent clocks in parent_data.
+
+Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
+
+Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
+ 1 file changed, 26 insertions(+), 26 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
+ };
+ 
+ static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
+-	{ .name = "pcie20_phy0_pipe_clk" },
++	{ .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
+ 	{ .fw_name = "xo", .name = "xo" },
+ };
+ 
+@@ -733,7 +733,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
+ };
+ 
+ static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
+-	{ .name = "pcie20_phy1_pipe_clk" },
++	{ .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
+ 	{ .fw_name = "xo", .name = "xo" },
+ };
+ 
+@@ -1137,7 +1137,7 @@ static const struct freq_tbl ftbl_nss_no
+ 
+ static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "bias_pll_nss_noc_clk" },
++	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
+ 	{ .hw = &gpll0.clkr.hw },
+ 	{ .hw = &gpll2.clkr.hw },
+ };
+@@ -1362,7 +1362,7 @@ static const struct freq_tbl ftbl_nss_pp
+ 
+ static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ 	{ .hw = &gpll0.clkr.hw },
+ 	{ .hw = &gpll4.clkr.hw },
+ 	{ .hw = &nss_crypto_pll.clkr.hw },
+@@ -1413,10 +1413,10 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "uniphy0_gcc_rx_clk" },
+-	{ .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+@@ -1465,10 +1465,10 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "uniphy0_gcc_tx_clk" },
+-	{ .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+@@ -1696,12 +1696,12 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "uniphy0_gcc_rx_clk" },
+-	{ .name = "uniphy0_gcc_tx_clk" },
+-	{ .name = "uniphy1_gcc_rx_clk" },
+-	{ .name = "uniphy1_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
++	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map
+@@ -1758,12 +1758,12 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "uniphy0_gcc_tx_clk" },
+-	{ .name = "uniphy0_gcc_rx_clk" },
+-	{ .name = "uniphy1_gcc_tx_clk" },
+-	{ .name = "uniphy1_gcc_rx_clk" },
++	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
++	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map
+@@ -1820,10 +1820,10 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "uniphy2_gcc_rx_clk" },
+-	{ .name = "uniphy2_gcc_tx_clk" },
++	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
++	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
+@@ -1877,10 +1877,10 @@ static const struct freq_tbl ftbl_nss_po
+ 
+ static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
+ 	{ .fw_name = "xo", .name = "xo" },
+-	{ .name = "uniphy2_gcc_tx_clk" },
+-	{ .name = "uniphy2_gcc_rx_clk" },
++	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
++	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
+ 	{ .hw = &ubi32_pll.clkr.hw },
+-	{ .name = "bias_pll_cc_clk" },
++	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+ 
+ static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {

target/linux/ipq807x/patches-6.1/0053-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch

@@ -0,0 +1,36 @@
+From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 30 Oct 2022 18:57:03 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
+
+Pass XO and sleep clocks to the GCC controller so it does not have to
+find them by matching globaly by name.
+
+If not passed directly, driver maintains backwards compatibility by then
+falling back to global lookup.
+
+Since we are here, set cell numbers in decimal instead of hex.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -361,9 +361,11 @@
+ 		gcc: gcc@1800000 {
+ 			compatible = "qcom,gcc-ipq8074";
+ 			reg = <0x01800000 0x80000>;
+-			#clock-cells = <0x1>;
++			clocks = <&xo>, <&sleep_clk>;
++			clock-names = "xo", "sleep_clk";
++			#clock-cells = <1>;
+ 			#power-domain-cells = <1>;
+-			#reset-cells = <0x1>;
++			#reset-cells = <1>;
+ 		};
+ 
+ 		tcsr_mutex: hwlock@1905000 {

target/linux/ipq807x/patches-6.1/0066-v6.2-arm64-dts-qcom-add-PMP8074-DTSI.patch

@@ -0,0 +1,149 @@
+From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:18:14 +0200
+Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
+
+PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
+controlled via SPMI.
+
+Add DTSI for it providing GPIO, regulator, RTC and VADC support.
+
+RTC is disabled by default as there is no built-in battery so it will
+loose time unless board vendor added a battery, so make it optional.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
+ 1 file changed, 125 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
+@@ -0,0 +1,125 @@
++// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
++
++#include <dt-bindings/spmi/spmi.h>
++#include <dt-bindings/iio/qcom,spmi-vadc.h>
++
++&spmi_bus {
++	pmic@0 {
++		compatible = "qcom,pmp8074", "qcom,spmi-pmic";
++		reg = <0x0 SPMI_USID>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		pmp8074_adc: adc@3100 {
++			compatible = "qcom,spmi-adc-rev2";
++			reg = <0x3100>;
++			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			#io-channel-cells = <1>;
++
++			ref-gnd@0 {
++				reg = <ADC5_REF_GND>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			vref-1p25@1 {
++				reg = <ADC5_1P25VREF>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			vref-vadc@2 {
++				reg = <ADC5_VREF_VADC>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			pmic_die: die-temp@6 {
++				reg = <ADC5_DIE_TEMP>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			xo_therm: xo-temp@76 {
++				reg = <ADC5_XO_THERM_100K_PU>;
++				qcom,ratiometric;
++				qcom,hw-settle-time = <200>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			pa_therm1: thermistor1@77 {
++				reg = <ADC5_AMUX_THM1_100K_PU>;
++				qcom,ratiometric;
++				qcom,hw-settle-time = <200>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			pa_therm2: thermistor2@78 {
++				reg = <ADC5_AMUX_THM2_100K_PU>;
++				qcom,ratiometric;
++				qcom,hw-settle-time = <200>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			pa_therm3: thermistor3@79 {
++				reg = <ADC5_AMUX_THM3_100K_PU>;
++				qcom,ratiometric;
++				qcom,hw-settle-time = <200>;
++				qcom,pre-scaling = <1 1>;
++			};
++
++			vph-pwr@131 {
++				reg = <ADC5_VPH_PWR>;
++				qcom,pre-scaling = <1 3>;
++			};
++		};
++
++		pmp8074_rtc: rtc@6000 {
++			compatible = "qcom,pm8941-rtc";
++			reg = <0x6000>;
++			reg-names = "rtc", "alarm";
++			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
++			allow-set-time;
++			status = "disabled";
++		};
++
++		pmp8074_gpios: gpio@c000 {
++			compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
++			reg = <0xc000>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			gpio-ranges = <&pmp8074_gpios 0 0 12>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++	};
++
++	pmic@1 {
++		compatible = "qcom,pmp8074", "qcom,spmi-pmic";
++		reg = <0x1 SPMI_USID>;
++
++		regulators {
++			compatible = "qcom,pmp8074-regulators";
++
++			s3: s3 {
++				regulator-name = "vdd_s3";
++				regulator-min-microvolt = <592000>;
++				regulator-max-microvolt = <1064000>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			s4: s4 {
++				regulator-name = "vdd_s4";
++				regulator-min-microvolt = <712000>;
++				regulator-max-microvolt = <992000>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++
++			l11: l11 {
++				regulator-name = "l11";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++			};
++		};
++	};
++};

target/linux/ipq807x/patches-6.1/0067-v6.2-arm64-dts-qcom-ipq8074-hk01-add-VQMMC-supply.patch

@@ -0,0 +1,37 @@
+From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 19 Aug 2022 00:18:15 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
+
+Since now we have control over the PMP8074 PMIC providing various system
+voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
+the SDHCI VQMMC supply.
+
+This allows SDHCI controller to switch to 1.8V I/O mode and support high
+speed modes like HS200 and HS400.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+@@ -3,6 +3,7 @@
+ /* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+  */
+ #include "ipq8074.dtsi"
++#include "pmp8074.dtsi"
+ 
+ / {
+ 	model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+@@ -84,6 +85,7 @@
+ 
+ &sdhc_1 {
+ 	status = "okay";
++	vqmmc-supply = <&l11>;
+ };
+ 
+ &qusb_phy_0 {

target/linux/ipq807x/patches-6.1/0068-v6.2-arm64-dts-qcom-hk01-use-GPIO-flags-for-tlmm.patch

@@ -0,0 +1,42 @@
+From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 7 Nov 2022 10:29:30 +0100
+Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
+
+Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
+harcoding the cell value.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
+---
+ arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+@@ -4,6 +4,7 @@
+  */
+ #include "ipq8074.dtsi"
+ #include "pmp8074.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
+@@ -52,12 +53,12 @@
+ 
+ &pcie0 {
+ 	status = "okay";
+-	perst-gpios = <&tlmm 61 0x1>;
++	perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ };
+ 
+ &pcie1 {
+ 	status = "okay";
+-	perst-gpios = <&tlmm 58 0x1>;
++	perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+ 
+ &pcie_qmp0 {

target/linux/ipq807x/patches-6.1/0069-v6.2-arm64-dts-qcom-ipq8074-Fix-up-comments.patch

@@ -0,0 +1,82 @@
+From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
+From: Konrad Dybcio <konrad.dybcio@linaro.org>
+Date: Mon, 7 Nov 2022 15:55:17 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
+
+Make sure all multiline C-style commends begin with just '/*' with
+the comment text starting on a new line.
+
+Also, fix up some whitespace within comments.
+
+Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074-hk01.dts    |  3 ++-
+ arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts |  3 ++-
+ arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts |  3 ++-
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi        | 12 ++++++------
+ 4 files changed, 12 insertions(+), 9 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /dts-v1/;
+-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
++/*
++ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+  */
+ #include "ipq8074.dtsi"
+ #include "pmp8074.dtsi"
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
++/*
++ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+  */
+ /dts-v1/;
+ 
+--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /dts-v1/;
+-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
++/*
++ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+  */
+ #include "ipq8074-hk10.dtsi"
+ 
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -129,10 +129,10 @@
+ 			status = "disabled";
+ 
+ 			usb1_ssphy: phy@58200 {
+-				reg = <0x00058200 0x130>,       /* Tx */
++				reg = <0x00058200 0x130>,     /* Tx */
+ 				      <0x00058400 0x200>,     /* Rx */
+-				      <0x00058800 0x1f8>,     /* PCS  */
+-				      <0x00058600 0x044>;     /* PCS misc*/
++				      <0x00058800 0x1f8>,     /* PCS */
++				      <0x00058600 0x044>;     /* PCS misc */
+ 				#phy-cells = <0>;
+ 				#clock-cells = <0>;
+ 				clocks = <&gcc GCC_USB1_PIPE_CLK>;
+@@ -172,10 +172,10 @@
+ 			status = "disabled";
+ 
+ 			usb0_ssphy: phy@78200 {
+-				reg = <0x00078200 0x130>,       /* Tx */
++				reg = <0x00078200 0x130>,     /* Tx */
+ 				      <0x00078400 0x200>,     /* Rx */
+-				      <0x00078800 0x1f8>,     /* PCS  */
+-				      <0x00078600 0x044>;     /* PCS misc*/
++				      <0x00078800 0x1f8>,     /* PCS */
++				      <0x00078600 0x044>;     /* PCS misc */
+ 				#phy-cells = <0>;
+ 				#clock-cells = <0>;
+ 				clocks = <&gcc GCC_USB0_PIPE_CLK>;

target/linux/ipq807x/patches-6.1/0070-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch

@@ -0,0 +1,60 @@
+From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Tue, 8 Nov 2022 15:23:57 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
+ DT schema
+
+DT schema expects TLMM pin configuration nodes to be named with
+'-state' suffix and their optional children with '-pins' suffix.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -318,35 +318,35 @@
+ 			interrupt-controller;
+ 			#interrupt-cells = <0x2>;
+ 
+-			serial_4_pins: serial4-pinmux {
++			serial_4_pins: serial4-state {
+ 				pins = "gpio23", "gpio24";
+ 				function = "blsp4_uart1";
+ 				drive-strength = <8>;
+ 				bias-disable;
+ 			};
+ 
+-			i2c_0_pins: i2c-0-pinmux {
++			i2c_0_pins: i2c-0-state {
+ 				pins = "gpio42", "gpio43";
+ 				function = "blsp1_i2c";
+ 				drive-strength = <8>;
+ 				bias-disable;
+ 			};
+ 
+-			spi_0_pins: spi-0-pins {
++			spi_0_pins: spi-0-state {
+ 				pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ 				function = "blsp0_spi";
+ 				drive-strength = <8>;
+ 				bias-disable;
+ 			};
+ 
+-			hsuart_pins: hsuart-pins {
++			hsuart_pins: hsuart-state {
+ 				pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ 				function = "blsp2_uart";
+ 				drive-strength = <8>;
+ 				bias-disable;
+ 			};
+ 
+-			qpic_pins: qpic-pins {
++			qpic_pins: qpic-state {
+ 				pins = "gpio1", "gpio3", "gpio4",
+ 				       "gpio5", "gpio6", "gpio7",
+ 				       "gpio8", "gpio10", "gpio11",

target/linux/ipq807x/patches-6.1/0079-v6.2-dt-bindings-arm-qcom-document-qcom-msm-id-and-qcom-b.patch

@@ -0,0 +1,207 @@
+From 77faa07c185c969e742cbb3e6aa487a11b0b616c Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Tue, 30 Aug 2022 09:57:42 +0300
+Subject: [PATCH] dt-bindings: arm: qcom: document qcom,msm-id and
+ qcom,board-id
+
+The top level qcom,msm-id and qcom,board-id properties are utilized by
+bootloaders on Qualcomm MSM platforms to determine which device tree
+should be used and passed to the kernel.
+
+The commit b32e592d3c28 ("devicetree: bindings: Document qcom board
+compatible format") from 2015 was a consensus during discussion about
+upstreaming qcom,msm-id and qcom,board-id fields.  There are however still
+problems with that consensus:
+1. It was reached 7 years ago but it turned out its implementation did
+   not reach all possible products.
+
+2. Initially additional tool (dtbTool) was needed for parsing these
+   fields to create a QCDT image consisting of multiple DTBs, later the
+   bootloaders were improved and they use these qcom,msm-id and
+   qcom,board-id properties directly.
+
+3. Extracting relevant information from the board compatible requires
+   this additional tool (dtbTool), which makes the build process more
+   complicated and not easily reproducible (DTBs are modified after the
+   kernel build).
+
+4. Some versions of Qualcomm bootloaders expect these properties even
+   when booting with a single DTB.  The community is stuck with these
+   bootloaders thus they require properties in the DTBs.
+
+Since several upstreamed Qualcomm SoC-based boards require these
+properties to properly boot and the properties are reportedly used by
+bootloaders, document them along with the bindings header with constants
+used by: bootloader, some DTS and socinfo driver.
+
+Link: https://lore.kernel.org/r/a3c932d1-a102-ce18-deea-18cbbd05ecab@linaro.org/
+Co-developed-by: Kumar Gala <galak@codeaurora.org>
+Signed-off-by: Kumar Gala <galak@codeaurora.org>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20220830065744.161163-2-krzysztof.kozlowski@linaro.org
+---
+ include/dt-bindings/arm/qcom,ids.h | 155 +++++++++++++++++++++++++++++
+ 1 file changed, 155 insertions(+)
+ create mode 100644 include/dt-bindings/arm/qcom,ids.h
+
+--- /dev/null
++++ b/include/dt-bindings/arm/qcom,ids.h
+@@ -0,0 +1,155 @@
++/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
++/*
++ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
++ * Copyright (c) 2022 Linaro Ltd
++ * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala.
++ */
++#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H
++#define _DT_BINDINGS_ARM_QCOM_IDS_H
++
++/*
++ * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for
++ * older chipsets (qcom,msm-id) and in socinfo driver:
++ */
++#define QCOM_ID_MSM8960			87
++#define QCOM_ID_APQ8064			109
++#define QCOM_ID_MSM8660A		122
++#define QCOM_ID_MSM8260A		123
++#define QCOM_ID_APQ8060A		124
++#define QCOM_ID_MSM8974			126
++#define QCOM_ID_MPQ8064			130
++#define QCOM_ID_MSM8960AB		138
++#define QCOM_ID_APQ8060AB		139
++#define QCOM_ID_MSM8260AB		140
++#define QCOM_ID_MSM8660AB		141
++#define QCOM_ID_MSM8626			145
++#define QCOM_ID_MSM8610			147
++#define QCOM_ID_APQ8064AB		153
++#define QCOM_ID_MSM8226			158
++#define QCOM_ID_MSM8526			159
++#define QCOM_ID_MSM8110			161
++#define QCOM_ID_MSM8210			162
++#define QCOM_ID_MSM8810			163
++#define QCOM_ID_MSM8212			164
++#define QCOM_ID_MSM8612			165
++#define QCOM_ID_MSM8112			166
++#define QCOM_ID_MSM8225Q		168
++#define QCOM_ID_MSM8625Q		169
++#define QCOM_ID_MSM8125Q		170
++#define QCOM_ID_APQ8064AA		172
++#define QCOM_ID_APQ8084			178
++#define QCOM_ID_APQ8074			184
++#define QCOM_ID_MSM8274			185
++#define QCOM_ID_MSM8674			186
++#define QCOM_ID_MSM8974PRO_AC		194
++#define QCOM_ID_MSM8126			198
++#define QCOM_ID_APQ8026			199
++#define QCOM_ID_MSM8926			200
++#define QCOM_ID_MSM8326			205
++#define QCOM_ID_MSM8916			206
++#define QCOM_ID_MSM8994			207
++#define QCOM_ID_APQ8074PRO_AA		208
++#define QCOM_ID_APQ8074PRO_AB		209
++#define QCOM_ID_APQ8074PRO_AC		210
++#define QCOM_ID_MSM8274PRO_AA		211
++#define QCOM_ID_MSM8274PRO_AB		212
++#define QCOM_ID_MSM8274PRO_AC		213
++#define QCOM_ID_MSM8674PRO_AA		214
++#define QCOM_ID_MSM8674PRO_AB		215
++#define QCOM_ID_MSM8674PRO_AC		216
++#define QCOM_ID_MSM8974PRO_AA		217
++#define QCOM_ID_MSM8974PRO_AB		218
++#define QCOM_ID_APQ8028			219
++#define QCOM_ID_MSM8128			220
++#define QCOM_ID_MSM8228			221
++#define QCOM_ID_MSM8528			222
++#define QCOM_ID_MSM8628			223
++#define QCOM_ID_MSM8928			224
++#define QCOM_ID_MSM8510			225
++#define QCOM_ID_MSM8512			226
++#define QCOM_ID_MSM8936			233
++#define QCOM_ID_MSM8939			239
++#define QCOM_ID_APQ8036			240
++#define QCOM_ID_APQ8039			241
++#define QCOM_ID_MSM8996			246
++#define QCOM_ID_APQ8016			247
++#define QCOM_ID_MSM8216			248
++#define QCOM_ID_MSM8116			249
++#define QCOM_ID_MSM8616			250
++#define QCOM_ID_MSM8992			251
++#define QCOM_ID_APQ8094			253
++#define QCOM_ID_MDM9607			290
++#define QCOM_ID_APQ8096			291
++#define QCOM_ID_MSM8998			292
++#define QCOM_ID_MSM8953			293
++#define QCOM_ID_MDM8207			296
++#define QCOM_ID_MDM9207			297
++#define QCOM_ID_MDM9307			298
++#define QCOM_ID_MDM9628			299
++#define QCOM_ID_APQ8053			304
++#define QCOM_ID_MSM8996SG		305
++#define QCOM_ID_MSM8996AU		310
++#define QCOM_ID_APQ8096AU		311
++#define QCOM_ID_APQ8096SG		312
++#define QCOM_ID_SDM660			317
++#define QCOM_ID_SDM630			318
++#define QCOM_ID_APQ8098			319
++#define QCOM_ID_SDM845			321
++#define QCOM_ID_MDM9206			322
++#define QCOM_ID_IPQ8074			323
++#define QCOM_ID_SDA660			324
++#define QCOM_ID_SDM658			325
++#define QCOM_ID_SDA658			326
++#define QCOM_ID_SDA630			327
++#define QCOM_ID_SDM450			338
++#define QCOM_ID_SDA845			341
++#define QCOM_ID_IPQ8072			342
++#define QCOM_ID_IPQ8076			343
++#define QCOM_ID_IPQ8078			344
++#define QCOM_ID_SDM636			345
++#define QCOM_ID_SDA636			346
++#define QCOM_ID_SDM632			349
++#define QCOM_ID_SDA632			350
++#define QCOM_ID_SDA450			351
++#define QCOM_ID_SM8250			356
++#define QCOM_ID_IPQ8070			375
++#define QCOM_ID_IPQ8071			376
++#define QCOM_ID_IPQ8072A		389
++#define QCOM_ID_IPQ8074A		390
++#define QCOM_ID_IPQ8076A		391
++#define QCOM_ID_IPQ8078A		392
++#define QCOM_ID_SM6125			394
++#define QCOM_ID_IPQ8070A		395
++#define QCOM_ID_IPQ8071A		396
++#define QCOM_ID_IPQ6018			402
++#define QCOM_ID_IPQ6028			403
++#define QCOM_ID_IPQ6000			421
++#define QCOM_ID_IPQ6010			422
++#define QCOM_ID_SC7180			425
++#define QCOM_ID_SM6350			434
++#define QCOM_ID_SM8350			439
++#define QCOM_ID_SC8280XP		449
++#define QCOM_ID_IPQ6005			453
++#define QCOM_ID_QRB5165			455
++#define QCOM_ID_SM8450			457
++#define QCOM_ID_SM7225			459
++#define QCOM_ID_SA8295P			460
++#define QCOM_ID_SA8540P			461
++#define QCOM_ID_SM8450_2		480
++#define QCOM_ID_SM8450_3		482
++#define QCOM_ID_SC7280			487
++#define QCOM_ID_SC7180P			495
++#define QCOM_ID_SM6375			507
++
++/*
++ * The board type and revision information, used by Qualcomm bootloaders and
++ * DTS for older chipsets (qcom,board-id):
++ */
++#define QCOM_BOARD_ID(a, major, minor) \
++	(((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BOARD_ID_##a)
++
++#define QCOM_BOARD_ID_MTP			8
++#define QCOM_BOARD_ID_DRAGONBOARD		10
++#define QCOM_BOARD_ID_SBC			24
++
++#endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */

target/linux/ipq807x/patches-6.1/0080-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch

@@ -0,0 +1,24 @@
+From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:48:36 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
+
+Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
+generation limit.
+This allows the generic DWC code to configure the link speed correctly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -766,6 +766,7 @@
+ 			linux,pci-domain = <1>;
+ 			bus-range = <0x00 0xff>;
+ 			num-lanes = <1>;
++			max-link-speed = <2>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 

target/linux/ipq807x/patches-6.1/0081-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch

@@ -0,0 +1,26 @@
+From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 13 Jan 2023 17:44:47 +0100
+Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
+
+IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
+Add compatible for Gen3 port which uses the same controller as IPQ6018.
+
+Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -1745,6 +1745,7 @@ static const struct of_device_id qcom_pc
+ 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
+ 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
+ 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
++	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
+ 	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
+ 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
+ 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },

target/linux/ipq807x/patches-6.1/0082-v6.3-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch

@@ -0,0 +1,38 @@
+From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 8 Jan 2023 13:36:28 +0100
+Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
+
+Having only .name populated in parent_data for clocks which are only
+globally searchable currently will not work as the clk core won't copy
+that name if there is no .fw_name present as well.
+
+So, populate .fw_name for usb3phy clocks in parent_data as they were
+missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
+
+Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+ };
+ 
+ static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+-	{ .name = "usb3phy_0_cc_pipe_clk" },
++	{ .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
+ 	{ .fw_name = "xo", .name = "xo" },
+ };
+ 
+@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
+ };
+ 
+ static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+-	{ .name = "usb3phy_1_cc_pipe_clk" },
++	{ .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
+ 	{ .fw_name = "xo", .name = "xo" },
+ };
+ 

target/linux/ipq807x/patches-6.1/0100-clk-qcom-clk-rcg2-introduce-support-for-multiple-con.patch

@@ -0,0 +1,203 @@
+From 032be4f49dda786fea9e1501212f6cd09a7ded96 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 3 Nov 2022 14:49:43 +0100
+Subject: [PATCH] clk: qcom: clk-rcg2: introduce support for multiple conf for
+ same freq
+
+Some RCG frequency can be reached by multiple configuration.
+
+We currently declare multiple configuration for the same frequency but
+that is not supported and always the first configuration will be taken.
+
+These multiple configuration are needed as based on the current parent
+configuration, it may be needed to use a different configuration to
+reach the same frequency.
+
+To handle this introduce 2 new macro, FM and C.
+
+- FM is used to declare an empty freq_tbl with just the frequency and an
+  array of confs to insert all the config for the provided frequency.
+
+- C is used to declare a fre_conf where src, pre_div, m and n are
+  provided.
+
+The driver is changed to handle this special freq_tbl and select the
+correct config by calculating the final rate and deciding based on the
+one that is less different than the requested one.
+
+Tested-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/clk-rcg.h  | 14 ++++++-
+ drivers/clk/qcom/clk-rcg2.c | 84 +++++++++++++++++++++++++++++++++----
+ 2 files changed, 88 insertions(+), 10 deletions(-)
+
+--- a/drivers/clk/qcom/clk-rcg.h
++++ b/drivers/clk/qcom/clk-rcg.h
+@@ -7,7 +7,17 @@
+ #include <linux/clk-provider.h>
+ #include "clk-regmap.h"
+ 
+-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
++#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n), 0, NULL }
++
++#define FM(_f, _confs) { .freq = (_f), .confs_num = ARRAY_SIZE(_confs), .confs = (_confs) }
++#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
++
++struct freq_conf {
++	u8 src;
++	u8 pre_div;
++	u16 m;
++	u16 n;
++};
+ 
+ struct freq_tbl {
+ 	unsigned long freq;
+@@ -15,6 +25,8 @@ struct freq_tbl {
+ 	u8 pre_div;
+ 	u16 m;
+ 	u16 n;
++	int confs_num;
++	const struct freq_conf *confs;
+ };
+ 
+ /**
+--- a/drivers/clk/qcom/clk-rcg2.c
++++ b/drivers/clk/qcom/clk-rcg2.c
+@@ -209,11 +209,60 @@ clk_rcg2_recalc_rate(struct clk_hw *hw,
+ 	return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
+ }
+ 
++static void
++clk_rcg2_select_conf(struct clk_hw *hw, struct freq_tbl *f_tbl,
++		     const struct freq_tbl *f, unsigned long req_rate)
++{
++	unsigned long best_rate = 0, parent_rate, rate;
++	const struct freq_conf *conf, *best_conf;
++	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
++	struct clk_hw *p;
++	int index, i;
++
++	/* Search in each provided config the one that is near the wanted rate */
++	for (i = 0, conf = f->confs; i < f->confs_num; i++, conf++) {
++		index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
++		if (index < 0)
++			continue;
++
++		p = clk_hw_get_parent_by_index(hw, index);
++		if (!p)
++			continue;
++
++		parent_rate =  clk_hw_get_rate(p);
++		rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
++
++		if (rate == req_rate) {
++			best_conf = conf;
++			break;
++		}
++
++		if (abs(req_rate - rate) < abs(best_rate - rate)) {
++			best_rate = rate;
++			best_conf = conf;
++		}
++	}
++
++	/*
++	 * Very unlikely.
++	 * Force the first conf if we can't find a correct config.
++	 */
++	if (unlikely(i == f->confs_num))
++		best_conf = f->confs;
++
++	/* Apply the config */
++	f_tbl->src = best_conf->src;
++	f_tbl->pre_div = best_conf->pre_div;
++	f_tbl->m = best_conf->m;
++	f_tbl->n = best_conf->n;
++}
++
+ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
+ 				    struct clk_rate_request *req,
+ 				    enum freq_policy policy)
+ {
+ 	unsigned long clk_flags, rate = req->rate;
++	struct freq_tbl f_tbl;
+ 	struct clk_hw *p;
+ 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+ 	int index;
+@@ -232,7 +281,15 @@ static int _freq_tbl_determine_rate(stru
+ 	if (!f)
+ 		return -EINVAL;
+ 
+-	index = qcom_find_src_index(hw, rcg->parent_map, f->src);
++	f_tbl = *f;
++	/*
++	 * A single freq may be reached by multiple configuration.
++	 * Try to find the bast one if we have this kind of freq_table.
++	 */
++	if (f->confs)
++		clk_rcg2_select_conf(hw, &f_tbl, f, rate);
++
++	index = qcom_find_src_index(hw, rcg->parent_map, f_tbl.src);
+ 	if (index < 0)
+ 		return index;
+ 
+@@ -242,18 +299,18 @@ static int _freq_tbl_determine_rate(stru
+ 		return -EINVAL;
+ 
+ 	if (clk_flags & CLK_SET_RATE_PARENT) {
+-		rate = f->freq;
+-		if (f->pre_div) {
++		rate = f_tbl.freq;
++		if (f_tbl.pre_div) {
+ 			if (!rate)
+ 				rate = req->rate;
+ 			rate /= 2;
+-			rate *= f->pre_div + 1;
++			rate *= f_tbl.pre_div + 1;
+ 		}
+ 
+-		if (f->n) {
++		if (f_tbl.n) {
+ 			u64 tmp = rate;
+-			tmp = tmp * f->n;
+-			do_div(tmp, f->m);
++			tmp = tmp * f_tbl.n;
++			do_div(tmp, f_tbl.m);
+ 			rate = tmp;
+ 		}
+ 	} else {
+@@ -261,7 +318,7 @@ static int _freq_tbl_determine_rate(stru
+ 	}
+ 	req->best_parent_hw = p;
+ 	req->best_parent_rate = rate;
+-	req->rate = f->freq;
++	req->rate = f_tbl.freq;
+ 
+ 	return 0;
+ }
+@@ -357,6 +414,7 @@ static int __clk_rcg2_set_rate(struct cl
+ {
+ 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+ 	const struct freq_tbl *f;
++	struct freq_tbl f_tbl;
+ 
+ 	switch (policy) {
+ 	case FLOOR:
+@@ -372,7 +430,15 @@ static int __clk_rcg2_set_rate(struct cl
+ 	if (!f)
+ 		return -EINVAL;
+ 
+-	return clk_rcg2_configure(rcg, f);
++	f_tbl = *f;
++	/*
++	 * A single freq may be reached by multiple configuration.
++	 * Try to find the best one if we have this kind of freq_table.
++	 */
++	if (f->confs)
++		clk_rcg2_select_conf(hw, &f_tbl, f, rate);
++
++	return clk_rcg2_configure(rcg, &f_tbl);
+ }
+ 
+ static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,

target/linux/ipq807x/patches-6.1/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch

@@ -0,0 +1,129 @@
+From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 3 Nov 2022 14:49:44 +0100
+Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
+ conf
+
+Rework nss_port5/6 to use the new multiple configuration implementation
+and correctly fix the clocks for these port under some corner case.
+
+This is particularly relevant for device that have 2.5G or 10G port
+connected to port5 or port 6 on ipq8074. As the parent are shared
+across multiple port it may be required to select the correct
+configuration to accomplish the desired clock. Without this patch such
+port doesn't work in some specific ethernet speed as the clock will be
+set to the wrong frequency as we just select the first configuration for
+the related frequency instead of selecting the best one.
+
+Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
+ 1 file changed, 48 insertions(+), 16 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -1682,13 +1682,21 @@ static struct clk_regmap_div nss_port4_t
+ 	},
+ };
+ 
++static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
++	C(P_UNIPHY1_RX, 12.5, 0, 0),
++	C(P_UNIPHY0_RX, 5, 0, 0),
++};
++
++static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
++	C(P_UNIPHY1_RX, 2.5, 0, 0),
++	C(P_UNIPHY0_RX, 1, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
+ 	F(19200000, P_XO, 1, 0, 0),
+-	F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
+-	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
++	FM(25000000, ftbl_nss_port5_rx_clk_src_25),
+ 	F(78125000, P_UNIPHY1_RX, 4, 0, 0),
+-	F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
+-	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
++	FM(125000000, ftbl_nss_port5_rx_clk_src_125),
+ 	F(156250000, P_UNIPHY1_RX, 2, 0, 0),
+ 	F(312500000, P_UNIPHY1_RX, 1, 0, 0),
+ 	{ }
+@@ -1744,13 +1752,21 @@ static struct clk_regmap_div nss_port5_r
+ 	},
+ };
+ 
++static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
++	C(P_UNIPHY1_TX, 12.5, 0, 0),
++	C(P_UNIPHY0_TX, 5, 0, 0),
++};
++
++static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
++	C(P_UNIPHY1_TX, 2.5, 0, 0),
++	C(P_UNIPHY0_TX, 1, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
+ 	F(19200000, P_XO, 1, 0, 0),
+-	F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
+-	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
++	FM(25000000, ftbl_nss_port5_tx_clk_src_25),
+ 	F(78125000, P_UNIPHY1_TX, 4, 0, 0),
+-	F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
+-	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
++	FM(125000000, ftbl_nss_port5_tx_clk_src_125),
+ 	F(156250000, P_UNIPHY1_TX, 2, 0, 0),
+ 	F(312500000, P_UNIPHY1_TX, 1, 0, 0),
+ 	{ }
+@@ -1806,13 +1822,21 @@ static struct clk_regmap_div nss_port5_t
+ 	},
+ };
+ 
++static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
++	C(P_UNIPHY2_RX, 5, 0, 0),
++	C(P_UNIPHY2_RX, 12.5, 0, 0),
++};
++
++static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
++	C(P_UNIPHY2_RX, 1, 0, 0),
++	C(P_UNIPHY2_RX, 2.5, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
+ 	F(19200000, P_XO, 1, 0, 0),
+-	F(25000000, P_UNIPHY2_RX, 5, 0, 0),
+-	F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
++	FM(25000000, ftbl_nss_port6_rx_clk_src_25),
+ 	F(78125000, P_UNIPHY2_RX, 4, 0, 0),
+-	F(125000000, P_UNIPHY2_RX, 1, 0, 0),
+-	F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
++	FM(125000000, ftbl_nss_port6_rx_clk_src_125),
+ 	F(156250000, P_UNIPHY2_RX, 2, 0, 0),
+ 	F(312500000, P_UNIPHY2_RX, 1, 0, 0),
+ 	{ }
+@@ -1863,13 +1887,21 @@ static struct clk_regmap_div nss_port6_r
+ 	},
+ };
+ 
++static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
++	C(P_UNIPHY2_TX, 5, 0, 0),
++	C(P_UNIPHY2_TX, 12.5, 0, 0),
++};
++
++static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
++	C(P_UNIPHY2_TX, 1, 0, 0),
++	C(P_UNIPHY2_TX, 2.5, 0, 0),
++};
++
+ static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
+ 	F(19200000, P_XO, 1, 0, 0),
+-	F(25000000, P_UNIPHY2_TX, 5, 0, 0),
+-	F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
++	FM(25000000, ftbl_nss_port6_tx_clk_src_25),
+ 	F(78125000, P_UNIPHY2_TX, 4, 0, 0),
+-	F(125000000, P_UNIPHY2_TX, 1, 0, 0),
+-	F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
++	FM(125000000, ftbl_nss_port6_tx_clk_src_125),
+ 	F(156250000, P_UNIPHY2_TX, 2, 0, 0),
+ 	F(312500000, P_UNIPHY2_TX, 1, 0, 0),
+ 	{ }

target/linux/ipq807x/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch

@@ -0,0 +1,70 @@
+From ad2d07f71739351eeea1d8a120c0918e2c4b265f Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 22 Dec 2021 12:23:34 +0100
+Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
+
+IPQ8074 has multiple reserved memory ranges, if they are not defined
+then weird things tend to happen, board hangs and resets when PCI or
+WLAN is used etc.
+
+So, to avoid all of that add the reserved memory nodes from the downstream
+5.4 kernel from QCA.
+This is their default layout meant for devices with 1GB of RAM, but
+devices with lower ammounts can override the Q6 node.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -85,6 +85,26 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		nss@40000000 {
++			no-map;
++			reg = <0x0 0x40000000 0x0 0x01000000>;
++		};
++
++		tzapp_region: tzapp@4a400000 {
++			no-map;
++			reg = <0x0 0x4a400000 0x0 0x00200000>;
++		};
++
++		uboot@4a600000 {
++			no-map;
++			reg = <0x0 0x4a600000 0x0 0x00400000>;
++		};
++
++		sbl@4aa00000 {
++			no-map;
++			reg = <0x0 0x4aa00000 0x0 0x00100000>;
++		};
++
+ 		smem@4ab00000 {
+ 			compatible = "qcom,smem";
+ 			reg = <0x0 0x4ab00000 0x0 0x00100000>;
+@@ -97,6 +117,21 @@
+ 			no-map;
+ 			reg = <0x0 0x4ac00000 0x0 0x00400000>;
+ 		};
++
++		q6_region: wcnss@4b000000 {
++			no-map;
++			reg = <0x0 0x4b000000 0x0 0x05f00000>;
++		};
++
++		q6_etr_region: q6_etr_dump@50f00000 {
++			no-map;
++			reg = <0x0 0x50f00000 0x0 0x00100000>;
++		};
++
++		m3_dump_region: m3_dump@51000000 {
++			no-map;
++			reg = <0x0 0x51000000 0x0 0x100000>;
++		};
+ 	};
+ 
+ 	firmware {

target/linux/ipq807x/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch

@@ -0,0 +1,30 @@
+From 8a576b5bc9f0555d1d970cacabcaa24a3b74fa57 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:15:01 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to
+ GCC
+
+Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
+find them by matching globaly by name.
+
+If not passed directly, driver maintains backwards compatibility by then
+falling back to global lookup.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -396,8 +396,8 @@
+ 		gcc: gcc@1800000 {
+ 			compatible = "qcom,gcc-ipq8074";
+ 			reg = <0x01800000 0x80000>;
+-			clocks = <&xo>, <&sleep_clk>;
+-			clock-names = "xo", "sleep_clk";
++			clocks = <&xo>, <&sleep_clk>, <&pcie_phy0>, <&pcie_phy1>;
++			clock-names = "xo", "sleep_clk", "pcie0_pipe", "pcie1_pipe";
+ 			#clock-cells = <1>;
+ 			#power-domain-cells = <1>;
+ 			#reset-cells = <1>;

target/linux/ipq807x/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch

@@ -0,0 +1,43 @@
+From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:26:25 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
+
+Instead of hardcoding the IRQ, simply use msi-parent instead.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -699,7 +699,7 @@
+ 			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+ 			ranges = <0 0xb00a000 0xffd>;
+ 
+-			v2m@0 {
++			gic_v2m0: v2m@0 {
+ 				compatible = "arm,gic-v2m-frame";
+ 				msi-controller;
+ 				reg = <0x0 0xffd>;
+@@ -811,8 +811,7 @@
+ 			ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
+ 				 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
+ 
+-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "msi";
++			msi-parent = <&gic_v2m0>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 0x7>;
+ 			interrupt-map = <0 0 0 1 &intc 0 142
+@@ -873,8 +872,7 @@
+ 			ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
+ 				 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
+ 
+-			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "msi";
++			msi-parent = <&gic_v2m0>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 0x7>;
+ 			interrupt-map = <0 0 0 1 &intc 0 75

target/linux/ipq807x/patches-6.1/0112-remoteproc-qcom-Add-PRNG-proxy-clock.patch

@@ -0,0 +1,155 @@
+From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:05 +0530
+Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
+
+PRNG clock is needed by the secure PIL, support for the same
+is added in subsequent patches.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
+ 1 file changed, 47 insertions(+), 18 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -91,19 +91,6 @@ enum {
+ 	WCSS_QCS404,
+ };
+ 
+-struct wcss_data {
+-	const char *firmware_name;
+-	unsigned int crash_reason_smem;
+-	u32 version;
+-	bool aon_reset_required;
+-	bool wcss_q6_reset_required;
+-	const char *ssr_name;
+-	const char *sysmon_name;
+-	int ssctl_id;
+-	const struct rproc_ops *ops;
+-	bool requires_force_stop;
+-};
+-
+ struct q6v5_wcss {
+ 	struct device *dev;
+ 
+@@ -128,6 +115,7 @@ struct q6v5_wcss {
+ 	struct clk *qdsp6ss_xo_cbcr;
+ 	struct clk *qdsp6ss_core_gfmux;
+ 	struct clk *lcc_bcr_sleep;
++	struct clk *prng_clk;
+ 	struct regulator *cx_supply;
+ 	struct qcom_sysmon *sysmon;
+ 
+@@ -151,6 +139,21 @@ struct q6v5_wcss {
+ 	struct qcom_rproc_ssr ssr_subdev;
+ };
+ 
++struct wcss_data {
++	int (*init_clock)(struct q6v5_wcss *wcss);
++	int (*init_regulator)(struct q6v5_wcss *wcss);
++	const char *firmware_name;
++	unsigned int crash_reason_smem;
++	u32 version;
++	bool aon_reset_required;
++	bool wcss_q6_reset_required;
++	const char *ssr_name;
++	const char *sysmon_name;
++	int ssctl_id;
++	const struct rproc_ops *ops;
++	bool requires_force_stop;
++};
++
+ static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
+ {
+ 	int ret;
+@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
+ 	struct q6v5_wcss *wcss = rproc->priv;
+ 	int ret;
+ 
++	ret = clk_prepare_enable(wcss->prng_clk);
++	if (ret) {
++		dev_err(wcss->dev, "prng clock enable failed\n");
++		return ret;
++	}
++
+ 	qcom_q6v5_prepare(&wcss->q6v5);
+ 
+ 	/* Release Q6 and WCSS reset */
+@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
+ 			return ret;
+ 	}
+ 
++	clk_disable_unprepare(wcss->prng_clk);
+ 	qcom_q6v5_unprepare(&wcss->q6v5);
+ 
+ 	return 0;
+@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
+ 	return 0;
+ }
+ 
+-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
++static int ipq8074_init_clock(struct q6v5_wcss *wcss)
++{
++	int ret;
++
++	wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
++	if (IS_ERR(wcss->prng_clk)) {
++		ret = PTR_ERR(wcss->prng_clk);
++		if (ret != -EPROBE_DEFER)
++			dev_err(wcss->dev, "Failed to get prng clock\n");
++		return ret;
++	}
++	return 0;
++}
++
++static int qcs404_init_clock(struct q6v5_wcss *wcss)
+ {
+ 	int ret;
+ 
+@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
+ 	return 0;
+ }
+ 
+-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
++static int qcs404_init_regulator(struct q6v5_wcss *wcss)
+ {
+ 	wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
+ 	if (IS_ERR(wcss->cx_supply))
+@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
+ 	if (ret)
+ 		goto free_rproc;
+ 
+-	if (wcss->version == WCSS_QCS404) {
+-		ret = q6v5_wcss_init_clock(wcss);
++	if (desc->init_clock) {
++		ret = desc->init_clock(wcss);
+ 		if (ret)
+ 			goto free_rproc;
++	}
+ 
+-		ret = q6v5_wcss_init_regulator(wcss);
++	if (desc->init_regulator) {
++		ret = desc->init_regulator(wcss);
+ 		if (ret)
+ 			goto free_rproc;
+ 	}
+@@ -1087,6 +1113,7 @@ static int q6v5_wcss_remove(struct platf
+ }
+ 
+ static const struct wcss_data wcss_ipq8074_res_init = {
++	.init_clock = ipq8074_init_clock,
+ 	.firmware_name = "IPQ8074/q6_fw.mdt",
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+ 	.aon_reset_required = true,
+@@ -1096,6 +1123,8 @@ static const struct wcss_data wcss_ipq80
+ };
+ 
+ static const struct wcss_data wcss_qcs404_res_init = {
++	.init_clock = qcs404_init_clock,
++	.init_regulator = qcs404_init_regulator,
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+ 	.firmware_name = "wcnss.mdt",
+ 	.version = WCSS_QCS404,

target/linux/ipq807x/patches-6.1/0113-remoteproc-qcom-Add-secure-PIL-support.patch

@@ -0,0 +1,143 @@
+From 7358d42dfbdfdb5d4f1d0d4c2e5c2bb4143a29b0 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:06 +0530
+Subject: [PATCH] remoteproc: qcom: Add secure PIL support
+
+IPQ8074 uses secure PIL. Hence, adding the support for the same.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
+ 1 file changed, 40 insertions(+), 3 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -18,6 +18,7 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/reset.h>
+ #include <linux/soc/qcom/mdt_loader.h>
++#include <linux/qcom_scm.h>
+ #include "qcom_common.h"
+ #include "qcom_pil_info.h"
+ #include "qcom_q6v5.h"
+@@ -86,6 +87,9 @@
+ #define TCSR_WCSS_CLK_ENABLE	0x14
+ 
+ #define MAX_HALT_REG		3
++
++#define WCNSS_PAS_ID		6
++
+ enum {
+ 	WCSS_IPQ8074,
+ 	WCSS_QCS404,
+@@ -134,6 +138,7 @@ struct q6v5_wcss {
+ 	unsigned int crash_reason_smem;
+ 	u32 version;
+ 	bool requires_force_stop;
++	bool need_mem_protection;
+ 
+ 	struct qcom_rproc_glink glink_subdev;
+ 	struct qcom_rproc_ssr ssr_subdev;
+@@ -152,6 +157,7 @@ struct wcss_data {
+ 	int ssctl_id;
+ 	const struct rproc_ops *ops;
+ 	bool requires_force_stop;
++	bool need_mem_protection;
+ };
+ 
+ static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
+@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
+ 
+ 	qcom_q6v5_prepare(&wcss->q6v5);
+ 
++	if (wcss->need_mem_protection) {
++		ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
++		if (ret) {
++			dev_err(wcss->dev, "wcss_reset failed\n");
++			return ret;
++		}
++		goto wait_for_reset;
++	}
++
+ 	/* Release Q6 and WCSS reset */
+ 	ret = reset_control_deassert(wcss->wcss_reset);
+ 	if (ret) {
+@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
+ 	if (ret)
+ 		goto wcss_q6_reset;
+ 
++wait_for_reset:
+ 	ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
+ 	if (ret == -ETIMEDOUT)
+ 		dev_err(wcss->dev, "start timed out\n");
+@@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
+ 	struct q6v5_wcss *wcss = rproc->priv;
+ 	int ret;
+ 
++	if (wcss->need_mem_protection) {
++		ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
++		if (ret) {
++			dev_err(wcss->dev, "not able to shutdown\n");
++			return ret;
++		}
++		goto pas_done;
++	}
++
+ 	/* WCSS powerdown */
+ 	if (wcss->requires_force_stop) {
+ 		ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
+@@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
+ 			return ret;
+ 	}
+ 
++pas_done:
+ 	clk_disable_unprepare(wcss->prng_clk);
+ 	qcom_q6v5_unprepare(&wcss->q6v5);
+ 
+@@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
+ 	struct q6v5_wcss *wcss = rproc->priv;
+ 	int ret;
+ 
+-	ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
+-				    0, wcss->mem_region, wcss->mem_phys,
+-				    wcss->mem_size, &wcss->mem_reloc);
++	if (wcss->need_mem_protection)
++		ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
++				    WCNSS_PAS_ID, wcss->mem_region,
++				    wcss->mem_phys, wcss->mem_size,
++				    &wcss->mem_reloc);
++	else
++		ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
++					    0, wcss->mem_region, wcss->mem_phys,
++					    wcss->mem_size, &wcss->mem_reloc);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1036,6 +1068,9 @@ static int q6v5_wcss_probe(struct platfo
+ 	if (!desc)
+ 		return -EINVAL;
+ 
++	if (desc->need_mem_protection && !qcom_scm_is_available())
++		return -EPROBE_DEFER;
++
+ 	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
+ 			    desc->firmware_name, sizeof(*wcss));
+ 	if (!rproc) {
+@@ -1049,6 +1084,7 @@ static int q6v5_wcss_probe(struct platfo
+ 
+ 	wcss->version = desc->version;
+ 	wcss->requires_force_stop = desc->requires_force_stop;
++	wcss->need_mem_protection = desc->need_mem_protection;
+ 
+ 	ret = q6v5_wcss_init_mmio(wcss, pdev);
+ 	if (ret)
+@@ -1120,6 +1156,7 @@ static const struct wcss_data wcss_ipq80
+ 	.wcss_q6_reset_required = true,
+ 	.ops = &q6v5_wcss_ipq8074_ops,
+ 	.requires_force_stop = true,
++	.need_mem_protection = true,
+ };
+ 
+ static const struct wcss_data wcss_qcs404_res_init = {

target/linux/ipq807x/patches-6.1/0114-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch

@@ -0,0 +1,103 @@
+From b422c9d4f048b086ce83f44a7cfcddcce162897f Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:07 +0530
+Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware
+
+IPQ8074 supports split firmware for q6 and m3 as well.
+So add support for loading the m3 firmware before q6.
+Now the drivers works fine for both split and unified
+firmwares.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
+ 1 file changed, 29 insertions(+), 4 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -139,6 +139,7 @@ struct q6v5_wcss {
+ 	u32 version;
+ 	bool requires_force_stop;
+ 	bool need_mem_protection;
++	const char *m3_firmware_name;
+ 
+ 	struct qcom_rproc_glink glink_subdev;
+ 	struct qcom_rproc_ssr ssr_subdev;
+@@ -147,7 +148,8 @@ struct q6v5_wcss {
+ struct wcss_data {
+ 	int (*init_clock)(struct q6v5_wcss *wcss);
+ 	int (*init_regulator)(struct q6v5_wcss *wcss);
+-	const char *firmware_name;
++	const char *q6_firmware_name;
++	const char *m3_firmware_name;
+ 	unsigned int crash_reason_smem;
+ 	u32 version;
+ 	bool aon_reset_required;
+@@ -789,8 +791,29 @@ static void *q6v5_wcss_da_to_va(struct r
+ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
+ {
+ 	struct q6v5_wcss *wcss = rproc->priv;
++	const struct firmware *m3_fw;
+ 	int ret;
+ 
++	if (wcss->m3_firmware_name) {
++		ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
++				       wcss->dev);
++		if (ret)
++			goto skip_m3;
++
++		ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
++					    wcss->m3_firmware_name, 0,
++					    wcss->mem_region, wcss->mem_phys,
++					    wcss->mem_size, &wcss->mem_reloc);
++
++		release_firmware(m3_fw);
++
++		if (ret) {
++			dev_err(wcss->dev, "can't load m3_fw.bXX\n");
++			return ret;
++		}
++	}
++
++skip_m3:
+ 	if (wcss->need_mem_protection)
+ 		ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
+ 				    WCNSS_PAS_ID, wcss->mem_region,
+@@ -1072,7 +1095,7 @@ static int q6v5_wcss_probe(struct platfo
+ 		return -EPROBE_DEFER;
+ 
+ 	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
+-			    desc->firmware_name, sizeof(*wcss));
++			    desc->q6_firmware_name, sizeof(*wcss));
+ 	if (!rproc) {
+ 		dev_err(&pdev->dev, "failed to allocate rproc\n");
+ 		return -ENOMEM;
+@@ -1085,6 +1108,7 @@ static int q6v5_wcss_probe(struct platfo
+ 	wcss->version = desc->version;
+ 	wcss->requires_force_stop = desc->requires_force_stop;
+ 	wcss->need_mem_protection = desc->need_mem_protection;
++	wcss->m3_firmware_name = desc->m3_firmware_name;
+ 
+ 	ret = q6v5_wcss_init_mmio(wcss, pdev);
+ 	if (ret)
+@@ -1150,7 +1174,8 @@ static int q6v5_wcss_remove(struct platf
+ 
+ static const struct wcss_data wcss_ipq8074_res_init = {
+ 	.init_clock = ipq8074_init_clock,
+-	.firmware_name = "IPQ8074/q6_fw.mdt",
++	.q6_firmware_name = "IPQ8074/q6_fw.mdt",
++	.m3_firmware_name = "IPQ8074/m3_fw.mdt",
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+ 	.aon_reset_required = true,
+ 	.wcss_q6_reset_required = true,
+@@ -1163,7 +1188,7 @@ static const struct wcss_data wcss_qcs40
+ 	.init_clock = qcs404_init_clock,
+ 	.init_regulator = qcs404_init_regulator,
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+-	.firmware_name = "wcnss.mdt",
++	.q6_firmware_name = "wcnss.mdt",
+ 	.version = WCSS_QCS404,
+ 	.aon_reset_required = false,
+ 	.wcss_q6_reset_required = false,

target/linux/ipq807x/patches-6.1/0115-remoteproc-qcom-Add-ssr-subdevice-identifier.patch

@@ -0,0 +1,24 @@
+From 3a8f67b4770c817b04794c9a02e3f88f85d86280 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:08 +0530
+Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier
+
+Add name for ssr subdevice on IPQ8074 SoC.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -1179,6 +1179,7 @@ static const struct wcss_data wcss_ipq80
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+ 	.aon_reset_required = true,
+ 	.wcss_q6_reset_required = true,
++	.ssr_name = "q6wcss",
+ 	.ops = &q6v5_wcss_ipq8074_ops,
+ 	.requires_force_stop = true,
+ 	.need_mem_protection = true,

target/linux/ipq807x/patches-6.1/0116-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch

@@ -0,0 +1,79 @@
+From 8c73af6e8d78c66cfef0f551b00d375ec0b67ff3 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:09 +0530
+Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
+
+Fixed issue in reading halt-regs parameter from device-tree.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
+ 1 file changed, 14 insertions(+), 8 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -86,7 +86,7 @@
+ #define TCSR_WCSS_CLK_MASK	0x1F
+ #define TCSR_WCSS_CLK_ENABLE	0x14
+ 
+-#define MAX_HALT_REG		3
++#define MAX_HALT_REG		4
+ 
+ #define WCNSS_PAS_ID		6
+ 
+@@ -154,6 +154,7 @@ struct wcss_data {
+ 	u32 version;
+ 	bool aon_reset_required;
+ 	bool wcss_q6_reset_required;
++	bool bcr_reset_required;
+ 	const char *ssr_name;
+ 	const char *sysmon_name;
+ 	int ssctl_id;
+@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
+ 		}
+ 	}
+ 
+-	wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
+-	if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
+-		dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
+-		return PTR_ERR(wcss->wcss_q6_bcr_reset);
++	if (desc->bcr_reset_required) {
++		wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
++									   "wcss_q6_bcr_reset");
++		if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
++			dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
++			return PTR_ERR(wcss->wcss_q6_bcr_reset);
++		}
+ 	}
+ 
+ 	return 0;
+@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
+ 		return -EINVAL;
+ 	}
+ 
+-	wcss->halt_q6 = halt_reg[0];
+-	wcss->halt_wcss = halt_reg[1];
+-	wcss->halt_nc = halt_reg[2];
++	wcss->halt_q6 = halt_reg[1];
++	wcss->halt_wcss = halt_reg[2];
++	wcss->halt_nc = halt_reg[3];
+ 
+ 	return 0;
+ }
+@@ -1179,6 +1183,7 @@ static const struct wcss_data wcss_ipq80
+ 	.crash_reason_smem = WCSS_CRASH_REASON,
+ 	.aon_reset_required = true,
+ 	.wcss_q6_reset_required = true,
++	.bcr_reset_required = false,
+ 	.ssr_name = "q6wcss",
+ 	.ops = &q6v5_wcss_ipq8074_ops,
+ 	.requires_force_stop = true,
+@@ -1193,6 +1198,7 @@ static const struct wcss_data wcss_qcs40
+ 	.version = WCSS_QCS404,
+ 	.aon_reset_required = false,
+ 	.wcss_q6_reset_required = false,
++	.bcr_reset_required = true,
+ 	.ssr_name = "mpss",
+ 	.sysmon_name = "wcnss",
+ 	.ssctl_id = 0x12,

target/linux/ipq807x/patches-6.1/0117-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch

@@ -0,0 +1,26 @@
+From ff7c6533ed8c4de58ed6c8aab03ea59c03eb4f31 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:10 +0530
+Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON
+
+Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+---
+ include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+@@ -381,6 +381,7 @@
+ #define GCC_NSSPORT4_RESET			143
+ #define GCC_NSSPORT5_RESET			144
+ #define GCC_NSSPORT6_RESET			145
++#define GCC_WCSSAON_RESET			146
+ 
+ #define USB0_GDSC				0
+ #define USB1_GDSC				1

target/linux/ipq807x/patches-6.1/0118-clk-qcom-Add-WCSSAON-reset.patch

@@ -0,0 +1,25 @@
+From 43d9788f546d24df22d8ba3fcc2497d7ccc198f3 Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:11 +0530
+Subject: [PATCH] clk: qcom: Add WCSSAON reset
+
+Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -4717,6 +4717,7 @@ static const struct qcom_reset_map gcc_i
+ 	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
+ 	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
+ 	[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
++	[GCC_WCSSAON_RESET] = { 0x59010, 0 },
+ };
+ 
+ static struct gdsc *gcc_ipq8074_gdscs[] = {

target/linux/ipq807x/patches-6.1/0119-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch

@@ -0,0 +1,48 @@
+From 406a332fd1bcc4e18d73cce390f56272fe9111d7 Mon Sep 17 00:00:00 2001
+From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
+Date: Fri, 17 Apr 2020 16:37:10 +0530
+Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
+
+There is no need for remoteproc to boot automatically, ath11k will trigger
+booting when its probing.
+
+Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -161,6 +161,7 @@ struct wcss_data {
+ 	const struct rproc_ops *ops;
+ 	bool requires_force_stop;
+ 	bool need_mem_protection;
++	bool need_auto_boot;
+ };
+ 
+ static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
+@@ -1150,6 +1151,7 @@ static int q6v5_wcss_probe(struct platfo
+ 						      desc->sysmon_name,
+ 						      desc->ssctl_id);
+ 
++	rproc->auto_boot = desc->need_auto_boot;
+ 	ret = rproc_add(rproc);
+ 	if (ret)
+ 		goto free_rproc;
+@@ -1188,6 +1190,7 @@ static const struct wcss_data wcss_ipq80
+ 	.ops = &q6v5_wcss_ipq8074_ops,
+ 	.requires_force_stop = true,
+ 	.need_mem_protection = true,
++	.need_auto_boot = false,
+ };
+ 
+ static const struct wcss_data wcss_qcs404_res_init = {
+@@ -1204,6 +1207,7 @@ static const struct wcss_data wcss_qcs40
+ 	.ssctl_id = 0x12,
+ 	.ops = &q6v5_wcss_qcs404_ops,
+ 	.requires_force_stop = false,
++	.need_auto_boot = true,
+ };
+ 
+ static const struct of_device_id q6v5_wcss_of_match[] = {

target/linux/ipq807x/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch

@@ -0,0 +1,120 @@
+From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Sat, 30 Jan 2021 10:50:13 +0530
+Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
+
+Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
+Also enables smp2p and mailboxes required for IPC.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
+ 1 file changed, 81 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -140,6 +140,32 @@
+ 		};
+ 	};
+ 
++	wcss: smp2p-wcss {
++		compatible = "qcom,smp2p";
++		qcom,smem = <435>, <428>;
++
++		interrupt-parent = <&intc>;
++		interrupts = <0 322 1>;
++
++		mboxes = <&apcs_glb 9>;
++
++		qcom,local-pid = <0>;
++		qcom,remote-pid = <1>;
++
++		wcss_smp2p_out: master-kernel {
++			qcom,entry-name = "master-kernel";
++			qcom,smp2p-feature-ssr-ack;
++			#qcom,smem-state-cells = <1>;
++		};
++
++		wcss_smp2p_in: slave-kernel {
++			qcom,entry-name = "slave-kernel";
++
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++	};
++
+ 	soc: soc {
+ 		#address-cells = <0x1>;
+ 		#size-cells = <0x1>;
+@@ -409,6 +435,11 @@
+ 			#hwlock-cells = <1>;
+ 		};
+ 
++		tcsr_q6: syscon@1945000 {
++			compatible = "syscon";
++			reg = <0x01945000 0xe000>;
++		};
++
+ 		spmi_bus: spmi@200f000 {
+ 			compatible = "qcom,spmi-pmic-arb";
+ 			reg = <0x0200f000 0x001000>,
+@@ -913,6 +944,56 @@
+ 				      "axi_s_sticky";
+ 			status = "disabled";
+ 		};
++
++		q6v5_wcss: q6v5_wcss@cd00000 {
++			compatible = "qcom,ipq8074-wcss-pil";
++			reg = <0x0cd00000 0x4040>,
++			      <0x004ab000 0x20>;
++			reg-names = "qdsp6",
++				    "rmb";
++			qca,auto-restart;
++			qca,extended-intc;
++			interrupts-extended = <&intc 0 325 1>,
++					      <&wcss_smp2p_in 0 0>,
++					      <&wcss_smp2p_in 1 0>,
++					      <&wcss_smp2p_in 2 0>,
++					      <&wcss_smp2p_in 3 0>;
++			interrupt-names = "wdog",
++					  "fatal",
++					  "ready",
++					  "handover",
++					  "stop-ack";
++
++			resets = <&gcc GCC_WCSSAON_RESET>,
++				 <&gcc GCC_WCSS_BCR>,
++				 <&gcc GCC_WCSS_Q6_BCR>;
++
++			reset-names = "wcss_aon_reset",
++				      "wcss_reset",
++				      "wcss_q6_reset";
++
++			clocks = <&gcc GCC_PRNG_AHB_CLK>;
++			clock-names = "prng";
++
++			qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
++
++			qcom,smem-states = <&wcss_smp2p_out 0>,
++					   <&wcss_smp2p_out 1>;
++			qcom,smem-state-names = "shutdown",
++						"stop";
++
++			memory-region = <&q6_region>;
++
++			glink-edge {
++				interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
++				qcom,remote-pid = <1>;
++				mboxes = <&apcs_glb 8>;
++
++				rpm_requests {
++					qcom,glink-channels = "IPCRTR";
++				};
++			};
++		};
+ 	};
+ 
+ 	timer {

target/linux/ipq807x/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch

@@ -0,0 +1,135 @@
+From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 21 Dec 2021 14:49:36 +0100
+Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
+
+IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
+by the ath11k.
+
+Add the required DT node to enable the built-in radios.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
+ 1 file changed, 111 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -994,6 +994,117 @@
+ 				};
+ 			};
+ 		};
++
++		wifi: wifi@c0000000 {
++			compatible = "qcom,ipq8074-wifi";
++			reg = <0xc000000 0x2000000>;
++
++			interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
++				     <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
++
++			interrupt-names = "misc-pulse1",
++					  "misc-latch",
++					  "sw-exception",
++					  "ce0",
++					  "ce1",
++					  "ce2",
++					  "ce3",
++					  "ce4",
++					  "ce5",
++					  "ce6",
++					  "ce7",
++					  "ce8",
++					  "ce9",
++					  "ce10",
++					  "ce11",
++					  "host2wbm-desc-feed",
++					  "host2reo-re-injection",
++					  "host2reo-command",
++					  "host2rxdma-monitor-ring3",
++					  "host2rxdma-monitor-ring2",
++					  "host2rxdma-monitor-ring1",
++					  "reo2ost-exception",
++					  "wbm2host-rx-release",
++					  "reo2host-status",
++					  "reo2host-destination-ring4",
++					  "reo2host-destination-ring3",
++					  "reo2host-destination-ring2",
++					  "reo2host-destination-ring1",
++					  "rxdma2host-monitor-destination-mac3",
++					  "rxdma2host-monitor-destination-mac2",
++					  "rxdma2host-monitor-destination-mac1",
++					  "ppdu-end-interrupts-mac3",
++					  "ppdu-end-interrupts-mac2",
++					  "ppdu-end-interrupts-mac1",
++					  "rxdma2host-monitor-status-ring-mac3",
++					  "rxdma2host-monitor-status-ring-mac2",
++					  "rxdma2host-monitor-status-ring-mac1",
++					  "host2rxdma-host-buf-ring-mac3",
++					  "host2rxdma-host-buf-ring-mac2",
++					  "host2rxdma-host-buf-ring-mac1",
++					  "rxdma2host-destination-ring-mac3",
++					  "rxdma2host-destination-ring-mac2",
++					  "rxdma2host-destination-ring-mac1",
++					  "host2tcl-input-ring4",
++					  "host2tcl-input-ring3",
++					  "host2tcl-input-ring2",
++					  "host2tcl-input-ring1",
++					  "wbm2host-tx-completions-ring3",
++					  "wbm2host-tx-completions-ring2",
++					  "wbm2host-tx-completions-ring1",
++					  "tcl2host-status-ring";
++			qcom,rproc = <&q6v5_wcss>;
++			status = "disabled";
++		};
+ 	};
+ 
+ 	timer {

target/linux/ipq807x/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch

@@ -0,0 +1,59 @@
+From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 31 Dec 2021 17:56:14 +0100
+Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
+
+Now that CPU clock is exposed and can be controlled, add the necessary
+properties to the CPU nodes.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -5,6 +5,7 @@
+ 
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
++#include <dt-bindings/clock/qcom,apss-ipq.h>
+ 
+ / {
+ 	#address-cells = <2>;
+@@ -38,6 +39,8 @@
+ 			reg = <0x0>;
+ 			next-level-cache = <&L2_0>;
+ 			enable-method = "psci";
++			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
++			clock-names = "cpu";
+ 		};
+ 
+ 		CPU1: cpu@1 {
+@@ -46,6 +49,8 @@
+ 			enable-method = "psci";
+ 			reg = <0x1>;
+ 			next-level-cache = <&L2_0>;
++			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
++			clock-names = "cpu";
+ 		};
+ 
+ 		CPU2: cpu@2 {
+@@ -54,6 +59,8 @@
+ 			enable-method = "psci";
+ 			reg = <0x2>;
+ 			next-level-cache = <&L2_0>;
++			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
++			clock-names = "cpu";
+ 		};
+ 
+ 		CPU3: cpu@3 {
+@@ -62,6 +69,8 @@
+ 			enable-method = "psci";
+ 			reg = <0x3>;
+ 			next-level-cache = <&L2_0>;
++			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
++			clock-names = "cpu";
+ 		};
+ 
+ 		L2_0: l2-cache {

target/linux/ipq807x/patches-6.1/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch

@@ -0,0 +1,48 @@
+From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 31 Dec 2021 20:38:06 +0100
+Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
+
+Since there is CPU Freq support as well as thermal sensor support
+now for the IPQ8074, add cooling cells to CPU nodes so that they can
+be used as cooling devices using CPU Freq.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -41,6 +41,7 @@
+ 			enable-method = "psci";
+ 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ 			clock-names = "cpu";
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		CPU1: cpu@1 {
+@@ -51,6 +52,7 @@
+ 			next-level-cache = <&L2_0>;
+ 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ 			clock-names = "cpu";
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		CPU2: cpu@2 {
+@@ -61,6 +63,7 @@
+ 			next-level-cache = <&L2_0>;
+ 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ 			clock-names = "cpu";
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		CPU3: cpu@3 {
+@@ -71,6 +74,7 @@
+ 			next-level-cache = <&L2_0>;
+ 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ 			clock-names = "cpu";
++			#cooling-cells = <2>;
+ 		};
+ 
+ 		L2_0: l2-cache {

target/linux/ipq807x/patches-6.1/0124-soc-qcom-socinfo-move-SMEM-item-struct-and-defines-t.patch

@@ -0,0 +1,168 @@
+From 97505f4c049fa2e8c86a53411a9e599033898533 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 31 Dec 2022 00:27:42 +0100
+Subject: [PATCH] soc: qcom: socinfo: move SMEM item struct and defines to a
+ header
+
+Move SMEM item struct and related defines to a header in order to be able
+to reuse them in the Qualcomm NVMEM CPUFreq driver instead of duplicating
+them.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/soc/qcom/socinfo.c       | 58 +--------------------------
+ include/linux/soc/qcom/socinfo.h | 67 ++++++++++++++++++++++++++++++++
+ 2 files changed, 68 insertions(+), 57 deletions(-)
+ create mode 100644 include/linux/soc/qcom/socinfo.h
+
+--- a/drivers/soc/qcom/socinfo.c
++++ b/drivers/soc/qcom/socinfo.c
+@@ -11,6 +11,7 @@
+ #include <linux/random.h>
+ #include <linux/slab.h>
+ #include <linux/soc/qcom/smem.h>
++#include <linux/soc/qcom/socinfo.h>
+ #include <linux/string.h>
+ #include <linux/sys_soc.h>
+ #include <linux/types.h>
+@@ -25,15 +26,6 @@
+ #define SOCINFO_MINOR(ver) ((ver) & 0xffff)
+ #define SOCINFO_VERSION(maj, min)  ((((maj) & 0xffff) << 16)|((min) & 0xffff))
+ 
+-#define SMEM_SOCINFO_BUILD_ID_LENGTH           32
+-#define SMEM_SOCINFO_CHIP_ID_LENGTH            32
+-
+-/*
+- * SMEM item id, used to acquire handles to respective
+- * SMEM region.
+- */
+-#define SMEM_HW_SW_BUILD_ID            137
+-
+ #ifdef CONFIG_DEBUG_FS
+ #define SMEM_IMAGE_VERSION_BLOCKS_COUNT        32
+ #define SMEM_IMAGE_VERSION_SIZE                4096
+@@ -116,54 +108,6 @@ static const char *const pmic_models[] =
+ };
+ #endif /* CONFIG_DEBUG_FS */
+ 
+-/* Socinfo SMEM item structure */
+-struct socinfo {
+-	__le32 fmt;
+-	__le32 id;
+-	__le32 ver;
+-	char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
+-	/* Version 2 */
+-	__le32 raw_id;
+-	__le32 raw_ver;
+-	/* Version 3 */
+-	__le32 hw_plat;
+-	/* Version 4 */
+-	__le32 plat_ver;
+-	/* Version 5 */
+-	__le32 accessory_chip;
+-	/* Version 6 */
+-	__le32 hw_plat_subtype;
+-	/* Version 7 */
+-	__le32 pmic_model;
+-	__le32 pmic_die_rev;
+-	/* Version 8 */
+-	__le32 pmic_model_1;
+-	__le32 pmic_die_rev_1;
+-	__le32 pmic_model_2;
+-	__le32 pmic_die_rev_2;
+-	/* Version 9 */
+-	__le32 foundry_id;
+-	/* Version 10 */
+-	__le32 serial_num;
+-	/* Version 11 */
+-	__le32 num_pmics;
+-	__le32 pmic_array_offset;
+-	/* Version 12 */
+-	__le32 chip_family;
+-	__le32 raw_device_family;
+-	__le32 raw_device_num;
+-	/* Version 13 */
+-	__le32 nproduct_id;
+-	char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
+-	/* Version 14 */
+-	__le32 num_clusters;
+-	__le32 ncluster_array_offset;
+-	__le32 num_defective_parts;
+-	__le32 ndefective_parts_array_offset;
+-	/* Version 15 */
+-	__le32 nmodem_supported;
+-};
+-
+ #ifdef CONFIG_DEBUG_FS
+ struct socinfo_params {
+ 	u32 raw_device_family;
+--- /dev/null
++++ b/include/linux/soc/qcom/socinfo.h
+@@ -0,0 +1,67 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
++ * Copyright (c) 2017-2019, Linaro Ltd.
++ */
++
++#ifndef __QCOM_SOCINFO_H__
++#define __QCOM_SOCINFO_H__
++
++/*
++ * SMEM item id, used to acquire handles to respective
++ * SMEM region.
++ */
++#define SMEM_HW_SW_BUILD_ID		137
++
++#define SMEM_SOCINFO_BUILD_ID_LENGTH	32
++#define SMEM_SOCINFO_CHIP_ID_LENGTH	32
++
++/* Socinfo SMEM item structure */
++struct socinfo {
++	__le32 fmt;
++	__le32 id;
++	__le32 ver;
++	char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
++	/* Version 2 */
++	__le32 raw_id;
++	__le32 raw_ver;
++	/* Version 3 */
++	__le32 hw_plat;
++	/* Version 4 */
++	__le32 plat_ver;
++	/* Version 5 */
++	__le32 accessory_chip;
++	/* Version 6 */
++	__le32 hw_plat_subtype;
++	/* Version 7 */
++	__le32 pmic_model;
++	__le32 pmic_die_rev;
++	/* Version 8 */
++	__le32 pmic_model_1;
++	__le32 pmic_die_rev_1;
++	__le32 pmic_model_2;
++	__le32 pmic_die_rev_2;
++	/* Version 9 */
++	__le32 foundry_id;
++	/* Version 10 */
++	__le32 serial_num;
++	/* Version 11 */
++	__le32 num_pmics;
++	__le32 pmic_array_offset;
++	/* Version 12 */
++	__le32 chip_family;
++	__le32 raw_device_family;
++	__le32 raw_device_num;
++	/* Version 13 */
++	__le32 nproduct_id;
++	char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
++	/* Version 14 */
++	__le32 num_clusters;
++	__le32 ncluster_array_offset;
++	__le32 num_defective_parts;
++	__le32 ndefective_parts_array_offset;
++	/* Version 15 */
++	__le32 nmodem_supported;
++};
++
++#endif

target/linux/ipq807x/patches-6.1/0125-cpufreq-qcom-nvmem-reuse-socinfo-SMEM-item-struct.patch

@@ -0,0 +1,50 @@
+From b7b7ea3a0cab42d4f1d4c9ae9eb7c7a3d03e7982 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 30 Dec 2022 22:51:47 +0100
+Subject: [PATCH] cpufreq: qcom-nvmem: reuse socinfo SMEM item struct
+
+Now that socinfo SMEM item struct and defines have been moved to a header
+so we can utilize that instead.
+
+Now the SMEM value can be accesed directly, there is no need for defining
+the ID for the SMEM request as well.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 14 +++++---------
+ 1 file changed, 5 insertions(+), 9 deletions(-)
+
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -28,8 +28,7 @@
+ #include <linux/pm_opp.h>
+ #include <linux/slab.h>
+ #include <linux/soc/qcom/smem.h>
+-
+-#define MSM_ID_SMEM	137
++#include <linux/soc/qcom/socinfo.h>
+ 
+ enum _msm_id {
+ 	MSM8996V3 = 0xF6ul,
+@@ -143,17 +142,14 @@ static void get_krait_bin_format_b(struc
+ static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
+ {
+ 	size_t len;
+-	u32 *msm_id;
++	struct socinfo *info;
+ 	enum _msm8996_version version;
+ 
+-	msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
+-	if (IS_ERR(msm_id))
++	info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, &len);
++	if (IS_ERR(info))
+ 		return NUM_OF_MSM8996_VERSIONS;
+ 
+-	/* The first 4 bytes are format, next to them is the actual msm-id */
+-	msm_id++;
+-
+-	switch ((enum _msm_id)*msm_id) {
++	switch (info->id) {
+ 	case MSM8996V3:
+ 	case APQ8096V3:
+ 		version = MSM8996_V3;

target/linux/ipq807x/patches-6.1/0126-cpufreq-qcom-nvmem-use-SoC-ID-s-from-bindings.patch

@@ -0,0 +1,46 @@
+From 132b2f15b8ae3f848b3e6f2962f409cfab0ca759 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 30 Dec 2022 23:33:47 +0100
+Subject: [PATCH] cpufreq: qcom-nvmem: use SoC ID-s from bindings
+
+SMEM SoC ID-s are now stored in DT bindings so lets use those instead of
+defining them in the driver again.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -30,12 +30,7 @@
+ #include <linux/soc/qcom/smem.h>
+ #include <linux/soc/qcom/socinfo.h>
+ 
+-enum _msm_id {
+-	MSM8996V3 = 0xF6ul,
+-	APQ8096V3 = 0x123ul,
+-	MSM8996SG = 0x131ul,
+-	APQ8096SG = 0x138ul,
+-};
++#include <dt-bindings/arm/qcom,ids.h>
+ 
+ enum _msm8996_version {
+ 	MSM8996_V3,
+@@ -150,12 +145,12 @@ static enum _msm8996_version qcom_cpufre
+ 		return NUM_OF_MSM8996_VERSIONS;
+ 
+ 	switch (info->id) {
+-	case MSM8996V3:
+-	case APQ8096V3:
++	case QCOM_ID_MSM8996:
++	case QCOM_ID_APQ8096:
+ 		version = MSM8996_V3;
+ 		break;
+-	case MSM8996SG:
+-	case APQ8096SG:
++	case QCOM_ID_MSM8996SG:
++	case QCOM_ID_APQ8096SG:
+ 		version = MSM8996_SG;
+ 		break;
+ 	default: