Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
2024-06-26 02:24:20 +08:00 · 2024-06-26 02:24:20 +08:00 · 64d9e0bf9e
commit 64d9e0bf9e
parent 3ed155f48c 1029340353
84 changed files with 3716 additions and 5423 deletions
--- a/package/boot/uboot-mvebu/Makefile
+++ b/package/boot/uboot-mvebu/Makefile
@ -60,13 +60,22 @@ define U-Boot/eDPU
  BUILD_SUBTARGET:=cortexa53
 endef

+define U-Boot/rb5009
+  NAME:=MikroTik RB5009
+  BUILD_SUBTARGET:=cortexa72
+  BUILD_DEVICES:=mikrotik_rb5009
+  UBOOT_CONFIG:=mvebu_rb5009
+  UBOOT_IMAGE:=u-boot.elf
+endef
+
 UBOOT_TARGETS:= \
 	clearfog \
 	helios4 \
 	omnia \
 	espressobin \
 	uDPU \
-	eDPU
+	eDPU \
+	rb5009

 define Package/u-boot/install
 	$(if $(findstring cortexa53,$(BUILD_SUBTARGET)),,$(Package/u-boot/install/default))
--- a/package/boot/uboot-mvebu/patches/100-mvebu-armada-8k-respect-CONFIG_DISTRO_DEFAULTS.patch
+++ b/package/boot/uboot-mvebu/patches/100-mvebu-armada-8k-respect-CONFIG_DISTRO_DEFAULTS.patch
@ -0,0 +1,38 @@
+From a322b1cbb3f3e606d33a11fd18df20811e5c16f2 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 21 Jun 2024 11:41:30 +0200
+Subject: [PATCH 1/3] mvebu: armada-8k: respect CONFIG_DISTRO_DEFAULTS
+
+Currently, Armada 8k config header is setting boot devices and including
+<config_distro_bootcmd.h> regardless of the CONFIG_DISTRO_DEFAULTS being
+enabled or not, thus populating the environment for distro boot even on
+devices that have no need for it.
+
+So, lets simply respect the value of CONFIG_DISTRO_DEFAULTS.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ include/configs/mvebu_armada-8k.h | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
+@@ -30,7 +30,7 @@
+ /*
+  * PCI configuration
+  */
+-
+#ifdef CONFIG_DISTRO_DEFAULTS
+ #define BOOT_TARGET_DEVICES(func) \
+ 	func(MMC, mmc, 1) \
+ 	func(MMC, mmc, 0) \
+@@ -40,6 +40,9 @@
+ 	func(DHCP, dhcp, na)
+ 
+ #include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+ 
+ #define CFG_EXTRA_ENV_SETTINGS	\
+ 	"scriptaddr=0x6d00000\0"	\
--- a/package/boot/uboot-mvebu/patches/101-net-mvpp2-fix-10GBase-R-support.patch
+++ b/package/boot/uboot-mvebu/patches/101-net-mvpp2-fix-10GBase-R-support.patch
@ -0,0 +1,108 @@
+From 0de5d031f36bca4f7c2686287eff1ef0f5412367 Mon Sep 17 00:00:00 2001
+From: Sergey Sergeev <adron@yapic.net>
+Date: Sun, 16 Jan 2022 17:19:35 +0100
+Subject: [PATCH 2/3] net: mvpp2: fix 10GBase-R support
+
+Due to the lack of XPCS register initialization code and partially incorrect
+initialization of the MPCS network controler registers (tested on Mikrotik RB5009
+in conjunction with MV88E6393X) the network does not work correctly.
+The problem manifests itself as an arbitrary delay (0.4-4 sec) for the actual
+data transmission to the network! Accordingly, an almost completely non-working
+network for U-Boot is obtained. The code is backported from a similar Linux driver.
+
+Signed-off-by: Sergey Sergeev <adron@yapic.net>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/net/mvpp2.c | 73 +++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
+@@ -3255,6 +3255,76 @@ static int gop_gpcs_reset(struct mvpp2_p
+ 	return 0;
+ }
+ 
+static void gop_pcs_reset_assert(struct mvpp2_port *port)
+{
+	u32 val;
+
+	if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
+		return;
+
+	val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		PCS_CLOCK_RESET);
+	val &= ~(MAC_CLK_RESET_MASK | RX_SD_CLK_RESET_MASK | TX_SD_CLK_RESET_MASK);
+	val |= CLK_DIV_PHASE_SET_MASK;
+	writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		PCS_CLOCK_RESET);
+
+	val = readl(port->priv->xpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		MVPP22_XPCS_GLOBAL_CFG_0_REG);
+	val &= ~MVPP22_XPCS_PCSRESET;
+	writel(val,	port->priv->xpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		MVPP22_XPCS_GLOBAL_CFG_0_REG);
+}
+
+static void gps_pcs_reset_deassert(struct mvpp2_port *port)
+{
+	u32 val;
+
+	if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
+		return;
+
+	/* this code is only for case of PHY_INTERFACE_MODE_10GBASER! */
+	val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		PCS_CLOCK_RESET);
+	val |= MAC_CLK_RESET_MASK | RX_SD_CLK_RESET_MASK |
+	       TX_SD_CLK_RESET_MASK;
+	val &= ~CLK_DIV_PHASE_SET_MASK;
+	writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		PCS_CLOCK_RESET);
+}
+
+/* Set the internal mux's to the required PCS in the PI */
+static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
+{
+	u32 val;
+	int lane;
+
+	switch (num_of_lanes) {
+	case 1:
+		lane = 0;
+		break;
+	case 2:
+		lane = 1;
+		break;
+	case 4:
+		lane = 2;
+		break;
+	default:
+		return -1;
+	}
+
+	/* configure XG MAC mode */
+	val = readl(port->priv->xpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		MVPP22_XPCS_GLOBAL_CFG_0_REG);
+	val &= ~MVPP22_XPCS_PCSMODE_MASK;
+	val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
+	val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
+	writel(val, port->priv->xpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+		MVPP22_XPCS_GLOBAL_CFG_0_REG);
+
+	return 0;
+}
+
+ static int gop_mpcs_mode(struct mvpp2_port *port)
+ {
+ 	u32 val;
+@@ -3397,7 +3467,10 @@ static int gop_port_init(struct mvpp2_po
+ 		num_of_act_lanes = 2;
+ 		mac_num = 0;
+ 		/* configure PCS */
+		gop_pcs_reset_assert(port);
+		gop_xpcs_mode(port, num_of_act_lanes);
+ 		gop_mpcs_mode(port);
+		gps_pcs_reset_deassert(port);
+ 		/* configure MAC */
+ 		gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
+ 
--- a/package/boot/uboot-mvebu/patches/102-arm-mvebu-add-support-for-MikroTik-RB5009UG-S-IN.patch
+++ b/package/boot/uboot-mvebu/patches/102-arm-mvebu-add-support-for-MikroTik-RB5009UG-S-IN.patch
@ -0,0 +1,459 @@
+From 163b07bda901b728f4f208a296c15b513f9d5b49 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 2 Jan 2022 15:10:34 +0100
+Subject: [PATCH 3/3] arm: mvebu: add support for MikroTik RB5009UG+S+IN
+
+Specifications:
+  - SoC: Marvell Armada 7040 (88F7040) - 4 cores, ARMv8, 1.4GHz, 64bit
+  - RAM: 1024MB DDR4
+  - Flash: 16MB SPI NOR flash, 1024MB NAND
+  - Ethernet: One Marvell 88E6393X - Amethyst: one 2.5G + seven 1G ports and one SFP+
+  - LED: User, SFP, Hdr1, Hdr2
+  - Buttons: Reset
+  - UART: 115200 8n1
+  - USB: One USB3 port
+
+This provides only the basic support required to boot OpenWrt, however
+networking via the switch also works since its preconfigured by MikroTik
+RouterBoot since we are using U-Boot as the secondary bootloader.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm/dts/Makefile                         |   1 +
+ arch/arm/dts/armada-7040-rb5009.dts           | 241 ++++++++++++++++++
+ arch/arm/mach-mvebu/arm64-common.c            |  10 +-
+ .../mvebu_armada-8k/mikrotik-rb5009.env       |  52 ++++
+ configs/mvebu_rb5009_defconfig                |  97 +++++++
+ 5 files changed, 398 insertions(+), 3 deletions(-)
+ create mode 100644 arch/arm/dts/armada-7040-rb5009.dts
+ create mode 100644 board/Marvell/mvebu_armada-8k/mikrotik-rb5009.env
+ create mode 100644 configs/mvebu_rb5009_defconfig
+
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -333,6 +333,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
+ 	armada-3720-uDPU.dtb			\
+ 	armada-7040-db-nand.dtb			\
+ 	armada-7040-db.dtb			\
+	armada-7040-rb5009.dtb			\
+ 	armada-8040-clearfog-gt-8k.dtb		\
+ 	armada-8040-db.dtb			\
+ 	armada-8040-mcbin.dtb			\
+--- /dev/null
+++ b/arch/arm/dts/armada-7040-rb5009.dts
+@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
+ */
+
+/*
+ * Device Tree file for MikroTik RB5009
+ * Boot device: SPI NOR, 0x0
+ */
+
+#include "armada-7040.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "MikroTik RB5009";
+	compatible = "mikrotik,rb5009", "marvell,armada7040",
+		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_user: user {
+			label = "green:user";
+			gpios = <&cp0_gpio1 26 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		sfp {
+			label = "green:sfp";
+			gpios = <&cp0_gpio1 25 GPIO_ACTIVE_LOW>;
+		};
+
+		hdr1 {
+			label = "blue:hdr1";
+			gpios = <&cp0_gpio0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		hdr2 {
+			label = "blue:hdr2";
+			gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&cp0_gpio0 28 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&ap_pinctl {
+	   /* MPP Bus:
+	    * SPI   [0-3]
+	    * UART0 [11,19]
+	    */
+		  /* 0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 3 3 3 3 0 0 0 0 0 0
+		     0 3 0 0 0 0 0 0 0 3 >;
+
+	ap_spi_pins: ap-spi-pins {
+		marvell,pins = < 0 1 2 3 >;
+		marvell,function = <3>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&ap_spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&ap_spi_pins>;
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <20000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Empty space on NOR repurposed for U-Boot environment */
+			partition@fe0000 {
+				compatible = "u-boot,env";
+				label = "u-boot-env";
+				reg = <0xfe0000 0x20000>;
+			};
+		};
+	};
+};
+
+&cp0_pinctl {
+		/* MPP Bus:
+		 * NF_RBn  [13]
+		 * DEV_BUS [15-27]
+		 * UART0   [29,30]
+		 * SMI     [35,36]
+		 * I2C0    [37,38]
+		 * SPI1    [47-50]
+		 */
+		/*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = < 0   0   0   0   0   0   0   0   0   0
+		     0   0   0   2   0   1   1   1   1   1
+		     1   1   1   1   1   1   1   1   0   0xA
+		     0xA 0   0   0   0   8   8   2   2   0
+		     0   0   0   0   0   0   0   5   5   5
+		     5   0   0   0   0   0   0   0   0   0
+		     0   0   0 >;
+
+	cp0_nand_pins: cp0-nand-pins {
+		marvell,pins = < 15 16 17 18 19 20 21 22 23 24 25 26 27 >;
+		marvell,function = <1>;
+	};
+
+	cp0_smi_pins: cp0-smi-pins {
+		marvell,pins = < 35 36 >;
+		marvell,function = <8>;
+	};
+
+	cp0_spi1_pins: cp0-spi-pins-1 {
+		marvell,pins = < 47 48 49 50 >;
+		marvell,function = <5>;
+	};
+};
+
+&cp0_gpio1 {
+	enable-usb-power {
+		gpio-hog;
+		gpios = <23 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "enable USB power";
+	};
+
+	enable-leds-power {
+		gpio-hog;
+		gpios = <27 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "enable LED-s power";
+	};
+};
+
+&cp0_nand {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_nand_pins>;
+
+	nand-ecc-strength = <4>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "YAFFS";
+			reg = <0x0 0x800000>;
+		};
+
+		partition@800000 {
+			label = "ubi";
+			reg = <0x800000 0x3f800000>;
+		};
+	};
+};
+
+&cp0_usb3_1 {
+	status = "okay";
+};
+
+&cp0_utmi1 {
+	status = "okay";
+};
+
+&cp0_i2c0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	clock-frequency = <100000>;
+};
+
+&cp0_comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+
+	phy3 {
+		phy-type = <COMPHY_TYPE_USB3_HOST1>;
+		phy-speed = <COMPHY_SPEED_5G>;
+	};
+
+	phy4 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+
+	phy5 {
+		phy-type = <COMPHY_TYPE_UNCONNECTED>;
+	};
+};
+
+&cp0_mdio {
+	status = "okay";
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "10gbase-r";
+};
+--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
+@@ -62,9 +62,13 @@ __weak int dram_init_banksize(void)
+ __weak int dram_init(void)
+ {
+ 	if (IS_ENABLED(CONFIG_ARMADA_8K)) {
+-		gd->ram_size = a8k_dram_scan_ap_sz();
+-		if (gd->ram_size != 0)
+-			return 0;
+		if (of_machine_is_compatible("mikrotik,rb5009"))
+			return fdtdec_setup_mem_size_base();
+		else {
+			gd->ram_size = a8k_dram_scan_ap_sz();
+			if (gd->ram_size != 0)
+				return 0;
+		}
+ 	}
+ 
+ 	if (IS_ENABLED(CONFIG_ARMADA_3700))
+--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/mikrotik-rb5009.env
+@@ -0,0 +1,52 @@
+openwrt_initramfs=openwrt-mvebu-cortexa72-mikrotik_rb5009-initramfs-uImage.itb
+boot_devices=ubi usb net
+recovery_boot_devices=usb net
+
+button_cmd_0_name=reset
+button_cmd_0=run recovery_bootcmd
+
+recovery_bootcmd=
+	led green:sfp on;
+	led blue:hdr1 on;
+	led blue:hdr2 on;
+
+	for b in ${recovery_boot_devices}; do
+		if test ${b} = usb; then
+			run usbboot;
+		fi;
+		if test ${b} = net; then
+			run netboot;
+		fi;
+	done;
+
+bootcmd=
+	for b in ${boot_devices}; do
+		if test ${b} = ubi; then
+			run ubiboot;
+		fi;
+		if test ${b} = usb; then
+			run usbboot;
+		fi;
+		if test ${b} = net; then
+			run netboot;
+		fi;
+	done;
+
+ubiboot=
+	echo Booting from NAND (UBI);
+	ubi part ubi;
+	setenv loadimagecmd ${ubiloadimage};
+	ubi read ${loadaddr} kernel;
+	bootm ${loadaddr};
+
+usbboot=
+	echo Booting from USB Storage;
+	usb start;
+	load usb 0:1 ${loadaddr} ${openwrt_initramfs};
+	bootm ${loadaddr};
+
+netboot=
+	echo Booting from Network;
+	dhcp;
+	tftpboot ${loadaddr} ${openwrt_initramfs};
+	bootm ${loadaddr};
+--- /dev/null
+++ b/configs/mvebu_rb5009_defconfig
+@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x0
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="mikrotik-rb5009"
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xfe0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-7040-rb5009"
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
+CONFIG_BUTTON_CMD=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_BOOTSTD is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOG_ERROR_RETURN=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVPP2=y
+CONFIG_PHY=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_YAFFS2=y
+# CONFIG_SHA256 is not set
+# CONFIG_EFI_LOADER is not set
--- a/package/kernel/linux/modules/hwmon.mk
+++ b/package/kernel/linux/modules/hwmon.mk
@ -198,7 +198,7 @@ define KernelPackage/hwmon-g762
 endef

 define KernelPackage/hwmon-g762/description
- Kernel module for Global Mixed-mode Technology Inc G762 and G763 fan speed PWM controller chips.
+ Kernel module for Global Mixed-mode Technology Inc G761/G762/G763 fan speed PWM controller chips.
 endef

 $(eval $(call KernelPackage,hwmon-g762))
--- a/package/utils/mtd-utils/Makefile
+++ b/package/utils/mtd-utils/Makefile
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk

 PKG_NAME:=mtd-utils
 PKG_VERSION:=2.1.6
-PKG_RELEASE:=2
+PKG_RELEASE:=3

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:=https://infraroot.at/pub/mtd/
--- a/package/utils/mtd-utils/patches/100-fix_includes.patch
+++ b/package/utils/mtd-utils/patches/100-fix_includes.patch
@ -1,10 +0,0 @@
--- a/lib/libfec.c
-+++ b/lib/libfec.c
-@@ -45,6 +45,7 @@
- #include <stdio.h>
- #include <stdlib.h>
- #include <string.h>
-+#include <sys/types.h>
- #include "libfec.h"
- 
- /*
--- a/package/utils/mtd-utils/patches/130-lzma_jffs2.patch
+++ b/package/utils/mtd-utils/patches/130-lzma_jffs2.patch
--- a/target/linux/bmips/Makefile
+++ b/target/linux/bmips/Makefile
@ -9,7 +9,7 @@ BOARDNAME:=Broadcom BMIPS
 SUBTARGETS:=bcm6318 bcm6328 bcm6358 bcm6362 bcm6368 bcm63268
 FEATURES:=gpio squashfs usb

-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6

 define Target/Description
 	Build firmware images for BCM33xx cable modem chips,
--- a/target/linux/bmips/bcm6318/config-6.6
+++ b/target/linux/bmips/bcm6318/config-6.6
@ -38,6 +38,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_NO_EFFICIENT_FFS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
@ -45,15 +46,16 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_CPUFREQ=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
 CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_INFO=y
@ -78,16 +80,19 @@ CONFIG_DT_NONE=y
 # CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y
 CONFIG_FW_CFE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
@ -105,7 +110,6 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GPIO_BRCMSTB is not set
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
@ -114,6 +118,7 @@ CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HZ_PERIODIC=y
 CONFIG_INITRAMFS_SOURCE=""
@ -122,6 +127,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
 # CONFIG_LEDS_SERCOMM_MSP430 is not set
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -132,7 +138,6 @@ CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_BCM6368=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MIPS=y
@ -145,11 +150,11 @@ CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_4=y
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_NR_CPU_NR_MAP=2
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@ -164,19 +169,25 @@ CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPLIT_BCM63XX_FW=y
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
 CONFIG_NET_DSA_TAG_BRCM=y
 CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
 CONFIG_NO_EXCEPT_FILL=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -200,6 +211,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYSICAL_START=0x80010000
 CONFIG_PHY_BCM63XX_USBH=y
@ -248,7 +260,7 @@ CONFIG_SPI=y
 CONFIG_SPI_BCM63XX_HSSPI=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWPHY=y
 CONFIG_SYNC_R4K=y
--- a/target/linux/bmips/bcm63268/config-6.6
+++ b/target/linux/bmips/bcm63268/config-6.6
@ -38,6 +38,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_NO_EFFICIENT_FFS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
@ -45,16 +46,17 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_CPUFREQ=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
 CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_INFO=y
@ -79,16 +81,19 @@ CONFIG_DT_NONE=y
 # CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y
 CONFIG_FW_CFE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
@ -106,7 +111,6 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GPIO_BRCMSTB is not set
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
@ -115,6 +119,7 @@ CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_BCM2835=y
@ -125,6 +130,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
 # CONFIG_LEDS_SERCOMM_MSP430 is not set
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -135,7 +141,6 @@ CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_BCM6368=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MIPS=y
@ -148,11 +153,11 @@ CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_4=y
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_NR_CPU_NR_MAP=2
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@ -178,19 +183,25 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
 CONFIG_NET_DSA_TAG_BRCM=y
 CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
 CONFIG_NO_EXCEPT_FILL=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -214,6 +225,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYSICAL_START=0x80010000
 CONFIG_PHY_BCM63XX_USBH=y
@ -262,7 +274,7 @@ CONFIG_SPI_BCM63XX=y
 CONFIG_SPI_BCM63XX_HSSPI=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWPHY=y
 CONFIG_SYNC_R4K=y
--- a/target/linux/bmips/bcm6328/config-6.6
+++ b/target/linux/bmips/bcm6328/config-6.6
@ -38,6 +38,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_NO_EFFICIENT_FFS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
@ -45,16 +46,17 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_CPUFREQ=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
 CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_INFO=y
@ -79,16 +81,19 @@ CONFIG_DT_NONE=y
 # CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y
 CONFIG_FW_CFE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
@ -106,7 +111,6 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GPIO_BRCMSTB is not set
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
@ -115,6 +119,7 @@ CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HZ_PERIODIC=y
 CONFIG_INITRAMFS_SOURCE=""
@ -123,6 +128,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
 # CONFIG_LEDS_SERCOMM_MSP430 is not set
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -133,7 +139,6 @@ CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_BCM6368=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MIPS=y
@ -146,11 +151,11 @@ CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_4=y
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_NR_CPU_NR_MAP=2
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@ -176,19 +181,25 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
 CONFIG_NET_DSA_TAG_BRCM=y
 CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
 CONFIG_NO_EXCEPT_FILL=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -212,6 +223,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYSICAL_START=0x80010000
 CONFIG_PHY_BCM63XX_USBH=y
@ -260,7 +272,7 @@ CONFIG_SPI=y
 CONFIG_SPI_BCM63XX_HSSPI=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWPHY=y
 CONFIG_SYNC_R4K=y
--- a/target/linux/bmips/bcm6358/config-6.6
+++ b/target/linux/bmips/bcm6358/config-6.6
@ -36,6 +36,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_NO_EFFICIENT_FFS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
@ -43,15 +44,16 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_CPUFREQ=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
 CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_INFO=y
@ -76,16 +78,19 @@ CONFIG_DT_NONE=y
 # CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y
 CONFIG_FW_CFE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
@ -103,7 +108,6 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GPIO_BRCMSTB is not set
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
@ -112,6 +116,7 @@ CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HZ_PERIODIC=y
 CONFIG_INITRAMFS_SOURCE=""
@ -120,6 +125,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
 # CONFIG_LEDS_SERCOMM_MSP430 is not set
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -129,7 +135,6 @@ CONFIG_MDIO_BUS=y
 # CONFIG_MDIO_BUS_MUX_BCM6368 is not set
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MIPS=y
@ -142,11 +147,11 @@ CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_4=y
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_NR_CPU_NR_MAP=2
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@ -162,19 +167,25 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPLIT_BCM63XX_FW=y
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
 CONFIG_NET_DSA_TAG_BRCM=y
 CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
 CONFIG_NO_EXCEPT_FILL=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -196,6 +207,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYSICAL_START=0x80010000
 CONFIG_PHY_BCM63XX_USBH=y
@ -239,10 +251,9 @@ CONFIG_SOCK_RX_QUEUE_MAPPING=y
 # CONFIG_SOC_BCM63XX is not set
 CONFIG_SPI=y
 CONFIG_SPI_BCM63XX=y
-# CONFIG_SPI_BCM63XX_HSSPI is not set
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWPHY=y
 CONFIG_SYNC_R4K=y
--- a/target/linux/bmips/bcm6362/config-6.6
+++ b/target/linux/bmips/bcm6362/config-6.6
@ -38,6 +38,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_NO_EFFICIENT_FFS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
@ -45,16 +46,17 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_CPUFREQ=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
 CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_INFO=y
@ -79,16 +81,19 @@ CONFIG_DT_NONE=y
 # CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y
 CONFIG_FW_CFE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
@ -106,7 +111,6 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GPIO_BRCMSTB is not set
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
@ -115,6 +119,7 @@ CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_BCM2835=y
@ -125,6 +130,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
 # CONFIG_LEDS_SERCOMM_MSP430 is not set
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -135,7 +141,6 @@ CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_BCM6368=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MIPS=y
@ -148,11 +153,11 @@ CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_4=y
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_NR_CPU_NR_MAP=2
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@ -177,19 +182,25 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
 CONFIG_NET_DSA_TAG_BRCM=y
 CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
 CONFIG_NO_EXCEPT_FILL=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -213,6 +224,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYSICAL_START=0x80010000
 CONFIG_PHY_BCM63XX_USBH=y
@ -261,7 +273,7 @@ CONFIG_SPI_BCM63XX=y
 CONFIG_SPI_BCM63XX_HSSPI=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWPHY=y
 CONFIG_SYNC_R4K=y
--- a/target/linux/bmips/bcm6368/config-6.6
+++ b/target/linux/bmips/bcm6368/config-6.6
@ -37,6 +37,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_NO_EFFICIENT_FFS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
@ -44,16 +45,17 @@ CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_CPUFREQ=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRASH_CORE=y
 CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_INFO=y
@ -78,16 +80,19 @@ CONFIG_DT_NONE=y
 # CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FWNODE_MDIO=y
 CONFIG_FW_CFE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
@ -105,7 +110,6 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-# CONFIG_GPIO_BRCMSTB is not set
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
@ -114,6 +118,7 @@ CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_BCM2835=y
@ -124,6 +129,7 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
+CONFIG_KEXEC_CORE=y
 # CONFIG_LEDS_SERCOMM_MSP430 is not set
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
@ -134,7 +140,6 @@ CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_BCM6368=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MIPS=y
@ -147,11 +152,11 @@ CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_4=y
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_NR_CPU_NR_MAP=2
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
@ -177,19 +182,25 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y
 CONFIG_NET_DSA_TAG_BRCM=y
 CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_DSA_TAG_NONE=y
+CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
 CONFIG_NO_EXCEPT_FILL=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -211,6 +222,7 @@ CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYSICAL_START=0x80010000
 CONFIG_PHY_BCM63XX_USBH=y
@ -254,10 +266,9 @@ CONFIG_SOCK_RX_QUEUE_MAPPING=y
 # CONFIG_SOC_BCM63XX is not set
 CONFIG_SPI=y
 CONFIG_SPI_BCM63XX=y
-# CONFIG_SPI_BCM63XX_HSSPI is not set
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWPHY=y
 CONFIG_SYNC_R4K=y
--- a/target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts
+++ b/target/linux/bmips/dts/bcm6328-innacomm-w3400v6.dts
@ -131,7 +131,6 @@
 		active-low;
 		function = LED_FUNCTION_POWER;
 		color = <LED_COLOR_ID_GREEN>;
-		default-state = "on";
 	};

 	led_power_red: led@5 {
--- a/target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts
+++ b/target/linux/bmips/dts/bcm6328-sercomm-ad1018.dts
@ -109,7 +109,6 @@
 		active-low;
 		function = LED_FUNCTION_POWER;
 		color = <LED_COLOR_ID_GREEN>;
-		default-state = "on";
 	};

 	led@10 {
--- a/target/linux/bmips/patches-6.6/100-irqchip-add-support-for-bcm6345-style-external-inter.patch
+++ b/target/linux/bmips/patches-6.6/100-irqchip-add-support-for-bcm6345-style-external-inter.patch
@ -50,7 +50,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 +};
 --- a/drivers/irqchip/Kconfig
 +++ b/drivers/irqchip/Kconfig
-@@ -109,6 +109,10 @@ config I8259
+@@ -111,6 +111,10 @@ config I8259
 	bool
 	select IRQ_DOMAIN
 
@ -63,7 +63,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 	select GENERIC_IRQ_CHIP
 --- a/drivers/irqchip/Makefile
 +++ b/drivers/irqchip/Makefile
-@@ -63,6 +63,7 @@ obj-$(CONFIG_XTENSA_MX)			+= irq-xtensa-
+@@ -62,6 +62,7 @@ obj-$(CONFIG_XTENSA_MX)			+= irq-xtensa-
 obj-$(CONFIG_XILINX_INTC)		+= irq-xilinx-intc.o
 obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
 obj-$(CONFIG_SOC_VF610)			+= irq-vf610-mscm-ir.o
--- a/target/linux/bmips/patches-6.6/200-mips-bmips-automatically-detect-CPU-frequency.patch
+++ b/target/linux/bmips/patches-6.6/200-mips-bmips-automatically-detect-CPU-frequency.patch
@ -15,7 +15,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/arch/mips/bmips/setup.c
 +++ b/arch/mips/bmips/setup.c
-@@ -32,13 +32,52 @@
+@@ -31,13 +31,52 @@
 
 #define RELO_NORMAL_VEC		BIT(18)
 
@ -68,7 +68,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 struct bmips_quirk {
 	const char		*compatible;
 	void			(*quirk_fn)(void);
-@@ -154,17 +193,161 @@ const char *get_system_type(void)
+@@ -153,17 +192,161 @@ const char *get_system_type(void)
 	return "Generic BMIPS kernel";
 }
 
--- a/target/linux/bmips/patches-6.6/201-mips-bmips-automatically-detect-RAM-size.patch
+++ b/target/linux/bmips/patches-6.6/201-mips-bmips-automatically-detect-RAM-size.patch
@ -15,15 +15,15 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/arch/mips/bmips/setup.c
 +++ b/arch/mips/bmips/setup.c
-@@ -19,6 +19,7 @@
- #include <linux/of_platform.h>
+@@ -18,6 +18,7 @@
+ #include <linux/of_fdt.h>
 #include <linux/libfdt.h>
 #include <linux/smp.h>
 +#include <linux/types.h>
 #include <asm/addrspace.h>
 #include <asm/bmips.h>
 #include <asm/bootinfo.h>
-@@ -35,13 +36,16 @@
+@@ -34,13 +35,16 @@
 #define REG_BCM6318_SOB		((void __iomem *)CKSEG1ADDR(0x10000900))
 #define BCM6318_FREQ_SHIFT	23
 #define BCM6318_FREQ_MASK	(0x3 << BCM6318_FREQ_SHIFT)
@ -40,7 +40,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 #define REG_BCM6358_DDR_PLLC	((void __iomem *)0xfffe12b8)
 #define BCM6358_PLLC_M1_SHIFT	0
 #define BCM6358_PLLC_M1_MASK	(0xff << BCM6358_PLLC_M1_SHIFT)
-@@ -53,7 +57,9 @@
+@@ -52,7 +56,9 @@
 #define REG_BCM6362_MISC_SB	((void __iomem *)CKSEG1ADDR(0x10001814))
 #define BCM6362_FCVO_SHIFT	1
 #define BCM6362_FCVO_MASK	(0x1f << BCM6362_FCVO_SHIFT)
@ -50,7 +50,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 #define REG_BCM6368_DDR_PLLC	((void __iomem *)CKSEG1ADDR(0x100012a0))
 #define BCM6368_PLLC_P1_SHIFT	0
 #define BCM6368_PLLC_P1_MASK	(0xf << BCM6368_PLLC_P1_SHIFT)
-@@ -68,6 +74,21 @@
+@@ -67,6 +73,21 @@
 #define REG_BCM63268_MISC_SB	((void __iomem *)CKSEG1ADDR(0x10001814))
 #define BCM63268_FCVO_SHIFT	21
 #define BCM63268_FCVO_MASK	(0xf << BCM63268_FCVO_SHIFT)
@ -72,7 +72,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 
 extern bool bmips_rac_flush_disable;
 
-@@ -78,6 +99,11 @@ struct bmips_cpufreq {
+@@ -77,6 +98,11 @@ struct bmips_cpufreq {
 	u32			(*cpu_freq)(void);
 };
 
@ -84,7 +84,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 struct bmips_quirk {
 	const char		*compatible;
 	void			(*quirk_fn)(void);
-@@ -352,9 +378,90 @@ void __init plat_time_init(void)
+@@ -351,9 +377,90 @@ void __init plat_time_init(void)
 	mips_hpt_frequency = freq;
 }
 
@ -175,7 +175,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 	const struct bmips_quirk *q;
 
 	set_io_port_base(0);
-@@ -372,6 +479,18 @@ void __init plat_mem_setup(void)
+@@ -374,6 +481,18 @@ void __init plat_mem_setup(void)
 
 	__dt_setup_arch(dtb);
 
--- a/target/linux/bmips/patches-6.6/202-mips-bmips-tweak-Kconfig-options.patch
+++ b/target/linux/bmips/patches-6.6/202-mips-bmips-tweak-Kconfig-options.patch
@ -13,7 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -274,19 +274,13 @@ config BMIPS_GENERIC
+@@ -272,19 +272,13 @@ config BMIPS_GENERIC
 	select SYNC_R4K
 	select COMMON_CLK
 	select BCM6345_L1_IRQ
@ -33,7 +33,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 	select SWAP_IO_SPACE
 	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
 	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
-@@ -296,6 +290,7 @@ config BMIPS_GENERIC
+@@ -294,6 +288,7 @@ config BMIPS_GENERIC
 	select HAVE_PCI
 	select PCI_DRIVERS_GENERIC
 	select FW_CFE
@ -43,7 +43,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 	  BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
 --- a/drivers/irqchip/Kconfig
 +++ b/drivers/irqchip/Kconfig
-@@ -122,7 +122,6 @@ config BCM6345_L1_IRQ
+@@ -124,7 +124,6 @@ config BCM6345_L1_IRQ
 config BCM7038_L1_IRQ
 	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
 	depends on ARCH_BRCMSTB || BMIPS_GENERIC
@ -51,7 +51,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
-@@ -130,14 +129,12 @@ config BCM7038_L1_IRQ
+@@ -132,14 +131,12 @@ config BCM7038_L1_IRQ
 config BCM7120_L2_IRQ
 	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
 	depends on ARCH_BRCMSTB || BMIPS_GENERIC
--- a/target/linux/bmips/patches-6.6/203-mips-bmips-dma-fix-CBR-address.patch
+++ b/target/linux/bmips/patches-6.6/203-mips-bmips-dma-fix-CBR-address.patch
@ -46,7 +46,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 }
 --- a/arch/mips/bmips/setup.c
 +++ b/arch/mips/bmips/setup.c
-@@ -90,7 +90,7 @@
+@@ -89,7 +89,7 @@
 
 #define DDR_CSEND_REG		0x8
 
@ -55,7 +55,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 
 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
 
-@@ -171,12 +171,6 @@ static void bcm6358_quirks(void)
+@@ -170,12 +170,6 @@ static void bcm6358_quirks(void)
 	 * disable SMP for now
 	 */
 	bmips_smp_enabled = 0;
@ -68,7 +68,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 }
 
 static void bcm6368_quirks(void)
-@@ -209,6 +203,11 @@ static void __init bmips_init_cfe(void)
+@@ -208,6 +202,11 @@ static void __init bmips_init_cfe(void)
 
 void __init prom_init(void)
 {
--- a/target/linux/bmips/patches-6.6/204-mips-bmips-enable-RAC-on-BMIPS4350.patch
+++ b/target/linux/bmips/patches-6.6/204-mips-bmips-enable-RAC-on-BMIPS4350.patch
@ -19,7 +19,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/arch/mips/kernel/smp-bmips.c
 +++ b/arch/mips/kernel/smp-bmips.c
-@@ -615,6 +615,20 @@ void bmips_cpu_setup(void)
+@@ -620,6 +620,20 @@ void bmips_cpu_setup(void)
 		__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 		break;
 
--- a/target/linux/bmips/patches-6.6/210-revert-macronix-nand-block-protection.patch
+++ b/target/linux/bmips/patches-6.6/210-revert-macronix-nand-block-protection.patch
@ -19,7 +19,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/drivers/mtd/nand/raw/nand_macronix.c
 +++ b/drivers/mtd/nand/raw/nand_macronix.c
-@@ -12,10 +12,6 @@
+@@ -13,10 +13,6 @@
 #define MACRONIX_READ_RETRY_BIT BIT(0)
 #define MACRONIX_NUM_READ_RETRY_MODES 6
 
@ -30,7 +30,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 #define ONFI_FEATURE_ADDR_MXIC_RANDOMIZER 0xB0
 #define MACRONIX_RANDOMIZER_BIT BIT(1)
 #define MACRONIX_RANDOMIZER_ENPGM BIT(0)
-@@ -179,73 +175,6 @@ static void macronix_nand_fix_broken_get
+@@ -189,73 +185,6 @@ static void macronix_nand_fix_broken_get
 		     ONFI_FEATURE_ADDR_TIMING_MODE, 1);
 }
 
@ -104,11 +104,11 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 static int nand_power_down_op(struct nand_chip *chip)
 {
 	int ret;
-@@ -323,7 +252,6 @@ static int macronix_nand_init(struct nan
+@@ -488,7 +417,6 @@ static int macronix_nand_init(struct nan
 
 	macronix_nand_fix_broken_get_timings(chip);
 	macronix_nand_onfi_init(chip);
 -	macronix_nand_block_protection_support(chip);
 	macronix_nand_deep_power_down_support(chip);
+ 	macronix_nand_setup_otp(chip);
 
- 	return 0;
--- a/target/linux/bmips/patches-6.6/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch
+++ b/target/linux/bmips/patches-6.6/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch
--- a/target/linux/bmips/patches-6.6/501-net-broadcom-add-BCM6348-enet-controller-driver.patch
+++ b/target/linux/bmips/patches-6.6/501-net-broadcom-add-BCM6348-enet-controller-driver.patch
--- a/target/linux/bmips/patches-6.6/502-net-mdio-mux-bcm6368-allow-disabling.patch
+++ b/target/linux/bmips/patches-6.6/502-net-mdio-mux-bcm6368-allow-disabling.patch
@ -13,7 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/drivers/net/mdio/Kconfig
 +++ b/drivers/net/mdio/Kconfig
-@@ -219,7 +219,6 @@ config MDIO_BUS_MUX_BCM6368
+@@ -244,7 +244,6 @@ config MDIO_BUS_MUX_BCM6368
 	tristate "Broadcom BCM6368 MDIO bus multiplexers"
 	depends on OF && OF_MDIO && (BMIPS_GENERIC || COMPILE_TEST)
 	select MDIO_BUS_MUX
--- a/target/linux/bmips/patches-6.6/600-mips-bmips-add-pci-support.patch
+++ b/target/linux/bmips/patches-6.6/600-mips-bmips-add-pci-support.patch
@ -14,7 +14,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -288,7 +288,6 @@ config BMIPS_GENERIC
+@@ -286,7 +286,6 @@ config BMIPS_GENERIC
 	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
 	select HARDIRQS_SW_RESEND
 	select HAVE_PCI
--- a/target/linux/bmips/patches-6.6/601-pci-controllers-add-bcm6328-pcie-support.patch
+++ b/target/linux/bmips/patches-6.6/601-pci-controllers-add-bcm6328-pcie-support.patch
@ -14,9 +14,9 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/drivers/pci/controller/Kconfig
 +++ b/drivers/pci/controller/Kconfig
-@@ -3,6 +3,11 @@
- menu "PCI controller drivers"
- 	depends on PCI
+@@ -173,6 +173,11 @@ config PCI_LOONGSON
+ 	  Say Y here if you want to enable PCI controller support on
+ 	  Loongson systems.
 
 +config PCIE_BCM6328
 +	bool "BCM6328 PCIe controller"
--- a/target/linux/bmips/patches-6.6/602-pci-controllers-add-bcm6318-pcie-support.patch
+++ b/target/linux/bmips/patches-6.6/602-pci-controllers-add-bcm6318-pcie-support.patch
@ -14,9 +14,9 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/drivers/pci/controller/Kconfig
 +++ b/drivers/pci/controller/Kconfig
-@@ -3,6 +3,11 @@
- menu "PCI controller drivers"
- 	depends on PCI
+@@ -173,6 +173,11 @@ config PCI_LOONGSON
+ 	  Say Y here if you want to enable PCI controller support on
+ 	  Loongson systems.
 
 +config PCIE_BCM6318
 +	bool "BCM6318 PCIe controller"
--- a/target/linux/bmips/patches-6.6/603-pci-controllers-add-bcm6348-pci-support.patch
+++ b/target/linux/bmips/patches-6.6/603-pci-controllers-add-bcm6348-pci-support.patch
@ -14,9 +14,9 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/drivers/pci/controller/Kconfig
 +++ b/drivers/pci/controller/Kconfig
-@@ -3,6 +3,11 @@
- menu "PCI controller drivers"
- 	depends on PCI
+@@ -173,6 +173,11 @@ config PCI_LOONGSON
+ 	  Say Y here if you want to enable PCI controller support on
+ 	  Loongson systems.
 
 +config PCI_BCM6348
 +	bool "BCM6348 PCI controller"
--- a/target/linux/bmips/patches-6.6/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
+++ b/target/linux/bmips/patches-6.6/700-leds-add-support-for-Sercomm-MSP430-LED-controller.patch
@ -17,7 +17,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -283,6 +283,15 @@ config LEDS_COBALT_RAQ
+@@ -299,6 +299,15 @@ config LEDS_COBALT_RAQ
 	help
 	  This option enables support for the Cobalt Raq series LEDs.
 
@ -35,9 +35,9 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
 	depends on LEDS_CLASS
 --- a/drivers/leds/Makefile
 +++ b/drivers/leds/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
+@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_POWERNV)		+= leds-powe
+ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
 obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
 obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
 +obj-$(CONFIG_LEDS_SERCOMM_MSP430)	+= leds-sercomm-msp430.o
 obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o
--- a/target/linux/bmips/patches-6.6/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch
+++ b/target/linux/bmips/patches-6.6/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch
--- a/target/linux/generic/backport-6.1/895-01-v6.8-net-phy-add-possible-interfaces.patch
+++ b/target/linux/generic/backport-6.1/895-01-v6.8-net-phy-add-possible-interfaces.patch
@ -0,0 +1,60 @@
+From 1a7aa058bc92f0edae7a0d1ef1a7b05aec0c643a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:27:52 +0000
+Subject: [PATCH 1/7] net: phy: add possible interfaces
+
+Add a possible_interfaces member to struct phy_device to indicate which
+interfaces a clause 45 PHY may switch between depending on the media.
+This must be populated by the PHY driver by the time the .config_init()
+method completes according to the PHYs host-side configuration.
+
+For example, the Marvell 88x3310 PHY can switch between 10GBASE-R,
+5GBASE-R, 2500BASE-X, and SGMII on the host side depending on the media
+side speed, so all these interface modes are set in the
+possible_interfaces member.
+
+This allows phylib users (such as phylink) to know in advance which
+interface modes to expect, which allows them to appropriately restrict
+the advertised link modes according to the capabilities of other parts
+of the link.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VHk-00DDLN-I7@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phy_device.c | 2 ++
+ include/linux/phy.h          | 3 +++
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
+@@ -1215,6 +1215,8 @@ int phy_init_hw(struct phy_device *phyde
+ 	if (ret < 0)
+ 		return ret;
+ 
+	phy_interface_zero(phydev->possible_interfaces);
+
+ 	if (phydev->drv->config_init) {
+ 		ret = phydev->drv->config_init(phydev);
+ 		if (ret < 0)
+--- a/include/linux/phy.h
+++ b/include/linux/phy.h
+@@ -600,6 +600,8 @@ struct macsec_ops;
+  * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended,
+  *             requiring a rerun of the interrupt handler after resume
+  * @interface: enum phy_interface_t value
+ * @possible_interfaces: bitmap if interface modes that the attached PHY
+ *			 will switch between depending on media speed.
+  * @skb: Netlink message for cable diagnostics
+  * @nest: Netlink nest used for cable diagnostics
+  * @ehdr: nNtlink header for cable diagnostics
+@@ -665,6 +667,7 @@ struct phy_device {
+ 	u32 dev_flags;
+ 
+ 	phy_interface_t interface;
+	DECLARE_PHY_INTERFACE_MASK(possible_interfaces);
+ 
+ 	/*
+ 	 * forced speed & duplex (no autoneg)
--- a/target/linux/generic/backport-6.1/895-02-v6.8-net-phylink-use-for_each_set_bit.patch
+++ b/target/linux/generic/backport-6.1/895-02-v6.8-net-phylink-use-for_each_set_bit.patch
@ -0,0 +1,46 @@
+From 85631f5b33f2acce7d42dec1d0a062ab40de95b8 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sun, 19 Nov 2023 21:07:43 +0000
+Subject: [PATCH 2/7] net: phylink: use for_each_set_bit()
+
+Use for_each_set_bit() rather than open coding the for() test_bit()
+loop.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Wojciech Drewek <wojciech.drewek@intel.com>
+Link: https://lore.kernel.org/r/E1r4p15-00Cpxe-C7@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/phylink.c | 18 ++++++++----------
+ 1 file changed, 8 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -690,18 +690,16 @@ static int phylink_validate_mask(struct
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_s) = { 0, };
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(s);
+ 	struct phylink_link_state t;
+-	int intf;
+	int interface;
+ 
+-	for (intf = 0; intf < PHY_INTERFACE_MODE_MAX; intf++) {
+-		if (test_bit(intf, interfaces)) {
+-			linkmode_copy(s, supported);
+	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX) {
+		linkmode_copy(s, supported);
+ 
+-			t = *state;
+-			t.interface = intf;
+-			if (!phylink_validate_mac_and_pcs(pl, s, &t)) {
+-				linkmode_or(all_s, all_s, s);
+-				linkmode_or(all_adv, all_adv, t.advertising);
+-			}
+		t = *state;
+		t.interface = interface;
+		if (!phylink_validate_mac_and_pcs(pl, s, &t)) {
+			linkmode_or(all_s, all_s, s);
+			linkmode_or(all_adv, all_adv, t.advertising);
+ 		}
+ 	}
+ 
--- a/target/linux/generic/backport-6.1/895-03-v6.8-net-phylink-split-out-per-interface-validation.patch
+++ b/target/linux/generic/backport-6.1/895-03-v6.8-net-phylink-split-out-per-interface-validation.patch
@ -0,0 +1,76 @@
+From d4788b4383ce5caeb4e68818357c81a02117a3f9 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:19 +0000
+Subject: [PATCH 3/7] net: phylink: split out per-interface validation
+
+Split out the internals of phylink_validate_mask() to make the code
+easier to read.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIB-00DDLr-7g@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 42 ++++++++++++++++++++++++++++-----------
+ 1 file changed, 30 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -682,26 +682,44 @@ static int phylink_validate_mac_and_pcs(
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+ 
+static void phylink_validate_one(struct phylink *pl,
+				 const unsigned long *supported,
+				 const struct phylink_link_state *state,
+				 phy_interface_t interface,
+				 unsigned long *accum_supported,
+				 unsigned long *accum_advertising)
+{
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_supported);
+	struct phylink_link_state tmp_state;
+
+	linkmode_copy(tmp_supported, supported);
+
+	tmp_state = *state;
+	tmp_state.interface = interface;
+
+	if (!phylink_validate_mac_and_pcs(pl, tmp_supported, &tmp_state)) {
+		phylink_dbg(pl, " interface %u (%s) rate match %s supports %*pbl\n",
+			    interface, phy_modes(interface),
+			    phy_rate_matching_to_str(tmp_state.rate_matching),
+			    __ETHTOOL_LINK_MODE_MASK_NBITS, tmp_supported);
+
+		linkmode_or(accum_supported, accum_supported, tmp_supported);
+		linkmode_or(accum_advertising, accum_advertising,
+			    tmp_state.advertising);
+	}
+}
+
+ static int phylink_validate_mask(struct phylink *pl, unsigned long *supported,
+ 				 struct phylink_link_state *state,
+ 				 const unsigned long *interfaces)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_adv) = { 0, };
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_s) = { 0, };
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(s);
+-	struct phylink_link_state t;
+ 	int interface;
+ 
+-	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX) {
+-		linkmode_copy(s, supported);
+-
+-		t = *state;
+-		t.interface = interface;
+-		if (!phylink_validate_mac_and_pcs(pl, s, &t)) {
+-			linkmode_or(all_s, all_s, s);
+-			linkmode_or(all_adv, all_adv, t.advertising);
+-		}
+-	}
+	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)
+		phylink_validate_one(pl, supported, state, interface,
+				     all_s, all_adv);
+ 
+ 	linkmode_copy(supported, all_s);
+ 	linkmode_copy(state->advertising, all_adv);
--- a/target/linux/generic/backport-6.1/895-04-v6.8-net-phylink-pass-PHY-into-phylink_validate_one.patch
+++ b/target/linux/generic/backport-6.1/895-04-v6.8-net-phylink-pass-PHY-into-phylink_validate_one.patch
@ -0,0 +1,47 @@
+From ce7273c31fadb3143fc80c96a72a42adc19c2757 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:24 +0000
+Subject: [PATCH 4/7] net: phylink: pass PHY into phylink_validate_one()
+
+Pass the phy (if any) into phylink_validate_one() so that we can
+validate each interface with its rate matching setting.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIG-00DDLx-Cb@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -682,7 +682,7 @@ static int phylink_validate_mac_and_pcs(
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+ 
+-static void phylink_validate_one(struct phylink *pl,
+static void phylink_validate_one(struct phylink *pl, struct phy_device *phy,
+ 				 const unsigned long *supported,
+ 				 const struct phylink_link_state *state,
+ 				 phy_interface_t interface,
+@@ -697,6 +697,9 @@ static void phylink_validate_one(struct
+ 	tmp_state = *state;
+ 	tmp_state.interface = interface;
+ 
+	if (phy)
+		tmp_state.rate_matching = phy_get_rate_matching(phy, interface);
+
+ 	if (!phylink_validate_mac_and_pcs(pl, tmp_supported, &tmp_state)) {
+ 		phylink_dbg(pl, " interface %u (%s) rate match %s supports %*pbl\n",
+ 			    interface, phy_modes(interface),
+@@ -718,7 +721,7 @@ static int phylink_validate_mask(struct
+ 	int interface;
+ 
+ 	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)
+-		phylink_validate_one(pl, supported, state, interface,
+		phylink_validate_one(pl, NULL, supported, state, interface,
+ 				     all_s, all_adv);
+ 
+ 	linkmode_copy(supported, all_s);
--- a/target/linux/generic/backport-6.1/895-05-v6.8-net-phylink-pass-PHY-into-phylink_validate_mask.patch
+++ b/target/linux/generic/backport-6.1/895-05-v6.8-net-phylink-pass-PHY-into-phylink_validate_mask.patch
@ -0,0 +1,58 @@
+From c6fec66d3cd76d797f70b30f1511bed10ba45a96 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:29 +0000
+Subject: [PATCH 5/7] net: phylink: pass PHY into phylink_validate_mask()
+
+Pass the phy (if any) into phylink_validate_mask() so that we can
+validate each interface with its rate matching setting.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIL-00DDM3-HJ@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -712,7 +712,8 @@ static void phylink_validate_one(struct
+ 	}
+ }
+ 
+-static int phylink_validate_mask(struct phylink *pl, unsigned long *supported,
+static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
+				 unsigned long *supported,
+ 				 struct phylink_link_state *state,
+ 				 const unsigned long *interfaces)
+ {
+@@ -721,7 +722,7 @@ static int phylink_validate_mask(struct
+ 	int interface;
+ 
+ 	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)
+-		phylink_validate_one(pl, NULL, supported, state, interface,
+		phylink_validate_one(pl, phy, supported, state, interface,
+ 				     all_s, all_adv);
+ 
+ 	linkmode_copy(supported, all_s);
+@@ -736,7 +737,8 @@ static int phylink_validate(struct phyli
+ 	const unsigned long *interfaces = pl->config->supported_interfaces;
+ 
+ 	if (state->interface == PHY_INTERFACE_MODE_NA)
+-		return phylink_validate_mask(pl, supported, state, interfaces);
+		return phylink_validate_mask(pl, NULL, supported, state,
+					     interfaces);
+ 
+ 	if (!test_bit(state->interface, interfaces))
+ 		return -EINVAL;
+@@ -3132,7 +3134,8 @@ static int phylink_sfp_config_optical(st
+ 	/* For all the interfaces that are supported, reduce the sfp_support
+ 	 * mask to only those link modes that can be supported.
+ 	 */
+-	ret = phylink_validate_mask(pl, pl->sfp_support, &config, interfaces);
+	ret = phylink_validate_mask(pl, NULL, pl->sfp_support, &config,
+				    interfaces);
+ 	if (ret) {
+ 		phylink_err(pl, "unsupported SFP module: validation with support %*pb failed\n",
+ 			    __ETHTOOL_LINK_MODE_MASK_NBITS, support);
--- a/target/linux/generic/backport-6.1/895-06-v6.8-net-phylink-split-out-PHY-validation-from-phylink_br.patch
+++ b/target/linux/generic/backport-6.1/895-06-v6.8-net-phylink-split-out-PHY-validation-from-phylink_br.patch
@ -0,0 +1,95 @@
+From ee0e0ddb910e7e989b65a19d72b6435baa641fc7 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:34 +0000
+Subject: [PATCH 6/7] net: phylink: split out PHY validation from
+ phylink_bringup_phy()
+
+When bringing up a PHY, we need to work out which ethtool link modes it
+should support and advertise. Clause 22 PHYs operate in a single
+interface mode, which can be easily dealt with. However, clause 45 PHYs
+tend to switch interface mode depending on the media. We need more
+flexible validation at this point, so this patch splits out that code
+in preparation to changing it.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIQ-00DDM9-LK@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 56 ++++++++++++++++++++++-----------------
+ 1 file changed, 31 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -1738,6 +1738,35 @@ static void phylink_phy_change(struct ph
+ 		    phylink_pause_to_str(pl->phy_state.pause));
+ }
+ 
+static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
+				unsigned long *supported,
+				struct phylink_link_state *state)
+{
+	/* Check whether we would use rate matching for the proposed interface
+	 * mode.
+	 */
+	state->rate_matching = phy_get_rate_matching(phy, state->interface);
+
+	/* Clause 45 PHYs may switch their Serdes lane between, e.g. 10GBASE-R,
+	 * 5GBASE-R, 2500BASE-X and SGMII if they are not using rate matching.
+	 * For some interface modes (e.g. RXAUI, XAUI and USXGMII) switching
+	 * their Serdes is either unnecessary or not reasonable.
+	 *
+	 * For these which switch interface modes, we really need to know which
+	 * interface modes the PHY supports to properly work out which ethtool
+	 * linkmodes can be supported. For now, as a work-around, we validate
+	 * against all interface modes, which may lead to more ethtool link
+	 * modes being advertised than are actually supported.
+	 */
+	if (phy->is_c45 && state->rate_matching == RATE_MATCH_NONE &&
+	    state->interface != PHY_INTERFACE_MODE_RXAUI &&
+	    state->interface != PHY_INTERFACE_MODE_XAUI &&
+	    state->interface != PHY_INTERFACE_MODE_USXGMII)
+		state->interface = PHY_INTERFACE_MODE_NA;
+
+	return phylink_validate(pl, supported, state);
+}
+
+ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,
+ 			       phy_interface_t interface)
+ {
+@@ -1758,32 +1787,9 @@ static int phylink_bringup_phy(struct ph
+ 	memset(&config, 0, sizeof(config));
+ 	linkmode_copy(supported, phy->supported);
+ 	linkmode_copy(config.advertising, phy->advertising);
+	config.interface = interface;
+ 
+-	/* Check whether we would use rate matching for the proposed interface
+-	 * mode.
+-	 */
+-	config.rate_matching = phy_get_rate_matching(phy, interface);
+-
+-	/* Clause 45 PHYs may switch their Serdes lane between, e.g. 10GBASE-R,
+-	 * 5GBASE-R, 2500BASE-X and SGMII if they are not using rate matching.
+-	 * For some interface modes (e.g. RXAUI, XAUI and USXGMII) switching
+-	 * their Serdes is either unnecessary or not reasonable.
+-	 *
+-	 * For these which switch interface modes, we really need to know which
+-	 * interface modes the PHY supports to properly work out which ethtool
+-	 * linkmodes can be supported. For now, as a work-around, we validate
+-	 * against all interface modes, which may lead to more ethtool link
+-	 * modes being advertised than are actually supported.
+-	 */
+-	if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE &&
+-	    interface != PHY_INTERFACE_MODE_RXAUI &&
+-	    interface != PHY_INTERFACE_MODE_XAUI &&
+-	    interface != PHY_INTERFACE_MODE_USXGMII)
+-		config.interface = PHY_INTERFACE_MODE_NA;
+-	else
+-		config.interface = interface;
+-
+-	ret = phylink_validate(pl, supported, &config);
+	ret = phylink_validate_phy(pl, phy, supported, &config);
+ 	if (ret) {
+ 		phylink_warn(pl, "validation of %s with support %*pb and advertisement %*pb failed: %pe\n",
+ 			     phy_modes(config.interface),
--- a/target/linux/generic/backport-6.1/895-07-v6.8-net-phylink-use-the-PHY-s-possible_interfaces-if-pop.patch
+++ b/target/linux/generic/backport-6.1/895-07-v6.8-net-phylink-use-the-PHY-s-possible_interfaces-if-pop.patch
@ -0,0 +1,130 @@
+From 8f7a9799c5949f94ecc3acfd71b36437a7ade73b Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:39 +0000
+Subject: [PATCH 7/7] net: phylink: use the PHY's possible_interfaces if
+ populated
+
+Some PHYs such as Aquantia, Broadcom 84881, and Marvell 88X33x0 can
+switch between a set of interface types depending on the negotiated
+media speed, or can use rate adaption for some or all of these
+interface types.
+
+We currently assume that these are Clause 45 PHYs that are configured
+not to use a specific set of interface modes, which has worked so far,
+but is just a work-around. In this workaround, we validate using all
+interfaces that the MAC supports, which can lead to extra modes being
+advertised that can not be supported.
+
+To properly address this, switch to using the newly introduced PHY
+possible_interfaces bitmap which indicates which interface modes will
+be used by the PHY as configured. We calculate the union of the PHY's
+possible interfaces and MACs supported interfaces, checking that is
+non-empty. If the PHY is on a SFP, we further reduce the set by those
+which can be used on a SFP module, again checking that is non-empty.
+Finally, we validate the subset of interfaces, taking account of
+whether rate matching will be used for each individual interface mode.
+
+This becomes independent of whether the PHY is clause 22 or clause 45.
+
+It is encouraged that all PHYs that switch interface modes or use
+rate matching should populate phydev->possible_interfaces.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIV-00DDMF-Pi@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 67 +++++++++++++++++++++++++++++++--------
+ 1 file changed, 54 insertions(+), 13 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -121,6 +121,19 @@ do {									\
+ })
+ #endif
+ 
+static const phy_interface_t phylink_sfp_interface_preference[] = {
+	PHY_INTERFACE_MODE_25GBASER,
+	PHY_INTERFACE_MODE_USXGMII,
+	PHY_INTERFACE_MODE_10GBASER,
+	PHY_INTERFACE_MODE_5GBASER,
+	PHY_INTERFACE_MODE_2500BASEX,
+	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_1000BASEX,
+	PHY_INTERFACE_MODE_100BASEX,
+};
+
+static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+
+ /**
+  * phylink_set_port_modes() - set the port type modes in the ethtool mask
+  * @mask: ethtool link mode mask
+@@ -1742,6 +1755,47 @@ static int phylink_validate_phy(struct p
+ 				unsigned long *supported,
+ 				struct phylink_link_state *state)
+ {
+	DECLARE_PHY_INTERFACE_MASK(interfaces);
+
+	/* If the PHY provides a bitmap of the interfaces it will be using
+	 * depending on the negotiated media speeds, use this to validate
+	 * which ethtool link modes can be used.
+	 */
+	if (!phy_interface_empty(phy->possible_interfaces)) {
+		/* We only care about the union of the PHY's interfaces and
+		 * those which the host supports.
+		 */
+		phy_interface_and(interfaces, phy->possible_interfaces,
+				  pl->config->supported_interfaces);
+
+		if (phy_interface_empty(interfaces)) {
+			phylink_err(pl, "PHY has no common interfaces\n");
+			return -EINVAL;
+		}
+
+		if (phy_on_sfp(phy)) {
+			/* If the PHY is on a SFP, limit the interfaces to
+			 * those that can be used with a SFP module.
+			 */
+			phy_interface_and(interfaces, interfaces,
+					  phylink_sfp_interfaces);
+
+			if (phy_interface_empty(interfaces)) {
+				phylink_err(pl, "SFP PHY's possible interfaces becomes empty\n");
+				return -EINVAL;
+			}
+		}
+
+		phylink_dbg(pl, "PHY %s uses interfaces %*pbl, validating %*pbl\n",
+			    phydev_name(phy),
+			    (int)PHY_INTERFACE_MODE_MAX,
+			    phy->possible_interfaces,
+			    (int)PHY_INTERFACE_MODE_MAX, interfaces);
+
+		return phylink_validate_mask(pl, phy, supported, state,
+					     interfaces);
+	}
+
+ 	/* Check whether we would use rate matching for the proposed interface
+ 	 * mode.
+ 	 */
+@@ -2985,19 +3039,6 @@ static void phylink_sfp_detach(void *ups
+ 	pl->netdev->sfp_bus = NULL;
+ }
+ 
+-static const phy_interface_t phylink_sfp_interface_preference[] = {
+-	PHY_INTERFACE_MODE_25GBASER,
+-	PHY_INTERFACE_MODE_USXGMII,
+-	PHY_INTERFACE_MODE_10GBASER,
+-	PHY_INTERFACE_MODE_5GBASER,
+-	PHY_INTERFACE_MODE_2500BASEX,
+-	PHY_INTERFACE_MODE_SGMII,
+-	PHY_INTERFACE_MODE_1000BASEX,
+-	PHY_INTERFACE_MODE_100BASEX,
+-};
+-
+-static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+-
+ static phy_interface_t phylink_choose_sfp_interface(struct phylink *pl,
+ 						    const unsigned long *intf)
+ {
--- a/target/linux/generic/backport-6.1/897-01-v6.9-net-phy-qcom-qca808x-add-helper-for-checking-for-1G-.patch
+++ b/target/linux/generic/backport-6.1/897-01-v6.9-net-phy-qcom-qca808x-add-helper-for-checking-for-1G-.patch
@ -0,0 +1,50 @@
+From f058b2dd70b1a5503dff899010aeb53b436091e5 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 28 Feb 2024 18:24:09 +0100
+Subject: [PATCH 1/2] net: phy: qcom: qca808x: add helper for checking for 1G
+ only model
+
+There are 2 versions of QCA808x, one 2.5G capable and one 1G capable.
+Currently, this matter only in the .get_features call however, it will
+be required for filling supported interface modes so lets add a helper
+that can be reused.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 17 ++++++++++++-----
+ 1 file changed, 12 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
+@@ -156,6 +156,17 @@ static bool qca808x_has_fast_retrain_or_
+ 	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+ }
+ 
+static bool qca808x_is_1g_only(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+	if (ret < 0)
+		return true;
+
+	return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
+}
+
+ static int qca808x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -350,11 +361,7 @@ static int qca808x_get_features(struct p
+ 	 * existed in the bit0 of MMD1.21, we need to remove it manually if
+ 	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
+ 	 */
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+	if (qca808x_is_1g_only(phydev))
+ 		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+ 
+ 	return 0;
--- a/target/linux/generic/backport-6.1/897-02-v6.9-net-phy-qcom-qca808x-fill-in-possible_interfaces.patch
+++ b/target/linux/generic/backport-6.1/897-02-v6.9-net-phy-qcom-qca808x-fill-in-possible_interfaces.patch
@ -0,0 +1,44 @@
+From cb28f702960695e26597c332b0e46776e825cc34 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 28 Feb 2024 18:24:10 +0100
+Subject: [PATCH 2/2] net: phy: qcom: qca808x: fill in possible_interfaces
+
+Currently QCA808x driver does not fill the possible_interfaces.
+2.5G QCA808x support SGMII and 2500Base-X while 1G model only supports
+SGMII, so fill the possible_interfaces accordingly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
+@@ -167,6 +167,16 @@ static bool qca808x_is_1g_only(struct ph
+ 	return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
+ }
+ 
+static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
+{
+	unsigned long *possible = phydev->possible_interfaces;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII, possible);
+
+	if (!qca808x_is_1g_only(phydev))
+		__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
+}
+
+ static int qca808x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -231,6 +241,8 @@ static int qca808x_config_init(struct ph
+ 		}
+ 	}
+ 
+	qca808x_fill_possible_interfaces(phydev);
+
+ 	/* Configure adc threshold as 100mv for the link 10M */
+ 	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
+ 				     QCA808X_ADC_THRESHOLD_MASK,
--- a/target/linux/generic/backport-6.6/310-v6.7-mips-kexec-fix-the-incorrect-ifdeffery-and-dependenc.patch
+++ b/target/linux/generic/backport-6.6/310-v6.7-mips-kexec-fix-the-incorrect-ifdeffery-and-dependenc.patch
@ -0,0 +1,206 @@
+From 8cd2accb71f5eb8e92d775fc1978d3779875c2e5 Mon Sep 17 00:00:00 2001
+From: Baoquan He <bhe@redhat.com>
+Date: Fri, 8 Dec 2023 15:30:34 +0800
+Subject: [PATCH] mips, kexec: fix the incorrect ifdeffery and dependency of
+ CONFIG_KEXEC
+
+The select of KEXEC for CRASH_DUMP in kernel/Kconfig.kexec will be
+dropped, then compiling errors will be triggered if below config items are
+set:
+
+===
+CONFIG_CRASH_CORE=y
+CONFIG_KEXEC_CORE=y
+CONFIG_CRASH_DUMP=y
+===
+
+--------------------------------------------------------------------
+mipsel-linux-ld: kernel/kexec_core.o: in function `kimage_free':
+kernel/kexec_core.c:(.text+0x2200): undefined reference to `machine_kexec_cleanup'
+mipsel-linux-ld: kernel/kexec_core.o: in function `__crash_kexec':
+kernel/kexec_core.c:(.text+0x2480): undefined reference to `machine_crash_shutdown'
+mipsel-linux-ld: kernel/kexec_core.c:(.text+0x2488): undefined reference to `machine_kexec'
+mipsel-linux-ld: kernel/kexec_core.o: in function `kernel_kexec':
+kernel/kexec_core.c:(.text+0x29b8): undefined reference to `machine_shutdown'
+mipsel-linux-ld: kernel/kexec_core.c:(.text+0x29c0): undefined reference to `machine_kexec'
+--------------------------------------------------------------------
+
+Here, change the dependency of building kexec_core related object files,
+and the ifdeffery in mips from CONFIG_KEXEC to CONFIG_KEXEC_CORE.
+
+Link: https://lkml.kernel.org/r/20231208073036.7884-4-bhe@redhat.com
+Signed-off-by: Baoquan He <bhe@redhat.com>
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202311302042.sn8cDPIX-lkp@intel.com/
+Cc: Eric DeVolder <eric_devolder@yahoo.com>
+Cc: Ignat Korchagin <ignat@cloudflare.com>
+Cc: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+---
+ arch/mips/cavium-octeon/smp.c   |  4 ++--
+ arch/mips/include/asm/kexec.h   |  2 +-
+ arch/mips/include/asm/smp-ops.h |  2 +-
+ arch/mips/include/asm/smp.h     |  2 +-
+ arch/mips/kernel/Makefile       |  2 +-
+ arch/mips/kernel/smp-bmips.c    |  4 ++--
+ arch/mips/kernel/smp-cps.c      | 10 +++++-----
+ arch/mips/loongson64/reset.c    |  4 ++--
+ arch/mips/loongson64/smp.c      |  2 +-
+ 9 files changed, 16 insertions(+), 16 deletions(-)
+
+--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
+@@ -422,7 +422,7 @@ static const struct plat_smp_ops octeon_
+ 	.cpu_disable		= octeon_cpu_disable,
+ 	.cpu_die		= octeon_cpu_die,
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	.kexec_nonboot_cpu	= kexec_nonboot_cpu_jump,
+ #endif
+ };
+@@ -502,7 +502,7 @@ static const struct plat_smp_ops octeon_
+ 	.cpu_disable		= octeon_cpu_disable,
+ 	.cpu_die		= octeon_cpu_die,
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	.kexec_nonboot_cpu	= kexec_nonboot_cpu_jump,
+ #endif
+ };
+--- a/arch/mips/include/asm/kexec.h
+++ b/arch/mips/include/asm/kexec.h
+@@ -31,7 +31,7 @@ static inline void crash_setup_regs(stru
+ 		prepare_frametrace(newregs);
+ }
+ 
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ struct kimage;
+ extern unsigned long kexec_args[4];
+ extern int (*_machine_kexec_prepare)(struct kimage *);
+--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
+@@ -35,7 +35,7 @@ struct plat_smp_ops {
+ 	void (*cpu_die)(unsigned int cpu);
+ 	void (*cleanup_dead_cpu)(unsigned cpu);
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	void (*kexec_nonboot_cpu)(void);
+ #endif
+ };
+--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
+@@ -93,7 +93,7 @@ static inline void __cpu_die(unsigned in
+ extern void __noreturn play_dead(void);
+ #endif
+ 
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ static inline void kexec_nonboot_cpu(void)
+ {
+ 	extern const struct plat_smp_ops *mp_ops;	/* private */
+--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
+@@ -90,7 +90,7 @@ obj-$(CONFIG_GPIO_TXX9)		+= gpio_txx9.o
+ 
+ obj-$(CONFIG_RELOCATABLE)	+= relocate.o
+ 
+-obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o crash.o
+obj-$(CONFIG_KEXEC_CORE)	+= machine_kexec.o relocate_kernel.o crash.o
+ obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o
+ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+ obj-$(CONFIG_EARLY_PRINTK_8250)	+= early_printk_8250.o
+--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
+@@ -434,7 +434,7 @@ const struct plat_smp_ops bmips43xx_smp_
+ 	.cpu_disable		= bmips_cpu_disable,
+ 	.cpu_die		= bmips_cpu_die,
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	.kexec_nonboot_cpu	= kexec_nonboot_cpu_jump,
+ #endif
+ };
+@@ -451,7 +451,7 @@ const struct plat_smp_ops bmips5000_smp_
+ 	.cpu_disable		= bmips_cpu_disable,
+ 	.cpu_die		= bmips_cpu_die,
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	.kexec_nonboot_cpu	= kexec_nonboot_cpu_jump,
+ #endif
+ };
+--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
+@@ -392,7 +392,7 @@ static void cps_smp_finish(void)
+ 	local_irq_enable();
+ }
+ 
+-#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
+ 
+ enum cpu_death {
+ 	CPU_DEATH_HALT,
+@@ -429,7 +429,7 @@ static void cps_shutdown_this_cpu(enum c
+ 	}
+ }
+ 
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 
+ static void cps_kexec_nonboot_cpu(void)
+ {
+@@ -439,9 +439,9 @@ static void cps_kexec_nonboot_cpu(void)
+ 		cps_shutdown_this_cpu(CPU_DEATH_POWER);
+ }
+ 
+-#endif /* CONFIG_KEXEC */
+#endif /* CONFIG_KEXEC_CORE */
+ 
+-#endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
+#endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */
+ 
+ #ifdef CONFIG_HOTPLUG_CPU
+ 
+@@ -610,7 +610,7 @@ static const struct plat_smp_ops cps_smp
+ 	.cpu_die		= cps_cpu_die,
+ 	.cleanup_dead_cpu	= cps_cleanup_dead_cpu,
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	.kexec_nonboot_cpu	= cps_kexec_nonboot_cpu,
+ #endif
+ };
+--- a/arch/mips/loongson64/reset.c
+++ b/arch/mips/loongson64/reset.c
+@@ -53,7 +53,7 @@ static void loongson_halt(void)
+ 	}
+ }
+ 
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 
+ /* 0X80000000~0X80200000 is safe */
+ #define MAX_ARGS	64
+@@ -158,7 +158,7 @@ static int __init mips_reboot_setup(void
+ 	_machine_halt = loongson_halt;
+ 	pm_power_off = loongson_poweroff;
+ 
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	kexec_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
+ 	if (WARN_ON(!kexec_argv))
+ 		return -ENOMEM;
+--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
+@@ -864,7 +864,7 @@ const struct plat_smp_ops loongson3_smp_
+ 	.cpu_disable = loongson3_cpu_disable,
+ 	.cpu_die = loongson3_cpu_die,
+ #endif
+-#ifdef CONFIG_KEXEC
+#ifdef CONFIG_KEXEC_CORE
+ 	.kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
+ #endif
+ };
--- a/target/linux/generic/backport-6.6/791-v6.11-01-net-phy-aquantia-move-priv-and-hw-stat-to-header.patch
+++ b/target/linux/generic/backport-6.6/791-v6.11-01-net-phy-aquantia-move-priv-and-hw-stat-to-header.patch
@ -0,0 +1,122 @@
+From c11d5dbbe73fa7b450aaa77bb18df86a9714b422 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 1 Jun 2024 01:35:02 +0200
+Subject: [PATCH 1/2] net: phy: aquantia: move priv and hw stat to header
+
+In preparation for LEDs support, move priv and hw stat to header to
+reference priv struct also in other .c outside aquantia.main
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia.h      | 38 ++++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 37 -----------------------
+ 2 files changed, 38 insertions(+), 37 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia.h
+++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -82,6 +82,18 @@
+ #define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
+ #define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
+ 
+/* MDIO_MMD_C22EXT */
+#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES		0xd292
+#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES		0xd294
+#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER		0xd297
+#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES		0xd313
+#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES		0xd315
+#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER		0xd317
+#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS		0xd318
+#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS	0xd319
+#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
+#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
+
+ #define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
+ #define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
+ 
+@@ -108,6 +120,32 @@
+ #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
+ #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
+ 
+struct aqr107_hw_stat {
+	const char *name;
+	int reg;
+	int size;
+};
+
+#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
+static const struct aqr107_hw_stat aqr107_hw_stats[] = {
+	SGMII_STAT("sgmii_rx_good_frames",	    RX_GOOD_FRAMES,	26),
+	SGMII_STAT("sgmii_rx_bad_frames",	    RX_BAD_FRAMES,	26),
+	SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER,	 8),
+	SGMII_STAT("sgmii_tx_good_frames",	    TX_GOOD_FRAMES,	26),
+	SGMII_STAT("sgmii_tx_bad_frames",	    TX_BAD_FRAMES,	26),
+	SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER,	 8),
+	SGMII_STAT("sgmii_tx_collisions",	    TX_COLLISIONS,	 8),
+	SGMII_STAT("sgmii_tx_line_collisions",	    TX_LINE_COLLISIONS,	 8),
+	SGMII_STAT("sgmii_tx_frame_alignment_err",  TX_FRAME_ALIGN_ERR,	16),
+	SGMII_STAT("sgmii_tx_runt_frames",	    TX_RUNT_FRAMES,	22),
+};
+
+#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
+
+struct aqr107_priv {
+	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+};
+
+ #if IS_REACHABLE(CONFIG_HWMON)
+ int aqr_hwmon_probe(struct phy_device *phydev);
+ #else
+--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -84,49 +84,12 @@
+ #define MDIO_AN_RX_VEND_STAT3			0xe832
+ #define MDIO_AN_RX_VEND_STAT3_AFR		BIT(0)
+ 
+-/* MDIO_MMD_C22EXT */
+-#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES		0xd292
+-#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES		0xd294
+-#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER		0xd297
+-#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES		0xd313
+-#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES		0xd315
+-#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER		0xd317
+-#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS		0xd318
+-#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS	0xd319
+-#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
+-#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
+-
+ /* Sleep and timeout for checking if the Processor-Intensive
+  * MDIO operation is finished
+  */
+ #define AQR107_OP_IN_PROG_SLEEP		1000
+ #define AQR107_OP_IN_PROG_TIMEOUT	100000
+ 
+-struct aqr107_hw_stat {
+-	const char *name;
+-	int reg;
+-	int size;
+-};
+-
+-#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
+-static const struct aqr107_hw_stat aqr107_hw_stats[] = {
+-	SGMII_STAT("sgmii_rx_good_frames",	    RX_GOOD_FRAMES,	26),
+-	SGMII_STAT("sgmii_rx_bad_frames",	    RX_BAD_FRAMES,	26),
+-	SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER,	 8),
+-	SGMII_STAT("sgmii_tx_good_frames",	    TX_GOOD_FRAMES,	26),
+-	SGMII_STAT("sgmii_tx_bad_frames",	    TX_BAD_FRAMES,	26),
+-	SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER,	 8),
+-	SGMII_STAT("sgmii_tx_collisions",	    TX_COLLISIONS,	 8),
+-	SGMII_STAT("sgmii_tx_line_collisions",	    TX_LINE_COLLISIONS,	 8),
+-	SGMII_STAT("sgmii_tx_frame_alignment_err",  TX_FRAME_ALIGN_ERR,	16),
+-	SGMII_STAT("sgmii_tx_runt_frames",	    TX_RUNT_FRAMES,	22),
+-};
+-#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
+-
+-struct aqr107_priv {
+-	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+-};
+-
+ static int aqr107_get_sset_count(struct phy_device *phydev)
+ {
+ 	return AQR107_SGMII_STAT_SZ;
--- a/target/linux/generic/backport-6.6/791-v6.11-02-net-phy-aquantia-add-support-for-PHY-LEDs.patch
+++ b/target/linux/generic/backport-6.6/791-v6.11-02-net-phy-aquantia-add-support-for-PHY-LEDs.patch
@ -1,7 +1,7 @@
-From c6a1759365fc35463138a7d9e335ee53f384b8df Mon Sep 17 00:00:00 2001
+From 61578f67937881abf54c8bd258eb913312dbe4c1 Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 10 May 2024 02:53:52 +0100
-Subject: [PATCH] net: phy: aquantia: add support for PHY LEDs
+Date: Sat, 1 Jun 2024 01:35:03 +0200
+Subject: [PATCH 2/2] net: phy: aquantia: add support for PHY LEDs

 Aquantia Ethernet PHYs got 3 LED output pins which are typically used
 to indicate link status and activity.
@ -10,80 +10,97 @@ with the 'netdev' trigger as well as software-driven forced control of
 the LEDs.

 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+[ rework indentation, fix checkpatch error and improve some functions ]
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
- drivers/net/phy/aquantia/Makefile        |   3 +
- drivers/net/phy/aquantia/aquantia.h      |  84 +++++++++++++
- drivers/net/phy/aquantia/aquantia_leds.c | 152 +++++++++++++++++++++++
- drivers/net/phy/aquantia/aquantia_main.c | 127 +++++++++++++------
- 4 files changed, 329 insertions(+), 37 deletions(-)
+ drivers/net/phy/aquantia/Makefile        |   2 +-
+ drivers/net/phy/aquantia/aquantia.h      |  40 ++++++
+ drivers/net/phy/aquantia/aquantia_leds.c | 150 +++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c |  63 +++++++++-
+ 4 files changed, 252 insertions(+), 3 deletions(-)
 create mode 100644 drivers/net/phy/aquantia/aquantia_leds.c

 --- a/drivers/net/phy/aquantia/Makefile
 +++ b/drivers/net/phy/aquantia/Makefile
-@@ -3,4 +3,7 @@ aquantia-objs			+= aquantia_main.o aquan
+@@ -1,5 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
+-aquantia-objs			+= aquantia_main.o aquantia_firmware.o
+aquantia-objs			+= aquantia_main.o aquantia_firmware.o aquantia_leds.o
 ifdef CONFIG_HWMON
 aquantia-objs			+= aquantia_hwmon.o
 endif
-+ifdef CONFIG_PHYLIB_LEDS
-+aquantia-objs			+= aquantia_leds.o
-+endif
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o
 --- a/drivers/net/phy/aquantia/aquantia.h
 +++ b/drivers/net/phy/aquantia/aquantia.h
-@@ -62,6 +62,26 @@
- #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
- #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
- #define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
-+
-+#define AQR_NUM_LEDS				3
-+
+@@ -58,6 +58,28 @@
+ #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD	BIT(6)
+ #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL	BIT(0)
+ 
 +#define VEND1_GLOBAL_LED_PROV			0xc430
-+#define AQR_LED_PROV(x)				(VEND1_GLOBAL_LED_PROV + x)
-+#define VEND1_GLOBAL_LED_PROV_ACT_STRETCH	GENMASK(0, 1)
-+#define VEND1_GLOBAL_LED_PROV_TX_ACT		BIT(2)
-+#define VEND1_GLOBAL_LED_PROV_RX_ACT		BIT(3)
-+#define VEND1_GLOBAL_LED_PROV_LINK_MASK		(GENMASK(15, 14) | GENMASK(8, 5))
-+#define VEND1_GLOBAL_LED_PROV_LINK100		BIT(5)
-+#define VEND1_GLOBAL_LED_PROV_LINK1000		BIT(6)
-+#define VEND1_GLOBAL_LED_PROV_LINK10000		BIT(7)
-+#define VEND1_GLOBAL_LED_PROV_FORCE_ON		BIT(8)
+#define AQR_LED_PROV(x)				(VEND1_GLOBAL_LED_PROV + (x))
 +#define VEND1_GLOBAL_LED_PROV_LINK2500		BIT(14)
 +#define VEND1_GLOBAL_LED_PROV_LINK5000		BIT(15)
+#define VEND1_GLOBAL_LED_PROV_FORCE_ON		BIT(8)
+#define VEND1_GLOBAL_LED_PROV_LINK10000		BIT(7)
+#define VEND1_GLOBAL_LED_PROV_LINK1000		BIT(6)
+#define VEND1_GLOBAL_LED_PROV_LINK100		BIT(5)
+#define VEND1_GLOBAL_LED_PROV_RX_ACT		BIT(3)
+#define VEND1_GLOBAL_LED_PROV_TX_ACT		BIT(2)
+#define VEND1_GLOBAL_LED_PROV_ACT_STRETCH	GENMASK(0, 1)
+
+#define VEND1_GLOBAL_LED_PROV_LINK_MASK		(VEND1_GLOBAL_LED_PROV_LINK100 | \
+						 VEND1_GLOBAL_LED_PROV_LINK1000 | \
+						 VEND1_GLOBAL_LED_PROV_LINK10000 | \
+						 VEND1_GLOBAL_LED_PROV_LINK5000 | \
+						 VEND1_GLOBAL_LED_PROV_LINK2500)
 +
 +#define VEND1_GLOBAL_LED_DRIVE			0xc438
 +#define VEND1_GLOBAL_LED_DRIVE_VDD		BIT(1)
-+#define AQR_LED_DRIVE(x)			(VEND1_GLOBAL_LED_DRIVE + x)
+#define AQR_LED_DRIVE(x)			(VEND1_GLOBAL_LED_DRIVE + (x))
 +
- #define VEND1_THERMAL_STAT1			0xc820
- #define VEND1_THERMAL_STAT2			0xc821
- #define VEND1_THERMAL_STAT2_VALID		BIT(0)
-@@ -115,3 +135,23 @@ static inline int aqr_hwmon_probe(struct
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
+ #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
+@@ -120,6 +142,8 @@
+ #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
+ #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
+ 
+#define AQR_MAX_LEDS				3
+
+ struct aqr107_hw_stat {
+ 	const char *name;
+ 	int reg;
+@@ -144,6 +168,7 @@ static const struct aqr107_hw_stat aqr10
+ 
+ struct aqr107_priv {
+ 	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+	unsigned long leds_active_low;
+ };
+ 
+ #if IS_REACHABLE(CONFIG_HWMON)
+@@ -153,3 +178,18 @@ static inline int aqr_hwmon_probe(struct
 #endif
 
 int aqr_firmware_load(struct phy_device *phydev);
 +
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index,
-+			 unsigned long *delay_on,
-+			 unsigned long *delay_off);
-+
+			  unsigned long *delay_on,
+			  unsigned long *delay_off);
 +int aqr_phy_led_brightness_set(struct phy_device *phydev,
 +			       u8 index, enum led_brightness value);
-+
 +int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
 +				unsigned long rules);
-+
 +int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
 +			       unsigned long *rules);
-+
 +int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
 +			       unsigned long rules);
-+
-+int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes);
-+#endif
+int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable);
+int aqr_phy_led_polarity_set(struct phy_device *phydev, int index,
+			     unsigned long modes);
 --- /dev/null
 +++ b/drivers/net/phy/aquantia/aquantia_leds.c
-@@ -0,0 +1,140 @@
+@@ -0,0 +1,150 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/* LED driver for Aquantia PHY
 + *
@ -97,29 +114,30 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +int aqr_phy_led_brightness_set(struct phy_device *phydev,
 +			       u8 index, enum led_brightness value)
 +{
-+	if (index > 2)
+	if (index >= AQR_MAX_LEDS)
 +		return -EINVAL;
 +
-+	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), VEND1_GLOBAL_LED_PROV_LINK_MASK |
-+						    VEND1_GLOBAL_LED_PROV_FORCE_ON |
-+						    VEND1_GLOBAL_LED_PROV_RX_ACT |
-+						    VEND1_GLOBAL_LED_PROV_TX_ACT,
-+						    value ? VEND1_GLOBAL_LED_PROV_FORCE_ON : 0);
+	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
+			      VEND1_GLOBAL_LED_PROV_LINK_MASK |
+			      VEND1_GLOBAL_LED_PROV_FORCE_ON |
+			      VEND1_GLOBAL_LED_PROV_RX_ACT |
+			      VEND1_GLOBAL_LED_PROV_TX_ACT,
+			      value ? VEND1_GLOBAL_LED_PROV_FORCE_ON : 0);
 +}
 +
-+static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK)        |
-+						 BIT(TRIGGER_NETDEV_LINK_100)    |
-+						 BIT(TRIGGER_NETDEV_LINK_1000)   |
-+						 BIT(TRIGGER_NETDEV_LINK_2500)   |
-+						 BIT(TRIGGER_NETDEV_LINK_5000)   |
+static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
+						 BIT(TRIGGER_NETDEV_LINK_100) |
+						 BIT(TRIGGER_NETDEV_LINK_1000) |
+						 BIT(TRIGGER_NETDEV_LINK_2500) |
+						 BIT(TRIGGER_NETDEV_LINK_5000) |
 +						 BIT(TRIGGER_NETDEV_LINK_10000)  |
-+						 BIT(TRIGGER_NETDEV_RX)          |
+						 BIT(TRIGGER_NETDEV_RX) |
 +						 BIT(TRIGGER_NETDEV_TX));
 +
 +int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
 +				unsigned long rules)
 +{
-+	if (index >= AQR_NUM_LEDS)
+	if (index >= AQR_MAX_LEDS)
 +		return -EINVAL;
 +
 +	/* All combinations of the supported triggers are allowed */
@ -134,7 +152,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +{
 +	int val;
 +
-+	if (index >= AQR_NUM_LEDS)
+	if (index >= AQR_MAX_LEDS)
 +		return -EINVAL;
 +
 +	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index));
@ -171,7 +189,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +{
 +	u16 val = 0;
 +
-+	if (index >= AQR_NUM_LEDS)
+	if (index >= AQR_MAX_LEDS)
 +		return -EINVAL;
 +
 +	if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
@ -196,18 +214,25 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		val |= VEND1_GLOBAL_LED_PROV_TX_ACT;
 +
 +	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
-+						    VEND1_GLOBAL_LED_PROV_LINK_MASK |
-+						    VEND1_GLOBAL_LED_PROV_FORCE_ON |
-+						    VEND1_GLOBAL_LED_PROV_RX_ACT |
-+						    VEND1_GLOBAL_LED_PROV_TX_ACT, val);
+			      VEND1_GLOBAL_LED_PROV_LINK_MASK |
+			      VEND1_GLOBAL_LED_PROV_FORCE_ON |
+			      VEND1_GLOBAL_LED_PROV_RX_ACT |
+			      VEND1_GLOBAL_LED_PROV_TX_ACT, val);
+}
+
+int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable)
+{
+	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
+			      VEND1_GLOBAL_LED_DRIVE_VDD, enable);
 +}
 +
 +int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes)
 +{
+	struct aqr107_priv *priv = phydev->priv;
 +	bool active_low = false;
 +	u32 mode;
 +
-+	if (index >= AQR_NUM_LEDS)
+	if (index >= AQR_MAX_LEDS)
 +		return -EINVAL;
 +
 +	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
@ -216,153 +241,155 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +			active_low = true;
 +			break;
 +		default:
-+		return -EINVAL;
+			return -EINVAL;
 +		}
 +	}
 +
-+	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
-+			      VEND1_GLOBAL_LED_DRIVE_VDD,
-+			      active_low ? VEND1_GLOBAL_LED_DRIVE_VDD : 0);
+	/* Save LED driver vdd state to restore on SW reset */
+	if (active_low)
+		priv->leds_active_low |= BIT(index);
+
+	return aqr_phy_led_active_low_set(phydev, index, active_low);
 +}
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -740,6 +740,13 @@ static struct phy_driver aqr_driver[] =
+@@ -475,7 +475,9 @@ static void aqr107_chip_info(struct phy_
+ 
+ static int aqr107_config_init(struct phy_device *phydev)
+ {
+-	int ret;
+	struct aqr107_priv *priv = phydev->priv;
+	u32 led_active_low;
+	int ret, index = 0;
+ 
+ 	/* Check that the PHY interface type is compatible */
+ 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+@@ -496,7 +498,19 @@ static int aqr107_config_init(struct phy
+ 	if (!ret)
+ 		aqr107_chip_info(phydev);
+ 
+-	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+	ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+	if (ret)
+		return ret;
+
+	/* Restore LED polarity state after reset */
+	for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) {
+		ret = aqr_phy_led_active_low_set(phydev, index, led_active_low);
+		if (ret)
+			return ret;
+		index++;
+	}
+
+	return 0;
+ }
+ 
+ static int aqcs109_config_init(struct phy_device *phydev)
+@@ -703,6 +717,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings	= aqr107_get_strings,
 	.get_stats	= aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
-@@ -759,6 +766,13 @@ static struct phy_driver aqr_driver[] =
+@@ -722,6 +741,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings	= aqr107_get_strings,
 	.get_stats	= aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
-@@ -778,6 +792,13 @@ static struct phy_driver aqr_driver[] =
+@@ -741,6 +765,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings	= aqr107_get_strings,
 	.get_stats	= aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
-@@ -797,6 +818,13 @@ static struct phy_driver aqr_driver[] =
+@@ -760,6 +789,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings	= aqr107_get_strings,
 	.get_stats	= aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
-@@ -823,6 +851,13 @@ static struct phy_driver aqr_driver[] =
+@@ -786,6 +820,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings	= aqr107_get_strings,
 	.get_stats	= aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
-@@ -841,6 +876,13 @@ static struct phy_driver aqr_driver[] =
- 	.get_strings	= aqr107_get_strings,
- 	.get_stats	= aqr107_get_stats,
- 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
-+	.led_brightness_set = aqr_phy_led_brightness_set,
-+	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
-+	.led_hw_control_set = aqr_phy_led_hw_control_set,
-+	.led_hw_control_get = aqr_phy_led_hw_control_get,
-+	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
- },
- {
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
-@@ -860,6 +902,13 @@ static struct phy_driver aqr_driver[] =
+@@ -823,6 +862,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings    = aqr107_get_strings,
 	.get_stats      = aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
-@@ -879,6 +928,13 @@ static struct phy_driver aqr_driver[] =
+@@ -842,6 +886,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings    = aqr107_get_strings,
 	.get_stats      = aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
-@@ -898,6 +954,13 @@ static struct phy_driver aqr_driver[] =
+@@ -861,6 +910,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings    = aqr107_get_strings,
 	.get_stats      = aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 {
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
-@@ -917,6 +980,13 @@ static struct phy_driver aqr_driver[] =
+@@ -880,6 +934,11 @@ static struct phy_driver aqr_driver[] =
 	.get_strings	= aqr107_get_strings,
 	.get_stats	= aqr107_get_stats,
 	.link_change_notify = aqr107_link_change_notify,
-+#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
 +	.led_brightness_set = aqr_phy_led_brightness_set,
 +	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
 +	.led_hw_control_set = aqr_phy_led_hw_control_set,
 +	.led_hw_control_get = aqr_phy_led_hw_control_get,
 +	.led_polarity_set = aqr_phy_led_polarity_set,
-+#endif
 },
 };
 
--- a/target/linux/generic/backport-6.6/810-v6.11-hwmon-g672-add-support-for-g761.patch
+++ b/target/linux/generic/backport-6.6/810-v6.11-hwmon-g672-add-support-for-g761.patch
@ -0,0 +1,106 @@
+From 6ce402327a6fb714a9f40a0bb59bcbfe383839a5 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 4 Jun 2024 18:43:43 +0200
+Subject: [PATCH] hwmon: g672: add support for g761
+
+Add support for g761 PWM Fan Controller.
+
+The g761 is a copy of the g763 with the only difference of supporting
+and internal clock. The internal clock is used if no clocks property is
+defined in device node and in such case the required bit is enabled and
+clock handling is skipped.
+
+The internal clock oscillator runs at 31KHz.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20240604164348.542-3-ansuelsmth@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+---
+ drivers/hwmon/g762.c | 33 ++++++++++++++++++++++++++++++---
+ 1 file changed, 30 insertions(+), 3 deletions(-)
+
+--- a/drivers/hwmon/g762.c
+++ b/drivers/hwmon/g762.c
+@@ -69,6 +69,7 @@ enum g762_regs {
+ #define G762_REG_FAN_CMD1_PWM_POLARITY  0x02 /* PWM polarity */
+ #define G762_REG_FAN_CMD1_PULSE_PER_REV 0x01 /* pulse per fan revolution */
+ 
+#define G761_REG_FAN_CMD2_FAN_CLOCK     0x20 /* choose internal clock*/
+ #define G762_REG_FAN_CMD2_GEAR_MODE_1   0x08 /* fan gear mode */
+ #define G762_REG_FAN_CMD2_GEAR_MODE_0   0x04
+ #define G762_REG_FAN_CMD2_FAN_STARTV_1  0x02 /* fan startup voltage */
+@@ -115,6 +116,7 @@ enum g762_regs {
+ 
+ struct g762_data {
+ 	struct i2c_client *client;
+	bool internal_clock;
+ 	struct clk *clk;
+ 
+ 	/* update mutex */
+@@ -566,6 +568,7 @@ static int do_set_fan_startv(struct devi
+ 
+ #ifdef CONFIG_OF
+ static const struct of_device_id g762_dt_match[] = {
+	{ .compatible = "gmt,g761" },
+ 	{ .compatible = "gmt,g762" },
+ 	{ .compatible = "gmt,g763" },
+ 	{ },
+@@ -597,6 +600,21 @@ static int g762_of_clock_enable(struct i
+ 	if (!client->dev.of_node)
+ 		return 0;
+ 
+	data = i2c_get_clientdata(client);
+
+	/*
+	 * Skip CLK detection and handling if we use internal clock.
+	 * This is only valid for g761.
+	 */
+	data->internal_clock = of_device_is_compatible(client->dev.of_node,
+						       "gmt,g761") &&
+			       !of_property_present(client->dev.of_node,
+						    "clocks");
+	if (data->internal_clock) {
+		do_set_clk_freq(&client->dev, 32768);
+		return 0;
+	}
+
+ 	clk = of_clk_get(client->dev.of_node, 0);
+ 	if (IS_ERR(clk)) {
+ 		dev_err(&client->dev, "failed to get clock\n");
+@@ -616,7 +634,6 @@ static int g762_of_clock_enable(struct i
+ 		goto clk_unprep;
+ 	}
+ 
+-	data = i2c_get_clientdata(client);
+ 	data->clk = clk;
+ 
+ 	ret = devm_add_action(&client->dev, g762_of_clock_disable, data);
+@@ -1025,16 +1042,26 @@ ATTRIBUTE_GROUPS(g762);
+ static inline int g762_fan_init(struct device *dev)
+ {
+ 	struct g762_data *data = g762_update_client(dev);
+	int ret;
+ 
+ 	if (IS_ERR(data))
+ 		return PTR_ERR(data);
+ 
+	/* internal_clock can only be set with compatible g761 */
+	if (data->internal_clock)
+		data->fan_cmd2 |= G761_REG_FAN_CMD2_FAN_CLOCK;
+
+ 	data->fan_cmd1 |= G762_REG_FAN_CMD1_DET_FAN_FAIL;
+ 	data->fan_cmd1 |= G762_REG_FAN_CMD1_DET_FAN_OOC;
+ 	data->valid = false;
+ 
+-	return i2c_smbus_write_byte_data(data->client, G762_REG_FAN_CMD1,
+-					 data->fan_cmd1);
+	ret = i2c_smbus_write_byte_data(data->client, G762_REG_FAN_CMD1,
+					data->fan_cmd1);
+	if (ret)
+		return ret;
+
+	return i2c_smbus_write_byte_data(data->client, G762_REG_FAN_CMD2,
+					 data->fan_cmd2);
+ }
+ 
+ static int g762_probe(struct i2c_client *client)
--- a/target/linux/generic/backport-6.6/895-01-v6.8-net-phy-add-possible-interfaces.patch
+++ b/target/linux/generic/backport-6.6/895-01-v6.8-net-phy-add-possible-interfaces.patch
@ -0,0 +1,60 @@
+From 1a7aa058bc92f0edae7a0d1ef1a7b05aec0c643a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:27:52 +0000
+Subject: [PATCH 1/7] net: phy: add possible interfaces
+
+Add a possible_interfaces member to struct phy_device to indicate which
+interfaces a clause 45 PHY may switch between depending on the media.
+This must be populated by the PHY driver by the time the .config_init()
+method completes according to the PHYs host-side configuration.
+
+For example, the Marvell 88x3310 PHY can switch between 10GBASE-R,
+5GBASE-R, 2500BASE-X, and SGMII on the host side depending on the media
+side speed, so all these interface modes are set in the
+possible_interfaces member.
+
+This allows phylib users (such as phylink) to know in advance which
+interface modes to expect, which allows them to appropriately restrict
+the advertised link modes according to the capabilities of other parts
+of the link.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VHk-00DDLN-I7@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phy_device.c | 2 ++
+ include/linux/phy.h          | 3 +++
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
+@@ -1247,6 +1247,8 @@ int phy_init_hw(struct phy_device *phyde
+ 	if (ret < 0)
+ 		return ret;
+ 
+	phy_interface_zero(phydev->possible_interfaces);
+
+ 	if (phydev->drv->config_init) {
+ 		ret = phydev->drv->config_init(phydev);
+ 		if (ret < 0)
+--- a/include/linux/phy.h
+++ b/include/linux/phy.h
+@@ -609,6 +609,8 @@ struct macsec_ops;
+  * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended,
+  *             requiring a rerun of the interrupt handler after resume
+  * @interface: enum phy_interface_t value
+ * @possible_interfaces: bitmap if interface modes that the attached PHY
+ *			 will switch between depending on media speed.
+  * @skb: Netlink message for cable diagnostics
+  * @nest: Netlink nest used for cable diagnostics
+  * @ehdr: nNtlink header for cable diagnostics
+@@ -678,6 +680,7 @@ struct phy_device {
+ 	u32 dev_flags;
+ 
+ 	phy_interface_t interface;
+	DECLARE_PHY_INTERFACE_MASK(possible_interfaces);
+ 
+ 	/*
+ 	 * forced speed & duplex (no autoneg)
--- a/target/linux/generic/backport-6.6/895-02-v6.8-net-phylink-use-for_each_set_bit.patch
+++ b/target/linux/generic/backport-6.6/895-02-v6.8-net-phylink-use-for_each_set_bit.patch
@ -0,0 +1,46 @@
+From 85631f5b33f2acce7d42dec1d0a062ab40de95b8 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sun, 19 Nov 2023 21:07:43 +0000
+Subject: [PATCH 2/7] net: phylink: use for_each_set_bit()
+
+Use for_each_set_bit() rather than open coding the for() test_bit()
+loop.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Wojciech Drewek <wojciech.drewek@intel.com>
+Link: https://lore.kernel.org/r/E1r4p15-00Cpxe-C7@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/phylink.c | 18 ++++++++----------
+ 1 file changed, 8 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -712,18 +712,16 @@ static int phylink_validate_mask(struct
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_s) = { 0, };
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(s);
+ 	struct phylink_link_state t;
+-	int intf;
+	int interface;
+ 
+-	for (intf = 0; intf < PHY_INTERFACE_MODE_MAX; intf++) {
+-		if (test_bit(intf, interfaces)) {
+-			linkmode_copy(s, supported);
+	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX) {
+		linkmode_copy(s, supported);
+ 
+-			t = *state;
+-			t.interface = intf;
+-			if (!phylink_validate_mac_and_pcs(pl, s, &t)) {
+-				linkmode_or(all_s, all_s, s);
+-				linkmode_or(all_adv, all_adv, t.advertising);
+-			}
+		t = *state;
+		t.interface = interface;
+		if (!phylink_validate_mac_and_pcs(pl, s, &t)) {
+			linkmode_or(all_s, all_s, s);
+			linkmode_or(all_adv, all_adv, t.advertising);
+ 		}
+ 	}
+ 
--- a/target/linux/generic/backport-6.6/895-03-v6.8-net-phylink-split-out-per-interface-validation.patch
+++ b/target/linux/generic/backport-6.6/895-03-v6.8-net-phylink-split-out-per-interface-validation.patch
@ -0,0 +1,76 @@
+From d4788b4383ce5caeb4e68818357c81a02117a3f9 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:19 +0000
+Subject: [PATCH 3/7] net: phylink: split out per-interface validation
+
+Split out the internals of phylink_validate_mask() to make the code
+easier to read.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIB-00DDLr-7g@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 42 ++++++++++++++++++++++++++++-----------
+ 1 file changed, 30 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -704,26 +704,44 @@ static int phylink_validate_mac_and_pcs(
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+ 
+static void phylink_validate_one(struct phylink *pl,
+				 const unsigned long *supported,
+				 const struct phylink_link_state *state,
+				 phy_interface_t interface,
+				 unsigned long *accum_supported,
+				 unsigned long *accum_advertising)
+{
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_supported);
+	struct phylink_link_state tmp_state;
+
+	linkmode_copy(tmp_supported, supported);
+
+	tmp_state = *state;
+	tmp_state.interface = interface;
+
+	if (!phylink_validate_mac_and_pcs(pl, tmp_supported, &tmp_state)) {
+		phylink_dbg(pl, " interface %u (%s) rate match %s supports %*pbl\n",
+			    interface, phy_modes(interface),
+			    phy_rate_matching_to_str(tmp_state.rate_matching),
+			    __ETHTOOL_LINK_MODE_MASK_NBITS, tmp_supported);
+
+		linkmode_or(accum_supported, accum_supported, tmp_supported);
+		linkmode_or(accum_advertising, accum_advertising,
+			    tmp_state.advertising);
+	}
+}
+
+ static int phylink_validate_mask(struct phylink *pl, unsigned long *supported,
+ 				 struct phylink_link_state *state,
+ 				 const unsigned long *interfaces)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_adv) = { 0, };
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_s) = { 0, };
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(s);
+-	struct phylink_link_state t;
+ 	int interface;
+ 
+-	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX) {
+-		linkmode_copy(s, supported);
+-
+-		t = *state;
+-		t.interface = interface;
+-		if (!phylink_validate_mac_and_pcs(pl, s, &t)) {
+-			linkmode_or(all_s, all_s, s);
+-			linkmode_or(all_adv, all_adv, t.advertising);
+-		}
+-	}
+	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)
+		phylink_validate_one(pl, supported, state, interface,
+				     all_s, all_adv);
+ 
+ 	linkmode_copy(supported, all_s);
+ 	linkmode_copy(state->advertising, all_adv);
--- a/target/linux/generic/backport-6.6/895-04-v6.8-net-phylink-pass-PHY-into-phylink_validate_one.patch
+++ b/target/linux/generic/backport-6.6/895-04-v6.8-net-phylink-pass-PHY-into-phylink_validate_one.patch
@ -0,0 +1,47 @@
+From ce7273c31fadb3143fc80c96a72a42adc19c2757 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:24 +0000
+Subject: [PATCH 4/7] net: phylink: pass PHY into phylink_validate_one()
+
+Pass the phy (if any) into phylink_validate_one() so that we can
+validate each interface with its rate matching setting.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIG-00DDLx-Cb@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -704,7 +704,7 @@ static int phylink_validate_mac_and_pcs(
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+ 
+-static void phylink_validate_one(struct phylink *pl,
+static void phylink_validate_one(struct phylink *pl, struct phy_device *phy,
+ 				 const unsigned long *supported,
+ 				 const struct phylink_link_state *state,
+ 				 phy_interface_t interface,
+@@ -719,6 +719,9 @@ static void phylink_validate_one(struct
+ 	tmp_state = *state;
+ 	tmp_state.interface = interface;
+ 
+	if (phy)
+		tmp_state.rate_matching = phy_get_rate_matching(phy, interface);
+
+ 	if (!phylink_validate_mac_and_pcs(pl, tmp_supported, &tmp_state)) {
+ 		phylink_dbg(pl, " interface %u (%s) rate match %s supports %*pbl\n",
+ 			    interface, phy_modes(interface),
+@@ -740,7 +743,7 @@ static int phylink_validate_mask(struct
+ 	int interface;
+ 
+ 	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)
+-		phylink_validate_one(pl, supported, state, interface,
+		phylink_validate_one(pl, NULL, supported, state, interface,
+ 				     all_s, all_adv);
+ 
+ 	linkmode_copy(supported, all_s);
--- a/target/linux/generic/backport-6.6/895-05-v6.8-net-phylink-pass-PHY-into-phylink_validate_mask.patch
+++ b/target/linux/generic/backport-6.6/895-05-v6.8-net-phylink-pass-PHY-into-phylink_validate_mask.patch
@ -0,0 +1,58 @@
+From c6fec66d3cd76d797f70b30f1511bed10ba45a96 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:29 +0000
+Subject: [PATCH 5/7] net: phylink: pass PHY into phylink_validate_mask()
+
+Pass the phy (if any) into phylink_validate_mask() so that we can
+validate each interface with its rate matching setting.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIL-00DDM3-HJ@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -734,7 +734,8 @@ static void phylink_validate_one(struct
+ 	}
+ }
+ 
+-static int phylink_validate_mask(struct phylink *pl, unsigned long *supported,
+static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
+				 unsigned long *supported,
+ 				 struct phylink_link_state *state,
+ 				 const unsigned long *interfaces)
+ {
+@@ -743,7 +744,7 @@ static int phylink_validate_mask(struct
+ 	int interface;
+ 
+ 	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)
+-		phylink_validate_one(pl, NULL, supported, state, interface,
+		phylink_validate_one(pl, phy, supported, state, interface,
+ 				     all_s, all_adv);
+ 
+ 	linkmode_copy(supported, all_s);
+@@ -758,7 +759,8 @@ static int phylink_validate(struct phyli
+ 	const unsigned long *interfaces = pl->config->supported_interfaces;
+ 
+ 	if (state->interface == PHY_INTERFACE_MODE_NA)
+-		return phylink_validate_mask(pl, supported, state, interfaces);
+		return phylink_validate_mask(pl, NULL, supported, state,
+					     interfaces);
+ 
+ 	if (!test_bit(state->interface, interfaces))
+ 		return -EINVAL;
+@@ -3194,7 +3196,8 @@ static int phylink_sfp_config_optical(st
+ 	/* For all the interfaces that are supported, reduce the sfp_support
+ 	 * mask to only those link modes that can be supported.
+ 	 */
+-	ret = phylink_validate_mask(pl, pl->sfp_support, &config, interfaces);
+	ret = phylink_validate_mask(pl, NULL, pl->sfp_support, &config,
+				    interfaces);
+ 	if (ret) {
+ 		phylink_err(pl, "unsupported SFP module: validation with support %*pb failed\n",
+ 			    __ETHTOOL_LINK_MODE_MASK_NBITS, support);
--- a/target/linux/generic/backport-6.6/895-06-v6.8-net-phylink-split-out-PHY-validation-from-phylink_br.patch
+++ b/target/linux/generic/backport-6.6/895-06-v6.8-net-phylink-split-out-PHY-validation-from-phylink_br.patch
@ -0,0 +1,95 @@
+From ee0e0ddb910e7e989b65a19d72b6435baa641fc7 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:34 +0000
+Subject: [PATCH 6/7] net: phylink: split out PHY validation from
+ phylink_bringup_phy()
+
+When bringing up a PHY, we need to work out which ethtool link modes it
+should support and advertise. Clause 22 PHYs operate in a single
+interface mode, which can be easily dealt with. However, clause 45 PHYs
+tend to switch interface mode depending on the media. We need more
+flexible validation at this point, so this patch splits out that code
+in preparation to changing it.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIQ-00DDM9-LK@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 56 ++++++++++++++++++++++-----------------
+ 1 file changed, 31 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -1775,6 +1775,35 @@ static void phylink_phy_change(struct ph
+ 		    phylink_pause_to_str(pl->phy_state.pause));
+ }
+ 
+static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
+				unsigned long *supported,
+				struct phylink_link_state *state)
+{
+	/* Check whether we would use rate matching for the proposed interface
+	 * mode.
+	 */
+	state->rate_matching = phy_get_rate_matching(phy, state->interface);
+
+	/* Clause 45 PHYs may switch their Serdes lane between, e.g. 10GBASE-R,
+	 * 5GBASE-R, 2500BASE-X and SGMII if they are not using rate matching.
+	 * For some interface modes (e.g. RXAUI, XAUI and USXGMII) switching
+	 * their Serdes is either unnecessary or not reasonable.
+	 *
+	 * For these which switch interface modes, we really need to know which
+	 * interface modes the PHY supports to properly work out which ethtool
+	 * linkmodes can be supported. For now, as a work-around, we validate
+	 * against all interface modes, which may lead to more ethtool link
+	 * modes being advertised than are actually supported.
+	 */
+	if (phy->is_c45 && state->rate_matching == RATE_MATCH_NONE &&
+	    state->interface != PHY_INTERFACE_MODE_RXAUI &&
+	    state->interface != PHY_INTERFACE_MODE_XAUI &&
+	    state->interface != PHY_INTERFACE_MODE_USXGMII)
+		state->interface = PHY_INTERFACE_MODE_NA;
+
+	return phylink_validate(pl, supported, state);
+}
+
+ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,
+ 			       phy_interface_t interface)
+ {
+@@ -1795,32 +1824,9 @@ static int phylink_bringup_phy(struct ph
+ 	memset(&config, 0, sizeof(config));
+ 	linkmode_copy(supported, phy->supported);
+ 	linkmode_copy(config.advertising, phy->advertising);
+	config.interface = interface;
+ 
+-	/* Check whether we would use rate matching for the proposed interface
+-	 * mode.
+-	 */
+-	config.rate_matching = phy_get_rate_matching(phy, interface);
+-
+-	/* Clause 45 PHYs may switch their Serdes lane between, e.g. 10GBASE-R,
+-	 * 5GBASE-R, 2500BASE-X and SGMII if they are not using rate matching.
+-	 * For some interface modes (e.g. RXAUI, XAUI and USXGMII) switching
+-	 * their Serdes is either unnecessary or not reasonable.
+-	 *
+-	 * For these which switch interface modes, we really need to know which
+-	 * interface modes the PHY supports to properly work out which ethtool
+-	 * linkmodes can be supported. For now, as a work-around, we validate
+-	 * against all interface modes, which may lead to more ethtool link
+-	 * modes being advertised than are actually supported.
+-	 */
+-	if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE &&
+-	    interface != PHY_INTERFACE_MODE_RXAUI &&
+-	    interface != PHY_INTERFACE_MODE_XAUI &&
+-	    interface != PHY_INTERFACE_MODE_USXGMII)
+-		config.interface = PHY_INTERFACE_MODE_NA;
+-	else
+-		config.interface = interface;
+-
+-	ret = phylink_validate(pl, supported, &config);
+	ret = phylink_validate_phy(pl, phy, supported, &config);
+ 	if (ret) {
+ 		phylink_warn(pl, "validation of %s with support %*pb and advertisement %*pb failed: %pe\n",
+ 			     phy_modes(config.interface),
--- a/target/linux/generic/backport-6.6/895-07-v6.8-net-phylink-use-the-PHY-s-possible_interfaces-if-pop.patch
+++ b/target/linux/generic/backport-6.6/895-07-v6.8-net-phylink-use-the-PHY-s-possible_interfaces-if-pop.patch
@ -0,0 +1,130 @@
+From 8f7a9799c5949f94ecc3acfd71b36437a7ade73b Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Nov 2023 12:28:39 +0000
+Subject: [PATCH 7/7] net: phylink: use the PHY's possible_interfaces if
+ populated
+
+Some PHYs such as Aquantia, Broadcom 84881, and Marvell 88X33x0 can
+switch between a set of interface types depending on the negotiated
+media speed, or can use rate adaption for some or all of these
+interface types.
+
+We currently assume that these are Clause 45 PHYs that are configured
+not to use a specific set of interface modes, which has worked so far,
+but is just a work-around. In this workaround, we validate using all
+interfaces that the MAC supports, which can lead to extra modes being
+advertised that can not be supported.
+
+To properly address this, switch to using the newly introduced PHY
+possible_interfaces bitmap which indicates which interface modes will
+be used by the PHY as configured. We calculate the union of the PHY's
+possible interfaces and MACs supported interfaces, checking that is
+non-empty. If the PHY is on a SFP, we further reduce the set by those
+which can be used on a SFP module, again checking that is non-empty.
+Finally, we validate the subset of interfaces, taking account of
+whether rate matching will be used for each individual interface mode.
+
+This becomes independent of whether the PHY is clause 22 or clause 45.
+
+It is encouraged that all PHYs that switch interface modes or use
+rate matching should populate phydev->possible_interfaces.
+
+Tested-by: Luo Jie <quic_luoj@quicinc.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1r6VIV-00DDMF-Pi@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 67 +++++++++++++++++++++++++++++++--------
+ 1 file changed, 54 insertions(+), 13 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
+@@ -121,6 +121,19 @@ do {									\
+ })
+ #endif
+ 
+static const phy_interface_t phylink_sfp_interface_preference[] = {
+	PHY_INTERFACE_MODE_25GBASER,
+	PHY_INTERFACE_MODE_USXGMII,
+	PHY_INTERFACE_MODE_10GBASER,
+	PHY_INTERFACE_MODE_5GBASER,
+	PHY_INTERFACE_MODE_2500BASEX,
+	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_1000BASEX,
+	PHY_INTERFACE_MODE_100BASEX,
+};
+
+static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+
+ /**
+  * phylink_set_port_modes() - set the port type modes in the ethtool mask
+  * @mask: ethtool link mode mask
+@@ -1779,6 +1792,47 @@ static int phylink_validate_phy(struct p
+ 				unsigned long *supported,
+ 				struct phylink_link_state *state)
+ {
+	DECLARE_PHY_INTERFACE_MASK(interfaces);
+
+	/* If the PHY provides a bitmap of the interfaces it will be using
+	 * depending on the negotiated media speeds, use this to validate
+	 * which ethtool link modes can be used.
+	 */
+	if (!phy_interface_empty(phy->possible_interfaces)) {
+		/* We only care about the union of the PHY's interfaces and
+		 * those which the host supports.
+		 */
+		phy_interface_and(interfaces, phy->possible_interfaces,
+				  pl->config->supported_interfaces);
+
+		if (phy_interface_empty(interfaces)) {
+			phylink_err(pl, "PHY has no common interfaces\n");
+			return -EINVAL;
+		}
+
+		if (phy_on_sfp(phy)) {
+			/* If the PHY is on a SFP, limit the interfaces to
+			 * those that can be used with a SFP module.
+			 */
+			phy_interface_and(interfaces, interfaces,
+					  phylink_sfp_interfaces);
+
+			if (phy_interface_empty(interfaces)) {
+				phylink_err(pl, "SFP PHY's possible interfaces becomes empty\n");
+				return -EINVAL;
+			}
+		}
+
+		phylink_dbg(pl, "PHY %s uses interfaces %*pbl, validating %*pbl\n",
+			    phydev_name(phy),
+			    (int)PHY_INTERFACE_MODE_MAX,
+			    phy->possible_interfaces,
+			    (int)PHY_INTERFACE_MODE_MAX, interfaces);
+
+		return phylink_validate_mask(pl, phy, supported, state,
+					     interfaces);
+	}
+
+ 	/* Check whether we would use rate matching for the proposed interface
+ 	 * mode.
+ 	 */
+@@ -3047,19 +3101,6 @@ static void phylink_sfp_detach(void *ups
+ 	pl->netdev->sfp_bus = NULL;
+ }
+ 
+-static const phy_interface_t phylink_sfp_interface_preference[] = {
+-	PHY_INTERFACE_MODE_25GBASER,
+-	PHY_INTERFACE_MODE_USXGMII,
+-	PHY_INTERFACE_MODE_10GBASER,
+-	PHY_INTERFACE_MODE_5GBASER,
+-	PHY_INTERFACE_MODE_2500BASEX,
+-	PHY_INTERFACE_MODE_SGMII,
+-	PHY_INTERFACE_MODE_1000BASEX,
+-	PHY_INTERFACE_MODE_100BASEX,
+-};
+-
+-static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+-
+ static phy_interface_t phylink_choose_sfp_interface(struct phylink *pl,
+ 						    const unsigned long *intf)
+ {
--- a/target/linux/generic/backport-6.6/896-01-v6.9-net-dsa-mv88e6xxx-rename-mv88e6xxx_g2_scratch_gpio_s.patch
+++ b/target/linux/generic/backport-6.6/896-01-v6.9-net-dsa-mv88e6xxx-rename-mv88e6xxx_g2_scratch_gpio_s.patch
@ -0,0 +1,61 @@
+From 5c5b0c444be3e851046f1c1074459b8d15d2a0f9 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 27 Feb 2024 18:54:21 +0100
+Subject: [PATCH 1/2] net: dsa: mv88e6xxx: rename
+ mv88e6xxx_g2_scratch_gpio_set_smi
+
+The name mv88e6xxx_g2_scratch_gpio_set_smi is a bit ambiguous as it appears
+to only be applicable to the 6390 family, so lets rename it to
+mv88e6390_g2_scratch_gpio_set_smi to make it more obvious.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c            | 2 +-
+ drivers/net/dsa/mv88e6xxx/global2.h         | 2 +-
+ drivers/net/dsa/mv88e6xxx/global2_scratch.c | 4 ++--
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -3668,7 +3668,7 @@ static int mv88e6xxx_mdio_register(struc
+ 
+ 	if (external) {
+ 		mv88e6xxx_reg_lock(chip);
+-		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
+		err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
+ 		mv88e6xxx_reg_unlock(chip);
+ 
+ 		if (err)
+--- a/drivers/net/dsa/mv88e6xxx/global2.h
+++ b/drivers/net/dsa/mv88e6xxx/global2.h
+@@ -378,7 +378,7 @@ extern const struct mv88e6xxx_avb_ops mv
+ 
+ extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
+ 
+-int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+ 				      bool external);
+ int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
+ int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
+--- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c
+++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
+@@ -240,7 +240,7 @@ const struct mv88e6xxx_gpio_ops mv88e635
+ };
+ 
+ /**
+- * mv88e6xxx_g2_scratch_gpio_set_smi - set gpio muxing for external smi
+ * mv88e6390_g2_scratch_gpio_set_smi - set gpio muxing for external smi
+  * @chip: chip private data
+  * @external: set mux for external smi, or free for gpio usage
+  *
+@@ -248,7 +248,7 @@ const struct mv88e6xxx_gpio_ops mv88e635
+  * an external SMI interface, or they may be made free for other
+  * GPIO uses.
+  */
+-int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+ 				      bool external)
+ {
+ 	int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
--- a/target/linux/generic/backport-6.6/896-02-v6.9-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch
+++ b/target/linux/generic/backport-6.6/896-02-v6.9-net-dsa-mv88e6xxx-add-Amethyst-specific-SMI-GPIO-fun.patch
@ -0,0 +1,92 @@
+From e3ab3267a0bbedc37725bb845a332ec33b247263 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 27 Feb 2024 18:54:22 +0100
+Subject: [PATCH 2/2] net: dsa: mv88e6xxx: add Amethyst specific SMI GPIO
+ function
+
+The existing mv88e6390_g2_scratch_gpio_set_smi() cannot be used on the
+88E6393X as it requires certain P0_MODE, it also checks the CPU mode
+as it impacts the bit setting value.
+
+This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only
+the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap
+pin value but it can be changed without restrictions so that GPIO pins
+9 and 10 are used as SMI pins.
+
+So, introduce Amethyst specific function and call that if the Amethyst
+family wants to setup the external PHY.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c            |  5 +++-
+ drivers/net/dsa/mv88e6xxx/global2.h         |  2 ++
+ drivers/net/dsa/mv88e6xxx/global2_scratch.c | 31 +++++++++++++++++++++
+ 3 files changed, 37 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -3668,7 +3668,10 @@ static int mv88e6xxx_mdio_register(struc
+ 
+ 	if (external) {
+ 		mv88e6xxx_reg_lock(chip);
+-		err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
+		if (chip->info->family == MV88E6XXX_FAMILY_6393)
+			err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
+		else
+			err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
+ 		mv88e6xxx_reg_unlock(chip);
+ 
+ 		if (err)
+--- a/drivers/net/dsa/mv88e6xxx/global2.h
+++ b/drivers/net/dsa/mv88e6xxx/global2.h
+@@ -380,6 +380,8 @@ extern const struct mv88e6xxx_gpio_ops m
+ 
+ int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+ 				      bool external);
+int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+				       bool external);
+ int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
+ int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
+ int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
+--- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c
+++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
+@@ -291,6 +291,37 @@ int mv88e6390_g2_scratch_gpio_set_smi(st
+ }
+ 
+ /**
+ * mv88e6393x_g2_scratch_gpio_set_smi - set gpio muxing for external smi
+ * @chip: chip private data
+ * @external: set mux for external smi, or free for gpio usage
+ *
+ * MV88E6191X/6193X/6393X GPIO pins 9 and 10 can be configured as an
+ * external SMI interface or as regular GPIO-s.
+ *
+ * They however have a different register layout then the existing
+ * function.
+ */
+
+int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+				       bool external)
+{
+	int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
+	int err;
+	u8 val;
+
+	err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val);
+	if (err)
+		return err;
+
+	if (external)
+		val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
+	else
+		val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
+
+	return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
+}
+
+/**
+  * mv88e6352_g2_scratch_port_has_serdes - indicate if a port can have a serdes
+  * @chip: chip private data
+  * @port: port number to check for serdes
--- a/target/linux/generic/backport-6.6/897-01-v6.9-net-phy-qcom-qca808x-add-helper-for-checking-for-1G-.patch
+++ b/target/linux/generic/backport-6.6/897-01-v6.9-net-phy-qcom-qca808x-add-helper-for-checking-for-1G-.patch
@ -0,0 +1,50 @@
+From f058b2dd70b1a5503dff899010aeb53b436091e5 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 28 Feb 2024 18:24:09 +0100
+Subject: [PATCH 1/2] net: phy: qcom: qca808x: add helper for checking for 1G
+ only model
+
+There are 2 versions of QCA808x, one 2.5G capable and one 1G capable.
+Currently, this matter only in the .get_features call however, it will
+be required for filling supported interface modes so lets add a helper
+that can be reused.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 17 ++++++++++++-----
+ 1 file changed, 12 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
+@@ -156,6 +156,17 @@ static bool qca808x_has_fast_retrain_or_
+ 	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+ }
+ 
+static bool qca808x_is_1g_only(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+	if (ret < 0)
+		return true;
+
+	return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
+}
+
+ static int qca808x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -350,11 +361,7 @@ static int qca808x_get_features(struct p
+ 	 * existed in the bit0 of MMD1.21, we need to remove it manually if
+ 	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
+ 	 */
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+	if (qca808x_is_1g_only(phydev))
+ 		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+ 
+ 	return 0;
--- a/target/linux/generic/backport-6.6/897-02-v6.9-net-phy-qcom-qca808x-fill-in-possible_interfaces.patch
+++ b/target/linux/generic/backport-6.6/897-02-v6.9-net-phy-qcom-qca808x-fill-in-possible_interfaces.patch
@ -0,0 +1,44 @@
+From cb28f702960695e26597c332b0e46776e825cc34 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 28 Feb 2024 18:24:10 +0100
+Subject: [PATCH 2/2] net: phy: qcom: qca808x: fill in possible_interfaces
+
+Currently QCA808x driver does not fill the possible_interfaces.
+2.5G QCA808x support SGMII and 2500Base-X while 1G model only supports
+SGMII, so fill the possible_interfaces accordingly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
+@@ -167,6 +167,16 @@ static bool qca808x_is_1g_only(struct ph
+ 	return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
+ }
+ 
+static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
+{
+	unsigned long *possible = phydev->possible_interfaces;
+
+	__set_bit(PHY_INTERFACE_MODE_SGMII, possible);
+
+	if (!qca808x_is_1g_only(phydev))
+		__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
+}
+
+ static int qca808x_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -231,6 +241,8 @@ static int qca808x_config_init(struct ph
+ 		}
+ 	}
+ 
+	qca808x_fill_possible_interfaces(phydev);
+
+ 	/* Configure adc threshold as 100mv for the link 10M */
+ 	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
+ 				     QCA808X_ADC_THRESHOLD_MASK,
--- a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+++ b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
@ -15,9 +15,9 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>

 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -127,6 +127,29 @@ struct aqr107_priv {
- 	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
- };
+@@ -90,6 +90,29 @@
+ #define AQR107_OP_IN_PROG_SLEEP		1000
+ #define AQR107_OP_IN_PROG_TIMEOUT	100000
 
 +/* registers in MDIO_MMD_VEND1 region */
 +#define AQUANTIA_VND1_GLOBAL_SC			0x000
@ -45,7 +45,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 static int aqr107_get_sset_count(struct phy_device *phydev)
 {
 	return AQR107_SGMII_STAT_SZ;
-@@ -233,6 +256,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -196,6 +219,51 @@ static int aqr_config_aneg(struct phy_de
 	return genphy_c45_check_and_restart_aneg(phydev, changed);
 }
 
@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 static int aqr_config_intr(struct phy_device *phydev)
 {
 	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -838,7 +906,7 @@ static struct phy_driver aqr_driver[] =
+@@ -807,7 +875,7 @@ static struct phy_driver aqr_driver[] =
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
 	.name		= "Aquantia AQR112",
 	.probe		= aqr107_probe,
@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 	.config_intr	= aqr_config_intr,
 	.handle_interrupt = aqr_handle_interrupt,
 	.get_tunable    = aqr107_get_tunable,
-@@ -863,7 +931,7 @@ static struct phy_driver aqr_driver[] =
+@@ -830,7 +898,7 @@ static struct phy_driver aqr_driver[] =
 	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
 	.name		= "Aquantia AQR412",
 	.probe		= aqr107_probe,
--- a/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+++ b/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>

 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -289,10 +289,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -252,10 +252,16 @@ static int aqr_config_aneg_set_prot(stru
 	phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
 		      aquantia_syscfg[if_type].start_rate);
 
--- a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+++ b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
@ -21,9 +21,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -1062,6 +1064,30 @@ static struct phy_driver aqr_driver[] =
+@@ -1014,6 +1016,30 @@ static struct phy_driver aqr_driver[] =
+ 	.led_hw_control_get = aqr_phy_led_hw_control_get,
 	.led_polarity_set = aqr_phy_led_polarity_set,
- #endif
 },
 +{
 +	PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 };
 
 module_phy_driver(aqr_driver);
-@@ -1082,6 +1108,8 @@ static struct mdio_device_id __maybe_unu
+@@ -1034,6 +1060,8 @@ static struct mdio_device_id __maybe_unu
 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
--- a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
+++ b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1850,6 +1850,9 @@ void phy_detach(struct phy_device *phyde
+@@ -1852,6 +1852,9 @@ void phy_detach(struct phy_device *phyde
 	struct module *ndev_owner = NULL;
 	struct mii_bus *bus;
 
@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 			sysfs_remove_link(&dev->dev.kobj, "phydev");
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -900,6 +900,12 @@ struct phy_driver {
+@@ -903,6 +903,12 @@ struct phy_driver {
 	/** @handle_interrupt: Override default interrupt handling */
 	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
 
--- a/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch
+++ b/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch
@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1908,6 +1908,9 @@ void phy_detach(struct phy_device *phyde
+@@ -1910,6 +1910,9 @@ void phy_detach(struct phy_device *phyde
 	if (phydev->devlink)
 		device_link_del(phydev->devlink);
 
@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 			sysfs_remove_link(&dev->dev.kobj, "phydev");
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -976,6 +976,12 @@ struct phy_driver {
+@@ -979,6 +979,12 @@ struct phy_driver {
 	/** @handle_interrupt: Override default interrupt handling */
 	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
 
--- a/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
+++ b/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>

 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -6989,6 +6989,7 @@ static int mv88e6xxx_register_switch(str
+@@ -6992,6 +6992,7 @@ static int mv88e6xxx_register_switch(str
 	ds->ops = &mv88e6xxx_switch_ops;
 	ds->ageing_time_min = chip->info->age_time_coeff;
 	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
--- a/target/linux/generic/pending-6.6/999-net-phy-move-LED-polarity-to-phy_init_hw.patch
+++ b/target/linux/generic/pending-6.6/999-net-phy-move-LED-polarity-to-phy_init_hw.patch
@ -1,100 +0,0 @@
-From 6e6fff51ae5e54092611d174fa45fa78c237a415 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 21 May 2024 20:01:46 +0200
-Subject: [PATCH] net: phy: move LED polarity to phy_init_hw
-
-Some PHY reset the polarity on reset and this cause the LED to
-malfunction as LED polarity is configured only when LED is
-registered.
-
-To better handle this, move the LED polarity configuration in
-phy_init_hw to reconfigure it after PHY reset.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- drivers/net/phy/phy_device.c | 53 +++++++++++++++++++++++++-----------
- 1 file changed, 37 insertions(+), 16 deletions(-)
-
--- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -1223,6 +1223,37 @@ static int phy_poll_reset(struct phy_dev
- 	return 0;
- }
- 
-+static int of_phy_led_init(struct phy_device *phydev)
-+{
-+	struct phy_led *phyled;
-+
-+	list_for_each_entry(phyled, &phydev->leds, list) {
-+		struct led_classdev *cdev = &phyled->led_cdev;
-+		struct device_node *np = cdev->dev->of_node;
-+		unsigned long modes = 0;
-+		int err;
-+
-+		if (of_property_read_bool(np, "active-low"))
-+			set_bit(PHY_LED_ACTIVE_LOW, &modes);
-+		if (of_property_read_bool(np, "inactive-high-impedance"))
-+			set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
-+
-+		if (!modes)
-+			continue;
-+
-+		/* Return error if asked to set polarity modes but not supported */
-+		if (!phydev->drv->led_polarity_set)
-+			return -EINVAL;
-+
-+		err = phydev->drv->led_polarity_set(phydev, phyled->index,
-+						    modes);
-+		if (err)
-+			return err;
-+	}
-+
-+	return 0;
-+}
-+
- int phy_init_hw(struct phy_device *phydev)
- {
- 	int ret = 0;
-@@ -1259,6 +1290,12 @@ int phy_init_hw(struct phy_device *phyde
- 			return ret;
- 	}
- 
-+	if (IS_ENABLED(CONFIG_PHYLIB_LEDS)) {
-+		ret = of_phy_led_init(phydev);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
- 	return 0;
- }
- EXPORT_SYMBOL(phy_init_hw);
-@@ -3204,7 +3241,6 @@ static int of_phy_led(struct phy_device
- 	struct device *dev = &phydev->mdio.dev;
- 	struct led_init_data init_data = {};
- 	struct led_classdev *cdev;
-	unsigned long modes = 0;
- 	struct phy_led *phyled;
- 	u32 index;
- 	int err;
-@@ -3222,21 +3258,6 @@ static int of_phy_led(struct phy_device
- 	if (index > U8_MAX)
- 		return -EINVAL;
- 
-	if (of_property_read_bool(led, "active-low"))
-		set_bit(PHY_LED_ACTIVE_LOW, &modes);
-	if (of_property_read_bool(led, "inactive-high-impedance"))
-		set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
-
-	if (modes) {
-		/* Return error if asked to set polarity modes but not supported */
-		if (!phydev->drv->led_polarity_set)
-			return -EINVAL;
-
-		err = phydev->drv->led_polarity_set(phydev, index, modes);
-		if (err)
-			return err;
-	}
-
- 	phyled->index = index;
- 	if (phydev->drv->led_brightness_set)
- 		cdev->brightness_set_blocking = phy_led_set_brightness;
--- a/target/linux/ipq806x/base-files/etc/board.d/01_leds
+++ b/target/linux/ipq806x/base-files/etc/board.d/01_leds
@ -46,6 +46,9 @@ fortinet,fap-421e)
 	ucidef_set_led_wlan "wlan5g" "5G" "yellow:5g" "phy0tpt"
 	ucidef_set_led_usbport "usb" "USB" "amber:power" "usb1-port1" "usb2-port1"
 	;;
+linksys,e8350-v1)
+	ucidef_set_led_wlan "wlan" "WLAN" "green:wifi" "phy0tpt"
+	;;
 meraki,mr52)
 	ucidef_set_led_netdev "eth0" "eth0" "green:lan1" "eth0"
 	ucidef_set_led_netdev "eth1" "eth1" "green:lan2" "eth1"
--- a/target/linux/ipq806x/base-files/etc/board.d/02_network
+++ b/target/linux/ipq806x/base-files/etc/board.d/02_network
@ -23,6 +23,7 @@ ipq806x_setup_interfaces()
 	netgear,r7500 |\
 	netgear,r7500v2 |\
 	qcom,ipq8064-ap148 |\
+	linksys,e8350-v1 |\
 	linksys,ea7500-v1 |\
 	linksys,ea8500 |\
 	nec,wg2600hp3 |\
@ -95,16 +96,17 @@ ipq806x_setup_macs()
 			ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
 			ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
 		;;
-		ruijie,rg-mtfi-m520)
-			hw_mac_addr=$(mtd_get_mac_ascii PRODUCTINFO ethaddr)
-			ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
-			ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 1)"
-		;;
+		linksys,e8350-v1 |\
 		zyxel,nbg6817)
 			hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr)
 			ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)"
 			ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)"
 		;;
+		ruijie,rg-mtfi-m520)
+			hw_mac_addr=$(mtd_get_mac_ascii PRODUCTINFO ethaddr)
+			ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
+			ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 1)"
+		;;
 		asrock,g10)
 			hw_mac_addr=$(mtd_get_mac_ascii hwconfig HW.LAN.MAC.Address)
 			ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
--- a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
@ -14,6 +14,7 @@ platform_do_upgrade() {
 	askey,rt4230w-rev6 |\
 	compex,wpq864|\
 	fortinet,fap-421e|\
+	linksys,e8350-v1|\
 	netgear,d7800 |\
 	netgear,r7500 |\
 	netgear,r7500v2 |\
--- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-e8350-v1.dts
+++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-e8350-v1.dts
@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#include "qcom-ipq8064-v2.0-smb208.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+	model = "Linksys E8350 V1 WiFi Router";
+	compatible = "linksys,e8350-v1", "qcom,ipq8064";
+
+	memory@0 {
+		reg = <0x42000000 0x1e000000>;
+		device_type = "memory";
+	};
+
+	aliases {
+		serial0 = &gsbi4_serial;
+
+		led-boot = &led_power;
+		led-failsafe = &led_power;
+		led-running = &led_power;
+		led-upgrade = &led_power;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+
+		wifi {
+			label = "wifi";
+			gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+			debounce-interval = <60>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		led_power: power {
+			label = "green:power";
+			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+
+		wps {
+			label = "green:wps";
+			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
+		};
+
+		wifi {
+			label = "green:wifi";
+			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	nand@0 {
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+
+			partition@0 {
+				label = "ubi";
+				reg = <0 0x4000000>;
+			};
+			partition@4000000 {
+				label = "extra";
+				reg = <0x4000000 0x4000000>;
+			};
+		};
+	};
+};
+
+&qcom_pinmux {
+	button_pins: button_pins {
+		mux {
+			pins = "gpio68","gpio65", "gpio67";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	led_pins: led_pins {
+		mux {
+			pins = "gpio26","gpio53", "gpio54";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	switch_reset: switch_reset_pins {
+		mux {
+			pins = "gpio63";
+			function = "gpio";
+			drive-strength = <12>;
+			bias-pull-up;
+		};
+	};
+};
+
+&gsbi5 {
+	qcom,mode = <GSBI_PROT_SPI>;
+	status = "okay";
+
+	spi5: spi@1a280000 {
+		status = "okay";
+
+		pinctrl-0 = <&spi_pins>;
+		pinctrl-names = "default";
+
+		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
+
+		m25p80@0 {
+			compatible = "jedec,spi-nor";
+			spi-max-frequency = <51200000>;
+			reg = <0>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					label = "0:sbl1";
+					reg = <0x0000000 0x0010000>;
+					read-only;
+				};
+
+				partition@10000 {
+					label = "0:mibib";
+					reg = <0x0010000 0x0020000>;
+					read-only;
+				};
+
+				partition@30000 {
+					label = "0:sbl2";
+					reg = <0x0030000 0x0020000>;
+					read-only;
+				};
+
+				partition@50000 {
+					label = "0:sbl3";
+					reg = <0x0050000 0x0030000>;
+					read-only;
+				};
+
+				partition@80000 {
+					label = "0:ddrconfig";
+					reg = <0x0080000 0x0010000>;
+					read-only;
+				};
+
+				partition@90000 {
+					label = "0:ssd";
+					reg = <0x0090000 0x0010000>;
+					read-only;
+				};
+
+				partition@a0000 {
+					label = "0:tz";
+					reg = <0x00a0000 0x0030000>;
+					read-only;
+				};
+
+				partition@d0000 {
+					label = "0:rpm";
+					reg = <0x00d0000 0x0020000>;
+					read-only;
+				};
+
+				partition@f0000 {
+					label = "0:oldappsbl";
+					reg = <0x00f0000 0x0040000>;
+					read-only;
+				};
+
+				partition@130000 {
+					label = "0:appsblenv";
+					reg = <0x0130000 0x0040000>;
+					read-only;
+				};
+
+				art: partition@170000 {
+					label = "0:ART";
+					reg = <0x0170000 0x0020000>;
+					read-only;
+				};
+
+				partition@190000 {
+					label = "0:uboot";
+					reg = <0x0190000 0x0050000>;
+					read-only;
+				};
+
+				partition@1e0000 {
+					label = "0:oldnss1";
+					reg = <0x01e0000 0x0020000>;
+					read-only;
+				};
+
+				partition@200000 {
+					label = "0:nvram";
+					reg = <0x0200000 0x0020000>;
+					read-only;
+				};
+
+				partition@220000 {
+					label = "0:oldkernel";
+					reg = <0x0220000 0x01e0000>;
+					read-only;
+				};
+			};
+		};
+	};
+};
+
+&hs_phy_0 {
+	status = "okay";
+};
+
+&ss_phy_0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&hs_phy_1 {
+	status = "okay";
+};
+
+&ss_phy_1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	max-link-speed = <1>;
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio0_pins>;
+	pinctrl-names = "default";
+
+	/* Switch from documentation require at least 12ms for reset */
+	reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
+	reset-post-delay-us = <12000>;
+
+	switch@10 {
+		compatible = "qca,qca8337";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x10>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "cpu";
+				ethernet = <&gmac1>;
+				phy-mode = "rgmii";
+				tx-internal-delay-ps = <1000>;
+				rx-internal-delay-ps = <1000>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan1";
+				phy-mode = "internal";
+				phy-handle = <&phy_port1>;
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+				phy-mode = "internal";
+				phy-handle = <&phy_port2>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan3";
+				phy-mode = "internal";
+				phy-handle = <&phy_port3>;
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan4";
+				phy-mode = "internal";
+				phy-handle = <&phy_port4>;
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "wan";
+				phy-mode = "internal";
+				phy-handle = <&phy_port5>;
+			};
+
+			port@6 {
+				reg = <6>;
+				label = "cpu";
+				ethernet = <&gmac2>;
+				phy-mode = "sgmii";
+				qca,sgmii-enable-pll;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+		};
+	};
+};
+
+&gmac1 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	qcom,id = <1>;
+
+	pinctrl-0 = <&rgmii2_pins>;
+	pinctrl-names = "default";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&gmac2 {
+	status = "okay";
+
+	phy-mode = "sgmii";
+	qcom,id = <2>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&tcsr {
+	qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
+	compatible = "qcom,tcsr", "syscon";
+};
+
+&adm_dma {
+	status = "okay";
+};
--- a/target/linux/ipq806x/image/generic.mk
+++ b/target/linux/ipq806x/image/generic.mk
@ -35,6 +35,18 @@ define Build/edimax-header
 	@mv $@.new $@
 endef

+# tune addpattern for Linksys E8350-V1 fw pattern generation
+define Build/linksys-bin
+        $(STAGING_DIR_HOST)/bin/addpattern -p $(FW_DEVICE_ID) -v $(FW_VERSION) $(if $(SERIAL),-s $(SERIAL)) -i $@ -o $@.new
+        mv $@.new $@
+endef
+
+# Use Linksys fw header generator to upgrade openwrt factory image over the native Linksys WEB interface
+define Build/linksys-addfwhdr
+        -$(STAGING_DIR_HOST)/bin/linksys-addfwhdr -i $@ -o $@.new \
+       	;mv "$@.new" "$@"
+endef
+
 define Device/DniImage
 	KERNEL_SUFFIX := -uImage
 	KERNEL = kernel-bin | append-dtb | uImage none
@ -189,6 +201,23 @@ define Device/fortinet_fap-421e
 endef
 TARGET_DEVICES += fortinet_fap-421e

+define Device/linksys_e8350-v1
+	$(call Device/LegacyImage)
+	DEVICE_VENDOR := Linksys
+	DEVICE_MODEL := E8350
+	DEVICE_VARIANT := v1
+	SOC := qcom-ipq8064
+	FW_VERSION := v1.0.03.003
+	FW_DEVICE_ID := 8350
+	PAGESIZE := 2048
+	BLOCKSIZE := 128k
+	KERNEL_IN_UBI := 1
+	IMAGES = factory.bin sysupgrade.bin
+	IMAGE/factory.bin := append-ubi | check-size 0x04000000 | linksys-addfwhdr | linksys-bin
+	DEVICE_PACKAGES := ath10k-firmware-qca988x-ct
+endef
+TARGET_DEVICES += linksys_e8350-v1
+
 define Device/linksys_ea7500-v1
 	$(call Device/LegacyImage)
 	$(Device/kernel-size-migration)
--- a/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
+++ b/target/linux/layerscape/patches-6.1/702-phy-Add-2.5G-SGMII-interface-mode.patch
@ -25,7 +25,7 @@ Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
 	case PHY_INTERFACE_MODE_QUSGMII:
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p
+@@ -231,6 +231,7 @@ static int phylink_interface_max_speed(p
 		return SPEED_1000;
 
 	case PHY_INTERFACE_MODE_2500BASEX:
--- a/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
+++ b/target/linux/layerscape/patches-6.1/704-net-phylink-treat-PHY_INTERFACE_MODE_2500SGMII-in-ph.patch
@ -32,7 +32,7 @@ Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -505,6 +505,7 @@ unsigned long phylink_get_capabilities(p
+@@ -518,6 +518,7 @@ unsigned long phylink_get_capabilities(p
 		break;
 
 	case PHY_INTERFACE_MODE_2500BASEX:
--- a/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch
+++ b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch
@ -25,7 +25,7 @@ Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
 	case PHY_INTERFACE_MODE_QUSGMII:
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p
+@@ -231,6 +231,7 @@ static int phylink_interface_max_speed(p
 		return SPEED_1000;
 
 	case PHY_INTERFACE_MODE_2500BASEX:
@ -33,7 +33,7 @@ Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
 		return SPEED_2500;
 
 	case PHY_INTERFACE_MODE_5GBASER:
-@@ -526,6 +527,7 @@ unsigned long phylink_get_capabilities(p
+@@ -539,6 +540,7 @@ unsigned long phylink_get_capabilities(p
 		break;
 
 	case PHY_INTERFACE_MODE_2500BASEX:
--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
@ -32,6 +32,9 @@ marvell,armada7040-db)
 marvell,armada8040-clearfog-gt-8k)
 	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 eth2" "eth0 eth1"
 	;;
+mikrotik,rb5009)
+	ucidef_set_interfaces_lan_wan "p2 p3 p4 p5 p6 p7 p8 sfp" "p1"
+	;;
 solidrun,clearfog-pro)
 	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5 lan6 eth0 eth1" "eth2"
 	;;
--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
@ -37,6 +37,9 @@ platform_do_upgrade() {
 	solidrun,clearfog-pro)
 		legacy_sdcard_do_upgrade "$1"
 		;;
+	mikrotik,rb5009)
+		nand_do_upgrade "$1"
+		;;
 	*)
 		default_do_upgrade "$1"
 		;;
--- a/target/linux/mvebu/cortexa72/config-6.6
+++ b/target/linux/mvebu/cortexa72/config-6.6
@ -37,6 +37,7 @@ CONFIG_ARM_GIC_V3_ITS=y
 CONFIG_ARM_GIC_V3_ITS_PCI=y
 # CONFIG_ARM_PL172_MPMC is not set
 CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_SBSA_WATCHDOG=y
 CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
 CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
@ -60,6 +61,10 @@ CONFIG_MFD_IEI_WT61P803_PUZZLE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MMC_SDHCI_XENON=y
 CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MIKROTIK=y
+CONFIG_MIKROTIK_RB_SYSFS=y
+CONFIG_MTD_ROUTERBOOT_PARTS=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
 CONFIG_MVEBU_GICP=y
 CONFIG_MVEBU_ICU=y
 CONFIG_MVEBU_ODMI=y
@ -69,8 +74,10 @@ CONFIG_MVPP2=y
 CONFIG_MV_XOR_V2=y
 CONFIG_NEED_SG_DMA_LENGTH=y
 CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_MIKROTIK=y
 CONFIG_NVMEM_LAYOUT_ONIE_TLV=y
 CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
 CONFIG_PARTITION_PERCPU=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEPORTBUS=y
@ -89,11 +96,13 @@ CONFIG_PINCTRL_ARMADA_AP806=y
 CONFIG_PINCTRL_ARMADA_CP110=y
 CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
 CONFIG_POWER_SUPPLY=y
+CONFIG_QCA808X_PHY=y
 CONFIG_QUEUED_RWLOCKS=y
 CONFIG_QUEUED_SPINLOCKS=y
 CONFIG_RAS=y
 # CONFIG_RAVE_SP_CORE is not set
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
 # CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
 CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
 CONFIG_SERIAL_DEV_BUS=y
--- a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts
+++ b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/armada-7040-rb5009.dts
@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "armada-7040.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "MikroTik RB5009";
+	compatible = "mikrotik,rb5009", "marvell,armada7040",
+		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	aliases {
+		led-boot = &led_user;
+		led-failsafe = &led_user;
+		led-running = &led_user;
+		led-upgrade = &led_user;
+	};
+
+	usb3_vbus: regulator-usb3-vbus0 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_leds: regulator-leds {
+		compatible = "regulator-fixed";
+		regulator-name = "LED-power";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&cp0_gpio2 27 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
+
+	output-led-power {
+		compatible = "regulator-output";
+		vout-supply = <&reg_leds>;
+	};
+
+	sfp_i2c: sfp-i2c {
+		compatible = "i2c-gpio";
+		sda-gpios = <&cp0_gpio1 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&cp0_gpio1 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&cp0_gpio1 28 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_user: user {
+			label = "green:user";
+			gpios = <&cp0_gpio2 26 GPIO_ACTIVE_LOW>;
+		};
+
+		sfp {
+			label = "green:sfp";
+			gpios = <&cp0_gpio2 25 GPIO_ACTIVE_LOW>;
+		};
+
+		hdr1 {
+			label = "blue:hdr1";
+			gpios = <&cp0_gpio1 4 GPIO_ACTIVE_LOW>;
+		};
+
+		hdr2 {
+			label = "blue:hdr2";
+			gpios = <&cp0_gpio2 19 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	sfp: sfp {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp_i2c>;
+		mod-def0-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>;
+		los-gpios = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&cp0_gpio1 6 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpios = <&cp0_gpio1 5 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&cp0_gpio1 3 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+
+	pinctrl-0 = <&uart0_pins>;
+	pinctrl-names = "default";
+};
+
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				compatible = "mikrotik,routerboot-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				label = "MikroTik";
+				reg = <0x0 0xfe0000>;
+
+				hard_config: hard_config {
+					read-only;
+
+					nvmem-layout {
+						compatible = "mikrotik,routerboot-nvmem";
+
+						macaddr_hard: base-mac-address {
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				soft_config {
+				};
+
+				dtb_config {
+					read-only;
+				};
+			};
+
+			partition@b0000 {
+				label = "RouterBOOT-primary";
+				reg = <0xb0000 0x10000>;
+			};
+
+			/* Empty space on NOR repurposed for U-Boot environment */
+			partition@fe0000 {
+				compatible = "u-boot,env";
+				label = "u-boot-env";
+				reg = <0xfe0000 0x20000>;
+			};
+		};
+	};
+};
+
+&cp0_nand_controller {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		nand-rb = <0>;
+		nand-ecc-mode = "hw";
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-on-flash-bbt;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "YAFFS";
+				reg = <0x0 0x800000>;
+			};
+
+			partition@800000 {
+				label = "ubi";
+				reg = <0x800000 0x3f800000>;
+			};
+		};
+	};
+};
+
+&cp0_utmi {
+	status = "okay";
+};
+
+&cp0_comphy3 {
+	connector {
+		compatible = "usb-a-connector";
+		phy-supply = <&usb3_vbus>;
+	};
+};
+
+&cp0_usb3_1 {
+	status = "okay";
+	phys = <&cp0_comphy3 1>, <&cp0_utmi1>;
+	phy-names = "cp0-usb3h1-comphy", "utmi";
+	dr_mode = "host";
+};
+
+&cp0_i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&cp0_mdio {
+	status = "okay";
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+&cp0_eth0 {
+	/* This port is connected to 88E6393X switch */
+	status = "okay";
+	phy-mode = "10gbase-r";
+	phys = <&cp0_comphy2 0>;
+	managed = "in-band-status";
+	nvmem-cells = <&macaddr_hard 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&cp0_mdio {
+	status = "okay";
+
+	switch@0 {
+		/* Actual device is MV88E6393X */
+		compatible = "marvell,mv88e6190";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		/* LED config is lost if switch is reset */
+		//reset-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "cpu";
+				ethernet = <&cp0_eth0>;
+				phy-mode = "10gbase-r";
+				managed = "in-band-status";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "p8";
+				phy-handle = <&switch0phy1>;
+				nvmem-cells = <&macaddr_hard 7>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "p7";
+				phy-handle = <&switch0phy2>;
+				nvmem-cells = <&macaddr_hard 6>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "p6";
+				phy-handle = <&switch0phy3>;
+				nvmem-cells = <&macaddr_hard 5>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "p5";
+				phy-handle = <&switch0phy4>;
+				nvmem-cells = <&macaddr_hard 4>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "p4";
+				phy-handle = <&switch0phy5>;
+				nvmem-cells = <&macaddr_hard 3>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@6 {
+				reg = <6>;
+				label = "p3";
+				phy-handle = <&switch0phy6>;
+				nvmem-cells = <&macaddr_hard 2>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@7 {
+				reg = <7>;
+				label = "p2";
+				phy-handle = <&switch0phy7>;
+				nvmem-cells = <&macaddr_hard 1>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@9 {
+				reg = <9>;
+				label = "p1";
+				phy-mode = "sgmii";
+				phy-handle = <&qca8081>;
+				managed = "in-band-status";
+				nvmem-cells = <&macaddr_hard 0>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@a {
+				reg = <10>;
+				label = "sfp";
+				phy-mode = "10gbase-r";
+				managed = "in-band-status";
+				sfp = <&sfp>;
+				nvmem-cells = <&macaddr_hard 8>;
+				nvmem-cell-names = "mac-address";
+			};
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch0phy1: switch0phy1@1 {
+				reg = <0x1>;
+			};
+
+			switch0phy2: switch0phy2@2 {
+				reg = <0x2>;
+			};
+
+			switch0phy3: switch0phy3@3 {
+				reg = <0x3>;
+			};
+
+			switch0phy4: switch0phy4@4 {
+				reg = <0x4>;
+			};
+
+			switch0phy5: switch0phy5@5 {
+				reg = <0x5>;
+			};
+
+			switch0phy6: switch0phy6@6 {
+				reg = <0x6>;
+			};
+
+			switch0phy7: switch0phy7@7 {
+				reg = <0x7>;
+			};
+		};
+
+		mdio1 {
+			compatible = "marvell,mv88e6xxx-mdio-external";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qca8081: qca8081@0 {
+				reg = <0>;
+			};
+		};
+	};
+};
--- a/target/linux/mvebu/image/cortexa72.mk
+++ b/target/linux/mvebu/image/cortexa72.mk
@ -1,3 +1,16 @@
+define Device/FitImage
+  KERNEL_SUFFIX := -uImage.itb
+  KERNEL = kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
+  KERNEL_NAME := Image
+endef
+
+define Device/UbiFit
+  KERNEL_IN_UBI := 1
+  IMAGES := factory.ubi sysupgrade.bin
+  IMAGE/factory.ubi := append-ubi
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+
 define Device/globalscale_mochabin
  $(call Device/Default-arm64)
  DEVICE_VENDOR := Globalscale
@ -52,6 +65,19 @@ define Device/marvell_macchiatobin-singleshot
 endef
 TARGET_DEVICES += marvell_macchiatobin-singleshot

+define Device/mikrotik_rb5009
+  $(call Device/Default-arm64)
+  $(Device/NAND-128K)
+  $(call Device/FitImage)
+  $(call Device/UbiFit)
+  DEVICE_VENDOR := MikroTik
+  DEVICE_MODEL := RB5009
+  SOC := armada-7040
+  KERNEL_LOADADDR := 0x22000000
+  DEVICE_PACKAGES += kmod-i2c-gpio yafut
+endef
+TARGET_DEVICES += mikrotik_rb5009
+
 define Device/marvell_clearfog-gt-8k
  $(call Device/Default-arm64)
  DEVICE_VENDOR := SolidRun
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-rax120v2.dts
@ -289,9 +289,8 @@
 	status = "okay";

 	g761@3e {
-		compatible = "gmt,g763";
+		compatible = "gmt,g761";
 		reg = <0x3e>;
-		clocks =<&sleep_clk>;
 		fan_gear_mode = <0>;
 		fan_start = <1>;
 		pwm_polarity = <0>;
--- a/target/linux/qualcommax/image/ipq807x.mk
+++ b/target/linux/qualcommax/image/ipq807x.mk
@ -161,7 +161,7 @@ define Device/netgear_rax120v2
 	NETGEAR_BOARD_ID := RAX120
 	NETGEAR_HW_ID := 29765589+0+512+1024+4x4+8x8
 	DEVICE_PACKAGES := ipq-wifi-netgear_rax120v2 kmod-spi-gpio \
-		kmod-spi-bitbang kmod-gpio-nxp-74hc164 kmod-hwmon-g761
+		kmod-spi-bitbang kmod-gpio-nxp-74hc164 kmod-hwmon-g762
 	IMAGES += web-ui-factory.img
 	IMAGE/web-ui-factory.img := append-image initramfs-uImage.itb | \
 		pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | \
--- a/target/linux/ramips/patches-6.6/720-NET-no-auto-carrier-off-support.patch
+++ b/target/linux/ramips/patches-6.6/720-NET-no-auto-carrier-off-support.patch
@ -21,7 +21,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 	if (phydev->mii_ts && phydev->mii_ts->link_state)
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -659,6 +659,7 @@ struct phy_device {
+@@ -661,6 +661,7 @@ struct phy_device {
 	unsigned downshifted_rate:1;
 	unsigned is_on_sfp_module:1;
 	unsigned mac_managed_pm:1;
--- a/tools/llvm-bpf/Makefile
+++ b/tools/llvm-bpf/Makefile
@ -7,12 +7,11 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=llvm-project
-PKG_VERSION:=15.0.7
-PKG_RELEASE:=1
+PKG_VERSION:=18.1.7

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).src.tar.xz
 PKG_SOURCE_URL:=https://github.com/llvm/llvm-project/releases/download/llvmorg-$(PKG_VERSION)
-PKG_HASH:=8b5fcb24b4128cf04df1b0b9410ce8b1a729cb3c544e6da885d234280dedeac6
+PKG_HASH:=74446ab6943f686391954cbda0d77ae92e8a60c432eff437b8666e121d748ec4
 PKG_CPE_ID:=cpe:/a:llvm:llvm

 HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION).src
@ -28,16 +27,27 @@ LLVM_BPF_PREFIX = llvm-bpf-$(PKG_VERSION).$(HOST_OS)-$(HOST_ARCH)
 CMAKE_HOST_INSTALL_PREFIX = $(STAGING_DIR_HOST)/$(LLVM_BPF_PREFIX)

 CMAKE_HOST_OPTIONS += \
-	-DLLVM_ENABLE_BINDINGS=OFF \
-	-DLLVM_INCLUDE_DOCS=OFF \
-	-DLLVM_INCLUDE_EXAMPLES=OFF \
-	-DLLVM_INCLUDE_TESTS=OFF \
-	-DLLVM_ENABLE_PROJECTS="clang;lld" \
 	-DLLVM_TARGETS_TO_BUILD=BPF \
-	-DCLANG_BUILD_EXAMPLES=OFF \
+	-DLLVM_DEFAULT_TARGET_TRIPLE=bpf \
+	-DLLVM_ENABLE_PROJECTS="clang;lld" \
 	-DLLVM_INSTALL_TOOLCHAIN_ONLY=ON \
 	-DLLVM_LINK_LLVM_DYLIB=ON \
 	-DLLVM_TOOLCHAIN_TOOLS="llvm-objcopy;llvm-objdump;llvm-readelf;llvm-strip;llvm-ar;llvm-as;llvm-dis;llvm-link;llvm-nm;llvm-ranlib;llc;opt" \
+	-DLLVM_INCLUDE_BENCHMARKS=OFF \
+	-DLLVM_INCLUDE_DOCS=OFF \
+	-DLLVM_INCLUDE_EXAMPLES=OFF \
+	-DLLVM_INCLUDE_TESTS=OFF \
+	-DLLVM_ENABLE_BINDINGS=OFF \
+	-DLLVM_ENABLE_IDE=OFF \
+	-DLLVM_ENABLE_LIBEDIT=OFF \
+	-DLLVM_ENABLE_LIBPFM=OFF \
+	-DLLVM_ENABLE_LIBXML2=OFF \
+	-DLLVM_ENABLE_OCAMLDOC=OFF \
+	-DLLVM_ENABLE_TERMINFO=OFF \
+	-DLLVM_ENABLE_Z3_SOLVER=OFF \
+	-DLLVM_ENABLE_ZLIB=OFF \
+	-DLLVM_ENABLE_ZSTD=OFF \
+	-DLLVM_PARALLEL_LINK_JOBS=1 \
 	-DCMAKE_SKIP_RPATH=OFF

 define Host/Install
--- a/tools/mtd-utils/Makefile
+++ b/tools/mtd-utils/Makefile
@ -7,12 +7,12 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=mtd-utils
-PKG_VERSION:=2.1.6
-PKG_RELEASE:=1
+PKG_VERSION:=2.2.0
+PKG_RELEASE:=2

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:=https://infraroot.at/pub/mtd/
-PKG_HASH:=c1d853bc4adf83bcabd2792fc95af33bdd8643c97e8f7b3f0180af36af76f0e5
+PKG_HASH:=250d082f67375ca8451b5fcfc9a23a53ced3ebebd8312c288daf2507bbab1324
 PKG_CPE_ID:=cpe:/a:mtd-utils_project:mtd-utils

 PKG_FIXUP:=autoreconf
@ -33,11 +33,12 @@ HOST_CONFIGURE_VARS+= \
 	UUID_CFLAGS="-I$(STAGING_DIR_HOST)/include/e2fsprogs/uuid"

 HOST_CONFIGURE_ARGS+= \
-	--disable-tests \
+	--without-tests \
 	--without-crypto \
 	--without-xattr \
 	--without-zstd \
-	--without-lzo
+	--without-lzo \
+	--with-lzma

 HOST_MAKE_FLAGS += \
 	PROGRAMS="mkfs.jffs2 ubinize mkfs.ubifs"
--- a/tools/mtd-utils/patches/110-portability.patch
+++ b/tools/mtd-utils/patches/110-portability.patch
@ -1,9 +1,9 @@
 --- a/jffsX-utils/compr_lzo.c
 +++ b/jffsX-utils/compr_lzo.c
-@@ -26,7 +26,6 @@
+@@ -24,7 +24,6 @@
+ #include <stdint.h>
+ #include <stdio.h>
 #include <string.h>
- 
- #ifndef WITHOUT_LZO
 -#include <asm/types.h>
 #include <linux/jffs2.h>
 #include <lzo/lzo1x.h>
@ -70,7 +70,7 @@
 #include <sys/types.h>
 --- a/ubifs-utils/mkfs.ubifs/mkfs.ubifs.c
 +++ b/ubifs-utils/mkfs.ubifs/mkfs.ubifs.c
-@@ -1542,6 +1542,7 @@ static int add_inode(struct stat *st, in
+@@ -1554,6 +1554,7 @@ static int add_inode(struct stat *st, in
 
 	if (c->default_compr != UBIFS_COMPR_NONE)
 		use_flags |= UBIFS_COMPR_FL;
@ -78,7 +78,7 @@
 	if (flags & FS_COMPR_FL)
 		use_flags |= UBIFS_COMPR_FL;
 	if (flags & FS_SYNC_FL)
-@@ -1554,6 +1555,7 @@ static int add_inode(struct stat *st, in
+@@ -1566,6 +1567,7 @@ static int add_inode(struct stat *st, in
 		use_flags |= UBIFS_DIRSYNC_FL;
 	if (fctx)
 		use_flags |= UBIFS_CRYPT_FL;
@ -86,7 +86,7 @@
 	memset(ino, 0, UBIFS_INO_NODE_SZ);
 
 	ino_key_init(&key, inum);
-@@ -1639,7 +1641,9 @@ static int add_dir_inode(const char *pat
+@@ -1651,7 +1653,9 @@ static int add_dir_inode(const char *pat
 		fd = dirfd(dir);
 		if (fd == -1)
 			return sys_err_msg("dirfd failed");
@ -96,23 +96,23 @@
 			flags = 0;
 	}
 
-@@ -1850,6 +1854,7 @@ static int add_file(const char *path_nam
+@@ -1862,6 +1866,7 @@ static int add_file(const char *path_nam
 		dn->ch.node_type = UBIFS_DATA_NODE;
 		key_write(&key, &dn->key);
 		out_len = NODE_BUFFER_SIZE - UBIFS_DATA_NODE_SZ;
 +#ifndef NO_NATIVE_SUPPORT
 		if (c->default_compr == UBIFS_COMPR_NONE &&
 		    !c->encrypted && (flags & FS_COMPR_FL))
- #ifdef WITHOUT_LZO
-@@ -1858,6 +1863,7 @@ static int add_file(const char *path_nam
- 			use_compr = UBIFS_COMPR_LZO;
+ #ifdef WITH_LZO
+@@ -1872,6 +1877,7 @@ static int add_file(const char *path_nam
+ 			use_compr = UBIFS_COMPR_NONE;
 #endif
 		else
 +#endif
 			use_compr = c->default_compr;
 		compr_type = compress_data(buf, bytes_read, &dn->data,
 					   &out_len, use_compr);
-@@ -1917,7 +1923,9 @@ static int add_non_dir(const char *path_
+@@ -1931,7 +1937,9 @@ static int add_non_dir(const char *path_
 		if (fd == -1)
 			return sys_err_msg("failed to open file '%s'",
 					   path_name);
--- a/tools/mtd-utils/patches/130-lzma_jffs2.patch
+++ b/tools/mtd-utils/patches/130-lzma_jffs2.patch
@ -1,25 +1,9 @@
 --- a/jffsX-utils/Makemodule.am
 +++ b/jffsX-utils/Makemodule.am
-@@ -4,7 +4,10 @@ mkfs_jffs2_SOURCES = \
- 	jffsX-utils/compr_zlib.c \
- 	jffsX-utils/compr.h \
- 	jffsX-utils/rbtree.c \
-	jffsX-utils/compr_lzo.c \
-+	jffsX-utils/compr_lzma.c \
-+	jffsX-utils/lzma/LzFind.c \
-+	jffsX-utils/lzma/LzmaEnc.c \
-+	jffsX-utils/lzma/LzmaDec.c \
- 	jffsX-utils/compr.c \
- 	jffsX-utils/compr_rtime.c \
- 	jffsX-utils/compr.h \
-@@ -12,8 +15,13 @@ mkfs_jffs2_SOURCES = \
+@@ -10,8 +10,9 @@ mkfs_jffs2_SOURCES = \
 	jffsX-utils/summary.h \
 	include/linux/jffs2.h \
 	include/mtd/jffs2-user.h
-+
-+if !WITHOUT_LZO
-+mkfs_jffs2_SOURCES += jffsX-utils/compr_lzo.c
-+endif
 +
 mkfs_jffs2_LDADD = libmtd.a $(ZLIB_LIBS) $(LZO_LIBS)
 -mkfs_jffs2_CPPFLAGS = $(AM_CPPFLAGS) $(ZLIB_CFLAGS) $(LZO_CFLAGS)
@ -27,36 +11,45 @@
 
 jffs2reader_SOURCES = jffsX-utils/jffs2reader.c	include/mtd/jffs2-user.h
 jffs2reader_LDADD = libmtd.a $(ZLIB_LIBS) $(LZO_LIBS)
+@@ -33,6 +34,14 @@ if WITH_ZLIB
+ mkfs_jffs2_SOURCES += jffsX-utils/compr_zlib.c
+ endif
+ 
+if WITH_LZMA
+mkfs_jffs2_SOURCES += \
+	jffsX-utils/compr_lzma.c \
+	jffsX-utils/lzma/LzFind.c \
+	jffsX-utils/lzma/LzmaEnc.c \
+	jffsX-utils/lzma/LzmaDec.c
+endif
+
+ EXTRA_DIST += jffsX-utils/device_table.txt jffsX-utils/mkfs.jffs2.1
+ 
+ dist_man1_MANS += jffsX-utils/mkfs.jffs2.1
 --- a/jffsX-utils/compr.c
 +++ b/jffsX-utils/compr.c
@@ -520,6 +520,9 @@ int jffs2_compressors_init(void)
- #ifdef CONFIG_JFFS2_LZO
+ #ifdef WITH_LZO
 	jffs2_lzo_init();
 #endif
-+#ifdef CONFIG_JFFS2_LZMA
+#ifdef WITH_LZMA
 +	jffs2_lzma_init();
 +#endif
 	return 0;
 }
 
@@ -534,5 +537,8 @@ int jffs2_compressors_exit(void)
- #ifdef CONFIG_JFFS2_LZO
+ #ifdef WITH_LZO
 	jffs2_lzo_exit();
 #endif
-+#ifdef CONFIG_JFFS2_LZMA
+#ifdef WITH_LZMA
 +	jffs2_lzma_exit();
 +#endif
 	return 0;
 }
 --- a/jffsX-utils/compr.h
 +++ b/jffsX-utils/compr.h
-@@ -18,13 +18,14 @@
- 
- #define CONFIG_JFFS2_ZLIB
- #define CONFIG_JFFS2_RTIME
-#define CONFIG_JFFS2_LZO
-+#define CONFIG_JFFS2_LZMA
- 
+@@ -21,8 +21,9 @@
 #define JFFS2_RUBINMIPS_PRIORITY 10
 #define JFFS2_DYNRUBIN_PRIORITY  20
 #define JFFS2_RTIME_PRIORITY     50
@ -68,11 +61,11 @@
 
 #define JFFS2_COMPR_MODE_NONE       0
 #define JFFS2_COMPR_MODE_PRIORITY   1
-@@ -115,5 +116,10 @@ void jffs2_rtime_exit(void);
+@@ -113,5 +114,10 @@ void jffs2_rtime_exit(void);
 int jffs2_lzo_init(void);
 void jffs2_lzo_exit(void);
 #endif
-+#ifdef CONFIG_JFFS2_LZMA
+#ifdef WITH_LZMA
 +int jffs2_lzma_init(void);
 +void jffs2_lzma_exit(void);
 +#endif
@ -5036,3 +5029,45 @@
 						  }
 						  break;
 					  }
+--- a/Makefile.am
+++ b/Makefile.am
+@@ -19,6 +19,10 @@ if WITH_ZSTD
+ AM_CPPFLAGS += -DWITH_ZSTD
+ endif
+ 
+if WITH_LZMA
+AM_CPPFLAGS += -DWITH_LZMA
+endif
+
+ if WITH_SELINUX
+ AM_CPPFLAGS += -DWITH_SELINUX
+ endif
+--- a/configure.ac
+++ b/configure.ac
+@@ -96,6 +96,10 @@ AC_ARG_WITH([zstd],
+ 	[AS_HELP_STRING([--with-zstd], [Support for ZSTD compression])],
+ 	[], [with_zstd="check"])
+ 
+AC_ARG_WITH([lzma],
+	[AS_HELP_STRING([--with-lzma], [Support for LZMA compression])],
+	[], [with_lzma="check"])
+
+ AC_ARG_WITH([selinux],
+ 	[AS_HELP_STRING([--with-selinux],
+ 		[Support for selinux extended attributes])],
+@@ -268,6 +272,7 @@ fi
+ AM_CONDITIONAL([WITH_LZO], [test "x$with_lzo" = "xyes"])
+ AM_CONDITIONAL([WITH_ZLIB], [test "x$with_zlib" = "xyes"])
+ AM_CONDITIONAL([WITH_ZSTD], [test "x$with_zstd" = "xyes"])
+AM_CONDITIONAL([WITH_LZMA], [test "x$with_lzma" = "xyes"])
+ AM_CONDITIONAL([WITH_XATTR], [test "x$with_xattr" = "xyes"])
+ AM_CONDITIONAL([WITH_SELINUX], [test "x$with_selinux" = "xyes"])
+ AM_CONDITIONAL([WITH_CRYPTO], [test "x$with_crypto" = "xyes"])
+@@ -312,6 +317,7 @@ AC_MSG_RESULT([
+ 	lzo support:       ${with_lzo}
+ 	zlib support:      ${with_zlib}
+ 	zstd support:      ${with_zstd}
+	lzma support:      ${with_lzma}
+ 	xattr/acl support: ${with_xattr}
+ 	SELinux support:   ${with_selinux}
+ 	fscrypt support:   ${with_crypto}