Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

include/prereq-build.mk

@@ -182,6 +182,7 @@ $(eval $(call SetupHostCommand,perl,Please install Perl 5.x, \
 	perl --version | grep "perl.*v5"))
 
 $(eval $(call SetupHostCommand,python,Please install Python >= 3.7, \
+	python3.12 -V 2>&1 | grep 'Python 3', \
 	python3.11 -V 2>&1 | grep 'Python 3', \
 	python3.10 -V 2>&1 | grep 'Python 3', \
 	python3.9 -V 2>&1 | grep 'Python 3', \
@@ -190,6 +191,7 @@ $(eval $(call SetupHostCommand,python,Please install Python >= 3.7, \
 	python3 -V 2>&1 | grep -E 'Python 3\.([7-9]|[0-9][0-9])\.?'))
 
 $(eval $(call SetupHostCommand,python3,Please install Python >= 3.7, \
+	python3.12 -V 2>&1 | grep 'Python 3', \
 	python3.11 -V 2>&1 | grep 'Python 3', \
 	python3.10 -V 2>&1 | grep 'Python 3', \
 	python3.9 -V 2>&1 | grep 'Python 3', \
@@ -199,7 +201,8 @@ $(eval $(call SetupHostCommand,python3,Please install Python >= 3.7, \
 
 $(eval $(call TestHostCommand,python3-distutils, \
 	Please install the Python3 distutils module, \
-	$(STAGING_DIR_HOST)/bin/python3 -c 'from distutils import util'))
+	printf 'from sys import version_info\nif version_info < (3, 12):\n\tfrom distutils import util' | \
+		$(STAGING_DIR_HOST)/bin/python3 -))
 
 $(eval $(call TestHostCommand,python3-stdlib, \
 	Please install the Python3 stdlib module, \

package/boot/uboot-ath79/Makefile

@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2024.07
+PKG_VERSION:=2024.10
-PKG_HASH:=f591da9ab90ef3d6b3d173766d0ddff90c4ed7330680897486117df390d83c8f
+PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0
 
 UBOOT_USE_INTREE_DTC:=1
 

package/boot/uboot-envtools/files/rockchip_armv8

@@ -11,9 +11,7 @@ touch /etc/config/ubootenv
 board=$(board_name)
 
 case "$board" in
-lyt,t68m)
+lyt,t68m|\
-	ubootenv_add_uci_config "/dev/mmcblk0" "0x3f8000" "0x8000"
-	;;
 xunlong,orangepi-r1-plus|\
 xunlong,orangepi-r1-plus-lts)
 	ubootenv_add_uci_config "/dev/mmcblk0" "0x3f8000" "0x8000"

package/boot/uboot-mediatek/patches/455-arm-provide-noncached_set_region-prototype-to-fix-build.patch

@@ -0,0 +1,43 @@
+From aab8e6cf7afbbcef60593c6b1795fa5d8e78e597 Mon Sep 17 00:00:00 2001
+From: Jonas Jelonek <jelonek.jonas@gmail.com>
+Date: Tue, 15 Oct 2024 20:02:25 +0200
+Subject: [PATCH] arm: provide noncached_set_region prototype to fix build
+
+Due to the removal of weak functions in 7d6cee2cd0 ("cmd: cache: Remove
+weak function"), uboot fails to compile after updating to v2024.10 for
+mediatek target in OpenWrt with GCC-14 with error:
+cmd/cache.c: In function 'do_dcache':
+cmd/cache.c:57:25: error: implicit declaration of function
+	'noncached_set_region' [-Wimplicit-function-declaration]
+
+Thus, provide a prototype in arm's include/asm/system.h to fix a build
+error in cmd/cache.c, since related prototypes are also located there.
+Also add an include of asm/system.h in cmd/cache.c have the function
+available there.
+
+Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
+---
+ arch/arm/include/asm/system.h | 1 +
+ cmd/cache.c                   | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -658,6 +658,7 @@ void mmu_set_region_dcache_behaviour(phy
+  * Return: 0 if OK
+  */
+ int noncached_init(void);
++void noncached_set_region(void);
+ 
+ phys_addr_t noncached_alloc(size_t size, size_t align);
+ #endif /* CONFIG_SYS_NONCACHED_MEMORY */
+--- a/cmd/cache.c
++++ b/cmd/cache.c
+@@ -10,6 +10,7 @@
+ #include <command.h>
+ #include <cpu_func.h>
+ #include <linux/compiler.h>
++#include <asm/system.h>
+ 
+ static int parse_argv(const char *);
+ 

package/firmware/linux-firmware/realtek.mk

@@ -180,7 +180,6 @@ $(eval $(call BuildPackage,rtl8852ae-firmware))
 Package/rtl8852be-firmware = $(call Package/firmware-default,RealTek RTL8852BE firmware)
 define Package/rtl8852be-firmware/install
 	$(INSTALL_DIR) $(1)/lib/firmware/rtw89
-	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852b_fw.bin $(1)/lib/firmware/rtw89
 	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852b_fw-1.bin $(1)/lib/firmware/rtw89
 endef
 $(eval $(call BuildPackage,rtl8852be-firmware))
@@ -191,3 +190,10 @@ define Package/rtl8852ce-firmware/install
 	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852c_fw.bin $(1)/lib/firmware/rtw89
 endef
 $(eval $(call BuildPackage,rtl8852ce-firmware))
+
+Package/rtl8922ae-firmware = $(call Package/firmware-default,RealTek RTL8922AE firmware)
+define Package/rtl8922ae-firmware/install
+	$(INSTALL_DIR) $(1)/lib/firmware/rtw89
+	$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8922a_fw.bin $(1)/lib/firmware/rtw89
+endef
+$(eval $(call BuildPackage,rtl8922ae-firmware))

package/kernel/mac80211/realtek.mk

@@ -4,7 +4,8 @@ PKG_DRIVERS += \
 	rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-sdio rtw88-8821c rtw88-8822b rtw88-8822c \
 	rtw88-8723x rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \
 	rtw88-8822ce rtw88-8822cu rtw88-8723de rtw88-8723ds rtw88-8723du \
-	rtw89 rtw89-pci rtw89-8851be rtw89-8852ae rtw89-8852b-common rtw89-8852be rtw89-8852ce
+	rtw89 rtw89-pci rtw89-8851be rtw89-8852ae rtw89-8852b-common \
+	rtw89-8852be rtw89-8852ce rtw89-8922ae
 
 config-$(call config_package,rtlwifi) += RTL_CARDS RTLWIFI
 config-$(call config_package,rtlwifi-pci) += RTLWIFI_PCI
@@ -56,6 +57,7 @@ config-$(call config_package,rtw89-8852ae) += RTW89_8852A RTW89_8852AE
 config-$(call config_package,rtw89-8852b-common) += RTW89_8852B_COMMON
 config-$(call config_package,rtw89-8852be) += RTW89_8852B RTW89_8852BE
 config-$(call config_package,rtw89-8852ce) += RTW89_8852C RTW89_8852CE
+config-$(call config_package,rtw89-8922ae) += RTW89_8922A RTW89_8922AE
 config-$(CONFIG_PACKAGE_RTW89_DEBUG) += RTW89_DEBUG
 config-$(CONFIG_PACKAGE_RTW89_DEBUGFS) += RTW89_DEBUGFS
 config-$(CONFIG_PACKAGE_RTW89_DEBUGMSG) += RTW89_DEBUGMSG
@@ -480,3 +482,13 @@ define KernelPackage/rtw89-8852ce
 	$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852ce.ko
   AUTOLOAD:=$(call AutoProbe,rtw89_8852ce)
 endef
+
+define KernelPackage/rtw89-8922ae
+  $(call KernelPackage/mac80211/Default)
+  TITLE:=Realtek RTL8922AE support
+  DEPENDS+= +kmod-rtw89-pci +rtl8922ae-firmware +@DRIVER_11BE_SUPPORT
+  FILES:= \
+	$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8922a.ko \
+	$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8922ae.ko
+  AUTOLOAD:=$(call AutoProbe,rtw89_8922ae)
+endef

package/system/opkg/Makefile

@@ -7,14 +7,14 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=opkg
-PKG_RELEASE:=2
+PKG_RELEASE:=1
 PKG_FLAGS:=essential
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=$(PROJECT_GIT)/project/opkg-lede.git
-PKG_SOURCE_DATE:=2022-02-24
+PKG_SOURCE_DATE:=2024-10-16
-PKG_SOURCE_VERSION:=d038e5b6d155784575f62a66a8bb7e874173e92e
+PKG_SOURCE_VERSION:=38eccbb1fd694d4798ac1baf88f9ba83d1eac616
-PKG_MIRROR_HASH:=6889f7d322996f9291f42d7d6a5877d256b91d4a01d6015cebaae9227702eb43
+PKG_MIRROR_HASH:=de58ff1c99c14789f9ba8946623c8c1e58d022e7e2a659d6f97c6fde54f2c4f4
 
 PKG_LICENSE:=GPL-2.0
 PKG_LICENSE_FILES:=COPYING

target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch

@@ -1,6 +1,6 @@
-From 49d46df79404a37685e0f32deb36506f5723e3a0 Mon Sep 17 00:00:00 2001
+From a2e1ba275eae96a8171deb19e9c7c2f5978fee7b Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 28 Aug 2024 23:52:09 +0100
+Date: Fri, 4 Oct 2024 17:18:16 +0100
 Subject: [PATCH] net: phy: aquantia: allow forcing order of MDI pairs
 
 Despite supporting Auto MDI-X, it looks like Aquantia only supports
@@ -35,6 +35,9 @@ Forcing normal pair order is required on the Adtran SDG-8733A Wi-Fi 7
 residential gateway.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/9ed760ff87d5fc456f31e407ead548bbb754497d.1728058550.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
  drivers/net/phy/aquantia/aquantia_main.c | 33 ++++++++++++++++++++++++
  1 file changed, 33 insertions(+)
@@ -74,7 +77,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf);
 +
 +	/* Do nothing in case property "marvell,mdi-cfg-order" is not present */
-+	if (ret == -EINVAL)
++	if (ret == -ENOENT)
 +		return 0;
 +
 +	if (ret)

target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch

@@ -0,0 +1,31 @@
+From ce21b8fb255ebf0b49913fb4c62741d7eb05c6f6 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 11 Oct 2024 22:28:43 +0100
+Subject: [PATCH] net: phy: aquantia: fix return value check in
+ aqr107_config_mdi()
+
+of_property_read_u32() returns -EINVAL in case the property cannot be
+found rather than -ENOENT. Fix the check to not abort probing in case
+of the property being missing, and also in case CONFIG_OF is not set
+which will result in -ENOSYS.
+
+Fixes: a2e1ba275eae ("net: phy: aquantia: allow forcing order of MDI pairs")
+Reported-by: Jon Hunter <jonathanh@nvidia.com>
+Closes: https://lore.kernel.org/all/114b4c03-5d16-42ed-945d-cf78eabea12b@nvidia.com/
+Suggested-by: Hans-Frieder Vogt <hfdevel@gmx.net>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -512,7 +512,7 @@ static int aqr107_config_mdi(struct phy_
+ 	ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf);
+ 
+ 	/* Do nothing in case property "marvell,mdi-cfg-order" is not present */
+-	if (ret == -ENOENT)
++	if (ret == -EINVAL || ret == -ENOSYS)
+ 		return 0;
+ 
+ 	if (ret)

target/linux/generic/backport-6.6/841-v6.13-net-phy-support-active-high-property-for-PHY-LEDs.patch

@@ -0,0 +1,53 @@
+From a274465cc3bef2dfd9c9ea5100848dda0a8641e1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 10 Oct 2024 13:54:19 +0100
+Subject: [PATCH 1/4] net: phy: support 'active-high' property for PHY LEDs
+
+In addition to 'active-low' and 'inactive-high-impedance' also
+support 'active-high' property for PHY LED pin configuration.
+As only either 'active-high' or 'active-low' can be set at the
+same time, WARN and return an error in case both are set.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/91598487773d768f254d5faf06cf65b13e972f0e.1728558223.git.daniel@makrotopia.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/phy_device.c | 6 ++++++
+ include/linux/phy.h          | 5 +++--
+ 2 files changed, 9 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -3219,11 +3219,17 @@ static int of_phy_led(struct phy_device
+ 	if (index > U8_MAX)
+ 		return -EINVAL;
+ 
++	if (of_property_read_bool(led, "active-high"))
++		set_bit(PHY_LED_ACTIVE_HIGH, &modes);
+ 	if (of_property_read_bool(led, "active-low"))
+ 		set_bit(PHY_LED_ACTIVE_LOW, &modes);
+ 	if (of_property_read_bool(led, "inactive-high-impedance"))
+ 		set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
+ 
++	if (WARN_ON(modes & BIT(PHY_LED_ACTIVE_LOW) &&
++		    modes & BIT(PHY_LED_ACTIVE_HIGH)))
++		return -EINVAL;
++
+ 	if (modes) {
+ 		/* Return error if asked to set polarity modes but not supported */
+ 		if (!phydev->drv->led_polarity_set)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -872,8 +872,9 @@ struct phy_led {
+ 
+ /* Modes for PHY LED configuration */
+ enum phy_led_modes {
+-	PHY_LED_ACTIVE_LOW = 0,
+-	PHY_LED_INACTIVE_HIGH_IMPEDANCE = 1,
++	PHY_LED_ACTIVE_HIGH = 0,
++	PHY_LED_ACTIVE_LOW = 1,
++	PHY_LED_INACTIVE_HIGH_IMPEDANCE = 2,
+ 
+ 	/* keep it last */
+ 	__PHY_LED_MODES_NUM,

target/linux/generic/backport-6.6/842-v6.13-net-phy-aquantia-correctly-describe-LED-polarity-ove.patch

@@ -0,0 +1,108 @@
+From 9d55e68b19f222e6334ef4021c5527998f5ab537 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 10 Oct 2024 13:55:00 +0100
+Subject: [PATCH 2/4] net: phy: aquantia: correctly describe LED polarity
+ override
+
+Use newly defined 'active-high' property to set the
+VEND1_GLOBAL_LED_DRIVE_VDD bit and let 'active-low' clear that bit. This
+reflects the technical reality which was inverted in the previous
+description in which the 'active-low' property was used to actually set
+the VEND1_GLOBAL_LED_DRIVE_VDD bit, which means that VDD (ie. supply
+voltage) of the LED is driven rather than GND.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/86a413b4387c42dcb54f587cc2433a06f16aae83.1728558223.git.daniel@makrotopia.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/aquantia/aquantia.h      |  1 +
+ drivers/net/phy/aquantia/aquantia_leds.c | 19 ++++++++++++++-----
+ drivers/net/phy/aquantia/aquantia_main.c | 12 +++++++++---
+ 3 files changed, 24 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -169,6 +169,7 @@ static const struct aqr107_hw_stat aqr10
+ struct aqr107_priv {
+ 	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+ 	unsigned long leds_active_low;
++	unsigned long leds_active_high;
+ };
+ 
+ #if IS_REACHABLE(CONFIG_HWMON)
+--- a/drivers/net/phy/aquantia/aquantia_leds.c
++++ b/drivers/net/phy/aquantia/aquantia_leds.c
+@@ -121,13 +121,13 @@ int aqr_phy_led_active_low_set(struct ph
+ {
+ 	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
+ 			      VEND1_GLOBAL_LED_DRIVE_VDD,
+-			      enable ? VEND1_GLOBAL_LED_DRIVE_VDD : 0);
++			      enable ? 0 : VEND1_GLOBAL_LED_DRIVE_VDD);
+ }
+ 
+ int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes)
+ {
++	bool force_active_low = false, force_active_high = false;
+ 	struct aqr107_priv *priv = phydev->priv;
+-	bool active_low = false;
+ 	u32 mode;
+ 
+ 	if (index >= AQR_MAX_LEDS)
+@@ -136,7 +136,10 @@ int aqr_phy_led_polarity_set(struct phy_
+ 	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ 		switch (mode) {
+ 		case PHY_LED_ACTIVE_LOW:
+-			active_low = true;
++			force_active_low = true;
++			break;
++		case PHY_LED_ACTIVE_HIGH:
++			force_active_high = true;
+ 			break;
+ 		default:
+ 			return -EINVAL;
+@@ -144,8 +147,14 @@ int aqr_phy_led_polarity_set(struct phy_
+ 	}
+ 
+ 	/* Save LED driver vdd state to restore on SW reset */
+-	if (active_low)
++	if (force_active_low)
+ 		priv->leds_active_low |= BIT(index);
+ 
+-	return aqr_phy_led_active_low_set(phydev, index, active_low);
++	if (force_active_high)
++		priv->leds_active_high |= BIT(index);
++
++	if (force_active_high || force_active_low)
++		return aqr_phy_led_active_low_set(phydev, index, force_active_low);
++
++	unreachable();
+ }
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -529,7 +529,7 @@ static int aqr107_config_mdi(struct phy_
+ static int aqr107_config_init(struct phy_device *phydev)
+ {
+ 	struct aqr107_priv *priv = phydev->priv;
+-	u32 led_active_low;
++	u32 led_idx;
+ 	int ret;
+ 
+ 	/* Check that the PHY interface type is compatible */
+@@ -569,8 +569,14 @@ static int aqr107_config_init(struct phy
+ 		return ret;
+ 
+ 	/* Restore LED polarity state after reset */
+-	for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) {
+-		ret = aqr_phy_led_active_low_set(phydev, led_active_low, true);
++	for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) {
++		ret = aqr_phy_led_active_low_set(phydev, led_idx, true);
++		if (ret)
++			return ret;
++	}
++
++	for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) {
++		ret = aqr_phy_led_active_low_set(phydev, led_idx, false);
+ 		if (ret)
+ 			return ret;
+ 	}

target/linux/generic/backport-6.6/843-v6.13-net-phy-mxl-gpy-add-basic-LED-support.patch

@@ -0,0 +1,332 @@
+From 78997e9a5e4d8a4df561e083a92c91ae23010e07 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 1 Oct 2024 01:17:18 +0100
+Subject: [PATCH] net: phy: mxl-gpy: add basic LED support
+
+Add basic support for LEDs connected to MaxLinear GPY2xx and GPY115 PHYs.
+The PHYs allow up to 4 LEDs to be connected.
+Implement controlling LEDs in software as well as netdev trigger offloading
+and LED polarity setup.
+
+The hardware claims to support 16 PWM brightness levels but there is no
+documentation on how to use that feature, hence this is not supported.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/b6ec9050339f8244ff898898a1cecc33b13a48fc.1727741563.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/mxl-gpy.c | 218 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 218 insertions(+)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -38,6 +38,7 @@
+ #define PHY_MIISTAT		0x18	/* MII state */
+ #define PHY_IMASK		0x19	/* interrupt mask */
+ #define PHY_ISTAT		0x1A	/* interrupt status */
++#define PHY_LED			0x1B	/* LEDs */
+ #define PHY_FWV			0x1E	/* firmware version */
+ 
+ #define PHY_MIISTAT_SPD_MASK	GENMASK(2, 0)
+@@ -61,6 +62,11 @@
+ 				 PHY_IMASK_ADSC | \
+ 				 PHY_IMASK_ANC)
+ 
++#define GPY_MAX_LEDS		4
++#define PHY_LED_POLARITY(idx)	BIT(12 + (idx))
++#define PHY_LED_HWCONTROL(idx)	BIT(8 + (idx))
++#define PHY_LED_ON(idx)		BIT(idx)
++
+ #define PHY_FWV_REL_MASK	BIT(15)
+ #define PHY_FWV_MAJOR_MASK	GENMASK(11, 8)
+ #define PHY_FWV_MINOR_MASK	GENMASK(7, 0)
+@@ -72,6 +78,23 @@
+ #define PHY_MDI_MDI_X_CD	0x1
+ #define PHY_MDI_MDI_X_CROSS	0x0
+ 
++/* LED */
++#define VSPEC1_LED(idx)		(1 + (idx))
++#define VSPEC1_LED_BLINKS	GENMASK(15, 12)
++#define VSPEC1_LED_PULSE	GENMASK(11, 8)
++#define VSPEC1_LED_CON		GENMASK(7, 4)
++#define VSPEC1_LED_BLINKF	GENMASK(3, 0)
++
++#define VSPEC1_LED_LINK10	BIT(0)
++#define VSPEC1_LED_LINK100	BIT(1)
++#define VSPEC1_LED_LINK1000	BIT(2)
++#define VSPEC1_LED_LINK2500	BIT(3)
++
++#define VSPEC1_LED_TXACT	BIT(0)
++#define VSPEC1_LED_RXACT	BIT(1)
++#define VSPEC1_LED_COL		BIT(2)
++#define VSPEC1_LED_NO_CON	BIT(3)
++
+ /* SGMII */
+ #define VSPEC1_SGMII_CTRL	0x08
+ #define VSPEC1_SGMII_CTRL_ANEN	BIT(12)		/* Aneg enable */
+@@ -827,6 +850,156 @@ static int gpy115_loopback(struct phy_de
+ 	return genphy_soft_reset(phydev);
+ }
+ 
++static int gpy_led_brightness_set(struct phy_device *phydev,
++				  u8 index, enum led_brightness value)
++{
++	int ret;
++
++	if (index >= GPY_MAX_LEDS)
++		return -EINVAL;
++
++	/* clear HWCONTROL and set manual LED state */
++	ret = phy_modify(phydev, PHY_LED,
++			 ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) |
++			 PHY_LED_ON(index),
++			 (value == LED_OFF) ? 0 : PHY_LED_ON(index));
++	if (ret)
++		return ret;
++
++	/* ToDo: set PWM brightness */
++
++	/* clear HW LED setup */
++	if (value == LED_OFF)
++		return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0);
++	else
++		return 0;
++}
++
++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
++						 BIT(TRIGGER_NETDEV_LINK_100) |
++						 BIT(TRIGGER_NETDEV_LINK_1000) |
++						 BIT(TRIGGER_NETDEV_LINK_2500) |
++						 BIT(TRIGGER_NETDEV_RX) |
++						 BIT(TRIGGER_NETDEV_TX));
++
++static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				   unsigned long rules)
++{
++	if (index >= GPY_MAX_LEDS)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~supported_triggers)
++		return -EOPNOTSUPP;
++
++	return 0;
++}
++
++static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index,
++				  unsigned long *rules)
++{
++	int val;
++
++	if (index >= GPY_MAX_LEDS)
++		return -EINVAL;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index));
++	if (val < 0)
++		return val;
++
++	if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_10);
++
++	if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_100);
++
++	if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
++
++	if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_2500);
++
++	if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 |
++					       VSPEC1_LED_LINK100 |
++					       VSPEC1_LED_LINK1000 |
++					       VSPEC1_LED_LINK2500))
++		*rules |= BIT(TRIGGER_NETDEV_LINK);
++
++	if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT)
++		*rules |= BIT(TRIGGER_NETDEV_TX);
++
++	if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT)
++		*rules |= BIT(TRIGGER_NETDEV_RX);
++
++	return 0;
++}
++
++static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index,
++				  unsigned long rules)
++{
++	u16 val = 0;
++	int ret;
++
++	if (index >= GPY_MAX_LEDS)
++		return -EINVAL;
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_10))
++		val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10);
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_100))
++		val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100);
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_1000))
++		val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000);
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_2500))
++		val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500);
++
++	if (rules & BIT(TRIGGER_NETDEV_TX))
++		val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT);
++
++	if (rules & BIT(TRIGGER_NETDEV_RX))
++		val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT);
++
++	/* allow RX/TX pulse without link indication */
++	if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) &&
++	    !(val & VSPEC1_LED_CON))
++		val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val);
++	if (ret)
++		return ret;
++
++	return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index));
++}
++
++static int gpy_led_polarity_set(struct phy_device *phydev, int index,
++				unsigned long modes)
++{
++	bool active_low = false;
++	u32 mode;
++
++	if (index >= GPY_MAX_LEDS)
++		return -EINVAL;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	return phy_modify(phydev, PHY_LED, PHY_LED_POLARITY(index),
++			  active_low ? 0 : PHY_LED_POLARITY(index));
++}
++
+ static struct phy_driver gpy_drivers[] = {
+ 	{
+ 		PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
+@@ -844,6 +1017,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		.phy_id		= PHY_ID_GPY115B,
+@@ -862,6 +1040,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy115_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
+@@ -879,6 +1062,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy115_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		.phy_id		= PHY_ID_GPY211B,
+@@ -897,6 +1085,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
+@@ -914,6 +1107,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		.phy_id		= PHY_ID_GPY212B,
+@@ -932,6 +1130,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
+@@ -949,6 +1152,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		.phy_id		= PHY_ID_GPY215B,
+@@ -967,6 +1175,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
+@@ -984,6 +1197,11 @@ static struct phy_driver gpy_drivers[] =
+ 		.set_wol	= gpy_set_wol,
+ 		.get_wol	= gpy_get_wol,
+ 		.set_loopback	= gpy_loopback,
++		.led_brightness_set = gpy_led_brightness_set,
++		.led_hw_is_supported = gpy_led_hw_is_supported,
++		.led_hw_control_get = gpy_led_hw_control_get,
++		.led_hw_control_set = gpy_led_hw_control_set,
++		.led_polarity_set = gpy_led_polarity_set,
+ 	},
+ 	{
+ 		PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),

target/linux/generic/backport-6.6/844-v6.13-net-phy-mxl-gpy-add-missing-support-for-TRIGGER_NETD.patch

@@ -0,0 +1,28 @@
+From f95b4725e796b12e5f347a0d161e1d3843142aa8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 4 Oct 2024 16:56:35 +0100
+Subject: [PATCH] net: phy: mxl-gpy: add missing support for
+ TRIGGER_NETDEV_LINK_10
+
+The PHY also support 10MBit/s links as well as the corresponding link
+indication trigger to be offloaded. Add TRIGGER_NETDEV_LINK_10 to the
+supported triggers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/cc5da0a989af8b0d49d823656d88053c4de2ab98.1728057367.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/mxl-gpy.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -876,6 +876,7 @@ static int gpy_led_brightness_set(struct
+ }
+ 
+ static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
++						 BIT(TRIGGER_NETDEV_LINK_10) |
+ 						 BIT(TRIGGER_NETDEV_LINK_100) |
+ 						 BIT(TRIGGER_NETDEV_LINK_1000) |
+ 						 BIT(TRIGGER_NETDEV_LINK_2500) |

target/linux/generic/backport-6.6/845-v6.13-net-phy-mxl-gpy-correctly-describe-LED-polarity.patch

@@ -0,0 +1,58 @@
+From eb89c79c1b8f17fc1611540768678e60df89ac42 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 10 Oct 2024 13:55:17 +0100
+Subject: [PATCH 3/4] net: phy: mxl-gpy: correctly describe LED polarity
+
+According the datasheet covering the LED (0x1b) register:
+0B Active High LEDx pin driven high when activated
+1B Active Low LEDx pin driven low when activated
+
+Make use of the now available 'active-high' property and correctly
+reflect the polarity setting which was previously inverted.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/180ccafa837f09908b852a8a874a3808c5ecd2d0.1728558223.git.daniel@makrotopia.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/mxl-gpy.c | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -981,7 +981,7 @@ static int gpy_led_hw_control_set(struct
+ static int gpy_led_polarity_set(struct phy_device *phydev, int index,
+ 				unsigned long modes)
+ {
+-	bool active_low = false;
++	bool force_active_low = false, force_active_high = false;
+ 	u32 mode;
+ 
+ 	if (index >= GPY_MAX_LEDS)
+@@ -990,15 +990,23 @@ static int gpy_led_polarity_set(struct p
+ 	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ 		switch (mode) {
+ 		case PHY_LED_ACTIVE_LOW:
+-			active_low = true;
++			force_active_low = true;
++			break;
++		case PHY_LED_ACTIVE_HIGH:
++			force_active_high = true;
+ 			break;
+ 		default:
+ 			return -EINVAL;
+ 		}
+ 	}
+ 
+-	return phy_modify(phydev, PHY_LED, PHY_LED_POLARITY(index),
+-			  active_low ? 0 : PHY_LED_POLARITY(index));
++	if (force_active_low)
++		return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
++
++	if (force_active_high)
++		return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index));
++
++	unreachable();
+ }
+ 
+ static struct phy_driver gpy_drivers[] = {

target/linux/generic/backport-6.6/846-v6.13-net-phy-intel-xway-add-support-for-PHY-LEDs.patch

@@ -0,0 +1,379 @@
+From 1758af47b98c17da464cb45f476875150955dd48 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 10 Oct 2024 13:55:29 +0100
+Subject: [PATCH 4/4] net: phy: intel-xway: add support for PHY LEDs
+
+The intel-xway PHY driver predates the PHY LED framework and currently
+initializes all LED pins to equal default values.
+
+Add PHY LED functions to the drivers and don't set default values if
+LEDs are defined in device tree.
+
+According the datasheets 3 LEDs are supported on all Intel XWAY PHYs.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/81f4717ab9acf38f3239727a4540ae96fd01109b.1728558223.git.daniel@makrotopia.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/intel-xway.c | 253 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 244 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/phy/intel-xway.c
++++ b/drivers/net/phy/intel-xway.c
+@@ -151,6 +151,13 @@
+ #define XWAY_MMD_LED3H			0x01E8
+ #define XWAY_MMD_LED3L			0x01E9
+ 
++#define XWAY_GPHY_MAX_LEDS		3
++#define XWAY_GPHY_LED_INV(idx)		BIT(12 + (idx))
++#define XWAY_GPHY_LED_EN(idx)		BIT(8 + (idx))
++#define XWAY_GPHY_LED_DA(idx)		BIT(idx)
++#define XWAY_MMD_LEDxH(idx)		(XWAY_MMD_LED0H + 2 * (idx))
++#define XWAY_MMD_LEDxL(idx)		(XWAY_MMD_LED0L + 2 * (idx))
++
+ #define PHY_ID_PHY11G_1_3		0x030260D1
+ #define PHY_ID_PHY22F_1_3		0x030260E1
+ #define PHY_ID_PHY11G_1_4		0xD565A400
+@@ -229,20 +236,12 @@ static int xway_gphy_rgmii_init(struct p
+ 			  XWAY_MDIO_MIICTRL_TXSKEW_MASK, val);
+ }
+ 
+-static int xway_gphy_config_init(struct phy_device *phydev)
++static int xway_gphy_init_leds(struct phy_device *phydev)
+ {
+ 	int err;
+ 	u32 ledxh;
+ 	u32 ledxl;
+ 
+-	/* Mask all interrupts */
+-	err = phy_write(phydev, XWAY_MDIO_IMASK, 0);
+-	if (err)
+-		return err;
+-
+-	/* Clear all pending interrupts */
+-	phy_read(phydev, XWAY_MDIO_ISTAT);
+-
+ 	/* Ensure that integrated led function is enabled for all leds */
+ 	err = phy_write(phydev, XWAY_MDIO_LED,
+ 			XWAY_MDIO_LED_LED0_EN |
+@@ -276,6 +275,26 @@ static int xway_gphy_config_init(struct
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
+ 
++	return 0;
++}
++
++static int xway_gphy_config_init(struct phy_device *phydev)
++{
++	struct device_node *np = phydev->mdio.dev.of_node;
++	int err;
++
++	/* Mask all interrupts */
++	err = phy_write(phydev, XWAY_MDIO_IMASK, 0);
++	if (err)
++		return err;
++
++	/* Use default LED configuration if 'leds' node isn't defined */
++	if (!of_get_child_by_name(np, "leds"))
++		xway_gphy_init_leds(phydev);
++
++	/* Clear all pending interrupts */
++	phy_read(phydev, XWAY_MDIO_ISTAT);
++
+ 	err = xway_gphy_rgmii_init(phydev);
+ 	if (err)
+ 		return err;
+@@ -347,6 +366,172 @@ static irqreturn_t xway_gphy_handle_inte
+ 	return IRQ_HANDLED;
+ }
+ 
++static int xway_gphy_led_brightness_set(struct phy_device *phydev,
++					u8 index, enum led_brightness value)
++{
++	int ret;
++
++	if (index >= XWAY_GPHY_MAX_LEDS)
++		return -EINVAL;
++
++	/* clear EN and set manual LED state */
++	ret = phy_modify(phydev, XWAY_MDIO_LED,
++			 ((value == LED_OFF) ? XWAY_GPHY_LED_EN(index) : 0) |
++			 XWAY_GPHY_LED_DA(index),
++			 (value == LED_OFF) ? 0 : XWAY_GPHY_LED_DA(index));
++	if (ret)
++		return ret;
++
++	/* clear HW LED setup */
++	if (value == LED_OFF) {
++		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), 0);
++		if (ret)
++			return ret;
++
++		return phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), 0);
++	} else {
++		return 0;
++	}
++}
++
++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
++						 BIT(TRIGGER_NETDEV_LINK_10) |
++						 BIT(TRIGGER_NETDEV_LINK_100) |
++						 BIT(TRIGGER_NETDEV_LINK_1000) |
++						 BIT(TRIGGER_NETDEV_RX) |
++						 BIT(TRIGGER_NETDEV_TX));
++
++static int xway_gphy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++					 unsigned long rules)
++{
++	if (index >= XWAY_GPHY_MAX_LEDS)
++		return -EINVAL;
++
++	/* activity triggers are not possible without combination with a link
++	 * trigger.
++	 */
++	if (rules & (BIT(TRIGGER_NETDEV_RX) | BIT(TRIGGER_NETDEV_TX)) &&
++	    !(rules & (BIT(TRIGGER_NETDEV_LINK) |
++		       BIT(TRIGGER_NETDEV_LINK_10) |
++		       BIT(TRIGGER_NETDEV_LINK_100) |
++		       BIT(TRIGGER_NETDEV_LINK_1000))))
++		return -EOPNOTSUPP;
++
++	/* All other combinations of the supported triggers are allowed */
++	if (rules & ~supported_triggers)
++		return -EOPNOTSUPP;
++
++	return 0;
++}
++
++static int xway_gphy_led_hw_control_get(struct phy_device *phydev, u8 index,
++					unsigned long *rules)
++{
++	int lval, hval;
++
++	if (index >= XWAY_GPHY_MAX_LEDS)
++		return -EINVAL;
++
++	hval = phy_read_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index));
++	if (hval < 0)
++		return hval;
++
++	lval = phy_read_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index));
++	if (lval < 0)
++		return lval;
++
++	if (hval & XWAY_MMD_LEDxH_CON_LINK10)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_10);
++
++	if (hval & XWAY_MMD_LEDxH_CON_LINK100)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_100);
++
++	if (hval & XWAY_MMD_LEDxH_CON_LINK1000)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
++
++	if ((hval & XWAY_MMD_LEDxH_CON_LINK10) &&
++	    (hval & XWAY_MMD_LEDxH_CON_LINK100) &&
++	    (hval & XWAY_MMD_LEDxH_CON_LINK1000))
++		*rules |= BIT(TRIGGER_NETDEV_LINK);
++
++	if (lval & XWAY_MMD_LEDxL_PULSE_TXACT)
++		*rules |= BIT(TRIGGER_NETDEV_TX);
++
++	if (lval & XWAY_MMD_LEDxL_PULSE_RXACT)
++		*rules |= BIT(TRIGGER_NETDEV_RX);
++
++	return 0;
++}
++
++static int xway_gphy_led_hw_control_set(struct phy_device *phydev, u8 index,
++					unsigned long rules)
++{
++	u16 hval = 0, lval = 0;
++	int ret;
++
++	if (index >= XWAY_GPHY_MAX_LEDS)
++		return -EINVAL;
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_10))
++		hval |= XWAY_MMD_LEDxH_CON_LINK10;
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_100))
++		hval |= XWAY_MMD_LEDxH_CON_LINK100;
++
++	if (rules & BIT(TRIGGER_NETDEV_LINK) ||
++	    rules & BIT(TRIGGER_NETDEV_LINK_1000))
++		hval |= XWAY_MMD_LEDxH_CON_LINK1000;
++
++	if (rules & BIT(TRIGGER_NETDEV_TX))
++		lval |= XWAY_MMD_LEDxL_PULSE_TXACT;
++
++	if (rules & BIT(TRIGGER_NETDEV_RX))
++		lval |= XWAY_MMD_LEDxL_PULSE_RXACT;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), hval);
++	if (ret)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), lval);
++	if (ret)
++		return ret;
++
++	return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_EN(index));
++}
++
++static int xway_gphy_led_polarity_set(struct phy_device *phydev, int index,
++				      unsigned long modes)
++{
++	bool force_active_low = false, force_active_high = false;
++	u32 mode;
++
++	if (index >= XWAY_GPHY_MAX_LEDS)
++		return -EINVAL;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			force_active_low = true;
++			break;
++		case PHY_LED_ACTIVE_HIGH:
++			force_active_high = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	if (force_active_low)
++		return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index));
++
++	if (force_active_high)
++		return phy_clear_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index));
++
++	unreachable();
++}
++
+ static struct phy_driver xway_gphy[] = {
+ 	{
+ 		.phy_id		= PHY_ID_PHY11G_1_3,
+@@ -359,6 +544,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY22F_1_3,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -370,6 +560,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY11G_1_4,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -381,6 +576,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY22F_1_4,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -392,6 +592,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY11G_1_5,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -402,6 +607,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY22F_1_5,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -412,6 +622,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY11G_VR9_1_1,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -422,6 +637,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY22F_VR9_1_1,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -432,6 +652,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY11G_VR9_1_2,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -442,6 +667,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	}, {
+ 		.phy_id		= PHY_ID_PHY22F_VR9_1_2,
+ 		.phy_id_mask	= 0xffffffff,
+@@ -452,6 +682,11 @@ static struct phy_driver xway_gphy[] = {
+ 		.config_intr	= xway_gphy_config_intr,
+ 		.suspend	= genphy_suspend,
+ 		.resume		= genphy_resume,
++		.led_brightness_set = xway_gphy_led_brightness_set,
++		.led_hw_is_supported = xway_gphy_led_hw_is_supported,
++		.led_hw_control_get = xway_gphy_led_hw_control_get,
++		.led_hw_control_set = xway_gphy_led_hw_control_set,
++		.led_polarity_set = xway_gphy_led_polarity_set,
+ 	},
+ };
+ module_phy_driver(xway_gphy);

target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch

@@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  static int aqr_config_intr(struct phy_device *phydev)
  {
  	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -848,7 +916,7 @@ static struct phy_driver aqr_driver[] =
+@@ -854,7 +922,7 @@ static struct phy_driver aqr_driver[] =
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
  	.name		= "Aquantia AQR112",
  	.probe		= aqr107_probe,
@@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  	.config_intr	= aqr_config_intr,
  	.handle_interrupt = aqr_handle_interrupt,
  	.get_tunable    = aqr107_get_tunable,
-@@ -871,7 +939,7 @@ static struct phy_driver aqr_driver[] =
+@@ -877,7 +945,7 @@ static struct phy_driver aqr_driver[] =
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
  	.name		= "Aquantia AQR412",
  	.probe		= aqr107_probe,

target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch

@@ -21,7 +21,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -1055,6 +1057,30 @@ static struct phy_driver aqr_driver[] =
+@@ -1061,6 +1063,30 @@ static struct phy_driver aqr_driver[] =
  	.led_hw_control_get = aqr_phy_led_hw_control_get,
  	.led_polarity_set = aqr_phy_led_polarity_set,
  },
@@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  };
  
  module_phy_driver(aqr_driver);
-@@ -1075,6 +1101,8 @@ static struct mdio_device_id __maybe_unu
+@@ -1081,6 +1107,8 @@ static struct mdio_device_id __maybe_unu
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },

target/linux/generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch

@@ -31,45 +31,21 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  #include <linux/phy.h>
  #include <linux/polynomial.h>
  #include <linux/property.h>
-@@ -38,6 +39,7 @@
+@@ -293,10 +294,39 @@ out:
- #define PHY_MIISTAT		0x18	/* MII state */
- #define PHY_IMASK		0x19	/* interrupt mask */
- #define PHY_ISTAT		0x1A	/* interrupt status */
-+#define PHY_LED			0x1B	/* LED control */
- #define PHY_FWV			0x1E	/* firmware version */
- 
- #define PHY_MIISTAT_SPD_MASK	GENMASK(2, 0)
-@@ -61,10 +63,15 @@
- 				 PHY_IMASK_ADSC | \
- 				 PHY_IMASK_ANC)
- 
-+#define PHY_LED_NUM_LEDS	4
-+
- #define PHY_FWV_REL_MASK	BIT(15)
- #define PHY_FWV_MAJOR_MASK	GENMASK(11, 8)
- #define PHY_FWV_MINOR_MASK	GENMASK(7, 0)
- 
-+/* LED */
-+#define VSPEC1_LED(x)		(0x1 + x)
-+
- #define PHY_PMA_MGBT_POLARITY	0x82
- #define PHY_MDI_MDI_X_MASK	GENMASK(1, 0)
- #define PHY_MDI_MDI_X_NORMAL	0x3
-@@ -270,10 +277,39 @@ out:
  	return ret;
  }
  
 +static int gpy_led_write(struct phy_device *phydev)
 +{
 +	struct device_node *node = phydev->mdio.dev.of_node;
-+	u32 led_regs[PHY_LED_NUM_LEDS];
++	u32 led_regs[GPY_MAX_LEDS];
 +	int i, ret;
 +	u16 val = 0xff00;
 +
 +	if (!IS_ENABLED(CONFIG_OF_MDIO))
 +		return 0;
 +
-+	if (of_property_read_u32_array(node, "mxl,led-config", led_regs, PHY_LED_NUM_LEDS))
++	if (of_property_read_u32_array(node, "mxl,led-config", led_regs, GPY_MAX_LEDS))
 +		return 0;
 +
 +	if (of_property_read_bool(node, "mxl,led-drive-vdd"))
@@ -79,7 +55,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 +	phy_write(phydev, PHY_LED, val);
 +
 +	/* Write LED register values */
-+	for (i = 0; i < PHY_LED_NUM_LEDS; i++) {
++	for (i = 0; i < GPY_MAX_LEDS; i++) {
 +		ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(i), (u16)led_regs[i]);
 +		if (ret < 0)
 +			return ret;

target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch

@@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  			sysfs_remove_link(&dev->dev.kobj, "phydev");
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -979,6 +979,12 @@ struct phy_driver {
+@@ -980,6 +980,12 @@ struct phy_driver {
  	/** @handle_interrupt: Override default interrupt handling */
  	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
  

target/linux/generic/pending-6.6/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch

@@ -1,4 +1,4 @@
-From 9e1a0d2006bc108b239b5bc00b42c2a8cc651217 Mon Sep 17 00:00:00 2001
+From 4e432e530db0056450fbc4a3cee793f16adc39a7 Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
 Date: Tue, 8 Oct 2024 23:58:41 +0100
 Subject: [PATCH] net: phy: populate host_interfaces when attaching PHY
@@ -15,18 +15,39 @@ full-duplex only.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 ---
- drivers/net/phy/phylink.c | 7 +++++++
+ drivers/net/phy/phylink.c | 21 ++++++++++++++++++++-
- 1 file changed, 7 insertions(+)
+ 1 file changed, 20 insertions(+), 1 deletion(-)
 
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -2044,6 +2044,13 @@ int phylink_fwnode_phy_connect(struct ph
+@@ -2017,7 +2017,7 @@ int phylink_fwnode_phy_connect(struct ph
+ {
+ 	struct fwnode_handle *phy_fwnode;
+ 	struct phy_device *phy_dev;
+-	int ret;
++	int i, ret;
+ 
+ 	/* Fixed links and 802.3z are handled without needing a PHY */
+ 	if (pl->cfg_link_an_mode == MLO_AN_FIXED ||
+@@ -2044,6 +2044,25 @@ int phylink_fwnode_phy_connect(struct ph
  		pl->link_config.interface = pl->link_interface;
  	}
  
-+	/* Assume SerDes interface modes share the same lanes and allow
++	/* Assume single-lane SerDes interface modes share the same
-+	 * the PHY to switch between them
++	 * lanes and allow the PHY to switch to slower also supported modes
 +	 */
++	for (i = ARRAY_SIZE(phylink_sfp_interface_preference) - 1; i >= 0; i--) {
++		/* skip unsupported modes */
++		if (!test_bit(phylink_sfp_interface_preference[i], pl->config->supported_interfaces))
++			continue;
++
++		__set_bit(phylink_sfp_interface_preference[i], phy_dev->host_interfaces);
++
++		/* skip all faster modes */
++		if (phylink_sfp_interface_preference[i] == pl->link_interface)
++			break;
++	}
++
 +	if (test_bit(pl->link_interface, phylink_sfp_interfaces))
 +		phy_interface_and(phy_dev->host_interfaces, phylink_sfp_interfaces,
 +				  pl->config->supported_interfaces);

target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface

@@ -14,6 +14,7 @@ set_preinit_iface() {
 		ip link set eth0 up
 		ifname=eth0
 		;;
+	smartrg,sdg-841-t6|\
 	smartrg,sdg-8622|\
 	smartrg,sdg-8632|\
 	smartrg,sdg-8733a)

target/linux/mediatek/dts/mt7622-smartrg-SDG-841-t6.dts

@@ -0,0 +1,518 @@
+/*
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ * Copyright (c) 2018-2023 MediaTek Inc.
+ * Authors: Daniel Golle <daniel@makrotopia.org>
+ *          Chad Monroe <chad.monroe@adtran.com>
+ *          Ryder Lee <ryder.lee@mediatek.com>
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+	model = "Adtran SmartRG 841-t6";
+	compatible = "smartrg,sdg-841-t6", "mediatek,mt7622";
+
+	aliases {
+		ethernet0 = &gmac1;
+		label-mac-device = &gmac0;
+		led-boot = &sys_status_blue;
+		led-failsafe = &sys_status_blue;
+		led-running = &sys_status_white;
+		led-upgrade = &sys_status_blue;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=PARTLABEL=res1";
+	};
+
+	cpus {
+		cpu@0 {
+			proc-supply = <&mt6380_vcpu_reg>;
+			sram-supply = <&mt6380_vm_reg>;
+		};
+
+		cpu@1 {
+			proc-supply = <&mt6380_vcpu_reg>;
+			sram-supply = <&mt6380_vm_reg>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		wifi2g {
+			label = "wifi2g";
+			gpios = <&pio 96 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0radio";
+		};
+
+		wifi5g-1 {
+			label = "wifi5g";
+			gpios = <&pio 97 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1radio";
+		};
+
+		wifi5g-2 {
+			label = "wifi5g2";
+			gpios = <&pio 98 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy2radio";
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&pio 99 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	memory {
+		reg = <0x0 0x40000000 0x0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/delete-node/ramoops@42ff0000;
+
+		bootdata@45000000 {
+			no-map;
+			reg = <0x0 0x45000000 0x0 0x00001000>;
+		};
+
+		ramoops_reserved: ramoops1@45001000 {
+			no-map;
+			compatible = "ramoops";
+			reg = <0x0 0x45001000 0x0 0x00140000>;
+			ftrace-size = <0x20000>;
+			record-size = <0x20000>;
+			console-size = <0x20000>;
+			pmsg-size = <0x80000>;
+		};
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&eth {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth_pins>;
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		label = "wan";
+
+		nvmem-cells = <&macaddr 0x0>;
+		nvmem-cell-names = "mac-address";
+
+		phy-handle = <&phy5>;
+		phy-mode = "2500base-x";
+		phy-connection-type = "2500base-x";
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		label = "lan";
+
+		nvmem-cells = <&macaddr 0x1>;
+		nvmem-cell-names = "mac-address";
+
+		phy-handle = <&phy0>;
+		phy-mode = "rgmii-rxid";
+		rx-internal-delay-ps = <2000>;
+	};
+
+	mdio: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@0 {
+			/* PEF7071 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+				};
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_AMBER>;
+					function = LED_FUNCTION_LAN;
+				};
+			};
+		};
+
+		phy5: ethernet-phy@5 {
+			/* GPY211 */
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <5>;
+
+			interrupt-parent = <&pio>;
+			interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_AMBER>;
+					function = LED_FUNCTION_WAN;
+				};
+
+				led@2 {
+					reg = <2>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_WAN;
+				};
+			};
+		};
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	system-leds@30 {
+		compatible = "srg,sysled";
+		reg = <0x30>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sys_status_blue: system_blue@3 {
+			label = "blue";
+			reg = <3>;
+		};
+
+		sys_status_white: system_white@4 {
+			label = "white";
+			reg = <4>;
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&emmc_pins_default>;
+	pinctrl-1 = <&emmc_pins_uhs>;
+	status = "okay";
+	bus-width = <8>;
+	max-frequency = <50000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+	non-removable;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			partitions {
+				block-partition-nvram {
+					partnum = <3>;
+					partname = "nvram";
+
+					nvmem-layout {
+						compatible = "u-boot,env";
+					};
+				};
+
+				block-partition-rf {
+					partnum = <4>;
+					partname = "rf";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						eeprom0: eeprom@0 {
+							reg = <0x0 0x5000>;
+						};
+
+						eeprom1: eeprom@5000 {
+							reg = <0x5000 0x5000>;
+						};
+					};
+				};
+
+				block-partition-mfginfo {
+					partnum = <7>;
+					partname = "mfginfo";
+
+					nvmem-layout {
+						compatible = "adtran,mfginfo";
+
+						macaddr: mfg-mac {
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+			};
+		};
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+&slot0 {
+	mt7915@0,0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom0>;
+		nvmem-cell-names = "eeprom";
+		ieee80211-freq-limit = <2400000 5330000>;
+
+		band@0 {
+			/* 2.4 GHz */
+			reg = <0>;
+			nvmem-cells = <&macaddr 0x4>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		band@1 {
+			/* lower 5 GHz */
+			reg = <1>;
+			nvmem-cells = <&macaddr 0xa>;
+			nvmem-cell-names = "mac-address";
+		};
+	};
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+&slot1 {
+	mt7915@0,0 {
+		/* upper 5 GHz */
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom1>, <&macaddr 0xf>;
+		nvmem-cell-names = "eeprom", "mac-address";
+		ieee80211-freq-limit = <5490000 5835000>;
+		rdd_antenna = <0x02>;
+	};
+};
+
+&pio {
+	/* eMMC is shared pin with parallel NAND */
+	emmc_pins_default: emmc-pins-default {
+		mux {
+			function = "emmc", "emmc_rst";
+			groups = "emmc";
+		};
+
+		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+		 */
+		conf-cmd-dat {
+			pins = "NDL0", "NDL1", "NDL2",
+			       "NDL3", "NDL4", "NDL5",
+			       "NDL6", "NDL7", "NRB";
+			input-enable;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "NCLE";
+			bias-pull-down;
+		};
+	};
+
+	emmc_pins_uhs: emmc-pins-uhs {
+		mux {
+			function = "emmc";
+			groups = "emmc";
+		};
+
+		conf-cmd-dat {
+			pins = "NDL0", "NDL1", "NDL2",
+			       "NDL3", "NDL4", "NDL5",
+			       "NDL6", "NDL7", "NRB";
+			input-enable;
+			drive-strength = <4>;
+			bias-pull-up;
+		};
+
+		conf-clk {
+			pins = "NCLE";
+			drive-strength = <4>;
+			bias-pull-down;
+		};
+	};
+
+	eth_pins: eth-pins {
+		mux {
+			function = "eth";
+			groups = "mdc_mdio", "rgmii_via_gmac2";
+		};
+	};
+
+	i2c0_pins: i2c0-pins {
+		mux {
+			function = "i2c";
+			groups =  "i2c0";
+		};
+	};
+
+	pcie0_pins: pcie0-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie0_pad_perst",
+				 "pcie0_1_waken",
+				 "pcie0_1_clkreq";
+		};
+	};
+
+	pcie1_pins: pcie1-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie1_pad_perst";
+		};
+	};
+
+	pmic_bus_pins: pmic-bus-pins {
+		mux {
+			function = "pmic";
+			groups = "pmic_bus";
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		mux {
+			function = "uart";
+			groups = "uart0_0_tx_rx" ;
+		};
+	};
+
+	uart3_pins: uart3-pins {
+		mux {
+			function = "uart";
+			groups = "uart3_1_tx_rx" ;
+		};
+	};
+
+	watchdog_pins: watchdog-pins {
+		mux {
+			function = "watchdog";
+			groups = "watchdog";
+		};
+	};
+};
+
+&pwrap {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmic_bus_pins>;
+	status = "okay";
+};
+
+&ssusb {
+	vusb33-supply = <&reg_3p3v>;
+	vbus-supply = <&reg_5v>;
+	status = "okay";
+};
+
+&u3phy {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "mediatek,mt7915-bluetooth";
+		vcc-supply = <&reg_5v>;
+		pinctrl-names = "runtime";
+		pinctrl-0 = <&uart3_pins>;
+		boot-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+		current-speed = <921600>;
+	};
+};
+
+&watchdog {
+	pinctrl-names = "default";
+	pinctrl-0 = <&watchdog_pins>;
+	status = "okay";
+};

target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi

@@ -14,8 +14,7 @@
 / {
 	aliases {
 		serial0 = &uart0;
-		ethernet0 = &gmac0;
+		label-mac-device = &gmac1;
-		ethernet1 = &gmac1;
 		led-boot = &led_status_green;
 		led-failsafe = &led_status_red;
 		led-running = &led_status_white;
@@ -188,16 +187,17 @@
 	gmac0: mac@0 {
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
-
+		nvmem-cells = <&macaddr 1>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 	};
 
 	gmac1: mac@1 {
-		label = "wan";
-
 		compatible = "mediatek,eth-mac";
 		reg = <1>;
-
+		label = "wan";
+		nvmem-cells = <&macaddr 0>;
+		nvmem-cell-names = "mac-address";
 		phy-mode = "2500base-x";
 	};
 
@@ -254,6 +254,47 @@
 	no-sd;
 	no-sdio;
 	status = "okay";
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+
+			partitions {
+				block-partition-factory {
+					partname = "factory";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						eeprom_factory_0: eeprom@0 {
+							reg = <0x0 0x1000>;
+						};
+
+						eeprom_factory_a0000: eeprom@a0000 {
+							reg = <0xa0000 0x1000>;
+						};
+					};
+				};
+
+				block-partition-mfginfo {
+					partname = "mfginfo";
+
+					nvmem-layout {
+						compatible = "adtran,mfginfo";
+
+						macaddr: mfg-mac {
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+			};
+		};
+	};
 };
 
 &pcie {
@@ -266,6 +307,9 @@
 
 		radio0: mt7915@0,0 {
 			reg = <0x0000 0 0 0 0>;
+
+			nvmem-cells = <&eeprom_factory_a0000>, <&macaddr 4>;
+			nvmem-cell-names = "eeprom", "mac-address";
 		};
 	};
 };
@@ -275,9 +319,28 @@
 };
 
 &wifi {
-	status = "okay";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wf_2g_5g_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "okay";
+
+	band@0 {
+		/* 2.4 GHz */
+		reg = <0>;
+		nvmem-cells = <&macaddr 2>;
+		nvmem-cell-names = "mac-address";
+	};
+
+	band@1 {
+		/* lower 5 GHz */
+		reg = <1>;
+		nvmem-cells = <&macaddr 3>;
+		nvmem-cell-names = "mac-address";
+	};
 };
 
 &pio {

target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi

@@ -15,8 +15,7 @@
 / {
 	aliases {
 		serial0 = &uart0;
-		ethernet0 = &gmac0;
+		label-mac-device = &gmac1;
-		ethernet1 = &gmac1;
 		led-boot = &led_sys_green;
 		led-failsafe = &led_sys_blue;
 		led-running = &led_sys_white;
@@ -250,21 +249,30 @@
 };
 
 &gmac0 {
+	nvmem-cells = <&macaddr 1>;
+	nvmem-cell-names = "mac-address";
+
 	status = "okay";
 };
 
 &gmac1 {
+	nvmem-cells = <&macaddr 0>;
+	nvmem-cell-names = "mac-address";
 	label = "wan";
-	status = "okay";
 	phy-mode = "usxgmii";
+
+	status = "okay";
 };
 
 &gmac2 {
+	nvmem-cells = <&macaddr 1>;
+	nvmem-cell-names = "mac-address";
 	label = "lan1";
-	status = "okay";
 	phy-mode = "usxgmii";
 	phy-connection-type = "usxgmii";
 	phy = <&phy8>;
+
+	status = "okay";
 };
 
 &gsw_phy0 {
@@ -433,7 +441,7 @@
 				reg = <2>;
 				function = LED_FUNCTION_WAN;
 				color = <LED_COLOR_ID_WHITE>;
-				active-low;
+				active-high;
 			};
 		};
 	};
@@ -467,7 +475,7 @@
 				reg = <2>;
 				function = LED_FUNCTION_LAN;
 				color = <LED_COLOR_ID_WHITE>;
-				active-low;
+				active-high;
 			};
 		};
 	};
@@ -513,6 +521,18 @@
 						};
 					};
 				};
+
+				block-partition-mfginfo {
+					partname = "mfginfo";
+
+					nvmem-layout {
+						compatible = "adtran,mfginfo";
+
+						macaddr: mfg-mac {
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
 			};
 		};
 	};
@@ -532,6 +552,27 @@
 			nvmem-cells = <&eeprom_factory_0>;
 			nvmem-cell-names = "eeprom";
 			ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>, <5945000 7125000>;
+
+			band@0 {
+				/* 2.4 GHz */
+				reg = <0>;
+				nvmem-cells = <&macaddr 4>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			band@1 {
+				/* 5 GHz */
+				reg = <1>;
+				nvmem-cells = <&macaddr 10>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			band@2 {
+				/* 6 GHz */
+				reg = <2>;
+				nvmem-cells = <&macaddr 6>;
+				nvmem-cell-names = "mac-address";
+			};
 		};
 	};
 };

target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts

@@ -62,6 +62,8 @@
 
 &gmac1 {
 	label = "lan";
+	nvmem-cells = <&macaddr 1>;
+	nvmem-cell-names = "mac-address";
 	phy-mode = "internal";
 	phy-connection-type = "internal";
 	phy = <&int_2p5g_phy>;
@@ -69,6 +71,8 @@
 
 &gmac2 {
 	label = "wan";
+	nvmem-cells = <&macaddr 0>;
+	nvmem-cell-names = "mac-address";
 	phy-mode = "usxgmii";
 	phy-connection-type = "usxgmii";
 	phy = <&phy8>;

target/linux/mediatek/filogic/base-files/etc/board.d/01_leds

@@ -114,16 +114,16 @@ smartrg,sdg-8733a)
 	ucidef_set_led_netdev "wan-orange" "WAN" "mdio-bus:08:orange:wan" "wan" "link_100 link_1000"
 	ucidef_set_led_netdev "wan-white" "WAN" "mdio-bus:08:white:wan" "wan" "link_10000"
 	;;
-wavlink,wl-wn586x3)
-	ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx"
-	ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx"
-	ucidef_set_led_netdev "wan" "wan" "blue:wan" "eth1" "link tx rx"
-	;;
 tplink,re6000xd)
 	ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-0" "lan1" "link tx rx"
 	ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-1" "lan2" "link tx rx"
 	ucidef_set_led_netdev "eth1" "lan-3" "blue:lan-2" "eth1" "link tx rx"
 	;;
+wavlink,wl-wn586x3)
+	ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx"
+	ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx"
+	ucidef_set_led_netdev "wan" "wan" "blue:wan" "eth1" "link tx rx"
+	;;
 xiaomi,mi-router-wr30u-stock|\
 xiaomi,mi-router-wr30u-ubootmod)
 	ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx"
@@ -141,7 +141,7 @@ zyxel,ex5601-t0-ubootmod)
 	ucidef_set_led_netdev "wan" "WAN" "green:inet" "eth1" "link tx rx"
 	ucidef_set_led_netdev "wifi-24g" "WIFI-2.4G" "green:wifi24g" "phy0-ap0" "link tx rx"
 	ucidef_set_led_netdev "wifi-5g" "WIFI-5G" "green:wifi5g" "phy1-ap0" "link tx rx"
-        ;;
+	;;
 esac
 
 board_config_flush

target/linux/mediatek/filogic/base-files/etc/board.d/02_network

@@ -8,9 +8,6 @@ mediatek_setup_interfaces()
 	local board="$1"
 
 	case $board in
-	acelink,ew-7886cax)
-		ucidef_set_interface_lan "eth0" "dhcp"
-		;;
 	abt,asr3000|\
 	cmcc,rax3000m|\
 	h3c,magic-nx30-pro|\
@@ -21,6 +18,9 @@ mediatek_setup_interfaces()
 	zbtlink,zbt-z8103ax)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1
 		;;
+	acelink,ew-7886cax)
+		ucidef_set_interface_lan "eth0" "dhcp"
+		;;
 	acer,predator-w6)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1
 		;;
@@ -48,7 +48,11 @@ mediatek_setup_interfaces()
 	zyxel,ex5601-t0-ubootmod)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
 		;;
-	asus,tuf-ax6000)
+	asus,tuf-ax6000|\
+	glinet,gl-mt6000|\
+	tplink,tl-xdr4288|\
+	tplink,tl-xdr6088|\
+	tplink,tl-xtr8488)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
 		;;
 	bananapi,bpi-r3)
@@ -65,6 +69,13 @@ mediatek_setup_interfaces()
 	comfast,cf-e393ax)
 		ucidef_set_interfaces_lan_wan "lan1" eth1
 		;;
+	cudy,ap3000outdoor-v1|\
+	cudy,re3000-v1|\
+	netgear,wax220|\
+	ubnt,unifi-6-plus|\
+	zyxel,nwa50ax-pro)
+		ucidef_set_interface_lan "eth0"
+		;;
 	cudy,m3000-v1|\
 	cudy,tr3000-v1|\
 	glinet,gl-mt2500|\
@@ -78,17 +89,11 @@ mediatek_setup_interfaces()
 	dlink,aquila-pro-ai-m30-a1)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet
 		;;
-	glinet,gl-mt6000|\
-	tplink,tl-xdr4288|\
-	tplink,tl-xdr6088|\
-	tplink,tl-xtr8488)
-		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
-		;;
 	mediatek,mt7986a-rfb)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan6" "eth1 wan"
 		;;
 	mediatek,mt7986b-rfb)
-		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1
+		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 lan4" eth1
 		;;
 	mediatek,mt7988a-rfb)
 		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth2" eth1
@@ -96,13 +101,6 @@ mediatek_setup_interfaces()
 	mercusys,mr90x-v1)
 		ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1
 		;;
-	cudy,ap3000outdoor-v1|\
-	cudy,re3000-v1|\
-	netgear,wax220|\
-	ubnt,unifi-6-plus|\
-	zyxel,nwa50ax-pro)
-		ucidef_set_interface_lan "eth0"
-		;;
 	smartrg,sdg-8622|\
 	smartrg,sdg-8632|\
 	smartrg,sdg-8733a|\
@@ -168,16 +166,6 @@ mediatek_setup_macs()
 		wan_mac=$label_mac
 		lan_mac=$(macaddr_add "$label_mac" 1)
 		;;
-	smartrg,sdg-8612|\
-	smartrg,sdg-8614|\
-	smartrg,sdg-8622|\
-	smartrg,sdg-8632|\
-	smartrg,sdg-8733|\
-	smartrg,sdg-8734)
-		label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC)
-		wan_mac=$label_mac
-		lan_mac=$(macaddr_add "$label_mac" 1)
-		;;
 	xiaomi,mi-router-ax3000t|\
 	xiaomi,mi-router-ax3000t-ubootmod|\
 	xiaomi,mi-router-wr30u-stock|\

target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata

@@ -7,21 +7,6 @@
 board=$(board_name)
 
 case "$FIRMWARE" in
-"mediatek/mt7915_eeprom.bin")
-	case "$board" in
-	smartrg,sdg-8622)
-		caldata_extract_mmc "factory" 0xa0000 0x1000
-		;;
-	esac
-	;;
-"mediatek/mt7916_eeprom.bin")
-	case "$board" in
-	acer,predator-w6|\
-	smartrg,sdg-8632)
-		caldata_extract_mmc "factory" 0xa0000 0x1000
-		;;
-	esac
-	;;
 "mediatek/mt7981_eeprom_mt7976_dbdc.bin")
 	case "$board" in
 	ubnt,unifi-6-plus)
@@ -36,12 +21,6 @@ case "$FIRMWARE" in
 		ln -sf /tmp/tp_data/MT7986_EEPROM.bin \
 			/lib/firmware/$FIRMWARE
 		;;
-	smartrg,sdg-8612|\
-	smartrg,sdg-8614|\
-	smartrg,sdg-8622|\
-	smartrg,sdg-8632)
-		caldata_extract_mmc "factory" 0x0 0x1000
-		;;
 	esac
 	;;
 "mediatek/mt7986_eeprom_mt7976.bin")

target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac

@@ -127,23 +127,6 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		;;
-	smartrg,sdg-8612|\
-	smartrg,sdg-8614|\
-	smartrg,sdg-8622|\
-	smartrg,sdg-8632)
-		addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
-		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
-		;;
-	smartrg,sdg-8733|\
-	smartrg,sdg-8733a|\
-	smartrg,sdg-8734)
-		addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
-		[ "$PHYNBR" = "0" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "1" ] && macaddr_add $addr a > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "2" ] && macaddr_add $addr 6 > /sys${DEVPATH}/macaddress
-		;;
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6086|\
 	tplink,tl-xdr6088)

target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh

@@ -22,26 +22,6 @@ preinit_set_mac_address() {
 		addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0)
 		ip link set dev eth1 address "$(macaddr_add $addr 1)"
 		;;
-	smartrg,sdg-8612|\
-	smartrg,sdg-8614|\
-	smartrg,sdg-8733|\
-	smartrg,sdg-8734)
-		addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
-		lan_addr=$(macaddr_add $addr 1)
-		ip link set dev wan address "$addr"
-		ip link set dev eth0 address "$lan_addr"
-		ip link set dev lan1 address "$lan_addr"
-		ip link set dev lan2 address "$lan_addr"
-		ip link set dev lan3 address "$lan_addr"
-		ip link set dev lan4 address "$lan_addr"
-		;;
-	smartrg,sdg-8622|\
-	smartrg,sdg-8632|\
-	smartrg,sdg-8733a)
-		addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
-		ip link set dev wan address "$addr"
-		ip link set dev lan address "$(macaddr_add $addr 1)"
-		;;
 	*)
 		;;
 	esac

target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh

@@ -136,13 +136,6 @@ platform_do_upgrade() {
 		EMMC_ROOT_DEV="$(cmdline_get_var root)"
 		emmc_do_upgrade "$1"
 		;;
-	xiaomi,mi-router-ax3000t|\
-	xiaomi,mi-router-wr30u-stock|\
-	xiaomi,redmi-router-ax6000-stock)
-		CI_KERN_UBIPART=ubi_kernel
-		CI_ROOT_UBIPART=ubi
-		nand_do_upgrade "$1"
-		;;
 	unielec,u7981-01*)
 		local rootdev="$(cmdline_get_var root)"
 		rootdev="${rootdev##*/}"
@@ -160,6 +153,13 @@ platform_do_upgrade() {
 			;;
 		esac
 		;;
+	xiaomi,mi-router-ax3000t|\
+	xiaomi,mi-router-wr30u-stock|\
+	xiaomi,redmi-router-ax6000-stock)
+		CI_KERN_UBIPART=ubi_kernel
+		CI_ROOT_UBIPART=ubi
+		nand_do_upgrade "$1"
+		;;
 	*)
 		nand_do_upgrade "$1"
 		;;

target/linux/mediatek/filogic/config-6.6

@@ -313,6 +313,7 @@ CONFIG_NR_CPUS=4
 CONFIG_NVMEM=y
 CONFIG_NVMEM_BLOCK=y
 CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_ADTRAN=y
 CONFIG_NVMEM_MTK_EFUSE=y
 CONFIG_NVMEM_SYSFS=y
 CONFIG_OF=y

target/linux/mediatek/image/filogic.mk

@@ -83,6 +83,10 @@ define Build/append-gl-metadata
 	}
 endef
 
+define Build/append-openwrt-one-eeprom
+	dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@
+endef
+
 define Build/zyxel-nwa-fit-filogic
 	$(TOPDIR)/scripts/mkits-zyxel-fit-filogic.sh \
 		$@.its $@ "80 e1 ff ff ff ff ff ff ff ff"
@@ -1247,10 +1251,6 @@ define Device/openembed_som7981
 endef
 TARGET_DEVICES += openembed_som7981
 
-define Build/append-openwrt-one-eeprom
-        dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@
-endef
-
 define Device/openwrt_one
   DEVICE_VENDOR := OpenWrt
   DEVICE_MODEL := One
@@ -1610,7 +1610,6 @@ define Device/yuncore_ax835
 endef
 TARGET_DEVICES += yuncore_ax835
 
-
 define Device/zbtlink_zbt-z8102ax
   DEVICE_VENDOR := Zbtlink
   DEVICE_MODEL := ZBT-Z8102AX

target/linux/mediatek/image/mt7622.mk

@@ -52,6 +52,17 @@ define Build/mt7622-gpt
 	rm $@.tmp
 endef
 
+define Device/smartrg_sdg-841-t6
+  DEVICE_VENDOR := Adtran
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  DEVICE_MODEL := SDG-841-t6
+  DEVICE_DTS := mt7622-smartrg-SDG-841-t6
+  DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware
+endef
+TARGET_DEVICES += smartrg_sdg-841-t6
+
 define Device/bananapi_bpi-r64
   DEVICE_VENDOR := Bananapi
   DEVICE_MODEL := BPi-R64

target/linux/mediatek/mt7622/base-files/etc/board.d/01_leds

@@ -11,6 +11,12 @@ linksys,e8450-ubi|\
 netgear,wax206)
 	ucidef_set_led_netdev "wan" "WAN" "inet:blue" "wan"
 	;;
+smartrg,sdg-841-t6)
+	ucidef_set_led_netdev "lan-green" "LAN" "mdio-bus:00:green:lan" "lan" "link_1000"
+	ucidef_set_led_netdev "lan-amber" "LAN" "mdio-bus:00:amber:lan" "lan" "link_10 link_100"
+	ucidef_set_led_netdev "wan-green" "WAN" "mdio-bus:05:green:wan" "wan" "link_1000 link_2500"
+	ucidef_set_led_netdev "wan-amber" "WAN" "mdio-bus:05:amber:wan" "wan" "link_10 link_100"
+	;;
 xiaomi,redmi-router-ax6s)
 	ucidef_set_led_netdev "wan" "WAN" "blue:net" "wan"
 	;;

target/linux/mediatek/mt7622/base-files/etc/board.d/02_network

@@ -24,6 +24,9 @@ mediatek_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"
 		;;
+	smartrg,sdg-841-t6)
+		ucidef_set_interfaces_lan_wan lan wan
+		;;
 	ubnt,unifi-6-lr*)
 		ucidef_set_interface_lan "eth0"
 		;;

target/linux/mediatek/mt7622/base-files/lib/preinit/04_set_netdev_label

@@ -0,0 +1,15 @@
+set_netdev_labels() {
+	local dir
+	local label
+	local netdev
+
+	for dir in /sys/class/net/*; do
+		[ -r "$dir/of_node/label" ] || continue
+		read -r label < "$dir/of_node/label"
+		netdev="${dir##*/}"
+		[ "$netdev" = "$label" ] && continue
+		ip link set "$netdev" name "$label"
+	done
+}
+
+boot_hook_add preinit_main set_netdev_labels

target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh

@@ -44,6 +44,11 @@ platform_do_upgrade() {
 		fi
 		default_do_upgrade "$1"
 		;;
+	smartrg,sdg-841-t6)
+		CI_KERNPART="boot"
+		CI_ROOTPART="res1"
+		emmc_do_upgrade "$1"
+		;;
 	*)
 		default_do_upgrade "$1"
 		;;
@@ -68,6 +73,7 @@ platform_check_image() {
 	elecom,wrc-x3200gst3|\
 	mediatek,mt7622-rfb1-ubi|\
 	netgear,wax206|\
+	smartrg,sdg-841-t6|\
 	totolink,a8000ru)
 		nand_do_platform_check "$board" "$1"
 		return $?
@@ -91,5 +97,8 @@ platform_copy_config() {
 			emmc_copy_config
 		fi
 		;;
+	smartrg,sdg-841-t6)
+		emmc_copy_config
+		;;
 	esac
 }

target/linux/mediatek/mt7622/config-6.6

@@ -213,6 +213,7 @@ CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HWMON=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_MTK=y
 CONFIG_I2C=y
@@ -222,6 +223,7 @@ CONFIG_I2C_MT65XX=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INTEL_XWAY_PHY=y
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_HIERARCHY=y
@@ -230,7 +232,7 @@ CONFIG_IRQ_TIME_ACCOUNTING=y
 CONFIG_IRQ_WORK=y
 CONFIG_JBD2=y
 CONFIG_JUMP_LABEL=y
-# CONFIG_LEDS_SMARTRG_LED is not set
+CONFIG_LEDS_SMARTRG_LED=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
@@ -313,7 +315,9 @@ CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
+CONFIG_NVMEM_BLOCK=y
 CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_ADTRAN=y
 CONFIG_NVMEM_MTK_EFUSE=y
 CONFIG_NVMEM_SYSFS=y
 CONFIG_OF=y
@@ -464,6 +468,7 @@ CONFIG_THERMAL_GOV_BANG_BANG=y
 CONFIG_THERMAL_GOV_FAIR_SHARE=y
 CONFIG_THERMAL_GOV_STEP_WISE=y
 CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
 CONFIG_THERMAL_OF=y
 CONFIG_THERMAL_WRITABLE_TRIPS=y
 CONFIG_THREAD_INFO_IN_TASK=y

target/linux/mediatek/mt7623/config-6.6

@@ -436,6 +436,7 @@ CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=4
 CONFIG_NVMEM=y
 CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
 CONFIG_NVMEM_MTK_EFUSE=y
 # CONFIG_NVMEM_SPMI_SDAM is not set
 CONFIG_NVMEM_SYSFS=y

target/linux/mediatek/mt7629/config-6.6

@@ -239,6 +239,7 @@ CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=2
 CONFIG_NVMEM=y
 CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
 # CONFIG_NVMEM_MTK_EFUSE is not set
 CONFIG_NVMEM_SYSFS=y
 CONFIG_OF=y

target/linux/mediatek/patches-6.6/450-nvmem-add-layout-for-Adtran-devices.patch

@@ -0,0 +1,191 @@
+From c22bc82183c2dea64919f975473ec518738baa3e Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 12 Jul 2023 13:38:35 +0100
+Subject: [PATCH] nvmem: add layout for Adtran devices
+
+Adtran stores unique factory data on GPT partitions on the eMMC.
+Using blk-nvmem the 'mfginfo' partition gets exposes as NVMEM provider.
+
+Add layout driver to parse mfginfo, mainly to provide MAC addresses to
+Ethernet and wireless interfaces.
+
+Variable names are converted to lower-case and '_' is replaced with '-'
+in order to comply with the device tree node naming convention.
+The main MAC address always ends on a 0 and up to 16 addresses are
+alocated for each device to use for various interfaces.
+
+Implement post-processing function for 'MFG_MAC' variable ('mfg-mac'
+node name in device tree) adding the nvmem cell index to the least
+significant digit of the MAC address.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/nvmem/layouts/Kconfig  |   9 +++
+ drivers/nvmem/layouts/Makefile |   1 +
+ drivers/nvmem/layouts/adtran.c | 135 +++++++++++++++++++++++++++++++++
+ 3 files changed, 145 insertions(+)
+ create mode 100644 drivers/nvmem/layouts/adtran.c
+
+--- a/drivers/nvmem/layouts/Kconfig
++++ b/drivers/nvmem/layouts/Kconfig
+@@ -8,6 +8,15 @@ if NVMEM_LAYOUTS
+ 
+ menu "Layout Types"
+ 
++config NVMEM_LAYOUT_ADTRAN
++	tristate "Adtran mfginfo layout support"
++	select GENERIC_NET_UTILS
++	help
++	  Say Y here if you want to support the layout used by Adtran for
++	  mfginfo.
++
++	  If unsure, say N.
++
+ config NVMEM_LAYOUT_SL28_VPD
+ 	tristate "Kontron sl28 VPD layout support"
+ 	select CRC8
+--- a/drivers/nvmem/layouts/Makefile
++++ b/drivers/nvmem/layouts/Makefile
+@@ -6,3 +6,4 @@
+ obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o
+ obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) += onie-tlv.o
+ obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) += u-boot-env.o
++obj-$(CONFIG_NVMEM_LAYOUT_ADTRAN) += adtran.o
+--- /dev/null
++++ b/drivers/nvmem/layouts/adtran.c
+@@ -0,0 +1,135 @@
++// SPDX-License-Identifier: GPL-2.0
++#include <linux/ctype.h>
++#include <linux/etherdevice.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/nvmem-provider.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++/*
++ * Adtran devices usually come with a main MAC address ending on 0 and
++ * hence may have up to 16 MAC addresses per device.
++ * The main MAC address is stored as variable MFG_MAC in ASCII format.
++ */
++static int adtran_mac_address_pp(void *priv, const char *id, int index,
++				  unsigned int offset, void *buf,
++				  size_t bytes)
++{
++	u8 mac[ETH_ALEN];
++
++	if (WARN_ON(bytes != 3 * ETH_ALEN - 1))
++		return -EINVAL;
++
++	if (!mac_pton(buf, mac))
++		return -EINVAL;
++
++	if (index)
++		eth_addr_add(mac, index);
++
++	ether_addr_copy(buf, mac);
++
++	return 0;
++}
++
++static int adtran_add_cells(struct nvmem_layout *layout)
++{
++	struct nvmem_device *nvmem = layout->nvmem;
++	struct nvmem_cell_info info;
++	struct device_node *layout_np;
++	char mfginfo[1024], *c, *t, *p;
++	int ret = -EINVAL;
++
++	ret = nvmem_device_read(nvmem, 0, sizeof(mfginfo), mfginfo);
++	if (ret < 0)
++		return ret;
++	else if (ret != sizeof(mfginfo))
++		return -EIO;
++
++	layout_np = of_nvmem_layout_get_container(nvmem);
++	if (!layout_np)
++		return -ENOENT;
++
++	c = mfginfo;
++	while (*c != 0xff) {
++		memset(&info, 0, sizeof(info));
++		if (*c == '#')
++			goto nextline;
++
++		t = strchr(c, '=');
++		if (!t)
++			goto nextline;
++
++		*t = '\0';
++		++t;
++		info.offset = t - mfginfo;
++		/* process variable name: convert to lower-case, '_' -> '-' */
++		p = c;
++		do {
++			*p = tolower(*p);
++			if (*p == '_')
++				*p = '-';
++		} while (*++p);
++		info.name = c;
++		c = strchr(t, 0xa); /* find newline */
++		if (!c)
++			break;
++
++		info.bytes = c - t;
++		if (!strcmp(info.name, "mfg-mac")) {
++			info.raw_len = info.bytes;
++			info.bytes = ETH_ALEN;
++			info.read_post_process = adtran_mac_address_pp;
++		}
++
++		info.np = of_get_child_by_name(layout_np, info.name);
++		ret = nvmem_add_one_cell(nvmem, &info);
++		if (ret)
++			break;
++
++		++c;
++		continue;
++
++nextline:
++		c = strchr(c, 0xa); /* find newline */
++		if (!c)
++			break;
++		++c;
++	}
++
++	of_node_put(layout_np);
++
++	return ret;
++}
++
++static int adtran_probe(struct nvmem_layout *layout)
++{
++	layout->add_cells = adtran_add_cells;
++
++	return nvmem_layout_register(layout);
++}
++
++static void adtran_remove(struct nvmem_layout *layout)
++{
++	nvmem_layout_unregister(layout);
++}
++
++static const struct of_device_id adtran_of_match_table[] = {
++	{ .compatible = "adtran,mfginfo" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, adtran_of_match_table);
++
++static struct nvmem_layout_driver adtran_layout = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "adtran-layout",
++		.of_match_table = adtran_of_match_table,
++	},
++	.probe = adtran_probe,
++	.remove = adtran_remove,
++};
++module_nvmem_layout_driver(adtran_layout);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("NVMEM layout driver for Adtran mfginfo");

target/linux/mediatek/patches-6.6/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch

@@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/mxl-gpy.c
 +++ b/drivers/net/phy/mxl-gpy.c
-@@ -385,8 +385,11 @@ static bool gpy_2500basex_chk(struct phy
+@@ -402,8 +402,11 @@ static bool gpy_2500basex_chk(struct phy
  
  	phydev->speed = SPEED_2500;
  	phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
@@ -28,7 +28,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	return true;
  }
  
-@@ -437,6 +440,14 @@ static int gpy_config_aneg(struct phy_de
+@@ -454,6 +457,14 @@ static int gpy_config_aneg(struct phy_de
  	u32 adv;
  	int ret;
  
@@ -43,7 +43,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	if (phydev->autoneg == AUTONEG_DISABLE) {
  		/* Configure half duplex with genphy_setup_forced,
  		 * because genphy_c45_pma_setup_forced does not support.
-@@ -559,6 +570,8 @@ static int gpy_update_interface(struct p
+@@ -576,6 +587,8 @@ static int gpy_update_interface(struct p
  	switch (phydev->speed) {
  	case SPEED_2500:
  		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
@@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
  				     VSPEC1_SGMII_CTRL_ANEN, 0);
  		if (ret < 0) {
-@@ -572,7 +585,7 @@ static int gpy_update_interface(struct p
+@@ -589,7 +602,7 @@ static int gpy_update_interface(struct p
  	case SPEED_100:
  	case SPEED_10:
  		phydev->interface = PHY_INTERFACE_MODE_SGMII;

target/linux/ramips/mt7620/config-6.6

@@ -102,6 +102,7 @@ CONFIG_IRQ_INTC=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
 CONFIG_LIBFDT=y
+# CONFIG_LIST_HARDENED is not set
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_MARVELL_PHY=y
 CONFIG_MDIO_BUS=y