mediatek: add support for TP-Link TL-XDR3230 v1
Specifications: - SoC: Mediatek MT7622B - RAM: 256M - Flash: EN25QH128 16M - Ethernet: RTL8367S 4xGE - WiFi: MT7622 2.4G 4x4 + MT7905 5G 4x4 - UART: 3.3v, 115200n8 -------------------------- | Layout | | ∇ | | ----------------- | | | VCC GND RX TX | JP1 | | ----------------- | -------------------------- Flash instruction: TP-Link locks down their firmware and serial console, so the firmware must be flashed with mtk_uartboot. 1. Download mtk_uartboot: https://github.com/981213/mtk_uartboot/releases 2. Download bootloaders: RAM loader for mtk_uartboot: https://drive.wrt.moe/uboot/mediatek/mt7622-bl2-ram-1ddr3.bin BL2: https://drive.wrt.moe/uboot/mediatek/mt7622-tplink_tl-xdr3230-v1-bl2.bin FIP: https://drive.wrt.moe/uboot/mediatek/mt7622-tplink_tl-xdr3230-v1-fip.bin 3. Open the case, and attach to the UART. 4. Start mtk_uartboot: ./mtk_uartboot -a -s /dev/ttyUSB0 -p mt7622-bl2-ram-1ddr3.bin -f \ mt7622-tplink_tl-xdr3230-v1-fip.bin --brom-load-baudrate 115200 \ --bl2-load-baudrate 115200 5. Cut off the power and re-engage, wait for UART download to complete. 6. Connect to the UART, write new BL2/FIP/Firmware with TFTP. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> [fixup wifi eeprom and macs, add network configuration, minor fixes] Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Chuanhong Guo
Tianling Shen
parent
1d978085ee
commit
9f73519e62
291
target/linux/mediatek/dts/mt7622-tplink_tl-xdr3230-v1.dts
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291
target/linux/mediatek/dts/mt7622-tplink_tl-xdr3230-v1.dts
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@ -0,0 +1,291 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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/ {
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model = "TP-Link TL-XDR3230 v1";
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compatible = "tplink,tl-xdr3230-v1", "mediatek,mt7622";
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aliases {
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led-boot = &red_status_led;
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led-failsafe = &red_status_led;
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led-running = &green_status_led;
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led-upgrade = &green_status_led;
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label-mac-device = &gmac0;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 root=/dev/fit0 rootwait";
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rootdisk = <&nor_rootdisk>;
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};
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memory@40000000 {
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reg = <0 0x40000000 0 0x10000000>;
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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cpu@1 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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/* It seems that reset isn't connected to any MT7622 GPIO. Here's the WPS button. */
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button-reset {
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label = "reset";
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gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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green_status_led: led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
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};
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red_status_led: led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&pio 90 GPIO_ACTIVE_HIGH>;
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};
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};
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rtkgsw: rtkgsw@0 {
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compatible = "mediatek,rtk-gsw";
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mediatek,ethsys = <ðsys>;
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mediatek,mdio = <&mdio>;
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mediatek,reset-pin = <&pio 54 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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};
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ð {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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nvmem-cells = <&macaddr_factory_d81c 0>;
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nvmem-cell-names = "mac-address";
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phy-connection-type = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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nvmem-cells = <&macaddr_factory_d81c 1>;
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nvmem-cell-names = "mac-address";
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&nor_flash {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_nor_pins>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@20000 {
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label = "fip";
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reg = <0x20000 0x40000>;
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read-only;
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};
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partition@60000 {
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label = "factory";
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reg = <0x60000 0x20000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_e000: eeprom@e000 {
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/* actual length 0x400 */
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reg = <0xe000 0x4da8>;
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};
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eeprom_factory_f000: eeprom@f000 {
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reg = <0xf000 0xe00>;
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};
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macaddr_factory_d81c: macaddr@d81c {
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compatible = "mac-base";
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reg = <0xd81c 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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nor_rootdisk: partition@80000 {
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compatible = "denx,fit";
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label = "firmware";
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reg = <0x80000 0xf80000>;
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};
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};
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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&pio {
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epa_elna_pins: epa-elna-pins {
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mux {
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function = "antsel";
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groups = "antsel0", "antsel1", "antsel2", "antsel3",
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"antsel4", "antsel5", "antsel6", "antsel7",
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"antsel8", "antsel9", "antsel12", "antsel13",
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"antsel14", "antsel15", "antsel16", "antsel17";
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};
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};
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio", "rgmii_via_gmac2";
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};
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};
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_0_waken",
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"pcie0_0_clkreq";
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};
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};
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pmic_bus_pins: pmic-bus-pins {
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mux {
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function = "pmic";
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groups = "pmic_bus";
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};
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};
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spi_nor_pins: spi-nor-pins {
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mux {
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function = "flash";
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groups = "spi_nor";
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0_0_tx_rx";
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};
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};
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watchdog_pins: watchdog-pins {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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};
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&pwrap {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_bus_pins>;
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status = "okay";
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};
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&rtc {
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status = "disabled";
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};
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&slot0 {
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mt7915@0,0 {
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reg = <0x0000 0 0 0 0>;
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ieee80211-freq-limit = <5000000 6000000>;
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nvmem-cells = <&eeprom_factory_f000>, <&macaddr_factory_d81c 2>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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&wmac {
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nvmem-cells = <&eeprom_factory_e000>, <&macaddr_factory_d81c 0>;
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nvmem-cell-names = "eeprom", "mac-address";
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pinctrl-names = "default";
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pinctrl-0 = <&epa_elna_pins>;
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status = "okay";
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};
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@ -326,6 +326,23 @@ define Device/totolink_a8000ru
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endef
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TARGET_DEVICES += totolink_a8000ru
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define Device/tplink_tl-xdr3230-v1
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DEVICE_VENDOR := TP-Link
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DEVICE_MODEL := TL-XDR3230
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DEVICE_VARIANT := v1
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DEVICE_DTS := mt7622-tplink_tl-xdr3230-v1
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DEVICE_DTS_DIR := ../dts
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DEVICE_PACKAGES := kmod-mt7915-firmware swconfig
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KERNEL := kernel-bin | lzma
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KERNEL_INITRAMFS_SUFFIX := -recovery.itb
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KERNEL_INITRAMFS := kernel-bin | lzma | \
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fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
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IMAGES := sysupgrade.itb
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IMAGE/sysupgrade.itb := append-kernel | \
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fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata
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endef
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TARGET_DEVICES += tplink_tl-xdr3230-v1
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define Device/ubnt_unifi-6-lr-v1
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DEVICE_VENDOR := Ubiquiti
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DEVICE_MODEL := UniFi U6 Long-Range
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@ -20,6 +20,10 @@ mediatek_setup_interfaces()
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ucidef_add_switch "switch0" \
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"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"
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;;
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tplink,tl-xdr3230-v1)
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ucidef_add_switch "switch0" \
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"1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"
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;;
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ubnt,unifi-6-lr*)
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ucidef_set_interface_lan "eth0"
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;;
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@ -8,6 +8,7 @@ platform_do_upgrade() {
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case "$board" in
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bananapi,bpi-r64|\
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linksys,e8450-ubi|\
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tplink,tl-xdr3230-v1|\
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ubnt,unifi-6-lr-v1-ubootmod|\
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ubnt,unifi-6-lr-v2-ubootmod|\
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ubnt,unifi-6-lr-v3-ubootmod|\
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