c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
50 lines
1.7 KiB
Diff
50 lines
1.7 KiB
Diff
From: Frank Sae <Frank.Sae@motor-comm.com>
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Date: Sun, 1 Sep 2024 01:35:25 -0700
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Subject: [PATCH 02/20] net: phy: Optimize phy speed mask to be compatible to
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yt8821
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yt8521 and yt8531s as Gigabit transceiver use bit15:14(bit9 reserved
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default 0) as phy speed mask, yt8821 as 2.5G transceiver uses bit9 bit15:14
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as phy speed mask.
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Be compatible to yt8821, reform phy speed mask and phy speed macro.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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(cherry picked from commit 8d878c87b5c45ae64b0aecd4aac71e210d19173f)
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---
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drivers/net/phy/motorcomm.c | 13 +++++--------
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1 file changed, 5 insertions(+), 8 deletions(-)
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -47,12 +47,10 @@
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/* Specific Status Register */
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#define YTPHY_SPECIFIC_STATUS_REG 0x11
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-#define YTPHY_SSR_SPEED_MODE_OFFSET 14
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-
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-#define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14))
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-#define YTPHY_SSR_SPEED_10M 0x0
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-#define YTPHY_SSR_SPEED_100M 0x1
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-#define YTPHY_SSR_SPEED_1000M 0x2
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+#define YTPHY_SSR_SPEED_MASK ((0x3 << 14) | BIT(9))
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+#define YTPHY_SSR_SPEED_10M ((0x0 << 14))
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+#define YTPHY_SSR_SPEED_100M ((0x1 << 14))
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+#define YTPHY_SSR_SPEED_1000M ((0x2 << 14))
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#define YTPHY_SSR_DUPLEX_OFFSET 13
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#define YTPHY_SSR_DUPLEX BIT(13)
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#define YTPHY_SSR_PAGE_RECEIVED BIT(12)
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@@ -1188,8 +1186,7 @@ static int yt8521_adjust_status(struct p
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else
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duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */
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- speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >>
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- YTPHY_SSR_SPEED_MODE_OFFSET;
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+ speed_mode = status & YTPHY_SSR_SPEED_MASK;
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switch (speed_mode) {
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case YTPHY_SSR_SPEED_10M:
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