c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
From: Chuanhong Guo <gch981213@gmail.com>
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Date: Tue, 20 Aug 2024 08:33:43 +0800
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Subject: [PATCH 06/20] reset: add support for sf19a2890
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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---
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drivers/reset/Kconfig | 8 ++++++++
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drivers/reset/Makefile | 1 +
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2 files changed, 9 insertions(+)
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--- a/drivers/reset/Kconfig
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+++ b/drivers/reset/Kconfig
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@@ -211,6 +211,14 @@ config RESET_SCMI
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This driver uses SCMI Message Protocol to interact with the
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firmware controlling all the reset signals.
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+config RESET_SF19A2890_PERIPH
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+ bool "Siflower SF19A2890 Peripheral Reset Controller Driver"
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+ default MACH_SIFLOWER_MIPS
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+ depends on HAS_IOMEM
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+ help
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+ This enables reset controller driver for peripheral reset blocks
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+ found on Siflower SF19A2890 SoC.
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+
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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
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default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
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--- a/drivers/reset/Makefile
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+++ b/drivers/reset/Makefile
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@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qc
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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+obj-$(CONFIG_RESET_SF19A2890_PERIPH) += reset-sf19a2890-periph.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
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