c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
From: Chuanhong Guo <gch981213@gmail.com>
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Date: Mon, 9 Sep 2024 16:46:53 +0800
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Subject: [PATCH 11/20] usb: dwc2: add support for Siflower SF19A2890
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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---
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drivers/usb/dwc2/params.c | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/drivers/usb/dwc2/params.c
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+++ b/drivers/usb/dwc2/params.c
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@@ -200,6 +200,14 @@ static void dwc2_set_amcc_params(struct
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
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}
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+static void dwc2_set_sf19a2890_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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+
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+ p->max_transfer_size = 65535;
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+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT;
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+}
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+
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static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_core_params *p = &hsotg->params;
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@@ -294,6 +302,8 @@ const struct of_device_id dwc2_of_match_
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.data = dwc2_set_amlogic_a1_params },
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{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
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{ .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
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+ { .compatible = "siflower,sf19a2890-usb",
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+ .data = dwc2_set_sf19a2890_params },
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{ .compatible = "st,stm32f4x9-fsotg",
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.data = dwc2_set_stm32f4x9_fsotg_params },
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{ .compatible = "st,stm32f4x9-hsotg" },
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