cc67e3798d
Removed upstream patches: * 100-clk-rockchip-rk3568-fix-reset-handler.patch * 103-rockchip-rk3568-add-boot-device-detection.patch * 104-rockchip-rk3568-enable-automatic-clock-gating.patch * 108-rockchip-sdram-add-basic-support-for-sdram-reg-info-versi.patch * 109-rockchip-Align-FIT-image-data-to-SD-MMC-block-length.patch * 110-hack-fix-build-rk356x-idbloader.patch Refreshed all patches, dts and defconfigs. === NOTE === To compile with uboot-rockchip v2023.04 and higher, you must install pyelftools on your build host. e.g. `apt install python3-pyelftools` or `pip3 install pyelftools` Tested-by: ZiMing Mo <msylgj@immortalwrt.org> [NanoPi R4S] Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
96 lines
2.8 KiB
Diff
96 lines
2.8 KiB
Diff
From: Peter Geis <pgwipeout@gmail.com>
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To: Simon Glass <sjg@chromium.org>,
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Philipp Tomsich <philipp.tomsich@vrull.eu>,
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Kever Yang <kever.yang@rock-chips.com>
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Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
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Subject: [PATCH v1 06/11] rockchip: handle bootrom recovery mode in spl
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Date: Mon, 21 Feb 2022 20:31:25 -0500 [thread overview]
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Message-ID: <20220222013131.3114990-7-pgwipeout@gmail.com> (raw)
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In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
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Fixup the bootrom recovery mode code to function in spl, so we can
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handle recovery mode in case u-boot loading is broken.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/mach-rockchip/Makefile | 6 +++---
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arch/arm/mach-rockchip/boot_mode.c | 4 +++-
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arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
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3 files changed, 29 insertions(+), 4 deletions(-)
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--- a/arch/arm/mach-rockchip/Makefile
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+++ b/arch/arm/mach-rockchip/Makefile
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@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-
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obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
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-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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-
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# Always include boot_mode.o, as we bypass it (i.e. turn it off)
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# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
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# we can have the preprocessor correctly recognise both 0x0 and 0
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# meaning "turn it off".
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-obj-y += boot_mode.o
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+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
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+
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+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
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obj-$(CONFIG_MISC_INIT_R) += misc.o
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endif
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--- a/arch/arm/mach-rockchip/boot_mode.c
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+++ b/arch/arm/mach-rockchip/boot_mode.c
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@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void
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ret = -ENODEV;
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uclass_foreach_dev(dev, uc) {
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if (!strncmp(dev->name, "saradc", 6)) {
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- ret = adc_channel_single_shot(dev->name, 1, &val);
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+ ret = adc_channel_single_shot(dev->name, 0, &val);
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break;
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}
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}
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@@ -89,6 +89,7 @@ int setup_boot_mode(void)
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boot_mode = readl(reg);
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debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
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+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
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/* Clear boot mode */
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writel(BOOT_NORMAL, reg);
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@@ -102,6 +103,7 @@ int setup_boot_mode(void)
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env_set("preboot", "setenv preboot; ums mmc 0");
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break;
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}
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+#endif
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return 0;
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}
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--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
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+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
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@@ -135,3 +135,26 @@ int arch_cpu_init(void)
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#endif
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return 0;
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}
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+
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+#ifdef CONFIG_SPL_BUILD
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+
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+void __weak led_setup(void)
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+{
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+}
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+
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+void spl_board_init(void)
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+{
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+ led_setup();
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+
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+#if (CONFIG_IS_ENABLED(DM_REGULATOR))
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+ /*
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+ * Turning the eMMC and SPI back on (if disabled via the Qseven
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+ * BIOS_ENABLE) signal is done through a always-on regulator).
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+ */
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+ if (regulators_enable_boot_on(false))
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+ debug("%s: Cannot enable boot on regulator\n", __func__);
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+#endif
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+
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+ setup_boot_mode();
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+}
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+#endif
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