5663f8e166
b48688ea3c9ac r8169: disable RTL8126 ZRX-DC timeout 3d9b8ac534126 r8169: enable RTL8168H/RTL8168EP/RTL8168FP ASPM support 473367a5ffe16 r8169: increase max jumbo packet size on RTL8125/RTL8126 853e80369cfce r8169: add PHY c45 ops for MDIO_MMD_VENDOR2 registers d30460f42675f r8169: add support for Intel Killer E5000 faac69a4ae5ab r8169: don't scan PHY addresses > 0 135c3c86a7cef r8169: make Kconfig option for LED support user-visible Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> (cherry picked from commit 36623119b3e6532a3d051a37e93b2fbaa3dd1f6d)
61 lines
2.0 KiB
Diff
61 lines
2.0 KiB
Diff
From b48688ea3c9ac8d5d910c6e91fb7f80d846581f0 Mon Sep 17 00:00:00 2001
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From: ChunHao Lin <hau@realtek.com>
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Date: Tue, 18 Mar 2025 16:37:21 +0800
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Subject: [PATCH] r8169: disable RTL8126 ZRX-DC timeout
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Disable it due to it dose not meet ZRX-DC specification. If it is enabled,
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device will exit L1 substate every 100ms. Disable it for saving more power
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in L1 substate.
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Signed-off-by: ChunHao Lin <hau@realtek.com>
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Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
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Link: https://patch.msgid.link/20250318083721.4127-3-hau@realtek.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/realtek/r8169_main.c | 27 +++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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--- a/drivers/net/ethernet/realtek/r8169_main.c
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+++ b/drivers/net/ethernet/realtek/r8169_main.c
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@@ -2856,6 +2856,32 @@ static u32 rtl_csi_read(struct rtl8169_p
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RTL_R32(tp, CSIDR) : ~0;
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}
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+static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
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+{
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+ struct pci_dev *pdev = tp->pci_dev;
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+ u32 csi;
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+ int rc;
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+ u8 val;
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+
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+#define RTL_GEN3_RELATED_OFF 0x0890
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+#define RTL_GEN3_ZRXDC_NONCOMPL 0x1
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+ if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) {
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+ rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val);
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+ if (rc == PCIBIOS_SUCCESSFUL) {
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+ val &= ~RTL_GEN3_ZRXDC_NONCOMPL;
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+ rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF,
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+ val);
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+ if (rc == PCIBIOS_SUCCESSFUL)
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+ return;
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+ }
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+ }
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+
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+ netdev_notice_once(tp->dev,
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+ "No native access to PCI extended config space, falling back to CSI\n");
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+ csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF);
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+ rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL);
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+}
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+
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static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
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{
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struct pci_dev *pdev = tp->pci_dev;
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@@ -3828,6 +3854,7 @@ static void rtl_hw_start_8125d(struct rt
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static void rtl_hw_start_8126a(struct rtl8169_private *tp)
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{
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+ rtl_disable_zrxdc_timeout(tp);
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rtl_set_def_aspm_entry_latency(tp);
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rtl_hw_start_8125_common(tp);
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}
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