8e539afa95
In order to be able to define the external GPIO controller on an emulated MDIO bus, move the controller definition outside of the main GS1900 include for RTL838x-based devices. Additionally, a new DTSI is provided defining the RTL8231 on the emulated MDIO bus. Signed-off-by: Sander Vanheule <sander@svanheule.net> (cherry picked from commit a6a77896f4cddd6e69bcf86d5a6dc190fa82d53d)
134 lines
2.3 KiB
Plaintext
134 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl838x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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debounce-interval = <100>;
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};
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};
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leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-leds";
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led_sys: sys {
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label = "green:sys";
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "u-boot-env2";
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reg = <0x50000 0x10000>;
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};
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partition@60000 {
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label = "jffs";
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reg = <0x60000 0x100000>;
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};
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partition@160000 {
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label = "jffs2";
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reg = <0x160000 0x100000>;
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};
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partition@b260000 {
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label = "firmware";
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reg = <0x260000 0xda0000>;
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <0x83800000>;
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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