54 lines
1.5 KiB
Diff
54 lines
1.5 KiB
Diff
From: Peter Geis <pgwipeout@gmail.com>
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To: Simon Glass <sjg@chromium.org>,
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Philipp Tomsich <philipp.tomsich@vrull.eu>,
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Kever Yang <kever.yang@rock-chips.com>
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Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
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Subject: [PATCH v1 10/11] rockchip: rk3568: add dwc3 otg support
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Date: Mon, 21 Feb 2022 20:31:29 -0500 [thread overview]
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Message-ID: <20220222013131.3114990-11-pgwipeout@gmail.com> (raw)
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In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
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Add the required platform data to the rk3568 chip config, in order to
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support dwc3 otg on this chip.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
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+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
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@@ -158,3 +158,32 @@ void spl_board_init(void)
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setup_boot_mode();
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}
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#endif
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+
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+#if defined(CONFIG_USB_GADGET)
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+#include <usb.h>
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+
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+#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
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+#include <dwc3-uboot.h>
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+
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+static struct dwc3_device dwc3_device_data = {
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+ .maximum_speed = USB_SPEED_HIGH,
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+ .base = 0xfcc00000,
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+ .dr_mode = USB_DR_MODE_PERIPHERAL,
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+ .index = 0,
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+ .dis_u2_susphy_quirk = 1,
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+ .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
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+};
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+
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+int usb_gadget_handle_interrupts(int index)
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+{
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+ dwc3_uboot_handle_interrupt(0);
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+ return 0;
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+}
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+
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+int board_usb_init(int index, enum usb_init_type init)
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+{
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+ return dwc3_uboot_init(&dwc3_device_data);
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+}
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+#endif /* CONFIG_USB_DWC3_GADGET */
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+
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+#endif /* CONFIG_USB_GADGET */
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