110 lines
3.1 KiB
Diff
110 lines
3.1 KiB
Diff
From 2d2a4b860ef60b4d10754d2e690d6fc170571a83 Mon Sep 17 00:00:00 2001
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From: Hecanyang <hcy@rock-chips.com>
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Date: Sat, 23 Dec 2017 15:40:21 +0800
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Subject: [PATCH] arm64: dts: rockchip: add rk3328 ddr relate node
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except add note to existing dts file, also add ddr timing and de-skew's
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dts file.
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Change-Id: I92b7e9c2c6572babd4be00beadbbb75aae431707
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Signed-off-by: CanYang He <hcy@rock-chips.com>
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Signed-off-by: hmz007 <hmz007@gmail.com>
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---
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.../rockchip/rk3328-dram-2layer-timing.dtsi | 257 +++++++++++++++
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.../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++
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.../boot/dts/rockchip/rk3328-evb-android.dts | 9 +
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 67 ++++
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4 files changed, 644 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-2layer-timing.dtsi
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -11,6 +11,7 @@
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#include <dt-bindings/power/rk3328-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/thermal/thermal.h>
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+#include "rk3328-dram-default-timing.dtsi"
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/ {
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compatible = "rockchip,rk3328";
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@@ -1039,6 +1040,78 @@
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status = "disabled";
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};
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+ dfi: dfi@ff790000 {
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+ reg = <0x00 0xff790000 0x00 0x400>;
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+ compatible = "rockchip,rk3328-dfi";
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+ rockchip,grf = <&grf>;
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+ status = "okay";
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+ };
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+
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+ dmc: dmc {
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+ compatible = "rockchip,rk3328-dmc";
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+ devfreq-events = <&dfi>;
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+ clocks = <&cru SCLK_DDRCLK>;
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+ clock-names = "dmc_clk";
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+ operating-points-v2 = <&dmc_opp_table>;
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+ ddr_timing = <&ddr_timing>;
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+ upthreshold = <40>;
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+ downdifferential = <20>;
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+ auto-min-freq = <786000>;
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+ auto-freq-en = <0>;
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+ #cooling-cells = <2>;
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+ status = "disabled";
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+
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+ ddr_power_model: ddr_power_model {
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+ compatible = "ddr_power_model";
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+ dynamic-power-coefficient = <120>;
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+ static-power-coefficient = <200>;
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+ ts = <32000 4700 (-80) 2>;
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+ thermal-zone = "soc-thermal";
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+ };
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+ };
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+
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+ dmc_opp_table: dmc-opp-table {
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+ compatible = "operating-points-v2";
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+
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+ rockchip,leakage-voltage-sel = <
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+ 1 10 0
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+ 11 254 1
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+ >;
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+ nvmem-cells = <&logic_leakage>;
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+ nvmem-cell-names = "ddr_leakage";
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+
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+ opp-786000000 {
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+ opp-hz = /bits/ 64 <786000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-798000000 {
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+ opp-hz = /bits/ 64 <798000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-840000000 {
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+ opp-hz = /bits/ 64 <840000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-924000000 {
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+ opp-hz = /bits/ 64 <924000000>;
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+ opp-microvolt = <1100000>;
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+ opp-microvolt-L0 = <1100000>;
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+ opp-microvolt-L1 = <1075000>;
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+ };
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+ opp-1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1175000>;
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+ opp-microvolt-L0 = <1175000>;
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+ opp-microvolt-L1 = <1150000>;
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+ };
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+ };
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+
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gic: interrupt-controller@ff811000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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