f22febae1a
Add pending PCI patch that should correctly fix mediatek driver with Airoha SoC. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
82 lines
2.6 KiB
Diff
82 lines
2.6 KiB
Diff
From ca4217f3117dceb2d01e179d02031a8758404624 Mon Sep 17 00:00:00 2001
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Message-ID: <ca4217f3117dceb2d01e179d02031a8758404624.1736961235.git.lorenzo@kernel.org>
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Tue, 3 Sep 2024 23:14:02 +0200
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Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
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SoC
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Configure PBus base address and address mask in order to allow the hw
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detecting if a given address is on PCIE0, PCIE1 or PCIE2.
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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---
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drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++++++++-
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1 file changed, 28 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -15,6 +15,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_device.h>
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@@ -24,6 +25,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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+#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "../pci.h"
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@@ -122,6 +124,13 @@
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#define PCIE_MTK_RESET_TIME_US 10
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+#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3))
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+#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3))
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+#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \
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+ ((_n) == 2 ? 0x28000000 : \
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+ (_n) == 1 ? 0x24000000 : 0x20000000)
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+#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26)
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+
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/* Time in ms needed to complete PCIe reset on EN7581 SoC */
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#define PCIE_EN7581_RESET_TIME_MS 100
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@@ -893,7 +902,8 @@ static int mtk_pcie_parse_port(struct mt
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static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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- int err;
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+ struct regmap *map;
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+ int err, slot;
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u32 val;
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/*
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@@ -907,6 +917,23 @@ static int mtk_pcie_en7581_power_up(stru
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/* Wait for the time needed to complete the reset lines assert. */
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msleep(PCIE_EN7581_RESET_TIME_MS);
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+ map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
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+ if (IS_ERR(map))
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+ return PTR_ERR(map);
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+
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+ /*
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+ * Configure PBus base address and address mask in order to allow the
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+ * hw detecting if a given address is on PCIE0, PCIE1 or PCIE2.
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+ */
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+ slot = of_get_pci_domain_nr(dev->of_node);
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+ if (slot < 0)
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+ return slot;
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+
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+ regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot),
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+ PCIE_EN7581_PBUS_BASE_ADDR(slot));
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+ regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot),
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+ PCIE_EN7581_PBUS_BASE_ADDR_MASK);
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+
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/*
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* Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
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* requires PHY initialization and power-on before PHY reset deassert.
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