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realtek: fix PLL register inconsistencies

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Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Markus Stockhausen 2022-08-30 16:44:02 +02:00 committed by Hauke Mehrtens
parent e0753c5d5c
commit 6ff21c436d
1 changed files with 3 additions and 0 deletions
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3
target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
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@ -366,6 +366,9 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra
switch (rtcl_ccu->soc) { switch (rtcl_ccu->soc) {
case SOC_RTL838X: case SOC_RTL838X:
if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB))
return 200000000;
cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1); cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1);
cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)]; cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)];
break; break;