1ce87cf25c
Add several dt backports for the Gateworks Venice product family. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Link: https://github.com/openwrt/openwrt/pull/17717 Signed-off-by: Robert Marko <robimarko@gmail.com>
37 lines
1.5 KiB
Diff
37 lines
1.5 KiB
Diff
From e6d8fd29bd3d796a00ff9b69f9fae011aec3cb40 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 5 Sep 2024 11:32:28 -0700
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Subject: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio
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configuration
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The GW74xx D revision has added a M2SKT_GPIO10 GPIO which routes to the
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GPIO10 pin of the M.2 socket for compatibility with certain devices.
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Add the iomux and a line name for this.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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---
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arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
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+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
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@@ -264,7 +264,7 @@
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&gpio3 {
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gpio-line-names =
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"", "", "", "", "", "", "m2_rst", "",
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- "", "", "", "", "", "", "", "",
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+ "", "", "", "", "", "", "m2_gpio10", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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@@ -786,6 +786,7 @@
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MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
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MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
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MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
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+ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */
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MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
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MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
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MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
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