34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
99 lines
2.7 KiB
Diff
99 lines
2.7 KiB
Diff
From 3e4b53e04281ed3d9c7a4329c027097265c04d54 Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
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Date: Mon, 25 Sep 2023 15:58:26 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the CPUFreq support
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Add the APCS, A53 PLL, cpu-opp-table nodes to set
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the CPU frequency at 800MHz (idle) or 1.008GHz.
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Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
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1 file changed, 40 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -5,6 +5,7 @@
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* Copyright (c) 2023 The Linux Foundation. All rights reserved.
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*/
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+#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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@@ -36,6 +37,8 @@
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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CPU1: cpu@1 {
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@@ -44,6 +47,8 @@
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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L2_0: l2-cache {
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@@ -54,6 +59,25 @@
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};
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};
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+ cpu_opp_table: opp-table-cpu {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ /*
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <200000>;
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+ };
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+ */
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <200000>;
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+ };
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+ };
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+
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firmware {
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scm {
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compatible = "qcom,scm-ipq5018", "qcom,scm";
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@@ -267,6 +291,24 @@
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clocks = <&sleep_clk>;
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};
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+ apcs_glb: mailbox@b111000 {
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+ compatible = "qcom,ipq5018-apcs-apps-global",
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+ "qcom,ipq6018-apcs-apps-global";
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+ reg = <0x0b111000 0x1000>;
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+ #clock-cells = <1>;
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+ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
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+ clock-names = "pll", "xo", "gpll0";
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+ #mbox-cells = <1>;
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+ };
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+
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+ a53pll: clock@b116000 {
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+ compatible = "qcom,ipq5018-a53pll";
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+ reg = <0x0b116000 0x40>;
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+ #clock-cells = <0>;
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+ clocks = <&xo_board_clk>;
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+ clock-names = "xo";
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+ };
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+
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timer@b120000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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