34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
33 lines
1.1 KiB
Diff
33 lines
1.1 KiB
Diff
From: Gabor Juhos <j4g8y7@gmail.com>
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Subject: [PATCH] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
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Date: Tue, 26 Mar 2024 14:34:11 +0100
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According to ipq5018.dtsi, the maximum supported rate by the
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CPU is 1.008 GHz on the IPQ5018 platform, however the current
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configuration of the PLL results in 1.2 GHz rate.
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Change the 'L' value in the PLL configuration to limit the
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rate to 1.008 GHz. The downstream kernel also uses the same
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value [1]. Also add a comment to indicate the desired
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frequency.
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[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151
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Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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---
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drivers/clk/qcom/apss-ipq-pll.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/apss-ipq-pll.c
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+++ b/drivers/clk/qcom/apss-ipq-pll.c
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@@ -97,7 +97,7 @@ static struct clk_alpha_pll ipq_pll_stro
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};
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static const struct alpha_pll_config ipq5018_pll_config = {
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- .l = 0x32,
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+ .l = 0x2a,
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.config_ctl_val = 0x4001075b,
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.config_ctl_hi_val = 0x304,
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.main_output_mask = BIT(0),
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