34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
78 lines
2.7 KiB
Diff
78 lines
2.7 KiB
Diff
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Subject: [PATCH] PCI: qcom: Add support for IPQ5018
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Date: Tue, 3 Oct 2023 17:38:44 +0530
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Added a new compatible 'qcom,pcie-ipq5018' and modified
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get_resources of 'ops 2_9_0' to get the clocks from the
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device-tree.
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Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
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Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
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Co-developed-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++--------------
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1 file changed, 8 insertions(+), 14 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -202,8 +202,9 @@ struct qcom_pcie_resources_2_7_0 {
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#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5
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struct qcom_pcie_resources_2_9_0 {
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- struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS];
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+ struct clk_bulk_data *clks;
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struct reset_control *rst;
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+ int num_clks;
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};
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union qcom_pcie_resources {
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@@ -1073,17 +1074,10 @@ static int qcom_pcie_get_resources_2_9_0
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struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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- int ret;
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-
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- res->clks[0].id = "iface";
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- res->clks[1].id = "axi_m";
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- res->clks[2].id = "axi_s";
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- res->clks[3].id = "axi_bridge";
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- res->clks[4].id = "rchng";
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- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
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- if (ret < 0)
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- return ret;
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+ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
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+ if (res->num_clks < 0)
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+ return res->num_clks;
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res->rst = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(res->rst))
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@@ -1096,7 +1090,7 @@ static void qcom_pcie_deinit_2_9_0(struc
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{
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struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
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- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
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+ clk_bulk_disable_unprepare(res->num_clks, res->clks);
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}
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static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
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@@ -1125,7 +1119,7 @@ static int qcom_pcie_init_2_9_0(struct q
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usleep_range(2000, 2500);
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- return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
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+ return clk_bulk_prepare_enable(res->num_clks, res->clks);
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}
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static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
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@@ -1641,6 +1635,7 @@ static const struct of_device_id qcom_pc
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{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
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{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
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{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
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+ { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
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{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
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{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
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{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
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