34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
217 lines
5.6 KiB
Diff
217 lines
5.6 KiB
Diff
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes
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Date: Tue, 3 Oct 2023 17:38:45 +0530
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Add phy and controller nodes for PCIe0 and PCIe1.
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PCIe0 is 2-lane Gen2 and PCIe1 is 1-lane Gen2.
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 186 +++++++++++++++++++++++++-
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1 file changed, 184 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -149,6 +149,42 @@
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status = "disabled";
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};
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+ pcie1_phy: phy@7e000{
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+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
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+ reg = <0x0007e000 0x800>;
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+
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+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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+
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+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
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+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
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+
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+ #clock-cells = <0>;
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+
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+ #phy-cells = <0>;
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+
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+ num-lanes = <1>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie0_phy: phy@86000{
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+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
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+ reg = <0x00086000 0x800>;
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+
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+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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+
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+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
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+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
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+
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+ #clock-cells = <0>;
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+
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+ #phy-cells = <0>;
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+
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+ num-lanes = <2>;
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+
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+ status = "disabled";
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+ };
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+
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qfprom: qfprom@a0000 {
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compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
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reg = <0xa0000 0x1000>;
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@@ -283,8 +319,8 @@
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reg = <0x01800000 0x80000>;
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clocks = <&xo_board_clk>,
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<&sleep_clk>,
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- <0>,
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- <0>,
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+ <&pcie0_phy>,
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+ <&pcie1_phy>,
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<0>,
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<0>,
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<0>,
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@@ -501,6 +537,146 @@
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status = "disabled";
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};
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};
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+
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+ pcie1: pcie@80000000 {
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+ compatible = "qcom,pcie-ipq5018";
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+ reg = <0x80000000 0xf1d>,
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+ <0x80000f20 0xa8>,
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+ <0x80001000 0x1000>,
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+ <0x00078000 0x3000>,
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+ <0x80100000 0x1000>;
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+ reg-names = "dbi",
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+ "elbi",
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+ "atu",
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+ "parf",
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+ "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ max-link-speed = <2>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ phys = <&pcie1_phy>;
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+ phy-names ="pciephy";
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+
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+ ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */
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+ <0x82000000 0 0x80300000 0x80300000 0 0x10000000>; /* MEM */
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+
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+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "global_irq";
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+
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+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
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+ <&gcc GCC_PCIE1_AXI_M_CLK>,
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+ <&gcc GCC_PCIE1_AXI_S_CLK>,
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+ <&gcc GCC_PCIE1_AHB_CLK>,
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+ <&gcc GCC_PCIE1_AUX_CLK>,
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+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
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+ clock-names = "iface",
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+ "axi_m",
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+ "axi_s",
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+ "ahb",
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+ "aux",
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+ "axi_bridge";
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+
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+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
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+ <&gcc GCC_PCIE1_SLEEP_ARES>,
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+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
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+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
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+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
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+ <&gcc GCC_PCIE1_AHB_ARES>,
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+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
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+ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
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+ reset-names = "pipe",
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+ "sleep",
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+ "sticky",
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+ "axi_m",
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+ "axi_s",
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+ "ahb",
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+ "axi_m_sticky",
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+ "axi_s_sticky";
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+
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+ msi-map = <0x0 &v2m0 0x0 0xff8>;
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+ status = "disabled";
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+ };
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+
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+ pcie0: pcie@a0000000 {
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+ compatible = "qcom,pcie-ipq5018";
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+ reg = <0xa0000000 0xf1d>,
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+ <0xa0000f20 0xa8>,
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+ <0xa0001000 0x1000>,
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+ <0x00080000 0x3000>,
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+ <0xa0100000 0x1000>;
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+ reg-names = "dbi",
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+ "elbi",
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+ "atu",
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+ "parf",
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+ "config";
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+ device_type = "pci";
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+ linux,pci-domain = <1>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <2>;
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+ max-link-speed = <2>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ phys = <&pcie0_phy>;
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+ phy-names ="pciephy";
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+
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+ ranges = <0x81000000 0 0xa0200000 0xa0200000 0 0x00100000>, /* I/O */
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+ <0x82000000 0 0xa0300000 0xa0300000 0 0x10000000>; /* MEM */
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+
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+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "global_irq";
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+
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+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
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+ <&gcc GCC_PCIE0_AXI_M_CLK>,
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+ <&gcc GCC_PCIE0_AXI_S_CLK>,
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+ <&gcc GCC_PCIE0_AHB_CLK>,
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+ <&gcc GCC_PCIE0_AUX_CLK>,
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+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
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+ clock-names = "iface",
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+ "axi_m",
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+ "axi_s",
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+ "ahb",
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+ "aux",
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+ "axi_bridge";
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+
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+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
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+ <&gcc GCC_PCIE0_SLEEP_ARES>,
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+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
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+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
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+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
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+ <&gcc GCC_PCIE0_AHB_ARES>,
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+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
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+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
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+ reset-names = "pipe",
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+ "sleep",
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+ "sticky",
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+ "axi_m",
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+ "axi_s",
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+ "ahb",
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+ "axi_m_sticky",
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+ "axi_s_sticky";
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+
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+ msi-map = <0x0 &v2m0 0x0 0xff8>;
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+ status = "disabled";
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+ };
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};
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thermal-zones {
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