34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
From 50799703c6c8ec0860e19b102dd7cca3d29028e1 Mon Sep 17 00:00:00 2001
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From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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Date: Fri, 10 Nov 2023 14:49:34 +0530
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Subject: [PATCH] firmware: qcom_scm: ipq5332: add support to pass
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metadata size
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IPQ5332 security software running under trustzone
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requires metadata size. With V2 cmd, pass metadata
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size as well.
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Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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---
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drivers/firmware/qcom_scm.c | 8 ++++++++
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drivers/firmware/qcom_scm.h | 1 +
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2 files changed, 9 insertions(+)
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--- a/drivers/firmware/qcom_scm.c
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+++ b/drivers/firmware/qcom_scm.c
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@@ -592,6 +592,14 @@ int qcom_scm_pas_mem_setup(u32 periphera
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if (ret)
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goto disable_clk;
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+ if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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+ QCOM_SCM_PAS_INIT_IMAGE_V2)) {
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+ desc.cmd = QCOM_SCM_PAS_INIT_IMAGE_V2;
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+ desc.arginfo =
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+ QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL);
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+ desc.args[2] = size;
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+ }
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+
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ret = qcom_scm_call(__scm->dev, &desc, &res);
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qcom_scm_bw_disable();
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--- a/drivers/firmware/qcom_scm.h
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+++ b/drivers/firmware/qcom_scm.h
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@@ -92,6 +92,7 @@ extern int scm_legacy_call(struct device
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#define QCOM_SCM_SVC_PIL 0x02
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#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
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+#define QCOM_SCM_PAS_INIT_IMAGE_V2 0x1a
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#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
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#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
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