34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
185 lines
5.4 KiB
Diff
185 lines
5.4 KiB
Diff
From 77ad12b3a5e21cae859247c0b82cf9a5b661e531 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:11 +0800
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Subject: [PATCH 1/3] net: phy: qcom: Introduce IPQ5018 internal PHY driver
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Introduce the internal GE PHY driver, part of the Qualcomm IPQ50xx SoC.
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The driver registers two clock providers needed and referenced by the GCC
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using DT properties and phandles.
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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drivers/net/phy/qcom/Kconfig | 6 ++
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drivers/net/phy/qcom/Makefile | 1 +
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drivers/net/phy/qcom/ipq5018.c | 138 +++++++++++++++++++++++++++++++++
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3 files changed, 145 insertions(+)
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create mode 100644 drivers/net/phy/qcom/ipq5018.c
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--- a/drivers/net/phy/qcom/Kconfig
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+++ b/drivers/net/phy/qcom/Kconfig
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@@ -9,6 +9,12 @@ config AT803X_PHY
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help
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Currently supports the AR8030, AR8031, AR8033, AR8035 model
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+config IPQ5018_PHY
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+ tristate "Qualcomm IPQ5018 internal PHYs"
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+ select QCOM_NET_PHYLIB
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+ help
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+ Currently supports the Qualcomm IPQ5018 internal PHY
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+
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config QCA83XX_PHY
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tristate "Qualcomm Atheros QCA833x PHYs"
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select QCOM_NET_PHYLIB
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--- a/drivers/net/phy/qcom/Makefile
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+++ b/drivers/net/phy/qcom/Makefile
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@@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o
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obj-$(CONFIG_AT803X_PHY) += at803x.o
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+obj-$(CONFIG_IPQ5018_PHY) += ipq5018.o
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obj-$(CONFIG_QCA83XX_PHY) += qca83xx.o
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obj-$(CONFIG_QCA808X_PHY) += qca808x.o
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obj-$(CONFIG_QCA807X_PHY) += qca807x.o
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--- /dev/null
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+++ b/drivers/net/phy/qcom/ipq5018.c
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@@ -0,0 +1,138 @@
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+#include <linux/bitfield.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+#include <linux/phy.h>
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+#include <linux/reset.h>
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+
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+#include "qcom.h"
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+
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+#define IPQ5018_PHY_ID 0x004dd0c0
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+
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+#define TX_RX_CLK_RATE 125000000 /* 125M */
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+
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+#define IPQ5018_PHY_FIFO_CONTROL 0x19
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+#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0)
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+
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+struct ipq5018_phy {
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+ int num_clks;
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+ struct clk_bulk_data *clks;
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+ struct reset_control *rst;
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+
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+ struct clk_hw *clk_rx, *clk_tx;
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+ struct clk_hw_onecell_data *clk_data;
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+};
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+
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+static int ipq5018_probe(struct phy_device *phydev)
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+{
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+ struct ipq5018_phy *priv;
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+ struct device *dev = &phydev->mdio.dev;
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+ char name[64];
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+ int ret;
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return dev_err_probe(dev, -ENOMEM,
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+ "failed to allocate priv\n");
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+
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+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
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+ if (priv->num_clks < 0)
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+ return dev_err_probe(dev, priv->num_clks,
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+ "failed to acquire clocks\n");
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+
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+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
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+ if (ret)
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+ return dev_err_probe(dev, ret,
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+ "failed to enable clocks\n");
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+
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+ priv->rst = devm_reset_control_array_get_exclusive(dev);
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+ if (IS_ERR_OR_NULL(priv->rst))
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+ return dev_err_probe(dev, PTR_ERR(priv->rst),
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+ "failed to acquire reset\n");
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+
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+ ret = reset_control_reset(priv->rst);
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+ if (ret)
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+ return dev_err_probe(dev, ret,
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+ "failed to reset\n");
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+
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+ snprintf(name, sizeof(name), "%s#rx", dev_name(dev));
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+ priv->clk_rx = clk_hw_register_fixed_rate(dev, name, NULL, 0,
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+ TX_RX_CLK_RATE);
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+ if (IS_ERR_OR_NULL(priv->clk_rx))
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+ return dev_err_probe(dev, PTR_ERR(priv->clk_rx),
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+ "failed to register rx clock\n");
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+
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+ snprintf(name, sizeof(name), "%s#tx", dev_name(dev));
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+ priv->clk_tx = clk_hw_register_fixed_rate(dev, name, NULL, 0,
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+ TX_RX_CLK_RATE);
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+ if (IS_ERR_OR_NULL(priv->clk_tx))
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+ return dev_err_probe(dev, PTR_ERR(priv->clk_tx),
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+ "failed to register tx clock\n");
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+
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+ priv->clk_data = devm_kzalloc(dev,
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+ struct_size(priv->clk_data, hws, 2),
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+ GFP_KERNEL);
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+ if (!priv->clk_data)
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+ return dev_err_probe(dev, -ENOMEM,
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+ "failed to allocate clk_data\n");
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+
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+ priv->clk_data->num = 2;
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+ priv->clk_data->hws[0] = priv->clk_rx;
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+ priv->clk_data->hws[1] = priv->clk_tx;
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+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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+ priv->clk_data);
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+ if (ret)
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+ return dev_err_probe(dev, ret,
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+ "fail to register clock provider\n");
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+
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+ return 0;
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+}
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+
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+static int ipq5018_soft_reset(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL,
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+ IPQ5018_PHY_FIFO_RESET, 0);
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+ if (ret < 0)
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+ return ret;
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+
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+ msleep(50);
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+
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+ ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL,
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+ IPQ5018_PHY_FIFO_RESET, IPQ5018_PHY_FIFO_RESET);
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+ if (ret < 0)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int ipq5018_cable_test_start(struct phy_device *phydev)
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+{
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+ /* we do all the (time consuming) work later */
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+ return 0;
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+}
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+
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+static struct phy_driver ipq5018_internal_phy_driver[] = {
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+ {
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+ PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID),
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+ .name = "Qualcomm IPQ5018 internal PHY",
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+ .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST,
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+ .probe = ipq5018_probe,
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+ .soft_reset = ipq5018_soft_reset,
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+ .read_status = at803x_read_status,
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+ .config_intr = at803x_config_intr,
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+ .handle_interrupt = at803x_handle_interrupt,
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+ .cable_test_start = ipq5018_cable_test_start,
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+ .cable_test_get_status = qca808x_cable_test_get_status,
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+ },
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+};
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+module_phy_driver(ipq5018_internal_phy_driver);
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+
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+static struct mdio_device_id __maybe_unused ipq5018_internal_phy_ids[] = {
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+ { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) },
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+ { }
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+};
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+MODULE_DEVICE_TABLE(mdio, ipq5018_internal_phy_ids);
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+
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+MODULE_DESCRIPTION("Qualcomm IPQ5018 internal PHY driver");
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+MODULE_AUTHOR("Ziyang Huang <hzyitc@outlook.com>");
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