
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.78 Removed upstreamed: bcm27xx/patches-6.6/950-0487-drivers-media-imx296-Add-standby-delay-during-probe.patch[1] mediatek/patches-6.6/256-clk-mediatek-mt2701-vdec-fix-conversion-to-mtk_clk_s.patch[2] mediatek/patches-6.6/257-clk-mediatek-mt2701-aud-fix-conversion-to-mtk_clk_si.patch[3] mediatek/patches-6.6/258-clk-mediatek-mt2701-bdp-add-missing-dummy-clk.patch[4] mediatek/patches-6.6/259-clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch[5] mediatek/patches-6.6/260-clk-mediatek-mt2701-img-add-missing-dummy-clk.patch[6] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.78&id=25abffee5ceb6691ecd4f089be2bb28842e2d2fd 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.78&id=b6c5237ab7af82c9f1d8d772dbf309bb4aadfdbb 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.78&id=20210b5c775d2d96f706591c64bc2ad975c37eaf 4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.78&id=a1fa3dda6bf0b7ecd95fa8f9125e5486b699a81f 5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.78&id=fc60e9357f15372698da373ee76de8f52d22aac2 6. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.78&id=6f4868e6b2887b55531bc8e0a4106ef0150e6326 Build system: x86/64 Build-tested: bcm27xx/bcm2712, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Run-tested: bcm27xx/bcm2712, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/18000 Signed-off-by: Robert Marko <robimarko@gmail.com>
109 lines
3.1 KiB
Diff
109 lines
3.1 KiB
Diff
From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
|
|
From: Christian Marangi <ansuelsmth@gmail.com>
|
|
Date: Tue, 9 May 2023 01:57:17 +0200
|
|
Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
|
|
|
|
comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
|
|
current problem, we are forced to use sdhci_set_clock.
|
|
|
|
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
|
---
|
|
drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
|
|
1 file changed, 43 insertions(+), 43 deletions(-)
|
|
|
|
--- a/drivers/mmc/host/sdhci-msm.c
|
|
+++ b/drivers/mmc/host/sdhci-msm.c
|
|
@@ -1804,49 +1804,49 @@ static unsigned int sdhci_msm_get_min_cl
|
|
return SDHCI_MSM_MIN_CLOCK;
|
|
}
|
|
|
|
-/*
|
|
- * __sdhci_msm_set_clock - sdhci_msm clock control.
|
|
- *
|
|
- * Description:
|
|
- * MSM controller does not use internal divider and
|
|
- * instead directly control the GCC clock as per
|
|
- * HW recommendation.
|
|
- **/
|
|
-static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
-{
|
|
- u16 clk;
|
|
-
|
|
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
|
|
-
|
|
- if (clock == 0)
|
|
- return;
|
|
-
|
|
- /*
|
|
- * MSM controller do not use clock divider.
|
|
- * Thus read SDHCI_CLOCK_CONTROL and only enable
|
|
- * clock with no divider value programmed.
|
|
- */
|
|
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
- sdhci_enable_clk(host, clk);
|
|
-}
|
|
-
|
|
-/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
|
|
-static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
-{
|
|
- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
|
|
-
|
|
- if (!clock) {
|
|
- host->mmc->actual_clock = msm_host->clk_rate = 0;
|
|
- goto out;
|
|
- }
|
|
-
|
|
- sdhci_msm_hc_select_mode(host);
|
|
-
|
|
- msm_set_clock_rate_for_bus_mode(host, clock);
|
|
-out:
|
|
- __sdhci_msm_set_clock(host, clock);
|
|
-}
|
|
+// /*
|
|
+// * __sdhci_msm_set_clock - sdhci_msm clock control.
|
|
+// *
|
|
+// * Description:
|
|
+// * MSM controller does not use internal divider and
|
|
+// * instead directly control the GCC clock as per
|
|
+// * HW recommendation.
|
|
+// **/
|
|
+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
+// {
|
|
+// u16 clk;
|
|
+
|
|
+// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
|
|
+
|
|
+// if (clock == 0)
|
|
+// return;
|
|
+
|
|
+// /*
|
|
+// * MSM controller do not use clock divider.
|
|
+// * Thus read SDHCI_CLOCK_CONTROL and only enable
|
|
+// * clock with no divider value programmed.
|
|
+// */
|
|
+// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
+// sdhci_enable_clk(host, clk);
|
|
+// }
|
|
+
|
|
+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
|
|
+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
+// {
|
|
+// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
+// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
|
|
+
|
|
+// if (!clock) {
|
|
+// host->mmc->actual_clock = msm_host->clk_rate = 0;
|
|
+// goto out;
|
|
+// }
|
|
+
|
|
+// sdhci_msm_hc_select_mode(host);
|
|
+
|
|
+// msm_set_clock_rate_for_bus_mode(host, clock);
|
|
+// out:
|
|
+// __sdhci_msm_set_clock(host, clock);
|
|
+// }
|
|
|
|
/*****************************************************************************\
|
|
* *
|