11f1f67a3e
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/17822 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
52 lines
1.4 KiB
Diff
52 lines
1.4 KiB
Diff
From 03cbf5e97bf4cd863aff002cb5e6def43f2034d0 Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Fri, 25 Oct 2024 09:25:19 +0530
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Subject: [PATCH 6/7] arm64: dts: qcom: ipq9574: Add nsscc node
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Add a node for the nss clock controller found on ipq9574 based devices.
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -12,6 +12,8 @@
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#include <dt-bindings/interconnect/qcom,ipq9574.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
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+#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
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+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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@@ -804,6 +806,26 @@
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status = "disabled";
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};
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};
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+
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+ nsscc: clock-controller@39b00000 {
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+ compatible = "qcom,ipq9574-nsscc";
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+ reg = <0x39b00000 0x80000>;
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+ clocks = <&xo_board_clk>,
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+ <&cmn_pll NSS_1200MHZ_CLK>,
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+ <&cmn_pll PPE_353MHZ_CLK>,
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+ <&gcc GPLL0_OUT_AUX>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <&gcc GCC_NSSCC_CLK>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ #power-domain-cells = <1>;
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+ #interconnect-cells = <1>;
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+ };
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};
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thermal-zones {
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