a0cbf7f5d5
Rework kernel patches for new kernel. Mainly adaptation for patch related to DTS and changes for the downstream div generalize patch that now use determine_rate. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
155 lines
3.3 KiB
Diff
155 lines
3.3 KiB
Diff
From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 18 Jan 2022 00:07:57 +0100
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Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
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and l2 for ipq8064
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Add multiple binding for cpu node, l2 node and add idle-states
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definition for ipq8064 dtsi.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Tested-by: Jonathan McDowell <noodles@earth.li>
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---
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arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
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1 file changed, 36 insertions(+)
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--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
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@@ -30,6 +30,15 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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+ clocks = <&kraitcc 0>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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};
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cpu1: cpu@1 {
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@@ -40,12 +49,36 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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+ clocks = <&kraitcc 1>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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+ };
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+
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+ idle-states {
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+ CPU_SPC: spc {
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+ compatible = "qcom,idle-state-spc";
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+ status = "disabled";
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+ entry-latency-us = <400>;
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+ exit-latency-us = <900>;
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+ min-residency-us = <3000>;
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+ };
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ qcom,saw = <&saw_l2>;
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+
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+ clocks = <&kraitcc 4>;
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+ clock-names = "l2";
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+ operating-points-v2 = <&opp_table_l2>;
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};
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};
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--- a/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi
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+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi
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@@ -2,6 +2,18 @@
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#include "qcom-ipq8064.dtsi"
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+&cpu0 {
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+ cpu-supply = <&smb208_s2a>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&smb208_s2b>;
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+};
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+
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+&L2 {
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+ l2-supply = <&smb208_s1a>;
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+};
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+
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&rpm {
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smb208_regulators: regulators {
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compatible = "qcom,rpm-smb208-regulators";
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--- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi
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+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi
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@@ -2,6 +2,18 @@
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#include "qcom-ipq8064-v2.0.dtsi"
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+&cpu0 {
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+ cpu-supply = <&smb208_s2a>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&smb208_s2b>;
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+};
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+
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+&L2 {
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+ l2-supply = <&smb208_s1a>;
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+};
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+
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&rpm {
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smb208_regulators: regulators {
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compatible = "qcom,rpm-smb208-regulators";
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--- a/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi
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+++ b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi
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@@ -2,6 +2,18 @@
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#include "qcom-ipq8062.dtsi"
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+&cpu0 {
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+ cpu-supply = <&smb208_s2a>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&smb208_s2b>;
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+};
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+
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+&L2 {
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+ l2-supply = <&smb208_s1a>;
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+};
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+
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&rpm {
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smb208_regulators: regulators {
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compatible = "qcom,rpm-smb208-regulators";
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--- a/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi
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+++ b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi
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@@ -2,6 +2,18 @@
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#include "qcom-ipq8065.dtsi"
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+&cpu0 {
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+ cpu-supply = <&smb208_s2a>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&smb208_s2b>;
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+};
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+
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+&L2 {
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+ l2-supply = <&smb208_s1a>;
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+};
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+
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&rpm {
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smb208_regulators: regulators {
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compatible = "qcom,rpm-smb208-regulators";
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