b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
185 lines
5.9 KiB
Diff
185 lines
5.9 KiB
Diff
From 56d254c9b7abf3e5632dd1b257927e23b4449019 Mon Sep 17 00:00:00 2001
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From: Dong Aisheng <aisheng.dong@nxp.com>
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Date: Fri, 16 Aug 2019 18:01:43 +0800
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Subject: [PATCH] Revert "ASoC: fsl_sai: Add registers definition for multiple
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datalines"
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This reverts commit 5f0ac20ed6db1d6da2eea8b862cf3d54fdfb5830.
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---
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sound/soc/fsl/fsl_sai.c | 76 +++++++------------------------------------------
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sound/soc/fsl/fsl_sai.h | 36 +++--------------------
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2 files changed, 14 insertions(+), 98 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -685,14 +685,7 @@ static struct reg_default fsl_sai_reg_de
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{FSL_SAI_TCR3, 0},
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{FSL_SAI_TCR4, 0},
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{FSL_SAI_TCR5, 0},
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- {FSL_SAI_TDR0, 0},
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- {FSL_SAI_TDR1, 0},
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- {FSL_SAI_TDR2, 0},
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- {FSL_SAI_TDR3, 0},
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- {FSL_SAI_TDR4, 0},
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- {FSL_SAI_TDR5, 0},
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- {FSL_SAI_TDR6, 0},
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- {FSL_SAI_TDR7, 0},
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+ {FSL_SAI_TDR, 0},
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{FSL_SAI_TMR, 0},
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{FSL_SAI_RCR1, 0},
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{FSL_SAI_RCR2, 0},
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@@ -711,14 +704,7 @@ static bool fsl_sai_readable_reg(struct
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case FSL_SAI_TCR3:
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case FSL_SAI_TCR4:
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case FSL_SAI_TCR5:
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- case FSL_SAI_TFR0:
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- case FSL_SAI_TFR1:
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- case FSL_SAI_TFR2:
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- case FSL_SAI_TFR3:
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- case FSL_SAI_TFR4:
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- case FSL_SAI_TFR5:
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- case FSL_SAI_TFR6:
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- case FSL_SAI_TFR7:
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+ case FSL_SAI_TFR:
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case FSL_SAI_TMR:
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case FSL_SAI_RCSR:
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case FSL_SAI_RCR1:
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@@ -726,22 +712,8 @@ static bool fsl_sai_readable_reg(struct
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case FSL_SAI_RCR3:
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case FSL_SAI_RCR4:
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case FSL_SAI_RCR5:
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- case FSL_SAI_RDR0:
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- case FSL_SAI_RDR1:
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- case FSL_SAI_RDR2:
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- case FSL_SAI_RDR3:
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- case FSL_SAI_RDR4:
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- case FSL_SAI_RDR5:
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- case FSL_SAI_RDR6:
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- case FSL_SAI_RDR7:
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- case FSL_SAI_RFR0:
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- case FSL_SAI_RFR1:
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- case FSL_SAI_RFR2:
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- case FSL_SAI_RFR3:
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- case FSL_SAI_RFR4:
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- case FSL_SAI_RFR5:
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- case FSL_SAI_RFR6:
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- case FSL_SAI_RFR7:
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+ case FSL_SAI_RDR:
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+ case FSL_SAI_RFR:
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case FSL_SAI_RMR:
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return true;
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default:
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@@ -754,30 +726,9 @@ static bool fsl_sai_volatile_reg(struct
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switch (reg) {
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case FSL_SAI_TCSR:
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case FSL_SAI_RCSR:
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- case FSL_SAI_TFR0:
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- case FSL_SAI_TFR1:
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- case FSL_SAI_TFR2:
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- case FSL_SAI_TFR3:
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- case FSL_SAI_TFR4:
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- case FSL_SAI_TFR5:
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- case FSL_SAI_TFR6:
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- case FSL_SAI_TFR7:
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- case FSL_SAI_RFR0:
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- case FSL_SAI_RFR1:
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- case FSL_SAI_RFR2:
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- case FSL_SAI_RFR3:
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- case FSL_SAI_RFR4:
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- case FSL_SAI_RFR5:
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- case FSL_SAI_RFR6:
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- case FSL_SAI_RFR7:
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- case FSL_SAI_RDR0:
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- case FSL_SAI_RDR1:
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- case FSL_SAI_RDR2:
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- case FSL_SAI_RDR3:
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- case FSL_SAI_RDR4:
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- case FSL_SAI_RDR5:
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- case FSL_SAI_RDR6:
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- case FSL_SAI_RDR7:
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+ case FSL_SAI_TFR:
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+ case FSL_SAI_RFR:
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+ case FSL_SAI_RDR:
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return true;
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default:
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return false;
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@@ -793,14 +744,7 @@ static bool fsl_sai_writeable_reg(struct
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case FSL_SAI_TCR3:
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case FSL_SAI_TCR4:
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case FSL_SAI_TCR5:
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- case FSL_SAI_TDR0:
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- case FSL_SAI_TDR1:
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- case FSL_SAI_TDR2:
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- case FSL_SAI_TDR3:
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- case FSL_SAI_TDR4:
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- case FSL_SAI_TDR5:
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- case FSL_SAI_TDR6:
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- case FSL_SAI_TDR7:
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+ case FSL_SAI_TDR:
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case FSL_SAI_TMR:
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case FSL_SAI_RCSR:
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case FSL_SAI_RCR1:
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@@ -942,8 +886,8 @@ static int fsl_sai_probe(struct platform
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MCLK_DIR(index));
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}
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- sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
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- sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
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+ sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
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+ sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
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sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
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sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
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--- a/sound/soc/fsl/fsl_sai.h
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+++ b/sound/soc/fsl/fsl_sai.h
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@@ -20,22 +20,8 @@
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#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
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#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
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#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
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-#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
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-#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
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-#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
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-#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
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-#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
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-#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
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-#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
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-#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
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-#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
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-#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
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-#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
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-#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
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-#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
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-#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
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-#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
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-#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
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+#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */
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+#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
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#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
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#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
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#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
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@@ -43,22 +29,8 @@
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#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
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#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
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#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
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-#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
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-#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
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-#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
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-#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
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-#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
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-#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
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-#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
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-#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
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-#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
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-#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
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-#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
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-#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
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-#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
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-#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
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-#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
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-#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
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+#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */
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+#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */
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#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
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#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
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