c4c986e419
Certain AP148 platforms (and derivative) use bootloaders which did not have DT enabled. In order to support these old platforms, we'll now make the following modifications: *explicitely add the memory node in the AP148 DT: this used to be added by new u-boot through a run-time patch mechanism. We'll now add it explicitely so it works on boots which don't support that feature. New boots will have the node twice, the second one will be ignored. *add the zImage generation next to the FIT image for AP148. Other platforms using non-DT enabled bootloaders may want to leverage this zImage code to generate their own firmare as well. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46555
146 lines
3.1 KiB
Diff
146 lines
3.1 KiB
Diff
From e81de9d28bd0421c236df322872e64edf4ee1852 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Mon, 11 May 2015 16:32:09 -0700
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Subject: [PATCH 7/8] ARM: dts: qcom: add mdio nodes to ap148 & db149
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 ++++++++++++++++++++++++++-
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arch/arm/boot/dts/qcom-ipq8064-db149.dts | 46 ++++++++++++++++++++++++++++++++
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2 files changed, 85 insertions(+), 1 deletion(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -19,8 +19,9 @@
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};
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};
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- alias {
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+ aliases {
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serial0 = &uart4;
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+ mdio-gpio0 = &mdio0;
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};
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chosen {
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@@ -59,6 +60,15 @@
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bias-none;
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};
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};
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+
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+ mdio0_pins: mdio0_pins {
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+ mux {
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+ pins = "gpio0", "gpio1";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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};
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gsbi@16300000 {
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@@ -144,5 +154,33 @@
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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};
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+
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+ mdio0: mdio {
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+ compatible = "virtual,mdio-gpio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
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+ pinctrl-0 = <&mdio0_pins>;
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+ pinctrl-names = "default";
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+
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+ phy0: ethernet-phy@0 {
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+ device_type = "ethernet-phy";
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+ reg = <0>;
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+ qca,ar8327-initvals = <
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+ 0x00004 0x7600000 /* PAD0_MODE */
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+ 0x00008 0x1000000 /* PAD5_MODE */
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+ 0x0000c 0x80 /* PAD6_MODE */
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+ 0x000e4 0xaa545 /* MAC_POWER_SEL */
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+ 0x000e0 0xc74164de /* SGMII_CTRL */
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+ 0x0007c 0x4e /* PORT0_STATUS */
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+ 0x00094 0x4e /* PORT6_STATUS */
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+ >;
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+ };
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+
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+ phy4: ethernet-phy@4 {
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+ device_type = "ethernet-phy";
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+ reg = <4>;
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+ };
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -16,6 +16,7 @@
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alias {
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serial0 = &uart2;
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+ mdio-gpio0 = &mdio0;
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};
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chosen {
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@@ -62,6 +63,15 @@
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bias-none;
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};
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};
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+
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+ mdio0_pins: mdio0_pins {
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+ mux {
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+ pins = "gpio0", "gpio1";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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};
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gsbi2: gsbi@12480000 {
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@@ -173,5 +183,44 @@
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pinctrl-0 = <&pcie3_pins>;
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pinctrl-names = "default";
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};
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+
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+ mdio0: mdio {
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+ compatible = "virtual,mdio-gpio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
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+
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+ pinctrl-0 = <&mdio0_pins>;
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+ pinctrl-names = "default";
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+
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+ phy0: ethernet-phy@0 {
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+ device_type = "ethernet-phy";
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+ reg = <0>;
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+ qca,ar8327-initvals = <
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+ 0x00004 0x7600000 /* PAD0_MODE */
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+ 0x00008 0x1000000 /* PAD5_MODE */
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+ 0x0000c 0x80 /* PAD6_MODE */
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+ 0x000e4 0xaa545 /* MAC_POWER_SEL */
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+ 0x000e0 0xc74164de /* SGMII_CTRL */
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+ 0x0007c 0x4e /* PORT0_STATUS */
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+ 0x00094 0x4e /* PORT6_STATUS */
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+ >;
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+ };
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+
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+ phy4: ethernet-phy@4 {
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+ device_type = "ethernet-phy";
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+ reg = <4>;
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+ };
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+
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+ phy6: ethernet-phy@6 {
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+ device_type = "ethernet-phy";
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+ reg = <6>;
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+ };
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+
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+ phy7: ethernet-phy@7 {
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+ device_type = "ethernet-phy";
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+ reg = <7>;
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+ };
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+ };
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};
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};
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