From 52315bec6ed633b6a71f28b746029602f8bd70b9 Mon Sep 17 00:00:00 2001
From: Balaji Prakash J <bjagadee@codeaurora.org>
Date: Wed, 22 Apr 2020 20:35:30 +0530
Subject: [PATCH] clk: ipq8074: fix gcc_blsp1_ahb_clk properties

All the voting enabled clocks does not support the enable
from CBCR register. So, updated gcc_blsp1_ahb_clk enable
register and mask to enable bit in APCS_CLOCK_BRANCH_ENA_VOTE.

Also, the voting controlled clocks are shared among multiple
components like APSS, RPM, NSS, TZ, etc. So, turning the
voting off from APSS does not make the clock off if it has
been voted from another component. Added the flag
BRANCH_HALT_VOTED in order to skip checking the clock
disable status.

This change is referred from the below commits,
1. 246b4fb3af9bd65d8af794aac2f0e7b1ed9cc2dd
2. c8374157d5ae91d3b3e0d513d62808a798b32d3a

Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230
---
 drivers/clk/qcom/gcc-ipq8074.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -2127,9 +2127,10 @@ struct clk_rcg2 adss_pwm_clk_src = {
 
 static struct clk_branch gcc_blsp1_ahb_clk = {
 	.halt_reg = 0x01008,
+	.halt_check = BRANCH_HALT_VOTED,
 	.clkr = {
-		.enable_reg = 0x01008,
-		.enable_mask = BIT(0),
+		.enable_reg = 0x0b004,
+		.enable_mask = BIT(10),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_ahb_clk",
 			.parent_hws = (const struct clk_hw *[]){
