From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes
Date: Tue, 3 Oct 2023 17:38:45 +0530

Add phy and controller nodes for PCIe0 and PCIe1.
PCIe0 is 2-lane Gen2 and PCIe1 is 1-lane Gen2.

Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 186 +++++++++++++++++++++++++-
 1 file changed, 184 insertions(+), 2 deletions(-)

--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -149,6 +149,42 @@
 			status = "disabled";
 		};
 
+		pcie1_phy: phy@7e000{
+			compatible = "qcom,ipq5018-uniphy-pcie-phy";
+			reg = <0x0007e000 0x800>;
+
+			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+
+			resets = <&gcc GCC_PCIE1_PHY_BCR>,
+					 <&gcc GCC_PCIE1PHY_PHY_BCR>;
+
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			num-lanes = <1>;
+
+			status = "disabled";
+		};
+
+		pcie0_phy: phy@86000{
+			compatible = "qcom,ipq5018-uniphy-pcie-phy";
+			reg = <0x00086000 0x800>;
+
+			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+
+			resets = <&gcc GCC_PCIE0_PHY_BCR>,
+					 <&gcc GCC_PCIE0PHY_PHY_BCR>;
+
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			num-lanes = <2>;
+
+			status = "disabled";
+		};
+
 		qfprom: qfprom@a0000 {
 			compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
 			reg = <0xa0000 0x1000>;
@@ -283,8 +319,8 @@
 			reg = <0x01800000 0x80000>;
 			clocks = <&xo_board_clk>,
 				 <&sleep_clk>,
-				 <0>,
-				 <0>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
 				 <0>,
 				 <0>,
 				 <0>,
@@ -501,6 +537,146 @@
 				status = "disabled";
 			};
 		};
+
+		pcie1: pcie@80000000 {
+			compatible = "qcom,pcie-ipq5018";
+			reg = <0x80000000 0xf1d>,
+				  <0x80000f20 0xa8>,
+				  <0x80001000 0x1000>,
+				  <0x00078000 0x3000>,
+				  <0x80100000 0x1000>;
+			reg-names = "dbi",
+						"elbi",
+						"atu",
+						"parf",
+						"config";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			max-link-speed = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			phys = <&pcie1_phy>;
+			phy-names ="pciephy";
+
+			ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>,	/* I/O */
+				  	 <0x82000000 0 0x80300000 0x80300000 0 0x10000000>;	/* MEM */
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+							<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+							<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+							<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global_irq";
+
+			clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+					 <&gcc GCC_PCIE1_AXI_M_CLK>,
+					 <&gcc GCC_PCIE1_AXI_S_CLK>,
+					 <&gcc GCC_PCIE1_AHB_CLK>,
+					 <&gcc GCC_PCIE1_AUX_CLK>,
+					 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
+			clock-names = "iface",
+						  "axi_m",
+						  "axi_s",
+						  "ahb",
+						  "aux",
+						  "axi_bridge";
+
+			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+					 <&gcc GCC_PCIE1_SLEEP_ARES>,
+					 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+					 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+					 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+					 <&gcc GCC_PCIE1_AHB_ARES>,
+					 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
+					 <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
+			reset-names = "pipe",
+						  "sleep",
+						  "sticky",
+						  "axi_m",
+						  "axi_s",
+						  "ahb",
+						  "axi_m_sticky",
+						  "axi_s_sticky";
+
+			msi-map = <0x0 &v2m0 0x0 0xff8>;
+			status = "disabled";
+		};
+
+		pcie0: pcie@a0000000 {
+			compatible = "qcom,pcie-ipq5018";
+			reg = <0xa0000000 0xf1d>,
+				  <0xa0000f20 0xa8>,
+				  <0xa0001000 0x1000>,
+				  <0x00080000 0x3000>,
+				  <0xa0100000 0x1000>;
+			reg-names = "dbi",
+						"elbi",
+						"atu",
+						"parf",
+						"config";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <2>;
+			max-link-speed = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			phys = <&pcie0_phy>;
+			phy-names ="pciephy";
+
+			ranges = <0x81000000 0 0xa0200000 0xa0200000 0 0x00100000>,	/* I/O */
+				  	 <0x82000000 0 0xa0300000 0xa0300000 0 0x10000000>;	/* MEM */
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+							<0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+							<0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+							<0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global_irq";
+
+			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+					 <&gcc GCC_PCIE0_AXI_M_CLK>,
+					 <&gcc GCC_PCIE0_AXI_S_CLK>,
+					 <&gcc GCC_PCIE0_AHB_CLK>,
+					 <&gcc GCC_PCIE0_AUX_CLK>,
+					 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
+			clock-names = "iface",
+						  "axi_m",
+						  "axi_s",
+						  "ahb",
+						  "aux",
+						  "axi_bridge";
+
+			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+					 <&gcc GCC_PCIE0_SLEEP_ARES>,
+					 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+					 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+					 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+					 <&gcc GCC_PCIE0_AHB_ARES>,
+					 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+					 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+			reset-names = "pipe",
+						  "sleep",
+						  "sticky",
+						  "axi_m",
+						  "axi_s",
+						  "ahb",
+						  "axi_m_sticky",
+						  "axi_s_sticky";
+
+			msi-map = <0x0 &v2m0 0x0 0xff8>;
+			status = "disabled";
+		};
 	};
 
 	thermal-zones {
