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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2025-04-03 18:10:21 +08:00
commit 1d18cfed2c
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GPG Key ID: 6850B6345C862176
12 changed files with 454 additions and 120 deletions
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2
package/kernel/ath10k-ct/Makefile
View File

@ -1,7 +1,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=ath10k-ct
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_LICENSE:=GPLv2
PKG_LICENSE_FILES:=

60
package/kernel/ath10k-ct/patches/130-ath10k-read-qcom-coexist-support-as-a-u32.patch
View File

@ -1,60 +0,0 @@
From 630df9786fdaeb78c21f1e28c9b70ac83a1b482c Mon Sep 17 00:00:00 2001
From: Vincent Tremblay <vincent@vtremblay.dev>
Date: Sat, 31 Dec 2022 09:24:00 -0500
Subject: [PATCH] ath10k: read qcom,coexist-support as a u32
Read qcom,coexist-support as a u32 instead of a u8
When we set the property to <1> in the DT (as specified in the doc),
"of_property_read_u8" read 0 instead of 1. This is because of the data format.
By default <1> is written with 32 bits.
The problem is that the driver is trying to read a u8.
The difference can be visualized using hexdump in a running device:
Default 32 bits output:
=======================
0000000 0000 0100
0000004
8 bits output:
==============
0000000 0001
0000001
By changing "of_property_read_u8" by "of_property_read_u32", the driver
is aligned with the documentation and is able to read the value without
modifying the DT.
The other solution would be to force the value in the DT to be saved as
an 8 bits value (qcom,coexist-support = /bits/ 8 <1>),
which is against the doc and less intuitive.
Validation:
===========
The patch was tested on a real device and we can see in the debug logs
that the feature is properly initialized:
[ 109.102097] ath10k_ahb a000000.wifi: boot coex_support 1 coex_gpio_pin 52
Signed-off-by: Vincent Tremblay <vincent@vtremblay.dev>
--- a/ath10k-6.14/core.c
+++ b/ath10k-6.14/core.c
@@ -2888,14 +2888,14 @@ done:
static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
{
struct device_node *node;
- u8 coex_support = 0;
+ u32 coex_support = 0;
int ret;
node = ar->dev->of_node;
if (!node)
goto out;
- ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
+ ret = of_property_read_u32(node, "qcom,coexist-support", &coex_support);
if (ret) {
ar->coex_support = true;
goto out;

6
package/kernel/bcm63xx-cfe/Makefile
View File

@ -6,9 +6,9 @@ PKG_RELEASE:=1
PKG_SOURCE_URL:=https://github.com/openwrt/bcm63xx-cfe.git
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2024-06-25
PKG_SOURCE_VERSION:=6519bd2dde3535cafeea43157755f4dbef2f90c5
PKG_MIRROR_HASH:=db4da580b7a611a2b4ddd4ff812e5f8ddfd9694b6f5fd8246a341e61967c00ef
PKG_SOURCE_DATE:=2025-04-02
PKG_SOURCE_VERSION:=b8128fa4bdcdaf97549138965b00d5d7ceb7bb0f
PKG_MIRROR_HASH:=d33fad4fb5f4419bb287f3c3df6cceabab01fc7852c24cf29a15befa38cc0d45
PKG_FLAGS:=nonshared

13
target/linux/bmips/bcm63268/base-files/etc/board.d/02_network
View File

@ -5,6 +5,13 @@
board_config_update
case "$(board_name)" in
actiontec,t1200h |\
comtrend,vg-8050 |\
sagem,fast-3864-op |\
sercomm,shg2500)
ucidef_set_bridge_device switch
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
comtrend,vr-3032u |\
smartrg,sr505n)
ucidef_set_bridge_device switch
@ -17,12 +24,6 @@ sercomm,h500-s-vfes)
ucidef_set_interface "qtn" device "wifi" protocol "static" ipaddr "1.1.1.1" netmask "255.255.255.252"
uci add_list firewall.@zone[0].network='qtn'
;;
comtrend,vg-8050 |\
sagem,fast-3864-op |\
sercomm,shg2500)
ucidef_set_bridge_device switch
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
esac
board_config_flush

1
target/linux/bmips/bcm63268/base-files/lib/upgrade/platform.sh
View File

@ -9,6 +9,7 @@ platform_check_image() {
platform_do_upgrade() {
case "$(board_name)" in
actiontec,t1200h |\
comtrend,vg-8050 |\
comtrend,vr-3032u |\
sagem,fast-3864-op)

253
target/linux/bmips/dts/bcm63168-actiontec-t1200h.dts Normal file
View File

@ -0,0 +1,253 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "bcm63268.dtsi"
/ {
model = "Actiontec T1200H";
compatible = "actiontec,t1200h", "brcm,bcm63168", "brcm,bcm63268";
aliases {
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_green;
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
reset {
label = "reset";
gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
};
wps {
label = "wps";
gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
label = "red:internet";
color = <LED_COLOR_ID_RED>;
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
};
led-1 {
label = "green:internet";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
led-9 {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
};
led_power_green: led-20 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
};
led-22 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
led_power_red: led-35 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
panic-indicator;
};
led-39 {
function = LED_FUNCTION_WLAN;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
};
led-43 {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
};
led-44 {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
led-46 {
label = "green:dsl";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
led-49 {
label = "red:dsl";
color = <LED_COLOR_ID_RED>;
gpios = <&gpio 49 GPIO_ACTIVE_LOW>;
};
};
};
&ehci {
status = "okay";
};
&ethernet {
status = "okay";
nvmem-cells = <&macaddr_cferom_6a0>;
nvmem-cell-names = "mac-address";
};
&mdio_ext {
switch@1e {
compatible = "brcm,bcm53125";
reg = <0x1e>;
dsa,member = <1 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@8 {
reg = <0x8>;
phy-mode = "rgmii";
ethernet = <&switch0port6>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&nflash {
status = "okay";
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-step-size = <512>;
nand-ecc-strength = <15>;
nand-on-flash-bbt;
brcm,nand-oob-sector-size = <64>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "cferom";
reg = <0x0 0x20000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_cferom_6a0: macaddr@6a0 {
reg = <0x6a0 0x6>;
};
};
};
partition@20000 {
compatible = "brcm,wfi-split";
label = "wfi";
reg = <0x20000 0x7ac0000>;
};
partition@7b00000 {
label = "data";
reg = <0x7b00000 0x400000>;
read-only;
};
};
};
};
&ohci {
status = "okay";
};
&pcie {
status = "okay";
};
&switch0 {
dsa,member = <0 0>;
ports {
port@3 {
reg = <3>;
label = "wan";
phy-handle = <&phy4>;
};
switch0port6: port@6 {
reg = <6>;
label = "extsw";
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&uart0 {
status = "okay";
};
&usbh {
status = "okay";
};

19
target/linux/bmips/image/bcm63268.mk
View File

@ -1,5 +1,24 @@
# SPDX-License-Identifier: GPL-2.0-or-later
define Device/actiontec_t1200h
$(Device/bcm63xx-nand)
DEVICE_VENDOR := Actiontec
DEVICE_MODEL := T1200H
CHIP_ID := 63268
SOC := bcm63168
CFE_RAM_FILE := actiontec,t1200h/cferam.000
CFE_RAM_JFFS2_NAME := cferam.000
BLOCKSIZE := 128k
PAGESIZE := 2048
SUBPAGESIZE := 512
VID_HDR_OFFSET := 2048
DEVICE_PACKAGES += $(USB2_PACKAGES) \
kmod-leds-gpio
CFE_WFI_FLASH_TYPE := 3
CFE_WFI_VERSION := 0x5732
endef
TARGET_DEVICES += actiontec_t1200h
define Device/comtrend_vg-8050
$(Device/bcm63xx-nand)
DEVICE_VENDOR := Comtrend

2
target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dtsi
View File

@ -274,7 +274,7 @@
pinctrl-0 = <&wifi_0_pins>;
pinctrl-names = "default";
qcom,coexist-support = <1>;
qcom,coexist-support = /bits/ 8 <1>;
qcom,coexist-gpio-pin = <52>;
};

123
target/linux/octeon/patches-6.6/702-qca833x-force-pcs-reset.patch Normal file
View File

@ -0,0 +1,123 @@
From: Andrew LaMarche <andrewjlamarche@gmail.com>
Date: Mon, 31 Mar 2025 13:00:00 +0000
Subject: [PATCH] octeon: force pcs reset
QCA833x devices misbehave with SGMII until a PCS reset is triggered. U-boot has
a newer vendor GPL dump that contains logic to reset the PCS. This patch
backports that functionality so that Octeon devices with QCA833{4/7} switchs
pass traffic between the switch and CPU.
References:
- https://github.com/u-boot/u-boot/blob/master/arch/mips/mach-octeon/cvmx-helper-sgmii.c#L197-L225
- https://github.com/u-boot/u-boot/blob/master/arch/mips/mach-octeon/cvmx-helper-sgmii.c#L701-L737
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -125,6 +125,17 @@ static int __cvmx_helper_sgmii_hardware_
return 0;
}
+static int __cvmx_helper_need_g15618(void)
+{
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN68XX))
+ return 1;
+ else
+ return 0;
+}
+
/**
* Initialize the SERTES link for the first time or after a loss
* of link.
@@ -172,6 +183,39 @@ static int __cvmx_helper_sgmii_hardware_
cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
control_reg.u64);
+ /* Force a PCS reset by powering down the PCS interface
+ * This is needed to deal with broken Qualcomm/Atheros PHYs and switches
+ * which never recover if PCS is not power cycled. The alternative
+ * is to power cycle or hardware reset the Qualcomm devices whenever
+ * SGMII is initialized.
+ *
+ * This is needed for the QCA8033 PHYs as well as the QCA833X switches
+ * to work. The QCA8337 switch has additional SGMII problems and is
+ * best avoided if at all possible. Failure to power cycle PCS prevents
+ * any traffic from flowing between Octeon and Qualcomm devices if there
+ * is a warm reset. Even a software reset to the Qualcomm device will
+ * not work.
+ *
+ * Note that this problem has been reported between Qualcomm and other
+ * vendor's processors as well so this problem is not unique to
+ * Qualcomm and Octeon.
+ *
+ * Power cycling PCS doesn't hurt anything with non-Qualcomm devices
+ * other than adding a 25ms delay during initialization.
+ */
+ control_reg.s.pwr_dn = 1;
+ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+ control_reg.u64);
+ cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+ /* 25ms should be enough, 10ms is too short */
+ mdelay(25);
+
+ control_reg.s.pwr_dn = 0;
+ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+ control_reg.u64);
+
/*
* Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
* that sgmii autonegotiation is complete. In MAC mode this
@@ -507,9 +551,47 @@ union cvmx_helper_link_info __cvmx_helpe
int __cvmx_helper_sgmii_link_set(int ipd_port,
union cvmx_helper_link_info link_info)
{
+ union cvmx_pcsx_mrx_control_reg control_reg;
int interface = cvmx_helper_get_interface_num(ipd_port);
int index = cvmx_helper_get_interface_index_num(ipd_port);
- __cvmx_helper_sgmii_hardware_init_link(interface, index);
+
+ /* For some devices, i.e. the Qualcomm QCA8337 switch we need to power
+ * down the PCS interface when the link goes down and power it back
+ * up when the link returns.
+ */
+ if (link_info.s.link_up || !__cvmx_helper_need_g15618()) {
+ __cvmx_helper_sgmii_hardware_init_link(interface, index);
+ } else {
+ union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
+
+ pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+
+ /* Disable autonegotiation when MAC mode is enabled or
+ * autonegotiation is disabled.
+ */
+ control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+ if (pcsx_miscx_ctl_reg.s.mac_phy == 0 ||
+ !cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface))) {
+
+ control_reg.s.an_en = 0;
+ control_reg.s.spdmsb = 1;
+ control_reg.s.spdlsb = 0;
+ control_reg.s.dup = 1;
+
+ }
+ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+ control_reg.u64);
+ cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+ /*
+ * Use GMXENO to force the link down it will get
+ * reenabled later...
+ */
+ pcsx_miscx_ctl_reg.s.gmxeno = 1;
+ cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
+ pcsx_miscx_ctl_reg.u64);
+ cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+ return 0;
+ }
return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
link_info);
}

86
target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c
View File

@ -798,10 +798,6 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
{
struct rtl838x_switch_priv *priv = ds->priv;
int sds_num;
u32 reg;
pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
port, mode, phy_modes(state->interface), state->speed, state->link);
/* Nothing to be done for the CPU-port */
if (port == priv->cpu_port)
@ -817,48 +813,6 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
state->interface == PHY_INTERFACE_MODE_SGMII ||
state->interface == PHY_INTERFACE_MODE_10GBASER))
rtl9300_serdes_setup(port, sds_num, state->interface);
reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
reg &= ~(0xf << 3);
switch (state->speed) {
case SPEED_10000:
reg |= 4 << 3;
break;
case SPEED_5000:
reg |= 6 << 3;
break;
case SPEED_2500:
reg |= 5 << 3;
break;
case SPEED_1000:
reg |= 2 << 3;
break;
case SPEED_100:
reg |= 1 << 3;
break;
default:
/* Also covers 10M */
break;
}
if (state->link)
reg |= RTL930X_FORCE_LINK_EN;
if (priv->lagmembers & BIT_ULL(port))
reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
if (state->duplex == DUPLEX_FULL)
reg |= RTL930X_DUPLEX_MODE;
else
reg &= ~RTL930X_DUPLEX_MODE; /* Clear duplex bit otherwise */
if (priv->ports[port].phy_is_integrated)
reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
else
reg |= RTL930X_FORCE_EN;
sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
}
static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
@ -964,11 +918,49 @@ static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
int speed, int duplex,
bool tx_pause, bool rx_pause)
{
struct dsa_port *dp = dsa_to_port(ds, port);
struct rtl838x_switch_priv *priv = ds->priv;
u32 mcr, spdsel;
if (speed == SPEED_10000)
spdsel = RTL_SPEED_10000;
else if (speed == SPEED_5000)
spdsel = RTL_SPEED_5000;
else if (speed == SPEED_2500)
spdsel = RTL_SPEED_2500;
else if (speed == SPEED_1000)
spdsel = RTL_SPEED_1000;
else if (speed == SPEED_100)
spdsel = RTL_SPEED_100;
else
spdsel = RTL_SPEED_10;
mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
if (priv->family_id == RTL9300_FAMILY_ID) {
mcr &= ~RTL930X_RX_PAUSE_EN;
mcr &= ~RTL930X_TX_PAUSE_EN;
mcr &= ~RTL930X_DUPLEX_MODE;
mcr &= ~RTL930X_SPEED_MASK;
mcr |= RTL930X_FORCE_LINK_EN;
mcr |= spdsel << RTL930X_SPEED_SHIFT;
if (tx_pause)
mcr |= RTL930X_TX_PAUSE_EN;
if (rx_pause)
mcr |= RTL930X_RX_PAUSE_EN;
if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port))
mcr |= RTL930X_DUPLEX_MODE;
if (dsa_port_is_cpu(dp) || !priv->ports[port].phy_is_integrated)
mcr |= RTL930X_FORCE_EN;
}
pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n",
__func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
/* Restart TX/RX to port */
sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
/* TODO: Set speed/duplex/pauses */
}
static void rtl83xx_get_strings(struct dsa_switch *ds,

5
target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/rtl838x.h
View File

@ -147,6 +147,9 @@
#define RTL_SPEED_10 0
#define RTL_SPEED_100 1
#define RTL_SPEED_1000 2
#define RTL_SPEED_2500 5
#define RTL_SPEED_5000 6
#define RTL_SPEED_10000 4
#define RTL83XX_FORCE_EN (1 << 0)
#define RTL83XX_FORCE_LINK_EN (1 << 1)
@ -169,6 +172,8 @@
#define RTL930X_FORCE_EN (1 << 0)
#define RTL930X_FORCE_LINK_EN (1 << 1)
#define RTL930X_DUPLEX_MODE (1 << 2)
#define RTL930X_SPEED_SHIFT (3)
#define RTL930X_SPEED_MASK (15 << RTL930X_SPEED_SHIFT)
#define RTL930X_TX_PAUSE_EN (1 << 7)
#define RTL930X_RX_PAUSE_EN (1 << 8)
#define RTL930X_MAC_FORCE_FC_EN (1 << 9)

4
tools/xz/Makefile
View File

@ -7,13 +7,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=xz
PKG_VERSION:=5.6.4
PKG_VERSION:=5.8.0
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://github.com/tukaani-project/xz/releases/download/v$(PKG_VERSION) \
@SF/lzmautils \
http://tukaani.org/xz
PKG_HASH:=176d510c30d80a23b8050bbc048f2ecaacb823ae48b6821727ed6591f0df9200
PKG_HASH:=8c107270289807e2047f35d687b4d7a5bb029137f7c89ebdcfa909cb3b674440
PKG_CPE_ID:=cpe:/a:tukaani:xz
HOST_BUILD_PARALLEL:=1