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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2025-01-11 00:34:41 +08:00
commit 3d1bbeb50b
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
85 changed files with 2355 additions and 924 deletions
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4
include/kernel-6.6
View File

@ -1,2 +1,2 @@
LINUX_VERSION-6.6 = .69
LINUX_KERNEL_HASH-6.6.69 = 9c6305567b75d99514cde6eb9de39973f3d5c857a75bd9dcdfca57041f8d4f34
LINUX_VERSION-6.6 = .70
LINUX_KERNEL_HASH-6.6.70 = 84d23ee07fb26febbcb6d1295ba15efdc67ac382b4137b2c8853146c10fd2f97

6
include/package-pack.mk
View File

@ -302,7 +302,7 @@ else
echo 'export pkgname="$(1)"'; \
echo "add_group_and_user"; \
echo "default_postinst"; \
[ ! -f $$(ADIR_$(1))/postinst-pkg ] || cat "$$(ADIR_$(1))/postinst-pkg"; \
[ ! -f $$(ADIR_$(1))/postinst-pkg ] || sed -z 's/^\s*#!/#!/' "$$(ADIR_$(1))/postinst-pkg"; \
) > $$(ADIR_$(1))/post-install;
( \
@ -312,9 +312,11 @@ else
echo 'export root="$$$${IPKG_INSTROOT}"'; \
echo 'export pkgname="$(1)"'; \
echo "default_prerm"; \
[ ! -f $$(ADIR_$(1))/prerm-pkg ] || cat "$$(ADIR_$(1))/prerm-pkg"; \
[ ! -f $$(ADIR_$(1))/prerm-pkg ] || sed -z 's/^\s*#!/#!/' "$$(ADIR_$(1))/prerm-pkg"; \
) > $$(ADIR_$(1))/pre-deinstall;
[ ! -f $$(ADIR_$(1))/postrm ] || sed -zi 's/^\s*#!/#!/' "$$(ADIR_$(1))/postrm";
if [ -n "$(USERID)" ]; then echo $(USERID) > $$(IDIR_$(1))/lib/apk/packages/$(1).rusers; fi;
if [ -n "$(ALTERNATIVES)" ]; then echo $(ALTERNATIVES) > $$(IDIR_$(1))/lib/apk/packages/$(1).alternatives; fi;
(cd $$(IDIR_$(1)) && find . -type f,l -printf "/%P\n" > $$(IDIR_$(1))/lib/apk/packages/$(1).list)

3
package/kernel/linux/modules/netsupport.mk
View File

@ -1026,7 +1026,7 @@ endef
$(eval $(call KernelPackage,bpf-test))
SCHED_MODULES_EXTRA = sch_codel sch_gred sch_multiq sch_sfq sch_teql sch_fq act_pedit act_simple act_skbmod act_csum em_cmp em_nbyte em_meta em_text
SCHED_MODULES_EXTRA = sch_codel sch_gred sch_multiq sch_sfq sch_teql sch_fq sch_ets act_pedit act_simple act_skbmod act_csum em_cmp em_nbyte em_meta em_text
SCHED_FILES_EXTRA = $(foreach mod,$(SCHED_MODULES_EXTRA),$(LINUX_DIR)/net/sched/$(mod).ko)
define KernelPackage/sched
@ -1040,6 +1040,7 @@ define KernelPackage/sched
CONFIG_NET_SCH_SFQ \
CONFIG_NET_SCH_TEQL \
CONFIG_NET_SCH_FQ \
CONFIG_NET_SCH_ETS \
CONFIG_NET_ACT_PEDIT \
CONFIG_NET_ACT_SIMP \
CONFIG_NET_ACT_SKBMOD \

11
target/linux/airoha/an7581/config-6.6
View File

@ -131,6 +131,8 @@ CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_COREDUMP=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPUSETS=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
@ -190,8 +192,6 @@ CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
CONFIG_DEBUG_INFO_NONE=y
CONFIG_DEBUG_MISC=y
CONFIG_DEVMEM=y
CONFIG_DMADEVICES=y
@ -351,6 +351,10 @@ CONFIG_MDIO_DEVRES=y
# CONFIG_MEMCG is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_RELA=y
@ -433,7 +437,8 @@ CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIE_MEDIATEK is not set
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_MEDIATEK_GEN3=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y

45
target/linux/airoha/dts/an7581-evb.dts
View File

@ -150,35 +150,40 @@
&spi_nand {
partitions {
compatible = "airoha,fixed-partitions";
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootloader@0 {
label = "bootloader";
reg = <0x00000000 0x00080000>;
read-only;
};
tclinux@80000 {
label = "tclinux";
compatible = "denx,fit";
reg = <0x00080000 0x02800000>;
};
tclinux_slave@2880000 {
label = "tclinux_slave";
reg = <0x02880000 0x02800000>;
};
rootfs_data@5080000 {
label = "rootfs_data";
reg = <0x5080000 0x00800000>;
};
art@ffffffff {
compatible = "airoha,dynamic-art";
art@200000 {
label = "art";
reg = <0xffffffff 0x00300000>;
reg = <0x00200000 0x00400000>;
};
tclinux@600000 {
label = "tclinux";
reg = <0x00600000 0x03200000>;
};
tclinux_slave@3800000 {
label = "tclinux_alt";
reg = <0x03800000 0x03200000>;
};
rootfs_data@6a00000 {
label = "rootfs_data";
reg = <0x06a00000 0x01400000>;
};
reserved_bmt@7e00000 {
label = "reserved_bmt";
reg = <0x07e00000 0x00200000>;
read-only;
};
};
};

118
target/linux/airoha/dts/an7581.dtsi
View File

@ -78,7 +78,10 @@
reg = <0x0>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
clocks = <&cpufreq>;
clock-names = "cpu";
power-domains = <&cpufreq>;
power-domain-names = "cpu_pd";
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -89,7 +92,10 @@
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
clocks = <&cpufreq>;
clock-names = "cpu";
power-domains = <&cpufreq>;
power-domain-names = "cpu_pd";
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -100,7 +106,10 @@
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
clocks = <&cpufreq>;
clock-names = "cpu";
power-domains = <&cpufreq>;
power-domain-names = "cpu_pd";
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -111,7 +120,10 @@
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
clocks = <&cpufreq>;
clock-names = "cpu";
power-domains = <&cpufreq>;
power-domain-names = "cpu_pd";
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@ -125,68 +137,156 @@
};
};
cpufreq: cpufreq {
compatible = "airoha,en7581-cpufreq";
operating-points-v2 = <&cpu_smcc_opp_table>;
#power-domain-cells = <0>;
#clock-cells = <0>;
};
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
required-opps = <&smcc_opp0>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
required-opps = <&smcc_opp1>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
required-opps = <&smcc_opp2>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
required-opps = <&smcc_opp3>;
};
opp-7000000000 {
opp-hz = /bits/ 64 <700000000>;
required-opps = <&smcc_opp4>;
};
opp-7500000000 {
opp-hz = /bits/ 64 <750000000>;
required-opps = <&smcc_opp5>;
};
opp-8000000000 {
opp-hz = /bits/ 64 <800000000>;
required-opps = <&smcc_opp6>;
};
opp-8500000000 {
opp-hz = /bits/ 64 <850000000>;
required-opps = <&smcc_opp7>;
};
opp-9000000000 {
opp-hz = /bits/ 64 <900000000>;
required-opps = <&smcc_opp8>;
};
opp-9500000000 {
opp-hz = /bits/ 64 <950000000>;
required-opps = <&smcc_opp9>;
};
opp-10000000000 {
opp-hz = /bits/ 64 <1000000000>;
required-opps = <&smcc_opp10>;
};
opp-10500000000 {
opp-hz = /bits/ 64 <1050000000>;
required-opps = <&smcc_opp11>;
};
opp-11000000000 {
opp-hz = /bits/ 64 <1100000000>;
required-opps = <&smcc_opp12>;
};
opp-11500000000 {
opp-hz = /bits/ 64 <1150000000>;
required-opps = <&smcc_opp13>;
};
opp-12000000000 {
opp-hz = /bits/ 64 <1200000000>;
required-opps = <&smcc_opp14>;
};
};
cpu_smcc_opp_table: opp-table-cpu-smcc {
compatible = "operating-points-v2";
smcc_opp0: opp0 {
opp-level = <0>;
};
smcc_opp1: opp1 {
opp-level = <1>;
};
smcc_opp2: opp2 {
opp-level = <2>;
};
smcc_opp3: opp3 {
opp-level = <3>;
};
smcc_opp4: opp4 {
opp-level = <4>;
};
smcc_opp5: opp5 {
opp-level = <5>;
};
smcc_opp6: opp6 {
opp-level = <6>;
};
smcc_opp7: opp7 {
opp-level = <7>;
};
smcc_opp8: opp8 {
opp-level = <8>;
};
smcc_opp9: opp9 {
opp-level = <9>;
};
smcc_opp10: opp10 {
opp-level = <10>;
};
smcc_opp11: opp11 {
opp-level = <11>;
};
smcc_opp12: opp12 {
opp-level = <12>;
};
smcc_opp13: opp13 {
opp-level = <13>;
};
smcc_opp14: opp14 {
opp-level = <14>;
};
};
@ -431,16 +531,16 @@
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <2>;
airoha,bmt;
};
};
mmc0: mmc@1fa0e000 {
compatible = "mediatek,mt7622-mmc";
compatible = "airoha,an7581-mmc";
reg = <0x0 0x1fa0e000 0x0 0x1000>,
<0x0 0x1fa0c000 0x0 0x60>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
clocks = <&scuclk EN7581_CLK_EMMC>;
clock-names = "source"; bus-width = <4>;
max-frequency = <52000000>;
disable-wp;
cap-mmc-highspeed;
@ -587,7 +687,7 @@
status = "disabled";
fixed-link {
speed = <1000>;
speed = <10000>;
full-duplex;
pause;
};
@ -648,7 +748,7 @@
phy-mode = "internal";
fixed-link {
speed = <1000>;
speed = <10000>;
full-duplex;
pause;
};

2
target/linux/airoha/patches-6.6/002-v6.11-i2c-mt7621-Add-Airoha-EN7581-i2c-support.patch
View File

@ -16,7 +16,7 @@ Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -839,7 +839,7 @@ config I2C_MT65XX
@@ -841,7 +841,7 @@ config I2C_MT65XX
config I2C_MT7621
tristate "MT7621/MT7628 I2C Controller"

11
target/linux/airoha/patches-6.6/109-clk-en7523-Fix-wrong-BUS-clock-for-EN7581.patch → target/linux/airoha/patches-6.6/035-v6.13-clk-en7523-Fix-wrong-BUS-clock-for-EN7581.patch
View File

@ -1,12 +1,12 @@
From 6d74b9e6d3bb07f50b22b9ea047b84a83aba185c Mon Sep 17 00:00:00 2001
From 2eb75f86d52565367211c51334d15fe672633085 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 17 Oct 2024 19:26:24 +0200
Date: Sat, 16 Nov 2024 11:56:53 +0100
Subject: [PATCH] clk: en7523: Fix wrong BUS clock for EN7581
The Documentation for EN7581 had a typo and still referenced the EN7523
BUS base source frequency. This was in conflict with a different page in
the Documentration that state that the BUS runs at 300MHz (600MHz source with
divisor set to 2) and the actual watchdog that tick at half the BUS
the Documentration that state that the BUS runs at 300MHz (600MHz source
with divisor set to 2) and the actual watchdog that tick at half the BUS
clock (150MHz). This was verified with the watchdog by timing the
seconds that the system takes to reboot (due too watchdog) and by
operating on different values of the BUS divisor.
@ -18,6 +18,9 @@ This was also confirmed by Airoha.
Cc: stable@vger.kernel.org
Fixes: 66bc47326ce2 ("clk: en7523: Add EN7581 support")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20241116105710.19748-1-ansuelsmth@gmail.com
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/clk-en7523.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

35
target/linux/airoha/patches-6.6/036-v6.13-net-airoha-Fix-typo-in-REG_CDM2_FWD_CFG-configuratio.patch Normal file
View File

@ -0,0 +1,35 @@
From 30d9d8f6a2d7e44a9f91737dd409dbc87ac6f6b7 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Tue, 15 Oct 2024 09:58:09 +0200
Subject: [PATCH] net: airoha: Fix typo in REG_CDM2_FWD_CFG configuration
Fix typo in airoha_fe_init routine configuring CDM2_OAM_QSEL_MASK field
of REG_CDM2_FWD_CFG register.
This bug is not introducing any user visible problem since Frame Engine
CDM2 port is used just by the second QDMA block and we currently enable
just QDMA1 block connected to the MT7530 dsa switch via CDM1 port.
Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet
support for EN7581 SoC")
Reported-by: ChihWei Cheng <chihwei.cheng@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Message-ID: <20241015-airoha-eth-cdm2-fixes-v1-1-9dc6993286c3@kernel.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -1369,7 +1369,8 @@ static int airoha_fe_init(struct airoha_
airoha_fe_set(eth, REG_GDM_MISC_CFG,
GDM2_RDM_ACK_WAIT_PREF_MASK |
GDM2_CHN_VLD_MODE_MASK);
- airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK, 15);
+ airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK,
+ FIELD_PREP(CDM2_OAM_QSEL_MASK, 15));
/* init fragment and assemble Force Port */
/* NPU Core-3, NPU Bridge Channel-3 */

102
target/linux/airoha/patches-6.6/037-v6.14-net-airoha-Fix-error-path-in-airoha_probe.patch Normal file
View File

@ -0,0 +1,102 @@
From 0c7469ee718e1dd929f52bfb142a7f6fb68f0765 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Mon, 16 Dec 2024 18:47:33 +0100
Subject: [PATCH] net: airoha: Fix error path in airoha_probe()
Do not run napi_disable() if airoha_hw_init() fails since Tx/Rx napi
has not been started yet. In order to fix the issue, introduce
airoha_qdma_stop_napi routine and remove napi_disable in
airoha_hw_cleanup().
Fixes: 23020f049327 ("net: airoha: Introduce ethernet support for EN7581 SoC")
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20241216-airoha_probe-error-path-fix-v2-1-6b10e04e9a5c@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 33 ++++++++++++++++------
1 file changed, 25 insertions(+), 8 deletions(-)
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -2139,17 +2139,14 @@ static void airoha_hw_cleanup(struct air
if (!qdma->q_rx[i].ndesc)
continue;
- napi_disable(&qdma->q_rx[i].napi);
netif_napi_del(&qdma->q_rx[i].napi);
airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]);
if (qdma->q_rx[i].page_pool)
page_pool_destroy(qdma->q_rx[i].page_pool);
}
- for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
- napi_disable(&qdma->q_tx_irq[i].napi);
+ for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
netif_napi_del(&qdma->q_tx_irq[i].napi);
- }
for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
if (!qdma->q_tx[i].ndesc)
@@ -2174,6 +2171,21 @@ static void airoha_qdma_start_napi(struc
}
}
+static void airoha_qdma_stop_napi(struct airoha_qdma *qdma)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
+ napi_disable(&qdma->q_tx_irq[i].napi);
+
+ for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
+ if (!qdma->q_rx[i].ndesc)
+ continue;
+
+ napi_disable(&qdma->q_rx[i].napi);
+ }
+}
+
static void airoha_update_hw_stats(struct airoha_gdm_port *port)
{
struct airoha_eth *eth = port->qdma->eth;
@@ -2731,7 +2743,7 @@ static int airoha_probe(struct platform_
err = airoha_hw_init(pdev, eth);
if (err)
- goto error;
+ goto error_hw_cleanup;
for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
airoha_qdma_start_napi(&eth->qdma[i]);
@@ -2746,13 +2758,16 @@ static int airoha_probe(struct platform_
err = airoha_alloc_gdm_port(eth, np);
if (err) {
of_node_put(np);
- goto error;
+ goto error_napi_stop;
}
}
return 0;
-error:
+error_napi_stop:
+ for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
+ airoha_qdma_stop_napi(&eth->qdma[i]);
+error_hw_cleanup:
for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
airoha_hw_cleanup(&eth->qdma[i]);
@@ -2773,8 +2788,10 @@ static void airoha_remove(struct platfor
struct airoha_eth *eth = platform_get_drvdata(pdev);
int i;
- for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
+ for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
+ airoha_qdma_stop_napi(&eth->qdma[i]);
airoha_hw_cleanup(&eth->qdma[i]);
+ }
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];

27
target/linux/airoha/patches-6.6/038-01-v6.14-net-airoha-Enable-Tx-drop-capability-for-each-Tx-DMA.patch Normal file
View File

@ -0,0 +1,27 @@
From 5f795590380476f1c9b7ed0ac945c9b0269dc23a Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Fri, 3 Jan 2025 13:17:02 +0100
Subject: [PATCH 1/4] net: airoha: Enable Tx drop capability for each Tx DMA
ring
This is a preliminary patch in order to enable hw Qdisc offloading.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -1790,6 +1790,10 @@ static int airoha_qdma_init_tx_queue(str
WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val));
}
+ /* xmit ring drop default setting */
+ airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid),
+ TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK);
+
airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr);
airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head));

86
target/linux/airoha/patches-6.6/038-02-v6.14-net-airoha-Introduce-ndo_select_queue-callback.patch Normal file
View File

@ -0,0 +1,86 @@
From 2b288b81560b94958cd68bbe54673e55a1730c95 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Fri, 3 Jan 2025 13:17:03 +0100
Subject: [PATCH 2/4] net: airoha: Introduce ndo_select_queue callback
Airoha EN7581 SoC supports 32 Tx DMA rings used to feed packets to QoS
channels. Each channels supports 8 QoS queues where the user can apply
QoS scheduling policies. In a similar way, the user can configure hw
rate shaping for each QoS channel.
Introduce ndo_select_queue callback in order to select the tx queue
based on QoS channel and QoS queue. In particular, for dsa device select
QoS channel according to the dsa user port index, rely on port id
otherwise. Select QoS queue based on the skb priority.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 30 ++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -23,6 +23,8 @@
#define AIROHA_MAX_NUM_XSI_RSTS 5
#define AIROHA_MAX_MTU 2000
#define AIROHA_MAX_PACKET_SIZE 2048
+#define AIROHA_NUM_QOS_CHANNELS 4
+#define AIROHA_NUM_QOS_QUEUES 8
#define AIROHA_NUM_TX_RING 32
#define AIROHA_NUM_RX_RING 32
#define AIROHA_FE_MC_MAX_VLAN_TABLE 64
@@ -2422,21 +2424,44 @@ static void airoha_dev_get_stats64(struc
} while (u64_stats_fetch_retry(&port->stats.syncp, start));
}
+static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb,
+ struct net_device *sb_dev)
+{
+ struct airoha_gdm_port *port = netdev_priv(dev);
+ int queue, channel;
+
+ /* For dsa device select QoS channel according to the dsa user port
+ * index, rely on port id otherwise. Select QoS queue based on the
+ * skb priority.
+ */
+ channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id;
+ channel = channel % AIROHA_NUM_QOS_CHANNELS;
+ queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */
+ queue = channel * AIROHA_NUM_QOS_QUEUES + queue;
+
+ return queue < dev->num_tx_queues ? queue : 0;
+}
+
static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct skb_shared_info *sinfo = skb_shinfo(skb);
struct airoha_gdm_port *port = netdev_priv(dev);
- u32 msg0 = 0, msg1, len = skb_headlen(skb);
- int i, qid = skb_get_queue_mapping(skb);
+ u32 msg0, msg1, len = skb_headlen(skb);
struct airoha_qdma *qdma = port->qdma;
u32 nr_frags = 1 + sinfo->nr_frags;
struct netdev_queue *txq;
struct airoha_queue *q;
void *data = skb->data;
+ int i, qid;
u16 index;
u8 fport;
+ qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx);
+ msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK,
+ qid / AIROHA_NUM_QOS_QUEUES) |
+ FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK,
+ qid % AIROHA_NUM_QOS_QUEUES);
if (skb->ip_summed == CHECKSUM_PARTIAL)
msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) |
FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) |
@@ -2610,6 +2635,7 @@ static const struct net_device_ops airoh
.ndo_init = airoha_dev_init,
.ndo_open = airoha_dev_open,
.ndo_stop = airoha_dev_stop,
+ .ndo_select_queue = airoha_dev_select_queue,
.ndo_start_xmit = airoha_dev_xmit,
.ndo_get_stats64 = airoha_dev_get_stats64,
.ndo_set_mac_address = airoha_dev_set_macaddr,

292
target/linux/airoha/patches-6.6/038-03-v6.14-net-airoha-Add-sched-ETS-offload-support.patch Normal file
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@ -0,0 +1,292 @@
From 20bf7d07c956e5c7a22d3076c599cbb7a6054917 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Fri, 3 Jan 2025 13:17:04 +0100
Subject: [PATCH 3/4] net: airoha: Add sched ETS offload support
Introduce support for ETS Qdisc offload available on the Airoha EN7581
ethernet controller. In order to be effective, ETS Qdisc must configured
as leaf of a HTB Qdisc (HTB Qdisc offload will be added in the following
patch). ETS Qdisc available on EN7581 ethernet controller supports at
most 8 concurrent bands (QoS queues). We can enable an ETS Qdisc for
each available QoS channel.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 196 ++++++++++++++++++++-
1 file changed, 195 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -15,6 +15,7 @@
#include <linux/u64_stats_sync.h>
#include <net/dsa.h>
#include <net/page_pool/helpers.h>
+#include <net/pkt_cls.h>
#include <uapi/linux/ppp_defs.h>
#define AIROHA_MAX_NUM_GDM_PORTS 1
@@ -543,9 +544,24 @@
#define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
#define INGRESS_FAST_TICK_MASK GENMASK(15, 0)
+#define REG_QUEUE_CLOSE_CFG(_n) (0x00a0 + ((_n) & 0xfc))
+#define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3))
+
#define REG_TXQ_DIS_CFG_BASE(_n) ((_n) ? 0x20a0 : 0x00a0)
#define REG_TXQ_DIS_CFG(_n, _m) (REG_TXQ_DIS_CFG_BASE((_n)) + (_m) << 2)
+#define REG_CNTR_CFG(_n) (0x0400 + ((_n) << 3))
+#define CNTR_EN_MASK BIT(31)
+#define CNTR_ALL_CHAN_EN_MASK BIT(30)
+#define CNTR_ALL_QUEUE_EN_MASK BIT(29)
+#define CNTR_ALL_DSCP_RING_EN_MASK BIT(28)
+#define CNTR_SRC_MASK GENMASK(27, 24)
+#define CNTR_DSCP_RING_MASK GENMASK(20, 16)
+#define CNTR_CHAN_MASK GENMASK(7, 3)
+#define CNTR_QUEUE_MASK GENMASK(2, 0)
+
+#define REG_CNTR_VAL(_n) (0x0404 + ((_n) << 3))
+
#define REG_LMGR_INIT_CFG 0x1000
#define LMGR_INIT_START BIT(31)
#define LMGR_SRAM_MODE_MASK BIT(30)
@@ -571,9 +587,19 @@
#define TWRR_WEIGHT_SCALE_MASK BIT(31)
#define TWRR_WEIGHT_BASE_MASK BIT(3)
+#define REG_TXWRR_WEIGHT_CFG 0x1024
+#define TWRR_RW_CMD_MASK BIT(31)
+#define TWRR_RW_CMD_DONE BIT(30)
+#define TWRR_CHAN_IDX_MASK GENMASK(23, 19)
+#define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)
+#define TWRR_VALUE_MASK GENMASK(15, 0)
+
#define REG_PSE_BUF_USAGE_CFG 0x1028
#define PSE_BUF_ESTIMATE_EN_MASK BIT(29)
+#define REG_CHAN_QOS_MODE(_n) (0x1040 + ((_n) << 2))
+#define CHAN_QOS_MODE_MASK(_n) GENMASK(2 + ((_n) << 2), (_n) << 2)
+
#define REG_GLB_TRTCM_CFG 0x1080
#define GLB_TRTCM_EN_MASK BIT(31)
#define GLB_TRTCM_MODE_MASK BIT(30)
@@ -722,6 +748,17 @@ enum {
FE_PSE_PORT_DROP = 0xf,
};
+enum tx_sched_mode {
+ TC_SCH_WRR8,
+ TC_SCH_SP,
+ TC_SCH_WRR7,
+ TC_SCH_WRR6,
+ TC_SCH_WRR5,
+ TC_SCH_WRR4,
+ TC_SCH_WRR3,
+ TC_SCH_WRR2,
+};
+
struct airoha_queue_entry {
union {
void *buf;
@@ -812,6 +849,10 @@ struct airoha_gdm_port {
int id;
struct airoha_hw_stats stats;
+
+ /* qos stats counters */
+ u64 cpu_tx_packets;
+ u64 fwd_tx_packets;
};
struct airoha_eth {
@@ -1962,6 +2003,27 @@ static void airoha_qdma_init_qos(struct
FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40));
}
+static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)
+{
+ int i;
+
+ for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) {
+ /* Tx-cpu transferred count */
+ airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0);
+ airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
+ CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
+ CNTR_ALL_DSCP_RING_EN_MASK |
+ FIELD_PREP(CNTR_CHAN_MASK, i));
+ /* Tx-fwd transferred count */
+ airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0);
+ airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
+ CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
+ CNTR_ALL_DSCP_RING_EN_MASK |
+ FIELD_PREP(CNTR_SRC_MASK, 1) |
+ FIELD_PREP(CNTR_CHAN_MASK, i));
+ }
+}
+
static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
{
int i;
@@ -2012,6 +2074,7 @@ static int airoha_qdma_hw_init(struct ai
airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG,
TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN);
+ airoha_qdma_init_qos_stats(qdma);
return 0;
}
@@ -2631,6 +2694,135 @@ airoha_ethtool_get_rmon_stats(struct net
} while (u64_stats_fetch_retry(&port->stats.syncp, start));
}
+static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port,
+ int channel, enum tx_sched_mode mode,
+ const u16 *weights, u8 n_weights)
+{
+ int i;
+
+ for (i = 0; i < AIROHA_NUM_TX_RING; i++)
+ airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
+ TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i));
+
+ for (i = 0; i < n_weights; i++) {
+ u32 status;
+ int err;
+
+ airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG,
+ TWRR_RW_CMD_MASK |
+ FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) |
+ FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) |
+ FIELD_PREP(TWRR_VALUE_MASK, weights[i]));
+ err = read_poll_timeout(airoha_qdma_rr, status,
+ status & TWRR_RW_CMD_DONE,
+ USEC_PER_MSEC, 10 * USEC_PER_MSEC,
+ true, port->qdma,
+ REG_TXWRR_WEIGHT_CFG);
+ if (err)
+ return err;
+ }
+
+ airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3),
+ CHAN_QOS_MODE_MASK(channel),
+ mode << __ffs(CHAN_QOS_MODE_MASK(channel)));
+
+ return 0;
+}
+
+static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port,
+ int channel)
+{
+ static const u16 w[AIROHA_NUM_QOS_QUEUES] = {};
+
+ return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w,
+ ARRAY_SIZE(w));
+}
+
+static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port,
+ int channel,
+ struct tc_ets_qopt_offload *opt)
+{
+ struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params;
+ enum tx_sched_mode mode = TC_SCH_SP;
+ u16 w[AIROHA_NUM_QOS_QUEUES] = {};
+ int i, nstrict = 0;
+
+ if (p->bands > AIROHA_NUM_QOS_QUEUES)
+ return -EINVAL;
+
+ for (i = 0; i < p->bands; i++) {
+ if (!p->quanta[i])
+ nstrict++;
+ }
+
+ /* this configuration is not supported by the hw */
+ if (nstrict == AIROHA_NUM_QOS_QUEUES - 1)
+ return -EINVAL;
+
+ for (i = 0; i < p->bands - nstrict; i++)
+ w[i] = p->weights[nstrict + i];
+
+ if (!nstrict)
+ mode = TC_SCH_WRR8;
+ else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1)
+ mode = nstrict + 1;
+
+ return airoha_qdma_set_chan_tx_sched(port, channel, mode, w,
+ ARRAY_SIZE(w));
+}
+
+static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port,
+ int channel,
+ struct tc_ets_qopt_offload *opt)
+{
+ u64 cpu_tx_packets = airoha_qdma_rr(port->qdma,
+ REG_CNTR_VAL(channel << 1));
+ u64 fwd_tx_packets = airoha_qdma_rr(port->qdma,
+ REG_CNTR_VAL((channel << 1) + 1));
+ u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) +
+ (fwd_tx_packets - port->fwd_tx_packets);
+ _bstats_update(opt->stats.bstats, 0, tx_packets);
+
+ port->cpu_tx_packets = cpu_tx_packets;
+ port->fwd_tx_packets = fwd_tx_packets;
+
+ return 0;
+}
+
+static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port,
+ struct tc_ets_qopt_offload *opt)
+{
+ int channel = TC_H_MAJ(opt->handle) >> 16;
+
+ if (opt->parent == TC_H_ROOT)
+ return -EINVAL;
+
+ switch (opt->command) {
+ case TC_ETS_REPLACE:
+ return airoha_qdma_set_tx_ets_sched(port, channel, opt);
+ case TC_ETS_DESTROY:
+ /* PRIO is default qdisc scheduler */
+ return airoha_qdma_set_tx_prio_sched(port, channel);
+ case TC_ETS_STATS:
+ return airoha_qdma_get_tx_ets_stats(port, channel, opt);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type,
+ void *type_data)
+{
+ struct airoha_gdm_port *port = netdev_priv(dev);
+
+ switch (type) {
+ case TC_SETUP_QDISC_ETS:
+ return airoha_tc_setup_qdisc_ets(port, type_data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static const struct net_device_ops airoha_netdev_ops = {
.ndo_init = airoha_dev_init,
.ndo_open = airoha_dev_open,
@@ -2639,6 +2831,7 @@ static const struct net_device_ops airoh
.ndo_start_xmit = airoha_dev_xmit,
.ndo_get_stats64 = airoha_dev_get_stats64,
.ndo_set_mac_address = airoha_dev_set_macaddr,
+ .ndo_setup_tc = airoha_dev_tc_setup,
};
static const struct ethtool_ops airoha_ethtool_ops = {
@@ -2688,7 +2881,8 @@ static int airoha_alloc_gdm_port(struct
dev->watchdog_timeo = 5 * HZ;
dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
NETIF_F_TSO6 | NETIF_F_IPV6_CSUM |
- NETIF_F_SG | NETIF_F_TSO;
+ NETIF_F_SG | NETIF_F_TSO |
+ NETIF_F_HW_TC;
dev->features |= dev->hw_features;
dev->dev.of_node = np;
dev->irq = qdma->irq;

371
target/linux/airoha/patches-6.6/038-04-v6.14-net-airoha-Add-sched-HTB-offload-support.patch Normal file
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@ -0,0 +1,371 @@
From ef1ca9271313b4ea7b03de69576aacef1e78f381 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Fri, 3 Jan 2025 13:17:05 +0100
Subject: [PATCH 4/4] net: airoha: Add sched HTB offload support
Introduce support for HTB Qdisc offload available in the Airoha EN7581
ethernet controller. EN7581 can offload only one level of HTB leafs.
Each HTB leaf represents a QoS channel supported by EN7581 SoC.
The typical use-case is creating a HTB leaf for QoS channel to rate
limit the egress traffic and attach an ETS Qdisc to each HTB leaf in
order to enforce traffic prioritization.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 288 ++++++++++++++++++++-
1 file changed, 287 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -28,6 +28,8 @@
#define AIROHA_NUM_QOS_QUEUES 8
#define AIROHA_NUM_TX_RING 32
#define AIROHA_NUM_RX_RING 32
+#define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \
+ AIROHA_NUM_QOS_CHANNELS)
#define AIROHA_FE_MC_MAX_VLAN_TABLE 64
#define AIROHA_FE_MC_MAX_VLAN_PORT 16
#define AIROHA_NUM_TX_IRQ 2
@@ -43,6 +45,9 @@
#define PSE_RSV_PAGES 128
#define PSE_QUEUE_RSV_PAGES 64
+#define QDMA_METER_IDX(_n) ((_n) & 0xff)
+#define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3)
+
/* FE */
#define PSE_BASE 0x0100
#define CSR_IFC_BASE 0x0200
@@ -583,6 +588,17 @@
#define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
#define EGRESS_FAST_TICK_MASK GENMASK(15, 0)
+#define TRTCM_PARAM_RW_MASK BIT(31)
+#define TRTCM_PARAM_RW_DONE_MASK BIT(30)
+#define TRTCM_PARAM_TYPE_MASK GENMASK(29, 28)
+#define TRTCM_METER_GROUP_MASK GENMASK(27, 26)
+#define TRTCM_PARAM_INDEX_MASK GENMASK(23, 17)
+#define TRTCM_PARAM_RATE_TYPE_MASK BIT(16)
+
+#define REG_TRTCM_CFG_PARAM(_n) ((_n) + 0x4)
+#define REG_TRTCM_DATA_LOW(_n) ((_n) + 0x8)
+#define REG_TRTCM_DATA_HIGH(_n) ((_n) + 0xc)
+
#define REG_TXWRR_MODE_CFG 0x1020
#define TWRR_WEIGHT_SCALE_MASK BIT(31)
#define TWRR_WEIGHT_BASE_MASK BIT(3)
@@ -759,6 +775,29 @@ enum tx_sched_mode {
TC_SCH_WRR2,
};
+enum trtcm_param_type {
+ TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */
+ TRTCM_TOKEN_RATE_MODE,
+ TRTCM_BUCKETSIZE_SHIFT_MODE,
+ TRTCM_BUCKET_COUNTER_MODE,
+};
+
+enum trtcm_mode_type {
+ TRTCM_COMMIT_MODE,
+ TRTCM_PEAK_MODE,
+};
+
+enum trtcm_param {
+ TRTCM_TICK_SEL = BIT(0),
+ TRTCM_PKT_MODE = BIT(1),
+ TRTCM_METER_MODE = BIT(2),
+};
+
+#define MIN_TOKEN_SIZE 4096
+#define MAX_TOKEN_SIZE_OFFSET 17
+#define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6)
+#define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0)
+
struct airoha_queue_entry {
union {
void *buf;
@@ -850,6 +889,8 @@ struct airoha_gdm_port {
struct airoha_hw_stats stats;
+ DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
+
/* qos stats counters */
u64 cpu_tx_packets;
u64 fwd_tx_packets;
@@ -2810,6 +2851,243 @@ static int airoha_tc_setup_qdisc_ets(str
}
}
+static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel,
+ u32 addr, enum trtcm_param_type param,
+ enum trtcm_mode_type mode,
+ u32 *val_low, u32 *val_high)
+{
+ u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel);
+ u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) |
+ FIELD_PREP(TRTCM_METER_GROUP_MASK, group) |
+ FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) |
+ FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode);
+
+ airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
+ if (read_poll_timeout(airoha_qdma_rr, val,
+ val & TRTCM_PARAM_RW_DONE_MASK,
+ USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
+ qdma, REG_TRTCM_CFG_PARAM(addr)))
+ return -ETIMEDOUT;
+
+ *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
+ if (val_high)
+ *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
+
+ return 0;
+}
+
+static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel,
+ u32 addr, enum trtcm_param_type param,
+ enum trtcm_mode_type mode, u32 val)
+{
+ u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel);
+ u32 config = TRTCM_PARAM_RW_MASK |
+ FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) |
+ FIELD_PREP(TRTCM_METER_GROUP_MASK, group) |
+ FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) |
+ FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode);
+
+ airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
+ airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
+
+ return read_poll_timeout(airoha_qdma_rr, val,
+ val & TRTCM_PARAM_RW_DONE_MASK,
+ USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
+ qdma, REG_TRTCM_CFG_PARAM(addr));
+}
+
+static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel,
+ u32 addr, enum trtcm_mode_type mode,
+ bool enable, u32 enable_mask)
+{
+ u32 val;
+
+ if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
+ mode, &val, NULL))
+ return -EINVAL;
+
+ val = enable ? val | enable_mask : val & ~enable_mask;
+
+ return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
+ mode, val);
+}
+
+static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma,
+ int channel, u32 addr,
+ enum trtcm_mode_type mode,
+ u32 rate_val, u32 bucket_size)
+{
+ u32 val, config, tick, unit, rate, rate_frac;
+ int err;
+
+ if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
+ mode, &config, NULL))
+ return -EINVAL;
+
+ val = airoha_qdma_rr(qdma, addr);
+ tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val);
+ if (config & TRTCM_TICK_SEL)
+ tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val);
+ if (!tick)
+ return -EINVAL;
+
+ unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick;
+ if (!unit)
+ return -EINVAL;
+
+ rate = rate_val / unit;
+ rate_frac = rate_val % unit;
+ rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit;
+ rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) |
+ FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac);
+
+ err = airoha_qdma_set_trtcm_param(qdma, channel, addr,
+ TRTCM_TOKEN_RATE_MODE, mode, rate);
+ if (err)
+ return err;
+
+ val = max_t(u32, bucket_size, MIN_TOKEN_SIZE);
+ val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
+
+ return airoha_qdma_set_trtcm_param(qdma, channel, addr,
+ TRTCM_BUCKETSIZE_SHIFT_MODE,
+ mode, val);
+}
+
+static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port,
+ int channel, u32 rate,
+ u32 bucket_size)
+{
+ int i, err;
+
+ for (i = 0; i <= TRTCM_PEAK_MODE; i++) {
+ err = airoha_qdma_set_trtcm_config(port->qdma, channel,
+ REG_EGRESS_TRTCM_CFG, i,
+ !!rate, TRTCM_METER_MODE);
+ if (err)
+ return err;
+
+ err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel,
+ REG_EGRESS_TRTCM_CFG,
+ i, rate, bucket_size);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port,
+ struct tc_htb_qopt_offload *opt)
+{
+ u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
+ u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */
+ struct net_device *dev = port->dev;
+ int num_tx_queues = dev->real_num_tx_queues;
+ int err;
+
+ if (opt->parent_classid != TC_HTB_CLASSID_ROOT) {
+ NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid");
+ return -EINVAL;
+ }
+
+ err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum);
+ if (err) {
+ NL_SET_ERR_MSG_MOD(opt->extack,
+ "failed configuring htb offload");
+ return err;
+ }
+
+ if (opt->command == TC_HTB_NODE_MODIFY)
+ return 0;
+
+ err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1);
+ if (err) {
+ airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum);
+ NL_SET_ERR_MSG_MOD(opt->extack,
+ "failed setting real_num_tx_queues");
+ return err;
+ }
+
+ set_bit(channel, port->qos_sq_bmap);
+ opt->qid = AIROHA_NUM_TX_RING + channel;
+
+ return 0;
+}
+
+static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue)
+{
+ struct net_device *dev = port->dev;
+
+ netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1);
+ airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0);
+ clear_bit(queue, port->qos_sq_bmap);
+}
+
+static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port,
+ struct tc_htb_qopt_offload *opt)
+{
+ u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
+
+ if (!test_bit(channel, port->qos_sq_bmap)) {
+ NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
+ return -EINVAL;
+ }
+
+ airoha_tc_remove_htb_queue(port, channel);
+
+ return 0;
+}
+
+static int airoha_tc_htb_destroy(struct airoha_gdm_port *port)
+{
+ int q;
+
+ for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS)
+ airoha_tc_remove_htb_queue(port, q);
+
+ return 0;
+}
+
+static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port,
+ struct tc_htb_qopt_offload *opt)
+{
+ u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
+
+ if (!test_bit(channel, port->qos_sq_bmap)) {
+ NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
+ return -EINVAL;
+ }
+
+ opt->qid = channel;
+
+ return 0;
+}
+
+static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port,
+ struct tc_htb_qopt_offload *opt)
+{
+ switch (opt->command) {
+ case TC_HTB_CREATE:
+ break;
+ case TC_HTB_DESTROY:
+ return airoha_tc_htb_destroy(port);
+ case TC_HTB_NODE_MODIFY:
+ case TC_HTB_LEAF_ALLOC_QUEUE:
+ return airoha_tc_htb_alloc_leaf_queue(port, opt);
+ case TC_HTB_LEAF_DEL:
+ case TC_HTB_LEAF_DEL_LAST:
+ case TC_HTB_LEAF_DEL_LAST_FORCE:
+ return airoha_tc_htb_delete_leaf_queue(port, opt);
+ case TC_HTB_LEAF_QUERY_QUEUE:
+ return airoha_tc_get_htb_get_leaf_queue(port, opt);
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type,
void *type_data)
{
@@ -2818,6 +3096,8 @@ static int airoha_dev_tc_setup(struct ne
switch (type) {
case TC_SETUP_QDISC_ETS:
return airoha_tc_setup_qdisc_ets(port, type_data);
+ case TC_SETUP_QDISC_HTB:
+ return airoha_tc_setup_qdisc_htb(port, type_data);
default:
return -EOPNOTSUPP;
}
@@ -2868,7 +3148,8 @@ static int airoha_alloc_gdm_port(struct
}
dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port),
- AIROHA_NUM_TX_RING, AIROHA_NUM_RX_RING);
+ AIROHA_NUM_NETDEV_TX_RINGS,
+ AIROHA_NUM_RX_RING);
if (!dev) {
dev_err(eth->dev, "alloc_etherdev failed\n");
return -ENOMEM;
@@ -2888,6 +3169,11 @@ static int airoha_alloc_gdm_port(struct
dev->irq = qdma->irq;
SET_NETDEV_DEV(dev, eth->dev);
+ /* reserve hw queues for HTB offloading */
+ err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING);
+ if (err)
+ return err;
+
err = of_get_ethdev_address(np, dev);
if (err) {
if (err == -EPROBE_DEFER)

201
target/linux/airoha/patches-6.6/100-01-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch Normal file
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@ -0,0 +1,201 @@
From 76e4e6ce9aaae897f80e375345bf0095e1b09ff2 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Sat, 4 Jan 2025 19:03:09 +0100
Subject: [PATCH v9 1/2] pmdomain: airoha: Add Airoha CPU PM Domain support
Add Airoha CPU PM Domain support to control frequency and power of CPU
present on Airoha EN7581 SoC.
Frequency and power can be controlled with the use of the SMC command by
passing the performance state. The driver also expose a read-only clock
that expose the current CPU frequency with SMC command.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v9:
- Fix compile error targetting wrong branch (remove_new change)
Changes v8:
- Add this patch
- Use SMC invoke instead of 1.2
drivers/pmdomain/mediatek/Kconfig | 11 ++
drivers/pmdomain/mediatek/Makefile | 1 +
.../pmdomain/mediatek/airoha-cpu-pmdomain.c | 144 ++++++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -72,6 +72,17 @@ config MTK_SCPSYS_PM_DOMAINS
Control Processor System (SCPSYS) has several power management related
tasks in the system.
+config AIROHA_CPU_PM_DOMAIN
+ tristate "Airoha CPU power domain"
+ default ARCH_AIROHA
+ depends on PM
+ select PM_GENERIC_DOMAINS
+ help
+ Say y here to enable CPU power domain support for Airoha SoC.
+
+ CPU frequency and power is controlled by ATF with SMC command to
+ set performance states.
+
config MTK_MMSYS
tristate "MediaTek MMSYS Support"
default ARCH_MEDIATEK
--- a/drivers/pmdomain/mediatek/Makefile
+++ b/drivers/pmdomain/mediatek/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
+obj-$(CONFIG_AIROHA_CPU_PM_DOMAIN) += airoha-cpu-pmdomain.o
--- /dev/null
+++ b/drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/slab.h>
+
+#define AIROHA_SIP_AVS_HANDLE 0x82000301
+#define AIROHA_AVS_OP_BASE 0xddddddd0
+#define AIROHA_AVS_OP_MASK GENMASK(1, 0)
+#define AIROHA_AVS_OP_FREQ_DYN_ADJ (AIROHA_AVS_OP_BASE | \
+ FIELD_PREP(AIROHA_AVS_OP_MASK, 0x1))
+#define AIROHA_AVS_OP_GET_FREQ (AIROHA_AVS_OP_BASE | \
+ FIELD_PREP(AIROHA_AVS_OP_MASK, 0x2))
+
+struct airoha_cpu_pmdomain_priv {
+ struct clk_hw hw;
+ struct generic_pm_domain pd;
+};
+
+static long airoha_cpu_pmdomain_clk_round(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return rate;
+}
+
+static unsigned long airoha_cpu_pmdomain_clk_get(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(AIROHA_SIP_AVS_HANDLE, AIROHA_AVS_OP_GET_FREQ,
+ 0, 0, 0, 0, 0, 0, &res);
+
+ /* SMCCC returns freq in MHz */
+ return (int)(res.a0 * 1000 * 1000);
+}
+
+/* Airoha CPU clk SMCC is always enabled */
+static int airoha_cpu_pmdomain_clk_is_enabled(struct clk_hw *hw)
+{
+ return true;
+}
+
+static const struct clk_ops airoha_cpu_pmdomain_clk_ops = {
+ .recalc_rate = airoha_cpu_pmdomain_clk_get,
+ .is_enabled = airoha_cpu_pmdomain_clk_is_enabled,
+ .round_rate = airoha_cpu_pmdomain_clk_round,
+};
+
+static int airoha_cpu_pmdomain_set_performance_state(struct generic_pm_domain *domain,
+ unsigned int state)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(AIROHA_SIP_AVS_HANDLE, AIROHA_AVS_OP_FREQ_DYN_ADJ,
+ 0, state, 0, 0, 0, 0, &res);
+
+ /* SMC signal correct apply by unsetting BIT 0 */
+ return res.a0 & BIT(0) ? -EINVAL : 0;
+}
+
+static int airoha_cpu_pmdomain_probe(struct platform_device *pdev)
+{
+ struct airoha_cpu_pmdomain_priv *priv;
+ struct device *dev = &pdev->dev;
+ struct clk_init_data init = { };
+ struct generic_pm_domain *pd;
+ struct clk_hw *hw;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ /* Init and register a get-only clk for Cpufreq */
+ init.name = "cpu";
+ init.ops = &airoha_cpu_pmdomain_clk_ops;
+ /* Clock with no set_rate, can't cache */
+ init.flags = CLK_GET_RATE_NOCACHE;
+
+ hw = &priv->hw;
+ hw->init = &init;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ return ret;
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+ if (ret)
+ return ret;
+
+ /* Init and register a PD for CPU */
+ pd = &priv->pd;
+ pd->name = "cpu_pd";
+ pd->flags = GENPD_FLAG_ALWAYS_ON;
+ pd->set_performance_state = airoha_cpu_pmdomain_set_performance_state;
+
+ ret = pm_genpd_init(pd, NULL, false);
+ if (ret)
+ return ret;
+
+ ret = of_genpd_add_provider_simple(dev->of_node, pd);
+ if (ret)
+ goto err_add_provider;
+
+ platform_set_drvdata(pdev, priv);
+
+ return 0;
+
+err_add_provider:
+ pm_genpd_remove(pd);
+
+ return ret;
+}
+
+static void airoha_cpu_pmdomain_remove(struct platform_device *pdev)
+{
+ struct airoha_cpu_pmdomain_priv *priv = platform_get_drvdata(pdev);
+
+ of_genpd_del_provider(pdev->dev.of_node);
+ pm_genpd_remove(&priv->pd);
+}
+
+static const struct of_device_id airoha_cpu_pmdomain_of_match[] = {
+ { .compatible = "airoha,en7581-cpufreq" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, airoha_cpu_pmdomain_of_match);
+
+static struct platform_driver airoha_cpu_pmdomain_driver = {
+ .probe = airoha_cpu_pmdomain_probe,
+ .remove_new = airoha_cpu_pmdomain_remove,
+ .driver = {
+ .name = "airoha-cpu-pmdomain",
+ .of_match_table = airoha_cpu_pmdomain_of_match,
+ },
+};
+module_platform_driver(airoha_cpu_pmdomain_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("CPU PM domain driver for Airoha SoCs");
+MODULE_LICENSE("GPL");

253
target/linux/airoha/patches-6.6/100-02-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch Normal file
View File

@ -0,0 +1,253 @@
From fa27cb99b297a1a9c0a5824afe5a670e424fff61 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 16 Oct 2024 18:00:57 +0200
Subject: [PATCH v9 2/2] cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU
frequency scaling with SMC APIs and register a generic "cpufreq-dt"
device.
All CPU share the same frequency and can't be controlled independently.
CPU frequency is controlled by the attached PM domain.
Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq
driver is needed with OPP v2 nodes declared in DTS.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v9:
- Fix compile error targetting wrong branch (remove_new change and new PM OPs)
Changes v8:
- Split in dedicated PM domain driver
Changes v7:
- No changes
Changes v6:
- Improve Kconfig depends logic
- Select PM (PM_GENERIC_DOMAINS depends on it)
- Drop (int) cast for
Changes v5:
- Rename cpu_pd to perf for power domain name
- Use remove instead of remove_new
Changes v4:
- Rework to clk-only + PM set_performance_state implementation
Changes v3:
- Adapt to new cpufreq-dt APIs
- Register cpufreq-dt instead of custom freq driver
Changes v2:
- Fix kernel bot error with missing slab.h and bitfield.h header
- Limit COMPILE_TEST to ARM64 due to smcc 1.2
drivers/cpufreq/Kconfig.arm | 8 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/airoha-cpufreq.c | 152 +++++++++++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +
4 files changed, 163 insertions(+)
create mode 100644 drivers/cpufreq/airoha-cpufreq.c
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -41,6 +41,14 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVME
To compile this driver as a module, choose M here: the
module will be called sun50i-cpufreq-nvmem.
+config ARM_AIROHA_SOC_CPUFREQ
+ tristate "Airoha EN7581 SoC CPUFreq support"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ select PM_OPP
+ default ARCH_AIROHA
+ help
+ This adds the CPUFreq driver for Airoha EN7581 SoCs.
+
config ARM_APPLE_SOC_CPUFREQ
tristate "Apple Silicon SoC CPUFreq support"
depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY) +
##################################################################################
# ARM SoC drivers
+obj-$(CONFIG_ARM_AIROHA_SOC_CPUFREQ) += airoha-cpufreq.o
obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ) += apple-soc-cpufreq.o
obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ) += armada-8k-cpufreq.o
--- /dev/null
+++ b/drivers/cpufreq/airoha-cpufreq.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitfield.h>
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#include "cpufreq-dt.h"
+
+struct airoha_cpufreq_priv {
+ int opp_token;
+ struct device **virt_devs;
+ struct platform_device *cpufreq_dt;
+};
+
+static struct platform_device *cpufreq_pdev;
+
+/* NOP function to disable OPP from setting clock */
+static int airoha_cpufreq_config_clks_nop(struct device *dev,
+ struct opp_table *opp_table,
+ struct dev_pm_opp *old_opp,
+ struct dev_pm_opp *opp,
+ void *data, bool scaling_down)
+{
+ return 0;
+}
+
+static const char * const airoha_cpufreq_clk_names[] = { "cpu", NULL };
+static const char * const airoha_cpufreq_genpd_names[] = { "cpu_pd", NULL };
+
+static int airoha_cpufreq_probe(struct platform_device *pdev)
+{
+ struct dev_pm_opp_config config = { };
+ struct platform_device *cpufreq_dt;
+ struct airoha_cpufreq_priv *priv;
+ struct device *dev = &pdev->dev;
+ struct device **virt_devs = NULL;
+ struct device *cpu_dev;
+ int ret;
+
+ /* CPUs refer to the same OPP table */
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev)
+ return -ENODEV;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ config.clk_names = airoha_cpufreq_clk_names;
+ config.config_clks = airoha_cpufreq_config_clks_nop;
+ config.genpd_names = airoha_cpufreq_genpd_names;
+ config.virt_devs = &virt_devs;
+
+ priv->opp_token = dev_pm_opp_set_config(cpu_dev, &config);
+ if (priv->opp_token < 0)
+ return dev_err_probe(dev, priv->opp_token, "Failed to set OPP config\n");
+
+ /* Set Attached PM for OPP ACTIVE */
+ if (virt_devs) {
+ const char * const *name = airoha_cpufreq_genpd_names;
+ int i, j;
+
+ for (i = 0; *name; i++, name++) {
+ ret = pm_runtime_resume_and_get(virt_devs[i]);
+ if (ret) {
+ dev_err(cpu_dev, "failed to resume %s: %d\n",
+ *name, ret);
+
+ /* Rollback previous PM runtime calls */
+ name = config.genpd_names;
+ for (j = 0; *name && j < i; j++, name++)
+ pm_runtime_put(virt_devs[j]);
+
+ goto err_register_cpufreq;
+ }
+ }
+ priv->virt_devs = virt_devs;
+ }
+
+ cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
+ ret = PTR_ERR_OR_ZERO(cpufreq_dt);
+ if (ret) {
+ dev_err(dev, "failed to create cpufreq-dt device: %d\n", ret);
+ goto err_register_cpufreq;
+ }
+
+ priv->cpufreq_dt = cpufreq_dt;
+ platform_set_drvdata(pdev, priv);
+
+ return 0;
+
+err_register_cpufreq:
+ dev_pm_opp_clear_config(priv->opp_token);
+
+ return ret;
+}
+
+static void airoha_cpufreq_remove(struct platform_device *pdev)
+{
+ struct airoha_cpufreq_priv *priv = platform_get_drvdata(pdev);
+ const char * const *name = airoha_cpufreq_genpd_names;
+ int i;
+
+ platform_device_unregister(priv->cpufreq_dt);
+
+ dev_pm_opp_clear_config(priv->opp_token);
+
+ for (i = 0; *name; i++, name++)
+ pm_runtime_put(priv->virt_devs[i]);
+}
+
+static struct platform_driver airoha_cpufreq_driver = {
+ .probe = airoha_cpufreq_probe,
+ .remove_new = airoha_cpufreq_remove,
+ .driver = {
+ .name = "airoha-cpufreq",
+ },
+};
+
+static const struct of_device_id airoha_cpufreq_match_list[] __initconst = {
+ { .compatible = "airoha,en7581" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, airoha_cpufreq_match_list);
+
+static int __init airoha_cpufreq_init(void)
+{
+ struct device_node *np = of_find_node_by_path("/");
+ const struct of_device_id *match;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ match = of_match_node(airoha_cpufreq_match_list, np);
+ of_node_put(np);
+ if (!match)
+ return -ENODEV;
+
+ ret = platform_driver_register(&airoha_cpufreq_driver);
+ if (unlikely(ret < 0))
+ return ret;
+
+ cpufreq_pdev = platform_device_register_data(NULL, "airoha-cpufreq",
+ -1, match, sizeof(*match));
+ ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
+ if (ret)
+ platform_driver_unregister(&airoha_cpufreq_driver);
+
+ return ret;
+}
+module_init(airoha_cpufreq_init);
+
+static void __exit airoha_cpufreq_exit(void)
+{
+ platform_device_unregister(cpufreq_pdev);
+ platform_driver_unregister(&airoha_cpufreq_driver);
+}
+module_exit(airoha_cpufreq_exit);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("CPUfreq driver for Airoha SoCs");
+MODULE_LICENSE("GPL");
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -103,6 +103,8 @@ static const struct of_device_id allowli
* platforms using "operating-points-v2" property.
*/
static const struct of_device_id blocklist[] __initconst = {
+ { .compatible = "airoha,en7581", },
+
{ .compatible = "allwinner,sun50i-h6", },
{ .compatible = "apple,arm-platform", },

247
target/linux/airoha/patches-6.6/100-cpufreq-airoha-Add-EN7581-Cpufreq-SMC-driver.patch
View File

@ -1,247 +0,0 @@
From 5296da64f77ef6c809b715cdecf308977a08acb9 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 16 Oct 2024 18:00:57 +0200
Subject: [PATCH] cpufreq: airoha: Add EN7581 Cpufreq SMC driver
Add simple Cpufreq driver for Airoha EN7581 SoC that control CPU
frequency scaling with SMC APIs.
All CPU share the same frequency and can't be controlled independently.
Current shared CPU frequency is returned by the related SMC command.
Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq
driver is needed with OPP v2 nodes declared in DTS.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/cpufreq/Kconfig.arm | 8 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/airoha-cpufreq.c | 183 +++++++++++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +
4 files changed, 194 insertions(+)
create mode 100644 drivers/cpufreq/airoha-cpufreq.c
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -41,6 +41,14 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVME
To compile this driver as a module, choose M here: the
module will be called sun50i-cpufreq-nvmem.
+config ARM_AIROHA_SOC_CPUFREQ
+ tristate "Airoha EN7581 SoC CPUFreq support"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ select PM_OPP
+ default ARCH_AIROHA
+ help
+ This adds the CPUFreq driver for Airoha EN7581 SoCs.
+
config ARM_APPLE_SOC_CPUFREQ
tristate "Apple Silicon SoC CPUFreq support"
depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY) +
##################################################################################
# ARM SoC drivers
+obj-$(CONFIG_ARM_AIROHA_SOC_CPUFREQ) += airoha-cpufreq.o
obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ) += apple-soc-cpufreq.o
obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ) += armada-8k-cpufreq.o
--- /dev/null
+++ b/drivers/cpufreq/airoha-cpufreq.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/arm-smccc.h>
+
+#define AIROHA_SIP_AVS_HANDLE 0x82000301
+#define AIROHA_AVS_OP_BASE 0xddddddd0
+#define AIROHA_AVS_OP_MASK GENMASK(1, 0)
+#define AIROHA_AVS_OP_FREQ_DYN_ADJ (AIROHA_AVS_OP_BASE | \
+ FIELD_PREP(AIROHA_AVS_OP_MASK, 0x1))
+#define AIROHA_AVS_OP_GET_FREQ (AIROHA_AVS_OP_BASE | \
+ FIELD_PREP(AIROHA_AVS_OP_MASK, 0x2))
+
+struct airoha_cpufreq_priv {
+ struct list_head list;
+
+ cpumask_var_t cpus;
+ struct device *cpu_dev;
+ struct cpufreq_frequency_table *freq_table;
+};
+
+static LIST_HEAD(priv_list);
+
+static unsigned int airoha_cpufreq_get(unsigned int cpu)
+{
+ const struct arm_smccc_1_2_regs args = {
+ .a0 = AIROHA_SIP_AVS_HANDLE,
+ .a1 = AIROHA_AVS_OP_GET_FREQ,
+ };
+ struct arm_smccc_1_2_regs res;
+
+ arm_smccc_1_2_smc(&args, &res);
+
+ return (int)(res.a0 * 1000);
+}
+
+static int airoha_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index)
+{
+ const struct arm_smccc_1_2_regs args = {
+ .a0 = AIROHA_SIP_AVS_HANDLE,
+ .a1 = AIROHA_AVS_OP_FREQ_DYN_ADJ,
+ .a3 = index,
+ };
+ struct arm_smccc_1_2_regs res;
+
+ arm_smccc_1_2_smc(&args, &res);
+
+ /* SMC signal correct apply by unsetting BIT 0 */
+ return res.a0 & BIT(0) ? -EINVAL : 0;
+}
+
+static struct airoha_cpufreq_priv *airoha_cpufreq_find_data(int cpu)
+{
+ struct airoha_cpufreq_priv *priv;
+
+ list_for_each_entry(priv, &priv_list, list) {
+ if (cpumask_test_cpu(cpu, priv->cpus))
+ return priv;
+ }
+
+ return NULL;
+}
+
+static int airoha_cpufreq_init(struct cpufreq_policy *policy)
+{
+ struct airoha_cpufreq_priv *priv;
+ struct device *cpu_dev;
+
+ priv = airoha_cpufreq_find_data(policy->cpu);
+ if (!priv)
+ return -ENODEV;
+
+ cpu_dev = priv->cpu_dev;
+ cpumask_copy(policy->cpus, priv->cpus);
+ policy->driver_data = priv;
+ policy->freq_table = priv->freq_table;
+
+ return 0;
+}
+
+static struct cpufreq_driver airoha_cpufreq_driver = {
+ .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
+ CPUFREQ_IS_COOLING_DEV,
+ .verify = cpufreq_generic_frequency_table_verify,
+ .target_index = airoha_cpufreq_set_target,
+ .get = airoha_cpufreq_get,
+ .init = airoha_cpufreq_init,
+ .attr = cpufreq_generic_attr,
+ .name = "airoha-cpufreq",
+};
+
+static int airoha_cpufreq_driver_init_cpu(int cpu)
+{
+ struct airoha_cpufreq_priv *priv;
+ struct device *cpu_dev;
+ int ret;
+
+ cpu_dev = get_cpu_device(cpu);
+ if (!cpu_dev)
+ return -EPROBE_DEFER;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ if (!zalloc_cpumask_var(&priv->cpus, GFP_KERNEL))
+ return -ENOMEM;
+
+ cpumask_set_cpu(cpu, priv->cpus);
+ priv->cpu_dev = cpu_dev;
+
+ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, priv->cpus);
+ if (ret)
+ goto err;
+
+ ret = dev_pm_opp_of_cpumask_add_table(priv->cpus);
+ if (ret)
+ goto err;
+
+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &priv->freq_table);
+ if (ret)
+ goto err;
+
+ list_add(&priv->list, &priv_list);
+
+ return 0;
+
+err:
+ dev_pm_opp_of_cpumask_remove_table(priv->cpus);
+ free_cpumask_var(priv->cpus);
+
+ return ret;
+}
+
+static void airoha_cpufreq_release(void)
+{
+ struct airoha_cpufreq_priv *priv, *tmp;
+
+ list_for_each_entry_safe(priv, tmp, &priv_list, list) {
+ dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &priv->freq_table);
+ dev_pm_opp_of_cpumask_remove_table(priv->cpus);
+ free_cpumask_var(priv->cpus);
+ list_del(&priv->list);
+ kfree(priv);
+ }
+}
+
+static int __init airoha_cpufreq_driver_probe(void)
+{
+ int cpu, ret;
+
+ if (!of_machine_is_compatible("airoha,en7581"))
+ return -ENODEV;
+
+ for_each_possible_cpu(cpu) {
+ ret = airoha_cpufreq_driver_init_cpu(cpu);
+ if (ret)
+ goto err;
+ }
+
+ ret = cpufreq_register_driver(&airoha_cpufreq_driver);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ airoha_cpufreq_release();
+ return ret;
+}
+module_init(airoha_cpufreq_driver_probe);
+
+static void __exit airoha_cpufreq_driver_remove(void)
+{
+ cpufreq_unregister_driver(&airoha_cpufreq_driver);
+ airoha_cpufreq_release();
+}
+module_exit(airoha_cpufreq_driver_remove);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("CPUfreq driver for Airoha SoCs");
+MODULE_LICENSE("GPL");
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -103,6 +103,8 @@ static const struct of_device_id allowli
* platforms using "operating-points-v2" property.
*/
static const struct of_device_id blocklist[] __initconst = {
+ { .compatible = "airoha,en7581", },
+
{ .compatible = "allwinner,sun50i-h6", },
{ .compatible = "apple,arm-platform", },

82
target/linux/airoha/patches-6.6/110-01-clk-en7523-Rework-clock-handling-for-different-clock.patch Normal file
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@ -0,0 +1,82 @@
From 04cd09990fdc3106d9fc4c47dda100e521d62a43 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 18 Dec 2024 10:03:45 +0100
Subject: [PATCH 1/4] clk: en7523: Rework clock handling for different clock
numbers
Airoha EN7581 SoC have additional clock compared to EN7523 but current
driver permits to only support up to EN7523 clock numbers.
To handle this, rework the clock handling and permit to declare the
clocks number in match_data and alloca clk_data based on the compatible
match_data.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -75,6 +75,7 @@ struct en_rst_data {
};
struct en_clk_soc_data {
+ u32 num_clocks;
const struct clk_ops pcie_ops;
int (*hw_init)(struct platform_device *pdev,
struct clk_hw_onecell_data *clk_data);
@@ -525,8 +526,6 @@ static void en7523_register_clocks(struc
hw = en7523_register_pcie_clk(dev, np_base);
clk_data->hws[EN7523_CLK_PCIE] = hw;
-
- clk_data->num = EN7523_NUM_CLOCKS;
}
static int en7523_clk_hw_init(struct platform_device *pdev,
@@ -587,8 +586,6 @@ static void en7581_register_clocks(struc
hw = en7523_register_pcie_clk(dev, base);
clk_data->hws[EN7523_CLK_PCIE] = hw;
-
- clk_data->num = EN7523_NUM_CLOCKS;
}
static int en7523_reset_update(struct reset_controller_dev *rcdev,
@@ -702,21 +699,24 @@ static int en7523_clk_probe(struct platf
struct clk_hw_onecell_data *clk_data;
int r;
+ soc_data = device_get_match_data(&pdev->dev);
+
clk_data = devm_kzalloc(&pdev->dev,
- struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
+ struct_size(clk_data, hws, soc_data->num_clocks),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
- soc_data = device_get_match_data(&pdev->dev);
r = soc_data->hw_init(pdev, clk_data);
if (r)
return r;
+ clk_data->num = soc_data->num_clocks;
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct en_clk_soc_data en7523_data = {
+ .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
.pcie_ops = {
.is_enabled = en7523_pci_is_enabled,
.prepare = en7523_pci_prepare,
@@ -726,6 +726,8 @@ static const struct en_clk_soc_data en75
};
static const struct en_clk_soc_data en7581_data = {
+ /* We increment num_clocks by 1 to account for additional PCIe clock */
+ .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
.pcie_ops = {
.is_enabled = en7581_pci_is_enabled,
.enable = en7581_pci_enable,

23
target/linux/airoha/patches-6.6/110-02-dt-bindings-clock-drop-NUM_CLOCKS-define-for-EN7581.patch Normal file
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@ -0,0 +1,23 @@
From 8fc9b68ee448d0e687d4dc52ec95bf367eb04caa Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 19 Dec 2024 13:13:37 +0100
Subject: [PATCH 2/4] dt-bindings: clock: drop NUM_CLOCKS define for EN7581
Drop NUM_CLOCKS define for EN7581 include. This is not a binding and
should not be placed here. Value is derived internally in the user
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
include/dt-bindings/clock/en7523-clk.h | 2 --
1 file changed, 2 deletions(-)
--- a/include/dt-bindings/clock/en7523-clk.h
+++ b/include/dt-bindings/clock/en7523-clk.h
@@ -12,6 +12,4 @@
#define EN7523_CLK_CRYPTO 6
#define EN7523_CLK_PCIE 7
-#define EN7523_NUM_CLOCKS 8
-
#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */

23
target/linux/airoha/patches-6.6/110-03-dt-bindings-clock-add-ID-for-eMMC-for-EN7581.patch Normal file
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@ -0,0 +1,23 @@
From 238436f998c551688695d26ecdcd2ea4d51190b1 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 11 Dec 2024 12:22:37 +0100
Subject: [PATCH 3/4] dt-bindings: clock: add ID for eMMC for EN7581
Add ID for eMMC for EN7581. This is to control clock selection of eMMC
between 200MHz and 150MHz.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
include/dt-bindings/clock/en7523-clk.h | 2 ++
1 file changed, 2 insertions(+)
--- a/include/dt-bindings/clock/en7523-clk.h
+++ b/include/dt-bindings/clock/en7523-clk.h
@@ -12,4 +12,6 @@
#define EN7523_CLK_CRYPTO 6
#define EN7523_CLK_PCIE 7
+#define EN7581_CLK_EMMC 8
+
#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */

39
target/linux/airoha/patches-6.6/110-04-clk-en7523-Add-clock-for-eMMC-for-EN7581.patch Normal file
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@ -0,0 +1,39 @@
From 4fc22765b3888cf6575015b904718bfd36d1f49c Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 11 Dec 2024 12:22:38 +0100
Subject: [PATCH 4/4] clk: en7523: Add clock for eMMC for EN7581
Add clock for eMMC for EN7581. This is used to give info of the current
eMMC source clock and to switch it from 200MHz or 150MHz.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -91,6 +91,7 @@ static const u32 emi7581_base[] = { 5400
static const u32 bus7581_base[] = { 600000000, 540000000 };
static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
static const u32 crypto_base[] = { 540000000, 480000000 };
+static const u32 emmc7581_base[] = { 200000000, 150000000 };
static const struct en_clk_desc en7523_base_clks[] = {
{
@@ -281,6 +282,15 @@ static const struct en_clk_desc en7581_b
.base_shift = 0,
.base_values = crypto_base,
.n_base_values = ARRAY_SIZE(crypto_base),
+ }, {
+ .id = EN7581_CLK_EMMC,
+ .name = "emmc",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+ .base_bits = 1,
+ .base_shift = 12,
+ .base_values = emmc7581_base,
+ .n_base_values = ARRAY_SIZE(emmc7581_base),
}
};

138
target/linux/airoha/patches-6.6/111-mmc-mtk-sd-add-support-for-AN7581-MMC-Host.patch Normal file
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@ -0,0 +1,138 @@
From f38f16925e1aa7cc71f63d3d52997b1c98cd7781 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 11 Dec 2024 11:27:10 +0100
Subject: [PATCH 4/4] mmc: mtk-sd: add support for AN7581 MMC Host
Add support for AN7581 MMC Host. The MMC Host controller is based on
mt7622 with the difference of not having regulator supply and state_uhs
pins and hclk clock.
Some minor fixes are applied to check if the state_uhs pins are defined
and make hclk optional for the new airoha compatible.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/mmc/host/mtk-sd.c | 55 ++++++++++++++++++++++++++++++++-------
1 file changed, 46 insertions(+), 9 deletions(-)
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -615,6 +615,19 @@ static const struct mtk_mmc_compatible m
.stop_clk_fix = true,
};
+static const struct mtk_mmc_compatible an7581_compat = {
+ .clk_div_bits = 12,
+ .recheck_sdio_irq = true,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+ .enhance_rx = true,
+ .support_64g = false,
+};
+
static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
@@ -627,7 +640,7 @@ static const struct of_device_id msdc_of
{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
-
+ { .compatible = "airoha,an7581-mmc", .data = &an7581_compat},
{}
};
MODULE_DEVICE_TABLE(of, msdc_of_ids);
@@ -1479,6 +1492,10 @@ static int msdc_ops_switch_volt(struct m
struct msdc_host *host = mmc_priv(mmc);
int ret;
+ /* Skip setting supply if not supported */
+ if (!mmc->supply.vqmmc)
+ return 0;
+
if (!IS_ERR(mmc->supply.vqmmc)) {
if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
@@ -1578,7 +1595,9 @@ static void msdc_enable_sdio_irq(struct
dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
}
- pinctrl_select_state(host->pinctrl, host->pins_uhs);
+ /* Skip setting uhs pins if not supported */
+ if (host->pins_uhs)
+ pinctrl_select_state(host->pinctrl, host->pins_uhs);
} else {
dev_pm_clear_wake_irq(host->dev);
}
@@ -1886,6 +1905,10 @@ static void msdc_ops_set_ios(struct mmc_
msdc_set_buswidth(host, ios->bus_width);
+ /* Skip regulator if not supported */
+ if (!mmc->supply.vmmc)
+ goto skip_regulator;
+
/* Suspend/Resume will do power off/on */
switch (ios->power_mode) {
case MMC_POWER_UP:
@@ -1921,6 +1944,7 @@ static void msdc_ops_set_ios(struct mmc_
break;
}
+skip_regulator:
if (host->mclk != ios->clock || host->timing != ios->timing)
msdc_set_mclk(host, ios->timing, ios->clock);
}
@@ -2617,9 +2641,12 @@ static int msdc_of_clock_parse(struct pl
if (IS_ERR(host->src_clk))
return PTR_ERR(host->src_clk);
- host->h_clk = devm_clk_get(&pdev->dev, "hclk");
- if (IS_ERR(host->h_clk))
- return PTR_ERR(host->h_clk);
+ /* AN7581 SoC doesn't have hclk */
+ if (!device_is_compatible(&pdev->dev, "airoha,an7581-mmc")) {
+ host->h_clk = devm_clk_get(&pdev->dev, "hclk");
+ if (IS_ERR(host->h_clk))
+ return PTR_ERR(host->h_clk);
+ }
host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
if (IS_ERR(host->bus_clk))
@@ -2740,11 +2767,14 @@ static int msdc_drv_probe(struct platfor
goto host_free;
}
- host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
- if (IS_ERR(host->pins_uhs)) {
- ret = PTR_ERR(host->pins_uhs);
- dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
- goto host_free;
+ /* AN7581 doesn't have state_uhs pins */
+ if (!device_is_compatible(&pdev->dev, "airoha,an7581-mmc")) {
+ host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
+ if (IS_ERR(host->pins_uhs)) {
+ ret = PTR_ERR(host->pins_uhs);
+ dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
+ goto host_free;
+ }
}
/* Support for SDIO eint irq ? */
@@ -2825,6 +2855,12 @@ static int msdc_drv_probe(struct platfor
dev_err(&pdev->dev, "Cannot ungate clocks!\n");
goto release_mem;
}
+
+ /* AN7581 without regulator require tune to OCR values */
+ if (device_is_compatible(&pdev->dev, "airoha,an7581-mmc") &&
+ !mmc->ocr_avail)
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
msdc_init_hw(host);
if (mmc->caps2 & MMC_CAP2_CQE) {

83
target/linux/airoha/patches-6.6/112-PCI-mediatek-gen3-configure-PBUS_CSR-registers-for-E.patch Normal file
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@ -0,0 +1,83 @@
From 2285d3b428c7d8f1c4fda2fb995e7e46a05350e0 Mon Sep 17 00:00:00 2001
Message-ID: <2285d3b428c7d8f1c4fda2fb995e7e46a05350e0.1736324542.git.lorenzo@kernel.org>
In-Reply-To: <0c0ae72f5c84c5a29495337b254ac3cc2d5c16bb.1736324541.git.lorenzo@kernel.org>
References: <0c0ae72f5c84c5a29495337b254ac3cc2d5c16bb.1736324541.git.lorenzo@kernel.org>
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Tue, 3 Sep 2024 23:14:02 +0200
Subject: [PATCH 2/2] PCI: mediatek-gen3: configure PBUS_CSR registers for
EN7581 SoC
Configure PBus base address and address mask in order to allow the hw
detecting if a given address is on PCIE0, PCIE1 or PCIE2.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -15,6 +15,7 @@
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/msi.h>
#include <linux/of_device.h>
@@ -24,6 +25,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
#include "../pci.h"
@@ -120,6 +122,13 @@
#define MAX_NUM_PHY_RESETS 3
+#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3))
+#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3))
+#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \
+ ((_n) == 2 ? 0x28000000 : \
+ (_n) == 1 ? 0x24000000 : 0x20000000)
+#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26)
+
/* Time in ms needed to complete PCIe reset on EN7581 SoC */
#define PCIE_EN7581_RESET_TIME_MS 100
@@ -871,7 +880,8 @@ static int mtk_pcie_parse_port(struct mt
static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
{
struct device *dev = pcie->dev;
- int err;
+ struct regmap *map;
+ int err, slot;
u32 val;
/*
@@ -880,6 +890,23 @@ static int mtk_pcie_en7581_power_up(stru
*/
mdelay(PCIE_EN7581_RESET_TIME_MS);
+ map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ /*
+ * Configure PBus base address and address mask in order to allow the
+ * hw detecting if a given address is on PCIE0, PCIE1 or PCIE2.
+ */
+ slot = of_get_pci_domain_nr(dev->of_node);
+ if (slot < 0)
+ return slot;
+
+ regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot),
+ PCIE_EN7581_PBUS_BASE_ADDR(slot));
+ regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot),
+ PCIE_EN7581_PBUS_BASE_ADDR_MASK);
+
err = phy_init(pcie->phy);
if (err) {
dev_err(dev, "failed to initialize PHY\n");

104
target/linux/airoha/patches-6.6/113-net-airoha-Fix-channel-configuration-for-ETS-Qdisc.patch Normal file
View File

@ -0,0 +1,104 @@
From patchwork Tue Jan 7 22:26:28 2025
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From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Tue, 07 Jan 2025 23:26:28 +0100
Subject: [PATCH net-next] net: airoha: Fix channel configuration for ETS
Qdisc
Precedence: bulk
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X-Change-ID: 20250107-airoha-ets-fix-chan-e35ccac76d64
To: Felix Fietkau <nbd@nbd.name>, Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>, Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
Lorenzo Bianconi <lorenzo@kernel.org>
X-Mailer: b4 0.14.2
X-Patchwork-Delegate: kuba@kernel.org
Limit ETS QoS channel to AIROHA_NUM_QOS_CHANNELS in
airoha_tc_setup_qdisc_ets() in order to align the configured channel to
the value set in airoha_dev_select_queue().
Fixes: 20bf7d07c956 ("net: airoha: Add sched ETS offload support")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
---
drivers/net/ethernet/mediatek/airoha_eth.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
---
base-commit: a1942da8a38717ddd9b4c132f59e1657c85c1432
change-id: 20250107-airoha-ets-fix-chan-e35ccac76d64
Best regards,
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -2833,11 +2833,14 @@ static int airoha_qdma_get_tx_ets_stats(
static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port,
struct tc_ets_qopt_offload *opt)
{
- int channel = TC_H_MAJ(opt->handle) >> 16;
+ int channel;
if (opt->parent == TC_H_ROOT)
return -EINVAL;
+ channel = TC_H_MAJ(opt->handle) >> 16;
+ channel = channel % AIROHA_NUM_QOS_CHANNELS;
+
switch (opt->command) {
case TC_ETS_REPLACE:
return airoha_qdma_set_tx_ets_sched(port, channel, opt);

12
target/linux/airoha/patches-6.6/200-spinlock-extend-guard-with-spinlock_bh-variants.patch
View File

@ -12,9 +12,9 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/include/linux/spinlock.h
+++ b/include/linux/spinlock.h
@@ -515,6 +515,10 @@ DEFINE_LOCK_GUARD_1(raw_spinlock_irq, ra
raw_spin_lock_irq(_T->lock),
raw_spin_unlock_irq(_T->lock))
@@ -519,6 +519,10 @@ DEFINE_LOCK_GUARD_1(raw_spinlock_irq, ra
DEFINE_LOCK_GUARD_1_COND(raw_spinlock_irq, _try, raw_spin_trylock_irq(_T->lock))
+DEFINE_LOCK_GUARD_1(raw_spinlock_bh, raw_spinlock_t,
+ raw_spin_lock_bh(_T->lock),
@ -23,9 +23,9 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
DEFINE_LOCK_GUARD_1(raw_spinlock_irqsave, raw_spinlock_t,
raw_spin_lock_irqsave(_T->lock, _T->flags),
raw_spin_unlock_irqrestore(_T->lock, _T->flags),
@@ -528,6 +532,10 @@ DEFINE_LOCK_GUARD_1(spinlock_irq, spinlo
spin_lock_irq(_T->lock),
spin_unlock_irq(_T->lock))
@@ -540,6 +544,10 @@ DEFINE_LOCK_GUARD_1(spinlock_irq, spinlo
DEFINE_LOCK_GUARD_1_COND(spinlock_irq, _try,
spin_trylock_irq(_T->lock))
+DEFINE_LOCK_GUARD_1(spinlock_bh, spinlock_t,
+ spin_lock_bh(_T->lock),

2
target/linux/ath79/dts/ar9344_nec_aterm.dtsi
View File

@ -281,8 +281,6 @@
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
/delete-node/ port@1;
/* NEC uPD720114 */

4
target/linux/ath79/dts/ar9344_qihoo_c301.dts
View File

@ -59,8 +59,9 @@
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@ -208,7 +209,6 @@
&usb_phy {
status = "okay";
phy-supply = <&usb_vbus>;
};
&pcie {

2
target/linux/ath79/dts/qca9531_8dev_carambola3.dts
View File

@ -35,8 +35,6 @@
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb_phy {

2
target/linux/ath79/dts/qca9531_8dev_lima.dts
View File

@ -26,8 +26,6 @@
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb_phy {

2
target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
View File

@ -74,8 +74,6 @@
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb_phy {

2
target/linux/ath79/dts/qca9531_tplink_tl-wr810n-v1.dts
View File

@ -19,8 +19,6 @@
&usb0 {
status = "okay";
vbus-supply = <&reg_usb_vbus>;
};
&usb_phy {

1
target/linux/ath79/dts/qca953x.dtsi
View File

@ -193,7 +193,6 @@
interrupts = <3>;
resets = <&rst 5>;
dr_mode = "host";
has-transaction-translator;
caps-offset = <0x100>;

1
target/linux/ath79/dts/qca9558_aruba_ap-115.dts
View File

@ -243,6 +243,5 @@
};
&usb0 {
dr_mode = "host";
status = "okay";
};

2
target/linux/ath79/dts/qca9558_nec_aterm.dtsi
View File

@ -352,8 +352,6 @@
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
/delete-node/ port@1;
/* NEC uPD720114 */

4
target/linux/ath79/dts/qca9558_sophos_ap.dtsi
View File

@ -191,7 +191,3 @@
nvmem-cells = <&cal_art_1000>;
nvmem-cell-names = "calibration";
};
&usb0 {
vbus-supply = <&reg_usb_vbus>;
};

1
target/linux/ath79/dts/qca9558_sophos_ap100.dts
View File

@ -17,5 +17,4 @@
&usb0 {
status = "okay";
dr_mode = "host";
};

1
target/linux/ath79/dts/qca9558_sophos_ap55.dts
View File

@ -17,5 +17,4 @@
&usb0 {
status = "okay";
dr_mode = "host";
};

4
target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi
View File

@ -145,8 +145,6 @@
};
&usb0 {
dr_mode = "host";
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
@ -155,7 +153,5 @@
};
&usb1 {
dr_mode = "host";
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

12
target/linux/ath79/dts/qca955x_elecom_wab.dtsi
View File

@ -34,7 +34,7 @@
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_USB;
trigger-sources = <&usb_port1>;
trigger-sources = <&hub_port0>;
linux,default-trigger = "usbport";
};
};
@ -232,17 +232,7 @@
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
dr_mode = "host";
vbus-supply = <&reg_usb_vbus>;
usb_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&wdt {

4
target/linux/bcm27xx/patches-6.6/950-0061-Revert-Revert-xhci-add-quirk-for-host-controllers-th.patch
View File

@ -28,7 +28,7 @@ We don't agree with upstream revert so undo it.
pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -633,8 +633,11 @@ static int xhci_move_dequeue_past_td(str
@@ -634,8 +634,11 @@ static int xhci_move_dequeue_past_td(str
struct xhci_ring *ep_ring;
struct xhci_command *cmd;
struct xhci_segment *new_seg;
@ -40,7 +40,7 @@ We don't agree with upstream revert so undo it.
dma_addr_t addr;
u64 hw_dequeue;
bool cycle_found = false;
@@ -672,7 +675,27 @@ static int xhci_move_dequeue_past_td(str
@@ -673,7 +676,27 @@ static int xhci_move_dequeue_past_td(str
hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
new_seg = ep_ring->deq_seg;
new_deq = ep_ring->dequeue;

2
target/linux/bcm27xx/patches-6.6/950-0106-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch
View File

@ -17583,7 +17583,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
* For devices with more than one control interface, we assume the
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -2247,6 +2247,8 @@ static const struct usb_audio_quirk_flag
@@ -2249,6 +2249,8 @@ static const struct usb_audio_quirk_flag
QUIRK_FLAG_ALIGN_TRANSFER),
DEVICE_FLG(0x534d, 0x2109, /* MacroSilicon MS2109 */
QUIRK_FLAG_ALIGN_TRANSFER),

4
target/linux/bcm27xx/patches-6.6/950-0161-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1497,6 +1497,109 @@ command_cleanup:
@@ -1498,6 +1498,109 @@ command_cleanup:
}
/*
@ -125,7 +125,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
* non-error returns are a promise to giveback() the urb later
* we drop ownership so next owner (or urb unlink) can get it
*/
@@ -5347,6 +5450,7 @@ static const struct hc_driver xhci_hc_dr
@@ -5360,6 +5463,7 @@ static const struct hc_driver xhci_hc_dr
.endpoint_reset = xhci_endpoint_reset,
.check_bandwidth = xhci_check_bandwidth,
.reset_bandwidth = xhci_reset_bandwidth,

2
target/linux/bcm27xx/patches-6.6/950-0162-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch
View File

@ -26,7 +26,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -738,9 +738,9 @@ deq_found:
@@ -739,9 +739,9 @@ deq_found:
}
if ((ep->ep_state & SET_DEQ_PENDING)) {

2
target/linux/bcm27xx/patches-6.6/950-0163-usb-xhci-drop-and-add-the-endpoint-context-in-xhci_f.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1586,7 +1586,7 @@ static void xhci_fixup_endpoint(struct u
@@ -1587,7 +1587,7 @@ static void xhci_fixup_endpoint(struct u
return;
}
ctrl_ctx->add_flags = xhci_get_endpoint_flag_from_index(ep_index);

2
target/linux/bcm27xx/patches-6.6/950-0481-xhci-Use-more-event-ring-segment-table-entries.patch
View File

@ -52,7 +52,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1425,8 +1425,9 @@ struct urb_priv {
@@ -1426,8 +1426,9 @@ struct urb_priv {
* Each segment table entry is 4*32bits long. 1K seems like an ok size:
* (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
* meaning 64 ring segments.

4
target/linux/bcm27xx/patches-6.6/950-0482-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
View File

@ -34,7 +34,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -728,6 +728,15 @@ static int xhci_move_dequeue_past_td(str
@@ -729,6 +729,15 @@ static int xhci_move_dequeue_past_td(str
} while (!cycle_found || !td_last_trb_found);
deq_found:
@ -52,7 +52,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
addr = xhci_trb_virt_to_dma(new_seg, new_deq);
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1663,6 +1663,9 @@ struct xhci_hcd {
@@ -1664,6 +1664,9 @@ struct xhci_hcd {
#define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
#define XHCI_ETRON_HOST BIT_ULL(49)

2
target/linux/bcm27xx/patches-6.6/950-0484-usb-xhci-add-VLI_SS_BULK_OUT_BUG-quirk.patch
View File

@ -100,7 +100,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1665,6 +1665,7 @@ struct xhci_hcd {
@@ -1666,6 +1666,7 @@ struct xhci_hcd {
/* Downstream VLI fixes */
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(56)

8
target/linux/bcm27xx/patches-6.6/950-0485-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch
View File

@ -75,7 +75,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -3674,6 +3674,48 @@ static int xhci_align_td(struct xhci_hcd
@@ -3714,6 +3714,48 @@ static int xhci_align_td(struct xhci_hcd
return 1;
}
@ -124,7 +124,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
/* This is very similar to what ehci-q.c qtd_fill() does */
int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index)
@@ -3830,6 +3872,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
@@ -3870,6 +3912,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
}
check_trb_math(urb, enqd_len);
@ -133,7 +133,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
start_cycle, start_trb);
return 0;
@@ -3979,6 +4023,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
@@ -4019,6 +4063,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
/* Event on completion */
field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
@ -144,7 +144,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
return 0;
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1666,6 +1666,7 @@ struct xhci_hcd {
@@ -1667,6 +1667,7 @@ struct xhci_hcd {
/* Downstream VLI fixes */
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(56)
#define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(57)

4
target/linux/bcm27xx/patches-6.6/950-0519-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
View File

@ -333,7 +333,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
/* Global Debug LSP MUX Select */
#define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
@@ -1062,6 +1065,7 @@ struct dwc3_scratchpad_array {
@@ -1066,6 +1069,7 @@ struct dwc3_scratchpad_array {
* @tx_max_burst_prd: max periodic ESS transmit burst size
* @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
* @clear_stall_protocol: endpoint number that requires a delayed status phase
@ -341,7 +341,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
* @hsphy_interface: "utmi" or "ulpi"
* @connected: true when we're connected to a host, false otherwise
* @softconnect: true when gadget connect is called, false when disconnect runs
@@ -1299,6 +1303,7 @@ struct dwc3 {
@@ -1303,6 +1307,7 @@ struct dwc3 {
u8 tx_max_burst_prd;
u8 tx_fifo_resize_max_num;
u8 clear_stall_protocol;

4
target/linux/bcm27xx/patches-6.6/950-0853-drivers-usb-dwc3-add-FS-LS-bus-instance-parkmode-dis.patch
View File

@ -45,7 +45,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
/* Global Status Register */
@@ -1117,10 +1118,12 @@ struct dwc3_scratchpad_array {
@@ -1121,10 +1122,12 @@ struct dwc3_scratchpad_array {
* generation after resume from suspend.
* @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
* VBUS with an external supply.
@ -62,7 +62,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
* 0 - -6dB de-emphasis
@@ -1347,6 +1350,7 @@ struct dwc3 {
@@ -1351,6 +1354,7 @@ struct dwc3 {
unsigned ulpi_ext_vbus_drv:1;
unsigned parkmode_disable_ss_quirk:1;
unsigned parkmode_disable_hs_quirk:1;

2
target/linux/bcm27xx/patches-6.6/950-1261-mm-vmscan-Maintain-TLB-coherency-in-LRU-code.patch
View File

@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -4716,7 +4716,7 @@ void lru_gen_look_around(struct page_vma
@@ -4723,7 +4723,7 @@ void lru_gen_look_around(struct page_vma
if (!folio)
continue;

4
target/linux/bcm27xx/patches-6.6/950-1359-usb-dwc3-core-add-support-for-setting-NAK-enhancemen.patch
View File

@ -57,7 +57,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
#define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16)
#define DWC3_GUCTL1_PARKMODE_DISABLE_FSLS BIT(15)
@@ -1118,6 +1120,8 @@ struct dwc3_scratchpad_array {
@@ -1122,6 +1124,8 @@ struct dwc3_scratchpad_array {
* generation after resume from suspend.
* @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
* VBUS with an external supply.
@ -66,7 +66,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
* @parkmode_disable_ss_quirk: If set, disable park mode feature for all
* Superspeed instances.
* @parkmode_disable_hs_quirk: If set, disable park mode feature for all
@@ -1348,6 +1352,8 @@ struct dwc3 {
@@ -1352,6 +1356,8 @@ struct dwc3 {
unsigned dis_tx_ipgap_linecheck_quirk:1;
unsigned resume_hs_terminations:1;
unsigned ulpi_ext_vbus_drv:1;

2
target/linux/bcm27xx/patches-6.6/950-1361-drivers-usb-xhci-prevent-a-theoretical-race-on-non-c.patch
View File

@ -28,7 +28,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -505,6 +505,19 @@ void xhci_ring_ep_doorbell(struct xhci_h
@@ -506,6 +506,19 @@ void xhci_ring_ep_doorbell(struct xhci_h
trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));

6
target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
View File

@ -35,7 +35,7 @@ it on BCM4708 family.
/* called during probe() after chip reset completes */
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -161,6 +161,49 @@ int xhci_start(struct xhci_hcd *xhci)
@@ -162,6 +162,49 @@ int xhci_start(struct xhci_hcd *xhci)
return ret;
}
@ -85,7 +85,7 @@ it on BCM4708 family.
/*
* Reset a halted HC.
*
@@ -480,6 +523,15 @@ static int xhci_run_finished(struct xhci
@@ -481,6 +524,15 @@ static int xhci_run_finished(struct xhci
return -ENODEV;
}
@ -103,7 +103,7 @@ it on BCM4708 family.
if (xhci->quirks & XHCI_NEC_HOST)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1661,6 +1661,7 @@ struct xhci_hcd {
@@ -1662,6 +1662,7 @@ struct xhci_hcd {
#define XHCI_WRITE_64_HI_LO BIT_ULL(47)
#define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
#define XHCI_ETRON_HOST BIT_ULL(49)

260
target/linux/bmips/patches-6.6/110-pinctrl-bcm63268-add-gpio-function.patch
View File

@ -1,260 +0,0 @@
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From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>
To: linus.walleij@linaro.org,
kylehendrydev@gmail.com,
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linux-kernel@vger.kernel.org
Cc: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>
Subject: [PATCH v2] pinctrl: bcm63268: add gpio function
Date: Tue, 24 Dec 2024 11:36:45 +0100
Message-Id: <20241224103645.1709996-1-noltari@gmail.com>
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From: Kyle Hendry <kylehendrydev@gmail.com>
There is no guarantee that the bootloader will leave the pin configuration
in a known default state, so pinctrl needs to be explicitly set in some
cases. This patch adds a gpio function for drivers that need it, i.e.
gpio-leds.
Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
drivers/pinctrl/bcm/pinctrl-bcm63268.c | 71 +++++++++++++++++++++++++-
1 file changed, 70 insertions(+), 1 deletion(-)
--- a/drivers/pinctrl/bcm/pinctrl-bcm63268.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c
@@ -34,6 +34,7 @@
#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */
enum bcm63268_pinctrl_reg {
+ BCM63268_NONE,
BCM63268_LEDCTRL,
BCM63268_MODE,
BCM63268_CTRL,
@@ -242,6 +243,61 @@ static struct pingroup bcm63268_groups[]
BCM_PIN_GROUP(vdsl_phy3_grp),
};
+static const char * const gpio_groups[] = {
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+ "gpio8",
+ "gpio9",
+ "gpio10",
+ "gpio11",
+ "gpio12",
+ "gpio13",
+ "gpio14",
+ "gpio15",
+ "gpio16",
+ "gpio17",
+ "gpio18",
+ "gpio19",
+ "gpio20",
+ "gpio21",
+ "gpio22",
+ "gpio23",
+ "gpio24",
+ "gpio25",
+ "gpio26",
+ "gpio27",
+ "gpio28",
+ "gpio29",
+ "gpio30",
+ "gpio31",
+ "gpio32",
+ "gpio33",
+ "gpio34",
+ "gpio35",
+ "gpio36",
+ "gpio37",
+ "gpio38",
+ "gpio39",
+ "gpio40",
+ "gpio41",
+ "gpio42",
+ "gpio43",
+ "gpio44",
+ "gpio45",
+ "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49",
+ "gpio50",
+ "gpio51",
+};
+
static const char * const led_groups[] = {
"gpio0",
"gpio1",
@@ -394,6 +450,14 @@ static const char * const vdsl_phy_overr
"vdsl_phy_override_3_grp",
};
+#define BCM63268_GPIO_FUN(n) \
+ { \
+ .name = #n, \
+ .groups = n##_groups, \
+ .num_groups = ARRAY_SIZE(n##_groups), \
+ .reg = BCM63268_NONE, \
+ }
+
#define BCM63268_LED_FUN(n) \
{ \
.name = #n, \
@@ -428,6 +492,7 @@ static const char * const vdsl_phy_overr
}
static const struct bcm63268_function bcm63268_funcs[] = {
+ BCM63268_GPIO_FUN(gpio),
BCM63268_LED_FUN(led),
BCM63268_MODE_FUN(serial_led_clk),
BCM63268_MODE_FUN(serial_led_data),
@@ -542,6 +607,9 @@ static int bcm63268_pinctrl_set_mux(stru
bcm63268_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
+ case BCM63268_NONE:
+ reg = 0;
+ break;
case BCM63268_LEDCTRL:
reg = BCM63268_LED_REG;
mask = BIT(pg->pins[0]);
@@ -567,7 +635,8 @@ static int bcm63268_pinctrl_set_mux(stru
return -EINVAL;
}
- regmap_update_bits(pc->regs, reg, mask, val);
+ if (reg)
+ regmap_update_bits(pc->regs, reg, mask, val);
return 0;
}

6
target/linux/generic/backport-6.6/600-v6.10-net-Remove-conditional-threaded-NAPI-wakeup-based-on.patch
View File

@ -32,7 +32,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -4481,13 +4481,7 @@ static inline void ____napi_schedule(str
@@ -4483,13 +4483,7 @@ static inline void ____napi_schedule(str
*/
thread = READ_ONCE(napi->thread);
if (thread) {
@ -47,7 +47,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
wake_up_process(thread);
return;
}
@@ -6643,8 +6637,6 @@ static int napi_poll(struct napi_struct
@@ -6645,8 +6639,6 @@ static int napi_poll(struct napi_struct
static int napi_thread_wait(struct napi_struct *napi)
{
@ -56,7 +56,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
set_current_state(TASK_INTERRUPTIBLE);
while (!kthread_should_stop()) {
@@ -6653,15 +6645,13 @@ static int napi_thread_wait(struct napi_
@@ -6655,15 +6647,13 @@ static int napi_thread_wait(struct napi_
* Testing SCHED bit is not enough because SCHED bit might be
* set by some other busy poll thread or by napi_disable().
*/

22
target/linux/generic/backport-6.6/601-v6.10-net-Allow-to-use-SMP-threads-for-backlog-NAPI.patch
View File

@ -108,7 +108,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
static inline void rps_lock_irqsave(struct softnet_data *sd,
unsigned long *flags)
{
@@ -4449,6 +4475,7 @@ EXPORT_SYMBOL(__dev_direct_xmit);
@@ -4451,6 +4477,7 @@ EXPORT_SYMBOL(__dev_direct_xmit);
/*************************************************************************
* Receiver routines
*************************************************************************/
@ -116,7 +116,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
int netdev_max_backlog __read_mostly = 1000;
EXPORT_SYMBOL(netdev_max_backlog);
@@ -4481,12 +4508,16 @@ static inline void ____napi_schedule(str
@@ -4483,12 +4510,16 @@ static inline void ____napi_schedule(str
*/
thread = READ_ONCE(napi->thread);
if (thread) {
@ -133,7 +133,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
list_add_tail(&napi->poll_list, &sd->poll_list);
WRITE_ONCE(napi->list_owner, smp_processor_id());
/* If not called from net_rx_action()
@@ -4732,6 +4763,11 @@ static void napi_schedule_rps(struct sof
@@ -4734,6 +4765,11 @@ static void napi_schedule_rps(struct sof
#ifdef CONFIG_RPS
if (sd != mysd) {
@ -145,7 +145,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
sd->rps_ipi_next = mysd->rps_ipi_list;
mysd->rps_ipi_list = sd;
@@ -5955,7 +5991,7 @@ static void net_rps_action_and_irq_enabl
@@ -5957,7 +5993,7 @@ static void net_rps_action_and_irq_enabl
#ifdef CONFIG_RPS
struct softnet_data *remsd = sd->rps_ipi_list;
@ -154,7 +154,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
sd->rps_ipi_list = NULL;
local_irq_enable();
@@ -5970,7 +6006,7 @@ static void net_rps_action_and_irq_enabl
@@ -5972,7 +6008,7 @@ static void net_rps_action_and_irq_enabl
static bool sd_has_rps_ipi_waiting(struct softnet_data *sd)
{
#ifdef CONFIG_RPS
@ -163,7 +163,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
#else
return false;
#endif
@@ -6014,7 +6050,7 @@ static int process_backlog(struct napi_s
@@ -6016,7 +6052,7 @@ static int process_backlog(struct napi_s
* We can use a plain write instead of clear_bit(),
* and we dont need an smp_mb() memory barrier.
*/
@ -172,7 +172,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
again = false;
} else {
skb_queue_splice_tail_init(&sd->input_pkt_queue,
@@ -6680,43 +6716,48 @@ static void skb_defer_free_flush(struct
@@ -6682,43 +6718,48 @@ static void skb_defer_free_flush(struct
}
}
@ -250,7 +250,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
return 0;
}
@@ -11297,7 +11338,7 @@ static int dev_cpu_dead(unsigned int old
@@ -11299,7 +11340,7 @@ static int dev_cpu_dead(unsigned int old
list_del_init(&napi->poll_list);
if (napi->poll == process_backlog)
@ -259,7 +259,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
else
____napi_schedule(sd, napi);
}
@@ -11305,12 +11346,14 @@ static int dev_cpu_dead(unsigned int old
@@ -11307,12 +11348,14 @@ static int dev_cpu_dead(unsigned int old
raise_softirq_irqoff(NET_TX_SOFTIRQ);
local_irq_enable();
@ -278,7 +278,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
/* Process offline CPU's input_pkt_queue */
while ((skb = __skb_dequeue(&oldsd->process_queue))) {
@@ -11573,6 +11616,38 @@ static struct pernet_operations __net_in
@@ -11575,6 +11618,38 @@ static struct pernet_operations __net_in
*
*/
@ -317,7 +317,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
/*
* This is called single threaded during boot, so no need
* to take the rtnl semaphore.
@@ -11623,7 +11698,10 @@ static int __init net_dev_init(void)
@@ -11625,7 +11700,10 @@ static int __init net_dev_init(void)
init_gro_hash(&sd->backlog);
sd->backlog.poll = process_backlog;
sd->backlog.weight = weight_p;

2
target/linux/generic/backport-6.6/602-v6.10-net-Use-backlog-NAPI-to-clean-up-the-defer_list.patch
View File

@ -82,7 +82,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
spin_unlock_irq(&sd->input_pkt_queue.lock);
else if (!IS_ENABLED(CONFIG_PREEMPT_RT))
local_irq_enable();
@@ -4782,6 +4782,23 @@ static void napi_schedule_rps(struct sof
@@ -4784,6 +4784,23 @@ static void napi_schedule_rps(struct sof
__napi_schedule_irqoff(&mysd->backlog);
}

18
target/linux/generic/backport-6.6/603-v6.10-net-Rename-rps_lock-to-backlog_lock.patch
View File

@ -67,7 +67,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
{
if (IS_ENABLED(CONFIG_RPS) || use_backlog_threads())
spin_unlock_irq(&sd->input_pkt_queue.lock);
@@ -4787,12 +4787,12 @@ void kick_defer_list_purge(struct softne
@@ -4789,12 +4789,12 @@ void kick_defer_list_purge(struct softne
unsigned long flags;
if (use_backlog_threads()) {
@ -82,7 +82,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
} else if (!cmpxchg(&sd->defer_ipi_scheduled, 0, 1)) {
smp_call_function_single_async(cpu, &sd->defer_csd);
@@ -4854,7 +4854,7 @@ static int enqueue_to_backlog(struct sk_
@@ -4856,7 +4856,7 @@ static int enqueue_to_backlog(struct sk_
reason = SKB_DROP_REASON_NOT_SPECIFIED;
sd = &per_cpu(softnet_data, cpu);
@ -91,7 +91,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
if (!netif_running(skb->dev))
goto drop;
qlen = skb_queue_len(&sd->input_pkt_queue);
@@ -4863,7 +4863,7 @@ static int enqueue_to_backlog(struct sk_
@@ -4865,7 +4865,7 @@ static int enqueue_to_backlog(struct sk_
enqueue:
__skb_queue_tail(&sd->input_pkt_queue, skb);
input_queue_tail_incr_save(sd, qtail);
@ -100,7 +100,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
return NET_RX_SUCCESS;
}
@@ -4878,7 +4878,7 @@ enqueue:
@@ -4880,7 +4880,7 @@ enqueue:
drop:
sd->dropped++;
@ -109,7 +109,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
dev_core_stats_rx_dropped_inc(skb->dev);
kfree_skb_reason(skb, reason);
@@ -5909,7 +5909,7 @@ static void flush_backlog(struct work_st
@@ -5911,7 +5911,7 @@ static void flush_backlog(struct work_st
local_bh_disable();
sd = this_cpu_ptr(&softnet_data);
@ -118,7 +118,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
skb_queue_walk_safe(&sd->input_pkt_queue, skb, tmp) {
if (skb->dev->reg_state == NETREG_UNREGISTERING) {
__skb_unlink(skb, &sd->input_pkt_queue);
@@ -5917,7 +5917,7 @@ static void flush_backlog(struct work_st
@@ -5919,7 +5919,7 @@ static void flush_backlog(struct work_st
input_queue_head_incr(sd);
}
}
@ -127,7 +127,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
skb_queue_walk_safe(&sd->process_queue, skb, tmp) {
if (skb->dev->reg_state == NETREG_UNREGISTERING) {
@@ -5935,14 +5935,14 @@ static bool flush_required(int cpu)
@@ -5937,14 +5937,14 @@ static bool flush_required(int cpu)
struct softnet_data *sd = &per_cpu(softnet_data, cpu);
bool do_flush;
@ -144,7 +144,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
return do_flush;
#endif
@@ -6057,7 +6057,7 @@ static int process_backlog(struct napi_s
@@ -6059,7 +6059,7 @@ static int process_backlog(struct napi_s
}
@ -153,7 +153,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
if (skb_queue_empty(&sd->input_pkt_queue)) {
/*
* Inline a custom version of __napi_complete().
@@ -6073,7 +6073,7 @@ static int process_backlog(struct napi_s
@@ -6075,7 +6075,7 @@ static int process_backlog(struct napi_s
skb_queue_splice_tail_init(&sd->input_pkt_queue,
&sd->process_queue);
}

6
target/linux/generic/backport-6.6/611-02-v6.11-net-Make-USO-depend-on-CSUM-offload.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9759,6 +9759,15 @@ static void netdev_sync_lower_features(s
@@ -9761,6 +9761,15 @@ static void netdev_sync_lower_features(s
}
}
@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
static netdev_features_t netdev_fix_features(struct net_device *dev,
netdev_features_t features)
{
@@ -9840,15 +9849,9 @@ static netdev_features_t netdev_fix_feat
@@ -9842,15 +9851,9 @@ static netdev_features_t netdev_fix_feat
features &= ~NETIF_F_LRO;
}
@ -55,7 +55,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
}
if ((features & NETIF_F_HW_TLS_RX) && !(features & NETIF_F_RXCSUM)) {
@@ -9856,6 +9859,11 @@ static netdev_features_t netdev_fix_feat
@@ -9858,6 +9861,11 @@ static netdev_features_t netdev_fix_feat
features &= ~NETIF_F_HW_TLS_RX;
}

2
target/linux/generic/backport-6.6/612-v6.9-net-get-stats64-if-device-if-driver-is-configured.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -10666,6 +10666,8 @@ struct rtnl_link_stats64 *dev_get_stats(
@@ -10668,6 +10668,8 @@ struct rtnl_link_stats64 *dev_get_stats(
ops->ndo_get_stats64(dev, storage);
} else if (ops->ndo_get_stats) {
netdev_stats_to_stats64(storage, ops->ndo_get_stats(dev));

6
target/linux/generic/backport-6.6/700-v6.10-net-create-a-dummy-net_device-allocator.patch
View File

@ -49,7 +49,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
unsigned char name_assign_type,
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -10353,25 +10353,12 @@ err_free_name:
@@ -10355,25 +10355,12 @@ err_free_name:
}
EXPORT_SYMBOL(register_netdevice);
@ -79,7 +79,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
/* make sure we BUG if trying to hit standard
* register/unregister code path
*/
@@ -10391,12 +10378,32 @@ int init_dummy_netdev(struct net_device
@@ -10393,12 +10380,32 @@ int init_dummy_netdev(struct net_device
* because users of this 'device' dont need to change
* its refcount.
*/
@ -113,7 +113,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
/**
* register_netdev - register a network device
* @dev: device to register
@@ -10990,6 +10997,19 @@ void free_netdev(struct net_device *dev)
@@ -10992,6 +10999,19 @@ void free_netdev(struct net_device *dev)
EXPORT_SYMBOL(free_netdev);
/**

2
target/linux/generic/backport-6.6/770-net-introduce-napi_is_scheduled-helper.patch
View File

@ -85,7 +85,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
/**
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -6610,7 +6610,7 @@ static int __napi_poll(struct napi_struc
@@ -6612,7 +6612,7 @@ static int __napi_poll(struct napi_struc
* accidentally calling ->poll() when NAPI is not scheduled.
*/
work = 0;

2
target/linux/generic/backport-6.6/900-v6.11-net-free_netdev-exit-earlier-if-dummy.patch
View File

@ -23,7 +23,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -10983,7 +10983,8 @@ void free_netdev(struct net_device *dev)
@@ -10985,7 +10985,8 @@ void free_netdev(struct net_device *dev)
dev->xdp_bulkq = NULL;
/* Compatibility with error handling in drivers */

52
target/linux/generic/backport-6.6/902-net-llc-reset-skb-transport_header.patch
View File

@ -1,52 +0,0 @@
From a024e377efed31ecfb39210bed562932321345b3 Mon Sep 17 00:00:00 2001
From: Antonio Pastor <antonio.pastor@gmail.com>
Date: Tue, 24 Dec 2024 20:07:20 -0500
Subject: [PATCH] net: llc: reset skb->transport_header
802.2+LLC+SNAP frames received by napi_complete_done with GRO and DSA
have skb->transport_header set two bytes short, or pointing 2 bytes
before network_header & skb->data. As snap_rcv expects transport_header
to point to SNAP header (OID:PID) after LLC processing advances offset
over LLC header (llc_rcv & llc_fixup_skb), code doesn't find a match
and packet is dropped.
Between napi_complete_done and snap_rcv, transport_header is not used
until __netif_receive_skb_core, where originally it was being reset.
Commit fda55eca5a33 ("net: introduce skb_transport_header_was_set()")
only does so if not set, on the assumption the value was set correctly
by GRO (and also on assumption that "network stacks usually reset the
transport header anyway"). Afterwards it is moved forward by
llc_fixup_skb.
Locally generated traffic shows up at __netif_receive_skb_core with no
transport_header set and is processed without issue. On a setup with
GRO but no DSA, transport_header and network_header are both set to
point to skb->data which is also correct.
As issue is LLC specific, to avoid impacting non-LLC traffic, and to
follow up on original assumption made on previous code change,
llc_fixup_skb to reset the offset after skb pull. llc_fixup_skb
assumes the LLC header is at skb->data, and by definition SNAP header
immediately follows.
Fixes: fda55eca5a33 ("net: introduce skb_transport_header_was_set()")
Signed-off-by: Antonio Pastor <antonio.pastor@gmail.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://patch.msgid.link/20241225010723.2830290-1-antonio.pastor@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
net/llc/llc_input.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/net/llc/llc_input.c
+++ b/net/llc/llc_input.c
@@ -124,8 +124,8 @@ static inline int llc_fixup_skb(struct s
if (unlikely(!pskb_may_pull(skb, llc_len)))
return 0;
- skb->transport_header += llc_len;
skb_pull(skb, llc_len);
+ skb_reset_transport_header(skb);
if (skb->protocol == htons(ETH_P_802_2)) {
__be16 pdulen;
s32 data_size;

2
target/linux/generic/hack-6.6/901-debloat_sock_diag.patch
View File

@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
u32));
INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
@@ -2239,9 +2256,11 @@ static void __sk_free(struct sock *sk)
@@ -2242,9 +2259,11 @@ static void __sk_free(struct sock *sk)
if (likely(sk->sk_net_refcnt))
sock_inuse_add(sock_net(sk), -1);

2
target/linux/generic/hack-6.6/902-debloat_proc.patch
View File

@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -4140,6 +4140,8 @@ static __net_initdata struct pernet_oper
@@ -4143,6 +4143,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{

82
target/linux/generic/pending-6.6/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
View File

@ -1,82 +0,0 @@
From: Tobias Wolf <dev-NTEO@vplace.de>
Subject: mm: Fix alloc_node_mem_map with ARCH_PFN_OFFSET calculation
An rt288x (ralink) based router (Belkin F5D8235 v1) does not boot with any
kernel beyond version 4.3 resulting in:
BUG: Bad page state in process swapper pfn:086ac
bisect resulted in:
a1c34a3bf00af2cede839879502e12dc68491ad5 is the first bad commit
commit a1c34a3bf00af2cede839879502e12dc68491ad5
Author: Laura Abbott <laura@labbott.name>
Date: Thu Nov 5 18:48:46 2015 -0800
mm: Don't offset memmap for flatmem
Srinivas Kandagatla reported bad page messages when trying to remove the
bottom 2MB on an ARM based IFC6410 board
BUG: Bad page state in process swapper pfn:fffa8
page:ef7fb500 count:0 mapcount:0 mapping: (null) index:0x0
flags: 0x96640253(locked|error|dirty|active|arch_1|reclaim|mlocked)
page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set
bad because of flags:
flags: 0x200041(locked|active|mlocked)
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 3.19.0-rc3-00007-g412f9ba-dirty
#816
Hardware name: Qualcomm (Flattened Device Tree)
unwind_backtrace
show_stack
dump_stack
bad_page
free_pages_prepare
free_hot_cold_page
__free_pages
free_highmem_page
mem_init
start_kernel
Disabling lock debugging due to kernel taint
[...]
:040000 040000 2de013c372345fd471cd58f0553c9b38b0ef1cc4
0a8156f848733dfa21e16c196dfb6c0a76290709 M mm
This fix for ARM does not account ARCH_PFN_OFFSET for mem_map as later used by
page_to_pfn anymore.
The following output was generated with two hacked in printk statements:
printk("before %p vs. %p or %p\n", mem_map, mem_map - offset, mem_map -
(pgdat->node_start_pfn - ARCH_PFN_OFFSET));
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
mem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET);
printk("after %p\n", mem_map);
Output:
[ 0.000000] before 8861b280 vs. 8861b280 or 8851b280
[ 0.000000] after 8851b280
As seen in the first line mem_map with subtraction of offset does not equal the
mem_map after subtraction of ARCH_PFN_OFFSET.
After adding the offset of ARCH_PFN_OFFSET as well to mem_map as the
previously calculated offset is zero for the named platform it is able to boot
4.4 and 4.9-rc7 again.
Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
---
--- a/mm/mm_init.c
+++ b/mm/mm_init.c
@@ -1673,7 +1673,7 @@ static void __init alloc_node_mem_map(st
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
- mem_map -= offset;
+ mem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET);
}
#endif
}

87
target/linux/generic/pending-6.6/605-netfilter-nft_set_hash-unaligned-atomic-read-on-stru.patch
View File

@ -1,87 +0,0 @@
From 113fb8a8d1f27156f58b27ce0fc02af9b3705bf7 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Sun, 22 Dec 2024 11:02:39 +0100
Subject: [PATCH] netfilter: nft_set_hash: unaligned atomic read on struct
nft_set_ext
Access to genmask field in struct nft_set_ext results in unaligned
atomic read:
[ 72.130109] Unable to handle kernel paging request at virtual address ffff0000c2bb708c
[ 72.131036] Mem abort info:
[ 72.131213] ESR = 0x0000000096000021
[ 72.131446] EC = 0x25: DABT (current EL), IL = 32 bits
[ 72.132209] SET = 0, FnV = 0
[ 72.133216] EA = 0, S1PTW = 0
[ 72.134080] FSC = 0x21: alignment fault
[ 72.135593] Data abort info:
[ 72.137194] ISV = 0, ISS = 0x00000021, ISS2 = 0x00000000
[ 72.142351] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[ 72.145989] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[ 72.150115] swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000237d27000
[ 72.154893] [ffff0000c2bb708c] pgd=0000000000000000, p4d=180000023ffff403, pud=180000023f84b403, pmd=180000023f835403,
+pte=0068000102bb7707
[ 72.163021] Internal error: Oops: 0000000096000021 [#1] SMP
[...]
[ 72.170041] CPU: 7 UID: 0 PID: 54 Comm: kworker/7:0 Tainted: G E 6.13.0-rc3+ #2
[ 72.170509] Tainted: [E]=UNSIGNED_MODULE
[ 72.170720] Hardware name: QEMU QEMU Virtual Machine, BIOS edk2-stable202302-for-qemu 03/01/2023
[ 72.171192] Workqueue: events_power_efficient nft_rhash_gc [nf_tables]
[ 72.171552] pstate: 21400005 (nzCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[ 72.171915] pc : nft_rhash_gc+0x200/0x2d8 [nf_tables]
[ 72.172166] lr : nft_rhash_gc+0x128/0x2d8 [nf_tables]
[ 72.172546] sp : ffff800081f2bce0
[ 72.172724] x29: ffff800081f2bd40 x28: ffff0000c2bb708c x27: 0000000000000038
[ 72.173078] x26: ffff0000c6780ef0 x25: ffff0000c643df00 x24: ffff0000c6778f78
[ 72.173431] x23: 000000000000001a x22: ffff0000c4b1f000 x21: ffff0000c6780f78
[ 72.173782] x20: ffff0000c2bb70dc x19: ffff0000c2bb7080 x18: 0000000000000000
[ 72.174135] x17: ffff0000c0a4e1c0 x16: 0000000000003000 x15: 0000ac26d173b978
[ 72.174485] x14: ffffffffffffffff x13: 0000000000000030 x12: ffff0000c6780ef0
[ 72.174841] x11: 0000000000000000 x10: ffff800081f2bcf8 x9 : ffff0000c3000000
[ 72.175193] x8 : 00000000000004be x7 : 0000000000000000 x6 : 0000000000000000
[ 72.175544] x5 : 0000000000000040 x4 : ffff0000c3000010 x3 : 0000000000000000
[ 72.175871] x2 : 0000000000003a98 x1 : ffff0000c2bb708c x0 : 0000000000000004
[ 72.176207] Call trace:
[ 72.176316] nft_rhash_gc+0x200/0x2d8 [nf_tables] (P)
[ 72.176653] process_one_work+0x178/0x3d0
[ 72.176831] worker_thread+0x200/0x3f0
[ 72.176995] kthread+0xe8/0xf8
[ 72.177130] ret_from_fork+0x10/0x20
[ 72.177289] Code: 54fff984 d503201f d2800080 91003261 (f820303f)
[ 72.177557] ---[ end trace 0000000000000000 ]---
Align struct nft_set_ext to word size to address this and
documentation it.
pahole reports that this increases the size of elements for rhash and
pipapo in 8 bytes on x86_64.
Fixes: 7ffc7481153b ("netfilter: nft_set_hash: skip duplicated elements pending gc run")
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
include/net/netfilter/nf_tables.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
--- a/include/net/netfilter/nf_tables.h
+++ b/include/net/netfilter/nf_tables.h
@@ -721,15 +721,18 @@ struct nft_set_ext_tmpl {
/**
* struct nft_set_ext - set extensions
*
- * @genmask: generation mask
+ * @genmask: generation mask, but also flags (see NFT_SET_ELEM_DEAD_BIT)
* @offset: offsets of individual extension types
* @data: beginning of extension data
+ *
+ * This structure must be aligned to word size, otherwise atomic bitops
+ * on genmask field can cause aligment failure on some archs.
*/
struct nft_set_ext {
u8 genmask;
u8 offset[NFT_SET_EXT_NUM];
char data[];
-};
+} __aligned(BITS_PER_LONG / 8);
static inline void nft_set_ext_prepare(struct nft_set_ext_tmpl *tmpl)
{

16
target/linux/generic/pending-6.6/630-packet_socket_type.patch
View File

@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
#define PACKET_FANOUT_LB 1
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -1925,6 +1925,7 @@ static int packet_rcv_spkt(struct sk_buf
@@ -1911,6 +1911,7 @@ static int packet_rcv_spkt(struct sk_buf
{
struct sock *sk;
struct sockaddr_pkt *spkt;
@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/*
* When we registered the protocol we saved the socket in the data
@@ -1932,6 +1933,7 @@ static int packet_rcv_spkt(struct sk_buf
@@ -1918,6 +1919,7 @@ static int packet_rcv_spkt(struct sk_buf
*/
sk = pt->af_packet_priv;
@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
/*
* Yank back the headers [hope the device set this
@@ -1944,7 +1946,7 @@ static int packet_rcv_spkt(struct sk_buf
@@ -1930,7 +1932,7 @@ static int packet_rcv_spkt(struct sk_buf
* so that this procedure is noop.
*/
@ -55,7 +55,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
goto out;
if (!net_eq(dev_net(dev), sock_net(sk)))
@@ -2190,12 +2192,12 @@ static int packet_rcv(struct sk_buff *sk
@@ -2176,12 +2178,12 @@ static int packet_rcv(struct sk_buff *sk
unsigned int snaplen, res;
bool is_drop_n_account = false;
@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (!net_eq(dev_net(dev), sock_net(sk)))
goto drop;
@@ -2322,12 +2324,12 @@ static int tpacket_rcv(struct sk_buff *s
@@ -2308,12 +2310,12 @@ static int tpacket_rcv(struct sk_buff *s
BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32);
BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48);
@ -87,7 +87,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (!net_eq(dev_net(dev), sock_net(sk)))
goto drop;
@@ -3451,6 +3453,7 @@ static int packet_create(struct net *net
@@ -3437,6 +3439,7 @@ static int packet_create(struct net *net
mutex_init(&po->pg_vec_lock);
po->rollover = NULL;
po->prot_hook.func = packet_rcv;
@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (sock->type == SOCK_PACKET)
po->prot_hook.func = packet_rcv_spkt;
@@ -4118,6 +4121,16 @@ packet_setsockopt(struct socket *sock, i
@@ -4104,6 +4107,16 @@ packet_setsockopt(struct socket *sock, i
packet_sock_flag_set(po, PACKET_SOCK_QDISC_BYPASS, val);
return 0;
}
@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
default:
return -ENOPROTOOPT;
}
@@ -4177,6 +4190,13 @@ static int packet_getsockopt(struct sock
@@ -4163,6 +4176,13 @@ static int packet_getsockopt(struct sock
case PACKET_VNET_HDR_SZ:
val = READ_ONCE(po->vnet_hdr_sz);
break;

2
target/linux/generic/pending-6.6/681-net-remove-NETIF_F_GSO_FRAGLIST-from-NETIF_F_GSO_SOF.patch
View File

@ -96,7 +96,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
return features;
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -2441,7 +2441,7 @@ void sk_setup_caps(struct sock *sk, stru
@@ -2444,7 +2444,7 @@ void sk_setup_caps(struct sock *sk, stru
if (sk_is_tcp(sk))
sk->sk_route_caps |= NETIF_F_GSO;
if (sk->sk_route_caps & NETIF_F_GSO)

131
target/linux/generic/pending-6.6/821-gpio-regmap-Use-generic-request-free-ops.patch Normal file
View File

@ -0,0 +1,131 @@
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From: Sander Vanheule <sander@svanheule.net>
To: Michael Walle <mwalle@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>,
jonas.gorski@gmail.com, kylehendrydev@gmail.com,
florian.fainelli@broadcom.com, Sander Vanheule <sander@svanheule.net>
Subject: [PATCH] gpio: regmap: Use generic request/free ops
Date: Tue, 7 Jan 2025 21:16:20 +0100
Message-ID: <20250107201621.12467-1-sander@svanheule.net>
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Set the gpiochip request and free ops to the generic implementations.
This way a user can provide a gpio-ranges property defined for a pinmux,
easing muxing of gpio functions. Provided that the pin controller
implementents the pinmux op .gpio_request_enable(), pins will
automatically be muxed to their GPIO function when requested.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Acked-by: Michael Walle <mwalle@kernel.org>
---
Álvaro has submitted a similar patch today. My implementation's impact
is more limited, but I hadn't gotten around to submitting it yet.
For the original (short) discussion, see:
https://lore.kernel.org/linux-gpio/20250107102735.317446-1-noltari@gmail.com/T/#t
drivers/gpio/gpio-regmap.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -262,6 +262,8 @@ struct gpio_regmap *gpio_regmap_register
chip->label = config->label ?: dev_name(config->parent);
chip->can_sleep = regmap_might_sleep(config->regmap);
+ chip->request = gpiochip_generic_request;
+ chip->free = gpiochip_generic_free;
chip->get = gpio_regmap_get;
if (gpio->reg_set_base && gpio->reg_clr_base)
chip->set = gpio_regmap_set_with_clear;

1
target/linux/ipq40xx/chromium/config-default
View File

@ -1,4 +1,5 @@
CONFIG_BLK_DEV_SD=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SG_POOL=y

2
target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dtsi
View File

@ -8,12 +8,12 @@
/ {
aliases {
// TODO: Verify if the ethernet0 alias is needed
ethernet0 = &gmac;
led-boot = &led_blue;
led-failsafe = &led_red;
led-running = &led_blue;
led-upgrade = &led_red;
label-mac-device = &gmac;
};
soc {

61
target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wifi.dts
View File

@ -74,6 +74,67 @@
};
&tlmm {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
/* AP_FLASH_WP_L is crossystem ABI. */
"AP_FLASH_WP_L" /* 53 */,
"",
"",
"",
/* RECOVERY_SW_L is crossystem ABI. */
"RECOVERY_SW_L" /* 57 */;
fw_pinmux: fw_pinmux {
wp {
pins = "gpio53";

1
target/linux/ipq806x/chromium/config-default
View File

@ -1,6 +1,7 @@
CONFIG_ARM_PMUV3=y
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
CONFIG_BLK_DEV_SD=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_PHY_QCOM_IPQ806X_USB=y

21
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-tplink-onhub.dts
View File

@ -14,6 +14,27 @@
};
&qcom_pinmux {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
/* RECOVERY_SW_L is crossystem ABI. */
"RECOVERY_SW_L", /* 16 */
/* AP_FLASH_WP_L is crossystem ABI. */
"AP_FLASH_WP_L" /* 17 */;
i2c7_pins: i2c7_pinmux {
mux {
pins = "gpio8", "gpio9";

29
target/linux/ipq806x/patches-6.6/901-mtd-spi-nor-n25q064a-wp.patch Normal file
View File

@ -0,0 +1,29 @@
From 1e019e728800d4033b4b3b1b5570f5da5ed309f2 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Thu, 15 Dec 2022 01:49:20 -0800
Subject: [PATCH] mtd: spi-nor: micron-st: Add n25q064a WP support
These flash chips are used on Google / TP-Link / ASUS OnHub devices, and
OnHub devices are write-protected by default (same as any other
ChromeOS/Chromebook system).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
Submitted upstream at:
https://lore.kernel.org/linux-mtd/20240726185825.142733-1-computersforpeace@gmail.com/
https://patchwork.ozlabs.org/project/linux-mtd/patch/20240726185825.142733-1-computersforpeace@gmail.com/
drivers/mtd/spi-nor/micron-st.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -183,6 +183,8 @@ static const struct flash_info st_nor_pa
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |

2
target/linux/lantiq/patches-6.6/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -817,6 +817,16 @@ config I2C_MICROCHIP_CORE
@@ -819,6 +819,16 @@ config I2C_MICROCHIP_CORE
This driver can also be built as a module. If so, the module will be
called i2c-microchip-core.

2
target/linux/ramips/patches-6.6/810-uvc-add-iPassion-iP2970-support.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/media/usb/uvc/uvc_driver.c
+++ b/drivers/media/usb/uvc/uvc_driver.c
@@ -3249,6 +3249,18 @@ static const struct usb_device_id uvc_id
@@ -3271,6 +3271,18 @@ static const struct usb_device_id uvc_id
.bInterfaceSubClass = 1,
.bInterfaceProtocol = 0,
.driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) },

2
target/linux/ramips/patches-6.6/825-i2c-MIPS-adds-ralink-I2C-driver.patch
View File

@ -45,7 +45,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+};
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1021,6 +1021,11 @@ config I2C_RK3X
@@ -1023,6 +1023,11 @@ config I2C_RK3X
This driver can also be built as a module. If so, the module will
be called i2c-rk3x.

2
target/linux/realtek/patches-6.6/310-add-i2c-rtl9300-support.patch
View File

@ -17,7 +17,7 @@ Submitted-by: Birger Koblitz <git@birger-koblitz.de>
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1021,6 +1021,16 @@ config I2C_RK3X
@@ -1023,6 +1023,16 @@ config I2C_RK3X
This driver can also be built as a module. If so, the module will
be called i2c-rk3x.

26
target/linux/realtek/patches-6.6/801-gpio-regmap-Use-generic-request-free-ops.patch
View File

@ -1,26 +0,0 @@
From f21b15dfe254b51f80c552750eb20b1dc752507a Mon Sep 17 00:00:00 2001
From: Sander Vanheule <sander@svanheule.net>
Date: Mon, 30 Dec 2024 17:59:24 +0100
Subject: [PATCH] gpio: regmap: Use generic request/free ops
Set the gpiochip request and free ops to the generic implementations.
This way a user can provide a gpio-ranges property defined for a pinmux,
allowing pins to automatically be muxed to their GPIO function when
requested.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
drivers/gpio/gpio-regmap.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -270,6 +270,8 @@ struct gpio_regmap *gpio_regmap_register
chip->label = config->label ?: dev_name(config->parent);
chip->can_sleep = regmap_might_sleep(config->regmap);
+ chip->request = gpiochip_generic_request;
+ chip->free = gpiochip_generic_free;
chip->get = gpio_regmap_get;
if (gpio->reg_set_base && gpio->reg_clr_base)
chip->set = gpio_regmap_set_with_clear;

4
target/linux/rockchip/patches-6.6/035-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch
View File

@ -71,7 +71,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -998,6 +998,8 @@ struct dwc3_scratchpad_array {
@@ -1002,6 +1002,8 @@ struct dwc3_scratchpad_array {
* @bus_clk: clock for accessing the registers
* @ref_clk: reference clock
* @susp_clk: clock used when the SS phy is in low power (S3) state
@ -80,7 +80,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* @reset: reset control
* @regs: base address for our registers
* @regs_size: address space size
@@ -1170,6 +1172,8 @@ struct dwc3 {
@@ -1174,6 +1176,8 @@ struct dwc3 {
struct clk *bus_clk;
struct clk *ref_clk;
struct clk *susp_clk;

16
target/linux/starfive/patches-6.6/0109-usb-xhci-To-improve-performance-usb-using-lowmem-for.patch
View File

@ -160,7 +160,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
}
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -3667,7 +3667,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
@@ -3707,7 +3707,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
full_len = urb->transfer_buffer_length;
/* If we have scatter/gather list, we use it. */
@ -172,7 +172,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
addr = (u64) sg_dma_address(sg);
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -18,6 +18,8 @@
@@ -19,6 +19,8 @@
#include <linux/slab.h>
#include <linux/dmi.h>
#include <linux/dma-mapping.h>
@ -181,7 +181,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
#include "xhci.h"
#include "xhci-trace.h"
@@ -1285,6 +1287,55 @@ static void xhci_unmap_temp_buf(struct u
@@ -1286,6 +1288,55 @@ static void xhci_unmap_temp_buf(struct u
urb->transfer_buffer = NULL;
}
@ -237,7 +237,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
/*
* Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
* we'll copy the actual data into the TRB address register. This is limited to
@@ -1305,9 +1356,11 @@ static int xhci_map_urb_for_dma(struct u
@@ -1306,9 +1357,11 @@ static int xhci_map_urb_for_dma(struct u
if (xhci_urb_temp_buffer_required(hcd, urb))
return xhci_map_temp_buffer(hcd, urb);
}
@ -249,7 +249,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
{
struct xhci_hcd *xhci;
@@ -1320,8 +1373,10 @@ static void xhci_unmap_urb_for_dma(struc
@@ -1321,8 +1374,10 @@ static void xhci_unmap_urb_for_dma(struc
if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
xhci_unmap_temp_buf(hcd, urb);
@ -263,7 +263,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
/**
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1508,6 +1508,13 @@ struct xhci_hub {
@@ -1509,6 +1509,13 @@ struct xhci_hub {
u8 min_rev;
};
@ -277,7 +277,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
/* There is one xhci_hcd structure per controller */
struct xhci_hcd {
struct usb_hcd *main_hcd;
@@ -1662,6 +1669,8 @@ struct xhci_hcd {
@@ -1663,6 +1670,8 @@ struct xhci_hcd {
#define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)
#define XHCI_ETRON_HOST BIT_ULL(49)
@ -286,7 +286,7 @@ Signed-off-by: minda.chen <minda.chen@starfivetech.com>
unsigned int num_active_eps;
unsigned int limit_active_eps;
struct xhci_port *hw_ports;
@@ -1691,6 +1700,8 @@ struct xhci_hcd {
@@ -1692,6 +1701,8 @@ struct xhci_hcd {
struct list_head regset_list;
void *dbc;