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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2024-08-30 11:56:10 +08:00
commit b63dc53ff2
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GPG Key ID: 6850B6345C862176
40 changed files with 6573 additions and 137 deletions
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2
include/autotools.mk
View File

@ -44,7 +44,7 @@ define autoreconf
touch NEWS AUTHORS COPYING ABOUT-NLS ChangeLog; \
$(AM_TOOL_PATHS) \
LIBTOOLIZE='$(STAGING_DIR_HOST)/bin/libtoolize --install' \
$(STAGING_DIR_HOST)/bin/autoreconf -v -f -i -s \
$(STAGING_DIR_HOST)/bin/autoreconf -v -f -i \
$(if $(word 2,$(3)),--no-recursive) \
-B $(STAGING_DIR_HOST)/share/aclocal \
$(patsubst %,-I %,$(5)) \

4
include/cmake.mk
View File

@ -68,6 +68,8 @@ ifeq ($(HOST_USE_NINJA),1)
define Host/Uninstall/Default
+$(NINJA) -C $(HOST_CMAKE_BINARY_DIR) uninstall
endef
else
CMAKE_HOST_OPTIONS += -DCMAKE_GENERATOR="Unix Makefiles"
endif
ifeq ($(PKG_USE_NINJA),1)
@ -80,6 +82,8 @@ ifeq ($(PKG_USE_NINJA),1)
define Build/Install/Default
+DESTDIR="$(PKG_INSTALL_DIR)" $(NINJA) -C $(CMAKE_BINARY_DIR) install
endef
else
CMAKE_OPTIONS += -DCMAKE_GENERATOR="Unix Makefiles"
endif
define Build/Configure/Default

2
package/base-files/files/lib/preinit/80_mount_root
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@ -9,7 +9,7 @@ missing_lines() {
IFS=":"
while read line; do
set -- $line
grep -q "^$1:" "$file2" || echo "$*"
grep -q "^$1:" "$file2" || echo "$line"
done < "$file1"
IFS="$oIFS"
}

2
package/boot/uboot-envtools/files/ath79
View File

@ -89,6 +89,8 @@ zyxel,nbg6616)
aruba,ap-105|\
aruba,ap-115|\
aruba,ap-175|\
belkin,f9j1108-v2|\
belkin,f9k1115-v2|\
dongwon,dw02-412h-64m|\
dongwon,dw02-412h-128m|\
glinet,gl-ar300m-lite|\

24
package/boot/uboot-rockchip/Makefile
View File

@ -184,6 +184,20 @@ define U-Boot/radxa-cm3-io-rk3566
radxa_cm3-io
endef
define U-Boot/radxa-zero-3-rk3566
$(U-Boot/rk3566/Default)
NAME:=ZERO 3E/3W
BUILD_DEVICES:= \
radxa_zero-3e \
radxa_zero-3w
endef
define U-Boot/rock-3c-rk3566
$(U-Boot/rk3566/Default)
NAME:=ROCK 3C
BUILD_DEVICES:= \
radxa_rock-3c
endef
# RK3568 boards
@ -266,6 +280,13 @@ define U-Boot/rock-3a-rk3568
radxa_rock-3a
endef
define U-Boot/rock-3b-rk3568
$(U-Boot/rk3568/Default)
NAME:=ROCK 3B
BUILD_DEVICES:= \
radxa_rock-3b
endef
define U-Boot/sige3-rk3568
$(U-Boot/rk3568/Default)
NAME:=Sige3
@ -360,6 +381,8 @@ UBOOT_TARGETS := \
rock-pi-e-v3-rk3328 \
rock64-rk3328 \
radxa-cm3-io-rk3566 \
radxa-zero-3-rk3566 \
rock-3c-rk3566 \
bpi-r2-pro-rk3568 \
fastrhino-r66s-rk3568 \
fastrhino-r68s-rk3568 \
@ -370,6 +393,7 @@ UBOOT_TARGETS := \
radxa-e25-rk3568 \
roc-pc-rk3568 \
rock-3a-rk3568 \
rock-3b-rk3568 \
sige3-rk3568 \
nanopc-t6-rk3588 \
orangepi-5-plus-rk3588 \

2964
package/boot/uboot-rockchip/patches/000-backport-upstream-dts-sync.patch Normal file
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File diff suppressed because it is too large Load Diff

0
package/boot/uboot-rockchip/patches/000-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch → package/boot/uboot-rockchip/patches/001-rockchip-add-support-for-Radxa-ROCK-Pi-E-v3.0.patch
View File

178
package/boot/uboot-rockchip/patches/002-board-rockchip-add-Radxa-ROCK-3-Model-C.patch Normal file
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@ -0,0 +1,178 @@
From e6e82ce24d4e9d20c232db2a95b2d10faf8f2bcf Mon Sep 17 00:00:00 2001
From: Maxim Moskalets <maximmosk4@gmail.com>
Date: Thu, 8 Aug 2024 22:37:10 +0300
Subject: [PATCH] board: rockchip: add Radxa ROCK 3 Model C
Based on rock-3a-rk3568_defconfig.
Tested on v1.31 revision.
Board Specifications:
- Rockchip RK3566
- 1/2/4GB LPDDR4 2112MT/s
- eMMC socket
- uSD card slot
- M.2 2230 Connector
- GbE LAN with POE
- 3.5mm jack with mic
- HDMI 2.0, MIPI DSI/CSI
- USB 3.0 Host, USB 2.0 Host/OTG
- 40-pin GPIO expansion ports
Signed-off-by: Maxim Moskalets <maximmosk4@gmail.com>
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/rk3566-rock-3c-u-boot.dtsi | 18 +++++
board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
configs/rock-3c-rk3566_defconfig | 97 +++++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 123 insertions(+)
create mode 100644 arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
create mode 100644 configs/rock-3c-rk3566_defconfig
--- /dev/null
+++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
+
+/ {
+ leds {
+ led-0 {
+ default-state = "on";
+ };
+ };
+};
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -69,3 +69,10 @@ S: Maintained
F: configs/rock-3a-rk3568_defconfig
F: arch/arm/dts/rk3568-rock-3a.dts
F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+
+ROCK-3C
+M: Jonas Karlman <jonas@kwiboo.se>
+M: Maxim Moskalets <maximmosk4@gmail.com>
+S: Maintained
+F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
+F: configs/rock-3c-rk3566_defconfig
--- /dev/null
+++ b/configs/rock-3c-rk3566_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -106,6 +106,7 @@ List of mainline supported Rockchip boar
- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
- Powkiddy X55 (powkiddy-x55-rk3566)
- Radxa CM3 IO Board (radxa-cm3-io-rk3566)
+ - Radxa ROCK 3C (rock-3c-rk3566)
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)

67
package/boot/uboot-rockchip/patches/003-dm-adc-Add-SPL_ADC-Kconfig-symbol-for-use-of-ADC-in-.patch Normal file
View File

@ -0,0 +1,67 @@
From 232af1e58a977f3857074d3aba3709c860bd8058 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 2 Aug 2024 22:12:22 +0000
Subject: [PATCH] dm: adc: Add SPL_ADC Kconfig symbol for use of ADC in SPL
What model of Radxa ZERO 3W/3E board can be identified using ADC at
runtime, add a Kconfig symbol to allow use of ADC in SPL.
This will be used to identify board model in SPL to allow loading
correct FIT configuration and FDT for U-Boot proper at SPL phase.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/Makefile | 2 +-
drivers/adc/Kconfig | 5 +++++
drivers/adc/Makefile | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_TPL_)ADC) += adc/
obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/
obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
@@ -81,7 +82,6 @@ endif
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
-obj-y += adc/
obj-y += ata/
obj-$(CONFIG_DM_DEMO) += demo/
obj-y += block/
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -1,5 +1,6 @@
config ADC
bool "Enable ADC drivers using Driver Model"
+ depends on DM
help
This enables ADC API for drivers, which allows driving ADC features
by single and multi-channel methods for:
@@ -11,6 +12,10 @@ config ADC
- support supply's phandle with auto-enable
- supply polarity setting in fdt
+config SPL_ADC
+ bool "Enable ADC drivers using Driver Model in SPL"
+ depends on SPL_DM
+
config ADC_EXYNOS
bool "Enable Exynos 54xx ADC driver"
depends on ADC
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -4,7 +4,7 @@
# Przemyslaw Marczak <p.marczak@samsung.com>
#
-obj-$(CONFIG_ADC) += adc-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)ADC) += adc-uclass.o
obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o

295
package/boot/uboot-rockchip/patches/004-board-rockchip-Add-Radxa-ZERO-3W-3E.patch Normal file
View File

@ -0,0 +1,295 @@
From 5d199ad9a6bb43dbf43efe45ec37002c4ae305a0 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 2 Aug 2024 22:12:23 +0000
Subject: [PATCH] board: rockchip: Add Radxa ZERO 3W/3E
The Radxa ZERO 3W/3E is an ultra-small, high-performance single board
computer based on the Rockchip RK3566, with a compact form factor and
rich interfaces.
Implement rk_board_late_init() to set correct fdtfile env var and
board_fit_config_name_match() to load correct FIT config based on what
board is detected at runtime so a single board target can be used for
both board models.
Features tested on a ZERO 3W 8GB v1.11:
- SD-card boot
- eMMC boot
- USB gadget
- USB host
Features tested on a ZERO 3E 4GB v1.2:
- SD-card boot
- Ethernet
- USB gadget
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi | 15 ++++
arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi | 15 ++++
arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++
board/radxa/zero3-rk3566/Kconfig | 12 +++
board/radxa/zero3-rk3566/MAINTAINERS | 6 ++
board/radxa/zero3-rk3566/Makefile | 3 +
board/radxa/zero3-rk3566/zero3-rk3566.c | 59 +++++++++++++
configs/radxa-zero-3-rk3566_defconfig | 85 +++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
9 files changed, 202 insertions(+)
create mode 100644 arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
create mode 100644 board/radxa/zero3-rk3566/Kconfig
create mode 100644 board/radxa/zero3-rk3566/MAINTAINERS
create mode 100644 board/radxa/zero3-rk3566/Makefile
create mode 100644 board/radxa/zero3-rk3566/zero3-rk3566.c
create mode 100644 configs/radxa-zero-3-rk3566_defconfig
--- /dev/null
+++ b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&saradc {
+ bootph-pre-ram;
+};
+
+&usb_host0_xhci {
+ dr_mode = "otg";
+};
+
+&vcca_1v8 {
+ bootph-pre-ram;
+};
--- /dev/null
+++ b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&saradc {
+ bootph-pre-ram;
+};
+
+&usb_host0_xhci {
+ dr_mode = "otg";
+};
+
+&vcca_1v8 {
+ bootph-pre-ram;
+};
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -32,6 +32,11 @@ config TARGET_QUARTZ64_RK3566
help
Pine64 Quartz64 single board computer with a RK3566 SoC.
+config TARGET_RADXA_ZERO_3_RK3566
+ bool "Radxa ZERO 3W/3E"
+ help
+ Radxa ZERO 3W/3E single board computers with a RK3566 SoC.
+
endchoice
config ROCKCHIP_BOOT_MODE_REG
@@ -54,5 +59,6 @@ source "board/anbernic/rgxx3_rk3566/Kcon
source "board/hardkernel/odroid_m1/Kconfig"
source "board/pine64/quartz64_rk3566/Kconfig"
source "board/powkiddy/x55/Kconfig"
+source "board/radxa/zero3-rk3566/Kconfig"
endif
--- /dev/null
+++ b/board/radxa/zero3-rk3566/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RADXA_ZERO_3_RK3566
+
+config SYS_BOARD
+ default "zero3-rk3566"
+
+config SYS_VENDOR
+ default "radxa"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3568"
+
+endif
--- /dev/null
+++ b/board/radxa/zero3-rk3566/MAINTAINERS
@@ -0,0 +1,6 @@
+RADXA-ZERO-3-RK3566
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: board/radxa/zero3-rk3566
+F: configs/radxa-zero-3-rk3566_defconfig
+F: arch/arm/dts/rk3566-radxa-zero-3*
--- /dev/null
+++ b/board/radxa/zero3-rk3566/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += zero3-rk3566.o
--- /dev/null
+++ b/board/radxa/zero3-rk3566/zero3-rk3566.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <adc.h>
+#include <env.h>
+
+#define HW_ID_CHANNEL 1
+
+struct board_model {
+ unsigned int low;
+ unsigned int high;
+ const char *fdtfile;
+};
+
+static const struct board_model board_models[] = {
+ { 230, 270, "rockchip/rk3566-radxa-zero-3w.dtb" },
+ { 400, 450, "rockchip/rk3566-radxa-zero-3e.dtb" },
+};
+
+static const struct board_model *get_board_model(void)
+{
+ unsigned int val;
+ int i, ret;
+
+ ret = adc_channel_single_shot("saradc@fe720000", HW_ID_CHANNEL, &val);
+ if (ret)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(board_models); i++) {
+ unsigned int min = board_models[i].low;
+ unsigned int max = board_models[i].high;
+
+ if (min <= val && val <= max)
+ return &board_models[i];
+ }
+
+ return NULL;
+}
+
+int rk_board_late_init(void)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model)
+ env_set("fdtfile", model->fdtfile);
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ const struct board_model *model = get_board_model();
+
+ if (model && !strcmp(name, model->fdtfile))
+ return 0;
+
+ return -EINVAL;
+}
--- /dev/null
+++ b/configs/radxa-zero-3-rk3566_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-radxa-zero-3w"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_RADXA_ZERO_3_RK3566=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-zero-3w.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="rockchip/rk3566-radxa-zero-3w rockchip/rk3566-radxa-zero-3e"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_ADC=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -107,6 +107,7 @@ List of mainline supported Rockchip boar
- Powkiddy X55 (powkiddy-x55-rk3566)
- Radxa CM3 IO Board (radxa-cm3-io-rk3566)
- Radxa ROCK 3C (rock-3c-rk3566)
+ - Radxa ZERO 3W/3E (radxa-zero-3-rk3566)
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)

179
package/boot/uboot-rockchip/patches/005-board-rockchip-Add-Radxa-ROCK-3B.patch Normal file
View File

@ -0,0 +1,179 @@
From e20d57ae7e0c28f2d770a7d18c1501d332e8766a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 31 Jul 2024 07:28:54 +0000
Subject: [PATCH] board: rockchip: Add Radxa ROCK 3B
The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form
factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community
version based on the RK3568 SoC and an industrial version based on the
RK3568J SoC.
Features tested on ROCK 3B 8GB v1.51 (both variants):
- SD-card boot
- eMMC boot
- SPI Flash boot
- Ethernet
- PCIe/NVMe
- USB gadget
- USB host
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/rk3568-rock-3b-u-boot.dtsi | 15 ++++
board/rockchip/evb_rk3568/MAINTAINERS | 6 ++
configs/rock-3b-rk3568_defconfig | 100 ++++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 3 +-
4 files changed, 123 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
create mode 100644 configs/rock-3b-rk3568_defconfig
--- /dev/null
+++ b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&sdhci {
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -70,6 +70,12 @@ F: configs/rock-3a-rk3568_defconfig
F: arch/arm/dts/rk3568-rock-3a.dts
F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+ROCK-3B
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/rock-3b-rk3568_defconfig
+F: arch/arm/dts/rk3568-rock-3b*
+
ROCK-3C
M: Jonas Karlman <jonas@kwiboo.se>
M: Maxim Moskalets <maximmosk4@gmail.com>
--- /dev/null
+++ b/configs/rock-3b-rk3568_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3b"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3b.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -118,7 +118,8 @@ List of mainline supported Rockchip boar
- Generic RK3566/RK3568 (generic-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
- Radxa E25 Carrier Board (radxa-e25-rk3568)
- - Radxa ROCK 3 Model A (rock-3a-rk3568)
+ - Radxa ROCK 3A (rock-3a-rk3568)
+ - Radxa ROCK 3B (rock-3b-rk3568)
* rk3588
- Rockchip EVB (evb-rk3588)

57
package/boot/uboot-rockchip/patches/100-spl-Add-Kconfig-options-for-ADC.patch
View File

@ -1,57 +0,0 @@
From: Chris Morgan <macroalpha82@gmail.com>
To: u-boot@lists.denx.de
Cc: andre.przywara@arm.com, kever.yang@rock-chips.com,
philipp.tomsich@vrull.eu, sjg@chromium.org, jagan@edgeble.ai,
jonas@kwiboo.se, Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH V4 2/7] spl: Add Kconfig options for ADC
Date: Tue, 2 Jan 2024 09:46:49 -0600 [thread overview]
Message-ID: <20240102154654.191055-3-macroalpha82@gmail.com> (raw)
In-Reply-To: <20240102154654.191055-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add kconfig options to enable ADC in SPL
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
common/spl/Kconfig | 7 +++++++
drivers/Makefile | 1 +
drivers/adc/Makefile | 2 +-
3 files changed, 9 insertions(+), 1 deletion(-)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -595,6 +595,13 @@ config SPL_FIT_IMAGE_TINY
ensure this information is available to the next image
invoked).
+config SPL_ADC
+ bool "Support ADC drivers"
+ help
+ Enable ADC drivers in SPL. These drivers can allow the reading of
+ analog values from one or more channels. Enable this option to
+ build the drivers in drivers/adc as part of an SPL build.
+
config SPL_CACHE
bool "Support CACHE drivers"
help
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_)ADC) += adc/
obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/
obj-$(CONFIG_$(SPL_TPL_)BLK) += block/
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -4,7 +4,7 @@
# Przemyslaw Marczak <p.marczak@samsung.com>
#
-obj-$(CONFIG_ADC) += adc-uclass.o
+obj-$(CONFIG_$(SPL_)ADC) += adc-uclass.o
obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o

3
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-armsom-sige3.dts
View File

@ -96,8 +96,7 @@
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &clk32k_out1>;
post-power-on-delay-ms = <100>;
power-off-delay-us = <5000000>;
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
};

30
package/firmware/linux-firmware/mellanox.mk
View File

@ -7,3 +7,33 @@ define Package/mlxsw_spectrum-firmware/install
endef
$(eval $(call BuildPackage,mlxsw_spectrum-firmware))
Package/mlxsw_spectrum2-firmware = $(call Package/firmware-default,Mellanox Spectrum-2 firmware)
define Package/mlxsw_spectrum2-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mellanox
$(CP) \
$(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum2-*.mfa2 \
$(1)/lib/firmware/mellanox
endef
$(eval $(call BuildPackage,mlxsw_spectrum2-firmware))
Package/mlxsw_spectrum3-firmware = $(call Package/firmware-default,Mellanox Spectrum-3 firmware)
define Package/mlxsw_spectrum3-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mellanox
$(CP) \
$(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum3-*.mfa2 \
$(1)/lib/firmware/mellanox
endef
$(eval $(call BuildPackage,mlxsw_spectrum3-firmware))
Package/mlxsw_spectrum4-firmware = $(call Package/firmware-default,Mellanox Spectrum-4 firmware)
define Package/mlxsw_spectrum4-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mellanox
$(CP) \
$(PKG_BUILD_DIR)/mellanox/mlxsw_spectrum4-*.mfa2 \
$(1)/lib/firmware/mellanox
endef
$(eval $(call BuildPackage,mlxsw_spectrum4-firmware))

3
package/kernel/linux/modules/leds.mk
View File

@ -150,8 +150,9 @@ $(eval $(call KernelPackage,leds-apu))
define KernelPackage/leds-mlxcpld
SUBMENU:=$(LEDS_MENU)
TITLE:=LED support for the Mellanox boards
FILES:=$(LINUX_DIR)/drivers/leds/leds-mlxcpld.ko
DEPENDS:=@TARGET_x86
KCONFIG:=CONFIG_LEDS_MLXCPLD
FILES:=$(LINUX_DIR)/drivers/leds/leds-mlxcpld.ko
AUTOLOAD:=$(call AutoProbe,leds-mlxcpld)
endef

16
package/kernel/linux/modules/netdevices.mk
View File

@ -1481,7 +1481,7 @@ $(eval $(call KernelPackage,mlxfw))
define KernelPackage/mlxsw-core
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Mellanox Technologies Switch ASICs support
DEPENDS:=+kmod-mlxfw +kmod-hwmon-core
DEPENDS:=@TARGET_x86_64 +kmod-mlxfw +kmod-hwmon-core
FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlxsw/mlxsw_core.ko
KCONFIG:= \
CONFIG_MLXSW_CORE \
@ -1516,7 +1516,7 @@ $(eval $(call KernelPackage,mlxsw-i2c))
define KernelPackage/mlxsw-minimal
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Mellanox Technologies minimal I2C support
DEPENDS:=+kmod-mlxsw-core +kmod-mlxsw-i2c
DEPENDS:=+kmod-mlxsw-i2c
FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlxsw/mlxsw_minimal.ko
KCONFIG:=CONFIG_MLXSW_MINIMAL
AUTOLOAD:=$(call AutoProbe,mlxsw_minimal)
@ -1550,20 +1550,14 @@ define KernelPackage/mlxsw-spectrum
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Mellanox Technologies Spectrum family support
DEPENDS:= \
+kmod-mlxsw-core +kmod-mlxsw-pci +kmod-lib-objagg +kmod-lib-parman \
+kmod-mlxsw-pci +kmod-lib-objagg +kmod-lib-parman \
+kmod-ip6-tunnel +kmod-ptp +kmod-sched-act-sample +kmod-vxlan
FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlxsw/mlxsw_spectrum.ko
KCONFIG:= \
CONFIG_MLXSW_SPECTRUM \
CONFIG_NET_SWITCHDEV=y \
CONFIG_MLXSW_SPECTRUM_DCB=y \
CONFIG_DCB=y \
CONFIG_AMD_XGBE_DCB=n \
CONFIG_IXGBE_DCB=n \
CONFIG_I40E_DCB=n \
CONFIG_QLCNIC_DCB=n \
CONFIG_FSL_DPAA2_ETH_DCB=n \
CONFIG_FSL_DPAA2_SWITCH=n
CONFIG_NET_SWITCHDEV=y \
CONFIG_DCB=y
AUTOLOAD:=$(call AutoProbe,mlxsw_spectrum)
endef

17
target/linux/ath79/dts/qca955x_elecom_wab.dtsi
View File

@ -8,6 +8,7 @@
/ {
aliases {
label-mac-device = &eth0;
led-boot = &led_status;
led-failsafe = &led_status;
led-upgrade = &led_status;
@ -107,6 +108,9 @@
phy-mode = "rgmii-rxid";
pll-data = <0xae000000 0x80000101 0x80001313>;
nvmem-cells = <&macaddr_uboot_ethaddr 0>;
nvmem-cell-names = "mac-address";
gmac-config {
device = <&gmac>;
@ -144,8 +148,8 @@
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&cal_art_5000>;
nvmem-cell-names = "calibration";
nvmem-cells = <&cal_art_5000>, <&macaddr_uboot_ethaddr 1>;
nvmem-cell-names = "calibration", "mac-address";
};
};
@ -169,9 +173,14 @@
};
partition@40000 {
compatible = "u-boot,env";
label = "u-boot-env";
reg = <0x40000 0x10000>;
read-only;
macaddr_uboot_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
};
};
partition@50000 {
@ -252,6 +261,6 @@
&wmac {
status = "okay";
nvmem-cells = <&cal_art_1000>;
nvmem-cell-names = "calibration";
nvmem-cells = <&cal_art_1000>, <&macaddr_uboot_ethaddr 0>;
nvmem-cell-names = "calibration", "mac-address";
};

7
target/linux/ath79/dts/qca9561_nec_wf1200cr.dts
View File

@ -114,6 +114,10 @@
#address-cells = <1>;
#size-cells = <1>;
cal_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
precal_art_5000: pre-calibration@5000 {
reg = <0x5000 0x2f20>;
};
@ -177,5 +181,6 @@
&wmac {
status = "okay";
qca,no-eeprom;
nvmem-cells = <&cal_art_1000>;
nvmem-cell-names = "calibration";
};

7
target/linux/ath79/dts/qca9563_nec_wg1200cr.dts
View File

@ -129,6 +129,10 @@
#address-cells = <1>;
#size-cells = <1>;
cal_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
precal_art_5000: pre-calibration@5000 {
reg = <0x5000 0x2f20>;
};
@ -178,5 +182,6 @@
&wmac {
status = "okay";
qca,no-eeprom;
nvmem-cells = <&cal_art_1000>;
nvmem-cell-names = "calibration";
};

29
target/linux/ath79/dts/qca9563_nec_wg800hp.dts
View File

@ -142,6 +142,24 @@
#address-cells = <1>;
#size-cells = <1>;
macaddr_board_data_280: macaddr@280 {
compatible = "mac-base";
reg = <0x280 0x11>;
#nvmem-cell-cells = <1>;
};
macaddr_board_data_480: macaddr@480 {
compatible = "mac-base";
reg = <0x480 0x11>;
#nvmem-cell-cells = <1>;
};
macaddr_board_data_680: macaddr@680 {
compatible = "mac-base";
reg = <0x680 0x11>;
#nvmem-cell-cells = <1>;
};
macaddr_board_data_880: macaddr@880 {
compatible = "mac-base";
reg = <0x880 0x11>;
@ -160,6 +178,10 @@
#address-cells = <1>;
#size-cells = <1>;
cal_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
};
cal_art_5000: calibration@5000 {
reg = <0x5000 0x844>;
};
@ -191,6 +213,9 @@
phy-mode = "sgmii";
phy-handle = <&phy0>;
nvmem-cells = <&macaddr_board_data_280 0>;
nvmem-cell-names = "mac-address";
};
&pcie {
@ -206,5 +231,7 @@
&wmac {
status = "okay";
qca,no-eeprom;
nvmem-cells = <&macaddr_board_data_680 0>, <&cal_art_1000>;
nvmem-cell-names = "mac-address", "calibration";
};

4
target/linux/ath79/generic/base-files/etc/board.d/02_network
View File

@ -712,9 +712,6 @@ ath79_setup_macs()
lan_mac=$(mtd_get_mac_ascii devdata "lanmac")
wan_mac=$(mtd_get_mac_ascii devdata "wanmac")
;;
elecom,wab-i1750-ps|\
elecom,wab-s1167-ps|\
elecom,wab-s600-ps|\
engenius,ecb1200|\
engenius,ecb1750)
lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
@ -784,7 +781,6 @@ ath79_setup_macs()
label_mac=$wan_mac
;;
nec,wg800hp)
lan_mac=$(mtd_get_mac_text board_data 0x280)
wan_mac=$(mtd_get_mac_text board_data 0x480)
label_mac=$wan_mac
;;

6
target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
View File

@ -30,8 +30,6 @@ case "$FIRMWARE" in
dlink,dir-842-c1|\
dlink,dir-842-c2|\
dlink,dir-842-c3|\
nec,wf1200cr|\
nec,wg1200cr|\
wd,mynet-n600|\
wd,mynet-n750)
caldata_extract "art" 0x1000 0x440
@ -63,10 +61,6 @@ case "$FIRMWARE" in
caldata_extract "art" 0x1000 0x440
ath9k_patch_mac $(mtd_get_mac_ascii u-boot-env mac_addr)
;;
nec,wg800hp)
caldata_extract "art" 0x1000 0x440
ath9k_patch_mac $(mtd_get_mac_text board_data 0x680)
;;
qihoo,c301)
caldata_extract "radiocfg" 0x1000 0x440
ath9k_patch_mac $(mtd_get_mac_ascii devdata "wlan24mac")

19
target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
View File

@ -42,16 +42,6 @@ case "$board" in
[ "$PHYNBR" -eq 1 ] && \
mtd_get_mac_ascii bdcfg "wlanmac" > /sys${DEVPATH}/macaddress
;;
elecom,wab-i1750-ps|\
elecom,wab-s1167-ps|\
elecom,wab-s600-ps)
# set the 5G MAC address (= ethaddr + 1)
[ "$PHYNBR" -eq 0 ] && \
macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress
# set the 2.4G MAC address (= ethaddr)
[ "$PHYNBR" -eq 1 ] && \
mtd_get_mac_ascii u-boot-env "ethaddr" > /sys${DEVPATH}/macaddress
;;
engenius,ecb1200|\
engenius,ecb1750)
[ "$PHYNBR" -eq 0 ] && \
@ -88,12 +78,17 @@ case "$board" in
[ "$PHYNBR" -eq 1 ] && \
macaddr_add "$(mtd_get_mac_ascii u-boot-env ethaddr)" 1 > /sys${DEVPATH}/macaddress
;;
nec,wf1200cr|\
nec,wg1200cr|\
qihoo,c301)
[ "$PHYNBR" -eq 0 ] && \
mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress
;;
nec,wf1200cr|\
nec,wg1200cr|\
[ "$PHYNBR" -eq 0 ] && \
mtd_get_mac_ascii devdata wlan5mac > /sys${DEVPATH}/macaddress
[ "$PHYNBR" -eq 1 ] && \
mtd_get_mac_ascii devdata wlan24mac > /sys${DEVPATH}/macaddress
;;
phicomm,k2t)
[ "$PHYNBR" -eq 0 ] && \
k2t_get_mac "5g_mac" > /sys${DEVPATH}/macaddress

4
target/linux/generic/config-6.6
View File

@ -179,6 +179,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_AMD_MEM_ENCRYPT is not set
# CONFIG_AMD_PHY is not set
# CONFIG_AMD_XGBE is not set
# CONFIG_AMD_XGBE_DCB is not set
# CONFIG_AMD_XGBE_HAVE_ECC is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_AMILO_RFKILL is not set
@ -2530,6 +2531,7 @@ CONFIG_HZ_100=y
# CONFIG_I3C is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_I40E_DCB is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_I82092 is not set
# CONFIG_I82365 is not set
@ -2893,6 +2895,7 @@ CONFIG_ISDN=y
# CONFIG_IWLWIFI is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_IXGBE_DCB is not set
# CONFIG_JAILHOUSE_GUEST is not set
# CONFIG_JBD2_DEBUG is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
@ -4825,6 +4828,7 @@ CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_QFMT_V1 is not set
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
# CONFIG_QLCNIC_DCB is not set
# CONFIG_QLGE is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set

5
target/linux/generic/files/drivers/net/phy/rtl8366_smi.h
View File

@ -30,7 +30,9 @@ typedef enum rtl8367b_chip_e {
RTL8367B_CHIP_RTL8367R_VB, /* chip with exception in extif assignment */
/* Family C */
RTL8367B_CHIP_RTL8367RB_VB,
RTL8367B_CHIP_RTL8367S
RTL8367B_CHIP_RTL8367S,
/* Family D */
RTL8367B_CHIP_RTL8367S_VB /* chip with exception in extif assignment */
} rtl8367b_chip_t;
struct rtl8366_mib_counter {
@ -76,6 +78,7 @@ struct rtl8366_smi {
u32 phy_id;
rtl8367b_chip_t rtl8367b_chip;
struct mii_bus *ext_mbus;
struct rtl8366_vlan_mc *emu_vlanmc;
};
struct rtl8366_vlan_mc {

215
target/linux/generic/files/drivers/net/phy/rtl8367b.c
View File

@ -1,6 +1,7 @@
/*
* Platform driver for Realtek RTL8367B family chips, i.e. RTL8367RB and RTL8367R-VB
* extended with support for RTL8367C family chips, i.e. RTL8367RB-VB and RTL8367S
* extended with support for RTL8367D family chips, i.e. RTL8367S-VB
*
* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
*
@ -267,6 +268,37 @@ struct rtl8367b_initval {
#define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */
#define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */
#define RTL8367D_PORT_STATUS_REG(_p) (0x12d0 + (_p))
#define RTL8367D_PORT_STATUS_SPEED1_MASK 0x3000
#define RTL8367D_PORT_STATUS_SPEED1_SHIFT 10 /*12-2*/
#define RTL8367D_REG_MAC0_FORCE_SELECT 0x12c0
#define RTL8367D_REG_MAC0_FORCE_SELECT_EN 0x12c8
#define RTL8367D_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p))
#define RTL8367D_VLAN_PVID_CTRL_MASK 0xfff
#define RTL8367D_VLAN_PVID_CTRL_SHIFT(_p) 0
#define RTL8367D_FIDMAX 3
#define RTL8367D_FID_MASK 3
#define RTL8367D_TA_VLAN1_FID_SHIFT 0
#define RTL8367D_TA_VLAN1_FID_MASK RTL8367D_FID_MASK
#define RTL8367D_VID_MASK 0xfff
#define RTL8367D_TA_VLAN_VID_MASK RTL8367D_VID_MASK
#define RTL8367D_REG_EXT_TXC_DLY 0x13f9
#define RTL8367D_EXT1_RGMII_TX_DLY_MASK 0x38
#define RTL8367D_REG_TOP_CON0 0x1d70
#define RTL8367D_MAC7_SEL_EXT1_MASK 0x2000
#define RTL8367D_MAC4_SEL_EXT1_MASK 0x1000
#define RTL8367D_REG_SDS1_MISC0 0x1d78
#define RTL8367D_SDS1_MODE_MASK 0x1f
#define RTL8367D_PORT_SDS_MODE_DISABLE 0x1f
static struct rtl8366_mib_counter
rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
{0, 0, 4, "ifInOctets" },
@ -528,8 +560,13 @@ static int rtl8367b_init_regs(struct rtl8366_smi *smi)
break;
case RTL8367B_CHIP_RTL8367RB_VB:
case RTL8367B_CHIP_RTL8367S:
case RTL8367B_CHIP_RTL8367S_VB:
initvals = rtl8367c_initvals;
count = ARRAY_SIZE(rtl8367c_initvals);
if ((smi->rtl8367b_chip == RTL8367B_CHIP_RTL8367S_VB) && (smi->emu_vlanmc == NULL)) {
smi->emu_vlanmc = kzalloc(sizeof(struct rtl8366_vlan_mc) * smi->num_vlan_mc, GFP_KERNEL);
dev_info(smi->parent, "alloc vlan mc emulator");
}
break;
default:
return -ENODEV;
@ -567,6 +604,7 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
enum rtl8367_extif_mode mode)
{
int err;
u32 data;
/* set port mode */
switch (mode) {
@ -586,6 +624,15 @@ static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
RTL8367B_DEBUG1_DP_MASK(id),
(7 << RTL8367B_DEBUG1_DN_SHIFT(id)) |
(7 << RTL8367B_DEBUG1_DP_SHIFT(id)));
if ((smi->rtl8367b_chip == RTL8367B_CHIP_RTL8367S_VB) && (id == 1)) {
REG_RMW(smi, RTL8367D_REG_EXT_TXC_DLY, RTL8367D_EXT1_RGMII_TX_DLY_MASK, 0);
/* Configure RGMII/MII mux to port 7 if UTP_PORT4 is not RGMII mode */
REG_RD(smi, RTL8367D_REG_TOP_CON0, &data);
data &= RTL8367D_MAC4_SEL_EXT1_MASK;
if (data == 0)
REG_RMW(smi, RTL8367D_REG_TOP_CON0, RTL8367D_MAC7_SEL_EXT1_MASK, RTL8367D_MAC7_SEL_EXT1_MASK);
REG_RMW(smi, RTL8367D_REG_SDS1_MISC0, RTL8367D_SDS1_MODE_MASK, RTL8367D_PORT_SDS_MODE_DISABLE);
}
} else {
REG_RMW(smi, RTL8367B_CHIP_DEBUG2_REG,
RTL8367B_DEBUG2_DRI_EXT2 |
@ -644,23 +691,31 @@ static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
u32 val;
int err;
mask = (RTL8367B_DI_FORCE_MODE |
RTL8367B_DI_FORCE_NWAY |
RTL8367B_DI_FORCE_TXPAUSE |
RTL8367B_DI_FORCE_RXPAUSE |
RTL8367B_DI_FORCE_LINK |
RTL8367B_DI_FORCE_DUPLEX |
RTL8367B_DI_FORCE_SPEED_MASK);
val = pa->speed;
val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
val = pa->speed & RTL8367B_DI_FORCE_SPEED_MASK;
val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */
val |= (pa->speed << RTL8367D_PORT_STATUS_SPEED1_SHIFT) & RTL8367D_PORT_STATUS_SPEED1_MASK;
if (smi->cpu_port != UINT_MAX) {
REG_WR(smi, RTL8367D_REG_MAC0_FORCE_SELECT + smi->cpu_port, val);
REG_WR(smi, RTL8367D_REG_MAC0_FORCE_SELECT_EN + smi->cpu_port, pa->force_mode ? 0xffff : 0x0000);
}
} else {
val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
mask = (RTL8367B_DI_FORCE_MODE |
RTL8367B_DI_FORCE_NWAY |
RTL8367B_DI_FORCE_TXPAUSE |
RTL8367B_DI_FORCE_RXPAUSE |
RTL8367B_DI_FORCE_LINK |
RTL8367B_DI_FORCE_DUPLEX |
RTL8367B_DI_FORCE_SPEED_MASK);
REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
}
return 0;
}
@ -741,6 +796,14 @@ static int rtl8367b_extif_init_of(struct rtl8366_smi *smi,
err = -EINVAL;
goto err_init;
}
} else if (smi->rtl8367b_chip == RTL8367B_CHIP_RTL8367S_VB) { /* for the RTL8367S-VB chip, cpu_port 7 corresponds to extif1, cpu_port 6 corresponds to extif0 */
if (cpu_port != RTL8367B_CPU_PORT_NUM) {
id = cpu_port - RTL8367B_CPU_PORT_NUM - 1;
} else {
dev_err(smi->parent, "wrong cpu_port %u in %s property\n", cpu_port, name);
err = -EINVAL;
goto err_init;
}
} else {
id = cpu_port - RTL8367B_CPU_PORT_NUM;
}
@ -911,8 +974,12 @@ static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
RTL8367B_TA_VLAN0_MEMBER_MASK;
vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
RTL8367B_TA_VLAN0_UNTAG_MASK;
vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
RTL8367B_TA_VLAN1_FID_MASK;
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */
vlan4k->fid = (data[1] >> RTL8367D_TA_VLAN1_FID_SHIFT) &
RTL8367D_TA_VLAN1_FID_MASK;
else
vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
RTL8367B_TA_VLAN1_FID_MASK;
return 0;
}
@ -927,7 +994,7 @@ static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
vlan4k->untag > RTL8367B_UNTAG_MASK ||
vlan4k->fid > RTL8367B_FIDMAX)
vlan4k->fid > ((smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) ? RTL8367D_FIDMAX : RTL8367B_FIDMAX))
return -EINVAL;
memset(data, 0, sizeof(data));
@ -936,15 +1003,24 @@ static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
RTL8367B_TA_VLAN0_MEMBER_SHIFT;
data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
RTL8367B_TA_VLAN0_UNTAG_SHIFT;
data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
RTL8367B_TA_VLAN1_FID_SHIFT;
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */
data[1] = ((vlan4k->fid & RTL8367D_TA_VLAN1_FID_MASK) <<
RTL8367D_TA_VLAN1_FID_SHIFT) | 12; /* ivl_svl - BIT(3), svlan_chek_ivl_svl - BIT(2) */
else
data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
RTL8367B_TA_VLAN1_FID_SHIFT;
for (i = 0; i < ARRAY_SIZE(data); i++)
REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
/* write VID */
REG_WR(smi, RTL8367B_TA_ADDR_REG,
vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */
REG_WR(smi, RTL8367B_TA_ADDR_REG,
vlan4k->vid & RTL8367D_TA_VLAN_VID_MASK);
else
REG_WR(smi, RTL8367B_TA_ADDR_REG,
vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
/* write table access control word */
REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
@ -964,6 +1040,14 @@ static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
if (index >= RTL8367B_NUM_VLANS)
return -EINVAL;
if (smi->emu_vlanmc) { /* use vlan mc emulation */
vlanmc->vid = smi->emu_vlanmc[index].vid;
vlanmc->member = smi->emu_vlanmc[index].member;
vlanmc->fid = smi->emu_vlanmc[index].fid;
vlanmc->untag = smi->emu_vlanmc[index].untag;
return 0;
}
for (i = 0; i < ARRAY_SIZE(data); i++)
REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
@ -989,9 +1073,17 @@ static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
vlanmc->priority > RTL8367B_PRIORITYMAX ||
vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
vlanmc->untag > RTL8367B_UNTAG_MASK ||
vlanmc->fid > RTL8367B_FIDMAX)
vlanmc->fid > ((smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) ? RTL8367D_FIDMAX : RTL8367B_FIDMAX))
return -EINVAL;
if (smi->emu_vlanmc) { /* use vlanmc emulation */
smi->emu_vlanmc[index].vid = vlanmc->vid;
smi->emu_vlanmc[index].member = vlanmc->member;
smi->emu_vlanmc[index].fid = vlanmc->fid;
smi->emu_vlanmc[index].untag = vlanmc->untag;
return 0;
}
data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
RTL8367B_VLAN_MC0_MEMBER_SHIFT;
data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
@ -1014,10 +1106,41 @@ static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
if (port >= RTL8367B_NUM_PORTS)
return -EINVAL;
REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */
int i;
struct rtl8366_vlan_mc vlanmc;
*val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
RTL8367B_VLAN_PVID_CTRL_MASK;
err = rtl8366_smi_read_reg(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), &data);
if (err) {
dev_err(smi->parent, "read pvid register 0x%04x fail", RTL8367D_VLAN_PVID_CTRL_REG(port));
return err;
}
data &= RTL8367D_VLAN_PVID_CTRL_MASK;
for (i = 0; i < smi->num_vlan_mc; i++) {
err = rtl8367b_get_vlan_mc(smi, i, &vlanmc);
if (err) {
dev_err(smi->parent, "get vlan mc index %d fail", i);
return err;
}
if (data == vlanmc.vid) break;
}
if (i < smi->num_vlan_mc) {
*val = i;
} else {
dev_err(smi->parent, "vlan mc index for pvid %d not found", data);
return -EINVAL;
}
} else {
REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
*val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
RTL8367B_VLAN_PVID_CTRL_MASK;
}
return 0;
}
@ -1027,7 +1150,28 @@ static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
return -EINVAL;
return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) { /* Family D */
int pvid, err;
struct rtl8366_vlan_mc vlanmc;
err = rtl8367b_get_vlan_mc(smi, index, &vlanmc);
if (err) {
dev_err(smi->parent, "get vlan mc index %d fail", index);
return err;
}
pvid = vlanmc.vid & RTL8367D_VLAN_PVID_CTRL_MASK;
err = rtl8366_smi_write_reg(smi, RTL8367D_VLAN_PVID_CTRL_REG(port), pvid);
if (err) {
dev_err(smi->parent, "set port %d pvid %d fail", port, pvid);
return err;
}
return 0;
} else
return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
RTL8367B_VLAN_PVID_CTRL_MASK <<
RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
(index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
@ -1090,7 +1234,10 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
if (port >= RTL8367B_NUM_PORTS)
return -EINVAL;
rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */
rtl8366_smi_read_reg(smi, RTL8367D_PORT_STATUS_REG(port), &data);
else
rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
if (!link->link)
@ -1101,15 +1248,18 @@ static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
if (smi->rtl8367b_chip >= RTL8367B_CHIP_RTL8367S_VB) /* Family D */
speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK) | ((data & RTL8367D_PORT_STATUS_SPEED1_MASK) >> RTL8367D_PORT_STATUS_SPEED1_SHIFT);
else
speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
switch (speed) {
case 0:
case RTL8367B_PORT_STATUS_SPEED_10:
link->speed = SWITCH_PORT_SPEED_10;
break;
case 1:
case RTL8367B_PORT_STATUS_SPEED_100:
link->speed = SWITCH_PORT_SPEED_100;
break;
case 2:
case RTL8367B_PORT_STATUS_SPEED_1000:
link->speed = SWITCH_PORT_SPEED_1000;
break;
default:
@ -1328,6 +1478,7 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
u32 chip_ver;
int ret;
smi->emu_vlanmc = NULL;
smi->rtl8367b_chip = RTL8367B_CHIP_UNKNOWN;
rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
@ -1348,6 +1499,12 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
}
switch (chip_ver) {
case 0x0010:
if (chip_num == 0x6642) {
chip_name = "8367S-VB";
smi->rtl8367b_chip = RTL8367B_CHIP_RTL8367S_VB;
}
break;
case 0x0020:
if (chip_num == 0x6367) {
chip_name = "8367RB-VB";
@ -1437,6 +1594,8 @@ static int rtl8367b_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, NULL);
rtl8366_smi_cleanup(smi);
err_free_smi:
if (smi->emu_vlanmc)
kfree(smi->emu_vlanmc);
kfree(smi);
return err;
}

1
target/linux/rockchip/armv8/base-files/etc/board.d/02_network
View File

@ -27,6 +27,7 @@ rockchip_setup_interfaces()
friendlyarm,nanopi-r5c|\
lunzn,fastrhino-r66s|\
radxa,e25|\
radxa,rock-3b|\
xunlong,orangepi-5-plus)
ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
;;

3
target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-armsom-sige3.dts
View File

@ -101,8 +101,7 @@
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &clk32k_out1>;
post-power-on-delay-ms = <100>;
power-off-delay-us = <5000000>;
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
};

40
target/linux/rockchip/image/armv8.mk
View File

@ -264,6 +264,24 @@ define Device/radxa_rock-3a
endef
TARGET_DEVICES += radxa_rock-3a
define Device/radxa_rock-3b
DEVICE_VENDOR := Radxa
DEVICE_MODEL := ROCK 3B
SOC := rk3568
BOOT_FLOW := pine64-img
DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis
endef
TARGET_DEVICES += radxa_rock-3b
define Device/radxa_rock-3c
DEVICE_VENDOR := Radxa
DEVICE_MODEL := ROCK 3C
SOC := rk3566
BOOT_FLOW := pine64-img
DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis
endef
TARGET_DEVICES += radxa_rock-3c
define Device/radxa_rock-5a
DEVICE_VENDOR := Radxa
DEVICE_MODEL := ROCK 5A
@ -326,6 +344,28 @@ define Device/radxa_rock-pi-s
endef
TARGET_DEVICES += radxa_rock-pi-s
define Device/radxa_zero-3e
DEVICE_VENDOR := Radxa
DEVICE_MODEL := ZERO 3E
SOC := rk3566
DEVICE_DTS := rockchip/rk3566-radxa-zero-3e
UBOOT_DEVICE_NAME := radxa-zero-3-rk3566
BOOT_FLOW := pine64-img
DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis
endef
TARGET_DEVICES += radxa_zero-3e
define Device/radxa_zero-3w
DEVICE_VENDOR := Radxa
DEVICE_MODEL := ZERO 3W
SOC := rk3566
DEVICE_DTS := rockchip/rk3566-radxa-zero-3w
UBOOT_DEVICE_NAME := radxa-zero-3-rk3566
BOOT_FLOW := pine64-img
DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis
endef
TARGET_DEVICES += radxa_zero-3w
define Device/sinovoip_bpi-r2-pro
DEVICE_VENDOR := Bananapi
DEVICE_MODEL := BPi-R2 Pro

769
target/linux/rockchip/patches-6.6/009-01-v6.10-arm64-dts-rockchip-Add-Radxa-ROCK-3C.patch Normal file
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@ -0,0 +1,769 @@
From ee219017ddb50be14c60d3cbe3e51ac0b2008d40 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Sun, 28 Apr 2024 20:36:18 +0800
Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3C
The Radxa ROCK 3C is a development board with the
Rockchip RK3566 SoC. It has the following features:
- 1/2/4GB LPDDR4
- 1x HDMI Type A
- 1x PCIE 2.0 slot
- 1x FAN connector
- 3.5mm jack with mic
- 1GbE RTL8211F Ethernet
- 1x USB 3.0, 3x USB 2.0
- 40-pin expansion header
- MicroSD card/eMMC socket
- 16MB SPI NOR (gd25lq128d)
- AP6256 or AIC8800 WiFi/BT
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20240428123618.72170-3-amadeus@jmu.edu.cn
[dropped rk809-sound and not specified pmic sound properties]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-rock-3c.dts | 726 ++++++++++++++++++
2 files changed, 727 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
@@ -0,0 +1,726 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Radxa ROCK 3C";
+ compatible = "radxa,rock-3c", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led2>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc5v_dcin: vcc5v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_dcin>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en>;
+ regulator-name = "vcc5v0_usb30_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_cam: vcc-cam-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_cam_en>;
+ regulator-name = "vcc_cam";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_mipi: vcc-mipi-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_mipi_en>;
+ regulator-name = "vcc_mipi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus
+ &gmac1m1_clkinout>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+ system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ bluetooth {
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_h: bt-wake-host-h {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_h: bt-host-wake-h {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ cam {
+ vcc_cam_en: vcc_cam_en {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ display {
+ vcc_mipi_en: vcc_mipi_en {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led2: user-led2 {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_pwr_en: pcie-pwr-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake_h: wifi-host-wake-h {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcca1v8_pmu>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&sfc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <120000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};

26
target/linux/rockchip/patches-6.6/009-02-v6.11-arm64-dts-rockchip-change-spi-max-frequency-for-Radx.patch Normal file
View File

@ -0,0 +1,26 @@
From 06f6dd4d607766a527e37529f2f3f90dd1464293 Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Sun, 23 Jun 2024 11:33:29 +0900
Subject: [PATCH] arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK
3C
SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
@@ -633,7 +633,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
- spi-max-frequency = <120000000>;
+ spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};

657
target/linux/rockchip/patches-6.6/010-01-v6.11-arm64-dts-rockchip-Add-Radxa-ZERO-3W-3E.patch Normal file
View File

@ -0,0 +1,657 @@
From 1a5c8d307c83c808a32686ed51afb4bac2092d39 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 21 May 2024 20:28:05 +0000
Subject: [PATCH] arm64: dts: rockchip: Add Radxa ZERO 3W/3E
The Radxa ZERO 3W/3E is an ultra-small, high-performance single board
computer based on the Rockchip RK3566, with a compact form factor and
rich interfaces.
The ZERO 3W and ZERO 3E are basically the same size and model, but
differ only in storage and network interfaces.
- eMMC (3W)
- SD-card (both)
- Ethernet (3E)
- WiFi/BT (3W)
Add initial support for eMMC, SD-card, Ethernet, HDMI and USB.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240521202810.1225636-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 2 +
.../dts/rockchip/rk3566-radxa-zero-3.dtsi | 463 ++++++++++++++++++
.../dts/rockchip/rk3566-radxa-zero-3e.dts | 51 ++
.../dts/rockchip/rk3566-radxa-zero-3w.dts | 91 ++++
4 files changed, 607 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -80,6 +80,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
@@ -0,0 +1,463 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led2>;
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc_1v8: regulator-1v8-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_p>;
+ };
+
+ vcca_1v8: regulator-1v8-vcca {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_p>;
+ };
+
+ vcca1v8_image: regulator-1v8-vcca-image {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_p>;
+ };
+
+ vcc_3v3: regulator-3v3-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_npu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda_0v9>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ #clock-cells = <1>;
+ clock-output-names = "rk817-clkout1", "rk817-clkout2";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc5v_midu>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu_npu: DCDC_REG2 {
+ regulator-name = "vdd_gpu_npu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8_p: LDO_REG7 {
+ regulator-name = "vcc_1v8_p";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-name = "vcc2v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc5v_midu: BOOST {
+ regulator-name = "vcc5v_midu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vbus: OTG_SWITCH {
+ regulator-name = "vbus";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu: regulator@40 {
+ compatible = "rockchip,rk8600";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ user_led2: user-led2 {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-radxa-zero-3.dtsi"
+
+/ {
+ model = "Radxa ZERO 3E";
+ compatible = "radxa,zero-3e", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus
+ &gmac1m1_clkinout>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rstn>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ gmac1 {
+ gmac1_rstn: gmac1-rstn {
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-radxa-zero-3.dtsi"
+
+/ {
+ model = "Radxa ZERO 3W";
+ compatible = "radxa,zero-3w", "rockchip,rk3566";
+
+ aliases {
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk817 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ bluetooth {
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_h: bt-wake-host-h {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ host_wake_bt_h: host-wake-bt-h {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_wake_host_h: wifi-wake-host-h {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ no-mmc;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+};

64
target/linux/rockchip/patches-6.6/010-02-v6.11-arm64-dts-rockchip-fix-mmc-aliases-for-Radxa-ZERO-3E.patch Normal file
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@ -0,0 +1,64 @@
From 060c1950037e4c54ca4d8186a8f46269e35db901 Mon Sep 17 00:00:00 2001
From: FUKAUMI Naoki <naoki@radxa.com>
Date: Fri, 21 Jun 2024 07:44:35 +0900
Subject: [PATCH] arm64: dts: rockchip: fix mmc aliases for Radxa ZERO 3E/3W
align with other Radxa products.
- mmc0 is eMMC
- mmc1 is microSD
for ZERO 3E, there is no eMMC, but aliases should start at 0, so mmc0
is microSD as exception.
Fixes: 1a5c8d307c83 ("arm64: dts: rockchip: Add Radxa ZERO 3W/3E")
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Changes in v3:
- fix syntax error in rk3566-radxa-zero-3e.dts
Changes in v2:
- microSD is mmc0 instead of mmc1 for ZERO 3E
Link: https://lore.kernel.org/r/20240620224435.2752-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 4 ----
arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 1 +
arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 3 ++-
3 files changed, 3 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
@@ -6,10 +6,6 @@
#include "rk3566.dtsi"
/ {
- aliases {
- mmc0 = &sdmmc0;
- };
-
chosen {
stdout-path = "serial2:1500000n8";
};
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
@@ -10,6 +10,7 @@
aliases {
ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
@@ -9,7 +9,8 @@
compatible = "radxa,zero-3w", "rockchip,rk3566";
aliases {
- mmc1 = &sdhci;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
};

101
target/linux/rockchip/patches-6.6/010-03-v6.11-arm64-dts-rockchip-add-gpio-line-names-to-radxa-zero.patch Normal file
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From f7c742cbe664ebdedc075945e75443683d1175f7 Mon Sep 17 00:00:00 2001
From: Trevor Woerner <twoerner@gmail.com>
Date: Wed, 19 Jun 2024 21:32:49 -0400
Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to radxa-zero-3
Add names to the pins of the general-purpose expansion header as given
in the Radxa documentation[1] following the conventions in the kernel[2]
to make it easier for users to correlate pins with functions when using
utilities such as 'gpioinfo'.
[1] https://docs.radxa.com/en/zero/zero3/hardware-design/hardware-interface
[2] https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Link: https://lore.kernel.org/r/20240620013301.33653-1-twoerner@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../dts/rockchip/rk3566-radxa-zero-3.dtsi | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
@@ -105,6 +105,78 @@
cpu-supply = <&vdd_cpu>;
};
+&gpio0 {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_D0 - D7 */
+ "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "",
+ "", "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "",
+ "", "pin-37 [GPIO1_A4]", "",
+ "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ /* GPIO2_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO2_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO2_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO2_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ /* GPIO3_A0 - A7 */
+ "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]",
+ "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]",
+ "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]",
+ /* GPIO3_B0 - B7 */
+ "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]",
+ "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "",
+ "", "",
+ /* GPIO3_C0 - C7 */
+ "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]",
+ "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "",
+ "", "",
+ /* GPIO3_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ /* GPIO4_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO4_B0 - B7 */
+ "", "", "pin-27 [GPIO4_B2]",
+ "pin-28 [GPIO4_B3]", "", "", "", "",
+ /* GPIO4_C0 - C7 */
+ "", "", "pin-23 [GPIO4_C2]",
+ "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]",
+ "pin-24 [GPIO4_C6]", "",
+ /* GPIO4_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
&gpu {
mali-supply = <&vdd_gpu_npu>;
status = "okay";

815
target/linux/rockchip/patches-6.6/010-04-v6.11-arm64-dts-rockchip-Add-Radxa-ROCK-3B.patch Normal file
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@ -0,0 +1,815 @@
From 846ef7748fa9124c8eea76e2d5e833fa69b3ef7c Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 27 Jun 2024 21:17:31 +0000
Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3B
The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form
factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community
version based on the RK3568 SoC and an industrial version based on the
RK3568J SoC.
Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240627211737.1985549-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3568-rock-3b.dts | 781 ++++++++++++++++++
2 files changed, 782 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Radxa ROCK 3B";
+ compatible = "radxa,rock-3b", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_ir>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ /* pi6c pcie clock generator */
+ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren_h>;
+ regulator-name = "vcc3v3_pi6c_03";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <10000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: regulator-3v3-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys2: regulator-3v3-vcc-sys2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb_host: regulator-5v0-vcc-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren_h>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_pwren_h>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus
+ &gmac0_clkinout>;
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus
+ &gmac1m1_clkinout>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ clock-names = "mclk";
+ clock-output-names = "rk809-clkout1", "rk809-clkout2";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+ #sound-dai-cells = <0>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtcic_int_l>;
+ wakeup-source;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20m1_pins>;
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys2>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2m1_pins>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pinctrl {
+ bluetooth {
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_h: bt-wake-host-h {
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ host_wake_bt_h: host-wake-bt-h {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ir-receiver {
+ pwm3_ir: pwm3-ir {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led: led {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_pwren_h: pcie-pwren-h {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie20 {
+ pcie20m1_pins: pcie20m1-pins {
+ rockchip,pins =
+ <2 RK_PD0 4 &pcfg_pull_none>,
+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PD1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x2 {
+ pcie30x2m1_pins: pcie30x2m1-pins {
+ rockchip,pins =
+ <2 RK_PD4 4 &pcfg_pull_none>,
+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,
+ <2 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rtc {
+ rtcic_int_l: rtcic-int-l {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ usb_host_pwren_h: usb-host-pwren-h {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_otg_pwren_h: usb-otg-pwren-h {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_wake_host_h: wifi-wake-host-h {
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys2>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "disabled";
+};
+
+&sfc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};

2
target/linux/rockchip/patches-6.6/054-01-v6.7-arm64-dts-rockchip-Add-Orange-Pi-5.patch
View File

@ -21,7 +21,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -105,3 +105,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
@@ -109,3 +109,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb

2
target/linux/rockchip/patches-6.6/055-01-v6.7-arm64-dts-rockchip-Add-board-device-tree-for.patch
View File

@ -36,7 +36,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ed
@@ -105,6 +105,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ed
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb

85
target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch
View File

@ -233,6 +233,36 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
};
chosen: chosen {
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
@@ -6,6 +6,13 @@
#include "rk3566.dtsi"
/ {
+ aliases {
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
+ };
+
chosen {
stdout-path = "serial2:1500000n8";
};
@@ -26,12 +33,11 @@
pinctrl-names = "default";
pinctrl-0 = <&user_led2>;
- led-green {
+ led_green: led-green {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
@@ -9,6 +9,13 @@
@ -313,6 +343,34 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
pinctrl-names = "default";
pinctrl-0 = <&led_user_en>;
};
--- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
@@ -16,6 +16,10 @@
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
+ led-boot = &led_blue;
+ led-failsafe = &led_blue;
+ led-running = &led_blue;
+ led-upgrade = &led_blue;
};
chosen: chosen {
@@ -43,11 +47,10 @@
leds {
compatible = "gpio-leds";
- led-0 {
- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_HEARTBEAT;
+ led_blue: led-0 {
color = <LED_COLOR_ID_BLUE>;
- linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&user_led2>;
};
--- a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
@@ -19,6 +19,11 @@
@ -386,6 +444,33 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
pinctrl-names = "default";
pinctrl-0 = <&led_user_en>;
};
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -18,6 +18,10 @@
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc2;
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
};
chosen {
@@ -47,12 +51,11 @@
pinctrl-names = "default";
pinctrl-0 = <&led>;
- led-0 {
+ led_green: led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
@@ -8,6 +8,7 @@

5
target/linux/rockchip/patches-6.6/900-arm64-boot-add-dts-files.patch
View File

@ -16,7 +16,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
@@ -86,17 +88,21 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so
@@ -89,18 +91,22 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
@ -34,11 +34,12 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
@@ -105,5 +111,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-or
@@ -109,5 +115,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-or
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb

1
tools/libtool/Makefile
View File

@ -28,6 +28,7 @@ define Host/Bootstrap
cd $(HOST_BUILD_DIR); \
$(AM_TOOL_PATHS) \
./bootstrap \
--copy \
--force \
--skip-git \
--skip-po \