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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2025-03-25 14:32:32 +08:00
commit bc6a1bf70d
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GPG Key ID: 6850B6345C862176
40 changed files with 1569 additions and 349 deletions
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31
include/image-commands.mk
View File

@ -99,6 +99,37 @@ define Build/append-metadata
}
endef
metadata_gl_json = \
'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
"metadata_version": "1.1", \
"compat_version": "$(call json_quote,$(compat_version))", \
$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \
"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \
"version": { \
"release": "$(call json_quote,$(VERSION_NUMBER))", \
"date": "$(shell TZ='Asia/Chongqing' date '+%Y%m%d%H%M%S')", \
"dist": "$(call json_quote,$(VERSION_DIST))", \
"version": "$(call json_quote,$(VERSION_NUMBER))", \
"revision": "$(call json_quote,$(REVISION))", \
"target": "$(call json_quote,$(TARGETID))", \
"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
} \
}'
define Build/append-gl-metadata
$(if $(SUPPORTED_DEVICES),-echo $(call metadata_gl_json,$(SUPPORTED_DEVICES)) | fwtool -I - $@)
sha256sum "$@" | cut -d" " -f1 > "$@.sha256sum"
[ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \
cp "$(BUILD_KEY).ucert" "$@.ucert" ;\
usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\
ucert -A -c "$@.ucert" -x "$@.sig" ;\
fwtool -S "$@.ucert" "$@" ;\
}
endef
define Build/append-rootfs
dd if=$(IMAGE_ROOTFS) >> $@
endef

26
package/boot/uboot-tools/Makefile
View File

@ -22,19 +22,6 @@ PKG_BUILD_PARALLEL:=1
include $(INCLUDE_DIR)/package.mk
define Package/uboot-tools
SECTION:=utils
CATEGORY:=Utilities
SUBMENU:=Boot Loaders
TITLE:=U-Boot bootloader Tools
URL:=http://www.denx.de/wiki/U-Boot
endef
define Package/uboot-tools/description
U-Boot tools are a collection of utilities designed
to work with the U-Boot bootloader,
endef
define Package/dumpimage
SECTION:=utils
CATEGORY:=Utilities
@ -72,19 +59,26 @@ define Package/uboot-envtools/conffiles
endef
define Build/Configure
$(MAKE) -C $(PKG_BUILD_DIR) tools-only_defconfig
$(MAKE) -C $(PKG_BUILD_DIR) syncconfig
$(call Build/Compile/Default,tools-only_defconfig)
$(call Build/Compile/Default,syncconfig)
$(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
endef
MAKE_FLAGS += \
ARCH="sandbox" \
TARGET_CFLAGS="$(TARGET_CFLAGS)" \
TARGET_LDFLAGS="$(TARGET_LDFLAGS)"
TARGET_LDFLAGS="$(TARGET_LDFLAGS)" \
NO_PYTHON=1
define Build/Compile
ifneq ($(CONFIG_PACKAGE_uboot-envtools),)
$(call Build/Compile/Default,envtools)
endif
ifneq ($(CONFIG_PACKAGE_dumpimage),)
$(call Build/Compile/Default,cross_tools)
endif
endef
define Package/dumpimage/install

8
package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq60xx
View File

@ -19,13 +19,15 @@ case "$board" in
cambiumnetworks,xe3-4)
ubootenv_add_mtd "0:APPSBLENV" "0x0" "0x10000" "0x10000"
;;
linksys,mr7350)
ubootenv_add_mtd "u_env" "0x0" "0x40000" "0x20000"
;;
glinet,gl-ax1800|\
glinet,gl-axt1800|\
netgear,wax214|\
tplink,eap610-outdoor)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000"
;;
linksys,mr7350)
ubootenv_add_mtd "u_env" "0x0" "0x40000" "0x20000"
;;
yuncore,fap650)
ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x10000"
;;

4
package/firmware/ipq-wifi/Makefile
View File

@ -38,6 +38,8 @@ ALLWIFIBOARDS:= \
dynalink_dl-wrx36 \
edgecore_eap102 \
edimax_cax1800 \
glinet_gl-ax1800 \
glinet_gl-axt1800 \
linksys_homewrk \
linksys_mr5500 \
linksys_mr7350 \
@ -181,6 +183,8 @@ $(eval $(call generate-ipq-wifi-package,compex_wpq873,Compex WPQ-873))
$(eval $(call generate-ipq-wifi-package,dynalink_dl-wrx36,Dynalink DL-WRX36))
$(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102))
$(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800))
$(eval $(call generate-ipq-wifi-package,glinet_gl-ax1800,GL.iNet GL-AX1800))
$(eval $(call generate-ipq-wifi-package,glinet_gl-axt1800,GL.iNet GL-AXT1800))
$(eval $(call generate-ipq-wifi-package,linksys_homewrk,Linksys HomeWRK))
$(eval $(call generate-ipq-wifi-package,linksys_mr5500,Linksys MR5500))
$(eval $(call generate-ipq-wifi-package,linksys_mr7350,Linksys MR7350))

31
target/linux/mediatek/image/filogic.mk
View File

@ -52,37 +52,6 @@ define Build/mt798x-gpt
rm $@.tmp
endef
metadata_gl_json = \
'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
"metadata_version": "1.1", \
"compat_version": "$(call json_quote,$(compat_version))", \
$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \
"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \
"version": { \
"release": "$(call json_quote,$(VERSION_NUMBER))", \
"date": "$(shell TZ='Asia/Chongqing' date '+%Y%m%d%H%M%S')", \
"dist": "$(call json_quote,$(VERSION_DIST))", \
"version": "$(call json_quote,$(VERSION_NUMBER))", \
"revision": "$(call json_quote,$(REVISION))", \
"target": "$(call json_quote,$(TARGETID))", \
"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
} \
}'
define Build/append-gl-metadata
$(if $(SUPPORTED_DEVICES),-echo $(call metadata_gl_json,$(SUPPORTED_DEVICES)) | fwtool -I - $@)
sha256sum "$@" | cut -d" " -f1 > "$@.sha256sum"
[ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \
cp "$(BUILD_KEY).ucert" "$@.ucert" ;\
usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\
ucert -A -c "$@.ucert" -x "$@.sig" ;\
fwtool -S "$@.ucert" "$@" ;\
}
endef
define Build/append-openwrt-one-eeprom
dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@
endef

70
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-gl-ax1800.dts Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq6000-glinet.dtsi"
/ {
model = "GL.iNet GL-AX1800";
compatible = "glinet,gl-ax1800", "qcom,ipq6018";
aliases {
label-mac-device = &dp1;
};
};
&partitions {
partition@a00000 {
label = "rootfs";
reg = <0x0a00000 0x7300000>;
};
};
&switch {
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>;
switch_wan_bmp = <ESS_PORT1>;
};
&dp1 {
status = "okay";
phy-handle = <&qca8075_0>;
label = "wan";
nvmem-cells = <&macaddr_wan>;
nvmem-cell-names = "mac-address";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "lan1";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan2";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address";
};
&dp4 {
status = "okay";
phy-handle = <&qca8075_3>;
label = "lan3";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address";
};
&dp5 {
status = "okay";
phy-handle = <&qca8075_4>;
label = "lan4";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address";
};
&wifi {
qcom,ath11k-calibration-variant = "GL-iNet-GL-AX1800";
};

169
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-gl-axt1800.dts Normal file
View File

@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ipq6000-glinet.dtsi"
/ {
model = "GL.iNet GL-AXT1800";
compatible = "glinet,gl-axt1800", "qcom,ipq6018";
aliases {
label-mac-device = &dp1;
};
vcc_sd: regulator-vcc-sd {
compatible = "regulator-fixed";
regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
vcc_fan: regulator-vcc-fan {
compatible = "regulator-fixed";
regulator-name = "vcc_fan";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
fan: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm 1 40000 0>;
fan-supply = <&vcc_fan>;
interrupt-parent = <&tlmm>;
interrupts = <31 IRQ_TYPE_EDGE_RISING>;
cooling-levels = <36 128 192 255>;
#cooling-cells = <2>;
};
thermal-zones {
cpu-thermal {
trips {
cpu_trip_high: active-high {
temperature = <100000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_med: active-med {
temperature = <75000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_low: active-low {
temperature = <50000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
cpu-active-high {
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_high>;
};
cpu-active-med {
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_med>;
};
cpu-active-low {
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_low>;
};
};
};
};
};
&tlmm {
pwm_pins: pwm-pins {
pwm {
pins = "gpio30";
function = "pwm13";
drive-strength = <8>;
};
};
sd_pins: sd-pins {
sd {
pins = "gpio62";
function = "sd_card";
bias-pull-up;
};
ldo {
pins = "gpio66";
function = "gpio";
bias-pull-up;
};
};
};
&partitions {
partition@a00000 {
label = "rootfs";
reg = <0x0a00000 0x7280000>;
};
partition@7c80000 {
label = "log";
reg = <0x7c80000 0x0080000>;
};
};
&pwm {
pinctrl-0 = <&pwm_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhc {
mmc-ddr-1_8v;
bus-width = <4>;
cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
vqmmc-supply = <&vcc_sd>;
status = "okay";
};
&switch {
switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3)>;
switch_wan_bmp = <ESS_PORT1>;
};
&dp1 {
status = "okay";
phy-handle = <&qca8075_0>;
label = "wan";
nvmem-cells = <&macaddr_wan>;
nvmem-cell-names = "mac-address";
};
&dp2 {
status = "okay";
phy-handle = <&qca8075_1>;
label = "lan2";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address";
};
&dp3 {
status = "okay";
phy-handle = <&qca8075_2>;
label = "lan1";
nvmem-cells = <&macaddr_lan>;
nvmem-cell-names = "mac-address";
};
&wifi {
qcom,ath11k-calibration-variant = "GL-iNet-GL-AXT1800";
};

316
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6000-glinet.dtsi Normal file
View File

@ -0,0 +1,316 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ipq6018-512m.dtsi"
#include "ipq6018-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
led-boot = &led_run;
led-failsafe = &led_run;
led-running = &led_run;
led-upgrade = &led_run;
serial0 = &blsp1_uart3;
serial1 = &blsp1_uart4;
serial2 = &blsp1_uart5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
switch {
label = "switch";
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
};
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_run: run {
label = "blue:run";
color = <LED_COLOR_ID_BLUE>;
gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
};
system {
label = "white:system";
color = <LED_COLOR_ID_WHITE>;
gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
};
};
reg_usb_vbus: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio64";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio65";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
tluart_pins: tluart-pins {
mux {
pins = "gpio75", "gpio76";
function = "blsp3_uart";
drive-strength = <8>;
bias-disable;
};
};
hsuart_pins: hsuart-pins {
mux {
pins = "gpio57", "gpio58";
function = "blsp4_uart";
drive-strength = <8>;
bias-disable;
};
};
};
&blsp1_uart3 {
pinctrl-0 = <&serial_3_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart4 {
pinctrl-0 = <&tluart_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart5 {
pinctrl-0 = <&hsuart_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
#address-cells = <1>;
#size-cells = <1>;
partitions: partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0000000 0x0180000>;
read-only;
};
partition@180000 {
label = "0:mibib";
reg = <0x0180000 0x0100000>;
read-only;
};
partition@280000 {
label = "0:qsee";
reg = <0x0280000 0x0380000>;
read-only;
};
partition@600000 {
label = "0:devcfg";
reg = <0x0600000 0x0080000>;
read-only;
};
partition@680000 {
label = "0:rpm";
reg = <0x0680000 0x0080000>;
read-only;
};
partition@700000 {
label = "0:cdt";
reg = <0x0700000 0x0080000>;
read-only;
};
partition@780000 {
label = "0:appsblenv";
reg = <0x0780000 0x0080000>;
};
partition@800000 {
label = "0:appsbl";
reg = <0x0800000 0x0180000>;
read-only;
};
partition@980000 {
label = "0:art";
reg = <0x0980000 0x0080000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_wan: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_lan: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
/* rootfs defined in variant dts */
partition@7d00000 {
label = "0:ethphyfw";
reg = <0x7d00000 0x0080000>;
read-only;
};
};
};
};
&qusb_phy_0 {
vdd-supply = <&reg_usb_vbus>;
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb3 {
status = "okay";
};
&rpm {
status = "disabled";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 74 GPIO_ACTIVE_LOW>;
ethernet-phy-package@0 {
compatible = "qcom,qca8075-package";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8075_4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
};
&switch {
status = "okay";
switch_mac_mode = <MAC_MODE_PSGMII>;
qcom,port_phyinfo {
port@1 {
port_id = <1>;
phy_address = <0>;
};
port@2 {
port_id = <2>;
phy_address = <1>;
};
port@3 {
port_id = <3>;
phy_address = <2>;
};
port@4 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <5>;
phy_address = <4>;
};
};
};
&edma {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-fw-memory-mode = <1>;
};

4
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-mango-dvk.dts
View File

@ -270,12 +270,12 @@
};
};
&sdhc_1 {
&sdhc {
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
status = "okay";
vqmmc-supply = <&ipq6018_l2>;
bus-width = <4>;
cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
};

8
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6010-xe3-4.dts
View File

@ -3,7 +3,6 @@
/dts-v1/;
#include "ipq6018.dtsi"
#include "ipq6018-fixed-smps.dtsi"
#include "ipq6018-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -16,7 +15,6 @@
aliases {
serial0 = &blsp1_uart3;
sdhc2 = &sdhc_1;
ethernet0 = &dp5;
ethernet1 = &dp4;
label-mac-device = &dp5;
@ -88,6 +86,10 @@
status = "okay";
};
&rpm {
status = "disabled";
};
&tlmm {
/* TZ has exclusive control over GPIO20 */
gpio-reserved-ranges = <20 1>;
@ -172,7 +174,7 @@
};
};
&sdhc_1 {
&sdhc {
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
status = "okay";

43
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cp-cpu.dtsi
View File

@ -1,19 +1,54 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "ipq6018-cpr-regulator.dtsi"
#include "ipq6018-mp5496.dtsi"
&CPU0 {
&cpu0 {
cpu-supply = <&apc_vreg>;
};
&CPU1 {
&cpu1 {
cpu-supply = <&apc_vreg>;
};
&CPU2 {
&cpu2 {
cpu-supply = <&apc_vreg>;
};
&CPU3 {
&cpu3 {
cpu-supply = <&apc_vreg>;
};
&cpu_opp_table {
opp-864000000 {
opp-microvolt = <1>;
};
opp-1056000000 {
opp-microvolt = <2>;
};
opp-1200000000 {
opp-microvolt = <3>;
};
opp-1320000000 {
opp-microvolt = <3>;
};
opp-1440000000 {
opp-microvolt = <4>;
};
opp-1512000000 {
opp-microvolt = <5>;
};
opp-1608000000 {
opp-microvolt = <5>;
};
opp-1800000000 {
opp-microvolt = <6>;
};
};

2
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-cpr-regulator.dtsi
View File

@ -43,7 +43,7 @@
qcom,cpr-up-error-step-limit = <1>;
qcom,apm-ctrl = <&apc_apm>;
qcom,apm-threshold-voltage = <850000>;
vdd-supply = <&ipq6018_s2>;
vdd-supply = <&mp5496_s2>;
qcom,voltage-step = <12500>;
thread@0 {

52
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-fixed-smps.dtsi
View File

@ -1,52 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Board does not use companion MP5496 PMIC,
* but rather uses fixed external SMPS.
*/
&rpm {
status = "disabled";
};
&CPU0 {
/delete-property/ cpu-supply;
};
&CPU1 {
/delete-property/ cpu-supply;
};
&CPU2 {
/delete-property/ cpu-supply;
};
&CPU3 {
/delete-property/ cpu-supply;
};
&cpu_opp_table {
opp-864000000 {
opp-microvolt = <1100000>;
};
opp-1056000000 {
opp-microvolt = <1100000>;
};
opp-1320000000 {
opp-microvolt = <1100000>;
};
opp-1440000000 {
opp-microvolt = <1100000>;
};
opp-1608000000 {
opp-microvolt = <1100000>;
};
opp-1800000000 {
opp-microvolt = <1100000>;
};
};

48
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
View File

@ -3,22 +3,22 @@
#include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi"
&CPU0 {
&cpu0 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU1 {
&cpu1 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU2 {
&cpu2 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU3 {
&cpu3 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
@ -35,10 +35,10 @@
cooling-maps {
map0 {
trip = <&cpu0_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -55,10 +55,10 @@
cooling-maps {
map0 {
trip = <&cpu1_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -75,10 +75,10 @@
cooling-maps {
map0 {
trip = <&cpu2_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -95,10 +95,10 @@
cooling-maps {
map0 {
trip = <&cpu3_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -115,10 +115,10 @@
cooling-maps {
map0 {
trip = <&cluster_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

88
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
View File

@ -3,22 +3,22 @@
#include <dt-bindings/thermal/thermal.h>
#include "ipq8074-cpr-regulator.dtsi"
&CPU0 {
&cpu0 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU1 {
&cpu1 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU2 {
&cpu2 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
&CPU3 {
&cpu3 {
cpu-supply = <&apc_vreg>;
voltage-tolerance = <1>;
};
@ -41,17 +41,17 @@
cooling-maps {
map0 {
trip = <&cpu0_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -74,17 +74,17 @@
cooling-maps {
map0 {
trip = <&cpu1_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -107,17 +107,17 @@
cooling-maps {
map0 {
trip = <&cpu2_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -140,17 +140,17 @@
cooling-maps {
map0 {
trip = <&cpu3_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@ -173,17 +173,17 @@
cooling-maps {
map0 {
trip = <&cluster_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cluster_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

28
target/linux/qualcommax/image/ipq60xx.mk
View File

@ -24,6 +24,34 @@ define Device/cambiumnetworks_xe3-4
endef
TARGET_DEVICES += cambiumnetworks_xe3-4
define Device/glinet_gl-common
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := GL.iNet
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@cp03-c1
SOC := ipq6000
IMAGES += factory.bin
IMAGE/factory.bin := append-ubi | append-gl-metadata
endef
define Device/glinet_gl-ax1800
$(call Device/glinet_gl-common)
DEVICE_MODEL := GL-AX1800
DEVICE_PACKAGES := ipq-wifi-glinet_gl-ax1800
SUPPORTED_DEVICES += glinet,ax1800
endef
TARGET_DEVICES += glinet_gl-ax1800
define Device/glinet_gl-axt1800
$(call Device/glinet_gl-common)
DEVICE_MODEL := GL-AXT1800
DEVICE_PACKAGES := ipq-wifi-glinet_gl-axt1800 kmod-hwmon-pwmfan
SUPPORTED_DEVICES += glinet,axt1800
endef
TARGET_DEVICES += glinet_gl-axt1800
define Device/linksys_mr7350
$(call Device/FitImage)
DEVICE_VENDOR := Linksys

12
target/linux/qualcommax/ipq60xx/base-files/etc/board.d/02_network
View File

@ -11,12 +11,18 @@ ipq60xx_setup_interfaces()
local board="$1"
case "$board" in
8devices,mango-dvk)
8devices,mango-dvk|\
glinet,gl-axt1800)
ucidef_set_interfaces_lan_wan "lan1 lan2" "wan"
;;
cambiumnetworks,xe3-4)
ucidef_set_interface_lan "lan1 lan2" "dhcp"
;;
glinet,gl-ax1800|\
linksys,mr7350|\
yuncore,fap650)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
netgear,wax214)
ucidef_set_interfaces_lan_wan "lan"
;;
@ -26,10 +32,6 @@ ipq60xx_setup_interfaces()
tplink,eap610-outdoor)
ucidef_set_interface_lan "lan" "dhcp"
;;
linksys,mr7350|\
yuncore,fap650)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
*)
echo "Unsupported hardware. Network interfaces not initialized"
;;

8
target/linux/qualcommax/ipq60xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
View File

@ -15,6 +15,14 @@ case "$FIRMWARE" in
cambiumnetworks,xe3-4)
caldata_extract "0:ART" 0x1000 0x10000
;;
glinet,gl-ax1800|\
glinet,gl-axt1800)
caldata_extract "0:art" 0x1000 0x10000
label_mac=$(get_mac_label)
ath11k_patch_mac $(macaddr_add $label_mac 3) 0
ath11k_patch_mac $(macaddr_add $label_mac 2) 1
ath11k_set_macflag
;;
linksys,mr7350)
caldata_extract "0:art" 0x1000 0x10000
addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)

10
target/linux/qualcommax/ipq60xx/base-files/lib/upgrade/platform.sh
View File

@ -110,6 +110,12 @@ platform_do_upgrade() {
fw_setenv bootcount 0
nand_do_upgrade "$1"
;;
glinet,gl-ax1800|\
glinet,gl-axt1800|\
netgear,wax214|\
qihoo,360v6)
nand_do_upgrade "$1"
;;
linksys,mr7350)
boot_part="$(fw_printenv -n boot_part)"
if [ "$boot_part" -eq "1" ]; then
@ -124,10 +130,6 @@ platform_do_upgrade() {
fw_setenv auto_recovery yes
nand_do_upgrade "$1"
;;
netgear,wax214|\
qihoo,360v6)
nand_do_upgrade "$1"
;;
tplink,eap610-outdoor)
tplink_do_upgrade "$1"
;;

3
target/linux/qualcommax/ipq60xx/config-default
View File

@ -1,6 +1,9 @@
CONFIG_IPQ_GCC_6018=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PWM=y
CONFIG_PWM_IPQ=y
CONFIG_PWM_SYSFS=y
CONFIG_QCOM_APM=y
# CONFIG_QCOM_CLK_SMD_RPM is not set
# CONFIG_QCOM_RPMPD is not set

26
target/linux/qualcommax/patches-6.6/0082-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch Normal file
View File

@ -0,0 +1,26 @@
From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Thu, 20 Jun 2024 23:01:21 +0800
Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency
The mmc controller of the IPQ6018 does not support HS400 mode.
So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a
F(96000000, P_GPLL2, 12, 0, 0),
F(177777778, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL2, 6, 0, 0),
- F(384000000, P_GPLL2, 3, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
{ }
};

47
target/linux/qualcommax/patches-6.6/0083-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch Normal file
View File

@ -0,0 +1,47 @@
From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Thu, 20 Jun 2024 23:01:22 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: add sdhci node
Add node to support mmc controller inside of IPQ6018.
This controller supports both eMMC and SD cards.
Tested with:
eMMC (HS200)
SD Card (SDR50/SDR104)
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20240620150122.1406631-3-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -470,6 +470,25 @@
};
};
+ sdhc: mmc@7804000 {
+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x07804000 0x0 0x1000>,
+ <0x0 0x07805000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
+ max-frequency = <192000000>;
+ status = "disabled";
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;

381
target/linux/qualcommax/patches-6.6/0084-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch Normal file
View File

@ -0,0 +1,381 @@
From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 22 Oct 2024 17:47:26 +0200
Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
5 files changed, 61 insertions(+), 61 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -31,27 +31,27 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -30,47 +30,47 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -34,12 +34,12 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -47,12 +47,12 @@
#cooling-cells = <2>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -60,12 +60,12 @@
#cooling-cells = <2>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -73,12 +73,12 @@
#cooling-cells = <2>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -86,7 +86,7 @@
#cooling-cells = <2>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -993,10 +993,10 @@
cooling-maps {
map0 {
trip = <&cpu_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,39 +32,39 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -33,12 +33,12 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -46,12 +46,12 @@
#cooling-cells = <2>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x1>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -59,12 +59,12 @@
#cooling-cells = <2>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x2>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -72,12 +72,12 @@
#cooling-cells = <2>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x3>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
@@ -85,7 +85,7 @@
#cooling-cells = <2>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -845,10 +845,10 @@
cooling-maps {
map0 {
trip = <&cpu0_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -875,10 +875,10 @@
cooling-maps {
map0 {
trip = <&cpu1_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -905,10 +905,10 @@
cooling-maps {
map0 {
trip = <&cpu2_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -935,10 +935,10 @@
cooling-maps {
map0 {
trip = <&cpu3_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

33
target/linux/qualcommax/patches-6.6/0085-v6.15-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch Normal file
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@ -0,0 +1,33 @@
From 144230e5840c09984ad743c3df9de5fb443159a9 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Mon, 10 Feb 2025 15:01:18 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency
The final version of IPQ6000 (SoC id: IPQ6000, SBL version:
BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency
of 1.2GHz, so add this CPU frequency.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -119,6 +119,13 @@
clock-latency-ns = <200000>;
};
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <200000>;
+ };
+
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;

33
target/linux/qualcommax/patches-6.6/0086-v6.15-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch Normal file
View File

@ -0,0 +1,33 @@
From a96e765a7b3f64429f7eec3471a2093355ab041e Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Mon, 10 Feb 2025 15:01:19 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency
The early version of IPQ6000 (SoC id: IPQ6018, SBL version:
BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach
a max frequency of 1.5GHz, so add this CPU frequency.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -140,6 +140,13 @@
clock-latency-ns = <200000>;
};
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <937500>;
+ opp-supported-hw = <0x2>;
+ clock-latency-ns = <200000>;
+ };
+
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;

120
target/linux/qualcommax/patches-6.6/0087-v6.15-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch Normal file
View File

@ -0,0 +1,120 @@
From 0c4c0f14b7d704bcb728d018a74788771dc9286b Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Mon, 10 Feb 2025 15:01:20 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi
Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496
pmic was never part of the IPQ60xx SoC, it's optional, so we moved
it out of the soc dtsi.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +-
arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 -----------
3 files changed, 36 insertions(+), 15 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -7,7 +7,7 @@
/dts-v1/;
-#include "ipq6018.dtsi"
+#include "ipq6018-mp5496.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that
+ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC.
+ */
+
+#include "ipq6018.dtsi"
+
+&cpu0 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&cpu1 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&cpu2 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&cpu3 {
+ cpu-supply = <&ipq6018_s2>;
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+};
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -43,7 +43,6 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -56,7 +55,6 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -69,7 +67,6 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -82,7 +79,6 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
#cooling-cells = <2>;
};
@@ -184,16 +180,6 @@
rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018";
qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
};
};
};

50
target/linux/qualcommax/patches-6.6/0088-v6.15-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch Normal file
View File

@ -0,0 +1,50 @@
From e60f872c2dc4c1d9227977c8714373fe6328699c Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Mon, 10 Feb 2025 15:01:21 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator
Change the labels of mp5496 regulator from ipq6018 to mp5496.
Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
@@ -7,26 +7,26 @@
#include "ipq6018.dtsi"
&cpu0 {
- cpu-supply = <&ipq6018_s2>;
+ cpu-supply = <&mp5496_s2>;
};
&cpu1 {
- cpu-supply = <&ipq6018_s2>;
+ cpu-supply = <&mp5496_s2>;
};
&cpu2 {
- cpu-supply = <&ipq6018_s2>;
+ cpu-supply = <&mp5496_s2>;
};
&cpu3 {
- cpu-supply = <&ipq6018_s2>;
+ cpu-supply = <&mp5496_s2>;
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
- ipq6018_s2: s2 {
+ mp5496_s2: s2 {
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1062500>;
regulator-always-on;

33
target/linux/qualcommax/patches-6.6/0089-v6.15-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch Normal file
View File

@ -0,0 +1,33 @@
From a566fb9ba8ffecb56c50729390a9ea076f5c9532 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Mon, 10 Feb 2025 15:01:22 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
Add LDOA2 regulator from MP5496 to support SDCC voltage scaling.
Suggested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
@@ -31,5 +31,14 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
+
+ mp5496_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
};
+
+&sdhc {
+ vqmmc-supply = <&mp5496_l2>;
+};

16
target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch
View File

@ -23,37 +23,37 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
#address-cells = <2>;
@@ -38,6 +39,8 @@
reg = <0x0>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
enable-method = "psci";
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU1: cpu@1 {
cpu1: cpu@1 {
@@ -46,6 +49,8 @@
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU2: cpu@2 {
cpu2: cpu@2 {
@@ -54,6 +59,8 @@
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU3: cpu@3 {
cpu3: cpu@3 {
@@ -62,6 +69,8 @@
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
L2_0: l2-cache {
l2_0: l2-cache {

14
target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch
View File

@ -21,28 +21,28 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
@@ -51,6 +52,7 @@
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
@@ -61,6 +63,7 @@
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
@@ -71,6 +74,7 @@
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
l2_0: l2-cache {

8
target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
@@ -53,6 +54,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
@ -28,7 +28,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
@@ -64,6 +66,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
@ -36,7 +36,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
@@ -75,6 +78,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
@ -44,7 +44,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
+ operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
l2_0: l2-cache {
@@ -84,6 +88,54 @@
};
};

2
target/linux/qualcommax/patches-6.6/0140-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch → target/linux/qualcommax/patches-6.6/0135-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -199,6 +199,11 @@
@@ -194,6 +194,11 @@
no-map;
};

45
target/linux/qualcommax/patches-6.6/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch
View File

@ -1,45 +0,0 @@
From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 24 Apr 2023 15:13:32 +0300
Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
IPQ6018 has one SD/eMMC controller, add node for it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Tested-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -470,6 +470,29 @@
};
};
+ sdhc_1: mmc@7804000 {
+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x07804000 0x0 0x1000>,
+ <0x0 0x07805000 0x0 0x1000>,
+ <0x0 0x07808000 0x0 0x2000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface", "core", "xo", "ice";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+ supports-cqe;
+ bus-width = <8>;
+ status = "disabled";
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;

45
target/linux/qualcommax/patches-6.6/0138-arm64-dts-qcom-ipq6018-add-pwm-node.patch Normal file
View File

@ -0,0 +1,45 @@
From b4a32d218d424b81a58fbd419e1114b1c1f76168 Mon Sep 17 00:00:00 2001
From: Devi Priya <quic_devipriy@quicinc.com>
Date: Thu, 5 Oct 2023 21:35:50 +0530
Subject: [PATCH] arm64: dts: qcom: ipq6018: add pwm node
Describe the PWM block on IPQ6018.
The PWM is in the TCSR area. Make &tcsr "simple-mfd" compatible, and add
&pwm as child of &tcsr.
Add also ipq6018 specific compatible string.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -430,8 +430,21 @@
};
tcsr: syscon@1937000 {
- compatible = "qcom,tcsr-ipq6018", "syscon";
+ compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd";
reg = <0x0 0x01937000 0x0 0x21000>;
+ ranges = <0x0 0x0 0x01937000 0x21000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pwm: pwm@a010 {
+ compatible = "qcom,ipq6018-pwm";
+ reg = <0xa010 0x20>;
+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
+ assigned-clock-rates = <100000000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
};
usb2: usb@70f8800 {

27
target/linux/qualcommax/patches-6.6/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch
View File

@ -1,27 +0,0 @@
From d24bc08bfc66f47d6e0a294a080d62893a7696b5 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Thu, 18 Jan 2024 21:30:21 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
Add LDOA2 regulator of MP5496 to support SDCC voltage scaling.
Suggested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -179,6 +179,11 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
+
+ ipq6018_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
};
};

6
target/linux/qualcommax/patches-6.6/0141-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch
View File

@ -12,6 +12,12 @@ Co-developed-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
drivers/pwm/Kconfig | 12 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-ipq.c | 282 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 295 insertions(+)
create mode 100644 drivers/pwm/pwm-ipq.c
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -282,6 +282,18 @@ config PWM_INTEL_LGM

2
target/linux/qualcommax/patches-6.6/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -814,6 +814,102 @@
@@ -818,6 +818,102 @@
};
};

2
target/linux/qualcommax/patches-6.6/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -1162,6 +1162,7 @@
@@ -1166,6 +1166,7 @@
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";

2
target/linux/qualcommax/patches-6.6/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -935,8 +935,8 @@
@@ -939,8 +939,8 @@
"wcss_reset",
"wcss_q6_reset";

65
target/linux/qualcommax/patches-6.6/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch
View File

@ -1,65 +0,0 @@
From c67a1814bb1d0df290cf1e3f9c966f04aa41b9b9 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 30 Jan 2024 12:43:56 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: change voltage to perf levels for
CPR4 driver
Current CPR4 driver requires opp-microvolt to be an abstract
performance level instead of actual voltage level.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -107,42 +107,42 @@
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;
- opp-microvolt = <725000>;
+ opp-microvolt = <1>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
+ opp-microvolt = <2>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
+ opp-microvolt = <3>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
+ opp-microvolt = <4>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
+ opp-microvolt = <5>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
+ opp-microvolt = <6>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};