diff --git a/include/kernel-6.6 b/include/kernel-6.6 index 2b70664440..e3de08df98 100644 --- a/include/kernel-6.6 +++ b/include/kernel-6.6 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.6 = .85 -LINUX_KERNEL_HASH-6.6.85 = 5ebaccf4ca3428cd26817bae62171f4efd270eed866a3e3d0a1d9e970b7b7529 +LINUX_VERSION-6.6 = .87 +LINUX_KERNEL_HASH-6.6.87 = 8957e5c2dacdbc47a16dbf1f6303ca7088409be6197a3881f752313275357ac6 diff --git a/include/target.mk b/include/target.mk index 9abf3e8e78..93c079a84d 100644 --- a/include/target.mk +++ b/include/target.mk @@ -290,8 +290,8 @@ ifeq ($(DUMP),1) CPU_CFLAGS_archs = -mcpu=archs endif ifeq ($(ARCH),riscv64) - CPU_TYPE ?= riscv64 - CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc + CPU_TYPE ?= generic + CPU_CFLAGS_generic:=-mabi=lp64d -march=rv64gc endif ifeq ($(ARCH),loongarch64) CPU_TYPE ?= generic diff --git a/package/boot/tfa-layerscape/Makefile b/package/boot/tfa-layerscape/Makefile index 1302e35c40..a6519ca02d 100644 --- a/package/boot/tfa-layerscape/Makefile +++ b/package/boot/tfa-layerscape/Makefile @@ -43,6 +43,7 @@ endef define Trusted-Firmware-A/Default BUILD_TARGET:=layerscape BUILD_SUBTARGET:=armv8_64b + BUILD_DEVICES:=fsl_$(1) DEPENDS:=+layerscape-rcw +u-boot-fsl_$(1) endef diff --git a/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch b/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch index 55a94189d3..3422bd42ac 100644 --- a/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch +++ b/package/boot/uboot-mediatek/patches/445-add-netis-nx31.patch @@ -282,10 +282,10 @@ +bootcmd=run check_buttons ; if pstore check ; then run boot_recovery ; else run boot_ubi ; fi +bootconf=config-1 +bootdelay=0 -+bootfile=openwrt-mediatek-filogic-netis_nx31-initramfs-recovery.itb -+bootfile_bl2=openwrt-mediatek-filogic-netis_nx31-preloader.bin -+bootfile_fip=openwrt-mediatek-filogic-netis_nx31-bl31-uboot.fip -+bootfile_upg=openwrt-mediatek-filogic-netis_nx31-squashfs-sysupgrade.itb ++bootfile=immortalwrt-mediatek-filogic-netis_nx31-initramfs-recovery.itb ++bootfile_bl2=immortalwrt-mediatek-filogic-netis_nx31-preloader.bin ++bootfile_fip=immortalwrt-mediatek-filogic-netis_nx31-bl31-uboot.fip ++bootfile_upg=immortalwrt-mediatek-filogic-netis_nx31-squashfs-sysupgrade.itb +bootled_status=blue:status +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 +bootmenu_default=0 diff --git a/package/boot/uboot-mediatek/patches/461-add-netcore-n60-pro.patch b/package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch similarity index 100% rename from package/boot/uboot-mediatek/patches/461-add-netcore-n60-pro.patch rename to package/boot/uboot-mediatek/patches/462-add-netcore-n60-pro.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 76ff54fe96..5937f517f0 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -146,6 +146,20 @@ define U-Boot/nanopi-r4se-rk3399 friendlyarm_nanopi-r4se endef +define U-Boot/rock-4c-plus-rk3399 + $(U-Boot/rk3399/Default) + NAME:=ROCK 4C+ + BUILD_DEVICES:= \ + radxa_rock-4c-plus +endef + +define U-Boot/rock-4se-rk3399 + $(U-Boot/rk3399/Default) + NAME:=ROCK 4SE + BUILD_DEVICES:= \ + radxa_rock-4se +endef + define U-Boot/rock-pi-4-rk3399 $(U-Boot/rk3399/Default) NAME:=ROCK Pi 4 @@ -389,6 +403,8 @@ UBOOT_TARGETS := \ nanopc-t4-rk3399 \ nanopi-r4s-rk3399 \ nanopi-r4se-rk3399 \ + rock-4c-plus-rk3399 \ + rock-4se-rk3399 \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ rock-pi-s-rk3308 \ diff --git a/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic index 62fbdc9343..0201b2729f 100644 --- a/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic @@ -119,6 +119,7 @@ gatonetworks,gdsp) glinet,gl-mt3000) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000" ;; +mercusys,mr80x-v3|\ mercusys,mr90x-v1|\ routerich,ax3000|\ tenbay,wr3000k|\ diff --git a/package/firmware/layerscape/fman-ucode/Makefile b/package/firmware/layerscape/fman-ucode/Makefile index 3dc1bfcb14..2056bc5a99 100644 --- a/package/firmware/layerscape/fman-ucode/Makefile +++ b/package/firmware/layerscape/fman-ucode/Makefile @@ -25,6 +25,8 @@ define Package/layerscape-fman CATEGORY:=Firmware TITLE:=NXP FMan ucode DEPENDS:=@TARGET_layerscape + DEFAULT:=y if TARGET_layerscape_armv8_64b + HIDDEN:=1 endef define Build/Compile diff --git a/package/firmware/layerscape/ls-ddr-phy/Makefile b/package/firmware/layerscape/ls-ddr-phy/Makefile index ce39ea7dc6..322f383bd6 100644 --- a/package/firmware/layerscape/ls-ddr-phy/Makefile +++ b/package/firmware/layerscape/ls-ddr-phy/Makefile @@ -27,6 +27,8 @@ define Package/layerscape-ddr-phy CATEGORY:=Firmware TITLE:=NXP Layerscape DDR PHY firmware DEPENDS:=@TARGET_layerscape + DEFAULT:=y if TARGET_layerscape_armv8_64b + HIDDEN:=1 endef define Build/Compile diff --git a/package/firmware/layerscape/ls-dpl/Makefile b/package/firmware/layerscape/ls-dpl/Makefile index b4b10b9b0d..ade37d7dff 100644 --- a/package/firmware/layerscape/ls-dpl/Makefile +++ b/package/firmware/layerscape/ls-dpl/Makefile @@ -26,6 +26,8 @@ define Package/layerscape-dpl CATEGORY:=Firmware TITLE:=NXP DPL firmware DEPENDS:=@TARGET_layerscape + DEFAULT:=y if TARGET_layerscape_armv8_64b + HIDDEN:=1 endef MAKE_PATH:=config diff --git a/package/firmware/layerscape/ls-mc/Makefile b/package/firmware/layerscape/ls-mc/Makefile index 31ed1f98dc..54b17f3e97 100644 --- a/package/firmware/layerscape/ls-mc/Makefile +++ b/package/firmware/layerscape/ls-mc/Makefile @@ -25,6 +25,8 @@ define Package/layerscape-mc CATEGORY:=Firmware TITLE:=NXP MC firmware DEPENDS:=@TARGET_layerscape + DEFAULT:=y if TARGET_layerscape_armv8_64b + HIDDEN:=1 endef define Build/Compile diff --git a/package/firmware/layerscape/ls-rcw/Makefile b/package/firmware/layerscape/ls-rcw/Makefile index ca72d45b5b..901b0b72ef 100644 --- a/package/firmware/layerscape/ls-rcw/Makefile +++ b/package/firmware/layerscape/ls-rcw/Makefile @@ -25,6 +25,8 @@ define Package/layerscape-rcw CATEGORY:=Firmware TITLE:=NXP Layerscape RCW binaries DEPENDS:=@TARGET_layerscape + DEFAULT:=y if TARGET_layerscape_armv7 + HIDDEN:=1 endef BOARDS := \ diff --git a/package/firmware/linux-firmware/qca_ath12k.mk b/package/firmware/linux-firmware/qca_ath12k.mk index dc719c61af..4f0a3d6bf1 100644 --- a/package/firmware/linux-firmware/qca_ath12k.mk +++ b/package/firmware/linux-firmware/qca_ath12k.mk @@ -5,3 +5,11 @@ define Package/ath12k-firmware-wcn7850/install $(PKG_BUILD_DIR)/ath12k/WCN7850/hw2.0/* $(1)/lib/firmware/ath12k/WCN7850/hw2.0/ endef $(eval $(call BuildPackage,ath12k-firmware-wcn7850)) + +Package/ath12k-firmware-qcn9274 = $(call Package/firmware-default,QCN9274 ath12k firmware) +define Package/ath12k-firmware-qcn9274/install + $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN9274/hw2.0 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/ath12k/QCN9274/hw2.0/* $(1)/lib/firmware/ath12k/QCN9274/hw2.0/ +endef +$(eval $(call BuildPackage,ath12k-firmware-qcn9274)) diff --git a/package/kernel/ath10k-ct/patches/003-ath10k-ct-make-it-compatible-with-the-old-LTS-kernel.patch b/package/kernel/ath10k-ct/patches/003-ath10k-ct-make-it-compatible-with-the-old-LTS-kernel.patch index 632a419258..4f1918cf52 100644 --- a/package/kernel/ath10k-ct/patches/003-ath10k-ct-make-it-compatible-with-the-old-LTS-kernel.patch +++ b/package/kernel/ath10k-ct/patches/003-ath10k-ct-make-it-compatible-with-the-old-LTS-kernel.patch @@ -7,8 +7,7 @@ Rollback some APIs to fix compilation errors. Signed-off-by: Shiji Yang --- ath10k-6.14/ahb.c | 2 +- - ath10k-6.14/mac.c | 5 ++--- - 2 files changed, 3 insertions(+), 4 deletions(-) + 1 files changed, 1 insertions(+), 1 deletions(-) --- a/ath10k-6.14/ahb.c +++ b/ath10k-6.14/ahb.c @@ -21,26 +20,3 @@ Signed-off-by: Shiji Yang }; int ath10k_ahb_init(void) ---- a/ath10k-6.14/mac.c -+++ b/ath10k-6.14/mac.c -@@ -9607,10 +9607,9 @@ exit: - - static void ath10k_sta_rc_update(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, -- struct ieee80211_link_sta *link_sta, -+ struct ieee80211_sta *sta, - u32 changed) - { -- struct ieee80211_sta *sta = link_sta->sta; - struct ath10k *ar = hw->priv; - struct ath10k_sta *arsta = (struct ath10k_sta *)sta->drv_priv; - struct ath10k_vif *arvif = (void *)vif->drv_priv; -@@ -10603,7 +10602,7 @@ static const struct ieee80211_ops ath10k - .reconfig_complete = ath10k_reconfig_complete, - .get_survey = ath10k_get_survey, - .set_bitrate_mask = ath10k_mac_op_set_bitrate_mask, -- .link_sta_rc_update = ath10k_sta_rc_update, -+ .sta_rc_update = ath10k_sta_rc_update, - .offset_tsf = ath10k_offset_tsf, - .get_tsf = ath10k_get_tsf, - .ampdu_action = ath10k_ampdu_action, diff --git a/package/kernel/bcm63xx-cfe/Makefile b/package/kernel/bcm63xx-cfe/Makefile index 8b6fa8010c..18f52a0cda 100644 --- a/package/kernel/bcm63xx-cfe/Makefile +++ b/package/kernel/bcm63xx-cfe/Makefile @@ -35,9 +35,9 @@ define Package/bcm63xx-cfe/install endef define Build/InstallDev - rm -rf $(KERNEL_BUILD_DIR)/$(PKG_NAME) - mkdir -p $(KERNEL_BUILD_DIR)/$(PKG_NAME) - $(CP) -r $(PKG_BUILD_DIR)/* $(KERNEL_BUILD_DIR)/$(PKG_NAME) + rm -rf $(STAGING_DIR_IMAGE)/$(PKG_NAME) + mkdir -p $(STAGING_DIR_IMAGE)/$(PKG_NAME) + $(CP) -r $(PKG_BUILD_DIR)/* $(STAGING_DIR_IMAGE)/$(PKG_NAME) endef $(eval $(call BuildPackage,bcm63xx-cfe)) diff --git a/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c b/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c index 9876dee90f..ad2e0ca863 100644 --- a/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c +++ b/package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c @@ -674,7 +674,7 @@ static void gpio_keys_irq_close(struct gpio_keys_button_dev *bdev) } } -static int gpio_keys_remove(struct platform_device *pdev) +static void gpio_keys_remove(struct platform_device *pdev) { struct gpio_keys_button_dev *bdev = platform_get_drvdata(pdev); @@ -684,13 +684,11 @@ static int gpio_keys_remove(struct platform_device *pdev) gpio_keys_polled_close(bdev); else gpio_keys_irq_close(bdev); - - return 0; } static struct platform_driver gpio_keys_driver = { .probe = gpio_keys_probe, - .remove = gpio_keys_remove, + .remove_new = gpio_keys_remove, .driver = { .name = "gpio-keys", .of_match_table = of_match_ptr(gpio_keys_of_match), @@ -699,7 +697,7 @@ static struct platform_driver gpio_keys_driver = { static struct platform_driver gpio_keys_polled_driver = { .probe = gpio_keys_polled_probe, - .remove = gpio_keys_remove, + .remove_new = gpio_keys_remove, .driver = { .name = "gpio-keys-polled", .of_match_table = of_match_ptr(gpio_keys_polled_of_match), diff --git a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c index 20a63716a3..8c976565a0 100644 --- a/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c +++ b/package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c @@ -2780,7 +2780,7 @@ static int ltq_mei_probe(struct platform_device *pdev) return 0; } -static int ltq_mei_remove(struct platform_device *pdev) +static void ltq_mei_remove(struct platform_device *pdev) { int i = 0; int num; @@ -2794,7 +2794,6 @@ static int ltq_mei_remove(struct platform_device *pdev) IFX_MEI_ExitDevice (i); } } - return 0; } static const struct of_device_id ltq_mei_match[] = { @@ -2804,7 +2803,7 @@ static const struct of_device_id ltq_mei_match[] = { static struct platform_driver ltq_mei_driver = { .probe = ltq_mei_probe, - .remove = ltq_mei_remove, + .remove_new = ltq_mei_remove, .driver = { .name = "lantiq,mei-xway", .of_match_table = ltq_mei_match, diff --git a/package/kernel/lantiq/ltq-atm/src/ltq_atm.c b/package/kernel/lantiq/ltq-atm/src/ltq_atm.c index 6b1e0321b3..70eb3e88e0 100644 --- a/package/kernel/lantiq/ltq-atm/src/ltq_atm.c +++ b/package/kernel/lantiq/ltq-atm/src/ltq_atm.c @@ -1865,7 +1865,7 @@ INIT_PRIV_DATA_FAIL: return ret; } -static int ltq_atm_remove(struct platform_device *pdev) +static void ltq_atm_remove(struct platform_device *pdev) { int port_num; struct ltq_atm_ops *ops = platform_get_drvdata(pdev); @@ -1885,13 +1885,11 @@ static int ltq_atm_remove(struct platform_device *pdev) ops->shutdown(); clear_priv_data(); - - return 0; } static struct platform_driver ltq_atm_driver = { .probe = ltq_atm_probe, - .remove = ltq_atm_remove, + .remove_new = ltq_atm_remove, .driver = { .name = "atm", .of_match_table = ltq_atm_match, diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c index e44e84c03c..684f3c4df0 100644 --- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c +++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c @@ -143,7 +143,7 @@ static int ltq_deu_probe(struct platform_device *pdev) * \ingroup IFX_DEU_FUNCTIONS * \brief remove the loaded crypto algorithms */ -static int ltq_deu_remove(struct platform_device *pdev) +static void ltq_deu_remove(struct platform_device *pdev) { //#ifdef CONFIG_CRYPTO_DEV_PWR_SAVE_MODE #if defined(CONFIG_CRYPTO_DEV_DES) @@ -168,8 +168,6 @@ static int ltq_deu_remove(struct platform_device *pdev) ifxdeu_fini_md5_hmac (); #endif printk("DEU has exited successfully\n"); - - return 0; } @@ -193,7 +191,7 @@ MODULE_DEVICE_TABLE(of, ltq_deu_match); static struct platform_driver ltq_deu_driver = { .probe = ltq_deu_probe, - .remove = ltq_deu_remove, + .remove_new = ltq_deu_remove, .driver = { .name = "deu", .of_match_table = ltq_deu_match, diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c index 5e5535348d..23460501e1 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c @@ -1566,7 +1566,7 @@ INIT_PRIV_DATA_FAIL: * Output: * none */ -static int ltq_ptm_remove(struct platform_device *pdev) +static void ltq_ptm_remove(struct platform_device *pdev) { int i; @@ -1591,13 +1591,11 @@ static int ltq_ptm_remove(struct platform_device *pdev) ifx_ptm_uninit_chip(); clear_priv_data(); - - return 0; } static struct platform_driver ltq_ptm_driver = { .probe = ltq_ptm_probe, - .remove = ltq_ptm_remove, + .remove_new = ltq_ptm_remove, .driver = { .name = "ptm", .of_match_table = ltq_ptm_match, diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c index c5bbd9fd87..b3d14122d6 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c @@ -1079,7 +1079,7 @@ INIT_PRIV_DATA_FAIL: return ret; } -static int ltq_ptm_remove(struct platform_device *pdev) +static void ltq_ptm_remove(struct platform_device *pdev) { int i; ifx_mei_atm_showtime_enter = NULL; @@ -1103,8 +1103,6 @@ static int ltq_ptm_remove(struct platform_device *pdev) ifx_ptm_uninit_chip(); clear_priv_data(); - - return 0; } #ifndef MODULE @@ -1135,7 +1133,7 @@ static int __init queue_gamma_map_setup(char *line) #endif static struct platform_driver ltq_ptm_driver = { .probe = ltq_ptm_probe, - .remove = ltq_ptm_remove, + .remove_new = ltq_ptm_remove, .driver = { .name = "ptm", .of_match_table = ltq_ptm_match, diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index c9c41054d8..77f5928d33 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -658,7 +658,7 @@ $(eval $(call KernelPackage,dsa-realtek)) define KernelPackage/dsa-rtl8366rb SUBMENU:=$(NETWORK_DEVICES_MENU) - TITLE:=Realtek RTL8365MB switch DSA support + TITLE:=Realtek RTL8366RB switch DSA support DEPENDS:=+kmod-dsa-realtek @!TARGET_x86 @!TARGET_bcm47xx @!TARGET_uml KCONFIG:= \ CONFIG_NET_DSA_REALTEK_RTL8366RB \ diff --git a/package/kernel/linux/modules/usb.mk b/package/kernel/linux/modules/usb.mk index 1d6e2f3df7..0ac20f2c67 100644 --- a/package/kernel/linux/modules/usb.mk +++ b/package/kernel/linux/modules/usb.mk @@ -538,7 +538,7 @@ $(eval $(call KernelPackage,usb-dwc3-octeon)) define KernelPackage/usb-dwc3-qcom TITLE:=DWC3 Qualcomm USB driver - DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_qualcommax) +kmod-usb-dwc3 + DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x||TARGET_qualcommax||TARGET_qualcommbe) +kmod-usb-dwc3 KCONFIG:= CONFIG_USB_DWC3_QCOM FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3-qcom.ko AUTOLOAD:=$(call AutoLoad,53,dwc3-qcom,1) diff --git a/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch b/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch index b13bc33498..aa953c00fb 100644 --- a/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch +++ b/package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -9919,6 +9919,21 @@ static int ath10k_mac_init_rd(struct ath +@@ -9920,6 +9920,21 @@ static int ath10k_mac_init_rd(struct ath return 0; } @@ -22,7 +22,7 @@ int ath10k_mac_register(struct ath10k *ar) { static const u32 cipher_suites[] = { -@@ -10281,6 +10296,12 @@ int ath10k_mac_register(struct ath10k *a +@@ -10282,6 +10297,12 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; diff --git a/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch b/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch index fc41f5f151..4f555d704e 100644 --- a/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch +++ b/package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch @@ -40,7 +40,7 @@ Signed-off-by: Mathias Kresin if (ret) --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -10297,7 +10297,7 @@ int ath10k_mac_register(struct ath10k *a +@@ -10298,7 +10298,7 @@ int ath10k_mac_register(struct ath10k *a ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; #ifdef CPTCFG_MAC80211_LEDS diff --git a/package/kernel/mac80211/patches/ath11k/201-wifi-ath11k-Support-setting-bdf-addr-and-caldb-addr-.patch b/package/kernel/mac80211/patches/ath11k/201-wifi-ath11k-Support-setting-bdf-addr-and-caldb-addr-.patch index 109daf02f2..81aee57546 100644 --- a/package/kernel/mac80211/patches/ath11k/201-wifi-ath11k-Support-setting-bdf-addr-and-caldb-addr-.patch +++ b/package/kernel/mac80211/patches/ath11k/201-wifi-ath11k-Support-setting-bdf-addr-and-caldb-addr-.patch @@ -41,7 +41,7 @@ Signed-off-by: Ziyang Huang } } else { ab->qmi.target_mem[idx].paddr = 0; -@@ -2292,6 +2296,7 @@ static int ath11k_qmi_load_file_target_m +@@ -2295,6 +2299,7 @@ static int ath11k_qmi_load_file_target_m struct qmi_wlanfw_bdf_download_resp_msg_v01 resp; struct qmi_txn txn; const u8 *temp = data; @@ -49,7 +49,7 @@ Signed-off-by: Ziyang Huang void __iomem *bdf_addr = NULL; int ret = 0; u32 remaining = len; -@@ -2303,7 +2308,9 @@ static int ath11k_qmi_load_file_target_m +@@ -2306,7 +2311,9 @@ static int ath11k_qmi_load_file_target_m memset(&resp, 0, sizeof(resp)); if (ab->hw_params.fixed_bdf_addr) { diff --git a/package/kernel/mac80211/patches/ath11k/923-wifi-ath11k-update-hif_and-pci_ops-for-QCN6122.patch b/package/kernel/mac80211/patches/ath11k/923-wifi-ath11k-update-hif_and-pci_ops-for-QCN6122.patch index 9c9caef4f2..8497c3a8c9 100644 --- a/package/kernel/mac80211/patches/ath11k/923-wifi-ath11k-update-hif_and-pci_ops-for-QCN6122.patch +++ b/package/kernel/mac80211/patches/ath11k/923-wifi-ath11k-update-hif_and-pci_ops-for-QCN6122.patch @@ -91,9 +91,9 @@ Signed-off-by: George Moussalem #endif /* _HIF_H_ */ --- a/drivers/net/wireless/ath/ath11k/qmi.c +++ b/drivers/net/wireless/ath/ath11k/qmi.c -@@ -2184,6 +2184,8 @@ static int ath11k_qmi_request_device_inf - ab->mem = bar_addr_va; - ab->mem_len = resp.bar_size; +@@ -2187,6 +2187,8 @@ static int ath11k_qmi_request_device_inf + if (!ab->hw_params.ce_remap) + ab->mem_ce = ab->mem; + ath11k_hif_config_static_window(ab); + diff --git a/package/kernel/mac80211/patches/ath11k/924-wifi-ath11k-add-multipd-support-for-QCN6122.patch b/package/kernel/mac80211/patches/ath11k/924-wifi-ath11k-add-multipd-support-for-QCN6122.patch index e6170a74e4..5b0c58dd94 100644 --- a/package/kernel/mac80211/patches/ath11k/924-wifi-ath11k-add-multipd-support-for-QCN6122.patch +++ b/package/kernel/mac80211/patches/ath11k/924-wifi-ath11k-add-multipd-support-for-QCN6122.patch @@ -89,7 +89,7 @@ Signed-off-by: George Moussalem /* SMBIOS type containing Board Data File Name Extension */ #define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8 -@@ -945,6 +948,7 @@ struct ath11k_base { +@@ -951,6 +954,7 @@ struct ath11k_base { struct list_head peers; wait_queue_head_t peer_mapping_wq; u8 mac_addr[ETH_ALEN]; diff --git a/package/kernel/mac80211/patches/ath11k/932-wifi-ath11k-poll-reo-status-ipq5018.patch b/package/kernel/mac80211/patches/ath11k/932-wifi-ath11k-poll-reo-status-ipq5018.patch index d89fb92e22..8cb7bd6b08 100644 --- a/package/kernel/mac80211/patches/ath11k/932-wifi-ath11k-poll-reo-status-ipq5018.patch +++ b/package/kernel/mac80211/patches/ath11k/932-wifi-ath11k-poll-reo-status-ipq5018.patch @@ -132,7 +132,7 @@ Signed-off-by: Sriram R }; /* HTT definitions */ -@@ -1712,5 +1718,6 @@ void ath11k_dp_shadow_init_timer(struct +@@ -1689,5 +1695,6 @@ void ath11k_dp_shadow_init_timer(struct struct ath11k_hp_update_timer *update_timer, u32 interval, u32 ring_id); void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); diff --git a/package/kernel/mac80211/patches/ath12k/001-wifi-ath12k-add-11d-scan-offload-support-and-handle-country-code-for-WCN7850.patch b/package/kernel/mac80211/patches/ath12k/001-wifi-ath12k-add-11d-scan-offload-support-and-handle-country-code-for-WCN7850.patch index caa4e20f97..2afd7f8b0e 100644 --- a/package/kernel/mac80211/patches/ath12k/001-wifi-ath12k-add-11d-scan-offload-support-and-handle-country-code-for-WCN7850.patch +++ b/package/kernel/mac80211/patches/ath12k/001-wifi-ath12k-add-11d-scan-offload-support-and-handle-country-code-for-WCN7850.patch @@ -532,7 +532,7 @@ Acked-by: Jeff Johnson return ret; } -@@ -5994,7 +6009,7 @@ static int ath12k_mac_start(struct ath12 +@@ -5995,7 +6010,7 @@ static int ath12k_mac_start(struct ath12 /* TODO: Do we need to enable ANI? */ @@ -541,7 +541,7 @@ Acked-by: Jeff Johnson ar->num_started_vdevs = 0; ar->num_created_vdevs = 0; -@@ -6174,6 +6189,9 @@ static void ath12k_mac_stop(struct ath12 +@@ -6175,6 +6190,9 @@ static void ath12k_mac_stop(struct ath12 cancel_delayed_work_sync(&ar->scan.timeout); cancel_work_sync(&ar->regd_update_work); cancel_work_sync(&ar->ab->rfkill_work); @@ -551,7 +551,7 @@ Acked-by: Jeff Johnson spin_lock_bh(&ar->data_lock); list_for_each_entry_safe(ppdu_stats, tmp, &ar->ppdu_stats_info, list) { -@@ -6420,6 +6438,117 @@ static void ath12k_mac_op_update_vif_off +@@ -6421,6 +6439,117 @@ static void ath12k_mac_op_update_vif_off ath12k_mac_update_vif_offload(arvif); } @@ -669,7 +669,7 @@ Acked-by: Jeff Johnson static int ath12k_mac_vdev_create(struct ath12k *ar, struct ieee80211_vif *vif) { struct ath12k_hw *ah = ar->ah; -@@ -6534,6 +6663,7 @@ static int ath12k_mac_vdev_create(struct +@@ -6535,6 +6664,7 @@ static int ath12k_mac_vdev_create(struct arvif->vdev_id, ret); goto err_peer_del; } @@ -677,7 +677,7 @@ Acked-by: Jeff Johnson break; case WMI_VDEV_TYPE_STA: param_id = WMI_STA_PS_PARAM_RX_WAKE_POLICY; -@@ -6572,6 +6702,13 @@ static int ath12k_mac_vdev_create(struct +@@ -6573,6 +6703,13 @@ static int ath12k_mac_vdev_create(struct arvif->vdev_id, ret); goto err_peer_del; } @@ -691,7 +691,7 @@ Acked-by: Jeff Johnson break; default: break; -@@ -6912,6 +7049,11 @@ static void ath12k_mac_op_remove_interfa +@@ -6913,6 +7050,11 @@ static void ath12k_mac_op_remove_interfa ath12k_dbg(ab, ATH12K_DBG_MAC, "mac remove interface (vdev %d)\n", arvif->vdev_id); @@ -703,7 +703,7 @@ Acked-by: Jeff Johnson if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { ret = ath12k_peer_delete(ar, arvif->vdev_id, vif->addr); if (ret) -@@ -7752,6 +7894,14 @@ ath12k_mac_op_unassign_vif_chanctx(struc +@@ -7753,6 +7895,14 @@ ath12k_mac_op_unassign_vif_chanctx(struc ar->num_started_vdevs == 1 && ar->monitor_vdev_created) ath12k_mac_monitor_stop(ar); @@ -718,7 +718,7 @@ Acked-by: Jeff Johnson mutex_unlock(&ar->conf_mutex); } -@@ -8290,6 +8440,14 @@ ath12k_mac_op_reconfig_complete(struct i +@@ -8291,6 +8441,14 @@ ath12k_mac_op_reconfig_complete(struct i ath12k_warn(ar->ab, "pdev %d successfully recovered\n", ar->pdev->pdev_id); @@ -733,7 +733,7 @@ Acked-by: Jeff Johnson if (ab->is_reset) { recovery_count = atomic_inc_return(&ab->recovery_count); -@@ -9339,6 +9497,9 @@ static void ath12k_mac_setup(struct ath1 +@@ -9340,6 +9498,9 @@ static void ath12k_mac_setup(struct ath1 INIT_WORK(&ar->wmi_mgmt_tx_work, ath12k_mgmt_over_wmi_tx_work); skb_queue_head_init(&ar->wmi_mgmt_tx_queue); diff --git a/package/kernel/mac80211/patches/ath12k/002-wifi-ath12k-Fetch-regdb.bin-file-from-board-2.bin.patch b/package/kernel/mac80211/patches/ath12k/002-wifi-ath12k-Fetch-regdb.bin-file-from-board-2.bin.patch new file mode 100644 index 0000000000..67d62f9257 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/002-wifi-ath12k-Fetch-regdb.bin-file-from-board-2.bin.patch @@ -0,0 +1,67 @@ +From 24f587572acf7509127dbdfcbf1b681ef84eeba0 Mon Sep 17 00:00:00 2001 +From: Aaradhana Sahu +Date: Thu, 16 Jan 2025 08:58:35 +0530 +Subject: [PATCH] wifi: ath12k: Fetch regdb.bin file from board-2.bin + +Currently, ath12k_core_fetch_regdb() finds regdb.bin file through +board id's but in board-2.bin file regdb.bin file is present with +default board id because of which regdb.bin is not fetched. + +Add support to fetch regdb.bin file from board-2.bin through +default board id. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.3.1-00173-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Aaradhana Sahu +Reviewed-by: Aditya Kumar Singh +Link: https://patch.msgid.link/20250116032835.118397-1-quic_aarasahu@quicinc.com +Signed-off-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/core.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/core.c ++++ b/drivers/net/wireless/ath/ath12k/core.c +@@ -161,7 +161,7 @@ EXPORT_SYMBOL(ath12k_core_resume); + + static int __ath12k_core_create_board_name(struct ath12k_base *ab, char *name, + size_t name_len, bool with_variant, +- bool bus_type_mode) ++ bool bus_type_mode, bool with_default) + { + /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ + char variant[9 + ATH12K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; +@@ -192,7 +192,9 @@ static int __ath12k_core_create_board_na + "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", + ath12k_bus_str(ab->hif.bus), + ab->qmi.target.chip_id, +- ab->qmi.target.board_id, variant); ++ with_default ? ++ ATH12K_BOARD_ID_DEFAULT : ab->qmi.target.board_id, ++ variant); + break; + } + +@@ -204,19 +206,19 @@ static int __ath12k_core_create_board_na + static int ath12k_core_create_board_name(struct ath12k_base *ab, char *name, + size_t name_len) + { +- return __ath12k_core_create_board_name(ab, name, name_len, true, false); ++ return __ath12k_core_create_board_name(ab, name, name_len, true, false, false); + } + + static int ath12k_core_create_fallback_board_name(struct ath12k_base *ab, char *name, + size_t name_len) + { +- return __ath12k_core_create_board_name(ab, name, name_len, false, false); ++ return __ath12k_core_create_board_name(ab, name, name_len, false, false, true); + } + + static int ath12k_core_create_bus_type_board_name(struct ath12k_base *ab, char *name, + size_t name_len) + { +- return __ath12k_core_create_board_name(ab, name, name_len, false, true); ++ return __ath12k_core_create_board_name(ab, name, name_len, false, true, true); + } + + const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, diff --git a/package/kernel/mac80211/patches/ath12k/102-wifi-ath12k-limit-WMI_SCAN_CHAN_LIST_CMDID-arg.patch b/package/kernel/mac80211/patches/ath12k/102-wifi-ath12k-limit-WMI_SCAN_CHAN_LIST_CMDID-arg.patch new file mode 100644 index 0000000000..5b1628023f --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/102-wifi-ath12k-limit-WMI_SCAN_CHAN_LIST_CMDID-arg.patch @@ -0,0 +1,153 @@ +From patchwork Mon Mar 10 13:28:18 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Mantas +X-Patchwork-Id: 14010032 +X-Patchwork-Delegate: quic_jjohnson@quicinc.com +Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com + [209.85.167.41]) + (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ADD522A4DA + for ; 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+ Mon, 10 Mar 2025 06:28:46 -0700 (PDT) +Received: from [127.0.1.1] ([78.62.132.154]) + by smtp.gmail.com with ESMTPSA id + 2adb3069b0e04-5498b1bcaecsm1460408e87.200.2025.03.10.06.28.45 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Mon, 10 Mar 2025 06:28:45 -0700 (PDT) +From: Mantas Pucka +Date: Mon, 10 Mar 2025 15:28:18 +0200 +Subject: [PATCH ath-next] wifi: ath12k: limit WMI_SCAN_CHAN_LIST_CMDID + argument size +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +Message-Id: <20250310-limit-wmi-chanlist-v1-1-8f0fb45459a7@8devices.com> +X-B4-Tracking: v=1; b=H4sIAPHozmcC/x2MSwqEMBAFryK9tiGJ+MGriIuMtvpAM0MSHEG8u + 9FNQVG8d1IQDwnUZid52RHwdUl0ntGwWDcLY0xORplSFVrxig2R/xv46StCZF0Pn2Y0ibaiNPx + 5mXC8px3ZuLCTI1J/XTfUqQSebgAAAA== +X-Change-ID: 20250310-limit-wmi-chanlist-17cb8d27cba6 +To: ath12k@lists.infradead.org +Cc: Johannes Berg , + Jeff Johnson , linux-wireless@vger.kernel.org, + linux-kernel@vger.kernel.org, Mantas Pucka +X-Mailer: b4 0.14.2 + +When using BDF with both 5GHz and 6GHz bands enabled on QCN9274, interface +fails to start. It happens because FW fails to process +WMI_SCAN_CHAN_LIST_CMDID with argument size >2048, resulting in a command +timeout. The current code allows splitting channel list across multiple WMI +commands but uses WMI max_msg_len (4096) as chunk size, which is still too +large. + +Fix this by limiting the number of channels sent at once, using the value +specified in WMI interface description [1]. + +[1] https://git.codelinaro.org/clo/qsdk/platform/vendor/qcom-opensource/wlan/fw-api/-/blob/NHSS.QSDK.13.0.0.6/fw/wmi_unified.h#L6459 + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Mantas Pucka +--- + drivers/net/wireless/ath/ath12k/wmi.c | 3 +++ + drivers/net/wireless/ath/ath12k/wmi.h | 2 ++ + 2 files changed, 5 insertions(+) + + +--- +base-commit: 42aa76e608ca845c98e79f9e23af0bdb07b2eb1d +change-id: 20250310-limit-wmi-chanlist-17cb8d27cba6 + +Best regards, + +--- a/drivers/net/wireless/ath/ath12k/wmi.c ++++ b/drivers/net/wireless/ath/ath12k/wmi.c +@@ -2558,6 +2558,9 @@ int ath12k_wmi_send_scan_chan_list_cmd(s + max_chan_limit = (wmi->wmi_ab->max_msg_len[ar->pdev_idx] - len) / + sizeof(*chan_info); + ++ if (max_chan_limit > WMI_MAX_NUM_CHAN_PER_WMI_CMD) ++ max_chan_limit = WMI_MAX_NUM_CHAN_PER_WMI_CMD; ++ + num_send_chans = min(arg->nallchans, max_chan_limit); + + arg->nallchans -= num_send_chans; +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -3743,6 +3743,8 @@ struct wmi_stop_scan_cmd { + __le32 pdev_id; + } __packed; + ++#define WMI_MAX_NUM_CHAN_PER_WMI_CMD 58 ++ + struct ath12k_wmi_scan_chan_list_arg { + u32 pdev_id; + u16 nallchans; diff --git a/package/kernel/mac80211/patches/ath12k/103-wifi-ath12k-fix-5GHz-operation-on-wideband-QCN.patch b/package/kernel/mac80211/patches/ath12k/103-wifi-ath12k-fix-5GHz-operation-on-wideband-QCN.patch new file mode 100644 index 0000000000..619883cb9a --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/103-wifi-ath12k-fix-5GHz-operation-on-wideband-QCN.patch @@ -0,0 +1,137 @@ +From patchwork Thu Mar 13 09:00:56 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Mantas +X-Patchwork-Id: 14014575 +X-Patchwork-Delegate: quic_jjohnson@quicinc.com +Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com + [209.85.167.49]) + (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id F210C2641F0 + for ; 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This prevents the +addition of HT and VHT capabilities for the 5GHz band. Since QCN9274 is +capable of operating in multiple bands, remove the 6GHz support check and +exception for single_pdev_only (i.e. WCN7850). + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Mantas Pucka +--- + drivers/net/wireless/ath/ath12k/mac.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + + +--- +base-commit: 42aa76e608ca845c98e79f9e23af0bdb07b2eb1d +change-id: 20250313-ath12-wideband-caps-24b281788dfe + +Best regards, + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -5185,9 +5185,7 @@ static void ath12k_mac_setup_ht_vht_cap( + rate_cap_rx_chainmask); + } + +- if (cap->supported_bands & WMI_HOST_WLAN_5G_CAP && +- (ar->ab->hw_params->single_pdev_only || +- !ar->supports_6ghz)) { ++ if (cap->supported_bands & WMI_HOST_WLAN_5G_CAP) { + band = &ar->mac.sbands[NL80211_BAND_5GHZ]; + ht_cap = cap->band[NL80211_BAND_5GHZ].ht_cap_info; + if (ht_cap_info) diff --git a/package/kernel/mac80211/patches/ath12k/104-1-wifi-ath12k-push-HE-MU-MIMO-params-to-hardware.patch b/package/kernel/mac80211/patches/ath12k/104-1-wifi-ath12k-push-HE-MU-MIMO-params-to-hardware.patch new file mode 100644 index 0000000000..8c0e67a8bf --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-1-wifi-ath12k-push-HE-MU-MIMO-params-to-hardware.patch @@ -0,0 +1,469 @@ +From patchwork Wed Sep 18 21:20:48 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:06 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:06 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Muna Sinada , + "Jeff + Johnson" +Subject: [PATCH V8 1/9] wifi: ath12k: push HE MU-MIMO params to hardware +Date: Wed, 18 Sep 2024 14:20:48 -0700 +Message-ID: <20240918212056.4137076-2-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-ORIG-GUID: QTgqLsl2p5OGLwWEQsGrsmA8q68U11H8 +X-Proofpoint-GUID: QTgqLsl2p5OGLwWEQsGrsmA8q68U11H8 +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + malwarescore=0 suspectscore=0 + bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 + mlxlogscore=999 impostorscore=0 mlxscore=0 priorityscore=1501 phishscore=0 + classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 + definitions=main-2409180140 + +Currently, only the HE IE in management frames is updated with +respect to MU-MIMO configurations, but this change is not +reflected in the hardware. Add support to propagate MU-MIMO +configurations to the hardware as well. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: Muna Sinada +Signed-off-by: Muna Sinada +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 215 +++++++++++++++++--------- + drivers/net/wireless/ath/ath12k/mac.h | 15 ++ + drivers/net/wireless/ath/ath12k/wmi.h | 28 +--- + 3 files changed, 156 insertions(+), 102 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -2851,6 +2851,108 @@ static int ath12k_setup_peer_smps(struct + ath12k_smps_map[smps]); + } + ++static int ath12k_mac_set_he_txbf_conf(struct ath12k_vif *arvif) ++{ ++ struct ath12k *ar = arvif->ar; ++ u32 param = WMI_VDEV_PARAM_SET_HEMU_MODE; ++ u32 value = 0; ++ int ret; ++ ++ if (!arvif->vif->bss_conf.he_support) ++ return 0; ++ ++ if (arvif->vif->bss_conf.he_su_beamformer) { ++ value |= u32_encode_bits(HE_SU_BFER_ENABLE, HE_MODE_SU_TX_BFER); ++ if (arvif->vif->bss_conf.he_mu_beamformer && ++ arvif->vdev_type == WMI_VDEV_TYPE_AP) ++ value |= u32_encode_bits(HE_MU_BFER_ENABLE, HE_MODE_MU_TX_BFER); ++ } ++ ++ if (arvif->vif->type != NL80211_IFTYPE_MESH_POINT) { ++ value |= u32_encode_bits(HE_DL_MUOFDMA_ENABLE, HE_MODE_DL_OFDMA) | ++ u32_encode_bits(HE_UL_MUOFDMA_ENABLE, HE_MODE_UL_OFDMA); ++ ++ if (arvif->vif->bss_conf.he_full_ul_mumimo) ++ value |= u32_encode_bits(HE_UL_MUMIMO_ENABLE, HE_MODE_UL_MUMIMO); ++ ++ if (arvif->vif->bss_conf.he_su_beamformee) ++ value |= u32_encode_bits(HE_SU_BFEE_ENABLE, HE_MODE_SU_TX_BFEE); ++ } ++ ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, value); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to set vdev %d HE MU mode: %d\n", ++ arvif->vdev_id, ret); ++ return ret; ++ } ++ ++ param = WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE; ++ value = u32_encode_bits(HE_VHT_SOUNDING_MODE_ENABLE, HE_VHT_SOUNDING_MODE) | ++ u32_encode_bits(HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE, ++ HE_TRIG_NONTRIG_SOUNDING_MODE); ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, ++ param, value); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to set vdev %d sounding mode: %d\n", ++ arvif->vdev_id, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ath12k_mac_vif_recalc_sta_he_txbf(struct ath12k *ar, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta_he_cap *he_cap, ++ int *hemode) ++{ ++ struct ieee80211_he_cap_elem he_cap_elem = {}; ++ struct ieee80211_sta_he_cap *cap_band; ++ struct cfg80211_chan_def def; ++ ++ if (!vif->bss_conf.he_support) ++ return 0; ++ ++ if (vif->type != NL80211_IFTYPE_STATION) ++ return -EINVAL; ++ ++ if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) ++ return -EINVAL; ++ ++ if (def.chan->band == NL80211_BAND_2GHZ) ++ cap_band = &ar->mac.iftype[NL80211_BAND_2GHZ][vif->type].he_cap; ++ else ++ cap_band = &ar->mac.iftype[NL80211_BAND_5GHZ][vif->type].he_cap; ++ ++ memcpy(&he_cap_elem, &cap_band->he_cap_elem, sizeof(he_cap_elem)); ++ ++ *hemode = 0; ++ if (HECAP_PHY_SUBFME_GET(he_cap_elem.phy_cap_info)) { ++ if (HECAP_PHY_SUBFMR_GET(he_cap->he_cap_elem.phy_cap_info)) ++ *hemode |= u32_encode_bits(HE_SU_BFEE_ENABLE, HE_MODE_SU_TX_BFEE); ++ if (HECAP_PHY_MUBFMR_GET(he_cap->he_cap_elem.phy_cap_info)) ++ *hemode |= u32_encode_bits(HE_MU_BFEE_ENABLE, HE_MODE_MU_TX_BFEE); ++ } ++ ++ if (vif->type != NL80211_IFTYPE_MESH_POINT) { ++ *hemode |= u32_encode_bits(HE_DL_MUOFDMA_ENABLE, HE_MODE_DL_OFDMA) | ++ u32_encode_bits(HE_UL_MUOFDMA_ENABLE, HE_MODE_UL_OFDMA); ++ ++ if (HECAP_PHY_ULMUMIMO_GET(he_cap_elem.phy_cap_info)) ++ if (HECAP_PHY_ULMUMIMO_GET(he_cap->he_cap_elem.phy_cap_info)) ++ *hemode |= u32_encode_bits(HE_UL_MUMIMO_ENABLE, ++ HE_MODE_UL_MUMIMO); ++ ++ if (u32_get_bits(*hemode, HE_MODE_MU_TX_BFEE)) ++ *hemode |= u32_encode_bits(HE_SU_BFEE_ENABLE, HE_MODE_SU_TX_BFEE); ++ ++ if (u32_get_bits(*hemode, HE_MODE_MU_TX_BFER)) ++ *hemode |= u32_encode_bits(HE_SU_BFER_ENABLE, HE_MODE_SU_TX_BFER); ++ } ++ ++ return 0; ++} ++ + static void ath12k_bss_assoc(struct ath12k *ar, + struct ath12k_vif *arvif, + struct ieee80211_bss_conf *bss_conf) +@@ -2858,9 +2960,11 @@ static void ath12k_bss_assoc(struct ath1 + struct ieee80211_vif *vif = arvif->vif; + struct ath12k_wmi_vdev_up_params params = {}; + struct ath12k_wmi_peer_assoc_arg peer_arg; ++ struct ieee80211_sta_he_cap he_cap; + struct ieee80211_sta *ap_sta; + struct ath12k_peer *peer; + bool is_auth = false; ++ u32 hemode = 0; + int ret; + + lockdep_assert_held(&ar->conf_mutex); +@@ -2880,8 +2984,29 @@ static void ath12k_bss_assoc(struct ath1 + + ath12k_peer_assoc_prepare(ar, vif, ap_sta, &peer_arg, false); + ++ /* he_cap here is updated at assoc success for sta mode only */ ++ he_cap = ap_sta->deflink.he_cap; ++ ++ /* ap_sta->deflink.he_cap must be protected by rcu_read_lock */ ++ ret = ath12k_mac_vif_recalc_sta_he_txbf(ar, vif, &he_cap, &hemode); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to recalc he txbf for vdev %i on bss %pM: %d\n", ++ arvif->vdev_id, bss_conf->bssid, ret); ++ rcu_read_unlock(); ++ return; ++ } ++ + rcu_read_unlock(); + ++ /* keep this before ath12k_wmi_send_peer_assoc_cmd() */ ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, ++ WMI_VDEV_PARAM_SET_HEMU_MODE, hemode); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to submit vdev param txbf 0x%x: %d\n", ++ hemode, ret); ++ return; ++ } ++ + ret = ath12k_wmi_send_peer_assoc_cmd(ar, &peer_arg); + if (ret) { + ath12k_warn(ar->ab, "failed to run peer assoc for %pM vdev %i: %d\n", +@@ -3220,6 +3345,13 @@ static void ath12k_mac_bss_info_changed( + ether_addr_copy(arvif->bssid, info->bssid); + + if (changed & BSS_CHANGED_BEACON_ENABLED) { ++ if (info->enable_beacon) { ++ ret = ath12k_mac_set_he_txbf_conf(arvif); ++ if (ret) ++ ath12k_warn(ar->ab, ++ "failed to set HE TXBF config for vdev: %d\n", ++ arvif->vdev_id); ++ } + ath12k_control_beaconing(arvif, info); + + if (arvif->is_up && vif->bss_conf.he_support && +@@ -5351,11 +5483,14 @@ static void ath12k_mac_copy_he_cap(struc + + he_cap_elem->mac_cap_info[1] &= + IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_MASK; +- ++ he_cap_elem->phy_cap_info[0] &= ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; ++ he_cap_elem->phy_cap_info[0] &= ++ ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; + he_cap_elem->phy_cap_info[5] &= + ~IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; +- he_cap_elem->phy_cap_info[5] &= +- ~IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; + he_cap_elem->phy_cap_info[5] |= num_tx_chains - 1; + + switch (iftype) { +@@ -6317,71 +6452,6 @@ static int ath12k_mac_setup_vdev_create_ + return 0; + } + +-static u32 +-ath12k_mac_prepare_he_mode(struct ath12k_pdev *pdev, u32 viftype) +-{ +- struct ath12k_pdev_cap *pdev_cap = &pdev->cap; +- struct ath12k_band_cap *cap_band = NULL; +- u32 *hecap_phy_ptr = NULL; +- u32 hemode; +- +- if (pdev->cap.supported_bands & WMI_HOST_WLAN_2G_CAP) +- cap_band = &pdev_cap->band[NL80211_BAND_2GHZ]; +- else +- cap_band = &pdev_cap->band[NL80211_BAND_5GHZ]; +- +- hecap_phy_ptr = &cap_band->he_cap_phy_info[0]; +- +- hemode = u32_encode_bits(HE_SU_BFEE_ENABLE, HE_MODE_SU_TX_BFEE) | +- u32_encode_bits(HECAP_PHY_SUBFMR_GET(hecap_phy_ptr), +- HE_MODE_SU_TX_BFER) | +- u32_encode_bits(HECAP_PHY_ULMUMIMO_GET(hecap_phy_ptr), +- HE_MODE_UL_MUMIMO); +- +- /* TODO: WDS and other modes */ +- if (viftype == NL80211_IFTYPE_AP) { +- hemode |= u32_encode_bits(HECAP_PHY_MUBFMR_GET(hecap_phy_ptr), +- HE_MODE_MU_TX_BFER) | +- u32_encode_bits(HE_DL_MUOFDMA_ENABLE, HE_MODE_DL_OFDMA) | +- u32_encode_bits(HE_UL_MUOFDMA_ENABLE, HE_MODE_UL_OFDMA); +- } else { +- hemode |= u32_encode_bits(HE_MU_BFEE_ENABLE, HE_MODE_MU_TX_BFEE); +- } +- +- return hemode; +-} +- +-static int ath12k_set_he_mu_sounding_mode(struct ath12k *ar, +- struct ath12k_vif *arvif) +-{ +- u32 param_id, param_value; +- struct ath12k_base *ab = ar->ab; +- int ret; +- +- param_id = WMI_VDEV_PARAM_SET_HEMU_MODE; +- param_value = ath12k_mac_prepare_he_mode(ar->pdev, arvif->vif->type); +- ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- param_id, param_value); +- if (ret) { +- ath12k_warn(ab, "failed to set vdev %d HE MU mode: %d param_value %x\n", +- arvif->vdev_id, ret, param_value); +- return ret; +- } +- param_id = WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE; +- param_value = +- u32_encode_bits(HE_VHT_SOUNDING_MODE_ENABLE, HE_VHT_SOUNDING_MODE) | +- u32_encode_bits(HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE, +- HE_TRIG_NONTRIG_SOUNDING_MODE); +- ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- param_id, param_value); +- if (ret) { +- ath12k_warn(ab, "failed to set vdev %d HE MU mode: %d\n", +- arvif->vdev_id, ret); +- return ret; +- } +- return ret; +-} +- + static void ath12k_mac_update_vif_offload(struct ath12k_vif *arvif) + { + struct ieee80211_vif *vif = arvif->vif; +@@ -7339,7 +7409,6 @@ ath12k_mac_vdev_start_restart(struct ath + struct ath12k_base *ab = ar->ab; + struct wmi_vdev_start_req_arg arg = {}; + const struct cfg80211_chan_def *chandef = &ctx->def; +- int he_support = arvif->vif->bss_conf.he_support; + int ret; + + lockdep_assert_held(&ar->conf_mutex); +@@ -7395,14 +7464,6 @@ ath12k_mac_vdev_start_restart(struct ath + spin_unlock_bh(&ab->base_lock); + + /* TODO: Notify if secondary 80Mhz also needs radar detection */ +- if (he_support) { +- ret = ath12k_set_he_mu_sounding_mode(ar, arvif); +- if (ret) { +- ath12k_warn(ar->ab, "failed to set he mode vdev %i\n", +- arg.vdev_id); +- return ret; +- } +- } + } + + arg.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); +--- a/drivers/net/wireless/ath/ath12k/mac.h ++++ b/drivers/net/wireless/ath/ath12k/mac.h +@@ -41,6 +41,21 @@ struct ath12k_generic_iter { + #define ATH12K_TX_POWER_MAX_VAL 70 + #define ATH12K_TX_POWER_MIN_VAL 0 + ++#define HECAP_PHY_SUBFMR_GET(hecap_phy) \ ++ u8_get_bits(hecap_phy[3], IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ++ ++#define HECAP_PHY_SUBFME_GET(hecap_phy) \ ++ u8_get_bits(hecap_phy[4], IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE) ++ ++#define HECAP_PHY_MUBFMR_GET(hecap_phy) \ ++ u8_get_bits(hecap_phy[4], IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER) ++ ++#define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ ++ u8_get_bits(hecap_phy[2], IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO) ++ ++#define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ ++ u8_get_bits(hecap_phy[2], IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO) ++ + enum ath12k_supported_bw { + ATH12K_BW_20 = 0, + ATH12K_BW_40 = 1, +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -2995,31 +2995,6 @@ struct ath12k_wmi_rx_reorder_queue_remov + #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) + #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) + +-#define HECAP_PHYDWORD_0 0 +-#define HECAP_PHYDWORD_1 1 +-#define HECAP_PHYDWORD_2 2 +- +-#define HECAP_PHY_SU_BFER BIT(31) +-#define HECAP_PHY_SU_BFEE BIT(0) +-#define HECAP_PHY_MU_BFER BIT(1) +-#define HECAP_PHY_UL_MUMIMO BIT(22) +-#define HECAP_PHY_UL_MUOFDMA BIT(23) +- +-#define HECAP_PHY_SUBFMR_GET(hecap_phy) \ +- u32_get_bits(hecap_phy[HECAP_PHYDWORD_0], HECAP_PHY_SU_BFER) +- +-#define HECAP_PHY_SUBFME_GET(hecap_phy) \ +- u32_get_bits(hecap_phy[HECAP_PHYDWORD_1], HECAP_PHY_SU_BFEE) +- +-#define HECAP_PHY_MUBFMR_GET(hecap_phy) \ +- u32_get_bits(hecap_phy[HECAP_PHYDWORD_1], HECAP_PHY_MU_BFER) +- +-#define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ +- u32_get_bits(hecap_phy[HECAP_PHYDWORD_0], HECAP_PHY_UL_MUMIMO) +- +-#define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ +- u32_get_bits(hecap_phy[HECAP_PHYDWORD_0], HECAP_PHY_UL_MUOFDMA) +- + #define HE_MODE_SU_TX_BFEE BIT(0) + #define HE_MODE_SU_TX_BFER BIT(1) + #define HE_MODE_MU_TX_BFEE BIT(2) +@@ -3031,8 +3006,11 @@ struct ath12k_wmi_rx_reorder_queue_remov + #define HE_DL_MUOFDMA_ENABLE 1 + #define HE_UL_MUOFDMA_ENABLE 1 + #define HE_DL_MUMIMO_ENABLE 1 ++#define HE_UL_MUMIMO_ENABLE 1 + #define HE_MU_BFEE_ENABLE 1 + #define HE_SU_BFEE_ENABLE 1 ++#define HE_MU_BFER_ENABLE 1 ++#define HE_SU_BFER_ENABLE 1 + + #define HE_VHT_SOUNDING_MODE_ENABLE 1 + #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 diff --git a/package/kernel/mac80211/patches/ath12k/104-2-wifi-ath12k-push-EHT-MU-MIMO-params-to-hardware.patch b/package/kernel/mac80211/patches/ath12k/104-2-wifi-ath12k-push-EHT-MU-MIMO-params-to-hardware.patch new file mode 100644 index 0000000000..65ef65fa7f --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-2-wifi-ath12k-push-EHT-MU-MIMO-params-to-hardware.patch @@ -0,0 +1,222 @@ +From patchwork Wed Sep 18 21:20:49 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:07 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:06 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Muna Sinada , + "Jeff + Johnson" +Subject: [PATCH V8 2/9] wifi: ath12k: push EHT MU-MIMO params to hardware +Date: Wed, 18 Sep 2024 14:20:49 -0700 +Message-ID: <20240918212056.4137076-3-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-GUID: DiIEaDHD4453WG2b31qitb3_i0JkAM4u +X-Proofpoint-ORIG-GUID: DiIEaDHD4453WG2b31qitb3_i0JkAM4u +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + bulkscore=0 adultscore=0 + suspectscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 + phishscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 + spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 + engine=8.19.0-2408220000 definitions=main-2409180140 + +Currently, only the EHT IE in management frames is updated with +respect to MU-MIMO configurations, but this change is not +reflected in the hardware. Add support to propagate MU-MIMO +configurations to the hardware as well for AP mode. Similar +support for STA mode will be added in future. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: Muna Sinada +Signed-off-by: Muna Sinada +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 50 +++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath12k/wmi.h | 21 +++++++++++ + 2 files changed, 71 insertions(+) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -2953,6 +2953,50 @@ static int ath12k_mac_vif_recalc_sta_he_ + return 0; + } + ++static int ath12k_mac_set_eht_txbf_conf(struct ath12k_vif *arvif) ++{ ++ u32 param = WMI_VDEV_PARAM_SET_EHT_MU_MODE; ++ struct ath12k *ar = arvif->ar; ++ u32 value = 0; ++ int ret; ++ ++ if (!arvif->vif->bss_conf.eht_support) ++ return 0; ++ ++ if (arvif->vif->bss_conf.eht_su_beamformer) { ++ value |= u32_encode_bits(EHT_SU_BFER_ENABLE, EHT_MODE_SU_TX_BFER); ++ if (arvif->vif->bss_conf.eht_mu_beamformer && ++ arvif->vdev_type == WMI_VDEV_TYPE_AP) ++ value |= u32_encode_bits(EHT_MU_BFER_ENABLE, ++ EHT_MODE_MU_TX_BFER) | ++ u32_encode_bits(EHT_DL_MUOFDMA_ENABLE, ++ EHT_MODE_DL_OFDMA_MUMIMO) | ++ u32_encode_bits(EHT_UL_MUOFDMA_ENABLE, ++ EHT_MODE_UL_OFDMA_MUMIMO); ++ } ++ ++ if (arvif->vif->type != NL80211_IFTYPE_MESH_POINT) { ++ value |= u32_encode_bits(EHT_DL_MUOFDMA_ENABLE, EHT_MODE_DL_OFDMA) | ++ u32_encode_bits(EHT_UL_MUOFDMA_ENABLE, EHT_MODE_UL_OFDMA); ++ ++ if (arvif->vif->bss_conf.eht_80mhz_full_bw_ul_mumimo) ++ value |= u32_encode_bits(EHT_UL_MUMIMO_ENABLE, EHT_MODE_MUMIMO); ++ ++ if (arvif->vif->bss_conf.eht_su_beamformee) ++ value |= u32_encode_bits(EHT_SU_BFEE_ENABLE, ++ EHT_MODE_SU_TX_BFEE); ++ } ++ ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, value); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to set vdev %d EHT MU mode: %d\n", ++ arvif->vdev_id, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ + static void ath12k_bss_assoc(struct ath12k *ar, + struct ath12k_vif *arvif, + struct ieee80211_bss_conf *bss_conf) +@@ -3351,6 +3395,12 @@ static void ath12k_mac_bss_info_changed( + ath12k_warn(ar->ab, + "failed to set HE TXBF config for vdev: %d\n", + arvif->vdev_id); ++ ++ ret = ath12k_mac_set_eht_txbf_conf(arvif); ++ if (ret) ++ ath12k_warn(ar->ab, ++ "failed to set EHT TXBF config for vdev: %d\n", ++ arvif->vdev_id); + } + ath12k_control_beaconing(arvif, info); + +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -1139,6 +1139,7 @@ enum wmi_tlv_vdev_param { + WMI_VDEV_PARAM_BSS_COLOR, + WMI_VDEV_PARAM_SET_HEMU_MODE, + WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, ++ WMI_VDEV_PARAM_SET_EHT_MU_MODE = 0x8005, + }; + + enum wmi_tlv_peer_flags { +@@ -3012,6 +3013,26 @@ struct ath12k_wmi_rx_reorder_queue_remov + #define HE_MU_BFER_ENABLE 1 + #define HE_SU_BFER_ENABLE 1 + ++#define EHT_MODE_SU_TX_BFEE BIT(0) ++#define EHT_MODE_SU_TX_BFER BIT(1) ++#define EHT_MODE_MU_TX_BFEE BIT(2) ++#define EHT_MODE_MU_TX_BFER BIT(3) ++#define EHT_MODE_DL_OFDMA BIT(4) ++#define EHT_MODE_UL_OFDMA BIT(5) ++#define EHT_MODE_MUMIMO BIT(6) ++#define EHT_MODE_DL_OFDMA_TXBF BIT(7) ++#define EHT_MODE_DL_OFDMA_MUMIMO BIT(8) ++#define EHT_MODE_UL_OFDMA_MUMIMO BIT(9) ++ ++#define EHT_DL_MUOFDMA_ENABLE 1 ++#define EHT_UL_MUOFDMA_ENABLE 1 ++#define EHT_DL_MUMIMO_ENABLE 1 ++#define EHT_UL_MUMIMO_ENABLE 1 ++#define EHT_MU_BFEE_ENABLE 1 ++#define EHT_SU_BFEE_ENABLE 1 ++#define EHT_MU_BFER_ENABLE 1 ++#define EHT_SU_BFER_ENABLE 1 ++ + #define HE_VHT_SOUNDING_MODE_ENABLE 1 + #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 + #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 diff --git a/package/kernel/mac80211/patches/ath12k/104-3-wifi-ath12k-move-HE-MCS-mapper-to-a-separate-function.patch b/package/kernel/mac80211/patches/ath12k/104-3-wifi-ath12k-move-HE-MCS-mapper-to-a-separate-function.patch new file mode 100644 index 0000000000..bc2710a57d --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-3-wifi-ath12k-move-HE-MCS-mapper-to-a-separate-function.patch @@ -0,0 +1,162 @@ +From patchwork Wed Sep 18 21:20:50 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:07 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:07 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Muna Sinada , + "Jeff + Johnson" +Subject: [PATCH V8 3/9] wifi: ath12k: move HE MCS mapper to a separate + function +Date: Wed, 18 Sep 2024 14:20:50 -0700 +Message-ID: <20240918212056.4137076-4-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-ORIG-GUID: zHmCiFNBcWNOH7v_I9cuj0l6gmfKvBVa +X-Proofpoint-GUID: zHmCiFNBcWNOH7v_I9cuj0l6gmfKvBVa +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + priorityscore=1501 mlxscore=0 + suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 + mlxlogscore=999 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 + classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 + definitions=main-2409180140 + +Refactor the HE MCS mapper functionality in +ath12k_mac_copy_he_cap() into a new function. + +This helps improve readability, extensibility and will be used +when adding support for 160 MHz bandwidth in subsequent patches. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: Muna Sinada +Signed-off-by: Muna Sinada +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 22 ++++++++++++++-------- + 1 file changed, 14 insertions(+), 8 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -5518,12 +5518,24 @@ static __le16 ath12k_mac_setup_he_6ghz_c + return cpu_to_le16(bcap->he_6ghz_capa); + } + ++static void ath12k_mac_set_hemcsmap(struct ath12k_band_cap *band_cap, ++ struct ieee80211_sta_he_cap *he_cap) ++{ ++ struct ieee80211_he_mcs_nss_supp *mcs_nss = &he_cap->he_mcs_nss_supp; ++ ++ mcs_nss->rx_mcs_80 = cpu_to_le16(band_cap->he_mcs & 0xffff); ++ mcs_nss->tx_mcs_80 = cpu_to_le16(band_cap->he_mcs & 0xffff); ++ mcs_nss->rx_mcs_160 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ mcs_nss->tx_mcs_160 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ mcs_nss->rx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ mcs_nss->tx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++} ++ + static void ath12k_mac_copy_he_cap(struct ath12k_band_cap *band_cap, + int iftype, u8 num_tx_chains, + struct ieee80211_sta_he_cap *he_cap) + { + struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; +- struct ieee80211_he_mcs_nss_supp *mcs_nss = &he_cap->he_mcs_nss_supp; + + he_cap->has_he = true; + memcpy(he_cap_elem->mac_cap_info, band_cap->he_cap_info, +@@ -5561,13 +5573,7 @@ static void ath12k_mac_copy_he_cap(struc + break; + } + +- mcs_nss->rx_mcs_80 = cpu_to_le16(band_cap->he_mcs & 0xffff); +- mcs_nss->tx_mcs_80 = cpu_to_le16(band_cap->he_mcs & 0xffff); +- mcs_nss->rx_mcs_160 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- mcs_nss->tx_mcs_160 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- mcs_nss->rx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- mcs_nss->tx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- ++ ath12k_mac_set_hemcsmap(band_cap, he_cap); + memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); + if (he_cap_elem->phy_cap_info[6] & + IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) diff --git a/package/kernel/mac80211/patches/ath12k/104-4-wifi-ath12k-generate-rx-and-tx-mcs-maps-for-supported-HE-mcs.patch b/package/kernel/mac80211/patches/ath12k/104-4-wifi-ath12k-generate-rx-and-tx-mcs-maps-for-supported-HE-mcs.patch new file mode 100644 index 0000000000..3577889612 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-4-wifi-ath12k-generate-rx-and-tx-mcs-maps-for-supported-HE-mcs.patch @@ -0,0 +1,186 @@ +From patchwork Wed Sep 18 21:20:51 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:08 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:07 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Muna Sinada , + "Jeff + Johnson" +Subject: [PATCH V8 4/9] wifi: ath12k: generate rx and tx mcs maps for + supported HE mcs +Date: Wed, 18 Sep 2024 14:20:51 -0700 +Message-ID: <20240918212056.4137076-5-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-ORIG-GUID: wHJ63GZpWGKZ4XSyQZiVlsARNAgr5CQM +X-Proofpoint-GUID: wHJ63GZpWGKZ4XSyQZiVlsARNAgr5CQM +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + phishscore=0 mlxlogscore=999 + mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 + adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 + classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 + definitions=main-2409180140 + +Generate rx and tx mcs maps in ath12k_mac_set_hemcsmap() based +on number of supported tx/rx chains and set them in supported +mcs/nss for HE capabilities. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: Muna Sinada +Signed-off-by: Muna Sinada +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 40 ++++++++++++++++++++------- + 1 file changed, 30 insertions(+), 10 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -5518,20 +5518,40 @@ static __le16 ath12k_mac_setup_he_6ghz_c + return cpu_to_le16(bcap->he_6ghz_capa); + } + +-static void ath12k_mac_set_hemcsmap(struct ath12k_band_cap *band_cap, ++static void ath12k_mac_set_hemcsmap(struct ath12k *ar, ++ struct ath12k_pdev_cap *cap, + struct ieee80211_sta_he_cap *he_cap) + { + struct ieee80211_he_mcs_nss_supp *mcs_nss = &he_cap->he_mcs_nss_supp; ++ u16 txmcs_map, rxmcs_map; ++ u32 i; + +- mcs_nss->rx_mcs_80 = cpu_to_le16(band_cap->he_mcs & 0xffff); +- mcs_nss->tx_mcs_80 = cpu_to_le16(band_cap->he_mcs & 0xffff); +- mcs_nss->rx_mcs_160 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- mcs_nss->tx_mcs_160 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- mcs_nss->rx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); +- mcs_nss->tx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); ++ rxmcs_map = 0; ++ txmcs_map = 0; ++ for (i = 0; i < 8; i++) { ++ if (i < ar->num_tx_chains && ++ (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) ++ txmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ txmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ ++ if (i < ar->num_rx_chains && ++ (ar->cfg_rx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) ++ rxmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ rxmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ } ++ ++ mcs_nss->rx_mcs_80 = cpu_to_le16(rxmcs_map & 0xffff); ++ mcs_nss->tx_mcs_80 = cpu_to_le16(txmcs_map & 0xffff); ++ mcs_nss->rx_mcs_160 = cpu_to_le16(rxmcs_map & 0xffff); ++ mcs_nss->tx_mcs_160 = cpu_to_le16(txmcs_map & 0xffff); ++ mcs_nss->rx_mcs_80p80 = cpu_to_le16(rxmcs_map & 0xffff); ++ mcs_nss->tx_mcs_80p80 = cpu_to_le16(txmcs_map & 0xffff); + } + +-static void ath12k_mac_copy_he_cap(struct ath12k_band_cap *band_cap, ++static void ath12k_mac_copy_he_cap(struct ath12k *ar, ++ struct ath12k_band_cap *band_cap, + int iftype, u8 num_tx_chains, + struct ieee80211_sta_he_cap *he_cap) + { +@@ -5573,7 +5593,7 @@ static void ath12k_mac_copy_he_cap(struc + break; + } + +- ath12k_mac_set_hemcsmap(band_cap, he_cap); ++ ath12k_mac_set_hemcsmap(ar, &ar->pdev->cap, he_cap); + memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); + if (he_cap_elem->phy_cap_info[6] & + IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) +@@ -5762,7 +5782,7 @@ static int ath12k_mac_copy_sband_iftype_ + + data[idx].types_mask = BIT(i); + +- ath12k_mac_copy_he_cap(band_cap, i, ar->num_tx_chains, he_cap); ++ ath12k_mac_copy_he_cap(ar, band_cap, i, ar->num_tx_chains, he_cap); + if (band == NL80211_BAND_6GHZ) { + data[idx].he_6ghz_capa.capa = + ath12k_mac_setup_he_6ghz_cap(cap, band_cap); diff --git a/package/kernel/mac80211/patches/ath12k/104-5-wifi-ath12k-fix-TX-and-RX-MCS-rate-configurations-in-HE-mode.patch b/package/kernel/mac80211/patches/ath12k/104-5-wifi-ath12k-fix-TX-and-RX-MCS-rate-configurations-in-HE-mode.patch new file mode 100644 index 0000000000..e1d109cd56 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-5-wifi-ath12k-fix-TX-and-RX-MCS-rate-configurations-in-HE-mode.patch @@ -0,0 +1,141 @@ +From patchwork Wed Sep 18 21:20:52 2024 +Content-Type: text/plain; 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As a result, RX MCS rates +are configured for TX, and vice versa. This commit rectifies +the configuration to match what the firmware expects. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Fixes: d889913205cf ("wifi: ath12k: driver for Qualcomm Wi-Fi 7 devices") +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/wmi.c | 4 ++-- + drivers/net/wireless/ath/ath12k/wmi.h | 2 ++ + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/wmi.c ++++ b/drivers/net/wireless/ath/ath12k/wmi.c +@@ -2140,8 +2140,8 @@ int ath12k_wmi_send_peer_assoc_cmd(struc + he_mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_HE_RATE_SET, + sizeof(*he_mcs)); + +- he_mcs->rx_mcs_set = cpu_to_le32(arg->peer_he_rx_mcs_set[i]); +- he_mcs->tx_mcs_set = cpu_to_le32(arg->peer_he_tx_mcs_set[i]); ++ he_mcs->rx_mcs_set = cpu_to_le32(arg->peer_he_tx_mcs_set[i]); ++ he_mcs->tx_mcs_set = cpu_to_le32(arg->peer_he_rx_mcs_set[i]); + ptr += sizeof(*he_mcs); + } + +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -3953,7 +3953,9 @@ struct ath12k_wmi_vht_rate_set_params { + + struct ath12k_wmi_he_rate_set_params { + __le32 tlv_header; ++ /* MCS at which the peer can receive */ + __le32 rx_mcs_set; ++ /* MCS at which the peer can transmit */ + __le32 tx_mcs_set; + } __packed; + diff --git a/package/kernel/mac80211/patches/ath12k/104-6-wifi-ath12k-add-support-for-setting-fixed-HE-rate-GI-LTF.patch b/package/kernel/mac80211/patches/ath12k/104-6-wifi-ath12k-add-support-for-setting-fixed-HE-rate-GI-LTF.patch new file mode 100644 index 0000000000..d44e92751c --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-6-wifi-ath12k-add-support-for-setting-fixed-HE-rate-GI-LTF.patch @@ -0,0 +1,1095 @@ +From patchwork Wed Sep 18 21:20:53 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Pradeep Kumar Chitrapu +X-Patchwork-Id: 13807217 +X-Patchwork-Delegate: quic_jjohnson@quicinc.com +Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com + [205.220.168.131]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01CB41CB521 + for ; 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+ Wed, 18 Sep 2024 21:21:09 +0000 (GMT) +Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com + [10.47.209.196]) + by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id + 48ILL8jN020567 + (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); + Wed, 18 Sep 2024 21:21:08 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:08 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Muna Sinada , + "Jeff + Johnson" +Subject: [PATCH V8 6/9] wifi: ath12k: add support for setting fixed HE + rate/GI/LTF +Date: Wed, 18 Sep 2024 14:20:53 -0700 +Message-ID: <20240918212056.4137076-7-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-GUID: GGIeqOgMFye5oFp39WDjK5DZ7YoCK3Ap +X-Proofpoint-ORIG-GUID: GGIeqOgMFye5oFp39WDjK5DZ7YoCK3Ap +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + malwarescore=0 + mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 + lowpriorityscore=0 adultscore=0 phishscore=0 suspectscore=0 + priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 + reason=mlx scancount=1 engine=8.19.0-2408220000 + definitions=main-2409180140 + +Add support to set fixed HE rate/GI/LTF values using nl80211. +Reuse parts of the existing code path already used for HT/VHT +to implement the new helpers symmetrically, similar to how +HT/VHT is handled. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: Muna Sinada +Signed-off-by: Muna Sinada +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 604 ++++++++++++++++++++++++-- + drivers/net/wireless/ath/ath12k/wmi.h | 18 + + 2 files changed, 574 insertions(+), 48 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -441,6 +441,18 @@ ath12k_mac_max_vht_nss(const u16 *vht_mc + return 1; + } + ++static u32 ++ath12k_mac_max_he_nss(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) ++{ ++ int nss; ++ ++ for (nss = NL80211_HE_NSS_MAX - 1; nss >= 0; nss--) ++ if (he_mcs_mask[nss]) ++ return nss + 1; ++ ++ return 1; ++} ++ + static u8 ath12k_parse_mpdudensity(u8 mpdudensity) + { + /* From IEEE Std 802.11-2020 defined values for "Minimum MPDU Start Spacing": +@@ -1916,6 +1928,14 @@ static void ath12k_peer_assoc_h_ht(struc + arg->peer_rate_caps |= WMI_HOST_RC_CW40_FLAG; + } + ++ /* As firmware handles these two flags (IEEE80211_HT_CAP_SGI_20 ++ * and IEEE80211_HT_CAP_SGI_40) for enabling SGI, reset both ++ * flags if guard interval is Default GI ++ */ ++ if (arvif->bitrate_mask.control[band].gi == NL80211_TXRATE_DEFAULT_GI) ++ arg->peer_ht_caps &= ~(IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_SGI_40); ++ + if (arvif->bitrate_mask.control[band].gi != NL80211_TXRATE_FORCE_LGI) { + if (ht_cap->cap & (IEEE80211_HT_CAP_SGI_20 | + IEEE80211_HT_CAP_SGI_40)) +@@ -2039,11 +2059,12 @@ static void ath12k_peer_assoc_h_vht(stru + struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct cfg80211_chan_def def; + enum nl80211_band band; +- const u16 *vht_mcs_mask; ++ u16 *vht_mcs_mask; + u16 tx_mcs_map; + u8 ampdu_factor; + u8 max_nss, vht_mcs; +- int i; ++ int i, vht_nss, nss_idx; ++ bool user_rate_valid = true; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + return; +@@ -2086,6 +2107,25 @@ static void ath12k_peer_assoc_h_vht(stru + if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160) + arg->bw_160 = true; + ++ vht_nss = ath12k_mac_max_vht_nss(vht_mcs_mask); ++ ++ if (vht_nss > sta->deflink.rx_nss) { ++ user_rate_valid = false; ++ for (nss_idx = sta->deflink.rx_nss - 1; nss_idx >= 0; nss_idx--) { ++ if (vht_mcs_mask[nss_idx]) { ++ user_rate_valid = true; ++ break; ++ } ++ } ++ } ++ ++ if (!user_rate_valid) { ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "Setting vht range MCS value to peer supported nss:%d for peer %pM\n", ++ sta->deflink.rx_nss, sta->deflink.addr); ++ vht_mcs_mask[sta->deflink.rx_nss - 1] = vht_mcs_mask[vht_nss - 1]; ++ } ++ + /* Calculate peer NSS capability from VHT capabilities if STA + * supports VHT. + */ +@@ -2125,23 +2165,105 @@ static void ath12k_peer_assoc_h_vht(stru + /* TODO: rxnss_override */ + } + ++static int ath12k_mac_get_max_he_mcs_map(u16 mcs_map, int nss) ++{ ++ switch ((mcs_map >> (2 * nss)) & 0x3) { ++ case IEEE80211_HE_MCS_SUPPORT_0_7: return BIT(8) - 1; ++ case IEEE80211_HE_MCS_SUPPORT_0_9: return BIT(10) - 1; ++ case IEEE80211_HE_MCS_SUPPORT_0_11: return BIT(12) - 1; ++ } ++ return 0; ++} ++ ++static u16 ath12k_peer_assoc_h_he_limit(u16 tx_mcs_set, ++ const u16 *he_mcs_limit) ++{ ++ int idx_limit; ++ int nss; ++ u16 mcs_map; ++ u16 mcs; ++ ++ for (nss = 0; nss < NL80211_HE_NSS_MAX; nss++) { ++ mcs_map = ath12k_mac_get_max_he_mcs_map(tx_mcs_set, nss) & ++ he_mcs_limit[nss]; ++ ++ if (mcs_map) ++ idx_limit = fls(mcs_map) - 1; ++ else ++ idx_limit = -1; ++ ++ switch (idx_limit) { ++ case 0 ... 7: ++ mcs = IEEE80211_HE_MCS_SUPPORT_0_7; ++ break; ++ case 8: ++ case 9: ++ mcs = IEEE80211_HE_MCS_SUPPORT_0_9; ++ break; ++ case 10: ++ case 11: ++ mcs = IEEE80211_HE_MCS_SUPPORT_0_11; ++ break; ++ default: ++ WARN_ON(1); ++ fallthrough; ++ case -1: ++ mcs = IEEE80211_HE_MCS_NOT_SUPPORTED; ++ break; ++ } ++ ++ tx_mcs_set &= ~(0x3 << (nss * 2)); ++ tx_mcs_set |= mcs << (nss * 2); ++ } ++ ++ return tx_mcs_set; ++} ++ ++static bool ++ath12k_peer_assoc_h_he_masked(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) ++{ ++ int nss; ++ ++ for (nss = 0; nss < NL80211_HE_NSS_MAX; nss++) ++ if (he_mcs_mask[nss]) ++ return false; ++ ++ return true; ++} ++ + static void ath12k_peer_assoc_h_he(struct ath12k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ath12k_wmi_peer_assoc_arg *arg) + { + const struct ieee80211_sta_he_cap *he_cap = &sta->deflink.he_cap; ++ struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); ++ struct cfg80211_chan_def def; + int i; + u8 ampdu_factor, max_nss; + u8 rx_mcs_80 = IEEE80211_HE_MCS_NOT_SUPPORTED; + u8 rx_mcs_160 = IEEE80211_HE_MCS_NOT_SUPPORTED; + u16 mcs_160_map, mcs_80_map; + bool support_160; +- u16 v; ++ enum nl80211_band band; ++ u16 *he_mcs_mask; ++ u8 he_mcs; ++ u16 he_tx_mcs = 0, v = 0; ++ int he_nss, nss_idx; ++ bool user_rate_valid = true; ++ ++ if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) ++ return; + + if (!he_cap->has_he) + return; + ++ band = def.chan->band; ++ he_mcs_mask = arvif->bitrate_mask.control[band].he_mcs; ++ ++ if (ath12k_peer_assoc_h_he_masked(he_mcs_mask)) ++ return; ++ + arg->he_flag = true; + + support_160 = !!(he_cap->he_cap_elem.phy_cap_info[0] & +@@ -2247,25 +2369,47 @@ static void ath12k_peer_assoc_h_he(struc + if (he_cap->he_cap_elem.mac_cap_info[0] & IEEE80211_HE_MAC_CAP0_TWT_REQ) + arg->twt_requester = true; + ++ he_nss = ath12k_mac_max_he_nss(he_mcs_mask); ++ ++ if (he_nss > sta->deflink.rx_nss) { ++ user_rate_valid = false; ++ for (nss_idx = sta->deflink.rx_nss - 1; nss_idx >= 0; nss_idx--) { ++ if (he_mcs_mask[nss_idx]) { ++ user_rate_valid = true; ++ break; ++ } ++ } ++ } ++ ++ if (!user_rate_valid) { ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "Setting he range MCS value to peer supported nss:%d for peer %pM\n", ++ sta->deflink.rx_nss, sta->deflink.addr); ++ he_mcs_mask[sta->deflink.rx_nss - 1] = he_mcs_mask[he_nss - 1]; ++ } ++ + switch (sta->deflink.bandwidth) { + case IEEE80211_STA_RX_BW_160: + if (he_cap->he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) { +- v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_80p80); ++ v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); + arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v; + + v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80p80); + arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v; + + arg->peer_he_mcs_count++; ++ he_tx_mcs = v; + } + v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_160); + arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v; + +- v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_160); ++ v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); + arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v; + + arg->peer_he_mcs_count++; ++ if (!he_tx_mcs) ++ he_tx_mcs = v; + fallthrough; + + default: +@@ -2273,11 +2417,34 @@ static void ath12k_peer_assoc_h_he(struc + arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v; + + v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80); ++ v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); + arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v; + + arg->peer_he_mcs_count++; ++ if (!he_tx_mcs) ++ he_tx_mcs = v; + break; + } ++ ++ /* Calculate peer NSS capability from HE capabilities if STA ++ * supports HE. ++ */ ++ for (i = 0, max_nss = 0, he_mcs = 0; i < NL80211_HE_NSS_MAX; i++) { ++ he_mcs = he_tx_mcs >> (2 * i) & 3; ++ ++ /* In case of fixed rates, MCS Range in he_tx_mcs might have ++ * unsupported range, with he_mcs_mask set, so check either of them ++ * to find nss. ++ */ ++ if (he_mcs != IEEE80211_HE_MCS_NOT_SUPPORTED || ++ he_mcs_mask[i]) ++ max_nss = i + 1; ++ } ++ arg->peer_nss = min(sta->deflink.rx_nss, max_nss); ++ ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "mac he peer %pM nss %d mcs cnt %d\n", ++ sta->deflink.addr, arg->peer_nss, arg->peer_he_mcs_count); + } + + static void ath12k_peer_assoc_h_he_6ghz(struct ath12k *ar, +@@ -2586,6 +2753,7 @@ static void ath12k_peer_assoc_h_phymode( + enum nl80211_band band; + const u8 *ht_mcs_mask; + const u16 *vht_mcs_mask; ++ const u16 *he_mcs_mask; + enum wmi_phy_mode phymode = MODE_UNKNOWN; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) +@@ -2594,6 +2762,7 @@ static void ath12k_peer_assoc_h_phymode( + band = def.chan->band; + ht_mcs_mask = arvif->bitrate_mask.control[band].ht_mcs; + vht_mcs_mask = arvif->bitrate_mask.control[band].vht_mcs; ++ he_mcs_mask = arvif->bitrate_mask.control[band].he_mcs; + + switch (band) { + case NL80211_BAND_2GHZ: +@@ -2602,7 +2771,8 @@ static void ath12k_peer_assoc_h_phymode( + phymode = MODE_11BE_EHT40_2G; + else + phymode = MODE_11BE_EHT20_2G; +- } else if (sta->deflink.he_cap.has_he) { ++ } else if (sta->deflink.he_cap.has_he && ++ !ath12k_peer_assoc_h_he_masked(he_mcs_mask)) { + if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) + phymode = MODE_11AX_HE80_2G; + else if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40) +@@ -2632,7 +2802,8 @@ static void ath12k_peer_assoc_h_phymode( + /* Check EHT first */ + if (sta->deflink.eht_cap.has_eht) { + phymode = ath12k_mac_get_phymode_eht(ar, sta); +- } else if (sta->deflink.he_cap.has_he) { ++ } else if (sta->deflink.he_cap.has_he && ++ !ath12k_peer_assoc_h_he_masked(he_mcs_mask)) { + phymode = ath12k_mac_get_phymode_he(ar, sta); + } else if (sta->deflink.vht_cap.vht_supported && + !ath12k_peer_assoc_h_vht_masked(vht_mcs_mask)) { +@@ -4311,6 +4482,20 @@ ath12k_mac_bitrate_mask_num_vht_rates(st + } + + static int ++ath12k_mac_bitrate_mask_num_he_rates(struct ath12k *ar, ++ enum nl80211_band band, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ int num_rates = 0; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(mask->control[band].he_mcs); i++) ++ num_rates += hweight16(mask->control[band].he_mcs[i]); ++ ++ return num_rates; ++} ++ ++static int + ath12k_mac_set_peer_vht_fixed_rate(struct ath12k_vif *arvif, + struct ieee80211_sta *sta, + const struct cfg80211_bitrate_mask *mask, +@@ -4356,6 +4541,57 @@ ath12k_mac_set_peer_vht_fixed_rate(struc + return ret; + } + ++static int ++ath12k_mac_set_peer_he_fixed_rate(struct ath12k_vif *arvif, ++ struct ieee80211_sta *sta, ++ const struct cfg80211_bitrate_mask *mask, ++ enum nl80211_band band) ++{ ++ struct ath12k *ar = arvif->ar; ++ u8 he_rate, nss; ++ u32 rate_code; ++ int ret, i; ++ ++ lockdep_assert_held(&ar->conf_mutex); ++ ++ nss = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(mask->control[band].he_mcs); i++) { ++ if (hweight16(mask->control[band].he_mcs[i]) == 1) { ++ nss = i + 1; ++ he_rate = ffs(mask->control[band].he_mcs[i]) - 1; ++ } ++ } ++ ++ if (!nss) { ++ ath12k_warn(ar->ab, "No single HE Fixed rate found to set for %pM", ++ sta->deflink.addr); ++ return -EINVAL; ++ } ++ ++ /* Avoid updating invalid nss as fixed rate*/ ++ if (nss > sta->deflink.rx_nss) ++ return -EINVAL; ++ ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "Setting Fixed HE Rate for peer %pM. Device will not switch to any other selected rates", ++ sta->deflink.addr); ++ ++ rate_code = ATH12K_HW_RATE_CODE(he_rate, nss - 1, ++ WMI_RATE_PREAMBLE_HE); ++ ++ ret = ath12k_wmi_set_peer_param(ar, sta->deflink.addr, ++ arvif->vdev_id, ++ WMI_PEER_PARAM_FIXED_RATE, ++ rate_code); ++ if (ret) ++ ath12k_warn(ar->ab, ++ "failed to update STA %pM Fixed Rate %d: %d\n", ++ sta->deflink.addr, rate_code, ret); ++ ++ return ret; ++} ++ + static int ath12k_station_assoc(struct ath12k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, +@@ -4367,7 +4603,7 @@ static int ath12k_station_assoc(struct a + struct cfg80211_chan_def def; + enum nl80211_band band; + struct cfg80211_bitrate_mask *mask; +- u8 num_vht_rates; ++ u8 num_vht_rates, num_he_rates; + + lockdep_assert_held(&ar->conf_mutex); + +@@ -4398,15 +4634,19 @@ static int ath12k_station_assoc(struct a + } + + num_vht_rates = ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask); ++ num_he_rates = ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask); + +- /* If single VHT rate is configured (by set_bitrate_mask()), +- * peer_assoc will disable VHT. This is now enabled by a peer specific ++ /* If single VHT/HE rate is configured (by set_bitrate_mask()), ++ * peer_assoc will disable VHT/HE. This is now enabled by a peer specific + * fixed param. + * Note that all other rates and NSS will be disabled for this peer. + */ + if (sta->deflink.vht_cap.vht_supported && num_vht_rates == 1) { +- ret = ath12k_mac_set_peer_vht_fixed_rate(arvif, sta, mask, +- band); ++ ret = ath12k_mac_set_peer_vht_fixed_rate(arvif, sta, mask, band); ++ if (ret) ++ return ret; ++ } else if (sta->deflink.he_cap.has_he && num_he_rates == 1) { ++ ret = ath12k_mac_set_peer_he_fixed_rate(arvif, sta, mask, band); + if (ret) + return ret; + } +@@ -4480,8 +4720,9 @@ static void ath12k_sta_rc_update_wk(stru + enum nl80211_band band; + const u8 *ht_mcs_mask; + const u16 *vht_mcs_mask; +- u32 changed, bw, nss, smps, bw_prev; +- int err, num_vht_rates; ++ const u16 *he_mcs_mask; ++ u32 changed, bw, nss, mac_nss, smps, bw_prev; ++ int err, num_vht_rates, num_he_rates; + const struct cfg80211_bitrate_mask *mask; + struct ath12k_wmi_peer_assoc_arg peer_arg; + enum wmi_phy_mode peer_phymode; +@@ -4497,6 +4738,7 @@ static void ath12k_sta_rc_update_wk(stru + band = def.chan->band; + ht_mcs_mask = arvif->bitrate_mask.control[band].ht_mcs; + vht_mcs_mask = arvif->bitrate_mask.control[band].vht_mcs; ++ he_mcs_mask = arvif->bitrate_mask.control[band].he_mcs; + + spin_lock_bh(&ar->data_lock); + +@@ -4513,8 +4755,10 @@ static void ath12k_sta_rc_update_wk(stru + mutex_lock(&ar->conf_mutex); + + nss = max_t(u32, 1, nss); +- nss = min(nss, max(ath12k_mac_max_ht_nss(ht_mcs_mask), +- ath12k_mac_max_vht_nss(vht_mcs_mask))); ++ mac_nss = max3(ath12k_mac_max_ht_nss(ht_mcs_mask), ++ ath12k_mac_max_vht_nss(vht_mcs_mask), ++ ath12k_mac_max_he_nss(he_mcs_mask)); ++ nss = min(nss, mac_nss); + + if (changed & IEEE80211_RC_BW_CHANGED) { + ath12k_peer_assoc_h_phymode(ar, arvif->vif, sta, &peer_arg); +@@ -4592,6 +4836,8 @@ static void ath12k_sta_rc_update_wk(stru + mask = &arvif->bitrate_mask; + num_vht_rates = ath12k_mac_bitrate_mask_num_vht_rates(ar, band, + mask); ++ num_he_rates = ath12k_mac_bitrate_mask_num_he_rates(ar, band, ++ mask); + + /* Peer_assoc_prepare will reject vht rates in + * bitrate_mask if its not available in range format and +@@ -4607,11 +4853,24 @@ static void ath12k_sta_rc_update_wk(stru + if (sta->deflink.vht_cap.vht_supported && num_vht_rates == 1) { + ath12k_mac_set_peer_vht_fixed_rate(arvif, sta, mask, + band); ++ } else if (sta->deflink.he_cap.has_he && num_he_rates == 1) { ++ ath12k_mac_set_peer_he_fixed_rate(arvif, sta, mask, band); + } else { +- /* If the peer is non-VHT or no fixed VHT rate ++ /* If the peer is non-VHT/HE or no fixed VHT/HE rate + * is provided in the new bitrate mask we set the +- * other rates using peer_assoc command. ++ * other rates using peer_assoc command. Also clear ++ * the peer fixed rate settings as it has higher proprity ++ * than peer assoc + */ ++ ++ err = ath12k_wmi_set_peer_param(ar, sta->deflink.addr, ++ arvif->vdev_id, ++ WMI_PEER_PARAM_FIXED_RATE, ++ WMI_FIXED_RATE_NONE); ++ if (err) ++ ath12k_warn(ar->ab, ++ "failed to disable peer fixed rate for STA %pM ret %d\n", ++ sta->deflink.addr, err); + ath12k_peer_assoc_prepare(ar, arvif->vif, sta, + &peer_arg, true); + +@@ -7058,10 +7317,13 @@ static int ath12k_mac_op_add_interface(s + + for (i = 0; i < ARRAY_SIZE(arvif->bitrate_mask.control); i++) { + arvif->bitrate_mask.control[i].legacy = 0xffffffff; ++ arvif->bitrate_mask.control[i].gi = NL80211_TXRATE_FORCE_SGI; + memset(arvif->bitrate_mask.control[i].ht_mcs, 0xff, + sizeof(arvif->bitrate_mask.control[i].ht_mcs)); + memset(arvif->bitrate_mask.control[i].vht_mcs, 0xff, + sizeof(arvif->bitrate_mask.control[i].vht_mcs)); ++ memset(arvif->bitrate_mask.control[i].he_mcs, 0xff, ++ sizeof(arvif->bitrate_mask.control[i].he_mcs)); + } + + /* Allocate Default Queue now and reassign during actual vdev create */ +@@ -8222,19 +8484,40 @@ ath12k_mac_has_single_legacy_rate(struct + if (ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask)) + return false; + ++ if (ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask)) ++ return false; ++ + return num_rates == 1; + } + ++static __le16 ++ath12k_mac_get_tx_mcs_map(const struct ieee80211_sta_he_cap *he_cap) ++{ ++ if (he_cap->he_cap_elem.phy_cap_info[0] & ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) ++ return he_cap->he_mcs_nss_supp.tx_mcs_80p80; ++ ++ if (he_cap->he_cap_elem.phy_cap_info[0] & ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) ++ return he_cap->he_mcs_nss_supp.tx_mcs_160; ++ ++ return he_cap->he_mcs_nss_supp.tx_mcs_80; ++} ++ + static bool + ath12k_mac_bitrate_mask_get_single_nss(struct ath12k *ar, ++ struct ieee80211_vif *vif, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask, + int *nss) + { + struct ieee80211_supported_band *sband = &ar->mac.sbands[band]; + u16 vht_mcs_map = le16_to_cpu(sband->vht_cap.vht_mcs.tx_mcs_map); ++ const struct ieee80211_sta_he_cap *he_cap; ++ u16 he_mcs_map = 0; + u8 ht_nss_mask = 0; + u8 vht_nss_mask = 0; ++ u8 he_nss_mask = 0; + int i; + + /* No need to consider legacy here. Basic rates are always present +@@ -8261,7 +8544,24 @@ ath12k_mac_bitrate_mask_get_single_nss(s + return false; + } + +- if (ht_nss_mask != vht_nss_mask) ++ he_cap = ieee80211_get_he_iftype_cap_vif(sband, vif); ++ if (!he_cap) ++ return false; ++ ++ he_mcs_map = le16_to_cpu(ath12k_mac_get_tx_mcs_map(he_cap)); ++ ++ for (i = 0; i < ARRAY_SIZE(mask->control[band].he_mcs); i++) { ++ if (mask->control[band].he_mcs[i] == 0) ++ continue; ++ ++ if (mask->control[band].he_mcs[i] == ++ ath12k_mac_get_max_he_mcs_map(he_mcs_map, i)) ++ he_nss_mask |= BIT(i); ++ else ++ return false; ++ } ++ ++ if (ht_nss_mask != vht_nss_mask || ht_nss_mask != he_nss_mask) + return false; + + if (ht_nss_mask == 0) +@@ -8308,54 +8608,158 @@ ath12k_mac_get_single_legacy_rate(struct + return 0; + } + +-static int ath12k_mac_set_fixed_rate_params(struct ath12k_vif *arvif, +- u32 rate, u8 nss, u8 sgi, u8 ldpc) ++static int ++ath12k_mac_set_fixed_rate_gi_ltf(struct ath12k_vif *arvif, u8 he_gi, u8 he_ltf) + { + struct ath12k *ar = arvif->ar; +- u32 vdev_param; + int ret; + +- lockdep_assert_held(&ar->conf_mutex); ++ /* 0.8 = 0, 1.6 = 2 and 3.2 = 3. */ ++ if (he_gi && he_gi != 0xFF) ++ he_gi += 1; + +- ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac set fixed rate params vdev %i rate 0x%02x nss %u sgi %u\n", +- arvif->vdev_id, rate, nss, sgi); ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, ++ WMI_VDEV_PARAM_SGI, he_gi); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to set HE GI:%d, error:%d\n", ++ he_gi, ret); ++ return ret; ++ } ++ /* start from 1 */ ++ if (he_ltf != 0xFF) ++ he_ltf += 1; + +- vdev_param = WMI_VDEV_PARAM_FIXED_RATE; + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- vdev_param, rate); ++ WMI_VDEV_PARAM_HE_LTF, he_ltf); + if (ret) { +- ath12k_warn(ar->ab, "failed to set fixed rate param 0x%02x: %d\n", +- rate, ret); ++ ath12k_warn(ar->ab, "failed to set HE LTF:%d, error:%d\n", ++ he_ltf, ret); + return ret; + } ++ return 0; ++} ++ ++static int ++ath12k_mac_set_auto_rate_gi_ltf(struct ath12k_vif *arvif, u16 he_gi, u8 he_ltf) ++{ ++ struct ath12k *ar = arvif->ar; ++ int ret; ++ u32 he_ar_gi_ltf; ++ ++ if (he_gi != 0xFF) { ++ switch (he_gi) { ++ case NL80211_RATE_INFO_HE_GI_0_8: ++ he_gi = WMI_AUTORATE_800NS_GI; ++ break; ++ case NL80211_RATE_INFO_HE_GI_1_6: ++ he_gi = WMI_AUTORATE_1600NS_GI; ++ break; ++ case NL80211_RATE_INFO_HE_GI_3_2: ++ he_gi = WMI_AUTORATE_3200NS_GI; ++ break; ++ default: ++ ath12k_warn(ar->ab, "Invalid GI\n"); ++ return -EINVAL; ++ } ++ } ++ ++ if (he_ltf != 0xFF) { ++ switch (he_ltf) { ++ case NL80211_RATE_INFO_HE_1XLTF: ++ he_ltf = WMI_HE_AUTORATE_LTF_1X; ++ break; ++ case NL80211_RATE_INFO_HE_2XLTF: ++ he_ltf = WMI_HE_AUTORATE_LTF_2X; ++ break; ++ case NL80211_RATE_INFO_HE_4XLTF: ++ he_ltf = WMI_HE_AUTORATE_LTF_4X; ++ break; ++ default: ++ ath12k_warn(ar->ab, "Invalid LTF\n"); ++ return -EINVAL; ++ } ++ } ++ ++ he_ar_gi_ltf = he_gi | he_ltf; + +- vdev_param = WMI_VDEV_PARAM_NSS; + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- vdev_param, nss); ++ WMI_VDEV_PARAM_AUTORATE_MISC_CFG, ++ he_ar_gi_ltf); + if (ret) { +- ath12k_warn(ar->ab, "failed to set nss param %d: %d\n", +- nss, ret); ++ ath12k_warn(ar->ab, ++ "failed to set HE autorate GI:%u, LTF:%u params, error:%d\n", ++ he_gi, he_ltf, ret); + return ret; + } + +- vdev_param = WMI_VDEV_PARAM_SGI; ++ return 0; ++} ++ ++static int ath12k_mac_set_rate_params(struct ath12k_vif *arvif, ++ u32 rate, u8 nss, u8 sgi, u8 ldpc, ++ u8 he_gi, u8 he_ltf, bool he_fixed_rate) ++{ ++ struct ath12k *ar = arvif->ar; ++ u32 vdev_param; ++ int ret; ++ ++ lockdep_assert_held(&ar->conf_mutex); ++ ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "mac set rate params vdev %i rate 0x%02x nss 0x%02x sgi 0x%02x ldpc 0x%02x\n", ++ arvif->vdev_id, rate, nss, sgi, ldpc); ++ ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "he_gi 0x%02x he_ltf 0x%02x he_fixed_rate %d\n", he_gi, ++ he_ltf, he_fixed_rate); ++ ++ if (!arvif->vif->bss_conf.he_support) { ++ vdev_param = WMI_VDEV_PARAM_FIXED_RATE; ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, ++ vdev_param, rate); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to set fixed rate param 0x%02x: %d\n", ++ rate, ret); ++ return ret; ++ } ++ } ++ ++ vdev_param = WMI_VDEV_PARAM_NSS; ++ + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- vdev_param, sgi); ++ vdev_param, nss); + if (ret) { +- ath12k_warn(ar->ab, "failed to set sgi param %d: %d\n", +- sgi, ret); ++ ath12k_warn(ar->ab, "failed to set nss param %d: %d\n", ++ nss, ret); + return ret; + } + +- vdev_param = WMI_VDEV_PARAM_LDPC; + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, +- vdev_param, ldpc); ++ WMI_VDEV_PARAM_LDPC, ldpc); + if (ret) { + ath12k_warn(ar->ab, "failed to set ldpc param %d: %d\n", + ldpc, ret); + return ret; + } + ++ if (arvif->vif->bss_conf.he_support) { ++ if (he_fixed_rate) ++ ret = ath12k_mac_set_fixed_rate_gi_ltf(arvif, he_gi, he_ltf); ++ else ++ ret = ath12k_mac_set_auto_rate_gi_ltf(arvif, he_gi, he_ltf); ++ if (ret) ++ return ret; ++ } else { ++ vdev_param = WMI_VDEV_PARAM_SGI; ++ ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, ++ vdev_param, sgi); ++ if (ret) { ++ ath12k_warn(ar->ab, "failed to set sgi param %d: %d\n", ++ sgi, ret); ++ return ret; ++ } ++ } ++ + return 0; + } + +@@ -8384,6 +8788,31 @@ ath12k_mac_vht_mcs_range_present(struct + return true; + } + ++static bool ++ath12k_mac_he_mcs_range_present(struct ath12k *ar, ++ enum nl80211_band band, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ int i; ++ u16 he_mcs; ++ ++ for (i = 0; i < NL80211_HE_NSS_MAX; i++) { ++ he_mcs = mask->control[band].he_mcs[i]; ++ ++ switch (he_mcs) { ++ case 0: ++ case BIT(8) - 1: ++ case BIT(10) - 1: ++ case BIT(12) - 1: ++ break; ++ default: ++ return false; ++ } ++ } ++ ++ return true; ++} ++ + static void ath12k_mac_set_bitrate_mask_iter(void *data, + struct ieee80211_sta *sta) + { +@@ -8423,6 +8852,54 @@ static void ath12k_mac_disable_peer_fixe + } + + static int ++ath12k_mac_validate_vht_he_fixed_rate_settings(struct ath12k *ar, enum nl80211_band band, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ bool he_fixed_rate = false, vht_fixed_rate = false; ++ struct ath12k_peer *peer; ++ const u16 *vht_mcs_mask, *he_mcs_mask; ++ u8 vht_nss, he_nss; ++ int ret = 0; ++ ++ vht_mcs_mask = mask->control[band].vht_mcs; ++ he_mcs_mask = mask->control[band].he_mcs; ++ ++ if (ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask) == 1) ++ vht_fixed_rate = true; ++ ++ if (ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask) == 1) ++ he_fixed_rate = true; ++ ++ if (!vht_fixed_rate && !he_fixed_rate) ++ return 0; ++ ++ vht_nss = ath12k_mac_max_vht_nss(vht_mcs_mask); ++ he_nss = ath12k_mac_max_he_nss(he_mcs_mask); ++ ++ rcu_read_lock(); ++ spin_lock_bh(&ar->ab->base_lock); ++ list_for_each_entry(peer, &ar->ab->peers, list) { ++ if (peer->sta) { ++ if (vht_fixed_rate && ++ (!peer->sta->deflink.vht_cap.vht_supported || ++ peer->sta->deflink.rx_nss < vht_nss)) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ if (he_fixed_rate && (!peer->sta->deflink.he_cap.has_he || ++ peer->sta->deflink.rx_nss < he_nss)) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ } ++exit: ++ spin_unlock_bh(&ar->ab->base_lock); ++ rcu_read_unlock(); ++ return ret; ++} ++ ++static int + ath12k_mac_op_set_bitrate_mask(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + const struct cfg80211_bitrate_mask *mask) +@@ -8433,13 +8910,17 @@ ath12k_mac_op_set_bitrate_mask(struct ie + enum nl80211_band band; + const u8 *ht_mcs_mask; + const u16 *vht_mcs_mask; ++ const u16 *he_mcs_mask; ++ u8 he_ltf = 0; ++ u8 he_gi = 0; + u32 rate; +- u8 nss; ++ u8 nss, mac_nss; + u8 sgi; + u8 ldpc; + int single_nss; + int ret; + int num_rates; ++ bool he_fixed_rate = false; + + if (ath12k_mac_vif_chan(vif, &def)) + return -EPERM; +@@ -8447,6 +8928,7 @@ ath12k_mac_op_set_bitrate_mask(struct ie + band = def.chan->band; + ht_mcs_mask = mask->control[band].ht_mcs; + vht_mcs_mask = mask->control[band].vht_mcs; ++ he_mcs_mask = mask->control[band].he_mcs; + ldpc = !!(ar->ht_cap_info & WMI_HT_CAP_LDPC); + + sgi = mask->control[band].gi; +@@ -8455,6 +8937,9 @@ ath12k_mac_op_set_bitrate_mask(struct ie + goto out; + } + ++ he_gi = mask->control[band].he_gi; ++ he_ltf = mask->control[band].he_ltf; ++ + /* mac80211 doesn't support sending a fixed HT/VHT MCS alone, rather it + * requires passing at least one of used basic rates along with them. + * Fixed rate setting across different preambles(legacy, HT, VHT) is +@@ -8474,15 +8959,27 @@ ath12k_mac_op_set_bitrate_mask(struct ie + ieee80211_iterate_stations_mtx(hw, + ath12k_mac_disable_peer_fixed_rate, + arvif); +- } else if (ath12k_mac_bitrate_mask_get_single_nss(ar, band, mask, ++ } else if (ath12k_mac_bitrate_mask_get_single_nss(ar, vif, band, mask, + &single_nss)) { + rate = WMI_FIXED_RATE_NONE; + nss = single_nss; ++ mutex_lock(&ar->conf_mutex); ++ arvif->bitrate_mask = *mask; ++ ieee80211_iterate_stations_mtx(hw, ++ ath12k_mac_set_bitrate_mask_iter, ++ arvif); ++ mutex_unlock(&ar->conf_mutex); + } else { + rate = WMI_FIXED_RATE_NONE; +- nss = min_t(u32, ar->num_tx_chains, +- max(ath12k_mac_max_ht_nss(ht_mcs_mask), +- ath12k_mac_max_vht_nss(vht_mcs_mask))); ++ ++ if (!ath12k_mac_validate_vht_he_fixed_rate_settings(ar, band, mask)) ++ ath12k_warn(ar->ab, ++ "could not update fixed rate settings to all peers due to mcs/nss incompatiblity\n"); ++ ++ mac_nss = max3(ath12k_mac_max_ht_nss(ht_mcs_mask), ++ ath12k_mac_max_vht_nss(vht_mcs_mask), ++ ath12k_mac_max_he_nss(he_mcs_mask)); ++ nss = min_t(u32, ar->num_tx_chains, mac_nss); + + /* If multiple rates across different preambles are given + * we can reconfigure this info with all peers using PEER_ASSOC +@@ -8518,12 +9015,22 @@ ath12k_mac_op_set_bitrate_mask(struct ie + goto out; + } + ++ num_rates = ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask); ++ if (num_rates == 1) ++ he_fixed_rate = true; ++ ++ if (!ath12k_mac_he_mcs_range_present(ar, band, mask) && ++ num_rates > 1) { ++ ath12k_warn(ar->ab, ++ "Setting more than one HE MCS Value in bitrate mask not supported\n"); ++ return -EINVAL; ++ } ++ ++ mutex_lock(&ar->conf_mutex); + ieee80211_iterate_stations_mtx(hw, + ath12k_mac_disable_peer_fixed_rate, + arvif); + +- mutex_lock(&ar->conf_mutex); +- + arvif->bitrate_mask = *mask; + ieee80211_iterate_stations_mtx(hw, + ath12k_mac_set_bitrate_mask_iter, +@@ -8534,9 +9041,10 @@ ath12k_mac_op_set_bitrate_mask(struct ie + + mutex_lock(&ar->conf_mutex); + +- ret = ath12k_mac_set_fixed_rate_params(arvif, rate, nss, sgi, ldpc); ++ ret = ath12k_mac_set_rate_params(arvif, rate, nss, sgi, ldpc, he_gi, ++ he_ltf, he_fixed_rate); + if (ret) { +- ath12k_warn(ar->ab, "failed to set fixed rate params on vdev %i: %d\n", ++ ath12k_warn(ar->ab, "failed to set rate params on vdev %i: %d\n", + arvif->vdev_id, ret); + } + +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -220,6 +220,22 @@ enum WMI_HOST_WLAN_BAND { + WMI_HOST_WLAN_2G_5G_CAP = 3, + }; + ++/* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. ++ * Used only for HE auto rate mode. ++ */ ++enum { ++ /* HE LTF related configuration */ ++ WMI_HE_AUTORATE_LTF_1X = BIT(0), ++ WMI_HE_AUTORATE_LTF_2X = BIT(1), ++ WMI_HE_AUTORATE_LTF_4X = BIT(2), ++ ++ /* HE GI related configuration */ ++ WMI_AUTORATE_400NS_GI = BIT(8), ++ WMI_AUTORATE_800NS_GI = BIT(9), ++ WMI_AUTORATE_1600NS_GI = BIT(10), ++ WMI_AUTORATE_3200NS_GI = BIT(11), ++}; ++ + enum wmi_cmd_group { + /* 0 to 2 are reserved */ + WMI_GRP_START = 0x3, +@@ -1132,7 +1148,9 @@ enum wmi_tlv_vdev_param { + WMI_VDEV_PARAM_HE_RANGE_EXT, + WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, + WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, ++ WMI_VDEV_PARAM_HE_LTF = 0x74, + WMI_VDEV_PARAM_BA_MODE = 0x7e, ++ WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, + WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, + WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, + WMI_VDEV_PARAM_PROTOTYPE = 0x8000, diff --git a/package/kernel/mac80211/patches/ath12k/104-7-wifi-ath12k-clean-up-80P80-support.patch b/package/kernel/mac80211/patches/ath12k/104-7-wifi-ath12k-clean-up-80P80-support.patch new file mode 100644 index 0000000000..a2792bf6e7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-7-wifi-ath12k-clean-up-80P80-support.patch @@ -0,0 +1,254 @@ +From patchwork Wed Sep 18 21:20:54 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:09 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:08 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Jeff Johnson +Subject: [PATCH V8 7/9] wifi: ath12k: clean up 80P80 support +Date: Wed, 18 Sep 2024 14:20:54 -0700 +Message-ID: <20240918212056.4137076-8-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-ORIG-GUID: zOl2cVhwvoAFaH70WioUIdrk_oIr5c-T +X-Proofpoint-GUID: zOl2cVhwvoAFaH70WioUIdrk_oIr5c-T +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + phishscore=0 impostorscore=0 + clxscore=1015 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 + priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 + mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 + engine=8.19.0-2408220000 definitions=main-2409180141 + +Clean up unused 80P80 references as hardware does not support +it. This is applicable to both QCN9274 and WCN7850. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 51 ++++++--------------------- + drivers/net/wireless/ath/ath12k/wmi.c | 5 +-- + drivers/net/wireless/ath/ath12k/wmi.h | 1 - + 3 files changed, 11 insertions(+), 46 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -206,7 +206,7 @@ ath12k_phymodes[NUM_NL80211_BANDS][ATH12 + [NL80211_CHAN_WIDTH_40] = MODE_11BE_EHT40, + [NL80211_CHAN_WIDTH_80] = MODE_11BE_EHT80, + [NL80211_CHAN_WIDTH_160] = MODE_11BE_EHT160, +- [NL80211_CHAN_WIDTH_80P80] = MODE_11BE_EHT80_80, ++ [NL80211_CHAN_WIDTH_80P80] = MODE_UNKNOWN, + [NL80211_CHAN_WIDTH_320] = MODE_11BE_EHT320, + }, + [NL80211_BAND_6GHZ] = { +@@ -217,7 +217,7 @@ ath12k_phymodes[NUM_NL80211_BANDS][ATH12 + [NL80211_CHAN_WIDTH_40] = MODE_11BE_EHT40, + [NL80211_CHAN_WIDTH_80] = MODE_11BE_EHT80, + [NL80211_CHAN_WIDTH_160] = MODE_11BE_EHT160, +- [NL80211_CHAN_WIDTH_80P80] = MODE_11BE_EHT80_80, ++ [NL80211_CHAN_WIDTH_80P80] = MODE_UNKNOWN, + [NL80211_CHAN_WIDTH_320] = MODE_11BE_EHT320, + }, + +@@ -2390,17 +2390,6 @@ static void ath12k_peer_assoc_h_he(struc + + switch (sta->deflink.bandwidth) { + case IEEE80211_STA_RX_BW_160: +- if (he_cap->he_cap_elem.phy_cap_info[0] & +- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) { +- v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); +- arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v; +- +- v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80p80); +- arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v; +- +- arg->peer_he_mcs_count++; +- he_tx_mcs = v; +- } + v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_160); + arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v; + +@@ -2658,16 +2647,11 @@ static enum wmi_phy_mode ath12k_mac_get_ + struct ieee80211_sta *sta) + { + if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160) { +- switch (sta->deflink.vht_cap.cap & +- IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) { +- case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ: ++ if (sta->deflink.vht_cap.cap & ++ IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ) + return MODE_11AC_VHT160; +- case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ: +- return MODE_11AC_VHT80_80; +- default: +- /* not sure if this is a valid case? */ +- return MODE_11AC_VHT160; +- } ++ ++ return MODE_UNKNOWN; + } + + if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) +@@ -2689,11 +2673,8 @@ static enum wmi_phy_mode ath12k_mac_get_ + if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) + return MODE_11AX_HE160; +- else if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[0] & +- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) +- return MODE_11AX_HE80_80; +- /* not sure if this is a valid case? */ +- return MODE_11AX_HE160; ++ ++ return MODE_UNKNOWN; + } + + if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) +@@ -2721,14 +2702,7 @@ static enum wmi_phy_mode ath12k_mac_get_ + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) + return MODE_11BE_EHT160; + +- if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[0] & +- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) +- return MODE_11BE_EHT80_80; +- +- ath12k_warn(ar->ab, "invalid EHT PHY capability info for 160 Mhz: %d\n", +- sta->deflink.he_cap.he_cap_elem.phy_cap_info[0]); +- +- return MODE_11BE_EHT160; ++ return MODE_UNKNOWN; + } + + if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) +@@ -5805,8 +5779,6 @@ static void ath12k_mac_set_hemcsmap(stru + mcs_nss->tx_mcs_80 = cpu_to_le16(txmcs_map & 0xffff); + mcs_nss->rx_mcs_160 = cpu_to_le16(rxmcs_map & 0xffff); + mcs_nss->tx_mcs_160 = cpu_to_le16(txmcs_map & 0xffff); +- mcs_nss->rx_mcs_80p80 = cpu_to_le16(rxmcs_map & 0xffff); +- mcs_nss->tx_mcs_80p80 = cpu_to_le16(txmcs_map & 0xffff); + } + + static void ath12k_mac_copy_he_cap(struct ath12k *ar, +@@ -5828,6 +5800,7 @@ static void ath12k_mac_copy_he_cap(struc + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; ++ /* 80PLUS80 is not supported */ + he_cap_elem->phy_cap_info[0] &= + ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; + he_cap_elem->phy_cap_info[5] &= +@@ -8494,10 +8467,6 @@ static __le16 + ath12k_mac_get_tx_mcs_map(const struct ieee80211_sta_he_cap *he_cap) + { + if (he_cap->he_cap_elem.phy_cap_info[0] & +- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) +- return he_cap->he_mcs_nss_supp.tx_mcs_80p80; +- +- if (he_cap->he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) + return he_cap->he_mcs_nss_supp.tx_mcs_160; + +--- a/drivers/net/wireless/ath/ath12k/wmi.c ++++ b/drivers/net/wireless/ath/ath12k/wmi.c +@@ -986,10 +986,7 @@ static void ath12k_wmi_put_wmi_channel(s + + chan->mhz = cpu_to_le32(arg->freq); + chan->band_center_freq1 = cpu_to_le32(arg->band_center_freq1); +- if (arg->mode == MODE_11AC_VHT80_80) +- chan->band_center_freq2 = cpu_to_le32(arg->band_center_freq2); +- else +- chan->band_center_freq2 = 0; ++ chan->band_center_freq2 = 0; + + chan->info |= le32_encode_bits(arg->mode, WMI_CHAN_INFO_MODE); + if (arg->passive) +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -3633,7 +3633,6 @@ struct wmi_vdev_install_key_arg { + #define WMI_HOST_MAX_HE_RATE_SET 3 + #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 + #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 +-#define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 + + struct wmi_rate_set_arg { + u32 num_rates; diff --git a/package/kernel/mac80211/patches/ath12k/104-8-wifi-ath12k-add-support-for-160-MHz-bandwidth.patch b/package/kernel/mac80211/patches/ath12k/104-8-wifi-ath12k-add-support-for-160-MHz-bandwidth.patch new file mode 100644 index 0000000000..f9b6c4065d --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-8-wifi-ath12k-add-support-for-160-MHz-bandwidth.patch @@ -0,0 +1,399 @@ +From patchwork Wed Sep 18 21:20:55 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:09 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:09 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + P Praneesh , + "Jeff + Johnson" +Subject: [PATCH V8 8/9] wifi: ath12k: add support for 160 MHz bandwidth +Date: Wed, 18 Sep 2024 14:20:55 -0700 +Message-ID: <20240918212056.4137076-9-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-ORIG-GUID: wO0mnzqAAbcWYLNaoEhU3YfsdCyDJ2hk +X-Proofpoint-GUID: wO0mnzqAAbcWYLNaoEhU3YfsdCyDJ2hk +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + phishscore=0 mlxlogscore=999 + mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 + adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 + classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 + definitions=main-2409180140 + +Add support to configure maximum NSS in 160 MHz bandwidth. +Firmware advertises support for handling NSS ratio information +as a part of service ready ext event using nss_ratio_enabled +flag. Save this information in ath12k_pdev_cap to calculate +NSS ratio. + +Additionally, reorder the code by moving +ath12k_peer_assoc_h_phymode() before ath12k_peer_assoc_h_vht() +to ensure that arg->peer_phymode correctly reflects the bandwidth +in the max NSS calculation. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Co-developed-by: P Praneesh +Signed-off-by: P Praneesh +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/core.h | 2 + + drivers/net/wireless/ath/ath12k/mac.c | 85 ++++++++++++++++++++++---- + drivers/net/wireless/ath/ath12k/mac.h | 2 + + drivers/net/wireless/ath/ath12k/wmi.c | 19 +++++- + drivers/net/wireless/ath/ath12k/wmi.h | 28 +++++++++ + 5 files changed, 124 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/core.h ++++ b/drivers/net/wireless/ath/ath12k/core.h +@@ -717,6 +717,8 @@ struct ath12k_pdev_cap { + u32 tx_chain_mask_shift; + u32 rx_chain_mask_shift; + struct ath12k_band_cap band[NUM_NL80211_BANDS]; ++ bool nss_ratio_enabled; ++ u8 nss_ratio_info; + }; + + struct mlo_timestamp { +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -2050,6 +2050,34 @@ ath12k_peer_assoc_h_vht_limit(u16 tx_mcs + return tx_mcs_set; + } + ++static u8 ath12k_get_nss_160mhz(struct ath12k *ar, ++ u8 max_nss) ++{ ++ u8 nss_ratio_info = ar->pdev->cap.nss_ratio_info; ++ u8 max_sup_nss = 0; ++ ++ switch (nss_ratio_info) { ++ case WMI_NSS_RATIO_1BY2_NSS: ++ max_sup_nss = max_nss >> 1; ++ break; ++ case WMI_NSS_RATIO_3BY4_NSS: ++ ath12k_warn(ar->ab, "WMI_NSS_RATIO_3BY4_NSS not supported\n"); ++ break; ++ case WMI_NSS_RATIO_1_NSS: ++ max_sup_nss = max_nss; ++ break; ++ case WMI_NSS_RATIO_2_NSS: ++ ath12k_warn(ar->ab, "WMI_NSS_RATIO_2_NSS not supported\n"); ++ break; ++ default: ++ ath12k_warn(ar->ab, "invalid nss ratio received from fw: %d\n", ++ nss_ratio_info); ++ break; ++ } ++ ++ return max_sup_nss; ++} ++ + static void ath12k_peer_assoc_h_vht(struct ath12k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, +@@ -2065,6 +2093,7 @@ static void ath12k_peer_assoc_h_vht(stru + u8 max_nss, vht_mcs; + int i, vht_nss, nss_idx; + bool user_rate_valid = true; ++ u32 rx_nss, tx_nss, nss_160; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + return; +@@ -2159,10 +2188,24 @@ static void ath12k_peer_assoc_h_vht(stru + /* TODO: Check */ + arg->tx_max_mcs_nss = 0xFF; + +- ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vht peer %pM max_mpdu %d flags 0x%x\n", +- sta->addr, arg->peer_max_mpdu, arg->peer_flags); ++ if (arg->peer_phymode == MODE_11AC_VHT160) { ++ tx_nss = ath12k_get_nss_160mhz(ar, max_nss); ++ rx_nss = min(arg->peer_nss, tx_nss); ++ arg->peer_bw_rxnss_override = ATH12K_BW_NSS_MAP_ENABLE; + +- /* TODO: rxnss_override */ ++ if (!rx_nss) { ++ ath12k_warn(ar->ab, "invalid max_nss\n"); ++ return; ++ } ++ ++ nss_160 = u32_encode_bits(rx_nss - 1, ATH12K_PEER_RX_NSS_160MHZ); ++ arg->peer_bw_rxnss_override |= nss_160; ++ } ++ ++ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, ++ "mac vht peer %pM max_mpdu %d flags 0x%x nss_override 0x%x\n", ++ sta->addr, arg->peer_max_mpdu, arg->peer_flags, ++ arg->peer_bw_rxnss_override); + } + + static int ath12k_mac_get_max_he_mcs_map(u16 mcs_map, int nss) +@@ -2251,6 +2294,7 @@ static void ath12k_peer_assoc_h_he(struc + u16 he_tx_mcs = 0, v = 0; + int he_nss, nss_idx; + bool user_rate_valid = true; ++ u32 rx_nss, tx_nss, nss_160; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + return; +@@ -2429,11 +2473,28 @@ static void ath12k_peer_assoc_h_he(struc + he_mcs_mask[i]) + max_nss = i + 1; + } ++ max_nss = min(max_nss, ar->num_tx_chains); + arg->peer_nss = min(sta->deflink.rx_nss, max_nss); + ++ if (arg->peer_phymode == MODE_11AX_HE160) { ++ tx_nss = ath12k_get_nss_160mhz(ar, max_nss); ++ rx_nss = min(arg->peer_nss, tx_nss); ++ arg->peer_bw_rxnss_override = ATH12K_BW_NSS_MAP_ENABLE; ++ ++ if (!rx_nss) { ++ ath12k_warn(ar->ab, "invalid max_nss\n"); ++ return; ++ } ++ ++ nss_160 = u32_encode_bits(rx_nss - 1, ATH12K_PEER_RX_NSS_160MHZ); ++ arg->peer_bw_rxnss_override |= nss_160; ++ } ++ + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, +- "mac he peer %pM nss %d mcs cnt %d\n", +- sta->deflink.addr, arg->peer_nss, arg->peer_he_mcs_count); ++ "mac he peer %pM nss %d mcs cnt %d nss_override 0x%x\n", ++ sta->deflink.addr, arg->peer_nss, ++ arg->peer_he_mcs_count, ++ arg->peer_bw_rxnss_override); + } + + static void ath12k_peer_assoc_h_he_6ghz(struct ath12k *ar, +@@ -2965,13 +3026,13 @@ static void ath12k_peer_assoc_prepare(st + ath12k_peer_assoc_h_basic(ar, vif, sta, arg); + ath12k_peer_assoc_h_crypto(ar, vif, sta, arg); + ath12k_peer_assoc_h_rates(ar, vif, sta, arg); ++ ath12k_peer_assoc_h_phymode(ar, vif, sta, arg); + ath12k_peer_assoc_h_ht(ar, vif, sta, arg); + ath12k_peer_assoc_h_vht(ar, vif, sta, arg); + ath12k_peer_assoc_h_he(ar, vif, sta, arg); + ath12k_peer_assoc_h_he_6ghz(ar, vif, sta, arg); + ath12k_peer_assoc_h_eht(ar, vif, sta, arg); + ath12k_peer_assoc_h_qos(ar, vif, sta, arg); +- ath12k_peer_assoc_h_phymode(ar, vif, sta, arg); + ath12k_peer_assoc_h_smps(sta, arg); + + /* TODO: amsdu_disable req? */ +@@ -5551,10 +5612,8 @@ ath12k_create_vht_cap(struct ath12k *ar, + + ath12k_set_vht_txbf_cap(ar, &vht_cap.cap); + +- /* TODO: Enable back VHT160 mode once association issues are fixed */ +- /* Disabling VHT160 and VHT80+80 modes */ +- vht_cap.cap &= ~IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK; +- vht_cap.cap &= ~IEEE80211_VHT_CAP_SHORT_GI_160; ++ /* 80P80 is not supported */ ++ vht_cap.cap &= ~IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ; + + rxmcs_map = 0; + txmcs_map = 0; +@@ -9710,7 +9769,8 @@ static int ath12k_mac_setup_iface_combin + combinations[0].radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | + BIT(NL80211_CHAN_WIDTH_20) | + BIT(NL80211_CHAN_WIDTH_40) | +- BIT(NL80211_CHAN_WIDTH_80); ++ BIT(NL80211_CHAN_WIDTH_80) | ++ BIT(NL80211_CHAN_WIDTH_160); + + wiphy->iface_combinations = combinations; + wiphy->n_iface_combinations = 1; +@@ -9926,6 +9986,9 @@ static int ath12k_mac_hw_register(struct + ieee80211_hw_set(hw, SUPPORTS_TX_FRAG); + ieee80211_hw_set(hw, REPORTS_LOW_ACK); + ++ if (cap->nss_ratio_enabled) ++ ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); ++ + if ((ht_cap & WMI_HT_CAP_ENABLED) || ar->supports_6ghz) { + ieee80211_hw_set(hw, AMPDU_AGGREGATION); + ieee80211_hw_set(hw, TX_AMPDU_SETUP_IN_HW); +--- a/drivers/net/wireless/ath/ath12k/mac.h ++++ b/drivers/net/wireless/ath/ath12k/mac.h +@@ -37,6 +37,8 @@ struct ath12k_generic_iter { + #define IEEE80211_DISABLE_VHT_MCS_SUPPORT_0_11 BIT(24) + + #define ATH12K_CHAN_WIDTH_NUM 14 ++#define ATH12K_BW_NSS_MAP_ENABLE BIT(31) ++#define ATH12K_PEER_RX_NSS_160MHZ GENMASK(2, 0) + + #define ATH12K_TX_POWER_MAX_VAL 70 + #define ATH12K_TX_POWER_MIN_VAL 0 +--- a/drivers/net/wireless/ath/ath12k/wmi.c ++++ b/drivers/net/wireless/ath/ath12k/wmi.c +@@ -525,6 +525,10 @@ ath12k_pull_mac_phy_cap_svc_ready_ext(st + pdev_cap->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g); + pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_5g); + pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_5g); ++ pdev_cap->nss_ratio_enabled = ++ WMI_NSS_RATIO_EN_DIS_GET(mac_caps->nss_ratio); ++ pdev_cap->nss_ratio_info = ++ WMI_NSS_RATIO_INFO_GET(mac_caps->nss_ratio); + } else { + return -EINVAL; + } +@@ -982,11 +986,24 @@ int ath12k_wmi_vdev_down(struct ath12k * + static void ath12k_wmi_put_wmi_channel(struct ath12k_wmi_channel_params *chan, + struct wmi_vdev_start_req_arg *arg) + { ++ u32 center_freq1 = arg->band_center_freq1; ++ + memset(chan, 0, sizeof(*chan)); + + chan->mhz = cpu_to_le32(arg->freq); + chan->band_center_freq1 = cpu_to_le32(arg->band_center_freq1); +- chan->band_center_freq2 = 0; ++ if (arg->mode == MODE_11AX_HE160) { ++ if (arg->freq > center_freq1) ++ chan->band_center_freq1 = ++ cpu_to_le32(center_freq1 + 40); ++ else ++ chan->band_center_freq1 = ++ cpu_to_le32(center_freq1 - 40); ++ ++ chan->band_center_freq2 = cpu_to_le32(arg->band_center_freq1); ++ } else { ++ chan->band_center_freq2 = 0; ++ } + + chan->info |= le32_encode_bits(arg->mode, WMI_CHAN_INFO_MODE); + if (arg->passive) +--- a/drivers/net/wireless/ath/ath12k/wmi.h ++++ b/drivers/net/wireless/ath/ath12k/wmi.h +@@ -2264,6 +2264,21 @@ enum wmi_direct_buffer_module { + WMI_DIRECT_BUF_MAX + }; + ++/** ++ * enum wmi_nss_ratio - NSS ratio received from FW during service ready ext event ++ * @WMI_NSS_RATIO_1BY2_NSS: Max nss of 160MHz is equals to half of the max nss of 80MHz ++ * @WMI_NSS_RATIO_3BY4_NSS: Max nss of 160MHz is equals to 3/4 of the max nss of 80MHz ++ * @WMI_NSS_RATIO_1_NSS: Max nss of 160MHz is equals to the max nss of 80MHz ++ * @WMI_NSS_RATIO_2_NSS: Max nss of 160MHz is equals to two times the max nss of 80MHz ++ */ ++ ++enum wmi_nss_ratio { ++ WMI_NSS_RATIO_1BY2_NSS, ++ WMI_NSS_RATIO_3BY4_NSS, ++ WMI_NSS_RATIO_1_NSS, ++ WMI_NSS_RATIO_2_NSS ++}; ++ + struct ath12k_wmi_pdev_band_arg { + u32 pdev_id; + u32 start_freq; +@@ -2580,6 +2595,12 @@ struct ath12k_wmi_hw_mode_cap_params { + } __packed; + + #define WMI_MAX_HECAP_PHY_SIZE (3) ++#define WMI_NSS_RATIO_EN_DIS_BITPOS BIT(0) ++#define WMI_NSS_RATIO_EN_DIS_GET(_val) \ ++ le32_get_bits(_val, WMI_NSS_RATIO_EN_DIS_BITPOS) ++#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) ++#define WMI_NSS_RATIO_INFO_GET(_val) \ ++ le32_get_bits(_val, WMI_NSS_RATIO_INFO_BITPOS) + + /* pdev_id is present in lower 16 bits of pdev_and_hw_link_ids in + * ath12k_wmi_mac_phy_caps_params & ath12k_wmi_caps_ext_params. +@@ -2621,6 +2642,13 @@ struct ath12k_wmi_mac_phy_caps_params { + __le32 he_cap_info_2g_ext; + __le32 he_cap_info_5g_ext; + __le32 he_cap_info_internal; ++ __le32 wireless_modes; ++ __le32 low_2ghz_chan_freq; ++ __le32 high_2ghz_chan_freq; ++ __le32 low_5ghz_chan_freq; ++ __le32 high_5ghz_chan_freq; ++ __le32 nss_ratio; ++ + } __packed; + + struct ath12k_wmi_hal_reg_caps_ext_params { diff --git a/package/kernel/mac80211/patches/ath12k/104-9-wifi-ath12k-add-extended-NSS-bandwidth-support-for-160-MHz.patch b/package/kernel/mac80211/patches/ath12k/104-9-wifi-ath12k-add-extended-NSS-bandwidth-support-for-160-MHz.patch new file mode 100644 index 0000000000..b7d8bcd599 --- /dev/null +++ b/package/kernel/mac80211/patches/ath12k/104-9-wifi-ath12k-add-extended-NSS-bandwidth-support-for-160-MHz.patch @@ -0,0 +1,191 @@ +From patchwork Wed Sep 18 21:20:56 2024 +Content-Type: text/plain; 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+ Wed, 18 Sep 2024 21:21:10 GMT +Received: from ath12k-linux1.qualcomm.com (10.80.80.8) by + nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server + (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id + 15.2.1544.9; Wed, 18 Sep 2024 14:21:09 -0700 +From: Pradeep Kumar Chitrapu +To: +CC: , + Pradeep Kumar Chitrapu + , + Jeff Johnson +Subject: [PATCH V8 9/9] wifi: ath12k: add extended NSS bandwidth support for + 160 MHz +Date: Wed, 18 Sep 2024 14:20:56 -0700 +Message-ID: <20240918212056.4137076-10-quic_pradeepc@quicinc.com> +X-Mailer: git-send-email 2.34.1 +In-Reply-To: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +References: <20240918212056.4137076-1-quic_pradeepc@quicinc.com> +Precedence: bulk +X-Mailing-List: linux-wireless@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To + nalasex01a.na.qualcomm.com (10.47.209.196) +X-QCInternal: smtphost +X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 + signatures=585085 +X-Proofpoint-GUID: Mta6b5FqdCLrvsiUf1WwMHFr8SiJUh5L +X-Proofpoint-ORIG-GUID: Mta6b5FqdCLrvsiUf1WwMHFr8SiJUh5L +X-Proofpoint-Virus-Version: vendor=baseguard + engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 + definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 +X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 + priorityscore=1501 + clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 + impostorscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 + bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 + engine=8.19.0-2408220000 definitions=main-2409180140 + +Currently rx and tx MCS map for 160 MHz under HE capabilities +are not updating properly, when 160 MHz is configured with NSS +lesser than max NSS support. Fix this by utilizing +nss_ratio_enabled and nss_ratio_info fields sent by firmware +in service ready event. + +However, if firmware advertises EXT NSS BW support in VHT caps +as 1(1x2) and when nss_ratio_info indicates 1:1, reset the EXT +NSS BW Support in VHT caps to 0 which indicates 1x1. This is +to avoid incorrectly choosing 1:2 NSS ratio when using the +default VHT caps advertised by firmware. + +Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Pradeep Kumar Chitrapu +Acked-by: Jeff Johnson +--- + drivers/net/wireless/ath/ath12k/mac.c | 33 ++++++++++++++++++++++----- + 1 file changed, 27 insertions(+), 6 deletions(-) + +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -2477,8 +2477,10 @@ static void ath12k_peer_assoc_h_he(struc + arg->peer_nss = min(sta->deflink.rx_nss, max_nss); + + if (arg->peer_phymode == MODE_11AX_HE160) { +- tx_nss = ath12k_get_nss_160mhz(ar, max_nss); ++ tx_nss = ath12k_get_nss_160mhz(ar, ar->num_tx_chains); + rx_nss = min(arg->peer_nss, tx_nss); ++ ++ arg->peer_nss = min(sta->deflink.rx_nss, ar->num_rx_chains); + arg->peer_bw_rxnss_override = ATH12K_BW_NSS_MAP_ENABLE; + + if (!rx_nss) { +@@ -5635,6 +5637,12 @@ ath12k_create_vht_cap(struct ath12k *ar, + vht_cap.vht_mcs.rx_mcs_map = cpu_to_le16(rxmcs_map); + vht_cap.vht_mcs.tx_mcs_map = cpu_to_le16(txmcs_map); + ++ /* Check if the HW supports 1:1 NSS ratio and reset ++ * EXT NSS BW Support field to 0 to indicate 1:1 ratio ++ */ ++ if (ar->pdev->cap.nss_ratio_info == WMI_NSS_RATIO_1_NSS) ++ vht_cap.cap &= ~IEEE80211_VHT_CAP_EXT_NSS_BW_MASK; ++ + return vht_cap; + } + +@@ -5815,11 +5823,12 @@ static void ath12k_mac_set_hemcsmap(stru + struct ieee80211_sta_he_cap *he_cap) + { + struct ieee80211_he_mcs_nss_supp *mcs_nss = &he_cap->he_mcs_nss_supp; +- u16 txmcs_map, rxmcs_map; ++ u8 maxtxnss_160 = ath12k_get_nss_160mhz(ar, ar->num_tx_chains); ++ u8 maxrxnss_160 = ath12k_get_nss_160mhz(ar, ar->num_rx_chains); ++ u16 txmcs_map_160 = 0, rxmcs_map_160 = 0; ++ u16 txmcs_map = 0, rxmcs_map = 0; + u32 i; + +- rxmcs_map = 0; +- txmcs_map = 0; + for (i = 0; i < 8; i++) { + if (i < ar->num_tx_chains && + (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) +@@ -5832,12 +5841,24 @@ static void ath12k_mac_set_hemcsmap(stru + rxmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + rxmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ ++ if (i < maxtxnss_160 && ++ (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) ++ txmcs_map_160 |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ txmcs_map_160 |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ ++ if (i < maxrxnss_160 && ++ (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) ++ rxmcs_map_160 |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ rxmcs_map_160 |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); + } + + mcs_nss->rx_mcs_80 = cpu_to_le16(rxmcs_map & 0xffff); + mcs_nss->tx_mcs_80 = cpu_to_le16(txmcs_map & 0xffff); +- mcs_nss->rx_mcs_160 = cpu_to_le16(rxmcs_map & 0xffff); +- mcs_nss->tx_mcs_160 = cpu_to_le16(txmcs_map & 0xffff); ++ mcs_nss->rx_mcs_160 = cpu_to_le16(rxmcs_map_160 & 0xffff); ++ mcs_nss->tx_mcs_160 = cpu_to_le16(txmcs_map_160 & 0xffff); + } + + static void ath12k_mac_copy_he_cap(struct ath12k *ar, diff --git a/package/kernel/mac80211/patches/subsys/306-wifi-mac80211-call-rate_control_rate_update-for-link.patch b/package/kernel/mac80211/patches/subsys/306-wifi-mac80211-call-rate_control_rate_update-for-link.patch new file mode 100644 index 0000000000..0ccdfb9fb5 --- /dev/null +++ b/package/kernel/mac80211/patches/subsys/306-wifi-mac80211-call-rate_control_rate_update-for-link.patch @@ -0,0 +1,548 @@ +From: Johannes Berg +Date: Mon, 7 Oct 2024 15:00:54 +0300 +Subject: [PATCH] wifi: mac80211: call rate_control_rate_update() for link STA + +In order to update the right link information, call the update +rate_control_rate_update() with the right link_sta, and then +pass that through to the driver's sta_rc_update() method. The +software rate control still doesn't support it, but that'll be +skipped by not having a rate control ref. + +Since it now operates on a link sta, rename the driver method. + +Signed-off-by: Johannes Berg +Signed-off-by: Miri Korenblit +Link: https://patch.msgid.link/20241007144851.5851b6b5fd41.Ibdf50d96afa4b761dd9b9dfd54a1147e77a75329@changeid +Signed-off-by: Johannes Berg +--- + +--- a/drivers/net/wireless/ath/ath10k/mac.c ++++ b/drivers/net/wireless/ath/ath10k/mac.c +@@ -8507,9 +8507,10 @@ exit: + + static void ath10k_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct ath10k *ar = hw->priv; + struct ath10k_sta *arsta = (struct ath10k_sta *)sta->drv_priv; + struct ath10k_vif *arvif = (void *)vif->drv_priv; +@@ -9450,7 +9451,7 @@ static const struct ieee80211_ops ath10k + .reconfig_complete = ath10k_reconfig_complete, + .get_survey = ath10k_get_survey, + .set_bitrate_mask = ath10k_mac_op_set_bitrate_mask, +- .sta_rc_update = ath10k_sta_rc_update, ++ .link_sta_rc_update = ath10k_sta_rc_update, + .offset_tsf = ath10k_offset_tsf, + .ampdu_action = ath10k_ampdu_action, + .get_et_sset_count = ath10k_debug_get_et_sset_count, +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -5079,9 +5079,10 @@ static void ath11k_mac_op_sta_set_4addr( + + static void ath11k_mac_op_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct ath11k *ar = hw->priv; + struct ath11k_sta *arsta = ath11k_sta_to_arsta(sta); + struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); +@@ -9708,7 +9709,7 @@ static const struct ieee80211_ops ath11k + .sta_state = ath11k_mac_op_sta_state, + .sta_set_4addr = ath11k_mac_op_sta_set_4addr, + .sta_set_txpwr = ath11k_mac_op_sta_set_txpwr, +- .sta_rc_update = ath11k_mac_op_sta_rc_update, ++ .link_sta_rc_update = ath11k_mac_op_sta_rc_update, + .conf_tx = ath11k_mac_op_conf_tx, + .set_antenna = ath11k_mac_op_set_antenna, + .get_antenna = ath11k_mac_op_get_antenna, +--- a/drivers/net/wireless/ath/ath12k/mac.c ++++ b/drivers/net/wireless/ath/ath12k/mac.c +@@ -4740,9 +4740,10 @@ out: + + static void ath12k_mac_op_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct ath12k *ar; + struct ath12k_sta *arsta = ath12k_sta_to_arsta(sta); + struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); +@@ -8684,7 +8685,7 @@ static const struct ieee80211_ops ath12k + .set_rekey_data = ath12k_mac_op_set_rekey_data, + .sta_state = ath12k_mac_op_sta_state, + .sta_set_txpwr = ath12k_mac_op_sta_set_txpwr, +- .sta_rc_update = ath12k_mac_op_sta_rc_update, ++ .link_sta_rc_update = ath12k_mac_op_sta_rc_update, + .conf_tx = ath12k_mac_op_conf_tx, + .set_antenna = ath12k_mac_op_set_antenna, + .get_antenna = ath12k_mac_op_get_antenna, +--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c ++++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c +@@ -1357,8 +1357,10 @@ static int ath9k_htc_sta_remove(struct i + + static void ath9k_htc_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, u32 changed) ++ struct ieee80211_link_sta *link_sta, ++ u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct ath9k_htc_sta *ista = (struct ath9k_htc_sta *) sta->drv_priv; + + if (!(changed & IEEE80211_RC_SUPP_RATES_CHANGED)) +@@ -1883,7 +1885,7 @@ struct ieee80211_ops ath9k_htc_ops = { + .sta_add = ath9k_htc_sta_add, + .sta_remove = ath9k_htc_sta_remove, + .conf_tx = ath9k_htc_conf_tx, +- .sta_rc_update = ath9k_htc_sta_rc_update, ++ .link_sta_rc_update = ath9k_htc_sta_rc_update, + .bss_info_changed = ath9k_htc_bss_info_changed, + .set_key = ath9k_htc_set_key, + .get_tsf = ath9k_htc_get_tsf, +--- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +@@ -4248,8 +4248,9 @@ int iwl_mvm_mac_set_rts_threshold(struct + } + + void iwl_mvm_sta_rc_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, u32 changed) ++ struct ieee80211_link_sta *link_sta, u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct iwl_mvm *mvm = IWL_MAC80211_GET_MVM(hw); + + if (changed & (IEEE80211_RC_BW_CHANGED | +@@ -6574,7 +6575,7 @@ const struct ieee80211_ops iwl_mvm_hw_op + .allow_buffered_frames = iwl_mvm_mac_allow_buffered_frames, + .release_buffered_frames = iwl_mvm_mac_release_buffered_frames, + .set_rts_threshold = iwl_mvm_mac_set_rts_threshold, +- .sta_rc_update = iwl_mvm_sta_rc_update, ++ .link_sta_rc_update = iwl_mvm_sta_rc_update, + .conf_tx = iwl_mvm_mac_conf_tx, + .mgd_prepare_tx = iwl_mvm_mac_mgd_prepare_tx, + .mgd_complete_tx = iwl_mvm_mac_mgd_complete_tx, +--- a/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c +@@ -1413,7 +1413,7 @@ const struct ieee80211_ops iwl_mvm_mld_h + .allow_buffered_frames = iwl_mvm_mac_allow_buffered_frames, + .release_buffered_frames = iwl_mvm_mac_release_buffered_frames, + .set_rts_threshold = iwl_mvm_mac_set_rts_threshold, +- .sta_rc_update = iwl_mvm_sta_rc_update, ++ .link_sta_rc_update = iwl_mvm_sta_rc_update, + .conf_tx = iwl_mvm_mld_mac_conf_tx, + .mgd_prepare_tx = iwl_mvm_mac_mgd_prepare_tx, + .mgd_complete_tx = iwl_mvm_mac_mgd_complete_tx, +--- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h ++++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +@@ -2914,7 +2914,7 @@ iwl_mvm_mac_release_buffered_frames(stru + bool more_data); + int iwl_mvm_mac_set_rts_threshold(struct ieee80211_hw *hw, u32 value); + void iwl_mvm_sta_rc_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, u32 changed); ++ struct ieee80211_link_sta *link_sta, u32 changed); + void iwl_mvm_mac_mgd_prepare_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_prep_tx_info *info); +--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c ++++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c +@@ -1163,9 +1163,10 @@ static void mt7915_sta_rc_work(void *dat + + static void mt7915_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct mt7915_phy *phy = mt7915_hw_phy(hw); + struct mt7915_dev *dev = phy->dev; + struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; +@@ -1709,7 +1710,7 @@ const struct ieee80211_ops mt7915_ops = + .stop_ap = mt7915_stop_ap, + .sta_state = mt76_sta_state, + .sta_pre_rcu_remove = mt76_sta_pre_rcu_remove, +- .sta_rc_update = mt7915_sta_rc_update, ++ .link_sta_rc_update = mt7915_sta_rc_update, + .set_key = mt7915_set_key, + .ampdu_action = mt7915_ampdu_action, + .set_rts_threshold = mt7915_set_rts_threshold, +--- a/drivers/net/wireless/mediatek/mt76/mt7996/main.c ++++ b/drivers/net/wireless/mediatek/mt76/mt7996/main.c +@@ -1060,9 +1060,10 @@ static void mt7996_sta_rc_work(void *dat + + static void mt7996_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct mt7996_phy *phy = mt7996_hw_phy(hw); + struct mt7996_dev *dev = phy->dev; + +@@ -1472,7 +1473,7 @@ const struct ieee80211_ops mt7996_ops = + .sta_add = mt7996_sta_add, + .sta_remove = mt7996_sta_remove, + .sta_pre_rcu_remove = mt76_sta_pre_rcu_remove, +- .sta_rc_update = mt7996_sta_rc_update, ++ .link_sta_rc_update = mt7996_sta_rc_update, + .set_key = mt7996_set_key, + .ampdu_action = mt7996_ampdu_action, + .set_rts_threshold = mt7996_set_rts_threshold, +--- a/drivers/net/wireless/realtek/rtw88/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw88/mac80211.c +@@ -928,8 +928,10 @@ static int rtw_ops_set_sar_specs(struct + + static void rtw_ops_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, u32 changed) ++ struct ieee80211_link_sta *link_sta, ++ u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct rtw_dev *rtwdev = hw->priv; + struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; + +@@ -973,7 +975,7 @@ const struct ieee80211_ops rtw_ops = { + .reconfig_complete = rtw_reconfig_complete, + .hw_scan = rtw_ops_hw_scan, + .cancel_hw_scan = rtw_ops_cancel_hw_scan, +- .sta_rc_update = rtw_ops_sta_rc_update, ++ .link_sta_rc_update = rtw_ops_sta_rc_update, + .set_sar_specs = rtw_ops_set_sar_specs, + #ifdef CONFIG_PM + .suspend = rtw_ops_suspend, +--- a/drivers/net/wireless/realtek/rtw89/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -1290,8 +1290,10 @@ out: + + static void rtw89_ops_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, u32 changed) ++ struct ieee80211_link_sta *link_sta, ++ u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct rtw89_dev *rtwdev = hw->priv; + + rtw89_phy_ra_update_sta(rtwdev, sta, changed); +@@ -1594,7 +1596,7 @@ const struct ieee80211_ops rtw89_ops = { + .remain_on_channel = rtw89_ops_remain_on_channel, + .cancel_remain_on_channel = rtw89_ops_cancel_remain_on_channel, + .set_sar_specs = rtw89_ops_set_sar_specs, +- .sta_rc_update = rtw89_ops_sta_rc_update, ++ .link_sta_rc_update = rtw89_ops_sta_rc_update, + .set_tid_config = rtw89_ops_set_tid_config, + #ifdef CONFIG_PM + .suspend = rtw89_ops_suspend, +--- a/drivers/net/wireless/ti/wlcore/main.c ++++ b/drivers/net/wireless/ti/wlcore/main.c +@@ -5789,9 +5789,10 @@ static int wlcore_op_cancel_remain_on_ch + + static void wlcore_op_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { ++ struct ieee80211_sta *sta = link_sta->sta; + struct wl12xx_vif *wlvif = wl12xx_vif_to_data(vif); + + wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update"); +@@ -6052,7 +6053,7 @@ static const struct ieee80211_ops wl1271 + .assign_vif_chanctx = wlcore_op_assign_vif_chanctx, + .unassign_vif_chanctx = wlcore_op_unassign_vif_chanctx, + .switch_vif_chanctx = wlcore_op_switch_vif_chanctx, +- .sta_rc_update = wlcore_op_sta_rc_update, ++ .link_sta_rc_update = wlcore_op_sta_rc_update, + .sta_statistics = wlcore_op_sta_statistics, + .get_expected_throughput = wlcore_op_get_expected_throughput, + CFG80211_TESTMODE_CMD(wl1271_tm_cmd) +--- a/drivers/net/wireless/virtual/mac80211_hwsim.c ++++ b/drivers/net/wireless/virtual/mac80211_hwsim.c +@@ -2594,10 +2594,11 @@ static void mac80211_hwsim_link_info_cha + static void + mac80211_hwsim_sta_rc_update(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed) + { + struct mac80211_hwsim_data *data = hw->priv; ++ struct ieee80211_sta *sta = link_sta->sta; + u32 bw = U32_MAX; + int link_id; + +@@ -2607,7 +2608,6 @@ mac80211_hwsim_sta_rc_update(struct ieee + link_id++) { + enum nl80211_chan_width confbw = NL80211_CHAN_WIDTH_20_NOHT; + struct ieee80211_bss_conf *vif_conf; +- struct ieee80211_link_sta *link_sta; + + link_sta = rcu_dereference(sta->link[link_id]); + +@@ -2659,7 +2659,7 @@ static int mac80211_hwsim_sta_add(struct + + hwsim_check_magic(vif); + hwsim_set_sta_magic(sta); +- mac80211_hwsim_sta_rc_update(hw, vif, sta, 0); ++ mac80211_hwsim_sta_rc_update(hw, vif, &sta->deflink, 0); + + if (sta->valid_links) { + WARN(hweight16(sta->valid_links) > 1, +@@ -3961,7 +3961,7 @@ out: + .link_info_changed = mac80211_hwsim_link_info_changed, \ + .tx_last_beacon = mac80211_hwsim_tx_last_beacon, \ + .sta_notify = mac80211_hwsim_sta_notify, \ +- .sta_rc_update = mac80211_hwsim_sta_rc_update, \ ++ .link_sta_rc_update = mac80211_hwsim_sta_rc_update, \ + .conf_tx = mac80211_hwsim_conf_tx, \ + .get_survey = mac80211_hwsim_get_survey, \ + CFG80211_TESTMODE_CMD(mac80211_hwsim_testmode_cmd) \ +--- a/include/net/mac80211.h ++++ b/include/net/mac80211.h +@@ -4075,8 +4075,8 @@ struct ieee80211_prep_tx_info { + * in @sta_state. + * The callback can sleep. + * +- * @sta_rc_update: Notifies the driver of changes to the bitrates that can be +- * used to transmit to the station. The changes are advertised with bits ++ * @link_sta_rc_update: Notifies the driver of changes to the bitrates that can ++ * be used to transmit to the station. The changes are advertised with bits + * from &enum ieee80211_rate_control_changed and the values are reflected + * in the station data. This callback should only be used when the driver + * uses hardware rate control (%IEEE80211_HW_HAS_RATE_CONTROL) since +@@ -4560,10 +4560,10 @@ struct ieee80211_ops { + void (*sta_pre_rcu_remove)(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta); +- void (*sta_rc_update)(struct ieee80211_hw *hw, +- struct ieee80211_vif *vif, +- struct ieee80211_sta *sta, +- u32 changed); ++ void (*link_sta_rc_update)(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_link_sta *link_sta, ++ u32 changed); + void (*sta_rate_tbl_update)(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta); +--- a/net/mac80211/chan.c ++++ b/net/mac80211/chan.c +@@ -467,7 +467,7 @@ static void ieee80211_chan_bw_change(str + continue; + + link_sta->pub->bandwidth = new_sta_bw; +- rate_control_rate_update(local, sband, sta, link_id, ++ rate_control_rate_update(local, sband, link_sta, + IEEE80211_RC_BW_CHANGED); + } + } +--- a/net/mac80211/driver-ops.c ++++ b/net/mac80211/driver-ops.c +@@ -181,9 +181,10 @@ int drv_sta_set_txpwr(struct ieee80211_l + return ret; + } + +-void drv_sta_rc_update(struct ieee80211_local *local, +- struct ieee80211_sub_if_data *sdata, +- struct ieee80211_sta *sta, u32 changed) ++void drv_link_sta_rc_update(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ struct ieee80211_link_sta *link_sta, ++ u32 changed) + { + sdata = get_bss_sdata(sdata); + if (!check_sdata_in_driver(sdata)) +@@ -193,10 +194,10 @@ void drv_sta_rc_update(struct ieee80211_ + (sdata->vif.type != NL80211_IFTYPE_ADHOC && + sdata->vif.type != NL80211_IFTYPE_MESH_POINT)); + +- trace_drv_sta_rc_update(local, sdata, sta, changed); +- if (local->ops->sta_rc_update) +- local->ops->sta_rc_update(&local->hw, &sdata->vif, +- sta, changed); ++ trace_drv_link_sta_rc_update(local, sdata, link_sta, changed); ++ if (local->ops->link_sta_rc_update) ++ local->ops->link_sta_rc_update(&local->hw, &sdata->vif, ++ link_sta, changed); + + trace_drv_return_void(local); + } +--- a/net/mac80211/driver-ops.h ++++ b/net/mac80211/driver-ops.h +@@ -594,9 +594,9 @@ int drv_sta_set_txpwr(struct ieee80211_l + struct ieee80211_sub_if_data *sdata, + struct sta_info *sta); + +-void drv_sta_rc_update(struct ieee80211_local *local, +- struct ieee80211_sub_if_data *sdata, +- struct ieee80211_sta *sta, u32 changed); ++void drv_link_sta_rc_update(struct ieee80211_local *local, ++ struct ieee80211_sub_if_data *sdata, ++ struct ieee80211_link_sta *link_sta, u32 changed); + + static inline void drv_sta_rate_tbl_update(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, +--- a/net/mac80211/ibss.c ++++ b/net/mac80211/ibss.c +@@ -1072,7 +1072,8 @@ static void ieee80211_update_sta_info(st + if (sta->sta.deflink.rx_nss != rx_nss) + changed |= IEEE80211_RC_NSS_CHANGED; + +- drv_sta_rc_update(local, sdata, &sta->sta, changed); ++ drv_link_sta_rc_update(local, sdata, &sta->sta.deflink, ++ changed); + } + + rcu_read_unlock(); +--- a/net/mac80211/mesh_plink.c ++++ b/net/mac80211/mesh_plink.c +@@ -489,7 +489,7 @@ static void mesh_sta_info_init(struct ie + if (!test_sta_flag(sta, WLAN_STA_RATE_CONTROL)) + rate_control_rate_init(sta); + else +- rate_control_rate_update(local, sband, sta, 0, changed); ++ rate_control_rate_update(local, sband, &sta->deflink, changed); + out: + spin_unlock_bh(&sta->mesh->plink_lock); + } +--- a/net/mac80211/rate.c ++++ b/net/mac80211/rate.c +@@ -93,16 +93,15 @@ void rate_control_tx_status(struct ieee8 + + void rate_control_rate_update(struct ieee80211_local *local, + struct ieee80211_supported_band *sband, +- struct sta_info *sta, unsigned int link_id, ++ struct link_sta_info *link_sta, + u32 changed) + { + struct rate_control_ref *ref = local->rate_ctrl; ++ struct sta_info *sta = link_sta->sta; + struct ieee80211_sta *ista = &sta->sta; + void *priv_sta = sta->rate_ctrl_priv; + struct ieee80211_chanctx_conf *chanctx_conf; + +- WARN_ON(link_id != 0); +- + if (ref && ref->ops->rate_update) { + rcu_read_lock(); + +@@ -120,7 +119,8 @@ void rate_control_rate_update(struct iee + } + + if (sta->uploaded) +- drv_sta_rc_update(local, sta->sdata, &sta->sta, changed); ++ drv_link_sta_rc_update(local, sta->sdata, link_sta->pub, ++ changed); + } + + int ieee80211_rate_control_register(const struct rate_control_ops *ops) +--- a/net/mac80211/rate.h ++++ b/net/mac80211/rate.h +@@ -32,8 +32,7 @@ void rate_control_tx_status(struct ieee8 + void rate_control_rate_init(struct sta_info *sta); + void rate_control_rate_update(struct ieee80211_local *local, + struct ieee80211_supported_band *sband, +- struct sta_info *sta, +- unsigned int link_id, ++ struct link_sta_info *link_sta, + u32 changed); + + static inline void *rate_control_alloc_sta(struct rate_control_ref *ref, +--- a/net/mac80211/rx.c ++++ b/net/mac80211/rx.c +@@ -3568,7 +3568,7 @@ ieee80211_rx_h_action(struct ieee80211_r + + sband = rx->local->hw.wiphy->bands[status->band]; + +- rate_control_rate_update(local, sband, rx->sta, 0, ++ rate_control_rate_update(local, sband, rx->link_sta, + IEEE80211_RC_SMPS_CHANGED); + cfg80211_sta_opmode_change_notify(sdata->dev, + rx->sta->addr, +@@ -3605,7 +3605,7 @@ ieee80211_rx_h_action(struct ieee80211_r + ieee80211_sta_rx_bw_to_chan_width(rx->link_sta); + sta_opmode.changed = STA_OPMODE_MAX_BW_CHANGED; + +- rate_control_rate_update(local, sband, rx->sta, 0, ++ rate_control_rate_update(local, sband, rx->link_sta, + IEEE80211_RC_BW_CHANGED); + cfg80211_sta_opmode_change_notify(sdata->dev, + rx->sta->addr, +--- a/net/mac80211/tdls.c ++++ b/net/mac80211/tdls.c +@@ -1342,7 +1342,8 @@ static void iee80211_tdls_recalc_chanctx + bw = min(bw, ieee80211_sta_cap_rx_bw(&sta->deflink)); + if (bw != sta->sta.deflink.bandwidth) { + sta->sta.deflink.bandwidth = bw; +- rate_control_rate_update(local, sband, sta, 0, ++ rate_control_rate_update(local, sband, ++ &sta->deflink, + IEEE80211_RC_BW_CHANGED); + /* + * if a TDLS peer BW was updated, we need to +--- a/net/mac80211/trace.h ++++ b/net/mac80211/trace.h +@@ -945,31 +945,34 @@ TRACE_EVENT(drv_sta_set_txpwr, + ) + ); + +-TRACE_EVENT(drv_sta_rc_update, ++TRACE_EVENT(drv_link_sta_rc_update, + TP_PROTO(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, +- struct ieee80211_sta *sta, ++ struct ieee80211_link_sta *link_sta, + u32 changed), + +- TP_ARGS(local, sdata, sta, changed), ++ TP_ARGS(local, sdata, link_sta, changed), + + TP_STRUCT__entry( + LOCAL_ENTRY + VIF_ENTRY + STA_ENTRY + __field(u32, changed) ++ __field(u32, link_id) + ), + + TP_fast_assign( + LOCAL_ASSIGN; + VIF_ASSIGN; +- STA_ASSIGN; ++ STA_NAMED_ASSIGN(link_sta->sta); + __entry->changed = changed; ++ __entry->link_id = link_sta->link_id; + ), + + TP_printk( +- LOCAL_PR_FMT VIF_PR_FMT STA_PR_FMT " changed: 0x%x", +- LOCAL_PR_ARG, VIF_PR_ARG, STA_PR_ARG, __entry->changed ++ LOCAL_PR_FMT VIF_PR_FMT STA_PR_FMT " (link %d) changed: 0x%x", ++ LOCAL_PR_ARG, VIF_PR_ARG, STA_PR_ARG, __entry->link_id, ++ __entry->changed + ) + ); + +--- a/net/mac80211/vht.c ++++ b/net/mac80211/vht.c +@@ -766,8 +766,7 @@ void ieee80211_vht_handle_opmode(struct + + if (changed > 0) { + ieee80211_recalc_min_chandef(sdata, link_sta->link_id); +- rate_control_rate_update(local, sband, link_sta->sta, +- link_sta->link_id, changed); ++ rate_control_rate_update(local, sband, link_sta, changed); + } + } + diff --git a/package/kernel/mac80211/patches/subsys/334-wifi-cfg80211-pass-net_device-to-.set_monitor_channel.patch b/package/kernel/mac80211/patches/subsys/334-wifi-cfg80211-pass-net_device-to-.set_monitor_channel.patch index ef8a36a9af..626f2facaf 100644 --- a/package/kernel/mac80211/patches/subsys/334-wifi-cfg80211-pass-net_device-to-.set_monitor_channel.patch +++ b/package/kernel/mac80211/patches/subsys/334-wifi-cfg80211-pass-net_device-to-.set_monitor_channel.patch @@ -126,7 +126,7 @@ Signed-off-by: Felix Fietkau } --- a/net/wireless/trace.h +++ b/net/wireless/trace.h -@@ -1318,19 +1318,21 @@ TRACE_EVENT(rdev_libertas_set_mesh_chann +@@ -1322,19 +1322,21 @@ TRACE_EVENT(rdev_libertas_set_mesh_chann ); TRACE_EVENT(rdev_set_monitor_channel, diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index bbc9cac552..6befd8c497 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -8,9 +8,9 @@ PKG_LICENSE_FILES:= PKG_SOURCE_URL:=https://github.com/openwrt/mt76 PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2025-02-14 -PKG_SOURCE_VERSION:=e5fef138524e63314cb96ff8314048d175294e95 -PKG_MIRROR_HASH:=4d6ea8669b3034c97f5b341a5473facf4fe21262a2fde71257b57c4d1c86be5e +PKG_SOURCE_DATE:=2025-04-11 +PKG_SOURCE_VERSION:=be28ef77e330fdee28054214c798f028ddfbbc02 +PKG_MIRROR_HASH:=71d0651fd74b00fd83f5ea965483623dd6b33581c9cb0a05552d8e3d29dd2767 PKG_MAINTAINER:=Felix Fietkau PKG_USE_NINJA:=0 diff --git a/package/kernel/r8127/Makefile b/package/kernel/r8127/Makefile new file mode 100644 index 0000000000..bb0c5e0a6c --- /dev/null +++ b/package/kernel/r8127/Makefile @@ -0,0 +1,47 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=r8127 +PKG_VERSION:=11.014.00 +PKG_RELEASE:=1 + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 +PKG_SOURCE_URL:=https://github.com/openwrt/rtl8127/releases/download/$(PKG_VERSION) +PKG_HASH:=f496bc16c32d2e8f9482c57d006604c70d9e8d55b4f1f999b88c602de9104094 + +PKG_BUILD_PARALLEL:=1 +PKG_LICENSE:=GPLv2 +PKG_MAINTAINER:=Alvaro Fernandez Rojas + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/r8127 + SUBMENU:=Network Devices + TITLE:=Realtek RTL8127 PCI 10 Gigabit Ethernet driver + DEPENDS:=@PCI_SUPPORT +kmod-libphy + FILES:=$(PKG_BUILD_DIR)/src/r8127.ko + AUTOLOAD:=$(call AutoProbe,r8127) + PROVIDES:=kmod-r8169 + VARIANT:=regular +endef + +define KernelPackage/r8127-rss +$(call KernelPackage/r8127) + CONFLICTS:=kmod-r8127 + TITLE+= (RSS) + VARIANT:=rss +endef + +ifeq ($(BUILD_VARIANT),rss) + PKG_MAKE_FLAGS += ENABLE_RSS_SUPPORT=y +endif + +define Build/Compile + +$(KERNEL_MAKE) $(PKG_JOBS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)/src" \ + modules +endef + +$(eval $(call KernelPackage,r8127)) +$(eval $(call KernelPackage,r8127-rss)) diff --git a/package/kernel/r8127/patches/200-r8127-print-link-speed-and-duplex-mode.patch b/package/kernel/r8127/patches/200-r8127-print-link-speed-and-duplex-mode.patch new file mode 100644 index 0000000000..2a42820785 --- /dev/null +++ b/package/kernel/r8127/patches/200-r8127-print-link-speed-and-duplex-mode.patch @@ -0,0 +1,107 @@ +From 5ca1d47e065c0318774a946ffdf76010c78cc164 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 10 Aug 2024 20:16:32 +0800 +Subject: [PATCH] r8127: print link speed and duplex mode +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Like other Ethernet drivers, print link speed and duplex mode +when the interface is up. Formatting output at the same time. + +Signed-off-by: Chukun Pan +Signed-off-by: Álvaro Fernández Rojas +--- + src/r8127.h | 2 ++ + src/r8127_n.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- + 2 files changed, 47 insertions(+), 3 deletions(-) + +--- a/src/r8127.h ++++ b/src/r8127.h +@@ -1753,6 +1753,11 @@ enum RTL8127_register_content { + LinkStatus = 0x02, + FullDup = 0x01, + ++#define RTL8127_FULL_DUPLEX_MASK (_10000bpsF | _5000bpsF | _2500bpsF | _1000bpsF | FullDup) ++#define RTL8127_SPEED_1000_MASK (_1000bpsF | _1000bpsL | _2500bpsL) ++#define RTL8127_SPEED_2500_MASK (_2500bpsF | _5000bpsL) ++#define RTL8127_SPEED_5000_MASK (_5000bpsF | _10000bpsL) ++ + /* DBG_reg */ + Fix_Nak_1 = (1 << 4), + Fix_Nak_2 = (1 << 3), +--- a/src/r8127_n.c ++++ b/src/r8127_n.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -4746,6 +4747,42 @@ rtl8127_link_down_patch(struct net_devic + #endif + } + ++static unsigned int rtl8127_phy_duplex(u32 status) ++{ ++ unsigned int duplex = DUPLEX_UNKNOWN; ++ ++ if (status & LinkStatus) { ++ if (status & RTL8127_FULL_DUPLEX_MASK) ++ duplex = DUPLEX_FULL; ++ else ++ duplex = DUPLEX_HALF; ++ } ++ ++ return duplex; ++} ++ ++static int rtl8127_phy_speed(u32 status) ++{ ++ int speed = SPEED_UNKNOWN; ++ ++ if (status & LinkStatus) { ++ if (status & _10000bpsF) ++ speed = SPEED_10000; ++ else if (status & RTL8127_SPEED_5000_MASK) ++ speed = SPEED_5000; ++ else if (status & RTL8127_SPEED_2500_MASK) ++ speed = SPEED_2500; ++ else if (status & RTL8127_SPEED_1000_MASK) ++ speed = SPEED_1000; ++ else if (status & _100bps) ++ speed = SPEED_100; ++ else if (status & _10bps) ++ speed = SPEED_10; ++ } ++ ++ return speed; ++} ++ + static void + _rtl8127_check_link_status(struct net_device *dev, unsigned int link_state) + { +@@ -4758,11 +4795,18 @@ _rtl8127_check_link_status(struct net_de + if (link_state == R8127_LINK_STATE_ON) { + rtl8127_link_on_patch(dev); + +- if (netif_msg_ifup(tp)) +- printk(KERN_INFO PFX "%s: link up\n", dev->name); ++ if (netif_msg_ifup(tp)) { ++ const u32 phy_status = RTL_R32(tp, PHYstatus); ++ const unsigned int phy_duplex = rtl8127_phy_duplex(phy_status); ++ const int phy_speed = rtl8127_phy_speed(phy_status); ++ printk(KERN_INFO PFX "%s: Link is Up - %s/%s\n", ++ dev->name, ++ phy_speed_to_str(phy_speed), ++ phy_duplex_to_str(phy_duplex)); ++ } + } else { + if (netif_msg_ifdown(tp)) +- printk(KERN_INFO PFX "%s: link down\n", dev->name); ++ printk(KERN_INFO PFX "%s: Link is Down\n", dev->name); + + rtl8127_link_down_patch(dev); + } diff --git a/package/kernel/ubootenv-nvram/src/ubootenv-nvram.c b/package/kernel/ubootenv-nvram/src/ubootenv-nvram.c index 106e41231c..ba1d7973f1 100644 --- a/package/kernel/ubootenv-nvram/src/ubootenv-nvram.c +++ b/package/kernel/ubootenv-nvram/src/ubootenv-nvram.c @@ -132,18 +132,17 @@ static int ubootenv_probe(struct platform_device *pdev) return misc_register(&data->misc); } -static int ubootenv_remove(struct platform_device *pdev) +static void ubootenv_remove(struct platform_device *pdev) { struct ubootenv_drvdata *data = platform_get_drvdata(pdev); data->env = NULL; misc_deregister(&data->misc); - return 0; } static struct platform_driver ubootenv_driver = { .probe = ubootenv_probe, - .remove = ubootenv_remove, + .remove_new = ubootenv_remove, .driver = { .name = NAME, .of_match_table = of_ubootenv_match, diff --git a/package/network/config/wifi-scripts/files/etc/hotplug.d/ieee80211/11-ath12k-trigger b/package/network/config/wifi-scripts/files/etc/hotplug.d/ieee80211/11-ath12k-trigger new file mode 100755 index 0000000000..3c07e52882 --- /dev/null +++ b/package/network/config/wifi-scripts/files/etc/hotplug.d/ieee80211/11-ath12k-trigger @@ -0,0 +1,36 @@ +#!/bin/sh + +# Restart ath12k radios that take long time to initialize on boot + +[ "${ACTION}" = "add" ] || exit 0 +[ $(grep -c DRIVER=ath12k_pci /sys/$DEVPATH/device/uevent) -gt 0 ] || exit 0 + +. /usr/share/libubox/jshn.sh + +restart_radio() { + radio=$1 + arg="{\"radio\": \"$radio\"}" + ubus call network reload + ubus call network.wireless down "$arg" + ubus call network.wireless up "$arg" +} + +json_init +json_load "$(ubus -S call network.wireless status)" +json_get_keys radios +for radio in $radios; do + json_select $radio + json_get_vars up + json_get_vars retry_setup_failed + + json_select config + json_get_vars path + json_select .. + + if [ $up = 0 -a $retry_setup_failed = 1 ] && + [ $(iwinfo nl80211 phyname "path=$path") = "$DEVICENAME" ]; then + restart_radio $radio + fi + + json_select .. +done diff --git a/package/network/services/dnsmasq/Makefile b/package/network/services/dnsmasq/Makefile index 47a5ae54ae..5290f1e468 100644 --- a/package/network/services/dnsmasq/Makefile +++ b/package/network/services/dnsmasq/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dnsmasq -PKG_UPSTREAM_VERSION:=2.90 +PKG_UPSTREAM_VERSION:=2.91 PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION))) -PKG_RELEASE:=4 +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz PKG_SOURCE_URL:=https://thekelleys.org.uk/dnsmasq/ -PKG_HASH:=8e50309bd837bfec9649a812e066c09b6988b73d749b7d293c06c57d46a109e4 +PKG_HASH:=f622682848b33677adb2b6ad08264618a2ae0a01da486a93fd8cd91186b3d153 PKG_LICENSE:=GPL-2.0 PKG_LICENSE_FILES:=COPYING diff --git a/package/network/services/dnsmasq/patches/0001-Fix-spurious-resource-limit-exceeded-messages.patch b/package/network/services/dnsmasq/patches/0001-Fix-spurious-resource-limit-exceeded-messages.patch deleted file mode 100644 index f25ee20413..0000000000 --- a/package/network/services/dnsmasq/patches/0001-Fix-spurious-resource-limit-exceeded-messages.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 1ed783b8d7343c42910a61f12a8fc6237eb80417 Mon Sep 17 00:00:00 2001 -From: Simon Kelley -Date: Mon, 19 Feb 2024 12:22:43 +0000 -Subject: Fix spurious "resource limit exceeded" messages. - -Replies from upstream with a REFUSED rcode can result in -log messages stating that a resource limit has been exceeded, -which is not the case. - -Thanks to Dominik Derigs and the Pi-hole project for -spotting this. ---- - CHANGELOG | 5 +++++ - src/forward.c | 6 +++--- - 2 files changed, 8 insertions(+), 3 deletions(-) - ---- a/CHANGELOG -+++ b/CHANGELOG -@@ -1,3 +1,8 @@ -+version 2.91 -+ Fix spurious "resource limit exceeded messages". Thanks to -+ Dominik Derigs for the bug report. -+ -+ - version 2.90 - Fix reversion in --rev-server introduced in 2.88 which - caused breakage if the prefix length is not exactly divisible ---- a/src/forward.c -+++ b/src/forward.c -@@ -937,10 +937,10 @@ static void dnssec_validate(struct frec - status = dnssec_validate_reply(now, header, plen, daemon->namebuff, daemon->keyname, &forward->class, - !option_bool(OPT_DNSSEC_IGN_NS) && (forward->sentto->flags & SERV_DO_DNSSEC), - NULL, NULL, NULL, &orig->validate_counter); -- } - -- if (STAT_ISEQUAL(status, STAT_ABANDONED)) -- log_resource = 1; -+ if (STAT_ISEQUAL(status, STAT_ABANDONED)) -+ log_resource = 1; -+ } - - /* Can't validate, as we're missing key data. Put this - answer aside, whilst we get that. */ diff --git a/package/network/services/dnsmasq/patches/0002-PATCH-Fix-error-introduced-in-51471cafa5a4fa44d6fe49.patch b/package/network/services/dnsmasq/patches/0002-PATCH-Fix-error-introduced-in-51471cafa5a4fa44d6fe49.patch deleted file mode 100644 index 5c50ae8446..0000000000 --- a/package/network/services/dnsmasq/patches/0002-PATCH-Fix-error-introduced-in-51471cafa5a4fa44d6fe49.patch +++ /dev/null @@ -1,31 +0,0 @@ -From ccff85ad72d2f858d9743d40525128e4f62d41a8 Mon Sep 17 00:00:00 2001 -From: renmingshuai -Date: Wed, 21 Feb 2024 00:24:25 +0000 -Subject: [PATCH] Fix error introduced in - 51471cafa5a4fa44d6fe490885d9910bd72a5907 - -Signed-off-by: renmingshuai ---- - src/dnssec.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/src/dnssec.c -+++ b/src/dnssec.c -@@ -1547,7 +1547,7 @@ static int prove_non_existence_nsec3(str - nsecs[i] = NULL; /* Speculative, will be restored if OK. */ - - if (!(p = skip_name(nsec3p, header, plen, 15))) -- return 0; /* bad packet */ -+ return DNSSEC_FAIL_BADPACKET; /* bad packet */ - - p += 10; /* type, class, TTL, rdlen */ - -@@ -1640,7 +1640,7 @@ static int prove_non_existence_nsec3(str - if (!wildname) - { - if (!(wildcard = strchr(next_closest, '.')) || wildcard == next_closest) -- return 0; -+ return DNSSEC_FAIL_NONSEC; - - wildcard--; - *wildcard = '*'; diff --git a/package/network/services/dnsmasq/patches/0003-Handle-DS-queries-to-auth-zones.patch b/package/network/services/dnsmasq/patches/0003-Handle-DS-queries-to-auth-zones.patch deleted file mode 100644 index bd7270c904..0000000000 --- a/package/network/services/dnsmasq/patches/0003-Handle-DS-queries-to-auth-zones.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 8ce27433f8b2e17c557cb55e4f16941d309deeac Mon Sep 17 00:00:00 2001 -From: Simon Kelley -Date: Fri, 17 Jan 2025 17:49:29 +0000 -Subject: [PATCH] Handle DS queries to auth zones. -Origin: upstream, v2.91test8 - -When dnsmasq is configured to act as an authoritative server and has -an authoritative zone configured, and recieves a query for -that zone _as_forwarder_ it answers the query directly rather -than forwarding it. This doesn't affect the answer, but it -saves dnsmasq forwarding the query to the recusor upstream, -whch then bounces it back to dnsmasq in auth mode. The -exception should be when the query is for the root of zone, for a DS -RR. The answer to that has to come from the parent, via the -recursor, and will typically be a proof-of-nonexistence since -dnsmasq doesn't support signed zones. This patch suppresses -local answers and forces forwarding to the upstream recursor -for such queries. It stops breakage when a DNSSEC validating -client makes queries to dnsmasq acting as forwarder for a zone -for which it is authoritative. - -[ukleinek: drop changes to CHANGELOG to prevent conflicts] ---- - src/forward.c | 52 +++++++++++++++++++++++++++++++++++++-------------- - 1 file changed, 38 insertions(+), 14 deletions(-) - ---- a/src/forward.c -+++ b/src/forward.c -@@ -1744,15 +1744,27 @@ void receive_query(struct listener *list - #endif - - #ifdef HAVE_AUTH -- /* find queries for zones we're authoritative for, and answer them directly */ -+ /* Find queries for zones we're authoritative for, and answer them directly. -+ The exception to this is DS queries for the zone route. They -+ have to come from the parent zone. Since dnsmasq's auth server -+ can't do DNSSEC, the zone will be unsigned, and anything using -+ dnsmasq as a forwarder and doing validation will be expecting to -+ see the proof of non-existence from the parent. */ - if (!auth_dns && !option_bool(OPT_LOCALISE)) - for (zone = daemon->auth_zones; zone; zone = zone->next) -- if (in_zone(zone, daemon->namebuff, NULL)) -- { -- auth_dns = 1; -- local_auth = 1; -- break; -- } -+ { -+ char *cut; -+ -+ if (in_zone(zone, daemon->namebuff, &cut)) -+ { -+ if (type != T_DS || cut) -+ { -+ auth_dns = 1; -+ local_auth = 1; -+ } -+ break; -+ } -+ } - #endif - - #ifdef HAVE_LOOP -@@ -2268,15 +2280,27 @@ unsigned char *tcp_request(int confd, ti - &peer_addr, auth_dns ? "auth" : "query", qtype); - - #ifdef HAVE_AUTH -- /* find queries for zones we're authoritative for, and answer them directly */ -+ /* Find queries for zones we're authoritative for, and answer them directly. -+ The exception to this is DS queries for the zone route. They -+ have to come from the parent zone. Since dnsmasq's auth server -+ can't do DNSSEC, the zone will be unsigned, and anything using -+ dnsmasq as a forwarder and doing validation will be expecting to -+ see the proof of non-existence from the parent. */ - if (!auth_dns && !option_bool(OPT_LOCALISE)) - for (zone = daemon->auth_zones; zone; zone = zone->next) -- if (in_zone(zone, daemon->namebuff, NULL)) -- { -- auth_dns = 1; -- local_auth = 1; -- break; -- } -+ { -+ char *cut; -+ -+ if (in_zone(zone, daemon->namebuff, &cut)) -+ { -+ if (qtype != T_DS || cut) -+ { -+ auth_dns = 1; -+ local_auth = 1; -+ } -+ break; -+ } -+ } - #endif - } - } diff --git a/package/network/services/dnsmasq/patches/200-ubus_dns.patch b/package/network/services/dnsmasq/patches/200-ubus_dns.patch index 72acbaeba9..a1a668818e 100644 --- a/package/network/services/dnsmasq/patches/200-ubus_dns.patch +++ b/package/network/services/dnsmasq/patches/200-ubus_dns.patch @@ -1,16 +1,16 @@ --- a/src/dnsmasq.c +++ b/src/dnsmasq.c -@@ -2021,6 +2021,10 @@ static void check_dns_listeners(time_t n - daemon->pipe_to_parent = pipefd[1]; - } +@@ -2097,6 +2097,10 @@ + daemon->pipe_to_parent = pipefd[1]; + } +#ifdef HAVE_UBUS -+ drop_ubus_listeners(); ++ drop_ubus_listeners(); +#endif + - /* start with no upstream connections. */ - for (s = daemon->servers; s; s = s->next) - s->tcpfd = -1; + /* The connected socket inherits non-blocking + attribute from the listening socket. + Reset that here. */ --- a/src/dnsmasq.h +++ b/src/dnsmasq.h @@ -1670,14 +1670,26 @@ void emit_dbus_signal(int action, struct diff --git a/package/network/services/lldpd/files/lldpd.init b/package/network/services/lldpd/files/lldpd.init index e60cc82fd3..e59b5d9800 100644 --- a/package/network/services/lldpd/files/lldpd.init +++ b/package/network/services/lldpd/files/lldpd.init @@ -1,6 +1,6 @@ #!/bin/sh /etc/rc.common # Copyright (C) 2008-2015 OpenWrt.org -# shellcheck disable=1091,2034,3037,3043,3045 +# shellcheck disable=1091,2034,3037,3043,3045,3057 START=90 STOP=01 @@ -24,15 +24,63 @@ LLDPD_RESTART_HASH=${LLDPD_RUN}/lldpd.restart_hash . "$IPKG_INSTROOT/lib/functions/network.sh" +# Load release info once for all 'find_*' functions +[ -s /etc/os-release ] && . /etc/os-release + +# Helper function to truncate output to 31 characters +truncate_output() { + # Some devices have trouble decoding inventory TLV strings > 31 chars + # lldpd truncates inventory TLV to a total TLV length of 36 (of which string = 32) + echo "${1:0:31}" +} + find_release_info() { - [ -s /etc/os-release ] && . /etc/os-release [ -z "$PRETTY_NAME" ] && [ -s /etc/openwrt_version ] && \ PRETTY_NAME="$(cat /etc/openwrt_version)" echo "${PRETTY_NAME:-Unknown OpenWrt release} @ $(cat /proc/sys/kernel/hostname)" } +find_hardware_revision() +{ + echo "${OPENWRT_DEVICE_REVISION:-Unknown hardware revision}" +} + +find_firmware_info() +{ + echo "${PRETTY_NAME:-Unknown firmware release}" +} + +find_software_revision() +{ + echo "${BUILD_ID:-Unknown software revision}" +} + +# Helper function to extract JSON values using jsonfilter +extract_json_field() { + local _path="$1" + jsonfilter -q -i /etc/board.json -e "$_path" 2>/dev/null +} + +find_manufacturer_info() +{ + local _id + # extract the model->id field, e.g.: "id": "glinet,gl-mt6000", + _id=$(extract_json_field '@.model.id') + # stash text up to first comma + _id="${_id%%,*}" + echo "${_id:-Unknown manufacturer}" +} + +find_model_info() +{ + local _name + # extract the model->name field, e.g.: "name": "GL.iNet GL-MT6000" + _name=$(extract_json_field '@.model.name') + echo "${_name:-Unknown model name}" +} + get_config_restart_hash() { local var="$1" local _string _hash v @@ -120,6 +168,48 @@ write_lldpd_conf() config_load 'lldpd' config_get lldp_description 'config' 'lldp_description' "$(find_release_info)" + # Check the 'do not send inventory' flag + local lldpmed_no_inventory + config_get_bool lldpmed_no_inventory 'config' 'lldpmed_no_inventory' 0 + + if [ "$lldpmed_no_inventory" = 0 ]; then + # lldpmed_no_inventory=1 ('-i' in start_service()) prevents these from being sent + # TIA TR-41 TLV 127 subtype 0x05 + local lldp_med_inv_hardware_revision + config_get lldp_med_inv_hardware_revision 'config' 'lldp_med_inv_hardware_revision' "$(find_hardware_revision)" + lldp_med_inv_hardware_revision=$(truncate_output "$lldp_med_inv_hardware_revision") + + # TIA TR-41 TLV 127 subtype 0x06 + local lldp_med_inv_firmware_revision + config_get lldp_med_inv_firmware_revision 'config' 'lldp_med_inv_firmware_revision' "$(find_firmware_info)" + lldp_med_inv_firmware_revision=$(truncate_output "$lldp_med_inv_firmware_revision") + + # TIA TR-41 TLV 127 subtype 0x07 + local lldp_med_inv_software_revision + config_get lldp_med_inv_software_revision 'config' 'lldp_med_inv_software_revision' "$(find_software_revision)" + lldp_med_inv_software_revision=$(truncate_output "$lldp_med_inv_software_revision") + + # TIA TR-41 TLV 127 subtype 0x08 + local lldp_med_inv_serial_number + config_get lldp_med_inv_serial_number 'config' 'lldp_med_inv_serial_number' + lldp_med_inv_serial_number=$(truncate_output "$lldp_med_inv_serial_number") + + # TIA TR-41 TLV 127 subtype 0x09 + local lldp_med_inv_manufacturer_name + config_get lldp_med_inv_manufacturer_name 'config' 'lldp_med_inv_manufacturer_name' "$(find_manufacturer_info)" + lldp_med_inv_manufacturer_name=$(truncate_output "$lldp_med_inv_manufacturer_name") + + # TIA TR-41 TLV 127 subtype 0x0a + local lldp_med_inv_model_name + config_get lldp_med_inv_model_name 'config' 'lldp_med_inv_model_name' "$(find_model_info)" + lldp_med_inv_model_name=$(truncate_output "$lldp_med_inv_model_name") + + # TIA TR-41 TLV 127 subtype 0x0b + local lldp_med_inv_asset_id + config_get lldp_med_inv_asset_id 'config' 'lldp_med_inv_asset_id' + lldp_med_inv_asset_id=$(truncate_output "$lldp_med_inv_asset_id") + fi + local lldp_hostname config_get lldp_hostname 'config' 'lldp_hostname' "$(cat /proc/sys/kernel/hostname)" @@ -182,6 +272,17 @@ write_lldpd_conf() [ -n "$lldp_mgmt_ip" ] && echo "configure system ip management pattern" "\"$lldp_mgmt_ip\"" >> "$LLDPD_CONF" [ -n "$lldp_syscapabilities" ] && echo "configure system capabilities enabled $lldp_syscapabilities" >> "$LLDPD_CONF" + if [ "$lldpmed_no_inventory" = 0 ]; then + # Hardware inventory info + [ -n "$lldp_med_inv_hardware_revision" ] && echo "configure inventory hardware-revision \"$lldp_med_inv_hardware_revision\"" >> "$LLDPD_CONF" + [ -n "$lldp_med_inv_firmware_revision" ] && echo "configure inventory firmware-revision \"$lldp_med_inv_firmware_revision\"" >> "$LLDPD_CONF" + [ -n "$lldp_med_inv_software_revision" ] && echo "configure inventory software-revision \"$lldp_med_inv_software_revision\"" >> "$LLDPD_CONF" + [ -n "$lldp_med_inv_serial_number" ] && echo "configure inventory serial-number \"$lldp_med_inv_serial_number\"" >> "$LLDPD_CONF" + [ -n "$lldp_med_inv_manufacturer_name" ] && echo "configure inventory manufacturer \"$lldp_med_inv_manufacturer_name\"" >> "$LLDPD_CONF" + [ -n "$lldp_med_inv_model_name" ] && echo "configure inventory model \"$lldp_med_inv_model_name\"" >> "$LLDPD_CONF" + [ -n "$lldp_med_inv_asset_id" ] && echo "configure inventory asset \"$lldp_med_inv_asset_id\"" >> "$LLDPD_CONF" + fi + if [ "$CONFIG_LLDPD_WITH_LLDPMED" = "y" ] && [ "$lldpmed_fast_start" -gt 0 ]; then if [ "$lldpmed_fast_start_tx_interval" -gt 0 ]; then echo "configure med fast-start tx-interval $lldpmed_fast_start_tx_interval" >> "$LLDPD_CONF" @@ -401,6 +502,14 @@ reload_service() { unconfigure system hostname unconfigure system ip management pattern unconfigure system platform + # Hardware inventory info + unconfigure inventory hardware-revision + unconfigure inventory firmware-revision + unconfigure inventory software-revision + unconfigure inventory serial-number + unconfigure inventory manufacturer + unconfigure inventory model + unconfigure inventory asset EOF if [ "$CONFIG_LLDPD_WITH_LLDPMED" = "y" ]; then $LLDPCLI -u "$LLDPSOCKET" >/dev/null 2>&1 <<-EOF diff --git a/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc b/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc index c12f4abce8..edc034343b 100644 --- a/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc +++ b/package/network/services/unetmsg/files/usr/share/ucode/unetmsg/unetmsgd-remote.uc @@ -99,7 +99,7 @@ function network_socket_handle_request(sock_data, req) if (list[name]) return 0; - let allowed; + let allowed = net.peers[host].allowed == null; for (let cur in net.peers[host].allowed) { if (!wildcard(name, cur)) continue; diff --git a/package/system/ca-certificates/Makefile b/package/system/ca-certificates/Makefile index 254d7b5178..5b282c339e 100644 --- a/package/system/ca-certificates/Makefile +++ b/package/system/ca-certificates/Makefile @@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ca-certificates -PKG_VERSION:=20240203 +PKG_VERSION:=20241223 PKG_RELEASE:=1 PKG_MAINTAINER:= @@ -16,7 +16,7 @@ PKG_LICENSE_FILES:=debian/copyright PKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@DEBIAN/pool/main/c/ca-certificates -PKG_HASH:=3286d3fc42c4d11b7086711a85f865b44065ce05cf1fb5376b2abed07622a9c6 +PKG_HASH:=dd8286d0a9dd35c756fea5f1df3fed1510fb891f376903891b003cd9b1ad7e03 PKG_INSTALL:=1 include $(INCLUDE_DIR)/package.mk diff --git a/package/utils/cli/files/usr/share/ucode/cli/object-editor.uc b/package/utils/cli/files/usr/share/ucode/cli/object-editor.uc index 0a44754064..1f36ee9d07 100644 --- a/package/utils/cli/files/usr/share/ucode/cli/object-editor.uc +++ b/package/utils/cli/files/usr/share/ucode/cli/object-editor.uc @@ -135,8 +135,14 @@ export function remove_call(ctx, argv, named) if (!data) continue; - for (let idx in val) + for (let idx in val) { + if (idx != "" + +idx) { + let cur_idx = index(data, idx); + if (cur_idx >= 0) + idx = cur_idx + 1; + } data[+idx - 1] = null; + } cur_obj[name] = filter(data, (v) => v != null); if (cur.attribute_allow_empty && !length(cur_obj[name])) diff --git a/package/utils/usbgadget/Makefile b/package/utils/usbgadget/Makefile index d3a68ea9df..0a88a49921 100644 --- a/package/utils/usbgadget/Makefile +++ b/package/utils/usbgadget/Makefile @@ -12,10 +12,14 @@ include $(INCLUDE_DIR)/package.mk define Package/$(PKG_NAME) SECTION:=utils CATEGORY:=Utilities - DEPENDS:=@USB_GADGET_SUPPORT +kmod-usb-gadget +kmod-usb-lib-composite + DEPENDS:=@USB_GADGET_SUPPORT +kmod-usb-gadget +kmod-fs-configfs +kmod-usb-lib-composite TITLE:=init script to create USB gadgets endef +define Package/$(PKG_NAME)/conffiles +/etc/config/usbgadget +endef + define Build/Compile endef @@ -35,7 +39,7 @@ define GadgetPreset SECTION:=utils CATEGORY:=Utilities TITLE+= $(2) gadget preset - DEPENDS+= $(3) + DEPENDS+= +usbgadget $(3) endef define Package/$(PKG_NAME)-$(1)/description @@ -51,4 +55,4 @@ define GadgetPreset endef $(eval $(call GadgetPreset,ncm,CDC-NCM,+kmod-usb-gadget-ncm)) -$(eval $(call GadgetPreset,acm,CDC-ACM,+kmod-usb-gadget-serial)) \ No newline at end of file +$(eval $(call GadgetPreset,acm,CDC-ACM,+kmod-usb-gadget-serial)) diff --git a/target/linux/ath79/image/common-nec.mk b/target/linux/ath79/image/common-nec.mk index 7981a72d8e..23671e215d 100644 --- a/target/linux/ath79/image/common-nec.mk +++ b/target/linux/ath79/image/common-nec.mk @@ -8,6 +8,7 @@ endef define Device/nec-netbsd-aterm DEVICE_VENDOR := NEC LOADER_TYPE := bin + LZMA_TEXT_START := 0x82800000 KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | uImage none KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-kernel | uImage none ARTIFACTS := uboot.bin diff --git a/target/linux/bcm27xx/patches-6.6/950-0215-PCI-brcmstb-Add-DT-property-to-control-L1SS.patch b/target/linux/bcm27xx/patches-6.6/950-0215-PCI-brcmstb-Add-DT-property-to-control-L1SS.patch index f29ecab071..c6a5810fad 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0215-PCI-brcmstb-Add-DT-property-to-control-L1SS.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0215-PCI-brcmstb-Add-DT-property-to-control-L1SS.patch @@ -65,7 +65,7 @@ Signed-off-by: Phil Elwell writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); return 0; -@@ -1536,6 +1551,7 @@ static int brcm_pcie_probe(struct platfo +@@ -1537,6 +1552,7 @@ static int brcm_pcie_probe(struct platfo pcie->gen = (ret < 0) ? 0 : ret; pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); diff --git a/target/linux/bcm27xx/patches-6.6/950-0521-PCI-brcmstb-Add-BCM2712-support.patch b/target/linux/bcm27xx/patches-6.6/950-0521-PCI-brcmstb-Add-BCM2712-support.patch index c4c79ae428..38f2e86317 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0521-PCI-brcmstb-Add-BCM2712-support.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0521-PCI-brcmstb-Add-BCM2712-support.patch @@ -831,7 +831,7 @@ Signed-off-by: Jonathan Bell return 0; } -@@ -1207,6 +1534,7 @@ static void brcm_pcie_enter_l23(struct b +@@ -1208,6 +1535,7 @@ static void brcm_pcie_enter_l23(struct b static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) { @@ -839,7 +839,7 @@ Signed-off-by: Jonathan Bell static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = { PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT, PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT, -@@ -1239,6 +1567,9 @@ static int brcm_phy_cntl(struct brcm_pci +@@ -1240,6 +1568,9 @@ static int brcm_phy_cntl(struct brcm_pci dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); return ret; @@ -849,7 +849,7 @@ Signed-off-by: Jonathan Bell } static inline int brcm_phy_start(struct brcm_pcie *pcie) -@@ -1271,6 +1602,12 @@ static void brcm_pcie_turn_off(struct br +@@ -1272,6 +1603,12 @@ static void brcm_pcie_turn_off(struct br u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); @@ -862,7 +862,7 @@ Signed-off-by: Jonathan Bell /* Shutdown PCIe bridge */ pcie->bridge_sw_init_set(pcie, 1); } -@@ -1301,9 +1638,9 @@ static int brcm_pcie_suspend_noirq(struc +@@ -1302,9 +1639,9 @@ static int brcm_pcie_suspend_noirq(struc if (brcm_phy_stop(pcie)) dev_err(dev, "Could not stop phy for suspend\n"); @@ -874,7 +874,7 @@ Signed-off-by: Jonathan Bell return ret; } -@@ -1398,7 +1735,7 @@ err_regulator: +@@ -1399,7 +1736,7 @@ err_regulator: if (pcie->sr) regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); err_reset: @@ -883,7 +883,7 @@ Signed-off-by: Jonathan Bell err_disable_clk: clk_disable_unprepare(pcie->clk); return ret; -@@ -1410,8 +1747,8 @@ static void __brcm_pcie_remove(struct br +@@ -1411,8 +1748,8 @@ static void __brcm_pcie_remove(struct br brcm_pcie_turn_off(pcie); if (brcm_phy_stop(pcie)) dev_err(pcie->dev, "Could not stop phy\n"); @@ -894,7 +894,7 @@ Signed-off-by: Jonathan Bell clk_disable_unprepare(pcie->clk); } -@@ -1429,12 +1766,16 @@ static const int pcie_offsets[] = { +@@ -1430,12 +1767,16 @@ static const int pcie_offsets[] = { [RGR1_SW_INIT_1] = 0x9210, [EXT_CFG_INDEX] = 0x9000, [EXT_CFG_DATA] = 0x9004, @@ -911,7 +911,7 @@ Signed-off-by: Jonathan Bell }; static const struct pcie_cfg_data generic_cfg = { -@@ -1442,6 +1783,7 @@ static const struct pcie_cfg_data generi +@@ -1443,6 +1784,7 @@ static const struct pcie_cfg_data generi .type = GENERIC, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, @@ -919,7 +919,7 @@ Signed-off-by: Jonathan Bell }; static const struct pcie_cfg_data bcm7425_cfg = { -@@ -1449,6 +1791,7 @@ static const struct pcie_cfg_data bcm742 +@@ -1450,6 +1792,7 @@ static const struct pcie_cfg_data bcm742 .type = BCM7425, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, @@ -927,7 +927,7 @@ Signed-off-by: Jonathan Bell }; static const struct pcie_cfg_data bcm7435_cfg = { -@@ -1463,12 +1806,15 @@ static const struct pcie_cfg_data bcm490 +@@ -1464,12 +1807,15 @@ static const struct pcie_cfg_data bcm490 .type = BCM4908, .perst_set = brcm_pcie_perst_set_4908, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, @@ -943,7 +943,7 @@ Signed-off-by: Jonathan Bell }; static const struct pcie_cfg_data bcm7278_cfg = { -@@ -1476,6 +1822,7 @@ static const struct pcie_cfg_data bcm727 +@@ -1477,6 +1823,7 @@ static const struct pcie_cfg_data bcm727 .type = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, @@ -951,7 +951,7 @@ Signed-off-by: Jonathan Bell }; static const struct pcie_cfg_data bcm2711_cfg = { -@@ -1483,10 +1830,27 @@ static const struct pcie_cfg_data bcm271 +@@ -1484,10 +1831,27 @@ static const struct pcie_cfg_data bcm271 .type = BCM2711, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, @@ -979,7 +979,7 @@ Signed-off-by: Jonathan Bell { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, -@@ -1527,7 +1891,7 @@ static int brcm_pcie_probe(struct platfo +@@ -1528,7 +1892,7 @@ static int brcm_pcie_probe(struct platfo data = of_device_get_match_data(&pdev->dev); if (!data) { @@ -988,7 +988,7 @@ Signed-off-by: Jonathan Bell return -EINVAL; } -@@ -1538,6 +1902,7 @@ static int brcm_pcie_probe(struct platfo +@@ -1539,6 +1903,7 @@ static int brcm_pcie_probe(struct platfo pcie->type = data->type; pcie->perst_set = data->perst_set; pcie->bridge_sw_init_set = data->bridge_sw_init_set; @@ -996,7 +996,7 @@ Signed-off-by: Jonathan Bell pcie->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pcie->base)) -@@ -1568,14 +1933,20 @@ static int brcm_pcie_probe(struct platfo +@@ -1569,14 +1934,20 @@ static int brcm_pcie_probe(struct platfo clk_disable_unprepare(pcie->clk); return PTR_ERR(pcie->perst_reset); } @@ -1019,7 +1019,7 @@ Signed-off-by: Jonathan Bell clk_disable_unprepare(pcie->clk); return ret; } -@@ -1598,6 +1969,33 @@ static int brcm_pcie_probe(struct platfo +@@ -1599,6 +1970,33 @@ static int brcm_pcie_probe(struct platfo dev_err(pcie->dev, "probe of internal MSI failed"); goto fail; } @@ -1053,7 +1053,7 @@ Signed-off-by: Jonathan Bell } bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; -@@ -1614,6 +2012,8 @@ static int brcm_pcie_probe(struct platfo +@@ -1615,6 +2013,8 @@ static int brcm_pcie_probe(struct platfo return ret; } diff --git a/target/linux/bcm27xx/patches-6.6/950-0695-PCI-brcmstb-Change-RCB_-MPS-64B-_MODE-bits.patch b/target/linux/bcm27xx/patches-6.6/950-0695-PCI-brcmstb-Change-RCB_-MPS-64B-_MODE-bits.patch index dba20dc854..70d8229b44 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0695-PCI-brcmstb-Change-RCB_-MPS-64B-_MODE-bits.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0695-PCI-brcmstb-Change-RCB_-MPS-64B-_MODE-bits.patch @@ -45,7 +45,7 @@ Signed-off-by: Phil Elwell writel(tmp, base + PCIE_MISC_MISC_CTRL); brcm_pcie_set_tc_qos(pcie); -@@ -1917,6 +1918,7 @@ static int brcm_pcie_probe(struct platfo +@@ -1918,6 +1919,7 @@ static int brcm_pcie_probe(struct platfo pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss"); diff --git a/target/linux/bcm27xx/patches-6.6/950-0697-drivers-pci-brcmstb-optionally-extend-Tperst_clk-tim.patch b/target/linux/bcm27xx/patches-6.6/950-0697-drivers-pci-brcmstb-optionally-extend-Tperst_clk-tim.patch index a0006d6a5a..604cf21b10 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0697-drivers-pci-brcmstb-optionally-extend-Tperst_clk-tim.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0697-drivers-pci-brcmstb-optionally-extend-Tperst_clk-tim.patch @@ -61,7 +61,7 @@ Signed-off-by: Jonathan Bell /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification -@@ -1919,6 +1940,7 @@ static int brcm_pcie_probe(struct platfo +@@ -1920,6 +1941,7 @@ static int brcm_pcie_probe(struct platfo pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss"); pcie->rcb_mps_mode = of_property_read_bool(np, "brcm,enable-mps-rcb"); diff --git a/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch b/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch index 68e2ef6007..fa16c52817 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch @@ -56,7 +56,7 @@ Signed-off-by: Richard Oliver depends on RENESAS_RPCIF --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -115,6 +115,7 @@ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockc +@@ -116,6 +116,7 @@ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockc obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o diff --git a/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch b/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch index 4f1ea9249c..02c4dc4498 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch @@ -18,7 +18,7 @@ Signed-off-by: Phil Elwell --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c -@@ -1932,6 +1932,7 @@ static void nvme_free_host_mem(struct nv +@@ -1948,6 +1948,7 @@ static void nvme_free_host_mem(struct nv dev->nr_host_mem_descs = 0; } @@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, u32 chunk_size) { -@@ -2000,9 +2001,11 @@ out: +@@ -2016,9 +2017,11 @@ out: dev->host_mem_descs = NULL; return -ENOMEM; } @@ -38,7 +38,7 @@ Signed-off-by: Phil Elwell u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); u64 chunk_size; -@@ -2015,6 +2018,7 @@ static int nvme_alloc_host_mem(struct nv +@@ -2031,6 +2034,7 @@ static int nvme_alloc_host_mem(struct nv nvme_free_host_mem(dev); } } diff --git a/target/linux/bcm27xx/patches-6.6/950-1452-Revert-PCI-Warn-if-no-host-bridge-NUMA-node-info.patch b/target/linux/bcm27xx/patches-6.6/950-1452-Revert-PCI-Warn-if-no-host-bridge-NUMA-node-info.patch index 5aa88661c3..470a90cb97 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1452-Revert-PCI-Warn-if-no-host-bridge-NUMA-node-info.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1452-Revert-PCI-Warn-if-no-host-bridge-NUMA-node-info.patch @@ -17,7 +17,7 @@ Signed-off-by: Dom Cobley --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c -@@ -968,9 +968,6 @@ static int pci_register_host_bridge(stru +@@ -967,9 +967,6 @@ static int pci_register_host_bridge(stru else pr_info("PCI host bridge to bus %s\n", name); diff --git a/target/linux/bcm27xx/patches-6.6/950-1558-media-i2c-imx477-Add-further-link-frequency-options.patch b/target/linux/bcm27xx/patches-6.6/950-1558-media-i2c-imx477-Add-further-link-frequency-options.patch new file mode 100644 index 0000000000..8ed80cd201 --- /dev/null +++ b/target/linux/bcm27xx/patches-6.6/950-1558-media-i2c-imx477-Add-further-link-frequency-options.patch @@ -0,0 +1,77 @@ +From 0553897d77e849a86e836ddf1e0c0dbbd8e64f83 Mon Sep 17 00:00:00 2001 +From: Dave Stevenson +Date: Mon, 20 Jan 2025 10:40:09 +0000 +Subject: [PATCH] media: i2c: imx477: Add further link frequency options + +https://github.com/raspberrypi/linux/issues/6004 reports further +issues with GPS interference. + +Untested, but adds further link frequency options. + +Signed-off-by: Dave Stevenson +--- + drivers/media/i2c/imx477.c | 33 +++++++++++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +--- a/drivers/media/i2c/imx477.c ++++ b/drivers/media/i2c/imx477.c +@@ -169,12 +169,18 @@ enum { + IMX477_LINK_FREQ_450MHZ, + IMX477_LINK_FREQ_453MHZ, + IMX477_LINK_FREQ_456MHZ, ++ IMX477_LINK_FREQ_459MHZ, ++ IMX477_LINK_FREQ_462MHZ, ++ IMX477_LINK_FREQ_498MHZ, + }; + + static const s64 link_freqs[] = { + [IMX477_LINK_FREQ_450MHZ] = 450000000, + [IMX477_LINK_FREQ_453MHZ] = 453000000, + [IMX477_LINK_FREQ_456MHZ] = 456000000, ++ [IMX477_LINK_FREQ_459MHZ] = 459000000, ++ [IMX477_LINK_FREQ_462MHZ] = 462000000, ++ [IMX477_LINK_FREQ_498MHZ] = 498000000, + }; + + /* 450MHz is the nominal "default" link frequency */ +@@ -193,6 +199,21 @@ static const struct imx477_reg link_456M + {0x030F, 0x98}, + }; + ++static const struct imx477_reg link_459Mhz_regs[] = { ++ {0x030E, 0x00}, ++ {0x030F, 0x99}, ++}; ++ ++static const struct imx477_reg link_462Mhz_regs[] = { ++ {0x030E, 0x00}, ++ {0x030F, 0x9a}, ++}; ++ ++static const struct imx477_reg link_498Mhz_regs[] = { ++ {0x030E, 0x00}, ++ {0x030F, 0xa6}, ++}; ++ + static const struct imx477_reg_list link_freq_regs[] = { + [IMX477_LINK_FREQ_450MHZ] = { + .regs = link_450Mhz_regs, +@@ -206,6 +227,18 @@ static const struct imx477_reg_list link + .regs = link_456Mhz_regs, + .num_of_regs = ARRAY_SIZE(link_456Mhz_regs) + }, ++ [IMX477_LINK_FREQ_459MHZ] = { ++ .regs = link_459Mhz_regs, ++ .num_of_regs = ARRAY_SIZE(link_459Mhz_regs) ++ }, ++ [IMX477_LINK_FREQ_462MHZ] = { ++ .regs = link_462Mhz_regs, ++ .num_of_regs = ARRAY_SIZE(link_462Mhz_regs) ++ }, ++ [IMX477_LINK_FREQ_498MHZ] = { ++ .regs = link_498Mhz_regs, ++ .num_of_regs = ARRAY_SIZE(link_498Mhz_regs) ++ }, + }; + + static const struct imx477_reg mode_common_regs[] = { diff --git a/target/linux/bcm27xx/patches-6.6/950-1559-overlays-Fix-some-unusable-fragments.patch b/target/linux/bcm27xx/patches-6.6/950-1559-overlays-Fix-some-unusable-fragments.patch new file mode 100644 index 0000000000..bebe055552 --- /dev/null +++ b/target/linux/bcm27xx/patches-6.6/950-1559-overlays-Fix-some-unusable-fragments.patch @@ -0,0 +1,82 @@ +From 9da8d6df2051478f0ba16d73c65995955c19cb3a Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 18 Mar 2025 13:09:11 +0000 +Subject: [PATCH] overlays: Fix some unusable fragments + +A forthcoming overlaycheck update looks for dormant fragments with no +parameters to enable them. The test discovered some real errors, which +this patch fixes, and one case where some fragments aren't yet being +used, which this comments out until they are. + +Signed-off-by: Phil Elwell +--- + arch/arm/boot/dts/overlays/rpi-poe-overlay.dts | 2 +- + arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts | 2 +- + arch/arm/boot/dts/overlays/sx150x-overlay.dts | 2 +- + arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts | 4 ++++ + 4 files changed, 7 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts ++++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts +@@ -145,7 +145,7 @@ + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; +- i2c = <0>, "+5+6", ++ i2c = <0>, "+7+8", + <&fwpwm>,"status=disabled", + <&i2c_bus>,"status=okay", + <&poe_mfd>,"status=okay", +--- a/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts ++++ b/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts +@@ -28,7 +28,7 @@ + }; + + __overrides__ { +- i2c = <0>, "+5+6", ++ i2c = <0>, "+7+8", + <&fwpwm>,"status=disabled", + <&rpi_poe_power_supply>,"status=disabled", + <&i2c_bus>,"status=okay", +--- a/arch/arm/boot/dts/overlays/sx150x-overlay.dts ++++ b/arch/arm/boot/dts/overlays/sx150x-overlay.dts +@@ -1681,7 +1681,7 @@ + sx1507-1-3E-int-gpio = <0>,"+67+99", <&sx150x_1_3E_pins>,"brcm,pins:0", <&sx1507_1_3E>,"interrupts:0"; + sx1507-0-3F-int-gpio = <0>,"+68+100", <&sx150x_0_3F_pins>,"brcm,pins:0", <&sx1507_0_3F>,"interrupts:0"; + sx1507-1-3F-int-gpio = <0>,"+69+101", <&sx150x_1_3F_pins>,"brcm,pins:0", <&sx1507_1_3F>,"interrupts:0"; +- sx1507-0-70-int-gpio = <0>,"+60+102", <&sx150x_0_70_pins>,"brcm,pins:0", <&sx1507_0_70>,"interrupts:0"; ++ sx1507-0-70-int-gpio = <0>,"+70+102", <&sx150x_0_70_pins>,"brcm,pins:0", <&sx1507_0_70>,"interrupts:0"; + sx1507-1-70-int-gpio = <0>,"+71+103", <&sx150x_1_70_pins>,"brcm,pins:0", <&sx1507_1_70>,"interrupts:0"; + sx1507-0-71-int-gpio = <0>,"+72+104", <&sx150x_0_71_pins>,"brcm,pins:0", <&sx1507_0_71>,"interrupts:0"; + sx1507-1-71-int-gpio = <0>,"+73+105", <&sx150x_1_71_pins>,"brcm,pins:0", <&sx1507_1_71>,"interrupts:0"; +--- a/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts +@@ -42,24 +42,28 @@ + pinctrl-0 = <&dpi_18bit_gpio0>; + }; + }; ++#if 0 + fragment@92 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_gpio0>; + }; + }; ++#endif + fragment@93 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_16bit_cpadhi_gpio0>; + }; + }; ++#if 0 + fragment@94 { + target = <&dpi>; + __dormant__ { + pinctrl-0 = <&dpi_16bit_gpio0>; + }; + }; ++#endif + + __overrides__ { + at056tn53v1 = <0>, "+0+90"; diff --git a/target/linux/bcm27xx/patches-6.6/950-1560-dts-rp1-Don-t-use-DMA-with-UARTs.patch b/target/linux/bcm27xx/patches-6.6/950-1560-dts-rp1-Don-t-use-DMA-with-UARTs.patch new file mode 100644 index 0000000000..df19f4cac6 --- /dev/null +++ b/target/linux/bcm27xx/patches-6.6/950-1560-dts-rp1-Don-t-use-DMA-with-UARTs.patch @@ -0,0 +1,33 @@ +From bba53a117a4a5c29da892962332ff1605990e17a Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 26 Mar 2025 11:28:28 +0000 +Subject: [PATCH] dts: rp1: Don't use DMA with UARTs + +DMA has been enabled on RP1's UART0, but with mixed success. Transmits +seem to work, but the DMA interface is not well suited to receiving +arbitrary amounts of data. In particular, the PL011 driver is slow to +pass on the received data, batching it into large blocks. + +On balance, it's better to just disable the DMA support. As with the +other UARTs, the required runes are left in the DTS as comments. + +Signed-off-by: Phil Elwell +--- + arch/arm64/boot/dts/broadcom/rp1.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/broadcom/rp1.dtsi ++++ b/arch/arm64/boot/dts/broadcom/rp1.dtsi +@@ -65,9 +65,9 @@ + interrupts = ; + clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; + clock-names = "uartclk", "apb_pclk"; +- dmas = <&rp1_dma RP1_DMA_UART0_TX>, +- <&rp1_dma RP1_DMA_UART0_RX>; +- dma-names = "tx", "rx"; ++ // dmas = <&rp1_dma RP1_DMA_UART0_TX>, ++ // <&rp1_dma RP1_DMA_UART0_RX>; ++ // dma-names = "tx", "rx"; + pinctrl-names = "default"; + arm,primecell-periphid = <0x00341011>; + uart-has-rtscts; diff --git a/target/linux/bcm4908/image/Makefile b/target/linux/bcm4908/image/Makefile index 658ec810d1..678881fda8 100644 --- a/target/linux/bcm4908/image/Makefile +++ b/target/linux/bcm4908/image/Makefile @@ -33,7 +33,7 @@ define Build/bcm4908img cp -r $(DEVICE_NAME)/* $@-bootfs/ touch $@-bootfs/1-openwrt cp $(DTS_DIR)/$(firstword $(DEVICE_DTS)).dtb $@-bootfs/94908.dtb - cp $(KDIR)/bcm63xx-cfe/$(subst _,$(comma),$(DEVICE_NAME))/cferam.000 $@-bootfs/ + cp $(STAGING_DIR_IMAGE)/bcm63xx-cfe/$(subst _,$(comma),$(DEVICE_NAME))/cferam.000 $@-bootfs/ cp $(IMAGE_KERNEL) $@-bootfs/vmlinux.lz $(STAGING_DIR_HOST)/bin/mkfs.jffs2 --pad=0x800000 --little-endian --squash-uids \ diff --git a/target/linux/bmips/image/Makefile b/target/linux/bmips/image/Makefile index 00580a2f7b..9fc58e9f99 100644 --- a/target/linux/bmips/image/Makefile +++ b/target/linux/bmips/image/Makefile @@ -136,7 +136,7 @@ define Build/cfe-jffs2-cferam # will have version 0 and let cferam be the second (version 1). touch $@-cferam/1-openwrt # Add cferam as the last file in the JFFS2 partition - cp $(KDIR)/bcm63xx-cfe/$(CFE_RAM_FILE) $@-cferam/$(CFE_RAM_JFFS2_NAME) + cp $(STAGING_DIR_IMAGE)/bcm63xx-cfe/$(CFE_RAM_FILE) $@-cferam/$(CFE_RAM_JFFS2_NAME) # The JFFS2 partition creation should result in the following # layout: diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile index b2869ff72e..ddfe67be2b 100644 --- a/target/linux/gemini/Makefile +++ b/target/linux/gemini/Makefile @@ -7,7 +7,7 @@ include $(TOPDIR)/rules.mk ARCH:=arm BOARD:=gemini BOARDNAME:=Cortina Systems CS351x -FEATURES:=squashfs pci rtc usb dt gpio display ext4 rootfs-part boot-part +FEATURES:=squashfs pci rtc usb usbgadget dt gpio display ext4 rootfs-part boot-part CPU_TYPE:=fa526 SUBTARGETS:=generic diff --git a/target/linux/gemini/base-files/etc/board.d/02_usbgadget b/target/linux/gemini/base-files/etc/board.d/02_usbgadget new file mode 100644 index 0000000000..7337e6638a --- /dev/null +++ b/target/linux/gemini/base-files/etc/board.d/02_usbgadget @@ -0,0 +1,11 @@ +. /lib/functions.sh + +case "$(board_name)" in +dlink,dns-313) + uci set usbgadget.@preset[0].name="acm" + uci set usbgadget.@preset[0].UDC="69000000.usb" + uci commit usbgadget + ;; +esac + +exit 0 diff --git a/target/linux/gemini/base-files/etc/inittab b/target/linux/gemini/base-files/etc/inittab new file mode 100644 index 0000000000..253036402d --- /dev/null +++ b/target/linux/gemini/base-files/etc/inittab @@ -0,0 +1,4 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +::askconsole:/usr/libexec/login.sh +ttyGS0::askfirst:/usr/libexec/login.sh diff --git a/target/linux/gemini/image/Makefile b/target/linux/gemini/image/Makefile index 389c8f8c44..c5d09e7120 100644 --- a/target/linux/gemini/image/Makefile +++ b/target/linux/gemini/image/Makefile @@ -170,7 +170,7 @@ define Device/dlink_dns-313 DEVICE_VENDOR := D-Link DEVICE_MODEL := DNS-313 1-Bay Network Storage Enclosure DEVICE_DTS := gemini-dlink-dns-313 - DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) + DEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) usbgadget-acm BLOCKSIZE := 1k FILESYSTEMS := ext4 IMAGES := factory.bin.gz diff --git a/target/linux/qualcommbe/patches-6.6/100-06-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch b/target/linux/generic/backport-6.6/416-v6.15-01-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch similarity index 88% rename from target/linux/qualcommbe/patches-6.6/100-06-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch rename to target/linux/generic/backport-6.6/416-v6.15-01-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch index 62f29cba3c..1a7d4867e9 100644 --- a/target/linux/qualcommbe/patches-6.6/100-06-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch +++ b/target/linux/generic/backport-6.6/416-v6.15-01-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch @@ -1,18 +1,7 @@ +From 7304d1909080ef0c9da703500a97f46c98393fcd Mon Sep 17 00:00:00 2001 From: Md Sadre Alam -To: , , , - , , - , , - , , - , - , , - , , - -Cc: , , - -Subject: [PATCH v14 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface -Date: Wed, 20 Nov 2024 14:45:04 +0530 [thread overview] -Message-ID: <20241120091507.1404368-7-quic_mdalam@quicinc.com> (raw) -In-Reply-To: <20241120091507.1404368-1-quic_mdalam@quicinc.com> +Date: Mon, 24 Feb 2025 16:44:14 +0530 +Subject: [PATCH] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. @@ -22,199 +11,23 @@ Signed-off-by: Sricharan Ramabadhran Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Signed-off-by: Md Sadre Alam +Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com +Signed-off-by: Mark Brown --- - -Change in [v14] - -* No Change - -Change in [v13] - -* Changed return type of qcom_spi_cmd_mapping() from u32 to - int to fix the kernel test bot warning -* Changed type of variable cmd in qcom_spi_write_page() from u32 - to int -* Removed unused variable s_op from qcom_spi_write_page() -* Updated return value variable type from u32 to int in - qcom_spi_send_cmdaddr() - -Change in [v12] - -* Added obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o in Makefile - to build qpic_common.c based on CONFIG_SPI_QPIC_SNAND - -Change in [v11] - -* Fixed build error reported by kernel test bot -* Changed "depends on MTD" to "select MTD" in - drivers/spi/Kconfig file - -Change in [v10] - -* Fixed compilation warnings reported by kernel test robot. -* Added depends on CONFIG_MTD -* removed extra bracket from statement if (i == (num_cw - 1)) in - qcom_spi_program_raw() api. - -Change in [v9] - -* Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand - structure -* In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix - compilation warning -* In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix - compilation warning -* In qcom_spi_init() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables - reqs, user, step_size, strength and added cpu_to_le32() macro as well - to fix compilation warning -* In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation - warning - -Change in [v8] - -* Included "bitfield.h" file to /spi-qpic-snand.c - to fix compilation warning reported by kernel test robot -* Removed unused variable "steps" in - qcom_spi_ecc_init_ctx_pipelined() to fix compilation warning - -Change in [v7] - -* Added read_oob() and write_oob() api - -* Handled offset value for oob layout - -* Made CONFIG_SPI_QPIC_SNAND as bool - -* Added macro ecceng_to_qspi() - -* Added FIELD_PREP() Macro in spi init - -* Added else condition in - qcom_spi_ecc_finish_io_req_pipelined() - for corrected ecc - -* Handled multiple error condition for api - qcom_spi_cmd_mapping() - -* Fix typo for printing debug message - -Change in [v6] - -* Added separate qpic_spi_nand{...} struct - -* moved qpic_ecc and qcom_ecc_stats struct to - spi-qpic-snand.c file, since its spi nand - specific - -* Added FIELD_PREP() and GENMASK() macro - -* Removed rawnand.h and partition.h from - spi-qpic-snand.c - -* Removed oob_buff assignment form - qcom_spi_write_page_cache - -* Added qcom_nand_unalloc() in remove() path - -* Fixes all all comments - -Change in [v5] - -* Added raw_read() and raw_write() api - -* Updated commit message - -* Removed register indirection - -* Added qcom_spi_ prefix to all the api - -* Removed snand_set_reg() api. - -* Fixed nandbiterr issue - -* Removed hardcoded num_cw and made it variable - -* Removed hardcoded value for mtd pagesize - -* Added -ENOSUPPORT in cmd mapping for unsupported - commands - -* Replace if..else with switch..case statement - -Change in [v4] - -* No change - -Change in [v3] - -* Set SPI_QPIC_SNAND to n and added COMPILE_TEST in Kconfig - -* Made driver name sorted in Make file - -* Made comment like c++ - -* Changed macro to functions, snandc_set_read_loc_last() - and snandc_set_read_loc_first() - -* Added error handling in snandc_set_reg() - -* Changed into normal conditional statement for - return snandc->ecc_stats.failed ? -EBADMSG : - snandc->ecc_stats.bitflips; - -* Remove cast of wbuf in qpic_snand_program_execute() - function - -* Made num_cw variable instead hardcoded value - -* changed if..else condition of function qpic_snand_io_op() - to switch..case statement - -* Added __devm_spi_alloc_controller() api instead of - devm_spi_alloc_master() - -* Disabling clock in remove path - -Change in [v2] - -* Added initial support for SPI-NAND driver - -Change in [v1] - -* Added RFC patch for design review - drivers/mtd/nand/Makefile | 4 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + - drivers/spi/spi-qpic-snand.c | 1633 ++++++++++++++++++++++++++ + drivers/spi/spi-qpic-snand.c | 1631 ++++++++++++++++++++++++++ include/linux/mtd/nand-qpic-common.h | 7 + - 5 files changed, 1654 insertions(+) + 5 files changed, 1652 insertions(+) create mode 100644 drivers/spi/spi-qpic-snand.c --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile -@@ -4,7 +4,11 @@ nandcore-objs := core.o bbt.o +@@ -3,7 +3,11 @@ + nandcore-objs := core.o bbt.o obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o - obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o +ifeq ($(CONFIG_SPI_QPIC_SNAND),y) +obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o +else @@ -253,7 +66,7 @@ Change in [v1] obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o --- /dev/null +++ b/drivers/spi/spi-qpic-snand.c -@@ -0,0 +1,1633 @@ +@@ -0,0 +1,1631 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + * @@ -314,6 +127,7 @@ Change in [v1] +#define BAD_BLOCK_MARKER_SIZE 0x2 +#define OOB_BUF_SIZE 128 +#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng) ++ +struct qpic_snand_op { + u32 cmd_reg; + u32 addr1_reg; @@ -1456,64 +1270,63 @@ Change in [v1] + return 0; +} + -+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode) ++static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd) +{ -+ int cmd = 0x0; -+ + switch (opcode) { + case SPINAND_RESET: -+ cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); ++ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); + break; + case SPINAND_READID: -+ cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); ++ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); + break; + case SPINAND_GET_FEATURE: -+ cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); ++ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); + break; + case SPINAND_SET_FEATURE: -+ cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | ++ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | + QPIC_SET_FEATURE); + break; + case SPINAND_READ: + if (snandc->qspi->raw_rw) { -+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | ++ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PAGE_READ); + } else { -+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | ++ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); + } + + break; + case SPINAND_ERASE: -+ cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | ++ *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | + SPI_HOLD | SPI_TRANSFER_MODE_x1; + break; + case SPINAND_WRITE_EN: -+ cmd = SPINAND_WRITE_EN; ++ *cmd = SPINAND_WRITE_EN; + break; + case SPINAND_PROGRAM_EXECUTE: -+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | ++ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); + break; + case SPINAND_PROGRAM_LOAD: -+ cmd = SPINAND_PROGRAM_LOAD; ++ *cmd = SPINAND_PROGRAM_LOAD; + break; + default: + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); + return -EOPNOTSUPP; + } + -+ return cmd; ++ return 0; +} + +static int qcom_spi_write_page(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ -+ int cmd; ++ int ret; ++ u32 cmd; + -+ cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); -+ if (cmd < 0) -+ return cmd; ++ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); ++ if (ret < 0) ++ return ret; + + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) + snandc->qspi->data_buf = (u8 *)op->data.buf.out; @@ -1528,12 +1341,10 @@ Change in [v1] + u32 cmd; + int ret, opcode; + -+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); ++ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); + if (ret < 0) + return ret; + -+ cmd = ret; -+ + s_op.cmd_reg = cmd; + s_op.addr1_reg = op->addr.val; + s_op.addr2_reg = 0; diff --git a/target/linux/generic/backport-6.6/416-v6.15-02-spi-spi-qpic-snand-Fix-ECC_CFG_ECC_DISABLE-shift-in-.patch b/target/linux/generic/backport-6.6/416-v6.15-02-spi-spi-qpic-snand-Fix-ECC_CFG_ECC_DISABLE-shift-in-.patch new file mode 100644 index 0000000000..ad43f8dff1 --- /dev/null +++ b/target/linux/generic/backport-6.6/416-v6.15-02-spi-spi-qpic-snand-Fix-ECC_CFG_ECC_DISABLE-shift-in-.patch @@ -0,0 +1,28 @@ +From cf1ba3cb245020459f2ca446b7a7b199839f5d83 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Thu, 6 Mar 2025 12:40:01 +0300 +Subject: [PATCH] spi: spi-qpic-snand: Fix ECC_CFG_ECC_DISABLE shift in + qcom_spi_read_last_cw() + +The ECC_CFG_ECC_DISABLE define is BIT(0). It's supposed to be used +directly instead of used as a shifter. + +Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") +Signed-off-by: Dan Carpenter +Link: https://patch.msgid.link/2f4b0a0b-2c03-41c0-8a4a-3d789a83832d@stanley.mountain +Signed-off-by: Mark Brown +--- + drivers/spi/spi-qpic-snand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-qpic-snand.c ++++ b/drivers/spi/spi-qpic-snand.c +@@ -514,7 +514,7 @@ static int qcom_spi_read_last_cw(struct + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | + 0 << CW_PER_PAGE; + cfg1 = ecc_cfg->cfg1_raw; +- ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; ++ ecc_bch_cfg = ECC_CFG_ECC_DISABLE; + + snandc->regs->cmd = snandc->qspi->cmd; + snandc->regs->cfg0 = cpu_to_le32(cfg0); diff --git a/target/linux/generic/backport-6.6/416-v6.15-03-spi-spi-qpic-snand-avoid-memleak-in-qcom_spi_ecc_ini.patch b/target/linux/generic/backport-6.6/416-v6.15-03-spi-spi-qpic-snand-avoid-memleak-in-qcom_spi_ecc_ini.patch new file mode 100644 index 0000000000..1e2a3b0298 --- /dev/null +++ b/target/linux/generic/backport-6.6/416-v6.15-03-spi-spi-qpic-snand-avoid-memleak-in-qcom_spi_ecc_ini.patch @@ -0,0 +1,35 @@ +From d450cdd9c4398add1f2aa7200f2c95f1e3b9f9fa Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Thu, 13 Mar 2025 19:31:21 +0100 +Subject: [PATCH] spi: spi-qpic-snand: avoid memleak in + qcom_spi_ecc_init_ctx_pipelined() + +When the allocation of the OOB buffer fails, the +qcom_spi_ecc_init_ctx_pipelined() function returns without freeing +the memory allocated for 'ecc_cfg' thus it can cause a memory leak. + +Call kfree() to free 'ecc_cfg' before returning from the function +to avoid that. + +Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") +Signed-off-by: Gabor Juhos +Link: https://patch.msgid.link/20250313-qpic-snand-memleak-fix-v1-1-e54e78d1da3a@gmail.com +Signed-off-by: Mark Brown +--- + drivers/spi/spi-qpic-snand.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/spi/spi-qpic-snand.c ++++ b/drivers/spi/spi-qpic-snand.c +@@ -263,8 +263,10 @@ static int qcom_spi_ecc_init_ctx_pipelin + return -ENOMEM; + snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize, + GFP_KERNEL); +- if (!snandc->qspi->oob_buf) ++ if (!snandc->qspi->oob_buf) { ++ kfree(ecc_cfg); + return -ENOMEM; ++ } + + memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); + diff --git a/target/linux/generic/backport-6.6/416-v6.15-04-spi-SPI_QPIC_SNAND-should-be-tristate-and-depend-on-.patch b/target/linux/generic/backport-6.6/416-v6.15-04-spi-SPI_QPIC_SNAND-should-be-tristate-and-depend-on-.patch new file mode 100644 index 0000000000..a5710f7fcf --- /dev/null +++ b/target/linux/generic/backport-6.6/416-v6.15-04-spi-SPI_QPIC_SNAND-should-be-tristate-and-depend-on-.patch @@ -0,0 +1,49 @@ +From d32c4e58545f17caaa854415f854691e32d42075 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Wed, 26 Mar 2025 15:22:19 +0100 +Subject: [PATCH] spi: SPI_QPIC_SNAND should be tristate and depend on MTD + +SPI_QPIC_SNAND is the only driver that selects MTD instead of depending +on it, which could lead to circular dependencies. Moreover, as +SPI_QPIC_SNAND is bool, this forces MTD (and various related symbols) to +be built-in, as can be seen in an allmodconfig kernel. + +Except for a missing semicolon, there is no reason why SPI_QPIC_SNAND +cannot be tristate; all MODULE_*() boilerplate is already present. +Hence make SPI_QPIC_SNAND tristate, let it depend on MTD, and add the +missing semicolon. + +Fixes: 7304d1909080ef0c ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") +Signed-off-by: Geert Uytterhoeven +Link: https://patch.msgid.link/b63db431cbf35223a4400e44c296293d32c4543c.1742998909.git.geert+renesas@glider.be +Signed-off-by: Mark Brown +--- + drivers/spi/Kconfig | 4 ++-- + drivers/spi/spi-qpic-snand.c | 2 +- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -871,9 +871,9 @@ config SPI_QCOM_QSPI + QSPI(Quad SPI) driver for Qualcomm QSPI controller. + + config SPI_QPIC_SNAND +- bool "QPIC SNAND controller" ++ tristate "QPIC SNAND controller" + depends on ARCH_QCOM || COMPILE_TEST +- select MTD ++ depends on MTD + help + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller. + QPIC controller supports both parallel nand and serial nand. +--- a/drivers/spi/spi-qpic-snand.c ++++ b/drivers/spi/spi-qpic-snand.c +@@ -1614,7 +1614,7 @@ static const struct of_device_id qcom_sn + .data = &ipq9574_snandc_props, + }, + {} +-} ++}; + MODULE_DEVICE_TABLE(of, qcom_snandc_of_match); + + static struct platform_driver qcom_spi_driver = { diff --git a/target/linux/generic/backport-6.6/416-v6.15-05-spi-spi-qpic-snand-use-kmalloc-for-OOB-buffer-alloca.patch b/target/linux/generic/backport-6.6/416-v6.15-05-spi-spi-qpic-snand-use-kmalloc-for-OOB-buffer-alloca.patch new file mode 100644 index 0000000000..5a3d498bcb --- /dev/null +++ b/target/linux/generic/backport-6.6/416-v6.15-05-spi-spi-qpic-snand-use-kmalloc-for-OOB-buffer-alloca.patch @@ -0,0 +1,29 @@ +From f48d80503504257682e493dc17408f2f0b47bcfa Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Thu, 20 Mar 2025 19:11:59 +0100 +Subject: [PATCH] spi: spi-qpic-snand: use kmalloc() for OOB buffer allocation + +The qcom_spi_ecc_init_ctx_pipelined() function allocates zeroed +memory for the OOB buffer, then it fills the buffer with '0xff' +bytes right after the allocation. In this case zeroing the memory +during allocation is superfluous, so use kmalloc() instead of +kzalloc() to avoid that. + +Signed-off-by: Gabor Juhos +Link: https://patch.msgid.link/20250320-qpic-snand-kmalloc-v1-1-94e267550675@gmail.com +Signed-off-by: Mark Brown +--- + drivers/spi/spi-qpic-snand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-qpic-snand.c ++++ b/drivers/spi/spi-qpic-snand.c +@@ -261,7 +261,7 @@ static int qcom_spi_ecc_init_ctx_pipelin + ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); + if (!ecc_cfg) + return -ENOMEM; +- snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize, ++ snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize, + GFP_KERNEL); + if (!snandc->qspi->oob_buf) { + kfree(ecc_cfg); diff --git a/target/linux/generic/files/drivers/net/phy/adm6996.c b/target/linux/generic/files/drivers/net/phy/adm6996.c index 66013f273d..dfee13c0bf 100644 --- a/target/linux/generic/files/drivers/net/phy/adm6996.c +++ b/target/linux/generic/files/drivers/net/phy/adm6996.c @@ -1199,19 +1199,17 @@ static int adm6996_gpio_probe(struct platform_device *pdev) return 0; } -static int adm6996_gpio_remove(struct platform_device *pdev) +static void adm6996_gpio_remove(struct platform_device *pdev) { struct adm6996_priv *priv = platform_get_drvdata(pdev); if (priv && (priv->model == ADM6996M || priv->model == ADM6996L)) unregister_switch(&priv->dev); - - return 0; } static struct platform_driver adm6996_gpio_driver = { .probe = adm6996_gpio_probe, - .remove = adm6996_gpio_remove, + .remove_new = adm6996_gpio_remove, .driver = { .name = "adm6996_gpio", }, diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.c b/target/linux/generic/files/drivers/net/phy/ar8327.c index cf9c2dc3c1..d6749ad70e 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8327.c +++ b/target/linux/generic/files/drivers/net/phy/ar8327.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -1209,7 +1210,7 @@ ar8327_sw_hw_apply(struct switch_dev *dev) return 0; } -int +static int ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -1227,7 +1228,7 @@ ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev, return 0; } -int +static int ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -1245,7 +1246,7 @@ ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev, return 0; } -int +static int ar8327_sw_get_igmp_snooping(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -1262,7 +1263,7 @@ ar8327_sw_get_igmp_snooping(struct switch_dev *dev, return 0; } -int +static int ar8327_sw_set_igmp_snooping(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -1278,7 +1279,7 @@ ar8327_sw_set_igmp_snooping(struct switch_dev *dev, return 0; } -int +static int ar8327_sw_get_igmp_v3(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) @@ -1294,7 +1295,7 @@ ar8327_sw_get_igmp_v3(struct switch_dev *dev, return 0; } -int +static int ar8327_sw_set_igmp_v3(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c b/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c index 0a21ff1de5..62dfe1c242 100644 --- a/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c @@ -217,19 +217,17 @@ static int b53_mmap_probe(struct platform_device *pdev) return b53_swconfig_switch_register(dev); } -static int b53_mmap_remove(struct platform_device *pdev) +static void b53_mmap_remove(struct platform_device *pdev) { struct b53_device *dev = platform_get_drvdata(pdev); if (dev) b53_switch_remove(dev); - - return 0; } static struct platform_driver b53_mmap_driver = { .probe = b53_mmap_probe, - .remove = b53_mmap_remove, + .remove_new = b53_mmap_remove, .driver = { .name = "b53-switch", }, diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c b/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c index ead5209cf0..f8cb99383f 100644 --- a/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c @@ -354,19 +354,17 @@ static int b53_srab_probe(struct platform_device *pdev) return b53_swconfig_switch_register(dev); } -static int b53_srab_remove(struct platform_device *pdev) +static void b53_srab_remove(struct platform_device *pdev) { struct b53_device *dev = platform_get_drvdata(pdev); if (dev) b53_switch_remove(dev); - - return 0; } static struct platform_driver b53_srab_driver = { .probe = b53_srab_probe, - .remove = b53_srab_remove, + .remove_new = b53_srab_remove, .driver = { .name = "b53-srab-switch", }, diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c index a26fd204cb..89fc04fa64 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c @@ -254,7 +254,7 @@ static int __rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data) #define MDC_MDIO_WRITE_OP 0x0003 #define MDC_REALTEK_PHY_ADDR 0x0 -int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data) +static int __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data) { u32 phy_id = smi->phy_id; struct mii_bus *mbus = smi->ext_mbus; @@ -1527,7 +1527,7 @@ static void rtl8366_smi_reset(struct rtl8366_smi *smi, bool active) reset_control_deassert(smi->reset); } -int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi) +static int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi) { int sck = of_get_named_gpio(pdev->dev.of_node, "gpio-sck", 0); int sda = of_get_named_gpio(pdev->dev.of_node, "gpio-sda", 0); @@ -1577,7 +1577,7 @@ static inline int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8 } #endif -int rtl8366_smi_probe_plat(struct platform_device *pdev, struct rtl8366_smi *smi) +static int rtl8366_smi_probe_plat(struct platform_device *pdev, struct rtl8366_smi *smi) { struct rtl8366_platform_data *pdata = pdev->dev.platform_data; diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366rb.c b/target/linux/generic/files/drivers/net/phy/rtl8366rb.c index 0878ca9f14..7057b25252 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8366rb.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8366rb.c @@ -1478,7 +1478,7 @@ static int rtl8366rb_probe(struct platform_device *pdev) return err; } -static int rtl8366rb_remove(struct platform_device *pdev) +static void rtl8366rb_remove(struct platform_device *pdev) { struct rtl8366_smi *smi = platform_get_drvdata(pdev); @@ -1488,8 +1488,6 @@ static int rtl8366rb_remove(struct platform_device *pdev) rtl8366_smi_cleanup(smi); kfree(smi); } - - return 0; } #ifdef CONFIG_OF @@ -1506,7 +1504,7 @@ static struct platform_driver rtl8366rb_driver = { .of_match_table = of_match_ptr(rtl8366rb_match), }, .probe = rtl8366rb_probe, - .remove = rtl8366rb_remove, + .remove_new = rtl8366rb_remove, }; static int __init rtl8366rb_module_init(void) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366s.c b/target/linux/generic/files/drivers/net/phy/rtl8366s.c index d4045fcc06..5458c50487 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8366s.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8366s.c @@ -1266,7 +1266,7 @@ static int rtl8366s_probe(struct platform_device *pdev) return err; } -static int rtl8366s_remove(struct platform_device *pdev) +static void rtl8366s_remove(struct platform_device *pdev) { struct rtl8366_smi *smi = platform_get_drvdata(pdev); @@ -1276,8 +1276,6 @@ static int rtl8366s_remove(struct platform_device *pdev) rtl8366_smi_cleanup(smi); kfree(smi); } - - return 0; } #ifdef CONFIG_OF @@ -1296,7 +1294,7 @@ static struct platform_driver rtl8366s_driver = { #endif }, .probe = rtl8366s_probe, - .remove = rtl8366s_remove, + .remove_new = rtl8366s_remove, }; static int __init rtl8366s_module_init(void) diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367.c b/target/linux/generic/files/drivers/net/phy/rtl8367.c index 950e9d2767..1b996019a6 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367.c @@ -1801,7 +1801,7 @@ static int rtl8367_probe(struct platform_device *pdev) return err; } -static int rtl8367_remove(struct platform_device *pdev) +static void rtl8367_remove(struct platform_device *pdev) { struct rtl8366_smi *smi = platform_get_drvdata(pdev); @@ -1811,8 +1811,6 @@ static int rtl8367_remove(struct platform_device *pdev) rtl8366_smi_cleanup(smi); kfree(smi); } - - return 0; } static void rtl8367_shutdown(struct platform_device *pdev) @@ -1839,7 +1837,7 @@ static struct platform_driver rtl8367_driver = { #endif }, .probe = rtl8367_probe, - .remove = rtl8367_remove, + .remove_new = rtl8367_remove, .shutdown = rtl8367_shutdown, }; diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c index 5f885aa5be..5adcf00f0c 100644 --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -1600,7 +1600,7 @@ static int rtl8367b_probe(struct platform_device *pdev) return err; } -static int rtl8367b_remove(struct platform_device *pdev) +static void rtl8367b_remove(struct platform_device *pdev) { struct rtl8366_smi *smi = platform_get_drvdata(pdev); @@ -1610,8 +1610,6 @@ static int rtl8367b_remove(struct platform_device *pdev) rtl8366_smi_cleanup(smi); kfree(smi); } - - return 0; } static void rtl8367b_shutdown(struct platform_device *pdev) @@ -1638,7 +1636,7 @@ static struct platform_driver rtl8367b_driver = { #endif }, .probe = rtl8367b_probe, - .remove = rtl8367b_remove, + .remove_new = rtl8367b_remove, .shutdown = rtl8367b_shutdown, }; diff --git a/target/linux/generic/files/drivers/net/phy/swconfig.c b/target/linux/generic/files/drivers/net/phy/swconfig.c index 10dc8d0607..71dd5b31f5 100644 --- a/target/linux/generic/files/drivers/net/phy/swconfig.c +++ b/target/linux/generic/files/drivers/net/phy/swconfig.c @@ -1057,7 +1057,7 @@ static struct genl_family switch_fam = { }; #ifdef CONFIG_OF -void +static void of_switch_load_portmap(struct switch_dev *dev) { struct device_node *port; diff --git a/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch b/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch index ecee160faa..90b5a64b51 100644 --- a/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch +++ b/target/linux/generic/hack-6.6/430-mtk-bmt-support.patch @@ -28,6 +28,6 @@ Subject: [PATCH] mtd/nand: add MediaTek NAND bad block managment table obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o +obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o - obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o - obj-y += onenand/ - obj-y += raw/ + ifeq ($(CONFIG_SPI_QPIC_SNAND),y) + obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o + else diff --git a/target/linux/generic/hack-6.6/781-usb-net-rndis-support-asr.patch b/target/linux/generic/hack-6.6/781-usb-net-rndis-support-asr.patch index 47339b6c22..d5cc7e0a7e 100644 --- a/target/linux/generic/hack-6.6/781-usb-net-rndis-support-asr.patch +++ b/target/linux/generic/hack-6.6/781-usb-net-rndis-support-asr.patch @@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/usb/rndis_host.c +++ b/drivers/net/usb/rndis_host.c -@@ -630,6 +630,16 @@ static const struct driver_info zte_rndi +@@ -640,6 +640,16 @@ static const struct driver_info wwan_rnd .tx_fixup = rndis_tx_fixup, }; @@ -30,7 +30,7 @@ Signed-off-by: Daniel Golle /*-------------------------------------------------------------------------*/ static const struct usb_device_id products [] = { -@@ -666,6 +676,36 @@ static const struct usb_device_id produc +@@ -676,6 +686,36 @@ static const struct usb_device_id produc USB_INTERFACE_INFO(USB_CLASS_WIRELESS_CONTROLLER, 1, 3), .driver_info = (unsigned long) &rndis_info, }, { @@ -64,6 +64,6 @@ Signed-off-by: Daniel Golle + USB_CLASS_WIRELESS_CONTROLLER, 1, 3), + .driver_info = (unsigned long) &asr_rndis_info, +}, { - /* Novatel Verizon USB730L */ - USB_INTERFACE_INFO(USB_CLASS_MISC, 4, 1), - .driver_info = (unsigned long) &rndis_info, + /* Mobile Broadband Modem, seen in Novatel Verizon USB730L and + * Telit FN990A (RNDIS) + */ diff --git a/target/linux/generic/pending-6.6/155-usbnet-restore-usb%d-name-exception-for-local-mac-addresses.patch b/target/linux/generic/pending-6.6/155-usbnet-restore-usb%d-name-exception-for-local-mac-addresses.patch deleted file mode 100644 index 0d32800cbc..0000000000 --- a/target/linux/generic/pending-6.6/155-usbnet-restore-usb%d-name-exception-for-local-mac-addresses.patch +++ /dev/null @@ -1,63 +0,0 @@ -From linux-netdev Tue Dec 03 13:04:55 2024 -From: Dominique Martinet -Date: Tue, 03 Dec 2024 13:04:55 +0000 -To: linux-netdev -Subject: [PATCH] net: usb: usbnet: restore usb%d name exception for local mac addresses -Message-Id: <20241203130457.904325-1-asmadeus () codewreck ! org> -X-MARC-Message: https://marc.info/?l=linux-netdev&m=173323431631309 - -From: Dominique Martinet - -The previous commit assumed that local addresses always came from the -kernel, but some devices hand out local mac addresses so we ended up -with point-to-point devices with a mac set by the driver, renaming to -eth%d when they used to be named usb%d. - -Userspace should not rely on device name, but for the sake of stability -restore the local mac address check portion of the naming exception: -point to point devices which either have no mac set by the driver or -have a local mac handed out by the driver will keep the usb%d name. - -Fixes: 8a7d12d674ac ("net: usb: usbnet: fix name regression") -Signed-off-by: Dominique Martinet ---- - drivers/net/usb/usbnet.c | 20 ++++++++++++++------ - 1 file changed, 14 insertions(+), 6 deletions(-) - ---- a/drivers/net/usb/usbnet.c -+++ b/drivers/net/usb/usbnet.c -@@ -178,6 +178,17 @@ int usbnet_get_ethernet_addr(struct usbn - } - EXPORT_SYMBOL_GPL(usbnet_get_ethernet_addr); - -+static bool usbnet_needs_usb_name_format(struct usbnet *dev, struct net_device *net) -+{ -+ /* Point to point devices which don't have a real MAC address -+ * (or report a fake local one) have historically used the usb%d -+ * naming. Preserve this.. -+ */ -+ return (dev->driver_info->flags & FLAG_POINTTOPOINT) != 0 && -+ (is_zero_ether_addr(net->dev_addr) || -+ is_local_ether_addr(net->dev_addr)); -+} -+ - static void intr_complete (struct urb *urb) - { - struct usbnet *dev = urb->context; -@@ -1766,13 +1777,10 @@ usbnet_probe (struct usb_interface *udev - if (status < 0) - goto out1; - -- // heuristic: "usb%d" for links we know are two-host, -- // else "eth%d" when there's reasonable doubt. userspace -- // can rename the link if it knows better. -+ /* heuristic: rename to "eth%d" if we are not sure this link -+ * is two-host (these links keep "usb%d") */ - if ((dev->driver_info->flags & FLAG_ETHER) != 0 && -- ((dev->driver_info->flags & FLAG_POINTTOPOINT) == 0 || -- /* somebody touched it*/ -- !is_zero_ether_addr(net->dev_addr))) -+ !usbnet_needs_usb_name_format(dev, net)) - strscpy(net->name, "eth%d", sizeof(net->name)); - /* WLAN devices should always be named "wlan%d" */ - if ((dev->driver_info->flags & FLAG_WLAN) != 0) diff --git a/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch index ccafdf2911..abd6586e6c 100644 --- a/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch +++ b/target/linux/generic/pending-6.6/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -138,7 +138,7 @@ Signed-off-by: Jonas Gorski static const struct rt6_info ip6_blk_hole_entry_template = { .dst = { .__rcuref = RCUREF_INIT(1), -@@ -1043,6 +1057,7 @@ static const int fib6_prop[RTN_MAX + 1] +@@ -1077,6 +1091,7 @@ static const int fib6_prop[RTN_MAX + 1] [RTN_BLACKHOLE] = -EINVAL, [RTN_UNREACHABLE] = -EHOSTUNREACH, [RTN_PROHIBIT] = -EACCES, @@ -146,7 +146,7 @@ Signed-off-by: Jonas Gorski [RTN_THROW] = -EAGAIN, [RTN_NAT] = -EINVAL, [RTN_XRESOLVE] = -EINVAL, -@@ -1078,6 +1093,10 @@ static void ip6_rt_init_dst_reject(struc +@@ -1112,6 +1127,10 @@ static void ip6_rt_init_dst_reject(struc rt->dst.output = ip6_pkt_prohibit_out; rt->dst.input = ip6_pkt_prohibit; break; @@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski case RTN_THROW: case RTN_UNREACHABLE: default: -@@ -4554,6 +4573,17 @@ static int ip6_pkt_prohibit_out(struct n +@@ -4588,6 +4607,17 @@ static int ip6_pkt_prohibit_out(struct n return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); } @@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski /* * Allocate a dst for local (unicast / anycast) address. */ -@@ -5045,7 +5075,8 @@ static int rtm_to_fib6_config(struct sk_ +@@ -5079,7 +5109,8 @@ static int rtm_to_fib6_config(struct sk_ if (rtm->rtm_type == RTN_UNREACHABLE || rtm->rtm_type == RTN_BLACKHOLE || rtm->rtm_type == RTN_PROHIBIT || @@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski cfg->fc_flags |= RTF_REJECT; if (rtm->rtm_type == RTN_LOCAL) -@@ -6307,6 +6338,8 @@ static int ip6_route_dev_notify(struct n +@@ -6341,6 +6372,8 @@ static int ip6_route_dev_notify(struct n #ifdef CONFIG_IPV6_MULTIPLE_TABLES net->ipv6.ip6_prohibit_entry->dst.dev = dev; net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); @@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_blk_hole_entry->dst.dev = dev; net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); #endif -@@ -6318,6 +6351,7 @@ static int ip6_route_dev_notify(struct n +@@ -6352,6 +6385,7 @@ static int ip6_route_dev_notify(struct n in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev); #ifdef CONFIG_IPV6_MULTIPLE_TABLES in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev); @@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev); #endif } -@@ -6518,6 +6552,8 @@ static int __net_init ip6_route_net_init +@@ -6552,6 +6586,8 @@ static int __net_init ip6_route_net_init #ifdef CONFIG_IPV6_MULTIPLE_TABLES net->ipv6.fib6_has_custom_rules = false; @@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template, sizeof(*net->ipv6.ip6_prohibit_entry), GFP_KERNEL); -@@ -6528,11 +6564,21 @@ static int __net_init ip6_route_net_init +@@ -6562,11 +6598,21 @@ static int __net_init ip6_route_net_init ip6_template_metrics, true); INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->dst.rt_uncached); @@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, ip6_template_metrics, true); -@@ -6559,6 +6605,8 @@ out: +@@ -6593,6 +6639,8 @@ out: return ret; #ifdef CONFIG_IPV6_MULTIPLE_TABLES @@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski out_ip6_prohibit_entry: kfree(net->ipv6.ip6_prohibit_entry); out_ip6_null_entry: -@@ -6578,6 +6626,7 @@ static void __net_exit ip6_route_net_exi +@@ -6612,6 +6660,7 @@ static void __net_exit ip6_route_net_exi kfree(net->ipv6.ip6_null_entry); #ifdef CONFIG_IPV6_MULTIPLE_TABLES kfree(net->ipv6.ip6_prohibit_entry); @@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski kfree(net->ipv6.ip6_blk_hole_entry); #endif dst_entries_destroy(&net->ipv6.ip6_dst_ops); -@@ -6661,6 +6710,9 @@ void __init ip6_route_init_special_entri +@@ -6695,6 +6744,9 @@ void __init ip6_route_init_special_entri init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); diff --git a/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch index 31e29c447e..d62ccc571c 100644 --- a/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch +++ b/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch @@ -161,7 +161,7 @@ Signed-off-by: Felix Fietkau struct rtnl_link { rtnl_doit_func doit; -@@ -4978,7 +4978,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu +@@ -4981,7 +4981,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu brport_nla_put_flag(skb, flags, mask, IFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) || brport_nla_put_flag(skb, flags, mask, diff --git a/target/linux/ipq40xx/config-6.6 b/target/linux/ipq40xx/config-6.6 index 4e3b53adc8..f975e25693 100644 --- a/target/linux/ipq40xx/config-6.6 +++ b/target/linux/ipq40xx/config-6.6 @@ -502,6 +502,7 @@ CONFIG_SPI_BITBANG=y CONFIG_SPI_GPIO=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y +# CONFIG_SPI_QPIC_SNAND is not set CONFIG_SPI_QUP=y CONFIG_SPMI=y # CONFIG_SPMI_HISI3670 is not set diff --git a/target/linux/ipq806x/config-6.6 b/target/linux/ipq806x/config-6.6 index 53eeb748a0..1d81c0e72b 100644 --- a/target/linux/ipq806x/config-6.6 +++ b/target/linux/ipq806x/config-6.6 @@ -500,6 +500,7 @@ CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y +# CONFIG_SPI_QPIC_SNAND is not set CONFIG_SPI_QUP=y CONFIG_SPMI=y # CONFIG_SPMI_HISI3670 is not set diff --git a/target/linux/layerscape/image/armv7.mk b/target/linux/layerscape/image/armv7.mk index fd617a5e8d..6caccae6c3 100644 --- a/target/linux/layerscape/image/armv7.mk +++ b/target/linux/layerscape/image/armv7.mk @@ -31,7 +31,6 @@ define Device/fsl_ls1021a-twr DEVICE_VENDOR := NXP DEVICE_MODEL := TWR-LS1021A DEVICE_VARIANT := Default - DEVICE_PACKAGES += ~layerscape-rcw IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-rcw.bin | pad-to 1M | \ diff --git a/target/linux/layerscape/image/armv8_64b.mk b/target/linux/layerscape/image/armv8_64b.mk index c048a81bc4..6c486e73fa 100644 --- a/target/linux/layerscape/image/armv8_64b.mk +++ b/target/linux/layerscape/image/armv8_64b.mk @@ -30,7 +30,6 @@ define Device/fsl_ls1012a-frdm DEVICE_MODEL := FRDM-LS1012A DEVICE_PACKAGES += \ layerscape-ppfe \ - ~trusted-firmware-a-ls1012a-frdm \ kmod-ppfe BLOCKSIZE := 256KiB IMAGE/firmware.bin := \ @@ -56,7 +55,6 @@ define Device/fsl_ls1012a-rdb DEVICE_MODEL := LS1012A-RDB DEVICE_PACKAGES += \ layerscape-ppfe \ - ~trusted-firmware-a-ls1012a-rdb \ kmod-hwmon-ina2xx \ kmod-iio-fxas21002c-i2c \ kmod-iio-fxos8700-i2c \ @@ -80,7 +78,6 @@ define Device/fsl_ls1012a-frwy-sdboot DEVICE_MODEL := FRWY-LS1012A DEVICE_PACKAGES += \ layerscape-ppfe \ - ~trusted-firmware-a-ls1012a-frwy-sdboot \ kmod-ppfe DEVICE_DTS := fsl-ls1012a-frwy IMAGES += firmware.bin @@ -105,7 +102,6 @@ define Device/fsl_ls1028a-rdb DEVICE_VARIANT := Default KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb DEVICE_PACKAGES += \ - ~trusted-firmware-a-ls1028a-rdb \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 \ kmod-rtc-pcf2127 @@ -130,7 +126,6 @@ define Device/fsl_ls1028a-rdb-sdboot DEVICE_VARIANT := SD Card Boot DEVICE_DTS := fsl-ls1028a-rdb DEVICE_PACKAGES += \ - ~trusted-firmware-a-ls1028a-rdb-sdboot \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 \ kmod-rtc-pcf2127 @@ -151,8 +146,6 @@ define Device/fsl_ls1043a-rdb DEVICE_MODEL := LS1043A-RDB DEVICE_VARIANT := Default DEVICE_PACKAGES += \ - ~layerscape-fman \ - ~trusted-firmware-a-ls1043a-rdb \ kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 @@ -175,8 +168,6 @@ define Device/fsl_ls1043a-rdb-sdboot DEVICE_MODEL := LS1043A-RDB DEVICE_VARIANT := SD Card Boot DEVICE_PACKAGES += \ - ~layerscape-fman \ - ~trusted-firmware-a-ls1043a-rdb-sdboot \ kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 @@ -197,9 +188,6 @@ define Device/fsl_ls1046a-frwy DEVICE_VENDOR := NXP DEVICE_MODEL := FRWY-LS1046A DEVICE_VARIANT := Default - DEVICE_PACKAGES += \ - ~layerscape-fman \ - ~trusted-firmware-a-ls1046a-frwy IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -217,9 +205,6 @@ define Device/fsl_ls1046a-frwy-sdboot DEVICE_VENDOR := NXP DEVICE_MODEL := FRWY-LS1046A DEVICE_VARIANT := SD Card Boot - DEVICE_PACKAGES += \ - ~layerscape-fman \ - ~trusted-firmware-a-ls1046a-frwy-sdboot DEVICE_DTS := fsl-ls1046a-frwy IMAGE/sdcard.img.gz := \ ls-clean | \ @@ -239,8 +224,6 @@ define Device/fsl_ls1046a-rdb DEVICE_MODEL := LS1046A-RDB DEVICE_VARIANT := Default DEVICE_PACKAGES += \ - ~layerscape-fman \ - ~trusted-firmware-a-ls1046a-rdb \ kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 @@ -263,8 +246,6 @@ define Device/fsl_ls1046a-rdb-sdboot DEVICE_MODEL := LS1046A-RDB DEVICE_VARIANT := SD Card Boot DEVICE_PACKAGES += \ - ~layerscape-fman \ - ~trusted-firmware-a-ls1046a-rdb-sdboot \ kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ kmod-hwmon-lm90 @@ -287,9 +268,6 @@ define Device/fsl_ls1088a-rdb DEVICE_MODEL := LS1088A-RDB DEVICE_VARIANT := Default DEVICE_PACKAGES += \ - ~layerscape-mc \ - ~layerscape-dpl \ - ~trusted-firmware-a-ls1088a-rdb \ restool \ kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ @@ -315,9 +293,6 @@ define Device/fsl_ls1088a-rdb-sdboot DEVICE_MODEL := LS1088A-RDB DEVICE_VARIANT := SD Card Boot DEVICE_PACKAGES += \ - ~layerscape-mc \ - ~layerscape-dpl \ - ~trusted-firmware-a-ls1088a-rdb-sdboot \ restool \ kmod-ahci-qoriq \ kmod-hwmon-ina2xx \ @@ -342,9 +317,6 @@ define Device/fsl_ls2088a-rdb DEVICE_VENDOR := NXP DEVICE_MODEL := LS2088ARDB DEVICE_PACKAGES += \ - ~layerscape-mc \ - ~layerscape-dpl \ - ~trusted-firmware-a-ls2088a-rdb \ restool \ kmod-ahci-qoriq IMAGE/firmware.bin := \ @@ -365,12 +337,7 @@ define Device/fsl_lx2160a-rdb DEVICE_VENDOR := NXP DEVICE_MODEL := LX2160A-RDB DEVICE_VARIANT := Rev2.0 silicon - DEVICE_PACKAGES += \ - ~layerscape-mc \ - ~layerscape-dpl \ - ~layerscape-ddr-phy \ - ~trusted-firmware-a-lx2160a-rdb \ - restool + DEVICE_PACKAGES += restool IMAGE/firmware.bin := \ ls-clean | \ ls-append $(1)-bl2.pbl | pad-to 1M | \ @@ -391,12 +358,7 @@ define Device/fsl_lx2160a-rdb-sdboot DEVICE_VENDOR := NXP DEVICE_MODEL := LX2160A-RDB DEVICE_VARIANT := Rev2.0 silicon SD Card Boot - DEVICE_PACKAGES += \ - ~layerscape-mc \ - ~layerscape-dpl \ - ~layerscape-ddr-phy \ - ~trusted-firmware-a-lx2160a-rdb-sdboot \ - restool + DEVICE_PACKAGES += restool DEVICE_DTS := fsl-lx2160a-rdb IMAGE/sdcard.img.gz := \ ls-clean | \ diff --git a/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts b/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts new file mode 100755 index 0000000000..3bd59f75a6 --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-mercusys-mr80x-v3.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include +#include + +#include "mt7981.dtsi" +/ { + model = "MERCUSYS MR80X v3"; + compatible = "mercusys,mr80x-v3", "mediatek,mt7981"; + + aliases { + led-boot = &led_status_green; + led-failsafe = &led_status_amber; + led-running = &led_status_green; + led-upgrade = &led_status_green; + + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_amber: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 4 GPIO_ACTIVE_LOW>; + }; + + led_status_green: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: spi_nand@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000 0x0200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x0200000 0x0100000>; + }; + + partition@300000 { + label = "ubi0"; + reg = <0x300000 0x3200000>; + }; + + partition@3500000 { + label = "ubi1"; + reg = <0x3500000 0x3200000>; + read-only; + }; + + partition@6700000 { + label = "userconfig"; + reg = <0x6700000 0x800000>; + read-only; + }; + + partition@6f00000 { + label = "tp_data"; + reg = <0x6f00000 0x800000>; + read-only; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + +&wifi { + status = "okay"; +}; diff --git a/target/linux/mediatek/dts/mt7986a-netcore-n60-pro.dts b/target/linux/mediatek/dts/mt7986a-netcore-n60-pro.dts index 4272bac7a5..3af7792971 100644 --- a/target/linux/mediatek/dts/mt7986a-netcore-n60-pro.dts +++ b/target/linux/mediatek/dts/mt7986a-netcore-n60-pro.dts @@ -13,11 +13,11 @@ aliases { serial0 = &uart0; - label-mac-device = &gmac0; led-boot = &led_power; led-failsafe = &led_power; led-running = &led_power; led-upgrade = &led_power; + label-mac-device = &gmac0; }; chosen { @@ -112,7 +112,7 @@ reg = <0>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_factory_1fef20 0>; + nvmem-cells = <&macaddr_factory_1fef20>; nvmem-cell-names = "mac-address"; fixed-link { @@ -128,7 +128,7 @@ phy-handle = <&phy6>; phy-mode = "2500base-x"; - nvmem-cells = <&macaddr_factory_1fef26 0>; + nvmem-cells = <&macaddr_factory_1fef26>; nvmem-cell-names = "mac-address"; }; @@ -273,15 +273,11 @@ }; macaddr_factory_1fef20: macaddr@1fef20 { - compatible = "mac-base"; reg = <0x1fef20 0x6>; - #nvmem-cell-cells = <1>; }; macaddr_factory_1fef26: macaddr@1fef26 { - compatible = "mac-base"; reg = <0x1fef26 0x6>; - #nvmem-cell-cells = <1>; }; }; }; @@ -343,16 +339,16 @@ }; }; -&trng { - status = "okay"; -}; - &ssusb { vusb33-supply = <®_3p3v>; vbus-supply = <®_5v>; status = "okay"; }; +&trng { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index 90b6c63473..0bc8daf842 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -85,6 +85,12 @@ livinet,zr-3020-ubootmod) ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0" ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0" ;; +mercusys,mr80x-v3) + ucidef_set_led_netdev "lan1" "lan-1" "green:lan-1" "lan1" "link tx rx" + ucidef_set_led_netdev "lan2" "lan-2" "green:lan-2" "lan2" "link tx rx" + ucidef_set_led_netdev "lan3" "lan-3" "green:lan-3" "lan3" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "green:wan" "wan" "link tx rx" + ;; mercusys,mr90x-v1|\ mercusys,mr90x-v1-ubi) ucidef_set_led_netdev "lan-0" "lan-0" "green:lan-0" "lan0" "link tx rx" @@ -96,9 +102,9 @@ netcore,n60) ucidef_set_led_netdev "wan" "WAN" "mdio-bus:06:green:wan" "eth1" "link tx rx" ;; netcore,n60-pro) - ucidef_set_led_netdev "wanlink" "WANLINK" "mdio-bus:06:green:wan" "eth1" "link_10 link_100 link_1000 link_2500 tx rx" - ucidef_set_led_netdev "lan-1" "LAN-1" "mdio-bus:05:green:lan" "lan1" "link_10 link_100 link_1000 link_2500 tx rx" - ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth1" "link" + ucidef_set_led_netdev "lan1" "LAN1" "mdio-bus:05:green:lan" "lan1" "link tx rx" + ucidef_set_led_netdev "wanact" "WANACT" "mdio-bus:06:green:wan" "eth1" "tx rx" + ucidef_set_led_netdev "wanlink" "WANLINK" "blue:wan" "eth1" "link" ;; netgear,wax220) ucidef_set_led_netdev "eth0" "LAN" "green:lan" "eth0" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index cd9c12c889..ff16e37fbe 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -17,6 +17,7 @@ mediatek_setup_interfaces() konka,komi-a31|\ netis,nx31|\ nokia,ea0326gmp|\ + mercusys,mr80x-v3|\ zbtlink,zbt-z8103ax) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1 ;; @@ -178,6 +179,12 @@ mediatek_setup_macs() lan_mac=$(macaddr_add "$wan_mac" 1) label_mac=$wan_mac ;; + mercusys,mr80x-v3) + mac_dirty=$(cat "/tmp/tp_data/default-mac" | sed -n 's/^'"MAC"'://p') + label_mac=$(macaddr_canonicalize "$mac_dirty") + lan_mac=$label_mac + wan_mac=$(macaddr_add "$lan_mac" 1) + ;; mercusys,mr90x-v1|\ tplink,re6000xd) label_mac=$(get_mac_binary "/tmp/tp_data/default-mac" 0) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index 8456c462b6..34aacb9312 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -9,6 +9,10 @@ board=$(board_name) case "$FIRMWARE" in "mediatek/mt7981_eeprom_mt7976_dbdc.bin") case "$board" in + mercusys,mr80x-v3) + ln -sf /tmp/tp_data/MT7981_EEPROM.bin \ + /lib/firmware/$FIRMWARE + ;; ubnt,unifi-6-plus) caldata_extract_mmc "factory" 0x0 0x1000 ;; diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 62a2d620ed..0e2869613b 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -112,6 +112,12 @@ case "$board" in [ "$PHYNBR" = "1" ] && \ macaddr_setbit_la "$(mtd_get_mac_binary rf-eeprom 0x4)" > /sys${DEVPATH}/macaddress ;; + mercusys,mr80x-v3) + mac_dirty=$(cat "/tmp/tp_data/default-mac" | sed -n 's/^'"MAC"'://p') + label_mac=$(macaddr_canonicalize "$mac_dirty") + [ "$PHYNBR" = "0" ] && macaddr_add $label_mac -1 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $label_mac -2 > /sys${DEVPATH}/macaddress + ;; mercusys,mr90x-v1|\ tplink,re6000xd) addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0) diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part b/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part index 11e3b598af..1474fad831 100644 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/09_mount_cfg_part @@ -12,6 +12,7 @@ mount_ubi_part() { preinit_mount_cfg_part() { case $(board_name) in + mercusys,mr80x-v3|\ mercusys,mr90x-v1|\ tplink,re6000xd) mount_ubi_part "tp_data" diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 9bfad26719..73097ae3d3 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -146,6 +146,7 @@ platform_do_upgrade() { fw_setenv sw_tryactive 0 nand_do_upgrade "$1" ;; + mercusys,mr80x-v3|\ mercusys,mr90x-v1|\ tplink,re6000xd) CI_UBIPART="ubi0" diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index d45ceab2e1..969593c1b0 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -1450,6 +1450,20 @@ define Device/mediatek_mt7988a-rfb endef TARGET_DEVICES += mediatek_mt7988a-rfb +define Device/mercusys_mr80x-v3 + DEVICE_VENDOR := MERCUSYS + DEVICE_MODEL := MR80X + DEVICE_VARIANT := v3 + DEVICE_DTS := mt7981b-mercusys-mr80x-v3 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += mercusys_mr80x-v3 + define Device/mercusys_mr90x-v1 DEVICE_VENDOR := MERCUSYS DEVICE_MODEL := MR90X v1 diff --git a/target/linux/mvebu/patches-6.6/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch b/target/linux/mvebu/patches-6.6/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch index e9c1d57d24..2f7361c93e 100644 --- a/target/linux/mvebu/patches-6.6/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch +++ b/target/linux/mvebu/patches-6.6/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch @@ -207,7 +207,7 @@ Cc: Robert Marko + }; --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -609,6 +609,8 @@ patternProperties: +@@ -611,6 +611,8 @@ patternProperties: description: IC Plus Corp. "^idt,.*": description: Integrated Device Technologies, Inc. diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623od-hd-v1.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623od-hd-v1.dts index a4e49c9d6f..f54593a08b 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623od-hd-v1.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-eap623od-hd-v1.dts @@ -16,10 +16,10 @@ aliases { serial0 = &blsp1_uart3; - led-boot = &led_system; - led-failsafe = &led_system; - led-running = &led_system; - led-upgrade = &led_system; + led-boot = &led_sys_green; + led-failsafe = &led_sys_yellow; + led-running = &led_sys_green; + led-upgrade = &led_sys_yellow; }; chosen { @@ -40,15 +40,15 @@ leds { compatible = "gpio-leds"; - led_system: system { + led_sys_green: led-0 { color = ; function = LED_FUNCTION_STATUS; gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; }; - wlan { + led_sys_yellow: led-1 { color = ; - function = LED_FUNCTION_WLAN; + function = LED_FUNCTION_STATUS; gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; }; }; @@ -86,15 +86,14 @@ &mdio { status = "okay"; - pinctrl-0 = <&mdio_pins>; + reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <50000>; + pinctrl-0 = <&mdio_pins>, <&phy_pins>; pinctrl-names = "default"; rtl8211f: ethernet-phy@4 { - compatible = "ethernet-phy-id001c.c916"; reg = <4>; - reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&phy_pins>; - pinctrl-names = "default"; realtek,clkout-disable; realtek,aldps-enable; diff --git a/target/linux/qualcommax/patches-6.6/0409-v14-6-8-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch b/target/linux/qualcommax/patches-6.6/0409-v14-6-8-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch deleted file mode 100644 index 8635746410..0000000000 --- a/target/linux/qualcommax/patches-6.6/0409-v14-6-8-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch +++ /dev/null @@ -1,2096 +0,0 @@ -From patchwork Wed Nov 20 09:15:04 2024 -Content-Type: text/plain; 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The original - message has been attached to this so you can view it or label - similar future email. If you have any questions, see - the administrator of that system for details. - Content preview: This driver implements support for the SPI-NAND mode of - QCOM - NAND Flash Interface as a SPI-MEM controller with pipelined ECC - capability. - Co-developed-by: Sricharan Ramabadhran - Signed-off-by: - Sricharan Ramabadhran Co-developed-by: - Varadarajan - Narayanan Sig [...] - Content analysis details: (-2.8 points, 5.0 required) - pts rule name description - ---- ---------------------- - -------------------------------------------------- - 0.0 RCVD_IN_VALIDITY_RPBL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to - Validity was blocked. See - https://knowledge.validity.com/hc/en-us/articles/20961730681243 - for more information. - [205.220.180.131 listed in - bl.score.senderscore.com] - 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to - Validity was blocked. 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See - https://knowledge.validity.com/hc/en-us/articles/20961730681243 - for more information. - [205.220.180.131 listed in - sa-trusted.bondedsender.org] - -0.0 SPF_PASS SPF: sender matches SPF record - 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record - -0.1 DKIM_VALID Message has at least one valid DKIM or DK - signature - -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from - envelope-from domain - -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from - author's - domain - 0.1 DKIM_SIGNED Message has a DKIM or DK signature, - not necessarily valid - -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% - [score: 0.0000] -X-BeenThere: linux-mtd@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: Linux MTD discussion mailing list -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Sender: "linux-mtd" -Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org - -This driver implements support for the SPI-NAND mode of QCOM NAND Flash -Interface as a SPI-MEM controller with pipelined ECC capability. - -Co-developed-by: Sricharan Ramabadhran -Signed-off-by: Sricharan Ramabadhran -Co-developed-by: Varadarajan Narayanan -Signed-off-by: Varadarajan Narayanan -Signed-off-by: Md Sadre Alam ---- - -Change in [v14] - -* No Change - -Change in [v13] - -* Changed return type of qcom_spi_cmd_mapping() from u32 to - int to fix the kernel test bot warning -* Changed type of variable cmd in qcom_spi_write_page() from u32 - to int -* Removed unused variable s_op from qcom_spi_write_page() -* Updated return value variable type from u32 to int in - qcom_spi_send_cmdaddr() - -Change in [v12] - -* Added obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o in Makefile - to build qpic_common.c based on CONFIG_SPI_QPIC_SNAND - -Change in [v11] - -* Fixed build error reported by kernel test bot -* Changed "depends on MTD" to "select MTD" in - drivers/spi/Kconfig file - -Change in [v10] - -* Fixed compilation warnings reported by kernel test robot. -* Added depends on CONFIG_MTD -* removed extra bracket from statement if (i == (num_cw - 1)) in - qcom_spi_program_raw() api. - -Change in [v9] - -* Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand - structure -* In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix - compilation warning -* In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix - compilation warning -* In qcom_spi_init() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables - reqs, user, step_size, strength and added cpu_to_le32() macro as well - to fix compilation warning -* In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilation - warning -* In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation - warning - -Change in [v8] - -* Included "bitfield.h" file to /spi-qpic-snand.c - to fix compilation warning reported by kernel test robot -* Removed unused variable "steps" in - qcom_spi_ecc_init_ctx_pipelined() to fix compilation warning - -Change in [v7] - -* Added read_oob() and write_oob() api - -* Handled offset value for oob layout - -* Made CONFIG_SPI_QPIC_SNAND as bool - -* Added macro ecceng_to_qspi() - -* Added FIELD_PREP() Macro in spi init - -* Added else condition in - qcom_spi_ecc_finish_io_req_pipelined() - for corrected ecc - -* Handled multiple error condition for api - qcom_spi_cmd_mapping() - -* Fix typo for printing debug message - -Change in [v6] - -* Added separate qpic_spi_nand{...} struct - -* moved qpic_ecc and qcom_ecc_stats struct to - spi-qpic-snand.c file, since its spi nand - specific - -* Added FIELD_PREP() and GENMASK() macro - -* Removed rawnand.h and partition.h from - spi-qpic-snand.c - -* Removed oob_buff assignment form - qcom_spi_write_page_cache - -* Added qcom_nand_unalloc() in remove() path - -* Fixes all all comments - -Change in [v5] - -* Added raw_read() and raw_write() api - -* Updated commit message - -* Removed register indirection - -* Added qcom_spi_ prefix to all the api - -* Removed snand_set_reg() api. - -* Fixed nandbiterr issue - -* Removed hardcoded num_cw and made it variable - -* Removed hardcoded value for mtd pagesize - -* Added -ENOSUPPORT in cmd mapping for unsupported - commands - -* Replace if..else with switch..case statement - -Change in [v4] - -* No change - -Change in [v3] - -* Set SPI_QPIC_SNAND to n and added COMPILE_TEST in Kconfig - -* Made driver name sorted in Make file - -* Made comment like c++ - -* Changed macro to functions, snandc_set_read_loc_last() - and snandc_set_read_loc_first() - -* Added error handling in snandc_set_reg() - -* Changed into normal conditional statement for - return snandc->ecc_stats.failed ? -EBADMSG : - snandc->ecc_stats.bitflips; - -* Remove cast of wbuf in qpic_snand_program_execute() - function - -* Made num_cw variable instead hardcoded value - -* changed if..else condition of function qpic_snand_io_op() - to switch..case statement - -* Added __devm_spi_alloc_controller() api instead of - devm_spi_alloc_master() - -* Disabling clock in remove path - -Change in [v2] - -* Added initial support for SPI-NAND driver - -Change in [v1] - -* Added RFC patch for design review - - drivers/mtd/nand/Makefile | 4 + - drivers/spi/Kconfig | 9 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-qpic-snand.c | 1633 ++++++++++++++++++++++++++ - include/linux/mtd/nand-qpic-common.h | 7 + - 5 files changed, 1654 insertions(+) - create mode 100644 drivers/spi/spi-qpic-snand.c - ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -4,7 +4,11 @@ nandcore-objs := core.o bbt.o - obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o - obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o - obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o -+ifeq ($(CONFIG_SPI_QPIC_SNAND),y) -+obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o -+else - obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o -+endif - obj-y += onenand/ - obj-y += raw/ - obj-y += spi/ ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -870,6 +870,15 @@ config SPI_QCOM_QSPI - help - QSPI(Quad SPI) driver for Qualcomm QSPI controller. - -+config SPI_QPIC_SNAND -+ bool "QPIC SNAND controller" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select MTD -+ help -+ QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller. -+ QPIC controller supports both parallel nand and serial nand. -+ This config will enable serial nand driver for QPIC controller. -+ - config SPI_QUP - tristate "Qualcomm SPI controller with QUP interface" - depends on ARCH_QCOM || COMPILE_TEST ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx- - obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o - obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o - obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o -+obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o - obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o - obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o ---- /dev/null -+++ b/drivers/spi/spi-qpic-snand.c -@@ -0,0 +1,1633 @@ -+/* -+ * SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. -+ * -+ * Authors: -+ * Md Sadre Alam -+ * Sricharan R -+ * Varadarajan Narayanan -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NAND_FLASH_SPI_CFG 0xc0 -+#define NAND_NUM_ADDR_CYCLES 0xc4 -+#define NAND_BUSY_CHECK_WAIT_CNT 0xc8 -+#define NAND_FLASH_FEATURES 0xf64 -+ -+/* QSPI NAND config reg bits */ -+#define LOAD_CLK_CNTR_INIT_EN BIT(28) -+#define CLK_CNTR_INIT_VAL_VEC 0x924 -+#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16) -+#define FEA_STATUS_DEV_ADDR 0xc0 -+#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8) -+#define SPI_CFG BIT(0) -+#define SPI_NUM_ADDR 0xDA4DB -+#define SPI_WAIT_CNT 0x10 -+#define QPIC_QSPI_NUM_CS 1 -+#define SPI_TRANSFER_MODE_x1 BIT(29) -+#define SPI_TRANSFER_MODE_x4 (3 << 29) -+#define SPI_WP BIT(28) -+#define SPI_HOLD BIT(27) -+#define QPIC_SET_FEATURE BIT(31) -+ -+#define SPINAND_RESET 0xff -+#define SPINAND_READID 0x9f -+#define SPINAND_GET_FEATURE 0x0f -+#define SPINAND_SET_FEATURE 0x1f -+#define SPINAND_READ 0x13 -+#define SPINAND_ERASE 0xd8 -+#define SPINAND_WRITE_EN 0x06 -+#define SPINAND_PROGRAM_EXECUTE 0x10 -+#define SPINAND_PROGRAM_LOAD 0x84 -+ -+#define ACC_FEATURE 0xe -+#define BAD_BLOCK_MARKER_SIZE 0x2 -+#define OOB_BUF_SIZE 128 -+#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng) -+struct qpic_snand_op { -+ u32 cmd_reg; -+ u32 addr1_reg; -+ u32 addr2_reg; -+}; -+ -+struct snandc_read_status { -+ __le32 snandc_flash; -+ __le32 snandc_buffer; -+ __le32 snandc_erased_cw; -+}; -+ -+/* -+ * ECC state struct -+ * @corrected: ECC corrected -+ * @bitflips: Max bit flip -+ * @failed: ECC failed -+ */ -+struct qcom_ecc_stats { -+ u32 corrected; -+ u32 bitflips; -+ u32 failed; -+}; -+ -+struct qpic_ecc { -+ struct device *dev; -+ int ecc_bytes_hw; -+ int spare_bytes; -+ int bbm_size; -+ int ecc_mode; -+ int bytes; -+ int steps; -+ int step_size; -+ int strength; -+ int cw_size; -+ int cw_data; -+ u32 cfg0; -+ u32 cfg1; -+ u32 cfg0_raw; -+ u32 cfg1_raw; -+ u32 ecc_buf_cfg; -+ u32 ecc_bch_cfg; -+ u32 clrflashstatus; -+ u32 clrreadstatus; -+ bool bch_enabled; -+}; -+ -+struct qpic_spi_nand { -+ struct qcom_nand_controller *snandc; -+ struct spi_controller *ctlr; -+ struct mtd_info *mtd; -+ struct clk *iomacro_clk; -+ struct qpic_ecc *ecc; -+ struct qcom_ecc_stats ecc_stats; -+ struct nand_ecc_engine ecc_eng; -+ u8 *data_buf; -+ u8 *oob_buf; -+ u32 wlen; -+ __le32 addr1; -+ __le32 addr2; -+ __le32 cmd; -+ u32 num_cw; -+ bool oob_rw; -+ bool page_rw; -+ bool raw_rw; -+}; -+ -+static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc, -+ int reg, int cw_offset, int read_size, -+ int is_last_read_loc) -+{ -+ __le32 locreg_val; -+ u32 val = (((cw_offset) << READ_LOCATION_OFFSET) | -+ ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc) -+ << READ_LOCATION_LAST)); -+ -+ locreg_val = cpu_to_le32(val); -+ -+ if (reg == NAND_READ_LOCATION_0) -+ snandc->regs->read_location0 = locreg_val; -+ else if (reg == NAND_READ_LOCATION_1) -+ snandc->regs->read_location1 = locreg_val; -+ else if (reg == NAND_READ_LOCATION_2) -+ snandc->regs->read_location1 = locreg_val; -+ else if (reg == NAND_READ_LOCATION_3) -+ snandc->regs->read_location3 = locreg_val; -+} -+ -+static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc, -+ int reg, int cw_offset, int read_size, -+ int is_last_read_loc) -+{ -+ __le32 locreg_val; -+ u32 val = (((cw_offset) << READ_LOCATION_OFFSET) | -+ ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc) -+ << READ_LOCATION_LAST)); -+ -+ locreg_val = cpu_to_le32(val); -+ -+ if (reg == NAND_READ_LOCATION_LAST_CW_0) -+ snandc->regs->read_location_last0 = locreg_val; -+ else if (reg == NAND_READ_LOCATION_LAST_CW_1) -+ snandc->regs->read_location_last1 = locreg_val; -+ else if (reg == NAND_READ_LOCATION_LAST_CW_2) -+ snandc->regs->read_location_last2 = locreg_val; -+ else if (reg == NAND_READ_LOCATION_LAST_CW_3) -+ snandc->regs->read_location_last3 = locreg_val; -+} -+ -+static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand) -+{ -+ struct nand_ecc_engine *eng = nand->ecc.engine; -+ struct qpic_spi_nand *qspi = ecceng_to_qspi(eng); -+ -+ return qspi->snandc; -+} -+ -+static int qcom_spi_init(struct qcom_nand_controller *snandc) -+{ -+ u32 snand_cfg_val = 0x0; -+ int ret; -+ -+ snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) | -+ FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) | -+ FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) | -+ FIELD_PREP(SPI_CFG, 0); -+ -+ snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); -+ snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR); -+ snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); -+ -+ snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN; -+ snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1, -+ NAND_BAM_NEXT_SGL); -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure in submitting spi init descriptor\n"); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_device *nand = mtd_to_nanddev(mtd); -+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); -+ struct qpic_ecc *qecc = snandc->qspi->ecc; -+ -+ if (section > 1) -+ return -ERANGE; -+ -+ oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes; -+ oobregion->offset = mtd->oobsize - oobregion->length; -+ -+ return 0; -+} -+ -+static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_device *nand = mtd_to_nanddev(mtd); -+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); -+ struct qpic_ecc *qecc = snandc->qspi->ecc; -+ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = qecc->steps * 4; -+ oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops qcom_spi_ooblayout = { -+ .ecc = qcom_spi_ooblayout_ecc, -+ .free = qcom_spi_ooblayout_free, -+}; -+ -+static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) -+{ -+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); -+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; -+ struct mtd_info *mtd = nanddev_to_mtd(nand); -+ int cwperpage, bad_block_byte; -+ struct qpic_ecc *ecc_cfg; -+ -+ cwperpage = mtd->writesize / NANDC_STEP_SIZE; -+ snandc->qspi->num_cw = cwperpage; -+ -+ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); -+ if (!ecc_cfg) -+ return -ENOMEM; -+ snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize, -+ GFP_KERNEL); -+ if (!snandc->qspi->oob_buf) -+ return -ENOMEM; -+ -+ memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); -+ -+ nand->ecc.ctx.priv = ecc_cfg; -+ snandc->qspi->mtd = mtd; -+ -+ ecc_cfg->ecc_bytes_hw = 7; -+ ecc_cfg->spare_bytes = 4; -+ ecc_cfg->bbm_size = 1; -+ ecc_cfg->bch_enabled = true; -+ ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size; -+ -+ ecc_cfg->steps = 4; -+ ecc_cfg->strength = 4; -+ ecc_cfg->step_size = 512; -+ ecc_cfg->cw_data = 516; -+ ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; -+ bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1; -+ -+ mtd_set_ooblayout(mtd, &qcom_spi_ooblayout); -+ -+ ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | -+ FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) | -+ FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) | -+ FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | -+ FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) | -+ FIELD_PREP(STATUS_BFR_READ, 0) | -+ FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) | -+ FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes); -+ -+ ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | -+ FIELD_PREP(CS_ACTIVE_BSY, 0) | -+ FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) | -+ FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) | -+ FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | -+ FIELD_PREP(WIDE_FLASH, 0) | -+ FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled); -+ -+ ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | -+ FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | -+ FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) | -+ FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0); -+ -+ ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | -+ FIELD_PREP(CS_ACTIVE_BSY, 0) | -+ FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) | -+ FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) | -+ FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | -+ FIELD_PREP(WIDE_FLASH, 0) | -+ FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1); -+ -+ ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) | -+ FIELD_PREP(ECC_SW_RESET, 0) | -+ FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | -+ FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) | -+ FIELD_PREP(ECC_MODE_MASK, 0) | -+ FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw); -+ -+ ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS; -+ ecc_cfg->clrflashstatus = FS_READY_BSY_N; -+ ecc_cfg->clrreadstatus = 0xc0; -+ -+ conf->step_size = ecc_cfg->step_size; -+ conf->strength = ecc_cfg->strength; -+ -+ snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET); -+ snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET); -+ -+ dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n", -+ ecc_cfg->strength, ecc_cfg->step_size); -+ -+ return 0; -+} -+ -+static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand) -+{ -+ struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); -+ -+ kfree(ecc_cfg); -+} -+ -+static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand, -+ struct nand_page_io_req *req) -+{ -+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); -+ struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); -+ -+ snandc->qspi->ecc = ecc_cfg; -+ snandc->qspi->raw_rw = false; -+ snandc->qspi->oob_rw = false; -+ snandc->qspi->page_rw = false; -+ -+ if (req->datalen) -+ snandc->qspi->page_rw = true; -+ -+ if (req->ooblen) -+ snandc->qspi->oob_rw = true; -+ -+ if (req->mode == MTD_OPS_RAW) -+ snandc->qspi->raw_rw = true; -+ -+ return 0; -+} -+ -+static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand, -+ struct nand_page_io_req *req) -+{ -+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); -+ struct mtd_info *mtd = nanddev_to_mtd(nand); -+ -+ if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ) -+ return 0; -+ -+ if (snandc->qspi->ecc_stats.failed) -+ mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed; -+ else -+ mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected; -+ -+ if (snandc->qspi->ecc_stats.failed) -+ return -EBADMSG; -+ else -+ return snandc->qspi->ecc_stats.bitflips; -+} -+ -+static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = { -+ .init_ctx = qcom_spi_ecc_init_ctx_pipelined, -+ .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined, -+ .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined, -+ .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined, -+}; -+ -+/* helper to configure location register values */ -+static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg, -+ int cw_offset, int read_size, int is_last_read_loc) -+{ -+ int reg_base = NAND_READ_LOCATION_0; -+ int num_cw = snandc->qspi->num_cw; -+ -+ if (cw == (num_cw - 1)) -+ reg_base = NAND_READ_LOCATION_LAST_CW_0; -+ -+ reg_base += reg * 4; -+ -+ if (cw == (num_cw - 1)) -+ return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset, -+ read_size, is_last_read_loc); -+ else -+ return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset, -+ read_size, is_last_read_loc); -+} -+ -+static void -+qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw) -+{ -+ __le32 *reg = &snandc->regs->read_location0; -+ int num_cw = snandc->qspi->num_cw; -+ -+ qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL); -+ if (cw == (num_cw - 1)) { -+ reg = &snandc->regs->read_location_last0; -+ qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, -+ NAND_BAM_NEXT_SGL); -+ } -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); -+ qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); -+ -+ qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); -+ qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, -+ NAND_BAM_NEXT_SGL); -+} -+ -+static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ int ret; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->addr0 = snandc->qspi->addr1; -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE)); -+ snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); -+ qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); -+ qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to erase block\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc, -+ bool use_ecc, int cw) -+{ -+ __le32 *reg = &snandc->regs->read_location0; -+ int num_cw = snandc->qspi->num_cw; -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, -+ NAND_ERASED_CW_DETECT_CFG, 1, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, -+ NAND_ERASED_CW_DETECT_CFG, 1, -+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); -+ -+ if (cw == (num_cw - 1)) { -+ reg = &snandc->regs->read_location_last0; -+ qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL); -+ } -+ qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); -+ qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); -+ -+ qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0); -+} -+ -+static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ struct mtd_info *mtd = snandc->qspi->mtd; -+ int size, ret = 0; -+ int col, bbpos; -+ u32 cfg0, cfg1, ecc_bch_cfg; -+ u32 num_cw = snandc->qspi->num_cw; -+ -+ qcom_clear_bam_transaction(snandc); -+ qcom_clear_read_regs(snandc); -+ -+ size = ecc_cfg->cw_size; -+ col = ecc_cfg->cw_size * (num_cw - 1); -+ -+ memset(snandc->data_buffer, 0xff, size); -+ snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ -+ cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | -+ 0 << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1_raw; -+ ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; -+ -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); -+ snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); -+ -+ qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1); -+ -+ qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0); -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failed to read last cw\n"); -+ return ret; -+ } -+ -+ qcom_nandc_dev_to_mem(snandc, true); -+ u32 flash = le32_to_cpu(snandc->reg_read_buf[0]); -+ -+ if (flash & (FS_OP_ERR | FS_MPU_ERR)) -+ return -EIO; -+ -+ bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); -+ -+ if (snandc->data_buffer[bbpos] == 0xff) -+ snandc->data_buffer[bbpos + 1] = 0xff; -+ if (snandc->data_buffer[bbpos] != 0xff) -+ snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos]; -+ -+ memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes); -+ -+ return ret; -+} -+ -+static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *data_buf, u8 *oob_buf) -+{ -+ struct snandc_read_status *buf; -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ int i, num_cw = snandc->qspi->num_cw; -+ bool flash_op_err = false, erased; -+ unsigned int max_bitflips = 0; -+ unsigned int uncorrectable_cws = 0; -+ -+ snandc->qspi->ecc_stats.failed = 0; -+ snandc->qspi->ecc_stats.corrected = 0; -+ -+ qcom_nandc_dev_to_mem(snandc, true); -+ buf = (struct snandc_read_status *)snandc->reg_read_buf; -+ -+ for (i = 0; i < num_cw; i++, buf++) { -+ u32 flash, buffer, erased_cw; -+ int data_len, oob_len; -+ -+ if (i == (num_cw - 1)) { -+ data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2); -+ oob_len = num_cw << 2; -+ } else { -+ data_len = ecc_cfg->cw_data; -+ oob_len = 0; -+ } -+ -+ flash = le32_to_cpu(buf->snandc_flash); -+ buffer = le32_to_cpu(buf->snandc_buffer); -+ erased_cw = le32_to_cpu(buf->snandc_erased_cw); -+ -+ if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) { -+ if (ecc_cfg->bch_enabled) -+ erased = (erased_cw & ERASED_CW) == ERASED_CW; -+ else -+ erased = false; -+ -+ if (!erased) -+ uncorrectable_cws |= BIT(i); -+ -+ } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) { -+ flash_op_err = true; -+ } else { -+ unsigned int stat; -+ -+ stat = buffer & BS_CORRECTABLE_ERR_MSK; -+ snandc->qspi->ecc_stats.corrected += stat; -+ max_bitflips = max(max_bitflips, stat); -+ } -+ -+ if (data_buf) -+ data_buf += data_len; -+ if (oob_buf) -+ oob_buf += oob_len + ecc_cfg->bytes; -+ } -+ -+ if (flash_op_err) -+ return -EIO; -+ -+ if (!uncorrectable_cws) -+ snandc->qspi->ecc_stats.bitflips = max_bitflips; -+ else -+ snandc->qspi->ecc_stats.failed++; -+ -+ return 0; -+} -+ -+static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt) -+{ -+ int i; -+ -+ qcom_nandc_dev_to_mem(snandc, true); -+ -+ for (i = 0; i < cw_cnt; i++) { -+ u32 flash = le32_to_cpu(snandc->reg_read_buf[i]); -+ -+ if (flash & (FS_OP_ERR | FS_MPU_ERR)) -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf, -+ u8 *oob_buf, int cw) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ struct mtd_info *mtd = snandc->qspi->mtd; -+ int data_size1, data_size2, oob_size1, oob_size2; -+ int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; -+ int raw_cw = cw; -+ u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; -+ int col; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ raw_cw = num_cw - 1; -+ -+ cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | -+ 0 << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1_raw; -+ ecc_bch_cfg = ECC_CFG_ECC_DISABLE; -+ -+ col = ecc_cfg->cw_size * cw; -+ -+ snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); -+ snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, -+ NAND_ERASED_CW_DETECT_CFG, 1, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, -+ NAND_ERASED_CW_DETECT_CFG, 1, -+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); -+ -+ data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); -+ oob_size1 = ecc_cfg->bbm_size; -+ -+ if (cw == (num_cw - 1)) { -+ data_size2 = NANDC_STEP_SIZE - data_size1 - -+ ((num_cw - 1) * 4); -+ oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw + -+ ecc_cfg->spare_bytes; -+ } else { -+ data_size2 = ecc_cfg->cw_data - data_size1; -+ oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; -+ } -+ -+ qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0); -+ read_loc += data_size1; -+ -+ qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0); -+ read_loc += oob_size1; -+ -+ qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0); -+ read_loc += data_size2; -+ -+ qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1); -+ -+ qcom_spi_config_cw_read(snandc, false, raw_cw); -+ -+ qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0); -+ reg_off += data_size1; -+ -+ qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0); -+ reg_off += oob_size1; -+ -+ qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0); -+ reg_off += data_size2; -+ -+ qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0); -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to read raw cw %d\n", cw); -+ return ret; -+ } -+ -+ return qcom_spi_check_raw_flash_errors(snandc, 1); -+} -+ -+static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ u8 *data_buf = NULL, *oob_buf = NULL; -+ int ret, cw; -+ u32 num_cw = snandc->qspi->num_cw; -+ -+ if (snandc->qspi->page_rw) -+ data_buf = op->data.buf.in; -+ -+ oob_buf = snandc->qspi->oob_buf; -+ memset(oob_buf, 0xff, OOB_BUF_SIZE); -+ -+ for (cw = 0; cw < num_cw; cw++) { -+ ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw); -+ if (ret) -+ return ret; -+ -+ if (data_buf) -+ data_buf += ecc_cfg->cw_data; -+ if (oob_buf) -+ oob_buf += ecc_cfg->bytes; -+ } -+ -+ return 0; -+} -+ -+static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start; -+ int ret, i; -+ u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; -+ -+ data_buf = op->data.buf.in; -+ data_buf_start = data_buf; -+ -+ oob_buf = snandc->qspi->oob_buf; -+ oob_buf_start = oob_buf; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ -+ cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | -+ (num_cw - 1) << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1; -+ ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; -+ -+ snandc->regs->addr0 = snandc->qspi->addr1; -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); -+ snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); -+ -+ qcom_clear_bam_transaction(snandc); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, -+ NAND_ERASED_CW_DETECT_CFG, 1, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, -+ NAND_ERASED_CW_DETECT_CFG, 1, -+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); -+ -+ for (i = 0; i < num_cw; i++) { -+ int data_size, oob_size; -+ -+ if (i == (num_cw - 1)) { -+ data_size = 512 - ((num_cw - 1) << 2); -+ oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + -+ ecc_cfg->spare_bytes; -+ } else { -+ data_size = ecc_cfg->cw_data; -+ oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; -+ } -+ -+ if (data_buf && oob_buf) { -+ qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0); -+ qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1); -+ } else if (data_buf) { -+ qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1); -+ } else { -+ qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); -+ } -+ -+ qcom_spi_config_cw_read(snandc, true, i); -+ -+ if (data_buf) -+ qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf, -+ data_size, 0); -+ if (oob_buf) { -+ int j; -+ -+ for (j = 0; j < ecc_cfg->bbm_size; j++) -+ *oob_buf++ = 0xff; -+ -+ qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, -+ oob_buf, oob_size, 0); -+ } -+ -+ if (data_buf) -+ data_buf += data_size; -+ if (oob_buf) -+ oob_buf += oob_size; -+ } -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to read page\n"); -+ return ret; -+ } -+ -+ return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start); -+} -+ -+static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start; -+ int ret, i; -+ u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; -+ -+ oob_buf = op->data.buf.in; -+ oob_buf_start = oob_buf; -+ -+ data_buf_start = data_buf; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ -+ cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | -+ (num_cw - 1) << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1; -+ ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; -+ -+ snandc->regs->addr0 = snandc->qspi->addr1; -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); -+ snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, -+ NAND_ERASED_CW_DETECT_CFG, 1, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, -+ NAND_ERASED_CW_DETECT_CFG, 1, -+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); -+ -+ for (i = 0; i < num_cw; i++) { -+ int data_size, oob_size; -+ -+ if (i == (num_cw - 1)) { -+ data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); -+ oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + -+ ecc_cfg->spare_bytes; -+ } else { -+ data_size = ecc_cfg->cw_data; -+ oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; -+ } -+ -+ qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); -+ -+ qcom_spi_config_cw_read(snandc, true, i); -+ -+ if (oob_buf) { -+ int j; -+ -+ for (j = 0; j < ecc_cfg->bbm_size; j++) -+ *oob_buf++ = 0xff; -+ -+ qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, -+ oob_buf, oob_size, 0); -+ } -+ -+ if (oob_buf) -+ oob_buf += oob_size; -+ } -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to read oob\n"); -+ return ret; -+ } -+ -+ return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start); -+} -+ -+static int qcom_spi_read_page(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ if (snandc->qspi->page_rw && snandc->qspi->raw_rw) -+ return qcom_spi_read_page_raw(snandc, op); -+ -+ if (snandc->qspi->page_rw) -+ return qcom_spi_read_page_ecc(snandc, op); -+ -+ if (snandc->qspi->oob_rw && snandc->qspi->raw_rw) -+ return qcom_spi_read_last_cw(snandc, op); -+ -+ if (snandc->qspi->oob_rw) -+ return qcom_spi_read_page_oob(snandc, op); -+ -+ return 0; -+} -+ -+static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc) -+{ -+ qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, -+ 1, NAND_BAM_NEXT_SGL); -+} -+ -+static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc) -+{ -+ qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); -+ qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); -+ qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0); -+ qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1, -+ NAND_BAM_NEXT_SGL); -+} -+ -+static int qcom_spi_program_raw(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ struct mtd_info *mtd = snandc->qspi->mtd; -+ u8 *data_buf = NULL, *oob_buf = NULL; -+ int i, ret; -+ int num_cw = snandc->qspi->num_cw; -+ u32 cfg0, cfg1, ecc_bch_cfg; -+ -+ cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | -+ (num_cw - 1) << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1_raw; -+ ecc_bch_cfg = ECC_CFG_ECC_DISABLE; -+ -+ data_buf = snandc->qspi->data_buf; -+ -+ oob_buf = snandc->qspi->oob_buf; -+ memset(oob_buf, 0xff, OOB_BUF_SIZE); -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ -+ snandc->regs->addr0 = snandc->qspi->addr1; -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); -+ snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_spi_config_page_write(snandc); -+ -+ for (i = 0; i < num_cw; i++) { -+ int data_size1, data_size2, oob_size1, oob_size2; -+ int reg_off = FLASH_BUF_ACC; -+ -+ data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); -+ oob_size1 = ecc_cfg->bbm_size; -+ -+ if (i == (num_cw - 1)) { -+ data_size2 = NANDC_STEP_SIZE - data_size1 - -+ ((num_cw - 1) << 2); -+ oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + -+ ecc_cfg->spare_bytes; -+ } else { -+ data_size2 = ecc_cfg->cw_data - data_size1; -+ oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; -+ } -+ -+ qcom_write_data_dma(snandc, reg_off, data_buf, data_size1, -+ NAND_BAM_NO_EOT); -+ reg_off += data_size1; -+ data_buf += data_size1; -+ -+ qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1, -+ NAND_BAM_NO_EOT); -+ oob_buf += oob_size1; -+ reg_off += oob_size1; -+ -+ qcom_write_data_dma(snandc, reg_off, data_buf, data_size2, -+ NAND_BAM_NO_EOT); -+ reg_off += data_size2; -+ data_buf += data_size2; -+ -+ qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0); -+ oob_buf += oob_size2; -+ -+ qcom_spi_config_cw_write(snandc); -+ } -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to write raw page\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ u8 *data_buf = NULL, *oob_buf = NULL; -+ int i, ret; -+ int num_cw = snandc->qspi->num_cw; -+ u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; -+ -+ cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | -+ (num_cw - 1) << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1; -+ ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; -+ ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; -+ -+ if (snandc->qspi->data_buf) -+ data_buf = snandc->qspi->data_buf; -+ -+ oob_buf = snandc->qspi->oob_buf; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ -+ snandc->regs->addr0 = snandc->qspi->addr1; -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ qcom_spi_config_page_write(snandc); -+ -+ for (i = 0; i < num_cw; i++) { -+ int data_size, oob_size; -+ -+ if (i == (num_cw - 1)) { -+ data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); -+ oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + -+ ecc_cfg->spare_bytes; -+ } else { -+ data_size = ecc_cfg->cw_data; -+ oob_size = ecc_cfg->bytes; -+ } -+ -+ if (data_buf) -+ qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size, -+ i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0); -+ -+ if (i == (num_cw - 1)) { -+ if (oob_buf) { -+ oob_buf += ecc_cfg->bbm_size; -+ qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size, -+ oob_buf, oob_size, 0); -+ } -+ } -+ -+ qcom_spi_config_cw_write(snandc); -+ -+ if (data_buf) -+ data_buf += data_size; -+ if (oob_buf) -+ oob_buf += oob_size; -+ } -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to write page\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int qcom_spi_program_oob(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; -+ u8 *oob_buf = NULL; -+ int ret, col, data_size, oob_size; -+ int num_cw = snandc->qspi->num_cw; -+ u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; -+ -+ cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) | -+ (num_cw - 1) << CW_PER_PAGE; -+ cfg1 = ecc_cfg->cfg1; -+ ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; -+ ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; -+ -+ col = ecc_cfg->cw_size * (num_cw - 1); -+ -+ oob_buf = snandc->qspi->data_buf; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); -+ snandc->regs->addr1 = snandc->qspi->addr2; -+ snandc->regs->cmd = snandc->qspi->cmd; -+ snandc->regs->cfg0 = cpu_to_le32(cfg0); -+ snandc->regs->cfg1 = cpu_to_le32(cfg1); -+ snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); -+ snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); -+ snandc->regs->exec = cpu_to_le32(1); -+ -+ /* calculate the data and oob size for the last codeword/step */ -+ data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); -+ oob_size = snandc->qspi->mtd->oobavail; -+ -+ memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data); -+ /* override new oob content to last codeword */ -+ mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size, -+ oob_buf, 0, snandc->qspi->mtd->oobavail); -+ qcom_spi_config_page_write(snandc); -+ qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0); -+ qcom_spi_config_cw_write(snandc); -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) { -+ dev_err(snandc->dev, "failure to write oob\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int qcom_spi_program_execute(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ if (snandc->qspi->page_rw && snandc->qspi->raw_rw) -+ return qcom_spi_program_raw(snandc, op); -+ -+ if (snandc->qspi->page_rw) -+ return qcom_spi_program_ecc(snandc, op); -+ -+ if (snandc->qspi->oob_rw) -+ return qcom_spi_program_oob(snandc, op); -+ -+ return 0; -+} -+ -+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode) -+{ -+ int cmd = 0x0; -+ -+ switch (opcode) { -+ case SPINAND_RESET: -+ cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); -+ break; -+ case SPINAND_READID: -+ cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); -+ break; -+ case SPINAND_GET_FEATURE: -+ cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); -+ break; -+ case SPINAND_SET_FEATURE: -+ cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | -+ QPIC_SET_FEATURE); -+ break; -+ case SPINAND_READ: -+ if (snandc->qspi->raw_rw) { -+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | -+ SPI_WP | SPI_HOLD | OP_PAGE_READ); -+ } else { -+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | -+ SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); -+ } -+ -+ break; -+ case SPINAND_ERASE: -+ cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | -+ SPI_HOLD | SPI_TRANSFER_MODE_x1; -+ break; -+ case SPINAND_WRITE_EN: -+ cmd = SPINAND_WRITE_EN; -+ break; -+ case SPINAND_PROGRAM_EXECUTE: -+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | -+ SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); -+ break; -+ case SPINAND_PROGRAM_LOAD: -+ cmd = SPINAND_PROGRAM_LOAD; -+ break; -+ default: -+ dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); -+ return -EOPNOTSUPP; -+ } -+ -+ return cmd; -+} -+ -+static int qcom_spi_write_page(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ int cmd; -+ -+ cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); -+ if (cmd < 0) -+ return cmd; -+ -+ if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) -+ snandc->qspi->data_buf = (u8 *)op->data.buf.out; -+ -+ return 0; -+} -+ -+static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc, -+ const struct spi_mem_op *op) -+{ -+ struct qpic_snand_op s_op = {}; -+ u32 cmd; -+ int ret, opcode; -+ -+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); -+ if (ret < 0) -+ return ret; -+ -+ cmd = ret; -+ -+ s_op.cmd_reg = cmd; -+ s_op.addr1_reg = op->addr.val; -+ s_op.addr2_reg = 0; -+ -+ opcode = op->cmd.opcode; -+ -+ switch (opcode) { -+ case SPINAND_WRITE_EN: -+ return 0; -+ case SPINAND_PROGRAM_EXECUTE: -+ s_op.addr1_reg = op->addr.val << 16; -+ s_op.addr2_reg = op->addr.val >> 16 & 0xff; -+ snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg); -+ snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); -+ snandc->qspi->cmd = cpu_to_le32(cmd); -+ return qcom_spi_program_execute(snandc, op); -+ case SPINAND_READ: -+ s_op.addr1_reg = (op->addr.val << 16); -+ s_op.addr2_reg = op->addr.val >> 16 & 0xff; -+ snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg); -+ snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); -+ snandc->qspi->cmd = cpu_to_le32(cmd); -+ return 0; -+ case SPINAND_ERASE: -+ s_op.addr2_reg = (op->addr.val >> 16) & 0xffff; -+ s_op.addr1_reg = op->addr.val; -+ snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16); -+ snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg); -+ snandc->qspi->cmd = cpu_to_le32(cmd); -+ qcom_spi_block_erase(snandc); -+ return 0; -+ default: -+ break; -+ } -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ -+ snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg); -+ snandc->regs->exec = cpu_to_le32(1); -+ snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg); -+ snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg); -+ -+ qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); -+ qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) -+ dev_err(snandc->dev, "failure in submitting cmd descriptor\n"); -+ -+ return ret; -+} -+ -+static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op) -+{ -+ int ret, val, opcode; -+ bool copy = false, copy_ftr = false; -+ -+ ret = qcom_spi_send_cmdaddr(snandc, op); -+ if (ret) -+ return ret; -+ -+ snandc->buf_count = 0; -+ snandc->buf_start = 0; -+ qcom_clear_read_regs(snandc); -+ qcom_clear_bam_transaction(snandc); -+ opcode = op->cmd.opcode; -+ -+ switch (opcode) { -+ case SPINAND_READID: -+ snandc->buf_count = 4; -+ qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); -+ copy = true; -+ break; -+ case SPINAND_GET_FEATURE: -+ snandc->buf_count = 4; -+ qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); -+ copy_ftr = true; -+ break; -+ case SPINAND_SET_FEATURE: -+ snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out); -+ qcom_write_reg_dma(snandc, &snandc->regs->flash_feature, -+ NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); -+ break; -+ case SPINAND_PROGRAM_EXECUTE: -+ case SPINAND_WRITE_EN: -+ case SPINAND_RESET: -+ case SPINAND_ERASE: -+ case SPINAND_READ: -+ return 0; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ ret = qcom_submit_descs(snandc); -+ if (ret) -+ dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode); -+ -+ if (copy) { -+ qcom_nandc_dev_to_mem(snandc, true); -+ memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count); -+ } -+ -+ if (copy_ftr) { -+ qcom_nandc_dev_to_mem(snandc, true); -+ val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf); -+ val >>= 8; -+ memcpy(op->data.buf.in, &val, snandc->buf_count); -+ } -+ -+ return ret; -+} -+ -+static bool qcom_spi_is_page_op(const struct spi_mem_op *op) -+{ -+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4) -+ return false; -+ -+ if (op->data.dir == SPI_MEM_DATA_IN) { -+ if (op->addr.buswidth == 4 && op->data.buswidth == 4) -+ return true; -+ -+ if (op->addr.nbytes == 2 && op->addr.buswidth == 1) -+ return true; -+ -+ } else if (op->data.dir == SPI_MEM_DATA_OUT) { -+ if (op->data.buswidth == 4) -+ return true; -+ if (op->addr.nbytes == 2 && op->addr.buswidth == 1) -+ return true; -+ } -+ -+ return false; -+} -+ -+static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) -+{ -+ if (!spi_mem_default_supports_op(mem, op)) -+ return false; -+ -+ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) -+ return false; -+ -+ if (qcom_spi_is_page_op(op)) -+ return true; -+ -+ return ((!op->addr.nbytes || op->addr.buswidth == 1) && -+ (!op->dummy.nbytes || op->dummy.buswidth == 1) && -+ (!op->data.nbytes || op->data.buswidth == 1)); -+} -+ -+static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) -+{ -+ struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller); -+ -+ dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, -+ op->addr.val, op->addr.buswidth, op->addr.nbytes, -+ op->data.buswidth, op->data.nbytes); -+ -+ if (qcom_spi_is_page_op(op)) { -+ if (op->data.dir == SPI_MEM_DATA_IN) -+ return qcom_spi_read_page(snandc, op); -+ if (op->data.dir == SPI_MEM_DATA_OUT) -+ return qcom_spi_write_page(snandc, op); -+ } else { -+ return qcom_spi_io_op(snandc, op); -+ } -+ -+ return 0; -+} -+ -+static const struct spi_controller_mem_ops qcom_spi_mem_ops = { -+ .supports_op = qcom_spi_supports_op, -+ .exec_op = qcom_spi_exec_op, -+}; -+ -+static const struct spi_controller_mem_caps qcom_spi_mem_caps = { -+ .ecc = true, -+}; -+ -+static int qcom_spi_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct spi_controller *ctlr; -+ struct qcom_nand_controller *snandc; -+ struct qpic_spi_nand *qspi; -+ struct qpic_ecc *ecc; -+ struct resource *res; -+ const void *dev_data; -+ int ret; -+ -+ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); -+ if (!ecc) -+ return -ENOMEM; -+ -+ qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL); -+ if (!qspi) -+ return -ENOMEM; -+ -+ ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false); -+ if (!ctlr) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, ctlr); -+ -+ snandc = spi_controller_get_devdata(ctlr); -+ qspi->snandc = snandc; -+ -+ snandc->dev = dev; -+ snandc->qspi = qspi; -+ snandc->qspi->ctlr = ctlr; -+ snandc->qspi->ecc = ecc; -+ -+ dev_data = of_device_get_match_data(dev); -+ if (!dev_data) { -+ dev_err(&pdev->dev, "failed to get device data\n"); -+ return -ENODEV; -+ } -+ -+ snandc->props = dev_data; -+ snandc->dev = &pdev->dev; -+ -+ snandc->core_clk = devm_clk_get(dev, "core"); -+ if (IS_ERR(snandc->core_clk)) -+ return PTR_ERR(snandc->core_clk); -+ -+ snandc->aon_clk = devm_clk_get(dev, "aon"); -+ if (IS_ERR(snandc->aon_clk)) -+ return PTR_ERR(snandc->aon_clk); -+ -+ snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom"); -+ if (IS_ERR(snandc->qspi->iomacro_clk)) -+ return PTR_ERR(snandc->qspi->iomacro_clk); -+ -+ snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); -+ if (IS_ERR(snandc->base)) -+ return PTR_ERR(snandc->base); -+ -+ snandc->base_phys = res->start; -+ snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res), -+ DMA_BIDIRECTIONAL, 0); -+ if (dma_mapping_error(dev, snandc->base_dma)) -+ return -ENXIO; -+ -+ ret = clk_prepare_enable(snandc->core_clk); -+ if (ret) -+ goto err_dis_core_clk; -+ -+ ret = clk_prepare_enable(snandc->aon_clk); -+ if (ret) -+ goto err_dis_aon_clk; -+ -+ ret = clk_prepare_enable(snandc->qspi->iomacro_clk); -+ if (ret) -+ goto err_dis_iom_clk; -+ -+ ret = qcom_nandc_alloc(snandc); -+ if (ret) -+ goto err_snand_alloc; -+ -+ ret = qcom_spi_init(snandc); -+ if (ret) -+ goto err_spi_init; -+ -+ /* setup ECC engine */ -+ snandc->qspi->ecc_eng.dev = &pdev->dev; -+ snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; -+ snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined; -+ snandc->qspi->ecc_eng.priv = snandc; -+ -+ ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret); -+ goto err_spi_init; -+ } -+ -+ ctlr->num_chipselect = QPIC_QSPI_NUM_CS; -+ ctlr->mem_ops = &qcom_spi_mem_ops; -+ ctlr->mem_caps = &qcom_spi_mem_caps; -+ ctlr->dev.of_node = pdev->dev.of_node; -+ ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL | -+ SPI_TX_QUAD | SPI_RX_QUAD; -+ -+ ret = spi_register_controller(ctlr); -+ if (ret) { -+ dev_err(&pdev->dev, "spi_register_controller failed.\n"); -+ goto err_spi_init; -+ } -+ -+ return 0; -+ -+err_spi_init: -+ qcom_nandc_unalloc(snandc); -+err_snand_alloc: -+ clk_disable_unprepare(snandc->qspi->iomacro_clk); -+err_dis_iom_clk: -+ clk_disable_unprepare(snandc->aon_clk); -+err_dis_aon_clk: -+ clk_disable_unprepare(snandc->core_clk); -+err_dis_core_clk: -+ dma_unmap_resource(dev, res->start, resource_size(res), -+ DMA_BIDIRECTIONAL, 0); -+ return ret; -+} -+ -+static void qcom_spi_remove(struct platform_device *pdev) -+{ -+ struct spi_controller *ctlr = platform_get_drvdata(pdev); -+ struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr); -+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ spi_unregister_controller(ctlr); -+ -+ qcom_nandc_unalloc(snandc); -+ -+ clk_disable_unprepare(snandc->aon_clk); -+ clk_disable_unprepare(snandc->core_clk); -+ clk_disable_unprepare(snandc->qspi->iomacro_clk); -+ -+ dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), -+ DMA_BIDIRECTIONAL, 0); -+} -+ -+static const struct qcom_nandc_props ipq9574_snandc_props = { -+ .dev_cmd_reg_start = 0x7000, -+ .supports_bam = true, -+}; -+ -+static const struct of_device_id qcom_snandc_of_match[] = { -+ { -+ .compatible = "qcom,ipq9574-snand", -+ .data = &ipq9574_snandc_props, -+ }, -+ {} -+} -+MODULE_DEVICE_TABLE(of, qcom_snandc_of_match); -+ -+static struct platform_driver qcom_spi_driver = { -+ .driver = { -+ .name = "qcom_snand", -+ .of_match_table = qcom_snandc_of_match, -+ }, -+ .probe = qcom_spi_probe, -+ .remove_new = qcom_spi_remove, -+}; -+module_platform_driver(qcom_spi_driver); -+ -+MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores"); -+MODULE_AUTHOR("Md Sadre Alam "); -+MODULE_LICENSE("GPL"); -+ ---- a/include/linux/mtd/nand-qpic-common.h -+++ b/include/linux/mtd/nand-qpic-common.h -@@ -325,6 +325,10 @@ struct nandc_regs { - __le32 read_location_last1; - __le32 read_location_last2; - __le32 read_location_last3; -+ __le32 spi_cfg; -+ __le32 num_addr_cycle; -+ __le32 busy_wait_cnt; -+ __le32 flash_feature; - - __le32 erased_cw_detect_cfg_clr; - __le32 erased_cw_detect_cfg_set; -@@ -339,6 +343,7 @@ struct nandc_regs { - * - * @core_clk: controller clock - * @aon_clk: another controller clock -+ * @iomacro_clk: io macro clock - * - * @regs: a contiguous chunk of memory for DMA register - * writes. contains the register values to be -@@ -348,6 +353,7 @@ struct nandc_regs { - * initialized via DT match data - * - * @controller: base controller structure -+ * @qspi: qpic spi structure - * @host_list: list containing all the chips attached to the - * controller - * -@@ -392,6 +398,7 @@ struct qcom_nand_controller { - const struct qcom_nandc_props *props; - - struct nand_controller *controller; -+ struct qpic_spi_nand *qspi; - struct list_head host_list; - - union { diff --git a/target/linux/qualcommax/patches-6.6/0410-spi-spi-qpic-fix-broken-driver-with-SPINAND_SET_FEAT.patch b/target/linux/qualcommax/patches-6.6/0410-spi-spi-qpic-fix-broken-driver-with-SPINAND_SET_FEAT.patch deleted file mode 100644 index d39d9588d9..0000000000 --- a/target/linux/qualcommax/patches-6.6/0410-spi-spi-qpic-fix-broken-driver-with-SPINAND_SET_FEAT.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 8716f3c03d9f71ed0bd12a26f6e9d1e85cff0d12 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Thu, 30 Jan 2025 00:27:22 +0100 -Subject: [PATCH 1/2] spi: spi-qpic: fix broken driver with SPINAND_SET_FEATURE - command - -The driver always return probe error with SPINAND_SET_FEATURE command: - -spi-nand: probe of spi0.0 failed with error -1207959538 - -The error doesn't match any expected negative error but instead seems to -be an u32 converted to an int. Investigating the entire codeflow I -reached the culprit: qcom_spi_cmd_mapping. - -Such function can return -EOPNOTSUPP or the cmd to run. Problem is that -in the specific context of SPINAND_SET_FEATURE, BIT(31) is set that in -the context of an integer, it gets treated as a negative value. - -To correctly handle this, rework the function to return 0 or a "correct" -negative error and pass a pointer to store the cmd. - -Signed-off-by: Christian Marangi ---- - drivers/spi/spi-qpic-snand.c | 40 +++++++++++++++++------------------- - 1 file changed, 19 insertions(+), 21 deletions(-) - ---- a/drivers/spi/spi-qpic-snand.c -+++ b/drivers/spi/spi-qpic-snand.c -@@ -1200,64 +1200,64 @@ static int qcom_spi_program_execute(stru - return 0; - } - --static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode) -+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, -+ u32 *cmd) - { -- int cmd = 0x0; -- - switch (opcode) { - case SPINAND_RESET: -- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); -+ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); - break; - case SPINAND_READID: -- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); -+ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); - break; - case SPINAND_GET_FEATURE: -- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); -+ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); - break; - case SPINAND_SET_FEATURE: -- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | -+ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | - QPIC_SET_FEATURE); - break; - case SPINAND_READ: - if (snandc->qspi->raw_rw) { -- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | -+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | - SPI_WP | SPI_HOLD | OP_PAGE_READ); - } else { -- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | -+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | - SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); - } - - break; - case SPINAND_ERASE: -- cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | -+ *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | - SPI_HOLD | SPI_TRANSFER_MODE_x1; - break; - case SPINAND_WRITE_EN: -- cmd = SPINAND_WRITE_EN; -+ *cmd = SPINAND_WRITE_EN; - break; - case SPINAND_PROGRAM_EXECUTE: -- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | -+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | - SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); - break; - case SPINAND_PROGRAM_LOAD: -- cmd = SPINAND_PROGRAM_LOAD; -+ *cmd = SPINAND_PROGRAM_LOAD; - break; - default: - dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); - return -EOPNOTSUPP; - } - -- return cmd; -+ return 0; - } - - static int qcom_spi_write_page(struct qcom_nand_controller *snandc, - const struct spi_mem_op *op) - { -- int cmd; -+ u32 cmd; -+ int ret; - -- cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); -- if (cmd < 0) -- return cmd; -+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); -+ if (ret < 0) -+ return ret; - - if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) - snandc->qspi->data_buf = (u8 *)op->data.buf.out; -@@ -1272,12 +1272,10 @@ static int qcom_spi_send_cmdaddr(struct - u32 cmd; - int ret, opcode; - -- ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); -+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); - if (ret < 0) - return ret; - -- cmd = ret; -- - s_op.cmd_reg = cmd; - s_op.addr1_reg = op->addr.val; - s_op.addr2_reg = 0; diff --git a/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch b/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch index 6442361b0a..803933313b 100644 --- a/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch +++ b/target/linux/qualcommax/patches-6.6/0411-spi-spi-qpic-snand-support-BCH8.patch @@ -13,7 +13,7 @@ Signed-off-by: George Moussalem --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c -@@ -252,6 +252,7 @@ static int qcom_spi_ecc_init_ctx_pipelin +@@ -253,6 +253,7 @@ static int qcom_spi_ecc_init_ctx_pipelin struct nand_ecc_props *conf = &nand->ecc.ctx.conf; struct mtd_info *mtd = nanddev_to_mtd(nand); int cwperpage, bad_block_byte; @@ -21,7 +21,7 @@ Signed-off-by: George Moussalem struct qpic_ecc *ecc_cfg; cwperpage = mtd->writesize / NANDC_STEP_SIZE; -@@ -270,14 +271,17 @@ static int qcom_spi_ecc_init_ctx_pipelin +@@ -273,14 +274,17 @@ static int qcom_spi_ecc_init_ctx_pipelin nand->ecc.ctx.priv = ecc_cfg; snandc->qspi->mtd = mtd; @@ -42,7 +42,7 @@ Signed-off-by: George Moussalem ecc_cfg->step_size = 512; ecc_cfg->cw_data = 516; ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; -@@ -319,7 +323,7 @@ static int qcom_spi_ecc_init_ctx_pipelin +@@ -322,7 +326,7 @@ static int qcom_spi_ecc_init_ctx_pipelin FIELD_PREP(ECC_SW_RESET, 0) | FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) | diff --git a/target/linux/qualcommbe/Makefile b/target/linux/qualcommbe/Makefile index 05882f7c67..d796e015d7 100644 --- a/target/linux/qualcommbe/Makefile +++ b/target/linux/qualcommbe/Makefile @@ -12,8 +12,8 @@ KERNEL_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ + kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \ kmod-leds-gpio kmod-gpio-button-hotplug \ - kmod-qca-nss-dp \ wpad-openssl uboot-envtools \ e2fsprogs kmod-fs-ext4 losetup diff --git a/target/linux/qualcommbe/config-6.6 b/target/linux/qualcommbe/config-6.6 index 1c6ebf1c95..c7497b7979 100644 --- a/target/linux/qualcommbe/config-6.6 +++ b/target/linux/qualcommbe/config-6.6 @@ -395,6 +395,7 @@ CONFIG_QCOM_BAM_DMA=y # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_HFPLL is not set # CONFIG_QCOM_ICC_BWMON is not set +# CONFIG_QCOM_IPA is not set # CONFIG_QCOM_IPCC is not set # CONFIG_QCOM_LLCC is not set CONFIG_QCOM_MDT_LOADER=y diff --git a/target/linux/qualcommbe/ipq95xx/config-default b/target/linux/qualcommbe/ipq95xx/config-default index 2f05b44fa0..3ac8eaf23c 100644 --- a/target/linux/qualcommbe/ipq95xx/config-default +++ b/target/linux/qualcommbe/ipq95xx/config-default @@ -44,7 +44,6 @@ CONFIG_IPQ_CMN_PLL=y CONFIG_IPQ_NSSCC_9574=y CONFIG_IPQ_NSSCC_QCA8K=y CONFIG_QCOM_PPE=y -CONFIG_QCOM_IPA=y CONFIG_INTERCONNECT_QCOM=y CONFIG_INTERCONNECT_QCOM_OSM_L3=y CONFIG_MTD_SPI_NAND=y diff --git a/target/linux/qualcommbe/patches-6.6/020-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch b/target/linux/qualcommbe/patches-6.6/020-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch new file mode 100644 index 0000000000..453620f320 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/020-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch @@ -0,0 +1,388 @@ +From 652935ba05860eadaa19ac9efe7aea61fb7a3aef Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Wed, 17 Apr 2024 12:32:53 +0530 +Subject: [PATCH] PCI: qcom: Use devm_clk_bulk_get_all() API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is no need for the device drivers to validate the clocks defined in +Devicetree. The validation should be performed by the DT schema and the +drivers should just get all the clocks from DT. Right now the driver +hardcodes the clock info and validates them against DT which is redundant. + +So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT +and get rid of all static clocks info from the driver. This simplifies the +driver. + +Link: https://lore.kernel.org/linux-pci/20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +--- + drivers/pci/controller/dwc/pcie-qcom.c | 177 ++++++++----------------- + 1 file changed, 58 insertions(+), 119 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -151,58 +151,56 @@ + + #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) + +-#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 + struct qcom_pcie_resources_1_0_0 { +- struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control *core; + struct regulator *vdda; + }; + +-#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 + #define QCOM_PCIE_2_1_0_MAX_RESETS 6 + #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 + struct qcom_pcie_resources_2_1_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; + int num_resets; + struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + }; + +-#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 + #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 + struct qcom_pcie_resources_2_3_2 { +- struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; + }; + +-#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 + #define QCOM_PCIE_2_3_3_MAX_RESETS 7 + struct qcom_pcie_resources_2_3_3 { +- struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; + }; + +-#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 + #define QCOM_PCIE_2_4_0_MAX_RESETS 12 + struct qcom_pcie_resources_2_4_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; + int num_clks; + struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; + int num_resets; + }; + +-#define QCOM_PCIE_2_7_0_MAX_CLOCKS 15 + #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 + struct qcom_pcie_resources_2_7_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; + int num_clks; + struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; + struct reset_control *rst; + }; + +-#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 + struct qcom_pcie_resources_2_9_0 { +- struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; ++ struct clk_bulk_data *clks; ++ int num_clks; + struct reset_control *rst; + }; + +@@ -313,21 +311,11 @@ static int qcom_pcie_get_resources_2_1_0 + if (ret) + return ret; + +- res->clks[0].id = "iface"; +- res->clks[1].id = "core"; +- res->clks[2].id = "phy"; +- res->clks[3].id = "aux"; +- res->clks[4].id = "ref"; +- +- /* iface, core, phy are required */ +- ret = devm_clk_bulk_get(dev, 3, res->clks); +- if (ret < 0) +- return ret; +- +- /* aux, ref are optional */ +- ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->resets[0].id = "pci"; + res->resets[1].id = "axi"; +@@ -349,7 +337,7 @@ static void qcom_pcie_deinit_2_1_0(struc + { + struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + reset_control_bulk_assert(res->num_resets, res->resets); + + writel(1, pcie->parf + PARF_PHY_CTRL); +@@ -401,7 +389,7 @@ static int qcom_pcie_post_init_2_1_0(str + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) + return ret; + +@@ -452,20 +440,16 @@ static int qcom_pcie_get_resources_1_0_0 + struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; +- int ret; + + res->vdda = devm_regulator_get(dev, "vdda"); + if (IS_ERR(res->vdda)) + return PTR_ERR(res->vdda); + +- res->clks[0].id = "iface"; +- res->clks[1].id = "aux"; +- res->clks[2].id = "master_bus"; +- res->clks[3].id = "slave_bus"; +- +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->core = devm_reset_control_get_exclusive(dev, "core"); + return PTR_ERR_OR_ZERO(res->core); +@@ -476,7 +460,7 @@ static void qcom_pcie_deinit_1_0_0(struc + struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; + + reset_control_assert(res->core); +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + regulator_disable(res->vdda); + } + +@@ -493,7 +477,7 @@ static int qcom_pcie_init_1_0_0(struct q + return ret; + } + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_reset; +@@ -508,7 +492,7 @@ static int qcom_pcie_init_1_0_0(struct q + return 0; + + err_disable_clks: +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + err_assert_reset: + reset_control_assert(res->core); + +@@ -556,14 +540,11 @@ static int qcom_pcie_get_resources_2_3_2 + if (ret) + return ret; + +- res->clks[0].id = "aux"; +- res->clks[1].id = "cfg"; +- res->clks[2].id = "bus_master"; +- res->clks[3].id = "bus_slave"; +- +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + return 0; + } +@@ -572,7 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struc + { + struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + } + +@@ -589,7 +570,7 @@ static int qcom_pcie_init_2_3_2(struct q + return ret; + } + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); +@@ -637,17 +618,11 @@ static int qcom_pcie_get_resources_2_4_0 + bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); + int ret; + +- res->clks[0].id = "aux"; +- res->clks[1].id = "master_bus"; +- res->clks[2].id = "slave_bus"; +- res->clks[3].id = "iface"; +- +- /* qcom,pcie-ipq4019 is defined without "iface" */ +- res->num_clks = is_ipq ? 3 : 4; +- +- ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->resets[0].id = "axi_m"; + res->resets[1].id = "axi_s"; +@@ -718,15 +693,11 @@ static int qcom_pcie_get_resources_2_3_3 + struct device *dev = pci->dev; + int ret; + +- res->clks[0].id = "iface"; +- res->clks[1].id = "axi_m"; +- res->clks[2].id = "axi_s"; +- res->clks[3].id = "ahb"; +- res->clks[4].id = "aux"; +- +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->rst[0].id = "axi_m"; + res->rst[1].id = "axi_s"; +@@ -747,7 +718,7 @@ static void qcom_pcie_deinit_2_3_3(struc + { + struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + } + + static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) +@@ -777,7 +748,7 @@ static int qcom_pcie_init_2_3_3(struct q + */ + usleep_range(2000, 2500); + +- ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_resets; +@@ -838,8 +809,6 @@ static int qcom_pcie_get_resources_2_7_0 + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; +- unsigned int num_clks, num_opt_clks; +- unsigned int idx; + int ret; + + res->rst = devm_reset_control_array_get_exclusive(dev); +@@ -853,36 +822,11 @@ static int qcom_pcie_get_resources_2_7_0 + if (ret) + return ret; + +- idx = 0; +- res->clks[idx++].id = "aux"; +- res->clks[idx++].id = "cfg"; +- res->clks[idx++].id = "bus_master"; +- res->clks[idx++].id = "bus_slave"; +- res->clks[idx++].id = "slave_q2a"; +- +- num_clks = idx; +- +- ret = devm_clk_bulk_get(dev, num_clks, res->clks); +- if (ret < 0) +- return ret; +- +- res->clks[idx++].id = "tbu"; +- res->clks[idx++].id = "ddrss_sf_tbu"; +- res->clks[idx++].id = "aggre0"; +- res->clks[idx++].id = "aggre1"; +- res->clks[idx++].id = "noc_aggr"; +- res->clks[idx++].id = "noc_aggr_4"; +- res->clks[idx++].id = "noc_aggr_south_sf"; +- res->clks[idx++].id = "cnoc_qx"; +- res->clks[idx++].id = "sleep"; +- res->clks[idx++].id = "cnoc_sf_axi"; +- +- num_opt_clks = idx - num_clks; +- res->num_clks = idx; +- +- ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + return 0; + } +@@ -1073,17 +1017,12 @@ static int qcom_pcie_get_resources_2_9_0 + struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; +- int ret; +- +- res->clks[0].id = "iface"; +- res->clks[1].id = "axi_m"; +- res->clks[2].id = "axi_s"; +- res->clks[3].id = "axi_bridge"; +- res->clks[4].id = "rchng"; + +- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); +- if (ret < 0) +- return ret; ++ res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); ++ if (res->num_clks < 0) { ++ dev_err(dev, "Failed to get clocks\n"); ++ return res->num_clks; ++ } + + res->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(res->rst)) +@@ -1096,7 +1035,7 @@ static void qcom_pcie_deinit_2_9_0(struc + { + struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; + +- clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); ++ clk_bulk_disable_unprepare(res->num_clks, res->clks); + } + + static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) +@@ -1125,7 +1064,7 @@ static int qcom_pcie_init_2_9_0(struct q + + usleep_range(2000, 2500); + +- return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ++ return clk_bulk_prepare_enable(res->num_clks, res->clks); + } + + static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) diff --git a/target/linux/qualcommbe/patches-6.6/021-v6.12-PCI-qcom-Disable-mirroring-of-DBI-and-iATU-register-.patch b/target/linux/qualcommbe/patches-6.6/021-v6.12-PCI-qcom-Disable-mirroring-of-DBI-and-iATU-register-.patch new file mode 100644 index 0000000000..34b0859f24 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/021-v6.12-PCI-qcom-Disable-mirroring-of-DBI-and-iATU-register-.patch @@ -0,0 +1,277 @@ +From 10ba0854c5e6165b58e17bda5fb671e729fecf9e Mon Sep 17 00:00:00 2001 +From: Prudhvi Yarlagadda +Date: Wed, 14 Aug 2024 15:03:38 -0700 +Subject: [PATCH] PCI: qcom: Disable mirroring of DBI and iATU register space + in BAR region +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PARF hardware block which is a wrapper on top of DWC PCIe controller +mirrors the DBI and ATU register space. It uses PARF_SLV_ADDR_SPACE_SIZE +register to get the size of the memory block to be mirrored and uses +PARF_DBI_BASE_ADDR, PARF_ATU_BASE_ADDR registers to determine the base +address of DBI and ATU space inside the memory block that is being +mirrored. + +When a memory region which is located above the SLV_ADDR_SPACE_SIZE +boundary is used for BAR region then there could be an overlap of DBI and +ATU address space that is getting mirrored and the BAR region. This +results in DBI and ATU address space contents getting updated when a PCIe +function driver tries updating the BAR/MMIO memory region. Reference +memory map of the PCIe memory region with DBI and ATU address space +overlapping BAR region is as below. + + |---------------| + | | + | | + ------- --------|---------------| + | | |---------------| + | | | DBI | + | | |---------------|---->DBI_BASE_ADDR + | | | | + | | | | + | PCIe | |---->2*SLV_ADDR_SPACE_SIZE + | BAR/MMIO|---------------| + | Region | ATU | + | | |---------------|---->ATU_BASE_ADDR + | | | | + PCIe | |---------------| + Memory | | DBI | + Region | |---------------|---->DBI_BASE_ADDR + | | | | + | --------| | + | | |---->SLV_ADDR_SPACE_SIZE + | |---------------| + | | ATU | + | |---------------|---->ATU_BASE_ADDR + | | | + | |---------------| + | | DBI | + | |---------------|---->DBI_BASE_ADDR + | | | + | | | + ----------------|---------------| + | | + | | + | | + |---------------| + +Currently memory region beyond the SLV_ADDR_SPACE_SIZE boundary is not +used for BAR region which is why the above mentioned issue is not +encountered. This issue is discovered as part of internal testing when we +tried moving the BAR region beyond the SLV_ADDR_SPACE_SIZE boundary. Hence +we are trying to fix this. + +As PARF hardware block mirrors DBI and ATU register space after every +PARF_SLV_ADDR_SPACE_SIZE (default 0x1000000) boundary multiple, program +maximum possible size to this register by writing 0x80000000 to it(it +considers only powers of 2 as values) to avoid mirroring DBI and ATU to +BAR/MMIO region. Write the physical base address of DBI and ATU register +blocks to PARF_DBI_BASE_ADDR (default 0x0) and PARF_ATU_BASE_ADDR (default +0x1000) respectively to make sure DBI and ATU blocks are at expected +memory locations. + +The register offsets PARF_DBI_BASE_ADDR_V2, PARF_SLV_ADDR_SPACE_SIZE_V2 +and PARF_ATU_BASE_ADDR are applicable for platforms that use Qcom IP +rev 1.9.0, 2.7.0 and 2.9.0. PARF_DBI_BASE_ADDR_V2 and +PARF_SLV_ADDR_SPACE_SIZE_V2 are applicable for Qcom IP rev 2.3.3. +PARF_DBI_BASE_ADDR and PARF_SLV_ADDR_SPACE_SIZE are applicable for Qcom +IP rev 1.0.0, 2.3.2 and 2.4.0. Update init()/post_init() functions of the +respective Qcom IP versions to program applicable PARF_DBI_BASE_ADDR, +PARF_SLV_ADDR_SPACE_SIZE and PARF_ATU_BASE_ADDR register offsets. Update +the SLV_ADDR_SPACE_SZ macro to 0x80000000 to set highest bit in +PARF_SLV_ADDR_SPACE_SIZE register. + +Cache DBI and iATU physical addresses in 'struct dw_pcie' so that +pcie_qcom.c driver can program these addresses in the PARF_DBI_BASE_ADDR +and PARF_ATU_BASE_ADDR registers. + +Suggested-by: Manivannan Sadhasivam +Link: https://lore.kernel.org/linux-pci/20240814220338.1969668-1-quic_pyarlaga@quicinc.com +Signed-off-by: Prudhvi Yarlagadda +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Manivannan Sadhasivam +Reviewed-by: Mayank Rana +--- + drivers/pci/controller/dwc/pcie-designware.c | 2 + + drivers/pci/controller/dwc/pcie-designware.h | 2 + + drivers/pci/controller/dwc/pcie-qcom.c | 72 ++++++++++++++++---- + 3 files changed, 61 insertions(+), 15 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware.c ++++ b/drivers/pci/controller/dwc/pcie-designware.c +@@ -112,6 +112,7 @@ int dw_pcie_get_resources(struct dw_pcie + pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); ++ pci->dbi_phys_addr = res->start; + } + + /* DBI2 is mainly useful for the endpoint controller */ +@@ -134,6 +135,7 @@ int dw_pcie_get_resources(struct dw_pcie + pci->atu_base = devm_ioremap_resource(pci->dev, res); + if (IS_ERR(pci->atu_base)) + return PTR_ERR(pci->atu_base); ++ pci->atu_phys_addr = res->start; + } else { + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -384,8 +384,10 @@ struct dw_pcie_ops { + struct dw_pcie { + struct device *dev; + void __iomem *dbi_base; ++ resource_size_t dbi_phys_addr; + void __iomem *dbi_base2; + void __iomem *atu_base; ++ resource_size_t atu_phys_addr; + size_t atu_size; + u32 num_ib_windows; + u32 num_ob_windows; +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -43,6 +43,7 @@ + #define PARF_PHY_REFCLK 0x4c + #define PARF_CONFIG_BITS 0x50 + #define PARF_DBI_BASE_ADDR 0x168 ++#define PARF_SLV_ADDR_SPACE_SIZE 0x16c + #define PARF_MHI_CLOCK_RESET_CTRL 0x174 + #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 + #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +@@ -50,7 +51,12 @@ + #define PARF_LTSSM 0x1b0 + #define PARF_SID_OFFSET 0x234 + #define PARF_BDF_TRANSLATE_CFG 0x24c +-#define PARF_SLV_ADDR_SPACE_SIZE 0x358 ++#define PARF_DBI_BASE_ADDR_V2 0x350 ++#define PARF_DBI_BASE_ADDR_V2_HI 0x354 ++#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 ++#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c ++#define PARF_ATU_BASE_ADDR 0x634 ++#define PARF_ATU_BASE_ADDR_HI 0x638 + #define PARF_DEVICE_TYPE 0x1000 + #define PARF_BDF_TO_SID_TABLE_N 0x2000 + #define PARF_BDF_TO_SID_CFG 0x2c00 +@@ -105,7 +111,7 @@ + #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) + + /* PARF_SLV_ADDR_SPACE_SIZE register value */ +-#define SLV_ADDR_SPACE_SZ 0x10000000 ++#define SLV_ADDR_SPACE_SZ 0x80000000 + + /* PARF_MHI_CLOCK_RESET_CTRL register fields */ + #define AHB_CLK_EN BIT(0) +@@ -285,6 +291,50 @@ static void qcom_pcie_clear_hpc(struct d + dw_pcie_dbi_ro_wr_dis(pci); + } + ++static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) ++{ ++ struct dw_pcie *pci = pcie->pci; ++ ++ if (pci->dbi_phys_addr) { ++ /* ++ * PARF_DBI_BASE_ADDR register is in CPU domain and require to ++ * be programmed with CPU physical address. ++ */ ++ writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + ++ PARF_DBI_BASE_ADDR); ++ writel(SLV_ADDR_SPACE_SZ, pcie->parf + ++ PARF_SLV_ADDR_SPACE_SIZE); ++ } ++} ++ ++static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) ++{ ++ struct dw_pcie *pci = pcie->pci; ++ ++ if (pci->dbi_phys_addr) { ++ /* ++ * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are ++ * in CPU domain and require to be programmed with CPU ++ * physical addresses. ++ */ ++ writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + ++ PARF_DBI_BASE_ADDR_V2); ++ writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + ++ PARF_DBI_BASE_ADDR_V2_HI); ++ ++ if (pci->atu_phys_addr) { ++ writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + ++ PARF_ATU_BASE_ADDR); ++ writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + ++ PARF_ATU_BASE_ADDR_HI); ++ } ++ ++ writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); ++ writel(SLV_ADDR_SPACE_SZ, pcie->parf + ++ PARF_SLV_ADDR_SPACE_SIZE_V2_HI); ++ } ++} ++ + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) + { + u32 val; +@@ -501,8 +551,7 @@ err_assert_reset: + + static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) + { +- /* change DBI base address */ +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_base(pcie); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); +@@ -589,8 +638,7 @@ static int qcom_pcie_post_init_2_3_2(str + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- /* change DBI base address */ +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_base(pcie); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(pcie->parf + PARF_SYS_CTRL); +@@ -772,13 +820,11 @@ static int qcom_pcie_post_init_2_3_3(str + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + +- writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); +- + val = readl(pcie->parf + PARF_PHY_CTRL); + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_atu_base(pcie); + + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS + | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | +@@ -874,8 +920,7 @@ static int qcom_pcie_init_2_7_0(struct q + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- /* change DBI base address */ +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_atu_base(pcie); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(pcie->parf + PARF_SYS_CTRL); +@@ -1074,14 +1119,11 @@ static int qcom_pcie_post_init_2_9_0(str + u32 val; + int i; + +- writel(SLV_ADDR_SPACE_SZ, +- pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); +- + val = readl(pcie->parf + PARF_PHY_CTRL); + val &= ~PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + +- writel(0, pcie->parf + PARF_DBI_BASE_ADDR); ++ qcom_pcie_configure_dbi_atu_base(pcie); + + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, diff --git a/target/linux/qualcommbe/patches-6.6/022-01-v6.11-phy-qcom-qmp-Add-missing-offsets-for-Qserdes-PLL-reg.patch b/target/linux/qualcommbe/patches-6.6/022-01-v6.11-phy-qcom-qmp-Add-missing-offsets-for-Qserdes-PLL-reg.patch new file mode 100644 index 0000000000..2b9eb62897 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/022-01-v6.11-phy-qcom-qmp-Add-missing-offsets-for-Qserdes-PLL-reg.patch @@ -0,0 +1,28 @@ +From f1aaa788b997ba8a7810da0696e89fd3f79ecce3 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 16 May 2024 08:54:34 +0530 +Subject: [PATCH 1/3] phy: qcom-qmp: Add missing offsets for Qserdes PLL + registers. + +Add missing register offsets for Qserdes PLL. + +Reviewed-by: Abel Vesa +Signed-off-by: devi priya +Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h +@@ -8,6 +8,9 @@ + + /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ + #define QSERDES_PLL_BG_TIMER 0x00c ++#define QSERDES_PLL_SSC_EN_CENTER 0x010 ++#define QSERDES_PLL_SSC_ADJ_PER1 0x014 ++#define QSERDES_PLL_SSC_ADJ_PER2 0x018 + #define QSERDES_PLL_SSC_PER1 0x01c + #define QSERDES_PLL_SSC_PER2 0x020 + #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 diff --git a/target/linux/qualcommbe/patches-6.6/022-02-v6.11-phy-qcom-qmp-Add-missing-register-definitions-for-PC.patch b/target/linux/qualcommbe/patches-6.6/022-02-v6.11-phy-qcom-qmp-Add-missing-register-definitions-for-PC.patch new file mode 100644 index 0000000000..1b33695282 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/022-02-v6.11-phy-qcom-qmp-Add-missing-register-definitions-for-PC.patch @@ -0,0 +1,41 @@ +From 71ae2acf1d7542ecd21c6933cae8fe65d550074b Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 16 May 2024 08:54:35 +0530 +Subject: [PATCH 2/3] phy: qcom-qmp: Add missing register definitions for PCS + V5 + +Add missing register offsets for PCS V5 registers. + +Reviewed-by: Abel Vesa +Signed-off-by: devi priya +Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +@@ -11,8 +11,22 @@ + #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c + #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 + #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 ++#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44 ++#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48 ++#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c ++#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50 + #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88 ++#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c + #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 ++#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4 + #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 ++#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0 ++#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4 + + #endif diff --git a/target/linux/qualcommbe/patches-6.6/022-03-v6.11-phy-qcom-qmp-pcie-Add-support-for-IPQ9574-g3x1-and-g.patch b/target/linux/qualcommbe/patches-6.6/022-03-v6.11-phy-qcom-qmp-pcie-Add-support-for-IPQ9574-g3x1-and-g.patch new file mode 100644 index 0000000000..25758bac54 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/022-03-v6.11-phy-qcom-qmp-pcie-Add-support-for-IPQ9574-g3x1-and-g.patch @@ -0,0 +1,358 @@ +From 2f2f5c13cc5ea87f1dd2debfd06fe5f624e5c0fd Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 16 May 2024 08:54:36 +0530 +Subject: [PATCH 3/3] phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 + PCIEs + +Add support for a single-lane and two-lane PCIe PHYs +found on Qualcomm IPQ9574 platform. + +Reviewed-by: Abel Vesa +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Signed-off-by: devi priya +Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com +Signed-off-by: Vinod Koul +--- + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 309 +++++++++++++++++++++++ + 1 file changed, 309 insertions(+) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +@@ -514,6 +514,243 @@ static const struct qmp_phy_init_tbl ipq + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + }; + ++static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), ++ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = { ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), ++ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), ++}; ++ ++static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), ++ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), ++}; ++ + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), +@@ -2354,6 +2591,16 @@ static const struct qmp_pcie_offsets qmp + .rx2 = 0x1800, + }; + ++static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { ++ .serdes = 0, ++ .pcs = 0x1000, ++ .pcs_misc = 0x1400, ++ .tx = 0x0200, ++ .rx = 0x0400, ++ .tx2 = 0x0600, ++ .rx2 = 0x0800, ++}; ++ + static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { + .serdes = 0x1000, + .pcs = 0x1200, +@@ -2466,6 +2713,62 @@ static const struct qmp_phy_cfg ipq6018_ + .phy_status = PHYSTATUS, + }; + ++static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { ++ .lanes = 1, ++ ++ .offsets = &qmp_pcie_offsets_v4x1, ++ ++ .tbls = { ++ .serdes = ipq9574_gen3x1_pcie_serdes_tbl, ++ .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), ++ .tx = ipq8074_pcie_gen3_tx_tbl, ++ .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), ++ .rx = ipq9574_pcie_rx_tbl, ++ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), ++ .pcs = ipq9574_gen3x1_pcie_pcs_tbl, ++ .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), ++ .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, ++ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), ++ }, ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_v4_regs_layout, ++ ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ .pipe_clock_rate = 250000000, ++}; ++ ++static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = { ++ .lanes = 2, ++ ++ .offsets = &qmp_pcie_offsets_ipq9574, ++ ++ .tbls = { ++ .serdes = ipq9574_gen3x2_pcie_serdes_tbl, ++ .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), ++ .tx = ipq8074_pcie_gen3_tx_tbl, ++ .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), ++ .rx = ipq9574_pcie_rx_tbl, ++ .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), ++ .pcs = ipq9574_gen3x2_pcie_pcs_tbl, ++ .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl), ++ .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, ++ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), ++ }, ++ .reset_list = ipq8074_pciephy_reset_l, ++ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), ++ .vreg_list = NULL, ++ .num_vregs = 0, ++ .regs = pciephy_v5_regs_layout, ++ ++ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, ++ .phy_status = PHYSTATUS, ++ .pipe_clock_rate = 250000000, ++}; ++ + static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { + .lanes = 1, + +@@ -3718,6 +4021,12 @@ static const struct of_device_id qmp_pci + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, + }, { ++ .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy", ++ .data = &ipq9574_gen3x1_pciephy_cfg, ++ }, { ++ .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", ++ .data = &ipq9574_gen3x2_pciephy_cfg, ++ }, { + .compatible = "qcom,msm8998-qmp-pcie-phy", + .data = &msm8998_pciephy_cfg, + }, { diff --git a/target/linux/qualcommbe/patches-6.6/023-01-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-controller-.patch b/target/linux/qualcommbe/patches-6.6/023-01-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-controller-.patch new file mode 100644 index 0000000000..13b1d75052 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/023-01-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-controller-.patch @@ -0,0 +1,468 @@ +From d80c7fbfa908e3d893a1ea7fe178dfa82ed66bf1 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:01 +0530 +Subject: [PATCH 1/2] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller + nodes + +Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices +found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 +host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 420 +++++++++++++++++++++++++- + 1 file changed, 416 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -239,6 +239,52 @@ + reg = <0x00060000 0x6000>; + }; + ++ pcie0_phy: phy@84000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x00084000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE0_PHY_BCR>, ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie0_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@8c000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x0008c000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE2_AUX_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE2_PHY_BCR>, ++ <&gcc GCC_PCIE2PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie2_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; +@@ -268,6 +314,52 @@ + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + ++ pcie3_phy: phy@f4000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x000f4000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE3_AUX_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE3_PHY_BCR>, ++ <&gcc GCC_PCIE3PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie3_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@fc000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x000fc000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE1_PHY_BCR>, ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie1_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; +@@ -334,10 +426,10 @@ + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, +- <0>, +- <0>, +- <0>, +- <0>, ++ <&pcie0_phy>, ++ <&pcie1_phy>, ++ <&pcie2_phy>, ++ <&pcie3_phy>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -777,6 +869,326 @@ + status = "disabled"; + }; + }; ++ ++ pcie1: pcie@10000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x10000000 0xf1d>, ++ <0x10000f20 0xa8>, ++ <0x10001000 0x1000>, ++ <0x000f8000 0x4000>, ++ <0x10100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, ++ <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE1_RCHNG_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE1_PIPE_ARES>, ++ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_ARES>, ++ <&gcc GCC_PCIE1_AUX_ARES>, ++ <&gcc GCC_PCIE1_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie1_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, ++ <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie3: pcie@18000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x18000000 0xf1d>, ++ <0x18000f20 0xa8>, ++ <0x18001000 0x1000>, ++ <0x000f0000 0x4000>, ++ <0x18100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, ++ <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE3_RCHNG_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE3_PIPE_ARES>, ++ <&gcc GCC_PCIE3_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_ARES>, ++ <&gcc GCC_PCIE3_AUX_ARES>, ++ <&gcc GCC_PCIE3_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie3_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, ++ <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie2: pcie@20000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x20000000 0xf1d>, ++ <0x20000f20 0xa8>, ++ <0x20001000 0x1000>, ++ <0x00088000 0x4000>, ++ <0x20100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, ++ <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE2_RCHNG_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE2_PIPE_ARES>, ++ <&gcc GCC_PCIE2_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_ARES>, ++ <&gcc GCC_PCIE2_AUX_ARES>, ++ <&gcc GCC_PCIE2_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie2_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, ++ <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie0: pci@28000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x28000000 0xf1d>, ++ <0x28000f20 0xa8>, ++ <0x28001000 0x1000>, ++ <0x00080000 0x4000>, ++ <0x28100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, ++ <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE0_RCHNG_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE0_PIPE_ARES>, ++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_ARES>, ++ <&gcc GCC_PCIE0_AUX_ARES>, ++ <&gcc GCC_PCIE0_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie0_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, ++ <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.6/023-02-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-controll.patch b/target/linux/qualcommbe/patches-6.6/023-02-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-controll.patch new file mode 100644 index 0000000000..d7b159ae27 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/023-02-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-controll.patch @@ -0,0 +1,152 @@ +From 438d05fb9be6bcd565e713c7e8d9ffb97e5f8d1e Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:02 +0530 +Subject: [PATCH 2/2] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and + controllers + +Enable the PCIe controller and PHY nodes corresponding to RDP 433. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ + 1 file changed, 113 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -8,6 +8,7 @@ + + /dts-v1/; + ++#include + #include "ipq9574-rdp-common.dtsi" + + / { +@@ -15,6 +16,45 @@ + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + }; + ++&pcie1_phy { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-0 = <&pcie1_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ status = "okay"; ++}; ++ ++&pcie2 { ++ pinctrl-0 = <&pcie2_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie3_phy { ++ status = "okay"; ++}; ++ ++&pcie3 { ++ pinctrl-0 = <&pcie3_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ + &sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; +@@ -28,6 +68,79 @@ + }; + + &tlmm { ++ ++ pcie1_default: pcie1-default-state { ++ clkreq-n-pins { ++ pins = "gpio25"; ++ function = "pcie1_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio26"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio27"; ++ function = "pcie1_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie2_default: pcie2-default-state { ++ clkreq-n-pins { ++ pins = "gpio28"; ++ function = "pcie2_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio29"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio30"; ++ function = "pcie2_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie3_default: pcie3-default-state { ++ clkreq-n-pins { ++ pins = "gpio31"; ++ function = "pcie3_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio32"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio33"; ++ function = "pcie3_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; diff --git a/target/linux/qualcommbe/patches-6.6/024-v6.11-PCI-qcom-Add-ICC-bandwidth-vote-for-CPU-to-PCIe-path.patch b/target/linux/qualcommbe/patches-6.6/024-v6.11-PCI-qcom-Add-ICC-bandwidth-vote-for-CPU-to-PCIe-path.patch new file mode 100644 index 0000000000..65bc0bfce3 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/024-v6.11-PCI-qcom-Add-ICC-bandwidth-vote-for-CPU-to-PCIe-path.patch @@ -0,0 +1,131 @@ +From 980136d1c2b95644b96df6c7ec00ca5d7c87f37f Mon Sep 17 00:00:00 2001 +From: Krishna chaitanya chundru +Date: Wed, 19 Jun 2024 20:41:10 +0530 +Subject: [PATCH] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +To access the host controller registers of the host controller and the +endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should +be voted otherwise it may lead to NoC (Network on chip) timeout. +We are surviving because of other driver voting for this path. + +As there is less access on this path compared to PCIe to mem path +add minimum vote i.e 1KBps bandwidth always which is sufficient enough +to keep the path active and is recommended by HW team. + +During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while +disabling the boot CPU). So do not disable the CPU-PCIe interconnect path +during S2RAM as that may lead to NoC error. + +Link: https://lore.kernel.org/linux-pci/20240619-opp_support-v15-1-aa769a2173a3@quicinc.com +Signed-off-by: Krishna chaitanya chundru +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +Reviewed-by: Bryan O'Donoghue +Reviewed-by: Manivannan Sadhasivam +--- + drivers/pci/controller/dwc/pcie-qcom.c | 45 +++++++++++++++++++++++++++++++--- + 1 file changed, 41 insertions(+), 4 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -245,6 +245,7 @@ struct qcom_pcie { + struct phy *phy; + struct gpio_desc *reset; + struct icc_path *icc_mem; ++ struct icc_path *icc_cpu; + const struct qcom_pcie_cfg *cfg; + struct dentry *debugfs; + bool suspended; +@@ -1357,6 +1358,9 @@ static int qcom_pcie_icc_init(struct qco + if (IS_ERR(pcie->icc_mem)) + return PTR_ERR(pcie->icc_mem); + ++ pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); ++ if (IS_ERR(pcie->icc_cpu)) ++ return PTR_ERR(pcie->icc_cpu); + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. +@@ -1366,11 +1370,25 @@ static int qcom_pcie_icc_init(struct qco + */ + ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); + if (ret) { +- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ++ dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + ++ /* ++ * Since the CPU-PCIe path is only used for activities like register ++ * access of the host controller and endpoint Config/BAR space access, ++ * HW team has recommended to use a minimal bandwidth of 1KBps just to ++ * keep the path active. ++ */ ++ ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); ++ if (ret) { ++ dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", ++ ret); ++ icc_set_bw(pcie->icc_mem, 0, 0); ++ return ret; ++ } ++ + return 0; + } + +@@ -1411,7 +1429,7 @@ static void qcom_pcie_icc_update(struct + + ret = icc_set_bw(pcie->icc_mem, 0, width * bw); + if (ret) { +- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ++ dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + } + } +@@ -1573,7 +1591,7 @@ static int qcom_pcie_suspend_noirq(struc + */ + ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + if (ret) { +- dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); ++ dev_err(dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); + return ret; + } + +@@ -1597,7 +1615,18 @@ static int qcom_pcie_suspend_noirq(struc + pcie->suspended = true; + } + +- return 0; ++ /* ++ * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. ++ * Because on some platforms, DBI access can happen very late during the ++ * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC ++ * error. ++ */ ++ if (pm_suspend_target_state != PM_SUSPEND_MEM) { ++ ret = icc_disable(pcie->icc_cpu); ++ if (ret) ++ dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); ++ } ++ return ret; + } + + static int qcom_pcie_resume_noirq(struct device *dev) +@@ -1605,6 +1634,14 @@ static int qcom_pcie_resume_noirq(struct + struct qcom_pcie *pcie = dev_get_drvdata(dev); + int ret; + ++ if (pm_suspend_target_state != PM_SUSPEND_MEM) { ++ ret = icc_enable(pcie->icc_cpu); ++ if (ret) { ++ dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); ++ return ret; ++ } ++ } ++ + if (pcie->suspended) { + ret = qcom_pcie_host_init(&pcie->pci->pp); + if (ret) diff --git a/target/linux/qualcommbe/patches-6.6/025-v6.15-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch b/target/linux/qualcommbe/patches-6.6/025-v6.15-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch new file mode 100644 index 0000000000..2407301d9e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/025-v6.15-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch @@ -0,0 +1,44 @@ +From c87d58bc7f831bf3d887e6ec846246cb673c2e50 Mon Sep 17 00:00:00 2001 +From: Manikanta Mylavarapu +Date: Thu, 13 Mar 2025 12:44:22 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of + pcie3 + +The MSI interrupt numbers of the PCIe3 controller are incorrect. Due +to this, the functional bring up of the QDSP6 processor on the PCIe +endpoint has failed. Correct the MSI interrupt numbers to properly +bring up the QDSP6 processor on the PCIe endpoint. + +Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes") +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313071422.510-1-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -968,14 +968,14 @@ + ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; + +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; + interrupt-names = "msi0", + "msi1", + "msi2", diff --git a/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch b/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch index 0b8eac37cb..46e64a1e01 100644 --- a/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch +++ b/target/linux/qualcommbe/patches-6.6/101-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch @@ -1,13 +1,40 @@ -From 968c5e8220209eb2185654f01748c349515a3b8e Mon Sep 17 00:00:00 2001 From: Md Sadre Alam -Date: Thu, 15 Feb 2024 12:26:40 +0530 -Subject: [PATCH v10 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support +To: , , , + , , + , , + , , + , + , , + , , + +Cc: , , + +Subject: [PATCH v14 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support +Date: Wed, 20 Nov 2024 14:45:05 +0530 [thread overview] +Message-ID: <20241120091507.1404368-8-quic_mdalam@quicinc.com> (raw) +In-Reply-To: <20241120091507.1404368-1-quic_mdalam@quicinc.com> Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam --- +Change in [v14] + +* No change + +Change in [v13] + +* No change + +Change in [v12] + +* No change + +Change in [v11] + +* No change + Change in [v10] * No change @@ -54,11 +81,11 @@ Change in [v1] arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ 2 files changed, 70 insertions(+) ---- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -59,4 +59,47 @@ - bias-pull-down; - }; +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -95,6 +95,49 @@ + drive-strength = <8>; + bias-disable; }; + + qpic_snand_default_state: qpic-snand-default-state { @@ -104,9 +131,11 @@ Change in [v1] + nand-ecc-step-size = <512>; + }; }; + + &usb_0_dwc3 { --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -355,6 +355,33 @@ +@@ -447,6 +447,33 @@ reg = <0x01937000 0x21000>; }; @@ -122,7 +151,7 @@ Change in [v1] + }; + + qpic_nand: spi@79b0000 { -+ compatible = "qcom,spi-qpic-snand", "qcom,ipq9574-nand"; ++ compatible = "qcom,ipq9574-snand"; + reg = <0x79b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch b/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch index 8e362b8e60..d54dc4cf99 100644 --- a/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch +++ b/target/linux/qualcommbe/patches-6.6/102-arm64-dts-qcom-ipq9574-Disable-eMMC-node.patch @@ -54,7 +54,7 @@ Change in [v1] --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -24,7 +24,7 @@ +@@ -64,7 +64,7 @@ mmc-hs400-enhanced-strobe; max-frequency = <384000000>; bus-width = <8>; diff --git a/target/linux/qualcommbe/patches-6.6/105-05-clk-qcom-Add-NSS-clock-Controller-driver-for-IPQ9574.patch b/target/linux/qualcommbe/patches-6.6/105-05-clk-qcom-Add-NSS-clock-Controller-driver-for-IPQ9574.patch index f4111456d4..6ec7057ae4 100644 --- a/target/linux/qualcommbe/patches-6.6/105-05-clk-qcom-Add-NSS-clock-Controller-driver-for-IPQ9574.patch +++ b/target/linux/qualcommbe/patches-6.6/105-05-clk-qcom-Add-NSS-clock-Controller-driver-for-IPQ9574.patch @@ -3118,7 +3118,7 @@ Signed-off-by: Manikanta Mylavarapu + .driver = { + .name = "qcom,nsscc-ipq9574", + .of_match_table = nss_cc_ipq9574_match_table, -+ .sync_state = icc_sync_state, /* TODO seems to cause hang */ ++ .sync_state = icc_sync_state, + }, +}; + diff --git a/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch b/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch index fd5ed0504b..9aba070e63 100644 --- a/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch +++ b/target/linux/qualcommbe/patches-6.6/105-06-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch @@ -22,11 +22,10 @@ Signed-off-by: Manikanta Mylavarapu #include / { -@@ -804,6 +806,26 @@ - status = "disabled"; - }; +@@ -1216,6 +1218,25 @@ + status = "disabled"; }; -+ + + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; diff --git a/target/linux/qualcommbe/patches-6.6/106-arm64-dts-qcom-fix-USB-vdda-pll-supply-for-ipq9574-r.patch b/target/linux/qualcommbe/patches-6.6/106-arm64-dts-qcom-fix-USB-vdda-pll-supply-for-ipq9574-r.patch index 0f36d32cfa..25f9a1b7ab 100644 --- a/target/linux/qualcommbe/patches-6.6/106-arm64-dts-qcom-fix-USB-vdda-pll-supply-for-ipq9574-r.patch +++ b/target/linux/qualcommbe/patches-6.6/106-arm64-dts-qcom-fix-USB-vdda-pll-supply-for-ipq9574-r.patch @@ -24,7 +24,7 @@ Signed-off-by: Christian Marangi regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; -@@ -102,7 +102,7 @@ +@@ -145,7 +145,7 @@ }; &usb_0_qmpphy { @@ -33,7 +33,7 @@ Signed-off-by: Christian Marangi vdda-phy-supply = <®ulator_fixed_0p925>; status = "okay"; -@@ -110,7 +110,7 @@ +@@ -153,7 +153,7 @@ &usb_0_qusbphy { vdd-supply = <®ulator_fixed_0p925>; diff --git a/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch b/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch index c020957aa7..6867024ec1 100644 --- a/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch +++ b/target/linux/qualcommbe/patches-6.6/200-01-arm64-dts-qcom-ipq9574-Add-PCS-UNIPHY-device-tree-su.patch @@ -30,7 +30,7 @@ Signed-off-by: Lei Wei */ #include -@@ -826,6 +826,114 @@ +@@ -1237,6 +1237,114 @@ #power-domain-cells = <1>; #interconnect-cells = <1>; }; diff --git a/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch b/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch index ff16521d91..edfc1f6497 100644 --- a/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch +++ b/target/linux/qualcommbe/patches-6.6/200-02-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Luo Jie --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -251,6 +251,8 @@ +@@ -297,6 +297,8 @@ mdio: mdio@90000 { compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; reg = <0x00090000 0x64>; @@ -24,7 +24,7 @@ Signed-off-by: Luo Jie #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_MDIO_AHB_CLK>; -@@ -322,6 +324,22 @@ +@@ -414,6 +416,22 @@ interrupt-controller; #interrupt-cells = <2>; diff --git a/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch b/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch index f33bb0ebdd..3cad4008a9 100644 --- a/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch +++ b/target/linux/qualcommbe/patches-6.6/200-03-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch @@ -15,11 +15,10 @@ Signed-off-by: Luo Jie --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -952,6 +952,44 @@ - "ch_tx"; - }; +@@ -1256,6 +1256,44 @@ + #interconnect-cells = <1>; }; -+ + + ethernet@3a000000 { + compatible = "qcom,ipq9574-ppe"; + reg = <0x3a000000 0xbef800>; @@ -57,6 +56,7 @@ Signed-off-by: Luo Jie + "memnoc_nssnoc", + "memnoc_nssnoc_1"; + }; - }; - - thermal-zones { ++ + pcsuniphy0: ethernet-uniphy@7a00000 { + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch b/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch index 8c3a0ac6e4..b024a37e6b 100644 --- a/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch +++ b/target/linux/qualcommbe/patches-6.6/200-04-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch @@ -14,7 +14,7 @@ Signed-off-by: Pavithra R --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -989,6 +989,74 @@ +@@ -1292,6 +1292,74 @@ "nssnoc_memnoc", "memnoc_nssnoc", "memnoc_nssnoc_1"; @@ -87,5 +87,5 @@ Signed-off-by: Pavithra R + "edma_misc"; + }; }; - }; + pcsuniphy0: ethernet-uniphy@7a00000 { diff --git a/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch b/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch index d48b34293d..2ea431850e 100644 --- a/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch +++ b/target/linux/qualcommbe/patches-6.6/200-05-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch @@ -18,23 +18,8 @@ Signed-off-by: Lei Wei --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -3,11 +3,13 @@ - * IPQ9574 RDP433 board device tree source - * - * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. -- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. -+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - - /dts-v1/; - -+#include -+ - #include "ipq9574-rdp-common.dtsi" - - / { -@@ -15,6 +17,46 @@ - compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; +@@ -55,6 +55,46 @@ + status = "okay"; }; +&mdio { @@ -80,8 +65,8 @@ Signed-off-by: Lei Wei &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; -@@ -103,3 +145,130 @@ - nand-ecc-step-size = <512>; +@@ -173,3 +213,130 @@ + }; }; }; + @@ -213,8 +198,8 @@ Signed-off-by: Lei Wei +}; --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi -@@ -953,7 +953,7 @@ - }; +@@ -1256,7 +1256,7 @@ + #interconnect-cells = <1>; }; - ethernet@3a000000 { diff --git a/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch b/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch index c7b7ea14b6..f0d89d96e6 100644 --- a/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch +++ b/target/linux/qualcommbe/patches-6.6/302-arm64-dts-qcom-Add-missing-clock-for-nsscc-from-pcs-.patch @@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi #include / { -@@ -832,12 +833,12 @@ +@@ -1243,12 +1244,12 @@ <&cmn_pll NSS_1200MHZ_CLK>, <&cmn_pll PPE_353MHZ_CLK>, <&gcc GPLL0_OUT_AUX>, diff --git a/target/linux/qualcommbe/patches-6.6/303-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch b/target/linux/qualcommbe/patches-6.6/303-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch index 526d559e34..c45cc9811c 100644 --- a/target/linux/qualcommbe/patches-6.6/303-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch +++ b/target/linux/qualcommbe/patches-6.6/303-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch @@ -104,7 +104,7 @@ Signed-off-by: Christian Marangi + partition@4d0000 { + label = "0:rpm"; + reg = <0x4d0000 0x20000>; -+ // read-only; ++ read-only; + }; + + partition@4f0000 { diff --git a/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch b/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch index 4de13b73ab..f897bc8992 100644 --- a/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch +++ b/target/linux/qualcommbe/patches-6.6/304-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433-board.patch @@ -13,7 +13,7 @@ Signed-off-by: Christian Marangi --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -49,11 +49,17 @@ +@@ -87,11 +87,17 @@ phy4: ethernet-phy@8 { compatible ="ethernet-phy-ieee802.3-c45"; reg = <8>; diff --git a/target/linux/qualcommbe/patches-6.6/307-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch b/target/linux/qualcommbe/patches-6.6/307-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch new file mode 100644 index 0000000000..b938a2ba07 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/307-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch @@ -0,0 +1,50 @@ +From 2f328bd852cbb27cf0d2cad1727d8fb7a69abe87 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 00:39:30 +0100 +Subject: [PATCH 2/2] arm64: dts: qcom: ipq9574: add QPIC SPI NAND default + partition nodes + +Add QPIC SPI NAND default partition nodes for RDP reference board. + +Signed-off-by: Christian Marangi +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -281,6 +281,34 @@ + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "0:training"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "0:license"; ++ reg = <0x80000 0x40000>; ++ read-only; ++ }; ++ ++ partition@c0000 { ++ label = "rootfs"; ++ reg = <0xc0000 0x3c00000>; ++ }; ++ ++ partition@3cc0000 { ++ label = "rootfs_1"; ++ reg = <0x3cc0000 0x3c00000>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/qualcommbe/patches-6.6/308-01-PM-runtime-add-of_pm_clk_add_clk_index-OP-variant.patch b/target/linux/qualcommbe/patches-6.6/308-01-PM-runtime-add-of_pm_clk_add_clk_index-OP-variant.patch new file mode 100644 index 0000000000..c2c2a48e62 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/308-01-PM-runtime-add-of_pm_clk_add_clk_index-OP-variant.patch @@ -0,0 +1,66 @@ +From afba5111aed03a05aa7fd46d3d9911319fa87a29 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 16:07:14 +0100 +Subject: [PATCH 1/3] PM: runtime: add of_pm_clk_add_clk_index OP variant + +Add of_pm_clk_add_clk_index OP variant of of_pm_clk_add_clk to take as +argument the clock index in DT instead of the name. This is to handle +case where clock-names property is not used by the node but clocks are +referenced with a dt-binding header or internally in the driver. + +Signed-off-by: Christian Marangi +--- + drivers/base/power/clock_ops.c | 31 +++++++++++++++++++++++++++++++ + include/linux/pm_clock.h | 1 + + 2 files changed, 32 insertions(+) + +--- a/drivers/base/power/clock_ops.c ++++ b/drivers/base/power/clock_ops.c +@@ -259,6 +259,37 @@ int pm_clk_add_clk(struct device *dev, s + } + EXPORT_SYMBOL_GPL(pm_clk_add_clk); + ++/** ++ * of_pm_clk_add_clk_index - Start using a device clock for power management. ++ * @dev: Device whose clock is going to be used for power management. ++ * @index: Index of clock that is going to be used for power management. ++ * ++ * Add the clock described in the 'clocks' device-tree node at the index ++ * provided, to the list of clocks used for the power management of @dev. ++ * On success, returns 0. Returns a negative error code if the clock is not ++ * found or cannot be added. ++ */ ++int of_pm_clk_add_clk_index(struct device *dev, int index) ++{ ++ struct clk *clk; ++ int ret; ++ ++ if (!dev || !dev->of_node || index < 0) ++ return -EINVAL; ++ ++ clk = of_clk_get(dev->of_node, index); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ ret = pm_clk_add_clk(dev, clk); ++ if (ret) { ++ clk_put(clk); ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(of_pm_clk_add_clk_index); + + /** + * of_pm_clk_add_clk - Start using a device clock for power management. +--- a/include/linux/pm_clock.h ++++ b/include/linux/pm_clock.h +@@ -41,6 +41,7 @@ extern int pm_clk_create(struct device * + extern void pm_clk_destroy(struct device *dev); + extern int pm_clk_add(struct device *dev, const char *con_id); + extern int pm_clk_add_clk(struct device *dev, struct clk *clk); ++extern int of_pm_clk_add_clk_index(struct device *dev, int index); + extern int of_pm_clk_add_clk(struct device *dev, const char *name); + extern int of_pm_clk_add_clks(struct device *dev); + extern void pm_clk_remove(struct device *dev, const char *con_id); diff --git a/target/linux/qualcommbe/patches-6.6/308-02-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch b/target/linux/qualcommbe/patches-6.6/308-02-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch new file mode 100644 index 0000000000..6750fdb2ef --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/308-02-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch @@ -0,0 +1,120 @@ +From 9408076fd9e4d41876af41523cad9bfa77b3a557 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 16:11:14 +0100 +Subject: [PATCH 2/3] clk: qcom: nsscc: Attach required NSSNOC clock to PM + domain + +There is currently a problem with ICC clock disabling the NSSNOC clock +as there isn't any user for them on calling sync_state. +This cause the kernel to stall if NSS is enabled and reboot with the watchdog. + +This is caused by the fact that the NSSNOC clock nsscc, snoc and snoc_1 +are actually required to make the NSS work and make the system continue +booting. + +To attach these clock, setup pm-clk in nsscc and setup the correct +resume/suspend OPs. + +With this change, the clock gets correctly attached and are not disabled +when ICC call the sync_state. + +Suggested-by: Dmitry Baryshkov +Signed-off-by: Christian Marangi +--- + drivers/clk/qcom/nsscc-ipq9574.c | 49 +++++++++++++++++++++++++++++++- + 1 file changed, 48 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/nsscc-ipq9574.c ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + +@@ -41,6 +43,9 @@ enum { + DT_UNIPHY1_NSS_TX_CLK, + DT_UNIPHY2_NSS_RX_CLK, + DT_UNIPHY2_NSS_TX_CLK, ++ DT_GCC_NSSNOC_NSSCC_CLK, ++ DT_GCC_NSSNOC_SNOC_CLK, ++ DT_GCC_NSSNOC_SNOC_1_CLK, + }; + + enum { +@@ -3046,6 +3051,10 @@ static const struct qcom_cc_desc nss_cc_ + .icc_first_node_id = IPQ_NSSCC_ID, + }; + ++static const struct dev_pm_ops nsscc_pm_ops = { ++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) ++}; ++ + static const struct of_device_id nss_cc_ipq9574_match_table[] = { + { .compatible = "qcom,ipq9574-nsscc" }, + { } +@@ -3054,7 +3063,33 @@ MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_m + + static int nss_cc_ipq9574_probe(struct platform_device *pdev) + { ++ struct device *dev = &pdev->dev; + struct regmap *regmap; ++ int ret; ++ ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ return ret; ++ ++ ret = devm_pm_clk_create(dev); ++ if (ret) ++ return ret; ++ ++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_NSSCC_CLK); ++ if (ret) ++ return dev_err_probe(dev, ret,"failed to acquire nssnoc clock\n"); ++ ++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_SNOC_CLK); ++ if (ret) ++ return dev_err_probe(dev, ret,"failed to acquire snoc clock\n"); ++ ++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_SNOC_1_CLK); ++ if (ret) ++ return dev_err_probe(dev, ret,"failed to acquire snoc_1 clock\n"); ++ ++ ret = pm_runtime_resume_and_get(dev); ++ if (ret) ++ return ret; + + regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc); + if (IS_ERR(regmap)) +@@ -3062,7 +3097,18 @@ static int nss_cc_ipq9574_probe(struct p + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + +- return qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap); ++ ret = qcom_cc_really_probe(dev, &nss_cc_ipq9574_desc, regmap); ++ if (ret) ++ goto err_put_pm; ++ ++ pm_runtime_put(dev); ++ ++ return 0; ++ ++err_put_pm: ++ pm_runtime_put_sync(dev); ++ ++ return ret; + } + + static struct platform_driver nss_cc_ipq9574_driver = { +@@ -3071,6 +3117,7 @@ static struct platform_driver nss_cc_ipq + .name = "qcom,nsscc-ipq9574", + .of_match_table = nss_cc_ipq9574_match_table, + .sync_state = icc_sync_state, ++ .pm = &nsscc_pm_ops, + }, + }; + diff --git a/target/linux/qualcommbe/patches-6.6/308-03-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch b/target/linux/qualcommbe/patches-6.6/308-03-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch new file mode 100644 index 0000000000..d2c3e500c4 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/308-03-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch @@ -0,0 +1,26 @@ +From 893fda72edd2a0b3d92be41af417d315c9c5c253 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 16:23:03 +0100 +Subject: [PATCH 3/3] arm64: dts: qcom: ipq9574: add NSSNOC clock to nss node + +Add NSSNOC clock to nss node to attach the clock with PM clock and fix +the boot stall after ICC sync_state. + +Signed-off-by: Christian Marangi +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -1250,7 +1250,9 @@ + <&pcsuniphy1 UNIPHY_NSS_TX_CLK>, + <&pcsuniphy2 UNIPHY_NSS_RX_CLK>, + <&pcsuniphy2 UNIPHY_NSS_TX_CLK>, +- <&gcc GCC_NSSCC_CLK>; ++ <&gcc GCC_NSSNOC_NSSCC_CLK>, ++ <&gcc GCC_NSSNOC_SNOC_CLK>, ++ <&gcc GCC_NSSNOC_SNOC_1_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; diff --git a/target/linux/qualcommbe/patches-6.6/309-clk-qcom-nsscc-ipq9574-enable-bus-clock.patch b/target/linux/qualcommbe/patches-6.6/309-clk-qcom-nsscc-ipq9574-enable-bus-clock.patch new file mode 100644 index 0000000000..b8bc466fa1 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/309-clk-qcom-nsscc-ipq9574-enable-bus-clock.patch @@ -0,0 +1,46 @@ +From 145aa2977a42b97d052ed0984fb305a853f55d49 Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Wed, 11 Apr 2025 15:14:19 +0300 +Subject: [PATCH] clk: qcom: nsscc-ipq9574: enable bus clock + +Enable bus clock, otherwise nsscc registers are unaccessible. + +Signed-off-by: Mantas Pucka +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 +- + drivers/clk/qcom/nsscc-ipq9574.c | 5 + + 2 file changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -1252,7 +1252,8 @@ + <&pcsuniphy2 UNIPHY_NSS_TX_CLK>, + <&gcc GCC_NSSNOC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, +- <&gcc GCC_NSSNOC_SNOC_1_CLK>; ++ <&gcc GCC_NSSNOC_SNOC_1_CLK>, ++ <&gcc GCC_NSSCC_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; +--- a/drivers/clk/qcom/nsscc-ipq9574.c ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -46,6 +46,7 @@ enum { + DT_GCC_NSSNOC_NSSCC_CLK, + DT_GCC_NSSNOC_SNOC_CLK, + DT_GCC_NSSNOC_SNOC_1_CLK, ++ DT_GCC_NSS_BUS_CLK, + }; + + enum { +@@ -3075,6 +3076,10 @@ static int nss_cc_ipq9574_probe(struct p + if (ret) + return ret; + ++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSS_BUS_CLK); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n"); ++ + ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_NSSCC_CLK); + if (ret) + return dev_err_probe(dev, ret,"failed to acquire nssnoc clock\n"); diff --git a/target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch b/target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch new file mode 100644 index 0000000000..ac846284bf --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch @@ -0,0 +1,46 @@ +From ce4c7eea1b6f05723240aadc5e1c240d26a6ef88 Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Mon, 31 Mar 2025 15:39:59 +0300 +Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config + +Currently there is no configuration to derive 25/125MHz port5 clock +from uniphy1 running at 125MHz. This is needed for SGMII mode when +port5 is using uniphy1. + +Fix this by adding option such clock config option. + +Signed-off-by: Mantas Pucka +--- + drivers/clk/qcom/nsscc-ipq9574.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/clk/qcom/nsscc-ipq9574.c ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -387,11 +387,13 @@ static const struct freq_multi_tbl ftbl_ + + static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), + }; + + static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + }; + +@@ -412,11 +414,13 @@ static const struct freq_multi_tbl ftbl_ + + static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), + }; + + static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + }; + diff --git a/target/linux/qualcommbe/patches-6.6/700-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch b/target/linux/qualcommbe/patches-6.6/700-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch new file mode 100644 index 0000000000..8ba365e7cf --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/700-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch @@ -0,0 +1,48 @@ +From 4c432babdc195a0dbef70ca67c92cec8adf01e30 Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Fri, 28 Mar 2025 14:22:21 +0200 +Subject: [PATCH 5/6] net: pcs: ipq-uniphy: keep autoneg enabled in SGMII mode + +For PHYs that don't use in-band-status (e.g. 2.5G PHY swiching between +SGMII and 2500base-x), SGMII autoneg still must be enabled. Only mode +that should use forced speed is 1000base-x + +Signed-off-by: Mantas Pucka +--- + drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c ++++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c +@@ -520,7 +520,7 @@ static int ipq_unipcs_config_sgmii(struc + mutex_unlock(&qunipcs->shared_lock); + + /* In-band autoneg mode is enabled by default for each PCS channel */ +- if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) ++ if (interface != PHY_INTERFACE_MODE_1000BASEX) + return 0; + + /* Force speed mode */ +@@ -758,10 +758,11 @@ ipq_unipcs_link_up_clock_rate_set(struct + static void ipq_unipcs_link_up_config_sgmii(struct ipq_uniphy_pcs *qunipcs, + int channel, + unsigned int neg_mode, +- int speed) ++ int speed, ++ phy_interface_t interface) + { + /* No need to config PCS speed if in-band autoneg is enabled */ +- if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) ++ if (interface != PHY_INTERFACE_MODE_1000BASEX) + goto pcs_adapter_reset; + + /* PCS speed set for force mode */ +@@ -966,7 +967,7 @@ static void ipq_unipcs_link_up(struct ph + case PHY_INTERFACE_MODE_PSGMII: + case PHY_INTERFACE_MODE_1000BASEX: + ipq_unipcs_link_up_config_sgmii(qunipcs, channel, +- neg_mode, speed); ++ neg_mode, speed, interface); + break; + case PHY_INTERFACE_MODE_2500BASEX: + ipq_unipcs_link_up_config_2500basex(qunipcs, diff --git a/target/linux/qualcommbe/patches-6.6/701-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch b/target/linux/qualcommbe/patches-6.6/701-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch new file mode 100644 index 0000000000..8430127566 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/701-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch @@ -0,0 +1,64 @@ +From 3bbf1aad312de653b894c2e60ea1b37ce912c6fe Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Fri, 28 Mar 2025 14:10:22 +0200 +Subject: [PATCH 3/6] net: pcs: ipq-uniphy: control MISC2 register for 2.5G + support + +When 2500base-x mode is enabled MISC2 regsister needs to have different +value than for other 1G modes. + +Signed-off-by: Mantas Pucka +--- + drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c ++++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c +@@ -20,6 +20,11 @@ + #define PCS_CALIBRATION 0x1e0 + #define PCS_CALIBRATION_DONE BIT(7) + ++#define PCS_MISC2 0x218 ++#define PCS_MISC2_MODE_MASK GENMASK(6, 5) ++#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1) ++#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2) ++ + #define PCS_MODE_CTRL 0x46c + #define PCS_MODE_SEL_MASK GENMASK(12, 8) + #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) +@@ -422,6 +427,9 @@ static int ipq_unipcs_config_mode(struct + ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL, + PCS_MODE_SEL_MASK | PCS_MODE_AN_MODE, + PCS_MODE_SGMII); ++ ipq_unipcs_reg_modify32(qunipcs, PCS_MISC2, ++ PCS_MISC2_MODE_MASK, ++ PCS_MISC2_MODE_SGMII); + break; + case PHY_INTERFACE_MODE_QSGMII: + rate = 125000000; +@@ -438,17 +446,25 @@ static int ipq_unipcs_config_mode(struct + PCS_MODE_PSGMII); + break; + case PHY_INTERFACE_MODE_1000BASEX: ++ rate = 125000000; + ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL, + PCS_MODE_SEL_MASK | + PCS_MODE_SGMII_CTRL_MASK, + PCS_MODE_SGMII | + PCS_MODE_SGMII_CTRL_1000BASEX); ++ ipq_unipcs_reg_modify32(qunipcs, PCS_MISC2, ++ PCS_MISC2_MODE_MASK, ++ PCS_MISC2_MODE_SGMII); + break; + case PHY_INTERFACE_MODE_2500BASEX: + rate = 312500000; + ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL, + PCS_MODE_SEL_MASK, + PCS_MODE_SGMII_PLUS); ++ ipq_unipcs_reg_modify32(qunipcs, PCS_MISC2, ++ PCS_MISC2_MODE_MASK, ++ PCS_MISC2_MODE_SGMII_PLUS); ++ + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: diff --git a/target/linux/qualcommbe/patches-6.6/702-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch b/target/linux/qualcommbe/patches-6.6/702-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch new file mode 100644 index 0000000000..46a1b5f847 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/702-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch @@ -0,0 +1,24 @@ +From d75aa2977a42b97d052ed0984fb305a853f55d49 Mon Sep 17 00:00:00 2001 +From: Mantas Pucka +Date: Wed, 9 Apr 2025 11:16:49 +0300 +Subject: [PATCH] net: pcs: ipq-uniphy: fix USXGMII link-up failure + +USXGMII link-up may fail due to too short delay after PLL reset. +Increase the delay to fix this. + +Signed-off-by: Mantas Pucka +--- + drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c ++++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c +@@ -490,7 +490,7 @@ static int ipq_unipcs_config_mode(struct + + /* PCS PLL reset */ + ipq_unipcs_reg_modify32(qunipcs, PCS_PLL_RESET, PCS_ANA_SW_RESET, 0); +- fsleep(10000); ++ fsleep(20000); + ipq_unipcs_reg_modify32(qunipcs, PCS_PLL_RESET, + PCS_ANA_SW_RESET, PCS_ANA_SW_RESET); + diff --git a/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch b/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch index f8c95d28d6..3a1bf5a651 100644 --- a/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch +++ b/target/linux/qualcommbe/patches-6.6/900-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch @@ -12,7 +12,7 @@ Signed-off-by: Christian Marangi --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts -@@ -161,6 +161,7 @@ +@@ -229,6 +229,7 @@ reg = <1>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy0>; pcs-handle = <&pcsuniphy0_ch0>; clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, -@@ -181,6 +182,7 @@ +@@ -249,6 +250,7 @@ reg = <2>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -28,7 +28,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy1>; pcs-handle = <&pcsuniphy0_ch1>; clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, -@@ -201,6 +203,7 @@ +@@ -269,6 +271,7 @@ reg = <3>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -36,7 +36,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy2>; pcs-handle = <&pcsuniphy0_ch2>; clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, -@@ -221,6 +224,7 @@ +@@ -289,6 +292,7 @@ reg = <4>; phy-mode = "qsgmii"; managed = "in-band-status"; @@ -44,7 +44,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy3>; pcs-handle = <&pcsuniphy0_ch3>; clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, -@@ -241,6 +245,7 @@ +@@ -309,6 +313,7 @@ reg = <5>; phy-mode = "usxgmii"; managed = "in-band-status"; @@ -52,7 +52,7 @@ Signed-off-by: Christian Marangi phy-handle = <&phy4>; pcs-handle = <&pcsuniphy1_ch0>; clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, -@@ -261,6 +266,7 @@ +@@ -329,6 +334,7 @@ reg = <6>; phy-mode = "usxgmii"; managed = "in-band-status"; diff --git a/target/linux/ramips/dts/mt7628an_mercusys_mb130-4g-v1.dts b/target/linux/ramips/dts/mt7628an_mercusys_mb130-4g-v1.dts new file mode 100644 index 0000000000..053de48d79 --- /dev/null +++ b/target/linux/ramips/dts/mt7628an_mercusys_mb130-4g-v1.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7628an.dtsi" + +#include +#include +#include + +/ { + compatible = "mercusys,mb130-4g-v1", "mediatek,mt7628an-soc"; + model = "MERCUSYS MB130-4G v1"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + label-mac-device = ðernet; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + leds { + compatible = "gpio-leds"; + + wan { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + }; + + lan { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + }; + + led_power: power { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + }; + + wps { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&gpio 40 GPIO_ACTIVE_LOW>; + }; + + signal1 { + label = "green:signal1"; + gpios = <&gpio 41 GPIO_ACTIVE_LOW>; + }; + + signal2 { + label = "green:signal2"; + gpios = <&gpio 42 GPIO_ACTIVE_LOW>; + }; + + signal3 { + label = "green:signal3"; + gpios = <&gpio 43 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 38 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + rfkill { + label = "rfkill"; + gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio_export { + compatible = "gpio-export"; + + out_atn { + gpio-export,name = "out_atn"; + gpio-export,output = <0>; + gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + }; + + usb_power { + gpio-export,name = "usb_power"; + gpio-export,output = <1>; + gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; + }; + + usb_boot { + gpio-export,name = "usb_boot"; + gpio-export,output = <0>; + gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + }; + + usb_reset { + gpio-export,name = "usb_reset"; + gpio-export,output = <0>; + gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + compatible = "tplink,firmware"; + label = "firmware"; + reg = <0x20000 0xe90000>; + }; + + partition@eb0000 { + label = "ispconfig"; + reg = <0xeb0000 0x10000>; + read-only; + }; + + partition@ec0000 { + label = "romfile"; + reg = <0xec0000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_romfile_f100: macaddr@f100 { + compatible = "mac-base"; + reg = <0xf100 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@ed0000 { + label = "config"; + reg = <0xed0000 0x10000>; + read-only; + }; + + partition@ee0000 { + label = "configbak"; + reg = <0xee0000 0x10000>; + read-only; + }; + + partition@ef0000 { + label = "radio"; + reg = <0xef0000 0x10000>; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_radio_0: eeprom@0 { + reg = <0x0 0x400>; + }; + + eeprom_radio_8000: eeprom@8000 { + reg = <0x8000 0x200>; + }; + }; + }; + + partition@f00000 { + label = "userdata"; + reg = <0xf00000 0x100000>; + read-only; + }; + }; + }; +}; + +&state_default { + gpio { + groups = "i2c", "p0led_an", "p1led_an", "p2led_an", "p3led_an", "p4led_an", "uart1", "wdt"; + function = "gpio"; + }; +}; + +&wmac { + nvmem-cells = <&eeprom_radio_0>, <&macaddr_romfile_f100 0>; + nvmem-cell-names = "eeprom", "mac-address"; + status = "okay"; +}; + +&esw { + mediatek,portmap = <0x37>; + mediatek,portdisable = <0x33>; +}; + +ðernet { + nvmem-cells = <&macaddr_romfile_f100 0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom_radio_8000>, <&macaddr_romfile_f100 (-1)>; + nvmem-cell-names = "eeprom", "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; diff --git a/target/linux/ramips/image/mt76x8.mk b/target/linux/ramips/image/mt76x8.mk index a20446e9d8..31d68236fc 100644 --- a/target/linux/ramips/image/mt76x8.mk +++ b/target/linux/ramips/image/mt76x8.mk @@ -489,6 +489,20 @@ define Device/mercury_mac1200r-v2 endef TARGET_DEVICES += mercury_mac1200r-v2 +define Device/mercusys_mb130-4g-v1 +$(Device/tplink-v2) + IMAGE_SIZE := 14912k + DEVICE_VENDOR := MERCUSYS + DEVICE_MODEL := MB130-4G + DEVICE_VARIANT := v1 + DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-mt7663-firmware-ap kmod-mt7615e \ + kmod-usb-serial-option kmod-usb-net-cdc-ether + TPLINK_FLASHLAYOUT := 16MLmtk + IMAGES := sysupgrade.bin tftp-recovery.bin + IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin) +endef +TARGET_DEVICES += mercusys_mb130-4g-v1 + define Device/minew_g1-c IMAGE_SIZE := 15744k DEVICE_VENDOR := Minew diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds index 79f78a2a45..846835bc57 100644 --- a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds +++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds @@ -96,6 +96,7 @@ tplink,archer-mr200-v6) ucidef_set_led_netdev "lan" "lan" "white:lan" "eth0" ucidef_set_led_netdev "wan" "wan" "white:wan" "wwan0" ;; +mercusys,mb130-4g-v1|\ tplink,re200-v2|\ tplink,re200-v3|\ tplink,re200-v4|\ diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network b/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network index 6e6e1310d3..ca282a9eb1 100644 --- a/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network @@ -156,6 +156,11 @@ ramips_setup_interfaces() ucidef_add_switch "switch0" \ "0:lan:1" "1:lan:2" "2:lan:3" "3:lan:4" "4:wan" "6@eth0" ;; + mercusys,mb130-4g-v1) + ucidef_add_switch "switch0" \ + "2:lan" "3:lan" "6@eth0" + ucidef_set_interface_wan "eth1" + ;; netgear,r6020|\ netgear,r6080|\ netgear,r6120|\ diff --git a/target/linux/ramips/patches-6.6/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-6.6/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch index f0d8c80fd5..91746b741c 100644 --- a/target/linux/ramips/patches-6.6/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-6.6/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch @@ -16,7 +16,7 @@ Acked-by: John Crispin --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -895,6 +895,12 @@ config SPI_QCOM_GENI +@@ -904,6 +904,12 @@ config SPI_QCOM_GENI This driver can also be built as a module. If so, the module will be called spi-geni-qcom. @@ -31,7 +31,7 @@ Acked-by: John Crispin depends on (PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST) --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -117,6 +117,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o +@@ -118,6 +118,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o obj-$(CONFIG_SPI_RSPI) += spi-rspi.o diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 6114d47c0a..d63e8b4e48 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -323,6 +323,22 @@ define Device/radxa_rock-3c endef TARGET_DEVICES += radxa_rock-3c +define Device/radxa_rock-4c-plus + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ROCK 4C+ + SOC := rk3399 + BOOT_FLOW := pine64-bin +endef +TARGET_DEVICES += radxa_rock-4c-plus + +define Device/radxa_rock-4se + DEVICE_VENDOR := Radxa + DEVICE_MODEL := ROCK 4SE + SOC := rk3399 + BOOT_FLOW := pine64-bin +endef +TARGET_DEVICES += radxa_rock-4se + define Device/radxa_rock-5a DEVICE_VENDOR := Radxa DEVICE_MODEL := ROCK 5A diff --git a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch index f7758dad7d..19c50c342e 100644 --- a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch +++ b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -209,6 +209,58 @@ Signed-off-by: David Bauer /delete-node/ display-subsystem; gpio-leds { +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +@@ -17,6 +17,10 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; + }; + + chosen { +@@ -44,11 +48,10 @@ + }; + + /* USER_LED2 */ +- led-1 { ++ led_blue: led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -14,6 +14,10 @@ + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; ++ led-boot = &led_blue; ++ led-failsafe = &led_blue; ++ led-running = &led_blue; ++ led-upgrade = &led_blue; + }; + + chosen { +@@ -33,11 +37,10 @@ + pinctrl-0 = <&user_led2>; + + /* USER_LED2 */ +- led-0 { ++ led_blue: led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + }; + --- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts @@ -24,6 +24,11 @@ diff --git a/target/linux/siflower/patches-6.6/017-spi-add-support-for-sf21-qspi.patch b/target/linux/siflower/patches-6.6/017-spi-add-support-for-sf21-qspi.patch index 5337477fbe..858e935fd7 100644 --- a/target/linux/siflower/patches-6.6/017-spi-add-support-for-sf21-qspi.patch +++ b/target/linux/siflower/patches-6.6/017-spi-add-support-for-sf21-qspi.patch @@ -20,7 +20,7 @@ Signed-off-by: Chuanhong Guo --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -940,6 +940,13 @@ config SPI_SIFIVE +@@ -949,6 +949,13 @@ config SPI_SIFIVE help This exposes the SPI controller IP from SiFive. @@ -36,7 +36,7 @@ Signed-off-by: Chuanhong Guo depends on ARCH_MEDIATEK || COMPILE_TEST --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -125,6 +125,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hsp +@@ -126,6 +126,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hsp obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o