d664d74669
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.79 Manually rebased: ramips/patches-6.6/810-uvc-add-iPassion-iP2970-support.patch All other patches automatically rebased. Build system: x86/64 Build-tested: bcm27xx/bcm2712, filogic/glinet_gl-mt6000, filogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Run-tested: bcm27xx/bcm2712, filogic/glinet_gl-mt6000, filogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/18066 Signed-off-by: Nick Hainke <vincent@systemli.org>
75 lines
2.5 KiB
Diff
75 lines
2.5 KiB
Diff
From: Shiji Yang <yangshiji66@outlook.com>
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Date: Wed, 10 Jul 2024 12:18:52 +0800
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Subject: [PATCH] mmc: mtk-sd: initialize the pad and tune registers
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++---
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1 file changed, 23 insertions(+), 3 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -75,8 +75,12 @@
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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#define MSDC_PATCH_BIT2 0xb8
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+#define MSDC_PAD_CTRL0 0xe0
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+#define MSDC_PAD_CTRL1 0xe4
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+#define MSDC_PAD_CTRL2 0xe8
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#define MSDC_PAD_TUNE 0xec
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#define MSDC_PAD_TUNE0 0xf0
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+#define MSDC_PAD_TUNE1 0xf4
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC51_CFG0 0x204
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@@ -402,6 +406,7 @@ struct mtk_mmc_compatible {
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bool enhance_rx;
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bool support_64g;
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bool use_internal_cd;
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+ bool legacy_mt762x; /* for mt7620, mt7621 and mt76x8 */
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};
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struct msdc_tune_para {
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@@ -539,6 +544,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.use_internal_cd = true,
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+ .legacy_mt762x = true,
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};
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static const struct mtk_mmc_compatible mt7622_compat = {
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@@ -1731,9 +1737,11 @@ static void msdc_init_hw(struct msdc_hos
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}
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writel(0, host->base + MSDC_IOCON);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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- writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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- sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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- writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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+ if(!host->dev_comp->legacy_mt762x) {
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+ writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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+ }
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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if (host->dev_comp->stop_clk_fix) {
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@@ -1797,6 +1805,18 @@ static void msdc_init_hw(struct msdc_hos
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MSDC_PAD_TUNE_RXDLYSEL);
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}
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+ if (host->dev_comp->legacy_mt762x) {
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+ /* Set pins drive strength */
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+ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
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+ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
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+ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
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+
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+ /* Set pad delay */
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+ writel(0x84101010, host->base + MSDC_PAD_TUNE);
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+ writel(0x10101010, host->base + MSDC_PAD_TUNE0);
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+ writel(0x10101010, host->base + MSDC_PAD_TUNE1);
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+ }
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+
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if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
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sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
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sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
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