34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
109 lines
4.6 KiB
Diff
109 lines
4.6 KiB
Diff
From: George Moussalem <george.moussalem@outlook.com>
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Date: Fri, 24 Jan 2025 17:18:12 +0400
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Subject: [PATCH] net: phy: qcom: add IPQ5018 initvals and CDT feature
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The Cable Diagnostics Test for IPQ5018 follows the same logic as qca808x.
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However, the IPQ5018 GE PHY has its own threshold values. So let's set the
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CDT thresholds for the IPQ5018 internal GE PHY. While add it, add and set
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thesholds for MSE for signal quality measurement and 8023az for EEE.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/drivers/net/phy/qcom/ipq5018.c
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+++ b/drivers/net/phy/qcom/ipq5018.c
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@@ -17,6 +17,38 @@
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#define IPQ5018_PHY_MMD1_MDAC 0x8100
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#define IPQ5018_PHY_DAC_MASK GENMASK(15,8)
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+#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000
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+#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001
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+#define IPQ5018_PHY_MMD3_AZ_CTRL1 0x8008
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+#define IPQ5018_PHY_MMD3_AZ_CTRL2 0x8009
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3 0x8074
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4 0x8075
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5 0x8076
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6 0x8077
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7 0x8078
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9 0x807a
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13 0x807e
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL14 0x807f
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+
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+#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1
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+#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6
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+#define IPQ5018_PHY_MMD3_AZ_CTRL1_VAL 0x7880
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+#define IPQ5018_PHY_MMD3_AZ_CTRL2_VAL 0xc8
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3_VAL 0xc040
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4_VAL 0xa060
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5_VAL 0xc040
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6_VAL 0xa060
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7_VAL 0xc24c
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9_VAL 0xc060
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+#define IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13_VAL 0xb060
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+#define IPQ5018_PHY_MMD3_NEAR_ECHO_THRESH_VAL 0x90b0
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+
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7,4)
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50
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+
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+#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080
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+
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struct ipq5018_phy {
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int num_clks;
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struct clk_bulk_data *clks;
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@@ -129,6 +161,24 @@ static int ipq5018_soft_reset(struct phy
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static int ipq5018_cable_test_start(struct phy_device *phydev)
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{
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL4_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL5_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL6_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL7_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL9_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13,
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+ IPQ5018_PHY_MMD3_CDT_THRESH_CTRL13_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_CDT_THRESH_CTRL3,
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+ IPQ5018_PHY_MMD3_NEAR_ECHO_THRESH_VAL);
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+
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/* we do all the (time consuming) work later */
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return 0;
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}
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@@ -136,8 +186,30 @@ static int ipq5018_cable_test_start(stru
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static int ipq5018_config_init(struct phy_device *phydev)
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{
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struct ipq5018_phy *priv = phydev->priv;
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+ u16 val = 0;
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int ret;
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+ /* set LDO efuse: first temporarily store ANA_DAC_FILTER value from
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+ debug register as it will be reset once the ANA_LDO_EFUSE register
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+ is written to */
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+ val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER);
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+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE,
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+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK,
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+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
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+ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
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+
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+ /* set 8023AZ CTRL values */
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_AZ_CTRL1,
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+ IPQ5018_PHY_MMD3_AZ_CTRL1_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_MMD3_AZ_CTRL2,
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+ IPQ5018_PHY_MMD3_AZ_CTRL2_VAL);
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+
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+ /* set MSE threshold values */
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+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
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+ IPQ5018_PHY_MMD1_MSE_THRESH1_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2,
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+ IPQ5018_PHY_MMD1_MSE_THRESH2_VAL);
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+
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/* setting mdac in MMD1 */
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if (priv->mdac) {
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ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC,
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