2d6cedab27
https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.92 Removed upstreamed: bcm27xx/patches-6.1/950-0270-net-bcmgenet-Reset-RBUF-on-first-open.patch generic/backport-6.1/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch generic/pending-6.1/681-net-bridge-fix-multicast-to-unicast-with-fraglist-GS.patch generic/pending-6.1/682-net-core-reject-skb_copy-_expand-for-fraglist-GSO-sk.patch generic/pending-6.1/684-net-bridge-fix-corrupted-ethernet-header-on-multicas.patch generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch imx/patches-6.1/002-6.2-phy-freescale-imx8m-pcie-Refine-i.MX8MM-PCIe-PHY-dri.patch All other patches automatically rebased. Signed-off-by: Zxl hhyccc <zxlhhy@gmail.com>
50 lines
1.9 KiB
Diff
50 lines
1.9 KiB
Diff
From ffcbb4ccd357eeb649036e379a34bf5fb8d4f47c Mon Sep 17 00:00:00 2001
|
|
From: Richard Zhu <hongxing.zhu@nxp.com>
|
|
Date: Thu, 13 Oct 2022 09:47:00 +0800
|
|
Subject: [PATCH 1/3] phy: freescale: imx8m-pcie: Refine register definitions
|
|
|
|
No function changes, refine PHY register definitions.
|
|
- Keep align with other CMN PHY registers, refine the definitions of
|
|
PHY_CMN_REG75.
|
|
- Remove two BIT definitions that are not used at all.
|
|
|
|
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
|
|
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
|
|
Tested-by: Marek Vasut <marex@denx.de>
|
|
Tested-by: Richard Leitner <richard.leitner@skidata.com>
|
|
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
|
|
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
|
|
---
|
|
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 11 ++++-------
|
|
1 file changed, 4 insertions(+), 7 deletions(-)
|
|
|
|
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
|
|
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
|
|
@@ -32,12 +32,10 @@
|
|
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
|
|
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
|
|
#define ANA_AUX_TX_LVL GENMASK(3, 0)
|
|
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
|
|
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
|
|
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
|
|
+#define ANA_PLL_DONE 0x3
|
|
#define PCIE_PHY_TRSV_REG5 0x414
|
|
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
|
|
#define PCIE_PHY_TRSV_REG6 0x418
|
|
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
|
|
|
|
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
|
|
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
|
|
@@ -152,9 +150,8 @@ static int imx8_pcie_phy_power_on(struct
|
|
}
|
|
|
|
/* Polling to check the phy is ready or not. */
|
|
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
|
|
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
|
|
- 10, 20000);
|
|
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
|
|
+ val, val == ANA_PLL_DONE, 10, 20000);
|
|
return ret;
|
|
}
|
|
|